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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 by Ralf Baechle
7 * Copyright (C) 2009, 2012 Cavium, Inc.
8 */
9#include <linux/clocksource.h>
10#include <linux/export.h>
11#include <linux/init.h>
12#include <linux/smp.h>
13
14#include <asm/cpu-info.h>
15#include <asm/cpu-type.h>
16#include <asm/time.h>
17
18#include <asm/octeon/octeon.h>
19#include <asm/octeon/cvmx-ipd-defs.h>
20#include <asm/octeon/cvmx-mio-defs.h>
21
22
23static u64 f;
24static u64 rdiv;
25static u64 sdiv;
26static u64 octeon_udelay_factor;
27static u64 octeon_ndelay_factor;
28
29void __init octeon_setup_delays(void)
30{
31 octeon_udelay_factor = octeon_get_clock_rate() / 1000000;
32 /*
33 * For __ndelay we divide by 2^16, so the factor is multiplied
34 * by the same amount.
35 */
36 octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull;
37
38 preset_lpj = octeon_get_clock_rate() / HZ;
39
40 if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
41 union cvmx_mio_rst_boot rst_boot;
42 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
43 rdiv = rst_boot.s.c_mul; /* CPU clock */
44 sdiv = rst_boot.s.pnr_mul; /* I/O clock */
45 f = (0x8000000000000000ull / sdiv) * 2;
46 }
47}
48
49/*
50 * Set the current core's cvmcount counter to the value of the
51 * IPD_CLK_COUNT. We do this on all cores as they are brought
52 * on-line. This allows for a read from a local cpu register to
53 * access a synchronized counter.
54 *
55 * On CPU_CAVIUM_OCTEON2 the IPD_CLK_COUNT is scaled by rdiv/sdiv.
56 */
57void octeon_init_cvmcount(void)
58{
59 unsigned long flags;
60 unsigned loops = 2;
61
62 /* Clobber loops so GCC will not unroll the following while loop. */
63 asm("" : "+r" (loops));
64
65 local_irq_save(flags);
66 /*
67 * Loop several times so we are executing from the cache,
68 * which should give more deterministic timing.
69 */
70 while (loops--) {
71 u64 ipd_clk_count = cvmx_read_csr(CVMX_IPD_CLK_COUNT);
72 if (rdiv != 0) {
73 ipd_clk_count *= rdiv;
74 if (f != 0) {
75 asm("dmultu\t%[cnt],%[f]\n\t"
76 "mfhi\t%[cnt]"
77 : [cnt] "+r" (ipd_clk_count)
78 : [f] "r" (f)
79 : "hi", "lo");
80 }
81 }
82 write_c0_cvmcount(ipd_clk_count);
83 }
84 local_irq_restore(flags);
85}
86
87static cycle_t octeon_cvmcount_read(struct clocksource *cs)
88{
89 return read_c0_cvmcount();
90}
91
92static struct clocksource clocksource_mips = {
93 .name = "OCTEON_CVMCOUNT",
94 .read = octeon_cvmcount_read,
95 .mask = CLOCKSOURCE_MASK(64),
96 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
97};
98
99unsigned long long notrace sched_clock(void)
100{
101 /* 64-bit arithmatic can overflow, so use 128-bit. */
102 u64 t1, t2, t3;
103 unsigned long long rv;
104 u64 mult = clocksource_mips.mult;
105 u64 shift = clocksource_mips.shift;
106 u64 cnt = read_c0_cvmcount();
107
108 asm (
109 "dmultu\t%[cnt],%[mult]\n\t"
110 "nor\t%[t1],$0,%[shift]\n\t"
111 "mfhi\t%[t2]\n\t"
112 "mflo\t%[t3]\n\t"
113 "dsll\t%[t2],%[t2],1\n\t"
114 "dsrlv\t%[rv],%[t3],%[shift]\n\t"
115 "dsllv\t%[t1],%[t2],%[t1]\n\t"
116 "or\t%[rv],%[t1],%[rv]\n\t"
117 : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3)
118 : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
119 : "hi", "lo");
120 return rv;
121}
122
123void __init plat_time_init(void)
124{
125 clocksource_mips.rating = 300;
126 clocksource_register_hz(&clocksource_mips, octeon_get_clock_rate());
127}
128
129void __udelay(unsigned long us)
130{
131 u64 cur, end, inc;
132
133 cur = read_c0_cvmcount();
134
135 inc = us * octeon_udelay_factor;
136 end = cur + inc;
137
138 while (end > cur)
139 cur = read_c0_cvmcount();
140}
141EXPORT_SYMBOL(__udelay);
142
143void __ndelay(unsigned long ns)
144{
145 u64 cur, end, inc;
146
147 cur = read_c0_cvmcount();
148
149 inc = ((ns * octeon_ndelay_factor) >> 16);
150 end = cur + inc;
151
152 while (end > cur)
153 cur = read_c0_cvmcount();
154}
155EXPORT_SYMBOL(__ndelay);
156
157void __delay(unsigned long loops)
158{
159 u64 cur, end;
160
161 cur = read_c0_cvmcount();
162 end = cur + loops;
163
164 while (end > cur)
165 cur = read_c0_cvmcount();
166}
167EXPORT_SYMBOL(__delay);
168
169
170/**
171 * octeon_io_clk_delay - wait for a given number of io clock cycles to pass.
172 *
173 * We scale the wait by the clock ratio, and then wait for the
174 * corresponding number of core clocks.
175 *
176 * @count: The number of clocks to wait.
177 */
178void octeon_io_clk_delay(unsigned long count)
179{
180 u64 cur, end;
181
182 cur = read_c0_cvmcount();
183 if (rdiv != 0) {
184 end = count * rdiv;
185 if (f != 0) {
186 asm("dmultu\t%[cnt],%[f]\n\t"
187 "mfhi\t%[cnt]"
188 : [cnt] "+r" (end)
189 : [f] "r" (f)
190 : "hi", "lo");
191 }
192 end = cur + end;
193 } else {
194 end = cur + count;
195 }
196 while (end > cur)
197 cur = read_c0_cvmcount();
198}
199EXPORT_SYMBOL(octeon_io_clk_delay);
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 by Ralf Baechle
7 * Copyright (C) 2009, 2010 Cavium Networks, Inc.
8 */
9#include <linux/clocksource.h>
10#include <linux/init.h>
11#include <linux/smp.h>
12
13#include <asm/cpu-info.h>
14#include <asm/time.h>
15
16#include <asm/octeon/octeon.h>
17#include <asm/octeon/cvmx-ipd-defs.h>
18#include <asm/octeon/cvmx-mio-defs.h>
19
20/*
21 * Set the current core's cvmcount counter to the value of the
22 * IPD_CLK_COUNT. We do this on all cores as they are brought
23 * on-line. This allows for a read from a local cpu register to
24 * access a synchronized counter.
25 *
26 * On CPU_CAVIUM_OCTEON2 the IPD_CLK_COUNT is scaled by rdiv/sdiv.
27 */
28void octeon_init_cvmcount(void)
29{
30 unsigned long flags;
31 unsigned loops = 2;
32 u64 f = 0;
33 u64 rdiv = 0;
34 u64 sdiv = 0;
35 if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
36 union cvmx_mio_rst_boot rst_boot;
37 rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
38 rdiv = rst_boot.s.c_mul; /* CPU clock */
39 sdiv = rst_boot.s.pnr_mul; /* I/O clock */
40 f = (0x8000000000000000ull / sdiv) * 2;
41 }
42
43
44 /* Clobber loops so GCC will not unroll the following while loop. */
45 asm("" : "+r" (loops));
46
47 local_irq_save(flags);
48 /*
49 * Loop several times so we are executing from the cache,
50 * which should give more deterministic timing.
51 */
52 while (loops--) {
53 u64 ipd_clk_count = cvmx_read_csr(CVMX_IPD_CLK_COUNT);
54 if (rdiv != 0) {
55 ipd_clk_count *= rdiv;
56 if (f != 0) {
57 asm("dmultu\t%[cnt],%[f]\n\t"
58 "mfhi\t%[cnt]"
59 : [cnt] "+r" (ipd_clk_count),
60 [f] "=r" (f)
61 : : "hi", "lo");
62 }
63 }
64 write_c0_cvmcount(ipd_clk_count);
65 }
66 local_irq_restore(flags);
67}
68
69static cycle_t octeon_cvmcount_read(struct clocksource *cs)
70{
71 return read_c0_cvmcount();
72}
73
74static struct clocksource clocksource_mips = {
75 .name = "OCTEON_CVMCOUNT",
76 .read = octeon_cvmcount_read,
77 .mask = CLOCKSOURCE_MASK(64),
78 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
79};
80
81unsigned long long notrace sched_clock(void)
82{
83 /* 64-bit arithmatic can overflow, so use 128-bit. */
84 u64 t1, t2, t3;
85 unsigned long long rv;
86 u64 mult = clocksource_mips.mult;
87 u64 shift = clocksource_mips.shift;
88 u64 cnt = read_c0_cvmcount();
89
90 asm (
91 "dmultu\t%[cnt],%[mult]\n\t"
92 "nor\t%[t1],$0,%[shift]\n\t"
93 "mfhi\t%[t2]\n\t"
94 "mflo\t%[t3]\n\t"
95 "dsll\t%[t2],%[t2],1\n\t"
96 "dsrlv\t%[rv],%[t3],%[shift]\n\t"
97 "dsllv\t%[t1],%[t2],%[t1]\n\t"
98 "or\t%[rv],%[t1],%[rv]\n\t"
99 : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3)
100 : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
101 : "hi", "lo");
102 return rv;
103}
104
105void __init plat_time_init(void)
106{
107 clocksource_mips.rating = 300;
108 clocksource_register_hz(&clocksource_mips, octeon_get_clock_rate());
109}
110
111static u64 octeon_udelay_factor;
112static u64 octeon_ndelay_factor;
113
114void __init octeon_setup_delays(void)
115{
116 octeon_udelay_factor = octeon_get_clock_rate() / 1000000;
117 /*
118 * For __ndelay we divide by 2^16, so the factor is multiplied
119 * by the same amount.
120 */
121 octeon_ndelay_factor = (octeon_udelay_factor * 0x10000ull) / 1000ull;
122
123 preset_lpj = octeon_get_clock_rate() / HZ;
124}
125
126void __udelay(unsigned long us)
127{
128 u64 cur, end, inc;
129
130 cur = read_c0_cvmcount();
131
132 inc = us * octeon_udelay_factor;
133 end = cur + inc;
134
135 while (end > cur)
136 cur = read_c0_cvmcount();
137}
138EXPORT_SYMBOL(__udelay);
139
140void __ndelay(unsigned long ns)
141{
142 u64 cur, end, inc;
143
144 cur = read_c0_cvmcount();
145
146 inc = ((ns * octeon_ndelay_factor) >> 16);
147 end = cur + inc;
148
149 while (end > cur)
150 cur = read_c0_cvmcount();
151}
152EXPORT_SYMBOL(__ndelay);
153
154void __delay(unsigned long loops)
155{
156 u64 cur, end;
157
158 cur = read_c0_cvmcount();
159 end = cur + loops;
160
161 while (end > cur)
162 cur = read_c0_cvmcount();
163}
164EXPORT_SYMBOL(__delay);