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1/*
2 * linux/arch/arm/include/asm/pmu.h
3 *
4 * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#ifndef __ARM_PMU_H__
13#define __ARM_PMU_H__
14
15#include <linux/interrupt.h>
16#include <linux/perf_event.h>
17
18/*
19 * struct arm_pmu_platdata - ARM PMU platform data
20 *
21 * @handle_irq: an optional handler which will be called from the
22 * interrupt and passed the address of the low level handler,
23 * and can be used to implement any platform specific handling
24 * before or after calling it.
25 * @runtime_resume: an optional handler which will be called by the
26 * runtime PM framework following a call to pm_runtime_get().
27 * Note that if pm_runtime_get() is called more than once in
28 * succession this handler will only be called once.
29 * @runtime_suspend: an optional handler which will be called by the
30 * runtime PM framework following a call to pm_runtime_put().
31 * Note that if pm_runtime_get() is called more than once in
32 * succession this handler will only be called following the
33 * final call to pm_runtime_put() that actually disables the
34 * hardware.
35 */
36struct arm_pmu_platdata {
37 irqreturn_t (*handle_irq)(int irq, void *dev,
38 irq_handler_t pmu_handler);
39 int (*runtime_resume)(struct device *dev);
40 int (*runtime_suspend)(struct device *dev);
41};
42
43#ifdef CONFIG_HW_PERF_EVENTS
44
45/* The events for a given PMU register set. */
46struct pmu_hw_events {
47 /*
48 * The events that are active on the PMU for the given index.
49 */
50 struct perf_event **events;
51
52 /*
53 * A 1 bit for an index indicates that the counter is being used for
54 * an event. A 0 means that the counter can be used.
55 */
56 unsigned long *used_mask;
57
58 /*
59 * Hardware lock to serialize accesses to PMU registers. Needed for the
60 * read/modify/write sequences.
61 */
62 raw_spinlock_t pmu_lock;
63};
64
65struct arm_pmu {
66 struct pmu pmu;
67 cpumask_t active_irqs;
68 char *name;
69 irqreturn_t (*handle_irq)(int irq_num, void *dev);
70 void (*enable)(struct perf_event *event);
71 void (*disable)(struct perf_event *event);
72 int (*get_event_idx)(struct pmu_hw_events *hw_events,
73 struct perf_event *event);
74 void (*clear_event_idx)(struct pmu_hw_events *hw_events,
75 struct perf_event *event);
76 int (*set_event_filter)(struct hw_perf_event *evt,
77 struct perf_event_attr *attr);
78 u32 (*read_counter)(struct perf_event *event);
79 void (*write_counter)(struct perf_event *event, u32 val);
80 void (*start)(struct arm_pmu *);
81 void (*stop)(struct arm_pmu *);
82 void (*reset)(void *);
83 int (*request_irq)(struct arm_pmu *, irq_handler_t handler);
84 void (*free_irq)(struct arm_pmu *);
85 int (*map_event)(struct perf_event *event);
86 int num_events;
87 atomic_t active_events;
88 struct mutex reserve_mutex;
89 u64 max_period;
90 struct platform_device *plat_device;
91 struct pmu_hw_events *(*get_hw_events)(void);
92};
93
94#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
95
96extern const struct dev_pm_ops armpmu_dev_pm_ops;
97
98int armpmu_register(struct arm_pmu *armpmu, int type);
99
100u64 armpmu_event_update(struct perf_event *event);
101
102int armpmu_event_set_period(struct perf_event *event);
103
104int armpmu_map_event(struct perf_event *event,
105 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
106 const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
107 [PERF_COUNT_HW_CACHE_OP_MAX]
108 [PERF_COUNT_HW_CACHE_RESULT_MAX],
109 u32 raw_event_mask);
110
111#endif /* CONFIG_HW_PERF_EVENTS */
112
113#endif /* __ARM_PMU_H__ */
1/*
2 * linux/arch/arm/include/asm/pmu.h
3 *
4 * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#ifndef __ARM_PMU_H__
13#define __ARM_PMU_H__
14
15#include <linux/interrupt.h>
16
17enum arm_pmu_type {
18 ARM_PMU_DEVICE_CPU = 0,
19 ARM_NUM_PMU_DEVICES,
20};
21
22/*
23 * struct arm_pmu_platdata - ARM PMU platform data
24 *
25 * @handle_irq: an optional handler which will be called from the interrupt and
26 * passed the address of the low level handler, and can be used to implement
27 * any platform specific handling before or after calling it.
28 */
29struct arm_pmu_platdata {
30 irqreturn_t (*handle_irq)(int irq, void *dev,
31 irq_handler_t pmu_handler);
32};
33
34#ifdef CONFIG_CPU_HAS_PMU
35
36/**
37 * reserve_pmu() - reserve the hardware performance counters
38 *
39 * Reserve the hardware performance counters in the system for exclusive use.
40 * The platform_device for the system is returned on success, ERR_PTR()
41 * encoded error on failure.
42 */
43extern struct platform_device *
44reserve_pmu(enum arm_pmu_type type);
45
46/**
47 * release_pmu() - Relinquish control of the performance counters
48 *
49 * Release the performance counters and allow someone else to use them.
50 * Callers must have disabled the counters and released IRQs before calling
51 * this. The platform_device returned from reserve_pmu() must be passed as
52 * a cookie.
53 */
54extern int
55release_pmu(enum arm_pmu_type type);
56
57/**
58 * init_pmu() - Initialise the PMU.
59 *
60 * Initialise the system ready for PMU enabling. This should typically set the
61 * IRQ affinity and nothing else. The users (oprofile/perf events etc) will do
62 * the actual hardware initialisation.
63 */
64extern int
65init_pmu(enum arm_pmu_type type);
66
67#else /* CONFIG_CPU_HAS_PMU */
68
69#include <linux/err.h>
70
71static inline struct platform_device *
72reserve_pmu(enum arm_pmu_type type)
73{
74 return ERR_PTR(-ENODEV);
75}
76
77static inline int
78release_pmu(enum arm_pmu_type type)
79{
80 return -ENODEV;
81}
82
83static inline int
84init_pmu(enum arm_pmu_type type)
85{
86 return -ENODEV;
87}
88
89#endif /* CONFIG_CPU_HAS_PMU */
90
91#endif /* __ARM_PMU_H__ */