1/*
 2 *  linux/arch/arm/include/asm/perf_event.h
 3 *
 4 *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
 5 *
 6 * This program is free software; you can redistribute it and/or modify
 7 * it under the terms of the GNU General Public License version 2 as
 8 * published by the Free Software Foundation.
 9 *
10 */
11
12#ifndef __ARM_PERF_EVENT_H__
13#define __ARM_PERF_EVENT_H__
14
15/*
16 * The ARMv7 CPU PMU supports up to 32 event counters.
17 */
18#define ARMPMU_MAX_HWEVENTS		32
19
20#define HW_OP_UNSUPPORTED		0xFFFF
21#define C(_x)				PERF_COUNT_HW_CACHE_##_x
22#define CACHE_OP_UNSUPPORTED		0xFFFF
 
 
 
 
 
 
 
 
 
23
24#ifdef CONFIG_HW_PERF_EVENTS
25struct pt_regs;
26extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
27extern unsigned long perf_misc_flags(struct pt_regs *regs);
28#define perf_misc_flags(regs)	perf_misc_flags(regs)
29#endif
30
31#endif /* __ARM_PERF_EVENT_H__ */

 1/*
 2 *  linux/arch/arm/include/asm/perf_event.h
 3 *
 4 *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
 5 *
 6 * This program is free software; you can redistribute it and/or modify
 7 * it under the terms of the GNU General Public License version 2 as
 8 * published by the Free Software Foundation.
 9 *
10 */
11
12#ifndef __ARM_PERF_EVENT_H__
13#define __ARM_PERF_EVENT_H__
14
15/* ARM performance counters start from 1 (in the cp15 accesses) so use the
16 * same indexes here for consistency. */
17#define PERF_EVENT_INDEX_OFFSET 1
 
18
19/* ARM perf PMU IDs for use by internal perf clients. */
20enum arm_perf_pmu_ids {
21	ARM_PERF_PMU_ID_XSCALE1	= 0,
22	ARM_PERF_PMU_ID_XSCALE2,
23	ARM_PERF_PMU_ID_V6,
24	ARM_PERF_PMU_ID_V6MP,
25	ARM_PERF_PMU_ID_CA8,
26	ARM_PERF_PMU_ID_CA9,
27	ARM_PERF_PMU_ID_CA5,
28	ARM_PERF_PMU_ID_CA15,
29	ARM_NUM_PMU_IDS,
30};
31
32extern enum arm_perf_pmu_ids
33armpmu_get_pmu_id(void);
34
35extern int
36armpmu_get_max_events(void);
 
37
38#endif /* __ARM_PERF_EVENT_H__ */