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1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009-12 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23#include <linux/regulator/consumer.h>
24#include <linux/slab.h>
25#include <sound/core.h>
26#include <sound/jack.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/initval.h>
31#include <sound/tlv.h>
32#include <trace/events/asoc.h>
33
34#include <linux/mfd/wm8994/core.h>
35#include <linux/mfd/wm8994/registers.h>
36#include <linux/mfd/wm8994/pdata.h>
37#include <linux/mfd/wm8994/gpio.h>
38
39#include "wm8994.h"
40#include "wm_hubs.h"
41
42#define WM1811_JACKDET_MODE_NONE 0x0000
43#define WM1811_JACKDET_MODE_JACK 0x0100
44#define WM1811_JACKDET_MODE_MIC 0x0080
45#define WM1811_JACKDET_MODE_AUDIO 0x0180
46
47#define WM8994_NUM_DRC 3
48#define WM8994_NUM_EQ 3
49
50static struct {
51 unsigned int reg;
52 unsigned int mask;
53} wm8994_vu_bits[] = {
54 { WM8994_LEFT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
55 { WM8994_RIGHT_LINE_INPUT_1_2_VOLUME, WM8994_IN1_VU },
56 { WM8994_LEFT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
57 { WM8994_RIGHT_LINE_INPUT_3_4_VOLUME, WM8994_IN2_VU },
58 { WM8994_SPEAKER_VOLUME_LEFT, WM8994_SPKOUT_VU },
59 { WM8994_SPEAKER_VOLUME_RIGHT, WM8994_SPKOUT_VU },
60 { WM8994_LEFT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
61 { WM8994_RIGHT_OUTPUT_VOLUME, WM8994_HPOUT1_VU },
62 { WM8994_LEFT_OPGA_VOLUME, WM8994_MIXOUT_VU },
63 { WM8994_RIGHT_OPGA_VOLUME, WM8994_MIXOUT_VU },
64
65 { WM8994_AIF1_DAC1_LEFT_VOLUME, WM8994_AIF1DAC1_VU },
66 { WM8994_AIF1_DAC1_RIGHT_VOLUME, WM8994_AIF1DAC1_VU },
67 { WM8994_AIF1_DAC2_LEFT_VOLUME, WM8994_AIF1DAC2_VU },
68 { WM8994_AIF1_DAC2_RIGHT_VOLUME, WM8994_AIF1DAC2_VU },
69 { WM8994_AIF2_DAC_LEFT_VOLUME, WM8994_AIF2DAC_VU },
70 { WM8994_AIF2_DAC_RIGHT_VOLUME, WM8994_AIF2DAC_VU },
71 { WM8994_AIF1_ADC1_LEFT_VOLUME, WM8994_AIF1ADC1_VU },
72 { WM8994_AIF1_ADC1_RIGHT_VOLUME, WM8994_AIF1ADC1_VU },
73 { WM8994_AIF1_ADC2_LEFT_VOLUME, WM8994_AIF1ADC2_VU },
74 { WM8994_AIF1_ADC2_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
75 { WM8994_AIF2_ADC_LEFT_VOLUME, WM8994_AIF2ADC_VU },
76 { WM8994_AIF2_ADC_RIGHT_VOLUME, WM8994_AIF1ADC2_VU },
77 { WM8994_DAC1_LEFT_VOLUME, WM8994_DAC1_VU },
78 { WM8994_DAC1_RIGHT_VOLUME, WM8994_DAC1_VU },
79 { WM8994_DAC2_LEFT_VOLUME, WM8994_DAC2_VU },
80 { WM8994_DAC2_RIGHT_VOLUME, WM8994_DAC2_VU },
81};
82
83static int wm8994_drc_base[] = {
84 WM8994_AIF1_DRC1_1,
85 WM8994_AIF1_DRC2_1,
86 WM8994_AIF2_DRC_1,
87};
88
89static int wm8994_retune_mobile_base[] = {
90 WM8994_AIF1_DAC1_EQ_GAINS_1,
91 WM8994_AIF1_DAC2_EQ_GAINS_1,
92 WM8994_AIF2_EQ_GAINS_1,
93};
94
95static const struct wm8958_micd_rate micdet_rates[] = {
96 { 32768, true, 1, 4 },
97 { 32768, false, 1, 1 },
98 { 44100 * 256, true, 7, 10 },
99 { 44100 * 256, false, 7, 10 },
100};
101
102static const struct wm8958_micd_rate jackdet_rates[] = {
103 { 32768, true, 0, 1 },
104 { 32768, false, 0, 1 },
105 { 44100 * 256, true, 10, 10 },
106 { 44100 * 256, false, 7, 8 },
107};
108
109static void wm8958_micd_set_rate(struct snd_soc_codec *codec)
110{
111 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
112 struct wm8994 *control = wm8994->wm8994;
113 int best, i, sysclk, val;
114 bool idle;
115 const struct wm8958_micd_rate *rates;
116 int num_rates;
117
118 idle = !wm8994->jack_mic;
119
120 sysclk = snd_soc_read(codec, WM8994_CLOCKING_1);
121 if (sysclk & WM8994_SYSCLK_SRC)
122 sysclk = wm8994->aifclk[1];
123 else
124 sysclk = wm8994->aifclk[0];
125
126 if (control->pdata.micd_rates) {
127 rates = control->pdata.micd_rates;
128 num_rates = control->pdata.num_micd_rates;
129 } else if (wm8994->jackdet) {
130 rates = jackdet_rates;
131 num_rates = ARRAY_SIZE(jackdet_rates);
132 } else {
133 rates = micdet_rates;
134 num_rates = ARRAY_SIZE(micdet_rates);
135 }
136
137 best = 0;
138 for (i = 0; i < num_rates; i++) {
139 if (rates[i].idle != idle)
140 continue;
141 if (abs(rates[i].sysclk - sysclk) <
142 abs(rates[best].sysclk - sysclk))
143 best = i;
144 else if (rates[best].idle != idle)
145 best = i;
146 }
147
148 val = rates[best].start << WM8958_MICD_BIAS_STARTTIME_SHIFT
149 | rates[best].rate << WM8958_MICD_RATE_SHIFT;
150
151 dev_dbg(codec->dev, "MICD rate %d,%d for %dHz %s\n",
152 rates[best].start, rates[best].rate, sysclk,
153 idle ? "idle" : "active");
154
155 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
156 WM8958_MICD_BIAS_STARTTIME_MASK |
157 WM8958_MICD_RATE_MASK, val);
158}
159
160static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
161{
162 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
163 int rate;
164 int reg1 = 0;
165 int offset;
166
167 if (aif)
168 offset = 4;
169 else
170 offset = 0;
171
172 switch (wm8994->sysclk[aif]) {
173 case WM8994_SYSCLK_MCLK1:
174 rate = wm8994->mclk[0];
175 break;
176
177 case WM8994_SYSCLK_MCLK2:
178 reg1 |= 0x8;
179 rate = wm8994->mclk[1];
180 break;
181
182 case WM8994_SYSCLK_FLL1:
183 reg1 |= 0x10;
184 rate = wm8994->fll[0].out;
185 break;
186
187 case WM8994_SYSCLK_FLL2:
188 reg1 |= 0x18;
189 rate = wm8994->fll[1].out;
190 break;
191
192 default:
193 return -EINVAL;
194 }
195
196 if (rate >= 13500000) {
197 rate /= 2;
198 reg1 |= WM8994_AIF1CLK_DIV;
199
200 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
201 aif + 1, rate);
202 }
203
204 wm8994->aifclk[aif] = rate;
205
206 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
207 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
208 reg1);
209
210 return 0;
211}
212
213static int configure_clock(struct snd_soc_codec *codec)
214{
215 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
216 int change, new;
217
218 /* Bring up the AIF clocks first */
219 configure_aif_clock(codec, 0);
220 configure_aif_clock(codec, 1);
221
222 /* Then switch CLK_SYS over to the higher of them; a change
223 * can only happen as a result of a clocking change which can
224 * only be made outside of DAPM so we can safely redo the
225 * clocking.
226 */
227
228 /* If they're equal it doesn't matter which is used */
229 if (wm8994->aifclk[0] == wm8994->aifclk[1]) {
230 wm8958_micd_set_rate(codec);
231 return 0;
232 }
233
234 if (wm8994->aifclk[0] < wm8994->aifclk[1])
235 new = WM8994_SYSCLK_SRC;
236 else
237 new = 0;
238
239 change = snd_soc_update_bits(codec, WM8994_CLOCKING_1,
240 WM8994_SYSCLK_SRC, new);
241 if (change)
242 snd_soc_dapm_sync(&codec->dapm);
243
244 wm8958_micd_set_rate(codec);
245
246 return 0;
247}
248
249static int check_clk_sys(struct snd_soc_dapm_widget *source,
250 struct snd_soc_dapm_widget *sink)
251{
252 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
253 const char *clk;
254
255 /* Check what we're currently using for CLK_SYS */
256 if (reg & WM8994_SYSCLK_SRC)
257 clk = "AIF2CLK";
258 else
259 clk = "AIF1CLK";
260
261 return strcmp(source->name, clk) == 0;
262}
263
264static const char *sidetone_hpf_text[] = {
265 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
266};
267
268static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
269 WM8994_SIDETONE, 7, sidetone_hpf_text);
270
271static const char *adc_hpf_text[] = {
272 "HiFi", "Voice 1", "Voice 2", "Voice 3"
273};
274
275static SOC_ENUM_SINGLE_DECL(aif1adc1_hpf,
276 WM8994_AIF1_ADC1_FILTERS, 13, adc_hpf_text);
277
278static SOC_ENUM_SINGLE_DECL(aif1adc2_hpf,
279 WM8994_AIF1_ADC2_FILTERS, 13, adc_hpf_text);
280
281static SOC_ENUM_SINGLE_DECL(aif2adc_hpf,
282 WM8994_AIF2_ADC_FILTERS, 13, adc_hpf_text);
283
284static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
285static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
286static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
287static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
288static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
289static const DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
290static const DECLARE_TLV_DB_SCALE(mixin_boost_tlv, 0, 900, 0);
291
292#define WM8994_DRC_SWITCH(xname, reg, shift) \
293 SOC_SINGLE_EXT(xname, reg, shift, 1, 0, \
294 snd_soc_get_volsw, wm8994_put_drc_sw)
295
296static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
297 struct snd_ctl_elem_value *ucontrol)
298{
299 struct soc_mixer_control *mc =
300 (struct soc_mixer_control *)kcontrol->private_value;
301 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
302 int mask, ret;
303
304 /* Can't enable both ADC and DAC paths simultaneously */
305 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
306 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
307 WM8994_AIF1ADC1R_DRC_ENA_MASK;
308 else
309 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
310
311 ret = snd_soc_read(codec, mc->reg);
312 if (ret < 0)
313 return ret;
314 if (ret & mask)
315 return -EINVAL;
316
317 return snd_soc_put_volsw(kcontrol, ucontrol);
318}
319
320static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
321{
322 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
323 struct wm8994 *control = wm8994->wm8994;
324 struct wm8994_pdata *pdata = &control->pdata;
325 int base = wm8994_drc_base[drc];
326 int cfg = wm8994->drc_cfg[drc];
327 int save, i;
328
329 /* Save any enables; the configuration should clear them. */
330 save = snd_soc_read(codec, base);
331 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
332 WM8994_AIF1ADC1R_DRC_ENA;
333
334 for (i = 0; i < WM8994_DRC_REGS; i++)
335 snd_soc_update_bits(codec, base + i, 0xffff,
336 pdata->drc_cfgs[cfg].regs[i]);
337
338 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
339 WM8994_AIF1ADC1L_DRC_ENA |
340 WM8994_AIF1ADC1R_DRC_ENA, save);
341}
342
343/* Icky as hell but saves code duplication */
344static int wm8994_get_drc(const char *name)
345{
346 if (strcmp(name, "AIF1DRC1 Mode") == 0)
347 return 0;
348 if (strcmp(name, "AIF1DRC2 Mode") == 0)
349 return 1;
350 if (strcmp(name, "AIF2DRC Mode") == 0)
351 return 2;
352 return -EINVAL;
353}
354
355static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
356 struct snd_ctl_elem_value *ucontrol)
357{
358 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
359 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
360 struct wm8994 *control = wm8994->wm8994;
361 struct wm8994_pdata *pdata = &control->pdata;
362 int drc = wm8994_get_drc(kcontrol->id.name);
363 int value = ucontrol->value.integer.value[0];
364
365 if (drc < 0)
366 return drc;
367
368 if (value >= pdata->num_drc_cfgs)
369 return -EINVAL;
370
371 wm8994->drc_cfg[drc] = value;
372
373 wm8994_set_drc(codec, drc);
374
375 return 0;
376}
377
378static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
379 struct snd_ctl_elem_value *ucontrol)
380{
381 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
382 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
383 int drc = wm8994_get_drc(kcontrol->id.name);
384
385 if (drc < 0)
386 return drc;
387 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
388
389 return 0;
390}
391
392static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
393{
394 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
395 struct wm8994 *control = wm8994->wm8994;
396 struct wm8994_pdata *pdata = &control->pdata;
397 int base = wm8994_retune_mobile_base[block];
398 int iface, best, best_val, save, i, cfg;
399
400 if (!pdata || !wm8994->num_retune_mobile_texts)
401 return;
402
403 switch (block) {
404 case 0:
405 case 1:
406 iface = 0;
407 break;
408 case 2:
409 iface = 1;
410 break;
411 default:
412 return;
413 }
414
415 /* Find the version of the currently selected configuration
416 * with the nearest sample rate. */
417 cfg = wm8994->retune_mobile_cfg[block];
418 best = 0;
419 best_val = INT_MAX;
420 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
421 if (strcmp(pdata->retune_mobile_cfgs[i].name,
422 wm8994->retune_mobile_texts[cfg]) == 0 &&
423 abs(pdata->retune_mobile_cfgs[i].rate
424 - wm8994->dac_rates[iface]) < best_val) {
425 best = i;
426 best_val = abs(pdata->retune_mobile_cfgs[i].rate
427 - wm8994->dac_rates[iface]);
428 }
429 }
430
431 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
432 block,
433 pdata->retune_mobile_cfgs[best].name,
434 pdata->retune_mobile_cfgs[best].rate,
435 wm8994->dac_rates[iface]);
436
437 /* The EQ will be disabled while reconfiguring it, remember the
438 * current configuration.
439 */
440 save = snd_soc_read(codec, base);
441 save &= WM8994_AIF1DAC1_EQ_ENA;
442
443 for (i = 0; i < WM8994_EQ_REGS; i++)
444 snd_soc_update_bits(codec, base + i, 0xffff,
445 pdata->retune_mobile_cfgs[best].regs[i]);
446
447 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
448}
449
450/* Icky as hell but saves code duplication */
451static int wm8994_get_retune_mobile_block(const char *name)
452{
453 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
454 return 0;
455 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
456 return 1;
457 if (strcmp(name, "AIF2 EQ Mode") == 0)
458 return 2;
459 return -EINVAL;
460}
461
462static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
463 struct snd_ctl_elem_value *ucontrol)
464{
465 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
466 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
467 struct wm8994 *control = wm8994->wm8994;
468 struct wm8994_pdata *pdata = &control->pdata;
469 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
470 int value = ucontrol->value.integer.value[0];
471
472 if (block < 0)
473 return block;
474
475 if (value >= pdata->num_retune_mobile_cfgs)
476 return -EINVAL;
477
478 wm8994->retune_mobile_cfg[block] = value;
479
480 wm8994_set_retune_mobile(codec, block);
481
482 return 0;
483}
484
485static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
487{
488 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
489 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
490 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
491
492 if (block < 0)
493 return block;
494
495 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
496
497 return 0;
498}
499
500static const char *aif_chan_src_text[] = {
501 "Left", "Right"
502};
503
504static SOC_ENUM_SINGLE_DECL(aif1adcl_src,
505 WM8994_AIF1_CONTROL_1, 15, aif_chan_src_text);
506
507static SOC_ENUM_SINGLE_DECL(aif1adcr_src,
508 WM8994_AIF1_CONTROL_1, 14, aif_chan_src_text);
509
510static SOC_ENUM_SINGLE_DECL(aif2adcl_src,
511 WM8994_AIF2_CONTROL_1, 15, aif_chan_src_text);
512
513static SOC_ENUM_SINGLE_DECL(aif2adcr_src,
514 WM8994_AIF2_CONTROL_1, 14, aif_chan_src_text);
515
516static SOC_ENUM_SINGLE_DECL(aif1dacl_src,
517 WM8994_AIF1_CONTROL_2, 15, aif_chan_src_text);
518
519static SOC_ENUM_SINGLE_DECL(aif1dacr_src,
520 WM8994_AIF1_CONTROL_2, 14, aif_chan_src_text);
521
522static SOC_ENUM_SINGLE_DECL(aif2dacl_src,
523 WM8994_AIF2_CONTROL_2, 15, aif_chan_src_text);
524
525static SOC_ENUM_SINGLE_DECL(aif2dacr_src,
526 WM8994_AIF2_CONTROL_2, 14, aif_chan_src_text);
527
528static const char *osr_text[] = {
529 "Low Power", "High Performance",
530};
531
532static SOC_ENUM_SINGLE_DECL(dac_osr,
533 WM8994_OVERSAMPLING, 0, osr_text);
534
535static SOC_ENUM_SINGLE_DECL(adc_osr,
536 WM8994_OVERSAMPLING, 1, osr_text);
537
538static const struct snd_kcontrol_new wm8994_snd_controls[] = {
539SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
540 WM8994_AIF1_ADC1_RIGHT_VOLUME,
541 1, 119, 0, digital_tlv),
542SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
543 WM8994_AIF1_ADC2_RIGHT_VOLUME,
544 1, 119, 0, digital_tlv),
545SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
546 WM8994_AIF2_ADC_RIGHT_VOLUME,
547 1, 119, 0, digital_tlv),
548
549SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
550SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
551SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
552SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
553
554SOC_ENUM("AIF1DACL Source", aif1dacl_src),
555SOC_ENUM("AIF1DACR Source", aif1dacr_src),
556SOC_ENUM("AIF2DACL Source", aif2dacl_src),
557SOC_ENUM("AIF2DACR Source", aif2dacr_src),
558
559SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
560 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
561SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
562 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
563SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
564 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
565
566SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
567SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
568
569SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
570SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
571SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
572
573WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
574WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
575WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
576
577WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
578WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
579WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
580
581WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
582WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
583WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
584
585SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
586 5, 12, 0, st_tlv),
587SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
588 0, 12, 0, st_tlv),
589SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
590 5, 12, 0, st_tlv),
591SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
592 0, 12, 0, st_tlv),
593SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
594SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
595
596SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
597SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
598
599SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
600SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
601
602SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
603SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
604
605SOC_ENUM("ADC OSR", adc_osr),
606SOC_ENUM("DAC OSR", dac_osr),
607
608SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
609 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
610SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
611 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
612
613SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
614 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
615SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
616 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
617
618SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
619 6, 1, 1, wm_hubs_spkmix_tlv),
620SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
621 2, 1, 1, wm_hubs_spkmix_tlv),
622
623SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
624 6, 1, 1, wm_hubs_spkmix_tlv),
625SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
626 2, 1, 1, wm_hubs_spkmix_tlv),
627
628SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
629 10, 15, 0, wm8994_3d_tlv),
630SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
631 8, 1, 0),
632SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
633 10, 15, 0, wm8994_3d_tlv),
634SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
635 8, 1, 0),
636SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
637 10, 15, 0, wm8994_3d_tlv),
638SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
639 8, 1, 0),
640};
641
642static const struct snd_kcontrol_new wm8994_eq_controls[] = {
643SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
644 eq_tlv),
645SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
646 eq_tlv),
647SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
648 eq_tlv),
649SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
650 eq_tlv),
651SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
652 eq_tlv),
653
654SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
655 eq_tlv),
656SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
657 eq_tlv),
658SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
659 eq_tlv),
660SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
661 eq_tlv),
662SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
663 eq_tlv),
664
665SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
666 eq_tlv),
667SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
668 eq_tlv),
669SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
670 eq_tlv),
671SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
672 eq_tlv),
673SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
674 eq_tlv),
675};
676
677static const struct snd_kcontrol_new wm8994_drc_controls[] = {
678SND_SOC_BYTES_MASK("AIF1.1 DRC", WM8994_AIF1_DRC1_1, 5,
679 WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
680 WM8994_AIF1ADC1R_DRC_ENA),
681SND_SOC_BYTES_MASK("AIF1.2 DRC", WM8994_AIF1_DRC2_1, 5,
682 WM8994_AIF1DAC2_DRC_ENA | WM8994_AIF1ADC2L_DRC_ENA |
683 WM8994_AIF1ADC2R_DRC_ENA),
684SND_SOC_BYTES_MASK("AIF2 DRC", WM8994_AIF2_DRC_1, 5,
685 WM8994_AIF2DAC_DRC_ENA | WM8994_AIF2ADCL_DRC_ENA |
686 WM8994_AIF2ADCR_DRC_ENA),
687};
688
689static const char *wm8958_ng_text[] = {
690 "30ms", "125ms", "250ms", "500ms",
691};
692
693static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac1_ng_hold,
694 WM8958_AIF1_DAC1_NOISE_GATE,
695 WM8958_AIF1DAC1_NG_THR_SHIFT,
696 wm8958_ng_text);
697
698static SOC_ENUM_SINGLE_DECL(wm8958_aif1dac2_ng_hold,
699 WM8958_AIF1_DAC2_NOISE_GATE,
700 WM8958_AIF1DAC2_NG_THR_SHIFT,
701 wm8958_ng_text);
702
703static SOC_ENUM_SINGLE_DECL(wm8958_aif2dac_ng_hold,
704 WM8958_AIF2_DAC_NOISE_GATE,
705 WM8958_AIF2DAC_NG_THR_SHIFT,
706 wm8958_ng_text);
707
708static const struct snd_kcontrol_new wm8958_snd_controls[] = {
709SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
710
711SOC_SINGLE("AIF1DAC1 Noise Gate Switch", WM8958_AIF1_DAC1_NOISE_GATE,
712 WM8958_AIF1DAC1_NG_ENA_SHIFT, 1, 0),
713SOC_ENUM("AIF1DAC1 Noise Gate Hold Time", wm8958_aif1dac1_ng_hold),
714SOC_SINGLE_TLV("AIF1DAC1 Noise Gate Threshold Volume",
715 WM8958_AIF1_DAC1_NOISE_GATE, WM8958_AIF1DAC1_NG_THR_SHIFT,
716 7, 1, ng_tlv),
717
718SOC_SINGLE("AIF1DAC2 Noise Gate Switch", WM8958_AIF1_DAC2_NOISE_GATE,
719 WM8958_AIF1DAC2_NG_ENA_SHIFT, 1, 0),
720SOC_ENUM("AIF1DAC2 Noise Gate Hold Time", wm8958_aif1dac2_ng_hold),
721SOC_SINGLE_TLV("AIF1DAC2 Noise Gate Threshold Volume",
722 WM8958_AIF1_DAC2_NOISE_GATE, WM8958_AIF1DAC2_NG_THR_SHIFT,
723 7, 1, ng_tlv),
724
725SOC_SINGLE("AIF2DAC Noise Gate Switch", WM8958_AIF2_DAC_NOISE_GATE,
726 WM8958_AIF2DAC_NG_ENA_SHIFT, 1, 0),
727SOC_ENUM("AIF2DAC Noise Gate Hold Time", wm8958_aif2dac_ng_hold),
728SOC_SINGLE_TLV("AIF2DAC Noise Gate Threshold Volume",
729 WM8958_AIF2_DAC_NOISE_GATE, WM8958_AIF2DAC_NG_THR_SHIFT,
730 7, 1, ng_tlv),
731};
732
733static const struct snd_kcontrol_new wm1811_snd_controls[] = {
734SOC_SINGLE_TLV("MIXINL IN1LP Boost Volume", WM8994_INPUT_MIXER_1, 7, 1, 0,
735 mixin_boost_tlv),
736SOC_SINGLE_TLV("MIXINL IN1RP Boost Volume", WM8994_INPUT_MIXER_1, 8, 1, 0,
737 mixin_boost_tlv),
738};
739
740/* We run all mode setting through a function to enforce audio mode */
741static void wm1811_jackdet_set_mode(struct snd_soc_codec *codec, u16 mode)
742{
743 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
744
745 if (!wm8994->jackdet || !wm8994->micdet[0].jack)
746 return;
747
748 if (wm8994->active_refcount)
749 mode = WM1811_JACKDET_MODE_AUDIO;
750
751 if (mode == wm8994->jackdet_mode)
752 return;
753
754 wm8994->jackdet_mode = mode;
755
756 /* Always use audio mode to detect while the system is active */
757 if (mode != WM1811_JACKDET_MODE_NONE)
758 mode = WM1811_JACKDET_MODE_AUDIO;
759
760 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
761 WM1811_JACKDET_MODE_MASK, mode);
762}
763
764static void active_reference(struct snd_soc_codec *codec)
765{
766 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
767
768 mutex_lock(&wm8994->accdet_lock);
769
770 wm8994->active_refcount++;
771
772 dev_dbg(codec->dev, "Active refcount incremented, now %d\n",
773 wm8994->active_refcount);
774
775 /* If we're using jack detection go into audio mode */
776 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_AUDIO);
777
778 mutex_unlock(&wm8994->accdet_lock);
779}
780
781static void active_dereference(struct snd_soc_codec *codec)
782{
783 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
784 u16 mode;
785
786 mutex_lock(&wm8994->accdet_lock);
787
788 wm8994->active_refcount--;
789
790 dev_dbg(codec->dev, "Active refcount decremented, now %d\n",
791 wm8994->active_refcount);
792
793 if (wm8994->active_refcount == 0) {
794 /* Go into appropriate detection only mode */
795 if (wm8994->jack_mic || wm8994->mic_detecting)
796 mode = WM1811_JACKDET_MODE_MIC;
797 else
798 mode = WM1811_JACKDET_MODE_JACK;
799
800 wm1811_jackdet_set_mode(codec, mode);
801 }
802
803 mutex_unlock(&wm8994->accdet_lock);
804}
805
806static int clk_sys_event(struct snd_soc_dapm_widget *w,
807 struct snd_kcontrol *kcontrol, int event)
808{
809 struct snd_soc_codec *codec = w->codec;
810 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
811
812 switch (event) {
813 case SND_SOC_DAPM_PRE_PMU:
814 return configure_clock(codec);
815
816 case SND_SOC_DAPM_POST_PMU:
817 /*
818 * JACKDET won't run until we start the clock and it
819 * only reports deltas, make sure we notify the state
820 * up the stack on startup. Use a *very* generous
821 * timeout for paranoia, there's no urgency and we
822 * don't want false reports.
823 */
824 if (wm8994->jackdet && !wm8994->clk_has_run) {
825 queue_delayed_work(system_power_efficient_wq,
826 &wm8994->jackdet_bootstrap,
827 msecs_to_jiffies(1000));
828 wm8994->clk_has_run = true;
829 }
830 break;
831
832 case SND_SOC_DAPM_POST_PMD:
833 configure_clock(codec);
834 break;
835 }
836
837 return 0;
838}
839
840static void vmid_reference(struct snd_soc_codec *codec)
841{
842 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
843
844 pm_runtime_get_sync(codec->dev);
845
846 wm8994->vmid_refcount++;
847
848 dev_dbg(codec->dev, "Referencing VMID, refcount is now %d\n",
849 wm8994->vmid_refcount);
850
851 if (wm8994->vmid_refcount == 1) {
852 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
853 WM8994_LINEOUT1_DISCH |
854 WM8994_LINEOUT2_DISCH, 0);
855
856 wm_hubs_vmid_ena(codec);
857
858 switch (wm8994->vmid_mode) {
859 default:
860 WARN_ON(NULL == "Invalid VMID mode");
861 case WM8994_VMID_NORMAL:
862 /* Startup bias, VMID ramp & buffer */
863 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
864 WM8994_BIAS_SRC |
865 WM8994_VMID_DISCH |
866 WM8994_STARTUP_BIAS_ENA |
867 WM8994_VMID_BUF_ENA |
868 WM8994_VMID_RAMP_MASK,
869 WM8994_BIAS_SRC |
870 WM8994_STARTUP_BIAS_ENA |
871 WM8994_VMID_BUF_ENA |
872 (0x2 << WM8994_VMID_RAMP_SHIFT));
873
874 /* Main bias enable, VMID=2x40k */
875 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
876 WM8994_BIAS_ENA |
877 WM8994_VMID_SEL_MASK,
878 WM8994_BIAS_ENA | 0x2);
879
880 msleep(300);
881
882 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
883 WM8994_VMID_RAMP_MASK |
884 WM8994_BIAS_SRC,
885 0);
886 break;
887
888 case WM8994_VMID_FORCE:
889 /* Startup bias, slow VMID ramp & buffer */
890 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
891 WM8994_BIAS_SRC |
892 WM8994_VMID_DISCH |
893 WM8994_STARTUP_BIAS_ENA |
894 WM8994_VMID_BUF_ENA |
895 WM8994_VMID_RAMP_MASK,
896 WM8994_BIAS_SRC |
897 WM8994_STARTUP_BIAS_ENA |
898 WM8994_VMID_BUF_ENA |
899 (0x2 << WM8994_VMID_RAMP_SHIFT));
900
901 /* Main bias enable, VMID=2x40k */
902 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
903 WM8994_BIAS_ENA |
904 WM8994_VMID_SEL_MASK,
905 WM8994_BIAS_ENA | 0x2);
906
907 msleep(400);
908
909 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
910 WM8994_VMID_RAMP_MASK |
911 WM8994_BIAS_SRC,
912 0);
913 break;
914 }
915 }
916}
917
918static void vmid_dereference(struct snd_soc_codec *codec)
919{
920 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
921
922 wm8994->vmid_refcount--;
923
924 dev_dbg(codec->dev, "Dereferencing VMID, refcount is now %d\n",
925 wm8994->vmid_refcount);
926
927 if (wm8994->vmid_refcount == 0) {
928 if (wm8994->hubs.lineout1_se)
929 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
930 WM8994_LINEOUT1N_ENA |
931 WM8994_LINEOUT1P_ENA,
932 WM8994_LINEOUT1N_ENA |
933 WM8994_LINEOUT1P_ENA);
934
935 if (wm8994->hubs.lineout2_se)
936 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
937 WM8994_LINEOUT2N_ENA |
938 WM8994_LINEOUT2P_ENA,
939 WM8994_LINEOUT2N_ENA |
940 WM8994_LINEOUT2P_ENA);
941
942 /* Start discharging VMID */
943 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
944 WM8994_BIAS_SRC |
945 WM8994_VMID_DISCH,
946 WM8994_BIAS_SRC |
947 WM8994_VMID_DISCH);
948
949 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
950 WM8994_VMID_SEL_MASK, 0);
951
952 msleep(400);
953
954 /* Active discharge */
955 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
956 WM8994_LINEOUT1_DISCH |
957 WM8994_LINEOUT2_DISCH,
958 WM8994_LINEOUT1_DISCH |
959 WM8994_LINEOUT2_DISCH);
960
961 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_3,
962 WM8994_LINEOUT1N_ENA |
963 WM8994_LINEOUT1P_ENA |
964 WM8994_LINEOUT2N_ENA |
965 WM8994_LINEOUT2P_ENA, 0);
966
967 /* Switch off startup biases */
968 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
969 WM8994_BIAS_SRC |
970 WM8994_STARTUP_BIAS_ENA |
971 WM8994_VMID_BUF_ENA |
972 WM8994_VMID_RAMP_MASK, 0);
973
974 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
975 WM8994_VMID_SEL_MASK, 0);
976 }
977
978 pm_runtime_put(codec->dev);
979}
980
981static int vmid_event(struct snd_soc_dapm_widget *w,
982 struct snd_kcontrol *kcontrol, int event)
983{
984 struct snd_soc_codec *codec = w->codec;
985
986 switch (event) {
987 case SND_SOC_DAPM_PRE_PMU:
988 vmid_reference(codec);
989 break;
990
991 case SND_SOC_DAPM_POST_PMD:
992 vmid_dereference(codec);
993 break;
994 }
995
996 return 0;
997}
998
999static bool wm8994_check_class_w_digital(struct snd_soc_codec *codec)
1000{
1001 int source = 0; /* GCC flow analysis can't track enable */
1002 int reg, reg_r;
1003
1004 /* We also need the same AIF source for L/R and only one path */
1005 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
1006 switch (reg) {
1007 case WM8994_AIF2DACL_TO_DAC1L:
1008 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
1009 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1010 break;
1011 case WM8994_AIF1DAC2L_TO_DAC1L:
1012 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
1013 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1014 break;
1015 case WM8994_AIF1DAC1L_TO_DAC1L:
1016 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
1017 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
1018 break;
1019 default:
1020 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
1021 return false;
1022 }
1023
1024 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
1025 if (reg_r != reg) {
1026 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
1027 return false;
1028 }
1029
1030 /* Set the source up */
1031 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
1032 WM8994_CP_DYN_SRC_SEL_MASK, source);
1033
1034 return true;
1035}
1036
1037static int aif1clk_ev(struct snd_soc_dapm_widget *w,
1038 struct snd_kcontrol *kcontrol, int event)
1039{
1040 struct snd_soc_codec *codec = w->codec;
1041 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1042 struct wm8994 *control = wm8994->wm8994;
1043 int mask = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA;
1044 int i;
1045 int dac;
1046 int adc;
1047 int val;
1048
1049 switch (control->type) {
1050 case WM8994:
1051 case WM8958:
1052 mask |= WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA;
1053 break;
1054 default:
1055 break;
1056 }
1057
1058 switch (event) {
1059 case SND_SOC_DAPM_PRE_PMU:
1060 /* Don't enable timeslot 2 if not in use */
1061 if (wm8994->channels[0] <= 2)
1062 mask &= ~(WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
1063
1064 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_1);
1065 if ((val & WM8994_AIF1ADCL_SRC) &&
1066 (val & WM8994_AIF1ADCR_SRC))
1067 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA;
1068 else if (!(val & WM8994_AIF1ADCL_SRC) &&
1069 !(val & WM8994_AIF1ADCR_SRC))
1070 adc = WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1071 else
1072 adc = WM8994_AIF1ADC1R_ENA | WM8994_AIF1ADC2R_ENA |
1073 WM8994_AIF1ADC1L_ENA | WM8994_AIF1ADC2L_ENA;
1074
1075 val = snd_soc_read(codec, WM8994_AIF1_CONTROL_2);
1076 if ((val & WM8994_AIF1DACL_SRC) &&
1077 (val & WM8994_AIF1DACR_SRC))
1078 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA;
1079 else if (!(val & WM8994_AIF1DACL_SRC) &&
1080 !(val & WM8994_AIF1DACR_SRC))
1081 dac = WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1082 else
1083 dac = WM8994_AIF1DAC1R_ENA | WM8994_AIF1DAC2R_ENA |
1084 WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC2L_ENA;
1085
1086 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1087 mask, adc);
1088 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1089 mask, dac);
1090 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1091 WM8994_AIF1DSPCLK_ENA |
1092 WM8994_SYSDSPCLK_ENA,
1093 WM8994_AIF1DSPCLK_ENA |
1094 WM8994_SYSDSPCLK_ENA);
1095 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4, mask,
1096 WM8994_AIF1ADC1R_ENA |
1097 WM8994_AIF1ADC1L_ENA |
1098 WM8994_AIF1ADC2R_ENA |
1099 WM8994_AIF1ADC2L_ENA);
1100 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5, mask,
1101 WM8994_AIF1DAC1R_ENA |
1102 WM8994_AIF1DAC1L_ENA |
1103 WM8994_AIF1DAC2R_ENA |
1104 WM8994_AIF1DAC2L_ENA);
1105 break;
1106
1107 case SND_SOC_DAPM_POST_PMU:
1108 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1109 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1110 snd_soc_read(codec,
1111 wm8994_vu_bits[i].reg));
1112 break;
1113
1114 case SND_SOC_DAPM_PRE_PMD:
1115 case SND_SOC_DAPM_POST_PMD:
1116 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1117 mask, 0);
1118 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1119 mask, 0);
1120
1121 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1122 if (val & WM8994_AIF2DSPCLK_ENA)
1123 val = WM8994_SYSDSPCLK_ENA;
1124 else
1125 val = 0;
1126 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1127 WM8994_SYSDSPCLK_ENA |
1128 WM8994_AIF1DSPCLK_ENA, val);
1129 break;
1130 }
1131
1132 return 0;
1133}
1134
1135static int aif2clk_ev(struct snd_soc_dapm_widget *w,
1136 struct snd_kcontrol *kcontrol, int event)
1137{
1138 struct snd_soc_codec *codec = w->codec;
1139 int i;
1140 int dac;
1141 int adc;
1142 int val;
1143
1144 switch (event) {
1145 case SND_SOC_DAPM_PRE_PMU:
1146 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_1);
1147 if ((val & WM8994_AIF2ADCL_SRC) &&
1148 (val & WM8994_AIF2ADCR_SRC))
1149 adc = WM8994_AIF2ADCR_ENA;
1150 else if (!(val & WM8994_AIF2ADCL_SRC) &&
1151 !(val & WM8994_AIF2ADCR_SRC))
1152 adc = WM8994_AIF2ADCL_ENA;
1153 else
1154 adc = WM8994_AIF2ADCL_ENA | WM8994_AIF2ADCR_ENA;
1155
1156
1157 val = snd_soc_read(codec, WM8994_AIF2_CONTROL_2);
1158 if ((val & WM8994_AIF2DACL_SRC) &&
1159 (val & WM8994_AIF2DACR_SRC))
1160 dac = WM8994_AIF2DACR_ENA;
1161 else if (!(val & WM8994_AIF2DACL_SRC) &&
1162 !(val & WM8994_AIF2DACR_SRC))
1163 dac = WM8994_AIF2DACL_ENA;
1164 else
1165 dac = WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA;
1166
1167 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1168 WM8994_AIF2ADCL_ENA |
1169 WM8994_AIF2ADCR_ENA, adc);
1170 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1171 WM8994_AIF2DACL_ENA |
1172 WM8994_AIF2DACR_ENA, dac);
1173 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1174 WM8994_AIF2DSPCLK_ENA |
1175 WM8994_SYSDSPCLK_ENA,
1176 WM8994_AIF2DSPCLK_ENA |
1177 WM8994_SYSDSPCLK_ENA);
1178 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1179 WM8994_AIF2ADCL_ENA |
1180 WM8994_AIF2ADCR_ENA,
1181 WM8994_AIF2ADCL_ENA |
1182 WM8994_AIF2ADCR_ENA);
1183 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1184 WM8994_AIF2DACL_ENA |
1185 WM8994_AIF2DACR_ENA,
1186 WM8994_AIF2DACL_ENA |
1187 WM8994_AIF2DACR_ENA);
1188 break;
1189
1190 case SND_SOC_DAPM_POST_PMU:
1191 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
1192 snd_soc_write(codec, wm8994_vu_bits[i].reg,
1193 snd_soc_read(codec,
1194 wm8994_vu_bits[i].reg));
1195 break;
1196
1197 case SND_SOC_DAPM_PRE_PMD:
1198 case SND_SOC_DAPM_POST_PMD:
1199 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1200 WM8994_AIF2DACL_ENA |
1201 WM8994_AIF2DACR_ENA, 0);
1202 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_4,
1203 WM8994_AIF2ADCL_ENA |
1204 WM8994_AIF2ADCR_ENA, 0);
1205
1206 val = snd_soc_read(codec, WM8994_CLOCKING_1);
1207 if (val & WM8994_AIF1DSPCLK_ENA)
1208 val = WM8994_SYSDSPCLK_ENA;
1209 else
1210 val = 0;
1211 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
1212 WM8994_SYSDSPCLK_ENA |
1213 WM8994_AIF2DSPCLK_ENA, val);
1214 break;
1215 }
1216
1217 return 0;
1218}
1219
1220static int aif1clk_late_ev(struct snd_soc_dapm_widget *w,
1221 struct snd_kcontrol *kcontrol, int event)
1222{
1223 struct snd_soc_codec *codec = w->codec;
1224 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1225
1226 switch (event) {
1227 case SND_SOC_DAPM_PRE_PMU:
1228 wm8994->aif1clk_enable = 1;
1229 break;
1230 case SND_SOC_DAPM_POST_PMD:
1231 wm8994->aif1clk_disable = 1;
1232 break;
1233 }
1234
1235 return 0;
1236}
1237
1238static int aif2clk_late_ev(struct snd_soc_dapm_widget *w,
1239 struct snd_kcontrol *kcontrol, int event)
1240{
1241 struct snd_soc_codec *codec = w->codec;
1242 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1243
1244 switch (event) {
1245 case SND_SOC_DAPM_PRE_PMU:
1246 wm8994->aif2clk_enable = 1;
1247 break;
1248 case SND_SOC_DAPM_POST_PMD:
1249 wm8994->aif2clk_disable = 1;
1250 break;
1251 }
1252
1253 return 0;
1254}
1255
1256static int late_enable_ev(struct snd_soc_dapm_widget *w,
1257 struct snd_kcontrol *kcontrol, int event)
1258{
1259 struct snd_soc_codec *codec = w->codec;
1260 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1261
1262 switch (event) {
1263 case SND_SOC_DAPM_PRE_PMU:
1264 if (wm8994->aif1clk_enable) {
1265 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1266 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1267 WM8994_AIF1CLK_ENA_MASK,
1268 WM8994_AIF1CLK_ENA);
1269 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1270 wm8994->aif1clk_enable = 0;
1271 }
1272 if (wm8994->aif2clk_enable) {
1273 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMU);
1274 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1275 WM8994_AIF2CLK_ENA_MASK,
1276 WM8994_AIF2CLK_ENA);
1277 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMU);
1278 wm8994->aif2clk_enable = 0;
1279 }
1280 break;
1281 }
1282
1283 /* We may also have postponed startup of DSP, handle that. */
1284 wm8958_aif_ev(w, kcontrol, event);
1285
1286 return 0;
1287}
1288
1289static int late_disable_ev(struct snd_soc_dapm_widget *w,
1290 struct snd_kcontrol *kcontrol, int event)
1291{
1292 struct snd_soc_codec *codec = w->codec;
1293 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1294
1295 switch (event) {
1296 case SND_SOC_DAPM_POST_PMD:
1297 if (wm8994->aif1clk_disable) {
1298 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1299 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1300 WM8994_AIF1CLK_ENA_MASK, 0);
1301 aif1clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1302 wm8994->aif1clk_disable = 0;
1303 }
1304 if (wm8994->aif2clk_disable) {
1305 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_PRE_PMD);
1306 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1307 WM8994_AIF2CLK_ENA_MASK, 0);
1308 aif2clk_ev(w, kcontrol, SND_SOC_DAPM_POST_PMD);
1309 wm8994->aif2clk_disable = 0;
1310 }
1311 break;
1312 }
1313
1314 return 0;
1315}
1316
1317static int adc_mux_ev(struct snd_soc_dapm_widget *w,
1318 struct snd_kcontrol *kcontrol, int event)
1319{
1320 late_enable_ev(w, kcontrol, event);
1321 return 0;
1322}
1323
1324static int micbias_ev(struct snd_soc_dapm_widget *w,
1325 struct snd_kcontrol *kcontrol, int event)
1326{
1327 late_enable_ev(w, kcontrol, event);
1328 return 0;
1329}
1330
1331static int dac_ev(struct snd_soc_dapm_widget *w,
1332 struct snd_kcontrol *kcontrol, int event)
1333{
1334 struct snd_soc_codec *codec = w->codec;
1335 unsigned int mask = 1 << w->shift;
1336
1337 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
1338 mask, mask);
1339 return 0;
1340}
1341
1342static const char *adc_mux_text[] = {
1343 "ADC",
1344 "DMIC",
1345};
1346
1347static SOC_ENUM_SINGLE_VIRT_DECL(adc_enum, adc_mux_text);
1348
1349static const struct snd_kcontrol_new adcl_mux =
1350 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1351
1352static const struct snd_kcontrol_new adcr_mux =
1353 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1354
1355static const struct snd_kcontrol_new left_speaker_mixer[] = {
1356SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1357SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1358SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1359SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1360SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1361};
1362
1363static const struct snd_kcontrol_new right_speaker_mixer[] = {
1364SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1365SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1366SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1367SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1368SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1369};
1370
1371/* Debugging; dump chip status after DAPM transitions */
1372static int post_ev(struct snd_soc_dapm_widget *w,
1373 struct snd_kcontrol *kcontrol, int event)
1374{
1375 struct snd_soc_codec *codec = w->codec;
1376 dev_dbg(codec->dev, "SRC status: %x\n",
1377 snd_soc_read(codec,
1378 WM8994_RATE_STATUS));
1379 return 0;
1380}
1381
1382static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1383SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1384 1, 1, 0),
1385SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1386 0, 1, 0),
1387};
1388
1389static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1390SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1391 1, 1, 0),
1392SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1393 0, 1, 0),
1394};
1395
1396static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1397SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1398 1, 1, 0),
1399SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1400 0, 1, 0),
1401};
1402
1403static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1404SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1405 1, 1, 0),
1406SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1407 0, 1, 0),
1408};
1409
1410static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1411SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1412 5, 1, 0),
1413SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1414 4, 1, 0),
1415SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1416 2, 1, 0),
1417SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1418 1, 1, 0),
1419SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1420 0, 1, 0),
1421};
1422
1423static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1424SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1425 5, 1, 0),
1426SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1427 4, 1, 0),
1428SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1429 2, 1, 0),
1430SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1431 1, 1, 0),
1432SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1433 0, 1, 0),
1434};
1435
1436#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1437 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
1438 snd_soc_dapm_get_volsw, wm8994_put_class_w)
1439
1440static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1441 struct snd_ctl_elem_value *ucontrol)
1442{
1443 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
1444 int ret;
1445
1446 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1447
1448 wm_hubs_update_class_w(codec);
1449
1450 return ret;
1451}
1452
1453static const struct snd_kcontrol_new dac1l_mix[] = {
1454WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1455 5, 1, 0),
1456WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1457 4, 1, 0),
1458WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1459 2, 1, 0),
1460WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1461 1, 1, 0),
1462WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1463 0, 1, 0),
1464};
1465
1466static const struct snd_kcontrol_new dac1r_mix[] = {
1467WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1468 5, 1, 0),
1469WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1470 4, 1, 0),
1471WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1472 2, 1, 0),
1473WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1474 1, 1, 0),
1475WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1476 0, 1, 0),
1477};
1478
1479static const char *sidetone_text[] = {
1480 "ADC/DMIC1", "DMIC2",
1481};
1482
1483static SOC_ENUM_SINGLE_DECL(sidetone1_enum,
1484 WM8994_SIDETONE, 0, sidetone_text);
1485
1486static const struct snd_kcontrol_new sidetone1_mux =
1487 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1488
1489static SOC_ENUM_SINGLE_DECL(sidetone2_enum,
1490 WM8994_SIDETONE, 1, sidetone_text);
1491
1492static const struct snd_kcontrol_new sidetone2_mux =
1493 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1494
1495static const char *aif1dac_text[] = {
1496 "AIF1DACDAT", "AIF3DACDAT",
1497};
1498
1499static const char *loopback_text[] = {
1500 "None", "ADCDAT",
1501};
1502
1503static SOC_ENUM_SINGLE_DECL(aif1_loopback_enum,
1504 WM8994_AIF1_CONTROL_2,
1505 WM8994_AIF1_LOOPBACK_SHIFT,
1506 loopback_text);
1507
1508static const struct snd_kcontrol_new aif1_loopback =
1509 SOC_DAPM_ENUM("AIF1 Loopback", aif1_loopback_enum);
1510
1511static SOC_ENUM_SINGLE_DECL(aif2_loopback_enum,
1512 WM8994_AIF2_CONTROL_2,
1513 WM8994_AIF2_LOOPBACK_SHIFT,
1514 loopback_text);
1515
1516static const struct snd_kcontrol_new aif2_loopback =
1517 SOC_DAPM_ENUM("AIF2 Loopback", aif2_loopback_enum);
1518
1519static SOC_ENUM_SINGLE_DECL(aif1dac_enum,
1520 WM8994_POWER_MANAGEMENT_6, 0, aif1dac_text);
1521
1522static const struct snd_kcontrol_new aif1dac_mux =
1523 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1524
1525static const char *aif2dac_text[] = {
1526 "AIF2DACDAT", "AIF3DACDAT",
1527};
1528
1529static SOC_ENUM_SINGLE_DECL(aif2dac_enum,
1530 WM8994_POWER_MANAGEMENT_6, 1, aif2dac_text);
1531
1532static const struct snd_kcontrol_new aif2dac_mux =
1533 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1534
1535static const char *aif2adc_text[] = {
1536 "AIF2ADCDAT", "AIF3DACDAT",
1537};
1538
1539static SOC_ENUM_SINGLE_DECL(aif2adc_enum,
1540 WM8994_POWER_MANAGEMENT_6, 2, aif2adc_text);
1541
1542static const struct snd_kcontrol_new aif2adc_mux =
1543 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1544
1545static const char *aif3adc_text[] = {
1546 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1547};
1548
1549static SOC_ENUM_SINGLE_DECL(wm8994_aif3adc_enum,
1550 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1551
1552static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1553 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1554
1555static SOC_ENUM_SINGLE_DECL(wm8958_aif3adc_enum,
1556 WM8994_POWER_MANAGEMENT_6, 3, aif3adc_text);
1557
1558static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1559 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1560
1561static const char *mono_pcm_out_text[] = {
1562 "None", "AIF2ADCL", "AIF2ADCR",
1563};
1564
1565static SOC_ENUM_SINGLE_DECL(mono_pcm_out_enum,
1566 WM8994_POWER_MANAGEMENT_6, 9, mono_pcm_out_text);
1567
1568static const struct snd_kcontrol_new mono_pcm_out_mux =
1569 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1570
1571static const char *aif2dac_src_text[] = {
1572 "AIF2", "AIF3",
1573};
1574
1575/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1576static SOC_ENUM_SINGLE_DECL(aif2dacl_src_enum,
1577 WM8994_POWER_MANAGEMENT_6, 7, aif2dac_src_text);
1578
1579static const struct snd_kcontrol_new aif2dacl_src_mux =
1580 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1581
1582static SOC_ENUM_SINGLE_DECL(aif2dacr_src_enum,
1583 WM8994_POWER_MANAGEMENT_6, 8, aif2dac_src_text);
1584
1585static const struct snd_kcontrol_new aif2dacr_src_mux =
1586 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1587
1588static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1589SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_late_ev,
1590 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1591SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_late_ev,
1592 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1593
1594SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1595 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1596SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1597 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1598SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1599 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1600SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1601 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1602SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1603 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1604
1605SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1606 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1607 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1608SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1609 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1610 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1611SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux,
1612 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1613SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux,
1614 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1615
1616SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1617};
1618
1619static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1620SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, aif1clk_ev,
1621 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1622 SND_SOC_DAPM_PRE_PMD),
1623SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, aif2clk_ev,
1624 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1625 SND_SOC_DAPM_PRE_PMD),
1626SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1627SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1628 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1629SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1630 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1631SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
1632SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
1633};
1634
1635static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1636SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1637 dac_ev, SND_SOC_DAPM_PRE_PMU),
1638SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1639 dac_ev, SND_SOC_DAPM_PRE_PMU),
1640SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1641 dac_ev, SND_SOC_DAPM_PRE_PMU),
1642SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1643 dac_ev, SND_SOC_DAPM_PRE_PMU),
1644};
1645
1646static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1647SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1648SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1649SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1650SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1651};
1652
1653static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1654SND_SOC_DAPM_VIRT_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1655 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1656SND_SOC_DAPM_VIRT_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1657 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1658};
1659
1660static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1661SND_SOC_DAPM_VIRT_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1662SND_SOC_DAPM_VIRT_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1663};
1664
1665static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1666SND_SOC_DAPM_INPUT("DMIC1DAT"),
1667SND_SOC_DAPM_INPUT("DMIC2DAT"),
1668SND_SOC_DAPM_INPUT("Clock"),
1669
1670SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1671 SND_SOC_DAPM_PRE_PMU),
1672SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, vmid_event,
1673 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1674
1675SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1676 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1677 SND_SOC_DAPM_PRE_PMD),
1678
1679SND_SOC_DAPM_SUPPLY("DSP1CLK", SND_SOC_NOPM, 3, 0, NULL, 0),
1680SND_SOC_DAPM_SUPPLY("DSP2CLK", SND_SOC_NOPM, 2, 0, NULL, 0),
1681SND_SOC_DAPM_SUPPLY("DSPINTCLK", SND_SOC_NOPM, 1, 0, NULL, 0),
1682
1683SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1684 0, SND_SOC_NOPM, 9, 0),
1685SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1686 0, SND_SOC_NOPM, 8, 0),
1687SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1688 SND_SOC_NOPM, 9, 0, wm8958_aif_ev,
1689 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1690SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1691 SND_SOC_NOPM, 8, 0, wm8958_aif_ev,
1692 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1693
1694SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1695 0, SND_SOC_NOPM, 11, 0),
1696SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1697 0, SND_SOC_NOPM, 10, 0),
1698SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1699 SND_SOC_NOPM, 11, 0, wm8958_aif_ev,
1700 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1701SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1702 SND_SOC_NOPM, 10, 0, wm8958_aif_ev,
1703 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1704
1705SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1706 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1707SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1708 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1709
1710SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1711 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1712SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1713 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1714
1715SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1716 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1717SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1718 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1719
1720SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1721SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1722
1723SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1724 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1725SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1726 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1727
1728SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1729 SND_SOC_NOPM, 13, 0),
1730SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1731 SND_SOC_NOPM, 12, 0),
1732SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1733 SND_SOC_NOPM, 13, 0, wm8958_aif_ev,
1734 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1735SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1736 SND_SOC_NOPM, 12, 0, wm8958_aif_ev,
1737 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1738
1739SND_SOC_DAPM_AIF_IN("AIF1DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1740SND_SOC_DAPM_AIF_IN("AIF2DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1741SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1742SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1743
1744SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1745SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1746SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1747
1748SND_SOC_DAPM_AIF_IN("AIF3DACDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1749SND_SOC_DAPM_AIF_OUT("AIF3ADCDAT", NULL, 0, SND_SOC_NOPM, 0, 0),
1750
1751SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1752
1753SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1754SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1755SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1756SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1757
1758/* Power is done with the muxes since the ADC power also controls the
1759 * downsampling chain, the chip will automatically manage the analogue
1760 * specific portions.
1761 */
1762SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1763SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1764
1765SND_SOC_DAPM_MUX("AIF1 Loopback", SND_SOC_NOPM, 0, 0, &aif1_loopback),
1766SND_SOC_DAPM_MUX("AIF2 Loopback", SND_SOC_NOPM, 0, 0, &aif2_loopback),
1767
1768SND_SOC_DAPM_POST("Debug log", post_ev),
1769};
1770
1771static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1772SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1773};
1774
1775static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1776SND_SOC_DAPM_SUPPLY("AIF3", WM8994_POWER_MANAGEMENT_6, 5, 1, NULL, 0),
1777SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1778SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1779SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1780SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1781};
1782
1783static const struct snd_soc_dapm_route intercon[] = {
1784 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1785 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1786
1787 { "DSP1CLK", NULL, "CLK_SYS" },
1788 { "DSP2CLK", NULL, "CLK_SYS" },
1789 { "DSPINTCLK", NULL, "CLK_SYS" },
1790
1791 { "AIF1ADC1L", NULL, "AIF1CLK" },
1792 { "AIF1ADC1L", NULL, "DSP1CLK" },
1793 { "AIF1ADC1R", NULL, "AIF1CLK" },
1794 { "AIF1ADC1R", NULL, "DSP1CLK" },
1795 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1796
1797 { "AIF1DAC1L", NULL, "AIF1CLK" },
1798 { "AIF1DAC1L", NULL, "DSP1CLK" },
1799 { "AIF1DAC1R", NULL, "AIF1CLK" },
1800 { "AIF1DAC1R", NULL, "DSP1CLK" },
1801 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1802
1803 { "AIF1ADC2L", NULL, "AIF1CLK" },
1804 { "AIF1ADC2L", NULL, "DSP1CLK" },
1805 { "AIF1ADC2R", NULL, "AIF1CLK" },
1806 { "AIF1ADC2R", NULL, "DSP1CLK" },
1807 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1808
1809 { "AIF1DAC2L", NULL, "AIF1CLK" },
1810 { "AIF1DAC2L", NULL, "DSP1CLK" },
1811 { "AIF1DAC2R", NULL, "AIF1CLK" },
1812 { "AIF1DAC2R", NULL, "DSP1CLK" },
1813 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1814
1815 { "AIF2ADCL", NULL, "AIF2CLK" },
1816 { "AIF2ADCL", NULL, "DSP2CLK" },
1817 { "AIF2ADCR", NULL, "AIF2CLK" },
1818 { "AIF2ADCR", NULL, "DSP2CLK" },
1819 { "AIF2ADCR", NULL, "DSPINTCLK" },
1820
1821 { "AIF2DACL", NULL, "AIF2CLK" },
1822 { "AIF2DACL", NULL, "DSP2CLK" },
1823 { "AIF2DACR", NULL, "AIF2CLK" },
1824 { "AIF2DACR", NULL, "DSP2CLK" },
1825 { "AIF2DACR", NULL, "DSPINTCLK" },
1826
1827 { "DMIC1L", NULL, "DMIC1DAT" },
1828 { "DMIC1L", NULL, "CLK_SYS" },
1829 { "DMIC1R", NULL, "DMIC1DAT" },
1830 { "DMIC1R", NULL, "CLK_SYS" },
1831 { "DMIC2L", NULL, "DMIC2DAT" },
1832 { "DMIC2L", NULL, "CLK_SYS" },
1833 { "DMIC2R", NULL, "DMIC2DAT" },
1834 { "DMIC2R", NULL, "CLK_SYS" },
1835
1836 { "ADCL", NULL, "AIF1CLK" },
1837 { "ADCL", NULL, "DSP1CLK" },
1838 { "ADCL", NULL, "DSPINTCLK" },
1839
1840 { "ADCR", NULL, "AIF1CLK" },
1841 { "ADCR", NULL, "DSP1CLK" },
1842 { "ADCR", NULL, "DSPINTCLK" },
1843
1844 { "ADCL Mux", "ADC", "ADCL" },
1845 { "ADCL Mux", "DMIC", "DMIC1L" },
1846 { "ADCR Mux", "ADC", "ADCR" },
1847 { "ADCR Mux", "DMIC", "DMIC1R" },
1848
1849 { "DAC1L", NULL, "AIF1CLK" },
1850 { "DAC1L", NULL, "DSP1CLK" },
1851 { "DAC1L", NULL, "DSPINTCLK" },
1852
1853 { "DAC1R", NULL, "AIF1CLK" },
1854 { "DAC1R", NULL, "DSP1CLK" },
1855 { "DAC1R", NULL, "DSPINTCLK" },
1856
1857 { "DAC2L", NULL, "AIF2CLK" },
1858 { "DAC2L", NULL, "DSP2CLK" },
1859 { "DAC2L", NULL, "DSPINTCLK" },
1860
1861 { "DAC2R", NULL, "AIF2DACR" },
1862 { "DAC2R", NULL, "AIF2CLK" },
1863 { "DAC2R", NULL, "DSP2CLK" },
1864 { "DAC2R", NULL, "DSPINTCLK" },
1865
1866 { "TOCLK", NULL, "CLK_SYS" },
1867
1868 { "AIF1DACDAT", NULL, "AIF1 Playback" },
1869 { "AIF2DACDAT", NULL, "AIF2 Playback" },
1870 { "AIF3DACDAT", NULL, "AIF3 Playback" },
1871
1872 { "AIF1 Capture", NULL, "AIF1ADCDAT" },
1873 { "AIF2 Capture", NULL, "AIF2ADCDAT" },
1874 { "AIF3 Capture", NULL, "AIF3ADCDAT" },
1875
1876 /* AIF1 outputs */
1877 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1878 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1879 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1880
1881 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1882 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1883 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1884
1885 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1886 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1887 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1888
1889 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1890 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1891 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1892
1893 /* Pin level routing for AIF3 */
1894 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1895 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1896 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1897 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1898
1899 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1 Loopback" },
1900 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1901 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2 Loopback" },
1902 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1903 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1904 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1905 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1906
1907 /* DAC1 inputs */
1908 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1909 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1910 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1911 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1912 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1913
1914 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1915 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1916 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1917 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1918 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1919
1920 /* DAC2/AIF2 outputs */
1921 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1922 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1923 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1924 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1925 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1926 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1927
1928 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1929 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1930 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1931 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1932 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1933 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1934
1935 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1936 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1937 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1938 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1939
1940 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1941
1942 /* AIF3 output */
1943 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1944 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1945 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1946 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1947 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1948 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1949 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1950 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1951
1952 /* Loopback */
1953 { "AIF1 Loopback", "ADCDAT", "AIF1ADCDAT" },
1954 { "AIF1 Loopback", "None", "AIF1DACDAT" },
1955 { "AIF2 Loopback", "ADCDAT", "AIF2ADCDAT" },
1956 { "AIF2 Loopback", "None", "AIF2DACDAT" },
1957
1958 /* Sidetone */
1959 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1960 { "Left Sidetone", "DMIC2", "DMIC2L" },
1961 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1962 { "Right Sidetone", "DMIC2", "DMIC2R" },
1963
1964 /* Output stages */
1965 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1966 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1967
1968 { "SPKL", "DAC1 Switch", "DAC1L" },
1969 { "SPKL", "DAC2 Switch", "DAC2L" },
1970
1971 { "SPKR", "DAC1 Switch", "DAC1R" },
1972 { "SPKR", "DAC2 Switch", "DAC2R" },
1973
1974 { "Left Headphone Mux", "DAC", "DAC1L" },
1975 { "Right Headphone Mux", "DAC", "DAC1R" },
1976};
1977
1978static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1979 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1980 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1981 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1982 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1983 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1984 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1985 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1986 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1987};
1988
1989static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1990 { "DAC1L", NULL, "DAC1L Mixer" },
1991 { "DAC1R", NULL, "DAC1R Mixer" },
1992 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1993 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1994};
1995
1996static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1997 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1998 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1999 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
2000 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
2001 { "MICBIAS1", NULL, "CLK_SYS" },
2002 { "MICBIAS1", NULL, "MICBIAS Supply" },
2003 { "MICBIAS2", NULL, "CLK_SYS" },
2004 { "MICBIAS2", NULL, "MICBIAS Supply" },
2005};
2006
2007static const struct snd_soc_dapm_route wm8994_intercon[] = {
2008 { "AIF2DACL", NULL, "AIF2DAC Mux" },
2009 { "AIF2DACR", NULL, "AIF2DAC Mux" },
2010 { "MICBIAS1", NULL, "VMID" },
2011 { "MICBIAS2", NULL, "VMID" },
2012};
2013
2014static const struct snd_soc_dapm_route wm8958_intercon[] = {
2015 { "AIF2DACL", NULL, "AIF2DACL Mux" },
2016 { "AIF2DACR", NULL, "AIF2DACR Mux" },
2017
2018 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
2019 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
2020 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
2021 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
2022
2023 { "AIF3DACDAT", NULL, "AIF3" },
2024 { "AIF3ADCDAT", NULL, "AIF3" },
2025
2026 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
2027 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
2028
2029 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
2030};
2031
2032/* The size in bits of the FLL divide multiplied by 10
2033 * to allow rounding later */
2034#define FIXED_FLL_SIZE ((1 << 16) * 10)
2035
2036struct fll_div {
2037 u16 outdiv;
2038 u16 n;
2039 u16 k;
2040 u16 lambda;
2041 u16 clk_ref_div;
2042 u16 fll_fratio;
2043};
2044
2045static int wm8994_get_fll_config(struct wm8994 *control, struct fll_div *fll,
2046 int freq_in, int freq_out)
2047{
2048 u64 Kpart;
2049 unsigned int K, Ndiv, Nmod, gcd_fll;
2050
2051 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
2052
2053 /* Scale the input frequency down to <= 13.5MHz */
2054 fll->clk_ref_div = 0;
2055 while (freq_in > 13500000) {
2056 fll->clk_ref_div++;
2057 freq_in /= 2;
2058
2059 if (fll->clk_ref_div > 3)
2060 return -EINVAL;
2061 }
2062 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
2063
2064 /* Scale the output to give 90MHz<=Fvco<=100MHz */
2065 fll->outdiv = 3;
2066 while (freq_out * (fll->outdiv + 1) < 90000000) {
2067 fll->outdiv++;
2068 if (fll->outdiv > 63)
2069 return -EINVAL;
2070 }
2071 freq_out *= fll->outdiv + 1;
2072 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
2073
2074 if (freq_in > 1000000) {
2075 fll->fll_fratio = 0;
2076 } else if (freq_in > 256000) {
2077 fll->fll_fratio = 1;
2078 freq_in *= 2;
2079 } else if (freq_in > 128000) {
2080 fll->fll_fratio = 2;
2081 freq_in *= 4;
2082 } else if (freq_in > 64000) {
2083 fll->fll_fratio = 3;
2084 freq_in *= 8;
2085 } else {
2086 fll->fll_fratio = 4;
2087 freq_in *= 16;
2088 }
2089 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
2090
2091 /* Now, calculate N.K */
2092 Ndiv = freq_out / freq_in;
2093
2094 fll->n = Ndiv;
2095 Nmod = freq_out % freq_in;
2096 pr_debug("Nmod=%d\n", Nmod);
2097
2098 switch (control->type) {
2099 case WM8994:
2100 /* Calculate fractional part - scale up so we can round. */
2101 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
2102
2103 do_div(Kpart, freq_in);
2104
2105 K = Kpart & 0xFFFFFFFF;
2106
2107 if ((K % 10) >= 5)
2108 K += 5;
2109
2110 /* Move down to proper range now rounding is done */
2111 fll->k = K / 10;
2112 fll->lambda = 0;
2113
2114 pr_debug("N=%x K=%x\n", fll->n, fll->k);
2115 break;
2116
2117 default:
2118 gcd_fll = gcd(freq_out, freq_in);
2119
2120 fll->k = (freq_out - (freq_in * fll->n)) / gcd_fll;
2121 fll->lambda = freq_in / gcd_fll;
2122
2123 }
2124
2125 return 0;
2126}
2127
2128static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
2129 unsigned int freq_in, unsigned int freq_out)
2130{
2131 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2132 struct wm8994 *control = wm8994->wm8994;
2133 int reg_offset, ret;
2134 struct fll_div fll;
2135 u16 reg, clk1, aif_reg, aif_src;
2136 unsigned long timeout;
2137 bool was_enabled;
2138
2139 switch (id) {
2140 case WM8994_FLL1:
2141 reg_offset = 0;
2142 id = 0;
2143 aif_src = 0x10;
2144 break;
2145 case WM8994_FLL2:
2146 reg_offset = 0x20;
2147 id = 1;
2148 aif_src = 0x18;
2149 break;
2150 default:
2151 return -EINVAL;
2152 }
2153
2154 reg = snd_soc_read(codec, WM8994_FLL1_CONTROL_1 + reg_offset);
2155 was_enabled = reg & WM8994_FLL1_ENA;
2156
2157 switch (src) {
2158 case 0:
2159 /* Allow no source specification when stopping */
2160 if (freq_out)
2161 return -EINVAL;
2162 src = wm8994->fll[id].src;
2163 break;
2164 case WM8994_FLL_SRC_MCLK1:
2165 case WM8994_FLL_SRC_MCLK2:
2166 case WM8994_FLL_SRC_LRCLK:
2167 case WM8994_FLL_SRC_BCLK:
2168 break;
2169 case WM8994_FLL_SRC_INTERNAL:
2170 freq_in = 12000000;
2171 freq_out = 12000000;
2172 break;
2173 default:
2174 return -EINVAL;
2175 }
2176
2177 /* Are we changing anything? */
2178 if (wm8994->fll[id].src == src &&
2179 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
2180 return 0;
2181
2182 /* If we're stopping the FLL redo the old config - no
2183 * registers will actually be written but we avoid GCC flow
2184 * analysis bugs spewing warnings.
2185 */
2186 if (freq_out)
2187 ret = wm8994_get_fll_config(control, &fll, freq_in, freq_out);
2188 else
2189 ret = wm8994_get_fll_config(control, &fll, wm8994->fll[id].in,
2190 wm8994->fll[id].out);
2191 if (ret < 0)
2192 return ret;
2193
2194 /* Make sure that we're not providing SYSCLK right now */
2195 clk1 = snd_soc_read(codec, WM8994_CLOCKING_1);
2196 if (clk1 & WM8994_SYSCLK_SRC)
2197 aif_reg = WM8994_AIF2_CLOCKING_1;
2198 else
2199 aif_reg = WM8994_AIF1_CLOCKING_1;
2200 reg = snd_soc_read(codec, aif_reg);
2201
2202 if ((reg & WM8994_AIF1CLK_ENA) &&
2203 (reg & WM8994_AIF1CLK_SRC_MASK) == aif_src) {
2204 dev_err(codec->dev, "FLL%d is currently providing SYSCLK\n",
2205 id + 1);
2206 return -EBUSY;
2207 }
2208
2209 /* We always need to disable the FLL while reconfiguring */
2210 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2211 WM8994_FLL1_ENA, 0);
2212
2213 if (wm8994->fll_byp && src == WM8994_FLL_SRC_BCLK &&
2214 freq_in == freq_out && freq_out) {
2215 dev_dbg(codec->dev, "Bypassing FLL%d\n", id + 1);
2216 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2217 WM8958_FLL1_BYP, WM8958_FLL1_BYP);
2218 goto out;
2219 }
2220
2221 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
2222 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
2223 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
2224 WM8994_FLL1_OUTDIV_MASK |
2225 WM8994_FLL1_FRATIO_MASK, reg);
2226
2227 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_3 + reg_offset,
2228 WM8994_FLL1_K_MASK, fll.k);
2229
2230 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
2231 WM8994_FLL1_N_MASK,
2232 fll.n << WM8994_FLL1_N_SHIFT);
2233
2234 if (fll.lambda) {
2235 snd_soc_update_bits(codec, WM8958_FLL1_EFS_1 + reg_offset,
2236 WM8958_FLL1_LAMBDA_MASK,
2237 fll.lambda);
2238 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2239 WM8958_FLL1_EFS_ENA, WM8958_FLL1_EFS_ENA);
2240 } else {
2241 snd_soc_update_bits(codec, WM8958_FLL1_EFS_2 + reg_offset,
2242 WM8958_FLL1_EFS_ENA, 0);
2243 }
2244
2245 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
2246 WM8994_FLL1_FRC_NCO | WM8958_FLL1_BYP |
2247 WM8994_FLL1_REFCLK_DIV_MASK |
2248 WM8994_FLL1_REFCLK_SRC_MASK,
2249 ((src == WM8994_FLL_SRC_INTERNAL)
2250 << WM8994_FLL1_FRC_NCO_SHIFT) |
2251 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
2252 (src - 1));
2253
2254 /* Clear any pending completion from a previous failure */
2255 try_wait_for_completion(&wm8994->fll_locked[id]);
2256
2257 /* Enable (with fractional mode if required) */
2258 if (freq_out) {
2259 /* Enable VMID if we need it */
2260 if (!was_enabled) {
2261 active_reference(codec);
2262
2263 switch (control->type) {
2264 case WM8994:
2265 vmid_reference(codec);
2266 break;
2267 case WM8958:
2268 if (control->revision < 1)
2269 vmid_reference(codec);
2270 break;
2271 default:
2272 break;
2273 }
2274 }
2275
2276 reg = WM8994_FLL1_ENA;
2277
2278 if (fll.k)
2279 reg |= WM8994_FLL1_FRAC;
2280 if (src == WM8994_FLL_SRC_INTERNAL)
2281 reg |= WM8994_FLL1_OSC_ENA;
2282
2283 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
2284 WM8994_FLL1_ENA | WM8994_FLL1_OSC_ENA |
2285 WM8994_FLL1_FRAC, reg);
2286
2287 if (wm8994->fll_locked_irq) {
2288 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
2289 msecs_to_jiffies(10));
2290 if (timeout == 0)
2291 dev_warn(codec->dev,
2292 "Timed out waiting for FLL lock\n");
2293 } else {
2294 msleep(5);
2295 }
2296 } else {
2297 if (was_enabled) {
2298 switch (control->type) {
2299 case WM8994:
2300 vmid_dereference(codec);
2301 break;
2302 case WM8958:
2303 if (control->revision < 1)
2304 vmid_dereference(codec);
2305 break;
2306 default:
2307 break;
2308 }
2309
2310 active_dereference(codec);
2311 }
2312 }
2313
2314out:
2315 wm8994->fll[id].in = freq_in;
2316 wm8994->fll[id].out = freq_out;
2317 wm8994->fll[id].src = src;
2318
2319 configure_clock(codec);
2320
2321 /*
2322 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2323 * for detection.
2324 */
2325 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2326 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2327
2328 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2329 & WM8994_AIF1CLK_RATE_MASK;
2330 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2331 & WM8994_AIF1CLK_RATE_MASK;
2332
2333 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2334 WM8994_AIF1CLK_RATE_MASK, 0x1);
2335 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2336 WM8994_AIF2CLK_RATE_MASK, 0x1);
2337 } else if (wm8994->aifdiv[0]) {
2338 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2339 WM8994_AIF1CLK_RATE_MASK,
2340 wm8994->aifdiv[0]);
2341 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2342 WM8994_AIF2CLK_RATE_MASK,
2343 wm8994->aifdiv[1]);
2344
2345 wm8994->aifdiv[0] = 0;
2346 wm8994->aifdiv[1] = 0;
2347 }
2348
2349 return 0;
2350}
2351
2352static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
2353{
2354 struct completion *completion = data;
2355
2356 complete(completion);
2357
2358 return IRQ_HANDLED;
2359}
2360
2361static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
2362
2363static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
2364 unsigned int freq_in, unsigned int freq_out)
2365{
2366 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
2367}
2368
2369static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
2370 int clk_id, unsigned int freq, int dir)
2371{
2372 struct snd_soc_codec *codec = dai->codec;
2373 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2374 int i;
2375
2376 switch (dai->id) {
2377 case 1:
2378 case 2:
2379 break;
2380
2381 default:
2382 /* AIF3 shares clocking with AIF1/2 */
2383 return -EINVAL;
2384 }
2385
2386 switch (clk_id) {
2387 case WM8994_SYSCLK_MCLK1:
2388 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
2389 wm8994->mclk[0] = freq;
2390 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
2391 dai->id, freq);
2392 break;
2393
2394 case WM8994_SYSCLK_MCLK2:
2395 /* TODO: Set GPIO AF */
2396 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
2397 wm8994->mclk[1] = freq;
2398 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
2399 dai->id, freq);
2400 break;
2401
2402 case WM8994_SYSCLK_FLL1:
2403 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
2404 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
2405 break;
2406
2407 case WM8994_SYSCLK_FLL2:
2408 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
2409 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
2410 break;
2411
2412 case WM8994_SYSCLK_OPCLK:
2413 /* Special case - a division (times 10) is given and
2414 * no effect on main clocking.
2415 */
2416 if (freq) {
2417 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
2418 if (opclk_divs[i] == freq)
2419 break;
2420 if (i == ARRAY_SIZE(opclk_divs))
2421 return -EINVAL;
2422 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
2423 WM8994_OPCLK_DIV_MASK, i);
2424 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2425 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
2426 } else {
2427 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
2428 WM8994_OPCLK_ENA, 0);
2429 }
2430
2431 default:
2432 return -EINVAL;
2433 }
2434
2435 configure_clock(codec);
2436
2437 /*
2438 * If SYSCLK will be less than 50kHz adjust AIFnCLK dividers
2439 * for detection.
2440 */
2441 if (max(wm8994->aifclk[0], wm8994->aifclk[1]) < 50000) {
2442 dev_dbg(codec->dev, "Configuring AIFs for 128fs\n");
2443
2444 wm8994->aifdiv[0] = snd_soc_read(codec, WM8994_AIF1_RATE)
2445 & WM8994_AIF1CLK_RATE_MASK;
2446 wm8994->aifdiv[1] = snd_soc_read(codec, WM8994_AIF2_RATE)
2447 & WM8994_AIF1CLK_RATE_MASK;
2448
2449 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2450 WM8994_AIF1CLK_RATE_MASK, 0x1);
2451 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2452 WM8994_AIF2CLK_RATE_MASK, 0x1);
2453 } else if (wm8994->aifdiv[0]) {
2454 snd_soc_update_bits(codec, WM8994_AIF1_RATE,
2455 WM8994_AIF1CLK_RATE_MASK,
2456 wm8994->aifdiv[0]);
2457 snd_soc_update_bits(codec, WM8994_AIF2_RATE,
2458 WM8994_AIF2CLK_RATE_MASK,
2459 wm8994->aifdiv[1]);
2460
2461 wm8994->aifdiv[0] = 0;
2462 wm8994->aifdiv[1] = 0;
2463 }
2464
2465 return 0;
2466}
2467
2468static int wm8994_set_bias_level(struct snd_soc_codec *codec,
2469 enum snd_soc_bias_level level)
2470{
2471 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2472 struct wm8994 *control = wm8994->wm8994;
2473
2474 wm_hubs_set_bias_level(codec, level);
2475
2476 switch (level) {
2477 case SND_SOC_BIAS_ON:
2478 break;
2479
2480 case SND_SOC_BIAS_PREPARE:
2481 /* MICBIAS into regulating mode */
2482 switch (control->type) {
2483 case WM8958:
2484 case WM1811:
2485 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2486 WM8958_MICB1_MODE, 0);
2487 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2488 WM8958_MICB2_MODE, 0);
2489 break;
2490 default:
2491 break;
2492 }
2493
2494 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2495 active_reference(codec);
2496 break;
2497
2498 case SND_SOC_BIAS_STANDBY:
2499 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
2500 switch (control->type) {
2501 case WM8958:
2502 if (control->revision == 0) {
2503 /* Optimise performance for rev A */
2504 snd_soc_update_bits(codec,
2505 WM8958_CHARGE_PUMP_2,
2506 WM8958_CP_DISCH,
2507 WM8958_CP_DISCH);
2508 }
2509 break;
2510
2511 default:
2512 break;
2513 }
2514
2515 /* Discharge LINEOUT1 & 2 */
2516 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
2517 WM8994_LINEOUT1_DISCH |
2518 WM8994_LINEOUT2_DISCH,
2519 WM8994_LINEOUT1_DISCH |
2520 WM8994_LINEOUT2_DISCH);
2521 }
2522
2523 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
2524 active_dereference(codec);
2525
2526 /* MICBIAS into bypass mode on newer devices */
2527 switch (control->type) {
2528 case WM8958:
2529 case WM1811:
2530 snd_soc_update_bits(codec, WM8958_MICBIAS1,
2531 WM8958_MICB1_MODE,
2532 WM8958_MICB1_MODE);
2533 snd_soc_update_bits(codec, WM8958_MICBIAS2,
2534 WM8958_MICB2_MODE,
2535 WM8958_MICB2_MODE);
2536 break;
2537 default:
2538 break;
2539 }
2540 break;
2541
2542 case SND_SOC_BIAS_OFF:
2543 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY)
2544 wm8994->cur_fw = NULL;
2545 break;
2546 }
2547
2548 codec->dapm.bias_level = level;
2549
2550 return 0;
2551}
2552
2553int wm8994_vmid_mode(struct snd_soc_codec *codec, enum wm8994_vmid_mode mode)
2554{
2555 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2556 struct snd_soc_dapm_context *dapm = &codec->dapm;
2557
2558 switch (mode) {
2559 case WM8994_VMID_NORMAL:
2560 snd_soc_dapm_mutex_lock(dapm);
2561
2562 if (wm8994->hubs.lineout1_se) {
2563 snd_soc_dapm_disable_pin_unlocked(dapm,
2564 "LINEOUT1N Driver");
2565 snd_soc_dapm_disable_pin_unlocked(dapm,
2566 "LINEOUT1P Driver");
2567 }
2568 if (wm8994->hubs.lineout2_se) {
2569 snd_soc_dapm_disable_pin_unlocked(dapm,
2570 "LINEOUT2N Driver");
2571 snd_soc_dapm_disable_pin_unlocked(dapm,
2572 "LINEOUT2P Driver");
2573 }
2574
2575 /* Do the sync with the old mode to allow it to clean up */
2576 snd_soc_dapm_sync_unlocked(dapm);
2577 wm8994->vmid_mode = mode;
2578
2579 snd_soc_dapm_mutex_unlock(dapm);
2580 break;
2581
2582 case WM8994_VMID_FORCE:
2583 snd_soc_dapm_mutex_lock(dapm);
2584
2585 if (wm8994->hubs.lineout1_se) {
2586 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2587 "LINEOUT1N Driver");
2588 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2589 "LINEOUT1P Driver");
2590 }
2591 if (wm8994->hubs.lineout2_se) {
2592 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2593 "LINEOUT2N Driver");
2594 snd_soc_dapm_force_enable_pin_unlocked(dapm,
2595 "LINEOUT2P Driver");
2596 }
2597
2598 wm8994->vmid_mode = mode;
2599 snd_soc_dapm_sync_unlocked(dapm);
2600
2601 snd_soc_dapm_mutex_unlock(dapm);
2602 break;
2603
2604 default:
2605 return -EINVAL;
2606 }
2607
2608 return 0;
2609}
2610
2611static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2612{
2613 struct snd_soc_codec *codec = dai->codec;
2614 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2615 struct wm8994 *control = wm8994->wm8994;
2616 int ms_reg;
2617 int aif1_reg;
2618 int dac_reg;
2619 int adc_reg;
2620 int ms = 0;
2621 int aif1 = 0;
2622 int lrclk = 0;
2623
2624 switch (dai->id) {
2625 case 1:
2626 ms_reg = WM8994_AIF1_MASTER_SLAVE;
2627 aif1_reg = WM8994_AIF1_CONTROL_1;
2628 dac_reg = WM8994_AIF1DAC_LRCLK;
2629 adc_reg = WM8994_AIF1ADC_LRCLK;
2630 break;
2631 case 2:
2632 ms_reg = WM8994_AIF2_MASTER_SLAVE;
2633 aif1_reg = WM8994_AIF2_CONTROL_1;
2634 dac_reg = WM8994_AIF1DAC_LRCLK;
2635 adc_reg = WM8994_AIF1ADC_LRCLK;
2636 break;
2637 default:
2638 return -EINVAL;
2639 }
2640
2641 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2642 case SND_SOC_DAIFMT_CBS_CFS:
2643 break;
2644 case SND_SOC_DAIFMT_CBM_CFM:
2645 ms = WM8994_AIF1_MSTR;
2646 break;
2647 default:
2648 return -EINVAL;
2649 }
2650
2651 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2652 case SND_SOC_DAIFMT_DSP_B:
2653 aif1 |= WM8994_AIF1_LRCLK_INV;
2654 lrclk |= WM8958_AIF1_LRCLK_INV;
2655 case SND_SOC_DAIFMT_DSP_A:
2656 aif1 |= 0x18;
2657 break;
2658 case SND_SOC_DAIFMT_I2S:
2659 aif1 |= 0x10;
2660 break;
2661 case SND_SOC_DAIFMT_RIGHT_J:
2662 break;
2663 case SND_SOC_DAIFMT_LEFT_J:
2664 aif1 |= 0x8;
2665 break;
2666 default:
2667 return -EINVAL;
2668 }
2669
2670 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2671 case SND_SOC_DAIFMT_DSP_A:
2672 case SND_SOC_DAIFMT_DSP_B:
2673 /* frame inversion not valid for DSP modes */
2674 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2675 case SND_SOC_DAIFMT_NB_NF:
2676 break;
2677 case SND_SOC_DAIFMT_IB_NF:
2678 aif1 |= WM8994_AIF1_BCLK_INV;
2679 break;
2680 default:
2681 return -EINVAL;
2682 }
2683 break;
2684
2685 case SND_SOC_DAIFMT_I2S:
2686 case SND_SOC_DAIFMT_RIGHT_J:
2687 case SND_SOC_DAIFMT_LEFT_J:
2688 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2689 case SND_SOC_DAIFMT_NB_NF:
2690 break;
2691 case SND_SOC_DAIFMT_IB_IF:
2692 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2693 lrclk |= WM8958_AIF1_LRCLK_INV;
2694 break;
2695 case SND_SOC_DAIFMT_IB_NF:
2696 aif1 |= WM8994_AIF1_BCLK_INV;
2697 break;
2698 case SND_SOC_DAIFMT_NB_IF:
2699 aif1 |= WM8994_AIF1_LRCLK_INV;
2700 lrclk |= WM8958_AIF1_LRCLK_INV;
2701 break;
2702 default:
2703 return -EINVAL;
2704 }
2705 break;
2706 default:
2707 return -EINVAL;
2708 }
2709
2710 /* The AIF2 format configuration needs to be mirrored to AIF3
2711 * on WM8958 if it's in use so just do it all the time. */
2712 switch (control->type) {
2713 case WM1811:
2714 case WM8958:
2715 if (dai->id == 2)
2716 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2717 WM8994_AIF1_LRCLK_INV |
2718 WM8958_AIF3_FMT_MASK, aif1);
2719 break;
2720
2721 default:
2722 break;
2723 }
2724
2725 snd_soc_update_bits(codec, aif1_reg,
2726 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2727 WM8994_AIF1_FMT_MASK,
2728 aif1);
2729 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2730 ms);
2731 snd_soc_update_bits(codec, dac_reg,
2732 WM8958_AIF1_LRCLK_INV, lrclk);
2733 snd_soc_update_bits(codec, adc_reg,
2734 WM8958_AIF1_LRCLK_INV, lrclk);
2735
2736 return 0;
2737}
2738
2739static struct {
2740 int val, rate;
2741} srs[] = {
2742 { 0, 8000 },
2743 { 1, 11025 },
2744 { 2, 12000 },
2745 { 3, 16000 },
2746 { 4, 22050 },
2747 { 5, 24000 },
2748 { 6, 32000 },
2749 { 7, 44100 },
2750 { 8, 48000 },
2751 { 9, 88200 },
2752 { 10, 96000 },
2753};
2754
2755static int fs_ratios[] = {
2756 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2757};
2758
2759static int bclk_divs[] = {
2760 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2761 640, 880, 960, 1280, 1760, 1920
2762};
2763
2764static int wm8994_hw_params(struct snd_pcm_substream *substream,
2765 struct snd_pcm_hw_params *params,
2766 struct snd_soc_dai *dai)
2767{
2768 struct snd_soc_codec *codec = dai->codec;
2769 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2770 struct wm8994 *control = wm8994->wm8994;
2771 struct wm8994_pdata *pdata = &control->pdata;
2772 int aif1_reg;
2773 int aif2_reg;
2774 int bclk_reg;
2775 int lrclk_reg;
2776 int rate_reg;
2777 int aif1 = 0;
2778 int aif2 = 0;
2779 int bclk = 0;
2780 int lrclk = 0;
2781 int rate_val = 0;
2782 int id = dai->id - 1;
2783
2784 int i, cur_val, best_val, bclk_rate, best;
2785
2786 switch (dai->id) {
2787 case 1:
2788 aif1_reg = WM8994_AIF1_CONTROL_1;
2789 aif2_reg = WM8994_AIF1_CONTROL_2;
2790 bclk_reg = WM8994_AIF1_BCLK;
2791 rate_reg = WM8994_AIF1_RATE;
2792 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2793 wm8994->lrclk_shared[0]) {
2794 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2795 } else {
2796 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2797 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2798 }
2799 break;
2800 case 2:
2801 aif1_reg = WM8994_AIF2_CONTROL_1;
2802 aif2_reg = WM8994_AIF2_CONTROL_2;
2803 bclk_reg = WM8994_AIF2_BCLK;
2804 rate_reg = WM8994_AIF2_RATE;
2805 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2806 wm8994->lrclk_shared[1]) {
2807 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2808 } else {
2809 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2810 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2811 }
2812 break;
2813 default:
2814 return -EINVAL;
2815 }
2816
2817 bclk_rate = params_rate(params);
2818 switch (params_format(params)) {
2819 case SNDRV_PCM_FORMAT_S16_LE:
2820 bclk_rate *= 16;
2821 break;
2822 case SNDRV_PCM_FORMAT_S20_3LE:
2823 bclk_rate *= 20;
2824 aif1 |= 0x20;
2825 break;
2826 case SNDRV_PCM_FORMAT_S24_LE:
2827 bclk_rate *= 24;
2828 aif1 |= 0x40;
2829 break;
2830 case SNDRV_PCM_FORMAT_S32_LE:
2831 bclk_rate *= 32;
2832 aif1 |= 0x60;
2833 break;
2834 default:
2835 return -EINVAL;
2836 }
2837
2838 wm8994->channels[id] = params_channels(params);
2839 if (pdata->max_channels_clocked[id] &&
2840 wm8994->channels[id] > pdata->max_channels_clocked[id]) {
2841 dev_dbg(dai->dev, "Constraining channels to %d from %d\n",
2842 pdata->max_channels_clocked[id], wm8994->channels[id]);
2843 wm8994->channels[id] = pdata->max_channels_clocked[id];
2844 }
2845
2846 switch (wm8994->channels[id]) {
2847 case 1:
2848 case 2:
2849 bclk_rate *= 2;
2850 break;
2851 default:
2852 bclk_rate *= 4;
2853 break;
2854 }
2855
2856 /* Try to find an appropriate sample rate; look for an exact match. */
2857 for (i = 0; i < ARRAY_SIZE(srs); i++)
2858 if (srs[i].rate == params_rate(params))
2859 break;
2860 if (i == ARRAY_SIZE(srs))
2861 return -EINVAL;
2862 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2863
2864 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2865 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2866 dai->id, wm8994->aifclk[id], bclk_rate);
2867
2868 if (wm8994->channels[id] == 1 &&
2869 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2870 aif2 |= WM8994_AIF1_MONO;
2871
2872 if (wm8994->aifclk[id] == 0) {
2873 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2874 return -EINVAL;
2875 }
2876
2877 /* AIFCLK/fs ratio; look for a close match in either direction */
2878 best = 0;
2879 best_val = abs((fs_ratios[0] * params_rate(params))
2880 - wm8994->aifclk[id]);
2881 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2882 cur_val = abs((fs_ratios[i] * params_rate(params))
2883 - wm8994->aifclk[id]);
2884 if (cur_val >= best_val)
2885 continue;
2886 best = i;
2887 best_val = cur_val;
2888 }
2889 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2890 dai->id, fs_ratios[best]);
2891 rate_val |= best;
2892
2893 /* We may not get quite the right frequency if using
2894 * approximate clocks so look for the closest match that is
2895 * higher than the target (we need to ensure that there enough
2896 * BCLKs to clock out the samples).
2897 */
2898 best = 0;
2899 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2900 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2901 if (cur_val < 0) /* BCLK table is sorted */
2902 break;
2903 best = i;
2904 }
2905 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2906 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2907 bclk_divs[best], bclk_rate);
2908 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2909
2910 lrclk = bclk_rate / params_rate(params);
2911 if (!lrclk) {
2912 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n",
2913 bclk_rate);
2914 return -EINVAL;
2915 }
2916 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2917 lrclk, bclk_rate / lrclk);
2918
2919 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2920 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2921 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2922 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2923 lrclk);
2924 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2925 WM8994_AIF1CLK_RATE_MASK, rate_val);
2926
2927 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2928 switch (dai->id) {
2929 case 1:
2930 wm8994->dac_rates[0] = params_rate(params);
2931 wm8994_set_retune_mobile(codec, 0);
2932 wm8994_set_retune_mobile(codec, 1);
2933 break;
2934 case 2:
2935 wm8994->dac_rates[1] = params_rate(params);
2936 wm8994_set_retune_mobile(codec, 2);
2937 break;
2938 }
2939 }
2940
2941 return 0;
2942}
2943
2944static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2945 struct snd_pcm_hw_params *params,
2946 struct snd_soc_dai *dai)
2947{
2948 struct snd_soc_codec *codec = dai->codec;
2949 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2950 struct wm8994 *control = wm8994->wm8994;
2951 int aif1_reg;
2952 int aif1 = 0;
2953
2954 switch (dai->id) {
2955 case 3:
2956 switch (control->type) {
2957 case WM1811:
2958 case WM8958:
2959 aif1_reg = WM8958_AIF3_CONTROL_1;
2960 break;
2961 default:
2962 return 0;
2963 }
2964 break;
2965 default:
2966 return 0;
2967 }
2968
2969 switch (params_format(params)) {
2970 case SNDRV_PCM_FORMAT_S16_LE:
2971 break;
2972 case SNDRV_PCM_FORMAT_S20_3LE:
2973 aif1 |= 0x20;
2974 break;
2975 case SNDRV_PCM_FORMAT_S24_LE:
2976 aif1 |= 0x40;
2977 break;
2978 case SNDRV_PCM_FORMAT_S32_LE:
2979 aif1 |= 0x60;
2980 break;
2981 default:
2982 return -EINVAL;
2983 }
2984
2985 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2986}
2987
2988static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2989{
2990 struct snd_soc_codec *codec = codec_dai->codec;
2991 int mute_reg;
2992 int reg;
2993
2994 switch (codec_dai->id) {
2995 case 1:
2996 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2997 break;
2998 case 2:
2999 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
3000 break;
3001 default:
3002 return -EINVAL;
3003 }
3004
3005 if (mute)
3006 reg = WM8994_AIF1DAC1_MUTE;
3007 else
3008 reg = 0;
3009
3010 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
3011
3012 return 0;
3013}
3014
3015static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
3016{
3017 struct snd_soc_codec *codec = codec_dai->codec;
3018 int reg, val, mask;
3019
3020 switch (codec_dai->id) {
3021 case 1:
3022 reg = WM8994_AIF1_MASTER_SLAVE;
3023 mask = WM8994_AIF1_TRI;
3024 break;
3025 case 2:
3026 reg = WM8994_AIF2_MASTER_SLAVE;
3027 mask = WM8994_AIF2_TRI;
3028 break;
3029 default:
3030 return -EINVAL;
3031 }
3032
3033 if (tristate)
3034 val = mask;
3035 else
3036 val = 0;
3037
3038 return snd_soc_update_bits(codec, reg, mask, val);
3039}
3040
3041static int wm8994_aif2_probe(struct snd_soc_dai *dai)
3042{
3043 struct snd_soc_codec *codec = dai->codec;
3044
3045 /* Disable the pulls on the AIF if we're using it to save power. */
3046 snd_soc_update_bits(codec, WM8994_GPIO_3,
3047 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3048 snd_soc_update_bits(codec, WM8994_GPIO_4,
3049 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3050 snd_soc_update_bits(codec, WM8994_GPIO_5,
3051 WM8994_GPN_PU | WM8994_GPN_PD, 0);
3052
3053 return 0;
3054}
3055
3056#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
3057
3058#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
3059 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
3060
3061static const struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
3062 .set_sysclk = wm8994_set_dai_sysclk,
3063 .set_fmt = wm8994_set_dai_fmt,
3064 .hw_params = wm8994_hw_params,
3065 .digital_mute = wm8994_aif_mute,
3066 .set_pll = wm8994_set_fll,
3067 .set_tristate = wm8994_set_tristate,
3068};
3069
3070static const struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
3071 .set_sysclk = wm8994_set_dai_sysclk,
3072 .set_fmt = wm8994_set_dai_fmt,
3073 .hw_params = wm8994_hw_params,
3074 .digital_mute = wm8994_aif_mute,
3075 .set_pll = wm8994_set_fll,
3076 .set_tristate = wm8994_set_tristate,
3077};
3078
3079static const struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
3080 .hw_params = wm8994_aif3_hw_params,
3081};
3082
3083static struct snd_soc_dai_driver wm8994_dai[] = {
3084 {
3085 .name = "wm8994-aif1",
3086 .id = 1,
3087 .playback = {
3088 .stream_name = "AIF1 Playback",
3089 .channels_min = 1,
3090 .channels_max = 2,
3091 .rates = WM8994_RATES,
3092 .formats = WM8994_FORMATS,
3093 .sig_bits = 24,
3094 },
3095 .capture = {
3096 .stream_name = "AIF1 Capture",
3097 .channels_min = 1,
3098 .channels_max = 2,
3099 .rates = WM8994_RATES,
3100 .formats = WM8994_FORMATS,
3101 .sig_bits = 24,
3102 },
3103 .ops = &wm8994_aif1_dai_ops,
3104 },
3105 {
3106 .name = "wm8994-aif2",
3107 .id = 2,
3108 .playback = {
3109 .stream_name = "AIF2 Playback",
3110 .channels_min = 1,
3111 .channels_max = 2,
3112 .rates = WM8994_RATES,
3113 .formats = WM8994_FORMATS,
3114 .sig_bits = 24,
3115 },
3116 .capture = {
3117 .stream_name = "AIF2 Capture",
3118 .channels_min = 1,
3119 .channels_max = 2,
3120 .rates = WM8994_RATES,
3121 .formats = WM8994_FORMATS,
3122 .sig_bits = 24,
3123 },
3124 .probe = wm8994_aif2_probe,
3125 .ops = &wm8994_aif2_dai_ops,
3126 },
3127 {
3128 .name = "wm8994-aif3",
3129 .id = 3,
3130 .playback = {
3131 .stream_name = "AIF3 Playback",
3132 .channels_min = 1,
3133 .channels_max = 2,
3134 .rates = WM8994_RATES,
3135 .formats = WM8994_FORMATS,
3136 .sig_bits = 24,
3137 },
3138 .capture = {
3139 .stream_name = "AIF3 Capture",
3140 .channels_min = 1,
3141 .channels_max = 2,
3142 .rates = WM8994_RATES,
3143 .formats = WM8994_FORMATS,
3144 .sig_bits = 24,
3145 },
3146 .ops = &wm8994_aif3_dai_ops,
3147 }
3148};
3149
3150#ifdef CONFIG_PM
3151static int wm8994_codec_suspend(struct snd_soc_codec *codec)
3152{
3153 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3154 int i, ret;
3155
3156 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3157 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
3158 sizeof(struct wm8994_fll_config));
3159 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
3160 if (ret < 0)
3161 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
3162 i + 1, ret);
3163 }
3164
3165 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3166
3167 return 0;
3168}
3169
3170static int wm8994_codec_resume(struct snd_soc_codec *codec)
3171{
3172 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3173 int i, ret;
3174
3175 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
3176 if (!wm8994->fll_suspend[i].out)
3177 continue;
3178
3179 ret = _wm8994_set_fll(codec, i + 1,
3180 wm8994->fll_suspend[i].src,
3181 wm8994->fll_suspend[i].in,
3182 wm8994->fll_suspend[i].out);
3183 if (ret < 0)
3184 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
3185 i + 1, ret);
3186 }
3187
3188 return 0;
3189}
3190#else
3191#define wm8994_codec_suspend NULL
3192#define wm8994_codec_resume NULL
3193#endif
3194
3195static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
3196{
3197 struct snd_soc_codec *codec = wm8994->hubs.codec;
3198 struct wm8994 *control = wm8994->wm8994;
3199 struct wm8994_pdata *pdata = &control->pdata;
3200 struct snd_kcontrol_new controls[] = {
3201 SOC_ENUM_EXT("AIF1.1 EQ Mode",
3202 wm8994->retune_mobile_enum,
3203 wm8994_get_retune_mobile_enum,
3204 wm8994_put_retune_mobile_enum),
3205 SOC_ENUM_EXT("AIF1.2 EQ Mode",
3206 wm8994->retune_mobile_enum,
3207 wm8994_get_retune_mobile_enum,
3208 wm8994_put_retune_mobile_enum),
3209 SOC_ENUM_EXT("AIF2 EQ Mode",
3210 wm8994->retune_mobile_enum,
3211 wm8994_get_retune_mobile_enum,
3212 wm8994_put_retune_mobile_enum),
3213 };
3214 int ret, i, j;
3215 const char **t;
3216
3217 /* We need an array of texts for the enum API but the number
3218 * of texts is likely to be less than the number of
3219 * configurations due to the sample rate dependency of the
3220 * configurations. */
3221 wm8994->num_retune_mobile_texts = 0;
3222 wm8994->retune_mobile_texts = NULL;
3223 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
3224 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
3225 if (strcmp(pdata->retune_mobile_cfgs[i].name,
3226 wm8994->retune_mobile_texts[j]) == 0)
3227 break;
3228 }
3229
3230 if (j != wm8994->num_retune_mobile_texts)
3231 continue;
3232
3233 /* Expand the array... */
3234 t = krealloc(wm8994->retune_mobile_texts,
3235 sizeof(char *) *
3236 (wm8994->num_retune_mobile_texts + 1),
3237 GFP_KERNEL);
3238 if (t == NULL)
3239 continue;
3240
3241 /* ...store the new entry... */
3242 t[wm8994->num_retune_mobile_texts] =
3243 pdata->retune_mobile_cfgs[i].name;
3244
3245 /* ...and remember the new version. */
3246 wm8994->num_retune_mobile_texts++;
3247 wm8994->retune_mobile_texts = t;
3248 }
3249
3250 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
3251 wm8994->num_retune_mobile_texts);
3252
3253 wm8994->retune_mobile_enum.items = wm8994->num_retune_mobile_texts;
3254 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
3255
3256 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3257 ARRAY_SIZE(controls));
3258 if (ret != 0)
3259 dev_err(wm8994->hubs.codec->dev,
3260 "Failed to add ReTune Mobile controls: %d\n", ret);
3261}
3262
3263static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
3264{
3265 struct snd_soc_codec *codec = wm8994->hubs.codec;
3266 struct wm8994 *control = wm8994->wm8994;
3267 struct wm8994_pdata *pdata = &control->pdata;
3268 int ret, i;
3269
3270 if (!pdata)
3271 return;
3272
3273 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
3274 pdata->lineout2_diff,
3275 pdata->lineout1fb,
3276 pdata->lineout2fb,
3277 pdata->jd_scthr,
3278 pdata->jd_thr,
3279 pdata->micb1_delay,
3280 pdata->micb2_delay,
3281 pdata->micbias1_lvl,
3282 pdata->micbias2_lvl);
3283
3284 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
3285
3286 if (pdata->num_drc_cfgs) {
3287 struct snd_kcontrol_new controls[] = {
3288 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
3289 wm8994_get_drc_enum, wm8994_put_drc_enum),
3290 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
3291 wm8994_get_drc_enum, wm8994_put_drc_enum),
3292 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
3293 wm8994_get_drc_enum, wm8994_put_drc_enum),
3294 };
3295
3296 /* We need an array of texts for the enum API */
3297 wm8994->drc_texts = devm_kzalloc(wm8994->hubs.codec->dev,
3298 sizeof(char *) * pdata->num_drc_cfgs, GFP_KERNEL);
3299 if (!wm8994->drc_texts) {
3300 dev_err(wm8994->hubs.codec->dev,
3301 "Failed to allocate %d DRC config texts\n",
3302 pdata->num_drc_cfgs);
3303 return;
3304 }
3305
3306 for (i = 0; i < pdata->num_drc_cfgs; i++)
3307 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
3308
3309 wm8994->drc_enum.items = pdata->num_drc_cfgs;
3310 wm8994->drc_enum.texts = wm8994->drc_texts;
3311
3312 ret = snd_soc_add_codec_controls(wm8994->hubs.codec, controls,
3313 ARRAY_SIZE(controls));
3314 for (i = 0; i < WM8994_NUM_DRC; i++)
3315 wm8994_set_drc(codec, i);
3316 } else {
3317 ret = snd_soc_add_codec_controls(wm8994->hubs.codec,
3318 wm8994_drc_controls,
3319 ARRAY_SIZE(wm8994_drc_controls));
3320 }
3321
3322 if (ret != 0)
3323 dev_err(wm8994->hubs.codec->dev,
3324 "Failed to add DRC mode controls: %d\n", ret);
3325
3326
3327 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
3328 pdata->num_retune_mobile_cfgs);
3329
3330 if (pdata->num_retune_mobile_cfgs)
3331 wm8994_handle_retune_mobile_pdata(wm8994);
3332 else
3333 snd_soc_add_codec_controls(wm8994->hubs.codec, wm8994_eq_controls,
3334 ARRAY_SIZE(wm8994_eq_controls));
3335
3336 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
3337 if (pdata->micbias[i]) {
3338 snd_soc_write(codec, WM8958_MICBIAS1 + i,
3339 pdata->micbias[i] & 0xffff);
3340 }
3341 }
3342}
3343
3344/**
3345 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
3346 *
3347 * @codec: WM8994 codec
3348 * @jack: jack to report detection events on
3349 * @micbias: microphone bias to detect on
3350 *
3351 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
3352 * being used to bring out signals to the processor then only platform
3353 * data configuration is needed for WM8994 and processor GPIOs should
3354 * be configured using snd_soc_jack_add_gpios() instead.
3355 *
3356 * Configuration of detection levels is available via the micbias1_lvl
3357 * and micbias2_lvl platform data members.
3358 */
3359int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3360 int micbias)
3361{
3362 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3363 struct wm8994_micdet *micdet;
3364 struct wm8994 *control = wm8994->wm8994;
3365 int reg, ret;
3366
3367 if (control->type != WM8994) {
3368 dev_warn(codec->dev, "Not a WM8994\n");
3369 return -EINVAL;
3370 }
3371
3372 switch (micbias) {
3373 case 1:
3374 micdet = &wm8994->micdet[0];
3375 if (jack)
3376 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3377 "MICBIAS1");
3378 else
3379 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3380 "MICBIAS1");
3381 break;
3382 case 2:
3383 micdet = &wm8994->micdet[1];
3384 if (jack)
3385 ret = snd_soc_dapm_force_enable_pin(&codec->dapm,
3386 "MICBIAS1");
3387 else
3388 ret = snd_soc_dapm_disable_pin(&codec->dapm,
3389 "MICBIAS1");
3390 break;
3391 default:
3392 dev_warn(codec->dev, "Invalid MICBIAS %d\n", micbias);
3393 return -EINVAL;
3394 }
3395
3396 if (ret != 0)
3397 dev_warn(codec->dev, "Failed to configure MICBIAS%d: %d\n",
3398 micbias, ret);
3399
3400 dev_dbg(codec->dev, "Configuring microphone detection on %d %p\n",
3401 micbias, jack);
3402
3403 /* Store the configuration */
3404 micdet->jack = jack;
3405 micdet->detecting = true;
3406
3407 /* If either of the jacks is set up then enable detection */
3408 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
3409 reg = WM8994_MICD_ENA;
3410 else
3411 reg = 0;
3412
3413 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
3414
3415 /* enable MICDET and MICSHRT deboune */
3416 snd_soc_update_bits(codec, WM8994_IRQ_DEBOUNCE,
3417 WM8994_MIC1_DET_DB_MASK | WM8994_MIC1_SHRT_DB_MASK |
3418 WM8994_MIC2_DET_DB_MASK | WM8994_MIC2_SHRT_DB_MASK,
3419 WM8994_MIC1_DET_DB | WM8994_MIC1_SHRT_DB);
3420
3421 snd_soc_dapm_sync(&codec->dapm);
3422
3423 return 0;
3424}
3425EXPORT_SYMBOL_GPL(wm8994_mic_detect);
3426
3427static void wm8994_mic_work(struct work_struct *work)
3428{
3429 struct wm8994_priv *priv = container_of(work,
3430 struct wm8994_priv,
3431 mic_work.work);
3432 struct regmap *regmap = priv->wm8994->regmap;
3433 struct device *dev = priv->wm8994->dev;
3434 unsigned int reg;
3435 int ret;
3436 int report;
3437
3438 pm_runtime_get_sync(dev);
3439
3440 ret = regmap_read(regmap, WM8994_INTERRUPT_RAW_STATUS_2, ®);
3441 if (ret < 0) {
3442 dev_err(dev, "Failed to read microphone status: %d\n",
3443 ret);
3444 pm_runtime_put(dev);
3445 return;
3446 }
3447
3448 dev_dbg(dev, "Microphone status: %x\n", reg);
3449
3450 report = 0;
3451 if (reg & WM8994_MIC1_DET_STS) {
3452 if (priv->micdet[0].detecting)
3453 report = SND_JACK_HEADSET;
3454 }
3455 if (reg & WM8994_MIC1_SHRT_STS) {
3456 if (priv->micdet[0].detecting)
3457 report = SND_JACK_HEADPHONE;
3458 else
3459 report |= SND_JACK_BTN_0;
3460 }
3461 if (report)
3462 priv->micdet[0].detecting = false;
3463 else
3464 priv->micdet[0].detecting = true;
3465
3466 snd_soc_jack_report(priv->micdet[0].jack, report,
3467 SND_JACK_HEADSET | SND_JACK_BTN_0);
3468
3469 report = 0;
3470 if (reg & WM8994_MIC2_DET_STS) {
3471 if (priv->micdet[1].detecting)
3472 report = SND_JACK_HEADSET;
3473 }
3474 if (reg & WM8994_MIC2_SHRT_STS) {
3475 if (priv->micdet[1].detecting)
3476 report = SND_JACK_HEADPHONE;
3477 else
3478 report |= SND_JACK_BTN_0;
3479 }
3480 if (report)
3481 priv->micdet[1].detecting = false;
3482 else
3483 priv->micdet[1].detecting = true;
3484
3485 snd_soc_jack_report(priv->micdet[1].jack, report,
3486 SND_JACK_HEADSET | SND_JACK_BTN_0);
3487
3488 pm_runtime_put(dev);
3489}
3490
3491static irqreturn_t wm8994_mic_irq(int irq, void *data)
3492{
3493 struct wm8994_priv *priv = data;
3494 struct snd_soc_codec *codec = priv->hubs.codec;
3495
3496#ifndef CONFIG_SND_SOC_WM8994_MODULE
3497 trace_snd_soc_jack_irq(dev_name(codec->dev));
3498#endif
3499
3500 pm_wakeup_event(codec->dev, 300);
3501
3502 queue_delayed_work(system_power_efficient_wq,
3503 &priv->mic_work, msecs_to_jiffies(250));
3504
3505 return IRQ_HANDLED;
3506}
3507
3508static void wm1811_micd_stop(struct snd_soc_codec *codec)
3509{
3510 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3511
3512 if (!wm8994->jackdet)
3513 return;
3514
3515 mutex_lock(&wm8994->accdet_lock);
3516
3517 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1, WM8958_MICD_ENA, 0);
3518
3519 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3520
3521 mutex_unlock(&wm8994->accdet_lock);
3522
3523 if (wm8994->wm8994->pdata.jd_ext_cap)
3524 snd_soc_dapm_disable_pin(&codec->dapm,
3525 "MICBIAS2");
3526}
3527
3528static void wm8958_button_det(struct snd_soc_codec *codec, u16 status)
3529{
3530 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3531 int report;
3532
3533 report = 0;
3534 if (status & 0x4)
3535 report |= SND_JACK_BTN_0;
3536
3537 if (status & 0x8)
3538 report |= SND_JACK_BTN_1;
3539
3540 if (status & 0x10)
3541 report |= SND_JACK_BTN_2;
3542
3543 if (status & 0x20)
3544 report |= SND_JACK_BTN_3;
3545
3546 if (status & 0x40)
3547 report |= SND_JACK_BTN_4;
3548
3549 if (status & 0x80)
3550 report |= SND_JACK_BTN_5;
3551
3552 snd_soc_jack_report(wm8994->micdet[0].jack, report,
3553 wm8994->btn_mask);
3554}
3555
3556static void wm8958_open_circuit_work(struct work_struct *work)
3557{
3558 struct wm8994_priv *wm8994 = container_of(work,
3559 struct wm8994_priv,
3560 open_circuit_work.work);
3561 struct device *dev = wm8994->wm8994->dev;
3562
3563 wm1811_micd_stop(wm8994->hubs.codec);
3564
3565 mutex_lock(&wm8994->accdet_lock);
3566
3567 dev_dbg(dev, "Reporting open circuit\n");
3568
3569 wm8994->jack_mic = false;
3570 wm8994->mic_detecting = true;
3571
3572 wm8958_micd_set_rate(wm8994->hubs.codec);
3573
3574 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3575 wm8994->btn_mask |
3576 SND_JACK_HEADSET);
3577
3578 mutex_unlock(&wm8994->accdet_lock);
3579}
3580
3581static void wm8958_mic_id(void *data, u16 status)
3582{
3583 struct snd_soc_codec *codec = data;
3584 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3585
3586 /* Either nothing present or just starting detection */
3587 if (!(status & WM8958_MICD_STS)) {
3588 /* If nothing present then clear our statuses */
3589 dev_dbg(codec->dev, "Detected open circuit\n");
3590
3591 queue_delayed_work(system_power_efficient_wq,
3592 &wm8994->open_circuit_work,
3593 msecs_to_jiffies(2500));
3594 return;
3595 }
3596
3597 /* If the measurement is showing a high impedence we've got a
3598 * microphone.
3599 */
3600 if (status & 0x600) {
3601 dev_dbg(codec->dev, "Detected microphone\n");
3602
3603 wm8994->mic_detecting = false;
3604 wm8994->jack_mic = true;
3605
3606 wm8958_micd_set_rate(codec);
3607
3608 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADSET,
3609 SND_JACK_HEADSET);
3610 }
3611
3612
3613 if (status & 0xfc) {
3614 dev_dbg(codec->dev, "Detected headphone\n");
3615 wm8994->mic_detecting = false;
3616
3617 wm8958_micd_set_rate(codec);
3618
3619 /* If we have jackdet that will detect removal */
3620 wm1811_micd_stop(codec);
3621
3622 snd_soc_jack_report(wm8994->micdet[0].jack, SND_JACK_HEADPHONE,
3623 SND_JACK_HEADSET);
3624 }
3625}
3626
3627/* Deferred mic detection to allow for extra settling time */
3628static void wm1811_mic_work(struct work_struct *work)
3629{
3630 struct wm8994_priv *wm8994 = container_of(work, struct wm8994_priv,
3631 mic_work.work);
3632 struct wm8994 *control = wm8994->wm8994;
3633 struct snd_soc_codec *codec = wm8994->hubs.codec;
3634
3635 pm_runtime_get_sync(codec->dev);
3636
3637 /* If required for an external cap force MICBIAS on */
3638 if (control->pdata.jd_ext_cap) {
3639 snd_soc_dapm_force_enable_pin(&codec->dapm,
3640 "MICBIAS2");
3641 snd_soc_dapm_sync(&codec->dapm);
3642 }
3643
3644 mutex_lock(&wm8994->accdet_lock);
3645
3646 dev_dbg(codec->dev, "Starting mic detection\n");
3647
3648 /* Use a user-supplied callback if we have one */
3649 if (wm8994->micd_cb) {
3650 wm8994->micd_cb(wm8994->micd_cb_data);
3651 } else {
3652 /*
3653 * Start off measument of microphone impedence to find out
3654 * what's actually there.
3655 */
3656 wm8994->mic_detecting = true;
3657 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_MIC);
3658
3659 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3660 WM8958_MICD_ENA, WM8958_MICD_ENA);
3661 }
3662
3663 mutex_unlock(&wm8994->accdet_lock);
3664
3665 pm_runtime_put(codec->dev);
3666}
3667
3668static irqreturn_t wm1811_jackdet_irq(int irq, void *data)
3669{
3670 struct wm8994_priv *wm8994 = data;
3671 struct wm8994 *control = wm8994->wm8994;
3672 struct snd_soc_codec *codec = wm8994->hubs.codec;
3673 int reg, delay;
3674 bool present;
3675
3676 pm_runtime_get_sync(codec->dev);
3677
3678 cancel_delayed_work_sync(&wm8994->mic_complete_work);
3679
3680 mutex_lock(&wm8994->accdet_lock);
3681
3682 reg = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3683 if (reg < 0) {
3684 dev_err(codec->dev, "Failed to read jack status: %d\n", reg);
3685 mutex_unlock(&wm8994->accdet_lock);
3686 pm_runtime_put(codec->dev);
3687 return IRQ_NONE;
3688 }
3689
3690 dev_dbg(codec->dev, "JACKDET %x\n", reg);
3691
3692 present = reg & WM1811_JACKDET_LVL;
3693
3694 if (present) {
3695 dev_dbg(codec->dev, "Jack detected\n");
3696
3697 wm8958_micd_set_rate(codec);
3698
3699 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3700 WM8958_MICB2_DISCH, 0);
3701
3702 /* Disable debounce while inserted */
3703 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3704 WM1811_JACKDET_DB, 0);
3705
3706 delay = control->pdata.micdet_delay;
3707 queue_delayed_work(system_power_efficient_wq,
3708 &wm8994->mic_work,
3709 msecs_to_jiffies(delay));
3710 } else {
3711 dev_dbg(codec->dev, "Jack not detected\n");
3712
3713 cancel_delayed_work_sync(&wm8994->mic_work);
3714
3715 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3716 WM8958_MICB2_DISCH, WM8958_MICB2_DISCH);
3717
3718 /* Enable debounce while removed */
3719 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3720 WM1811_JACKDET_DB, WM1811_JACKDET_DB);
3721
3722 wm8994->mic_detecting = false;
3723 wm8994->jack_mic = false;
3724 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3725 WM8958_MICD_ENA, 0);
3726 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_JACK);
3727 }
3728
3729 mutex_unlock(&wm8994->accdet_lock);
3730
3731 /* Turn off MICBIAS if it was on for an external cap */
3732 if (control->pdata.jd_ext_cap && !present)
3733 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS2");
3734
3735 if (present)
3736 snd_soc_jack_report(wm8994->micdet[0].jack,
3737 SND_JACK_MECHANICAL, SND_JACK_MECHANICAL);
3738 else
3739 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3740 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3741 wm8994->btn_mask);
3742
3743 /* Since we only report deltas force an update, ensures we
3744 * avoid bootstrapping issues with the core. */
3745 snd_soc_jack_report(wm8994->micdet[0].jack, 0, 0);
3746
3747 pm_runtime_put(codec->dev);
3748 return IRQ_HANDLED;
3749}
3750
3751static void wm1811_jackdet_bootstrap(struct work_struct *work)
3752{
3753 struct wm8994_priv *wm8994 = container_of(work,
3754 struct wm8994_priv,
3755 jackdet_bootstrap.work);
3756 wm1811_jackdet_irq(0, wm8994);
3757}
3758
3759/**
3760 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
3761 *
3762 * @codec: WM8958 codec
3763 * @jack: jack to report detection events on
3764 *
3765 * Enable microphone detection functionality for the WM8958. By
3766 * default simple detection which supports the detection of up to 6
3767 * buttons plus video and microphone functionality is supported.
3768 *
3769 * The WM8958 has an advanced jack detection facility which is able to
3770 * support complex accessory detection, especially when used in
3771 * conjunction with external circuitry. In order to provide maximum
3772 * flexiblity a callback is provided which allows a completely custom
3773 * detection algorithm.
3774 */
3775int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
3776 wm1811_micdet_cb det_cb, void *det_cb_data,
3777 wm1811_mic_id_cb id_cb, void *id_cb_data)
3778{
3779 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3780 struct wm8994 *control = wm8994->wm8994;
3781 u16 micd_lvl_sel;
3782
3783 switch (control->type) {
3784 case WM1811:
3785 case WM8958:
3786 break;
3787 default:
3788 return -EINVAL;
3789 }
3790
3791 if (jack) {
3792 snd_soc_dapm_force_enable_pin(&codec->dapm, "CLK_SYS");
3793 snd_soc_dapm_sync(&codec->dapm);
3794
3795 wm8994->micdet[0].jack = jack;
3796
3797 if (det_cb) {
3798 wm8994->micd_cb = det_cb;
3799 wm8994->micd_cb_data = det_cb_data;
3800 } else {
3801 wm8994->mic_detecting = true;
3802 wm8994->jack_mic = false;
3803 }
3804
3805 if (id_cb) {
3806 wm8994->mic_id_cb = id_cb;
3807 wm8994->mic_id_cb_data = id_cb_data;
3808 } else {
3809 wm8994->mic_id_cb = wm8958_mic_id;
3810 wm8994->mic_id_cb_data = codec;
3811 }
3812
3813 wm8958_micd_set_rate(codec);
3814
3815 /* Detect microphones and short circuits by default */
3816 if (control->pdata.micd_lvl_sel)
3817 micd_lvl_sel = control->pdata.micd_lvl_sel;
3818 else
3819 micd_lvl_sel = 0x41;
3820
3821 wm8994->btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3822 SND_JACK_BTN_2 | SND_JACK_BTN_3 |
3823 SND_JACK_BTN_4 | SND_JACK_BTN_5;
3824
3825 snd_soc_update_bits(codec, WM8958_MIC_DETECT_2,
3826 WM8958_MICD_LVL_SEL_MASK, micd_lvl_sel);
3827
3828 WARN_ON(codec->dapm.bias_level > SND_SOC_BIAS_STANDBY);
3829
3830 /*
3831 * If we can use jack detection start off with that,
3832 * otherwise jump straight to microphone detection.
3833 */
3834 if (wm8994->jackdet) {
3835 /* Disable debounce for the initial detect */
3836 snd_soc_update_bits(codec, WM1811_JACKDET_CTRL,
3837 WM1811_JACKDET_DB, 0);
3838
3839 snd_soc_update_bits(codec, WM8958_MICBIAS2,
3840 WM8958_MICB2_DISCH,
3841 WM8958_MICB2_DISCH);
3842 snd_soc_update_bits(codec, WM8994_LDO_1,
3843 WM8994_LDO1_DISCH, 0);
3844 wm1811_jackdet_set_mode(codec,
3845 WM1811_JACKDET_MODE_JACK);
3846 } else {
3847 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3848 WM8958_MICD_ENA, WM8958_MICD_ENA);
3849 }
3850
3851 } else {
3852 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
3853 WM8958_MICD_ENA, 0);
3854 wm1811_jackdet_set_mode(codec, WM1811_JACKDET_MODE_NONE);
3855 snd_soc_dapm_disable_pin(&codec->dapm, "CLK_SYS");
3856 snd_soc_dapm_sync(&codec->dapm);
3857 }
3858
3859 return 0;
3860}
3861EXPORT_SYMBOL_GPL(wm8958_mic_detect);
3862
3863static void wm8958_mic_work(struct work_struct *work)
3864{
3865 struct wm8994_priv *wm8994 = container_of(work,
3866 struct wm8994_priv,
3867 mic_complete_work.work);
3868 struct snd_soc_codec *codec = wm8994->hubs.codec;
3869
3870 pm_runtime_get_sync(codec->dev);
3871
3872 mutex_lock(&wm8994->accdet_lock);
3873
3874 wm8994->mic_id_cb(wm8994->mic_id_cb_data, wm8994->mic_status);
3875
3876 mutex_unlock(&wm8994->accdet_lock);
3877
3878 pm_runtime_put(codec->dev);
3879}
3880
3881static irqreturn_t wm8958_mic_irq(int irq, void *data)
3882{
3883 struct wm8994_priv *wm8994 = data;
3884 struct snd_soc_codec *codec = wm8994->hubs.codec;
3885 int reg, count, ret, id_delay;
3886
3887 /*
3888 * Jack detection may have detected a removal simulataneously
3889 * with an update of the MICDET status; if so it will have
3890 * stopped detection and we can ignore this interrupt.
3891 */
3892 if (!(snd_soc_read(codec, WM8958_MIC_DETECT_1) & WM8958_MICD_ENA))
3893 return IRQ_HANDLED;
3894
3895 cancel_delayed_work_sync(&wm8994->mic_complete_work);
3896 cancel_delayed_work_sync(&wm8994->open_circuit_work);
3897
3898 pm_runtime_get_sync(codec->dev);
3899
3900 /* We may occasionally read a detection without an impedence
3901 * range being provided - if that happens loop again.
3902 */
3903 count = 10;
3904 do {
3905 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
3906 if (reg < 0) {
3907 dev_err(codec->dev,
3908 "Failed to read mic detect status: %d\n",
3909 reg);
3910 pm_runtime_put(codec->dev);
3911 return IRQ_NONE;
3912 }
3913
3914 if (!(reg & WM8958_MICD_VALID)) {
3915 dev_dbg(codec->dev, "Mic detect data not valid\n");
3916 goto out;
3917 }
3918
3919 if (!(reg & WM8958_MICD_STS) || (reg & WM8958_MICD_LVL_MASK))
3920 break;
3921
3922 msleep(1);
3923 } while (count--);
3924
3925 if (count == 0)
3926 dev_warn(codec->dev, "No impedance range reported for jack\n");
3927
3928#ifndef CONFIG_SND_SOC_WM8994_MODULE
3929 trace_snd_soc_jack_irq(dev_name(codec->dev));
3930#endif
3931
3932 /* Avoid a transient report when the accessory is being removed */
3933 if (wm8994->jackdet) {
3934 ret = snd_soc_read(codec, WM1811_JACKDET_CTRL);
3935 if (ret < 0) {
3936 dev_err(codec->dev, "Failed to read jack status: %d\n",
3937 ret);
3938 } else if (!(ret & WM1811_JACKDET_LVL)) {
3939 dev_dbg(codec->dev, "Ignoring removed jack\n");
3940 goto out;
3941 }
3942 } else if (!(reg & WM8958_MICD_STS)) {
3943 snd_soc_jack_report(wm8994->micdet[0].jack, 0,
3944 SND_JACK_MECHANICAL | SND_JACK_HEADSET |
3945 wm8994->btn_mask);
3946 wm8994->mic_detecting = true;
3947 goto out;
3948 }
3949
3950 wm8994->mic_status = reg;
3951 id_delay = wm8994->wm8994->pdata.mic_id_delay;
3952
3953 if (wm8994->mic_detecting)
3954 queue_delayed_work(system_power_efficient_wq,
3955 &wm8994->mic_complete_work,
3956 msecs_to_jiffies(id_delay));
3957 else
3958 wm8958_button_det(codec, reg);
3959
3960out:
3961 pm_runtime_put(codec->dev);
3962 return IRQ_HANDLED;
3963}
3964
3965static irqreturn_t wm8994_fifo_error(int irq, void *data)
3966{
3967 struct snd_soc_codec *codec = data;
3968
3969 dev_err(codec->dev, "FIFO error\n");
3970
3971 return IRQ_HANDLED;
3972}
3973
3974static irqreturn_t wm8994_temp_warn(int irq, void *data)
3975{
3976 struct snd_soc_codec *codec = data;
3977
3978 dev_err(codec->dev, "Thermal warning\n");
3979
3980 return IRQ_HANDLED;
3981}
3982
3983static irqreturn_t wm8994_temp_shut(int irq, void *data)
3984{
3985 struct snd_soc_codec *codec = data;
3986
3987 dev_crit(codec->dev, "Thermal shutdown\n");
3988
3989 return IRQ_HANDLED;
3990}
3991
3992static int wm8994_codec_probe(struct snd_soc_codec *codec)
3993{
3994 struct wm8994 *control = dev_get_drvdata(codec->dev->parent);
3995 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3996 struct snd_soc_dapm_context *dapm = &codec->dapm;
3997 unsigned int reg;
3998 int ret, i;
3999
4000 wm8994->hubs.codec = codec;
4001
4002 snd_soc_codec_set_cache_io(codec, control->regmap);
4003
4004 mutex_init(&wm8994->accdet_lock);
4005 INIT_DELAYED_WORK(&wm8994->jackdet_bootstrap,
4006 wm1811_jackdet_bootstrap);
4007 INIT_DELAYED_WORK(&wm8994->open_circuit_work,
4008 wm8958_open_circuit_work);
4009
4010 switch (control->type) {
4011 case WM8994:
4012 INIT_DELAYED_WORK(&wm8994->mic_work, wm8994_mic_work);
4013 break;
4014 case WM1811:
4015 INIT_DELAYED_WORK(&wm8994->mic_work, wm1811_mic_work);
4016 break;
4017 default:
4018 break;
4019 }
4020
4021 INIT_DELAYED_WORK(&wm8994->mic_complete_work, wm8958_mic_work);
4022
4023 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4024 init_completion(&wm8994->fll_locked[i]);
4025
4026 wm8994->micdet_irq = control->pdata.micdet_irq;
4027
4028 /* By default use idle_bias_off, will override for WM8994 */
4029 codec->dapm.idle_bias_off = 1;
4030
4031 /* Set revision-specific configuration */
4032 switch (control->type) {
4033 case WM8994:
4034 /* Single ended line outputs should have VMID on. */
4035 if (!control->pdata.lineout1_diff ||
4036 !control->pdata.lineout2_diff)
4037 codec->dapm.idle_bias_off = 0;
4038
4039 switch (control->revision) {
4040 case 2:
4041 case 3:
4042 wm8994->hubs.dcs_codes_l = -5;
4043 wm8994->hubs.dcs_codes_r = -5;
4044 wm8994->hubs.hp_startup_mode = 1;
4045 wm8994->hubs.dcs_readback_mode = 1;
4046 wm8994->hubs.series_startup = 1;
4047 break;
4048 default:
4049 wm8994->hubs.dcs_readback_mode = 2;
4050 break;
4051 }
4052 break;
4053
4054 case WM8958:
4055 wm8994->hubs.dcs_readback_mode = 1;
4056 wm8994->hubs.hp_startup_mode = 1;
4057
4058 switch (control->revision) {
4059 case 0:
4060 break;
4061 default:
4062 wm8994->fll_byp = true;
4063 break;
4064 }
4065 break;
4066
4067 case WM1811:
4068 wm8994->hubs.dcs_readback_mode = 2;
4069 wm8994->hubs.no_series_update = 1;
4070 wm8994->hubs.hp_startup_mode = 1;
4071 wm8994->hubs.no_cache_dac_hp_direct = true;
4072 wm8994->fll_byp = true;
4073
4074 wm8994->hubs.dcs_codes_l = -9;
4075 wm8994->hubs.dcs_codes_r = -7;
4076
4077 snd_soc_update_bits(codec, WM8994_ANALOGUE_HP_1,
4078 WM1811_HPOUT1_ATTN, WM1811_HPOUT1_ATTN);
4079 break;
4080
4081 default:
4082 break;
4083 }
4084
4085 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR,
4086 wm8994_fifo_error, "FIFO error", codec);
4087 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN,
4088 wm8994_temp_warn, "Thermal warning", codec);
4089 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT,
4090 wm8994_temp_shut, "Thermal shutdown", codec);
4091
4092 switch (control->type) {
4093 case WM8994:
4094 if (wm8994->micdet_irq) {
4095 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4096 wm8994_mic_irq,
4097 IRQF_TRIGGER_RISING,
4098 "Mic1 detect",
4099 wm8994);
4100 if (ret != 0)
4101 dev_warn(codec->dev,
4102 "Failed to request Mic1 detect IRQ: %d\n",
4103 ret);
4104 }
4105
4106 ret = wm8994_request_irq(wm8994->wm8994,
4107 WM8994_IRQ_MIC1_SHRT,
4108 wm8994_mic_irq, "Mic 1 short",
4109 wm8994);
4110 if (ret != 0)
4111 dev_warn(codec->dev,
4112 "Failed to request Mic1 short IRQ: %d\n",
4113 ret);
4114
4115 ret = wm8994_request_irq(wm8994->wm8994,
4116 WM8994_IRQ_MIC2_DET,
4117 wm8994_mic_irq, "Mic 2 detect",
4118 wm8994);
4119 if (ret != 0)
4120 dev_warn(codec->dev,
4121 "Failed to request Mic2 detect IRQ: %d\n",
4122 ret);
4123
4124 ret = wm8994_request_irq(wm8994->wm8994,
4125 WM8994_IRQ_MIC2_SHRT,
4126 wm8994_mic_irq, "Mic 2 short",
4127 wm8994);
4128 if (ret != 0)
4129 dev_warn(codec->dev,
4130 "Failed to request Mic2 short IRQ: %d\n",
4131 ret);
4132 break;
4133
4134 case WM8958:
4135 case WM1811:
4136 if (wm8994->micdet_irq) {
4137 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
4138 wm8958_mic_irq,
4139 IRQF_TRIGGER_RISING,
4140 "Mic detect",
4141 wm8994);
4142 if (ret != 0)
4143 dev_warn(codec->dev,
4144 "Failed to request Mic detect IRQ: %d\n",
4145 ret);
4146 } else {
4147 wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4148 wm8958_mic_irq, "Mic detect",
4149 wm8994);
4150 }
4151 }
4152
4153 switch (control->type) {
4154 case WM1811:
4155 if (control->cust_id > 1 || control->revision > 1) {
4156 ret = wm8994_request_irq(wm8994->wm8994,
4157 WM8994_IRQ_GPIO(6),
4158 wm1811_jackdet_irq, "JACKDET",
4159 wm8994);
4160 if (ret == 0)
4161 wm8994->jackdet = true;
4162 }
4163 break;
4164 default:
4165 break;
4166 }
4167
4168 wm8994->fll_locked_irq = true;
4169 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
4170 ret = wm8994_request_irq(wm8994->wm8994,
4171 WM8994_IRQ_FLL1_LOCK + i,
4172 wm8994_fll_locked_irq, "FLL lock",
4173 &wm8994->fll_locked[i]);
4174 if (ret != 0)
4175 wm8994->fll_locked_irq = false;
4176 }
4177
4178 /* Make sure we can read from the GPIOs if they're inputs */
4179 pm_runtime_get_sync(codec->dev);
4180
4181 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
4182 * configured on init - if a system wants to do this dynamically
4183 * at runtime we can deal with that then.
4184 */
4185 ret = regmap_read(control->regmap, WM8994_GPIO_1, ®);
4186 if (ret < 0) {
4187 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
4188 goto err_irq;
4189 }
4190 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4191 wm8994->lrclk_shared[0] = 1;
4192 wm8994_dai[0].symmetric_rates = 1;
4193 } else {
4194 wm8994->lrclk_shared[0] = 0;
4195 }
4196
4197 ret = regmap_read(control->regmap, WM8994_GPIO_6, ®);
4198 if (ret < 0) {
4199 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
4200 goto err_irq;
4201 }
4202 if ((reg & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
4203 wm8994->lrclk_shared[1] = 1;
4204 wm8994_dai[1].symmetric_rates = 1;
4205 } else {
4206 wm8994->lrclk_shared[1] = 0;
4207 }
4208
4209 pm_runtime_put(codec->dev);
4210
4211 /* Latch volume update bits */
4212 for (i = 0; i < ARRAY_SIZE(wm8994_vu_bits); i++)
4213 snd_soc_update_bits(codec, wm8994_vu_bits[i].reg,
4214 wm8994_vu_bits[i].mask,
4215 wm8994_vu_bits[i].mask);
4216
4217 /* Set the low bit of the 3D stereo depth so TLV matches */
4218 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
4219 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
4220 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
4221 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
4222 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
4223 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
4224 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
4225 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
4226 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
4227
4228 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
4229 * use this; it only affects behaviour on idle TDM clock
4230 * cycles. */
4231 switch (control->type) {
4232 case WM8994:
4233 case WM8958:
4234 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
4235 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
4236 break;
4237 default:
4238 break;
4239 }
4240
4241 /* Put MICBIAS into bypass mode by default on newer devices */
4242 switch (control->type) {
4243 case WM8958:
4244 case WM1811:
4245 snd_soc_update_bits(codec, WM8958_MICBIAS1,
4246 WM8958_MICB1_MODE, WM8958_MICB1_MODE);
4247 snd_soc_update_bits(codec, WM8958_MICBIAS2,
4248 WM8958_MICB2_MODE, WM8958_MICB2_MODE);
4249 break;
4250 default:
4251 break;
4252 }
4253
4254 wm8994->hubs.check_class_w_digital = wm8994_check_class_w_digital;
4255 wm_hubs_update_class_w(codec);
4256
4257 wm8994_handle_pdata(wm8994);
4258
4259 wm_hubs_add_analogue_controls(codec);
4260 snd_soc_add_codec_controls(codec, wm8994_snd_controls,
4261 ARRAY_SIZE(wm8994_snd_controls));
4262 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
4263 ARRAY_SIZE(wm8994_dapm_widgets));
4264
4265 switch (control->type) {
4266 case WM8994:
4267 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
4268 ARRAY_SIZE(wm8994_specific_dapm_widgets));
4269 if (control->revision < 4) {
4270 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4271 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4272 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4273 ARRAY_SIZE(wm8994_adc_revd_widgets));
4274 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4275 ARRAY_SIZE(wm8994_dac_revd_widgets));
4276 } else {
4277 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4278 ARRAY_SIZE(wm8994_lateclk_widgets));
4279 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4280 ARRAY_SIZE(wm8994_adc_widgets));
4281 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4282 ARRAY_SIZE(wm8994_dac_widgets));
4283 }
4284 break;
4285 case WM8958:
4286 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4287 ARRAY_SIZE(wm8958_snd_controls));
4288 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4289 ARRAY_SIZE(wm8958_dapm_widgets));
4290 if (control->revision < 1) {
4291 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
4292 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
4293 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
4294 ARRAY_SIZE(wm8994_adc_revd_widgets));
4295 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
4296 ARRAY_SIZE(wm8994_dac_revd_widgets));
4297 } else {
4298 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4299 ARRAY_SIZE(wm8994_lateclk_widgets));
4300 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4301 ARRAY_SIZE(wm8994_adc_widgets));
4302 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4303 ARRAY_SIZE(wm8994_dac_widgets));
4304 }
4305 break;
4306
4307 case WM1811:
4308 snd_soc_add_codec_controls(codec, wm8958_snd_controls,
4309 ARRAY_SIZE(wm8958_snd_controls));
4310 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
4311 ARRAY_SIZE(wm8958_dapm_widgets));
4312 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
4313 ARRAY_SIZE(wm8994_lateclk_widgets));
4314 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
4315 ARRAY_SIZE(wm8994_adc_widgets));
4316 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
4317 ARRAY_SIZE(wm8994_dac_widgets));
4318 break;
4319 }
4320
4321 wm_hubs_add_analogue_routes(codec, 0, 0);
4322 ret = wm8994_request_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4323 wm_hubs_dcs_done, "DC servo done",
4324 &wm8994->hubs);
4325 if (ret == 0)
4326 wm8994->hubs.dcs_done_irq = true;
4327 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
4328
4329 switch (control->type) {
4330 case WM8994:
4331 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4332 ARRAY_SIZE(wm8994_intercon));
4333
4334 if (control->revision < 4) {
4335 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4336 ARRAY_SIZE(wm8994_revd_intercon));
4337 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4338 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4339 } else {
4340 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4341 ARRAY_SIZE(wm8994_lateclk_intercon));
4342 }
4343 break;
4344 case WM8958:
4345 if (control->revision < 1) {
4346 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
4347 ARRAY_SIZE(wm8994_intercon));
4348 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
4349 ARRAY_SIZE(wm8994_revd_intercon));
4350 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
4351 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
4352 } else {
4353 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4354 ARRAY_SIZE(wm8994_lateclk_intercon));
4355 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4356 ARRAY_SIZE(wm8958_intercon));
4357 }
4358
4359 wm8958_dsp2_init(codec);
4360 break;
4361 case WM1811:
4362 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
4363 ARRAY_SIZE(wm8994_lateclk_intercon));
4364 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
4365 ARRAY_SIZE(wm8958_intercon));
4366 break;
4367 }
4368
4369 return 0;
4370
4371err_irq:
4372 if (wm8994->jackdet)
4373 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4374 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_SHRT, wm8994);
4375 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET, wm8994);
4376 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT, wm8994);
4377 if (wm8994->micdet_irq)
4378 free_irq(wm8994->micdet_irq, wm8994);
4379 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4380 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4381 &wm8994->fll_locked[i]);
4382 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4383 &wm8994->hubs);
4384 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4385 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4386 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4387
4388 return ret;
4389}
4390
4391static int wm8994_codec_remove(struct snd_soc_codec *codec)
4392{
4393 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
4394 struct wm8994 *control = wm8994->wm8994;
4395 int i;
4396
4397 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
4398
4399 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
4400 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FLL1_LOCK + i,
4401 &wm8994->fll_locked[i]);
4402
4403 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_DCS_DONE,
4404 &wm8994->hubs);
4405 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_FIFOS_ERR, codec);
4406 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_SHUT, codec);
4407 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_TEMP_WARN, codec);
4408
4409 if (wm8994->jackdet)
4410 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_GPIO(6), wm8994);
4411
4412 switch (control->type) {
4413 case WM8994:
4414 if (wm8994->micdet_irq)
4415 free_irq(wm8994->micdet_irq, wm8994);
4416 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC2_DET,
4417 wm8994);
4418 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_SHRT,
4419 wm8994);
4420 wm8994_free_irq(wm8994->wm8994, WM8994_IRQ_MIC1_DET,
4421 wm8994);
4422 break;
4423
4424 case WM1811:
4425 case WM8958:
4426 if (wm8994->micdet_irq)
4427 free_irq(wm8994->micdet_irq, wm8994);
4428 break;
4429 }
4430 release_firmware(wm8994->mbc);
4431 release_firmware(wm8994->mbc_vss);
4432 release_firmware(wm8994->enh_eq);
4433 kfree(wm8994->retune_mobile_texts);
4434 return 0;
4435}
4436
4437static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
4438 .probe = wm8994_codec_probe,
4439 .remove = wm8994_codec_remove,
4440 .suspend = wm8994_codec_suspend,
4441 .resume = wm8994_codec_resume,
4442 .set_bias_level = wm8994_set_bias_level,
4443};
4444
4445static int wm8994_probe(struct platform_device *pdev)
4446{
4447 struct wm8994_priv *wm8994;
4448
4449 wm8994 = devm_kzalloc(&pdev->dev, sizeof(struct wm8994_priv),
4450 GFP_KERNEL);
4451 if (wm8994 == NULL)
4452 return -ENOMEM;
4453 platform_set_drvdata(pdev, wm8994);
4454
4455 wm8994->wm8994 = dev_get_drvdata(pdev->dev.parent);
4456
4457 pm_runtime_enable(&pdev->dev);
4458 pm_runtime_idle(&pdev->dev);
4459
4460 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
4461 wm8994_dai, ARRAY_SIZE(wm8994_dai));
4462}
4463
4464static int wm8994_remove(struct platform_device *pdev)
4465{
4466 snd_soc_unregister_codec(&pdev->dev);
4467 pm_runtime_disable(&pdev->dev);
4468
4469 return 0;
4470}
4471
4472#ifdef CONFIG_PM_SLEEP
4473static int wm8994_suspend(struct device *dev)
4474{
4475 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4476
4477 /* Drop down to power saving mode when system is suspended */
4478 if (wm8994->jackdet && !wm8994->active_refcount)
4479 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4480 WM1811_JACKDET_MODE_MASK,
4481 wm8994->jackdet_mode);
4482
4483 return 0;
4484}
4485
4486static int wm8994_resume(struct device *dev)
4487{
4488 struct wm8994_priv *wm8994 = dev_get_drvdata(dev);
4489
4490 if (wm8994->jackdet && wm8994->jackdet_mode)
4491 regmap_update_bits(wm8994->wm8994->regmap, WM8994_ANTIPOP_2,
4492 WM1811_JACKDET_MODE_MASK,
4493 WM1811_JACKDET_MODE_AUDIO);
4494
4495 return 0;
4496}
4497#endif
4498
4499static const struct dev_pm_ops wm8994_pm_ops = {
4500 SET_SYSTEM_SLEEP_PM_OPS(wm8994_suspend, wm8994_resume)
4501};
4502
4503static struct platform_driver wm8994_codec_driver = {
4504 .driver = {
4505 .name = "wm8994-codec",
4506 .owner = THIS_MODULE,
4507 .pm = &wm8994_pm_ops,
4508 },
4509 .probe = wm8994_probe,
4510 .remove = wm8994_remove,
4511};
4512
4513module_platform_driver(wm8994_codec_driver);
4514
4515MODULE_DESCRIPTION("ASoC WM8994 driver");
4516MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
4517MODULE_LICENSE("GPL");
4518MODULE_ALIAS("platform:wm8994-codec");
1/*
2 * wm8994.c -- WM8994 ALSA SoC Audio driver
3 *
4 * Copyright 2009 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/regulator/consumer.h>
23#include <linux/slab.h>
24#include <sound/core.h>
25#include <sound/jack.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31#include <trace/events/asoc.h>
32
33#include <linux/mfd/wm8994/core.h>
34#include <linux/mfd/wm8994/registers.h>
35#include <linux/mfd/wm8994/pdata.h>
36#include <linux/mfd/wm8994/gpio.h>
37
38#include "wm8994.h"
39#include "wm_hubs.h"
40
41#define WM8994_NUM_DRC 3
42#define WM8994_NUM_EQ 3
43
44static int wm8994_drc_base[] = {
45 WM8994_AIF1_DRC1_1,
46 WM8994_AIF1_DRC2_1,
47 WM8994_AIF2_DRC_1,
48};
49
50static int wm8994_retune_mobile_base[] = {
51 WM8994_AIF1_DAC1_EQ_GAINS_1,
52 WM8994_AIF1_DAC2_EQ_GAINS_1,
53 WM8994_AIF2_EQ_GAINS_1,
54};
55
56static int wm8994_readable(struct snd_soc_codec *codec, unsigned int reg)
57{
58 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
59 struct wm8994 *control = wm8994->control_data;
60
61 switch (reg) {
62 case WM8994_GPIO_1:
63 case WM8994_GPIO_2:
64 case WM8994_GPIO_3:
65 case WM8994_GPIO_4:
66 case WM8994_GPIO_5:
67 case WM8994_GPIO_6:
68 case WM8994_GPIO_7:
69 case WM8994_GPIO_8:
70 case WM8994_GPIO_9:
71 case WM8994_GPIO_10:
72 case WM8994_GPIO_11:
73 case WM8994_INTERRUPT_STATUS_1:
74 case WM8994_INTERRUPT_STATUS_2:
75 case WM8994_INTERRUPT_RAW_STATUS_2:
76 return 1;
77
78 case WM8958_DSP2_PROGRAM:
79 case WM8958_DSP2_CONFIG:
80 case WM8958_DSP2_EXECCONTROL:
81 if (control->type == WM8958)
82 return 1;
83 else
84 return 0;
85
86 default:
87 break;
88 }
89
90 if (reg >= WM8994_CACHE_SIZE)
91 return 0;
92 return wm8994_access_masks[reg].readable != 0;
93}
94
95static int wm8994_volatile(struct snd_soc_codec *codec, unsigned int reg)
96{
97 if (reg >= WM8994_CACHE_SIZE)
98 return 1;
99
100 switch (reg) {
101 case WM8994_SOFTWARE_RESET:
102 case WM8994_CHIP_REVISION:
103 case WM8994_DC_SERVO_1:
104 case WM8994_DC_SERVO_READBACK:
105 case WM8994_RATE_STATUS:
106 case WM8994_LDO_1:
107 case WM8994_LDO_2:
108 case WM8958_DSP2_EXECCONTROL:
109 case WM8958_MIC_DETECT_3:
110 return 1;
111 default:
112 return 0;
113 }
114}
115
116static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
117 unsigned int value)
118{
119 int ret;
120
121 BUG_ON(reg > WM8994_MAX_REGISTER);
122
123 if (!wm8994_volatile(codec, reg)) {
124 ret = snd_soc_cache_write(codec, reg, value);
125 if (ret != 0)
126 dev_err(codec->dev, "Cache write to %x failed: %d\n",
127 reg, ret);
128 }
129
130 return wm8994_reg_write(codec->control_data, reg, value);
131}
132
133static unsigned int wm8994_read(struct snd_soc_codec *codec,
134 unsigned int reg)
135{
136 unsigned int val;
137 int ret;
138
139 BUG_ON(reg > WM8994_MAX_REGISTER);
140
141 if (!wm8994_volatile(codec, reg) && wm8994_readable(codec, reg) &&
142 reg < codec->driver->reg_cache_size) {
143 ret = snd_soc_cache_read(codec, reg, &val);
144 if (ret >= 0)
145 return val;
146 else
147 dev_err(codec->dev, "Cache read from %x failed: %d\n",
148 reg, ret);
149 }
150
151 return wm8994_reg_read(codec->control_data, reg);
152}
153
154static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
155{
156 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
157 int rate;
158 int reg1 = 0;
159 int offset;
160
161 if (aif)
162 offset = 4;
163 else
164 offset = 0;
165
166 switch (wm8994->sysclk[aif]) {
167 case WM8994_SYSCLK_MCLK1:
168 rate = wm8994->mclk[0];
169 break;
170
171 case WM8994_SYSCLK_MCLK2:
172 reg1 |= 0x8;
173 rate = wm8994->mclk[1];
174 break;
175
176 case WM8994_SYSCLK_FLL1:
177 reg1 |= 0x10;
178 rate = wm8994->fll[0].out;
179 break;
180
181 case WM8994_SYSCLK_FLL2:
182 reg1 |= 0x18;
183 rate = wm8994->fll[1].out;
184 break;
185
186 default:
187 return -EINVAL;
188 }
189
190 if (rate >= 13500000) {
191 rate /= 2;
192 reg1 |= WM8994_AIF1CLK_DIV;
193
194 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
195 aif + 1, rate);
196 }
197
198 wm8994->aifclk[aif] = rate;
199
200 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
201 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
202 reg1);
203
204 return 0;
205}
206
207static int configure_clock(struct snd_soc_codec *codec)
208{
209 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
210 int old, new;
211
212 /* Bring up the AIF clocks first */
213 configure_aif_clock(codec, 0);
214 configure_aif_clock(codec, 1);
215
216 /* Then switch CLK_SYS over to the higher of them; a change
217 * can only happen as a result of a clocking change which can
218 * only be made outside of DAPM so we can safely redo the
219 * clocking.
220 */
221
222 /* If they're equal it doesn't matter which is used */
223 if (wm8994->aifclk[0] == wm8994->aifclk[1])
224 return 0;
225
226 if (wm8994->aifclk[0] < wm8994->aifclk[1])
227 new = WM8994_SYSCLK_SRC;
228 else
229 new = 0;
230
231 old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
232
233 /* If there's no change then we're done. */
234 if (old == new)
235 return 0;
236
237 snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
238
239 snd_soc_dapm_sync(&codec->dapm);
240
241 return 0;
242}
243
244static int check_clk_sys(struct snd_soc_dapm_widget *source,
245 struct snd_soc_dapm_widget *sink)
246{
247 int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
248 const char *clk;
249
250 /* Check what we're currently using for CLK_SYS */
251 if (reg & WM8994_SYSCLK_SRC)
252 clk = "AIF2CLK";
253 else
254 clk = "AIF1CLK";
255
256 return strcmp(source->name, clk) == 0;
257}
258
259static const char *sidetone_hpf_text[] = {
260 "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
261};
262
263static const struct soc_enum sidetone_hpf =
264 SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
265
266static const char *adc_hpf_text[] = {
267 "HiFi", "Voice 1", "Voice 2", "Voice 3"
268};
269
270static const struct soc_enum aif1adc1_hpf =
271 SOC_ENUM_SINGLE(WM8994_AIF1_ADC1_FILTERS, 13, 4, adc_hpf_text);
272
273static const struct soc_enum aif1adc2_hpf =
274 SOC_ENUM_SINGLE(WM8994_AIF1_ADC2_FILTERS, 13, 4, adc_hpf_text);
275
276static const struct soc_enum aif2adc_hpf =
277 SOC_ENUM_SINGLE(WM8994_AIF2_ADC_FILTERS, 13, 4, adc_hpf_text);
278
279static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
280static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
281static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
282static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
283static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
284
285#define WM8994_DRC_SWITCH(xname, reg, shift) \
286{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
287 .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
288 .put = wm8994_put_drc_sw, \
289 .private_value = SOC_SINGLE_VALUE(reg, shift, 1, 0) }
290
291static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
292 struct snd_ctl_elem_value *ucontrol)
293{
294 struct soc_mixer_control *mc =
295 (struct soc_mixer_control *)kcontrol->private_value;
296 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
297 int mask, ret;
298
299 /* Can't enable both ADC and DAC paths simultaneously */
300 if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
301 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
302 WM8994_AIF1ADC1R_DRC_ENA_MASK;
303 else
304 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
305
306 ret = snd_soc_read(codec, mc->reg);
307 if (ret < 0)
308 return ret;
309 if (ret & mask)
310 return -EINVAL;
311
312 return snd_soc_put_volsw(kcontrol, ucontrol);
313}
314
315static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
316{
317 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
318 struct wm8994_pdata *pdata = wm8994->pdata;
319 int base = wm8994_drc_base[drc];
320 int cfg = wm8994->drc_cfg[drc];
321 int save, i;
322
323 /* Save any enables; the configuration should clear them. */
324 save = snd_soc_read(codec, base);
325 save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
326 WM8994_AIF1ADC1R_DRC_ENA;
327
328 for (i = 0; i < WM8994_DRC_REGS; i++)
329 snd_soc_update_bits(codec, base + i, 0xffff,
330 pdata->drc_cfgs[cfg].regs[i]);
331
332 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
333 WM8994_AIF1ADC1L_DRC_ENA |
334 WM8994_AIF1ADC1R_DRC_ENA, save);
335}
336
337/* Icky as hell but saves code duplication */
338static int wm8994_get_drc(const char *name)
339{
340 if (strcmp(name, "AIF1DRC1 Mode") == 0)
341 return 0;
342 if (strcmp(name, "AIF1DRC2 Mode") == 0)
343 return 1;
344 if (strcmp(name, "AIF2DRC Mode") == 0)
345 return 2;
346 return -EINVAL;
347}
348
349static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
350 struct snd_ctl_elem_value *ucontrol)
351{
352 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
353 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
354 struct wm8994_pdata *pdata = wm8994->pdata;
355 int drc = wm8994_get_drc(kcontrol->id.name);
356 int value = ucontrol->value.integer.value[0];
357
358 if (drc < 0)
359 return drc;
360
361 if (value >= pdata->num_drc_cfgs)
362 return -EINVAL;
363
364 wm8994->drc_cfg[drc] = value;
365
366 wm8994_set_drc(codec, drc);
367
368 return 0;
369}
370
371static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
372 struct snd_ctl_elem_value *ucontrol)
373{
374 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
375 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
376 int drc = wm8994_get_drc(kcontrol->id.name);
377
378 ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
379
380 return 0;
381}
382
383static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
384{
385 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
386 struct wm8994_pdata *pdata = wm8994->pdata;
387 int base = wm8994_retune_mobile_base[block];
388 int iface, best, best_val, save, i, cfg;
389
390 if (!pdata || !wm8994->num_retune_mobile_texts)
391 return;
392
393 switch (block) {
394 case 0:
395 case 1:
396 iface = 0;
397 break;
398 case 2:
399 iface = 1;
400 break;
401 default:
402 return;
403 }
404
405 /* Find the version of the currently selected configuration
406 * with the nearest sample rate. */
407 cfg = wm8994->retune_mobile_cfg[block];
408 best = 0;
409 best_val = INT_MAX;
410 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
411 if (strcmp(pdata->retune_mobile_cfgs[i].name,
412 wm8994->retune_mobile_texts[cfg]) == 0 &&
413 abs(pdata->retune_mobile_cfgs[i].rate
414 - wm8994->dac_rates[iface]) < best_val) {
415 best = i;
416 best_val = abs(pdata->retune_mobile_cfgs[i].rate
417 - wm8994->dac_rates[iface]);
418 }
419 }
420
421 dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
422 block,
423 pdata->retune_mobile_cfgs[best].name,
424 pdata->retune_mobile_cfgs[best].rate,
425 wm8994->dac_rates[iface]);
426
427 /* The EQ will be disabled while reconfiguring it, remember the
428 * current configuration.
429 */
430 save = snd_soc_read(codec, base);
431 save &= WM8994_AIF1DAC1_EQ_ENA;
432
433 for (i = 0; i < WM8994_EQ_REGS; i++)
434 snd_soc_update_bits(codec, base + i, 0xffff,
435 pdata->retune_mobile_cfgs[best].regs[i]);
436
437 snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
438}
439
440/* Icky as hell but saves code duplication */
441static int wm8994_get_retune_mobile_block(const char *name)
442{
443 if (strcmp(name, "AIF1.1 EQ Mode") == 0)
444 return 0;
445 if (strcmp(name, "AIF1.2 EQ Mode") == 0)
446 return 1;
447 if (strcmp(name, "AIF2 EQ Mode") == 0)
448 return 2;
449 return -EINVAL;
450}
451
452static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
453 struct snd_ctl_elem_value *ucontrol)
454{
455 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
456 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
457 struct wm8994_pdata *pdata = wm8994->pdata;
458 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
459 int value = ucontrol->value.integer.value[0];
460
461 if (block < 0)
462 return block;
463
464 if (value >= pdata->num_retune_mobile_cfgs)
465 return -EINVAL;
466
467 wm8994->retune_mobile_cfg[block] = value;
468
469 wm8994_set_retune_mobile(codec, block);
470
471 return 0;
472}
473
474static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
475 struct snd_ctl_elem_value *ucontrol)
476{
477 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
478 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
479 int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
480
481 ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
482
483 return 0;
484}
485
486static const char *aif_chan_src_text[] = {
487 "Left", "Right"
488};
489
490static const struct soc_enum aif1adcl_src =
491 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
492
493static const struct soc_enum aif1adcr_src =
494 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
495
496static const struct soc_enum aif2adcl_src =
497 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
498
499static const struct soc_enum aif2adcr_src =
500 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
501
502static const struct soc_enum aif1dacl_src =
503 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
504
505static const struct soc_enum aif1dacr_src =
506 SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
507
508static const struct soc_enum aif2dacl_src =
509 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
510
511static const struct soc_enum aif2dacr_src =
512 SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
513
514static const char *osr_text[] = {
515 "Low Power", "High Performance",
516};
517
518static const struct soc_enum dac_osr =
519 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 0, 2, osr_text);
520
521static const struct soc_enum adc_osr =
522 SOC_ENUM_SINGLE(WM8994_OVERSAMPLING, 1, 2, osr_text);
523
524static const struct snd_kcontrol_new wm8994_snd_controls[] = {
525SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
526 WM8994_AIF1_ADC1_RIGHT_VOLUME,
527 1, 119, 0, digital_tlv),
528SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
529 WM8994_AIF1_ADC2_RIGHT_VOLUME,
530 1, 119, 0, digital_tlv),
531SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
532 WM8994_AIF2_ADC_RIGHT_VOLUME,
533 1, 119, 0, digital_tlv),
534
535SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
536SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
537SOC_ENUM("AIF2ADCL Source", aif2adcl_src),
538SOC_ENUM("AIF2ADCR Source", aif2adcr_src),
539
540SOC_ENUM("AIF1DACL Source", aif1dacl_src),
541SOC_ENUM("AIF1DACR Source", aif1dacr_src),
542SOC_ENUM("AIF2DACL Source", aif2dacl_src),
543SOC_ENUM("AIF2DACR Source", aif2dacr_src),
544
545SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
546 WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
547SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
548 WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
549SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
550 WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
551
552SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
553SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
554
555SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
556SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
557SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
558
559WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
560WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
561WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
562
563WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
564WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
565WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
566
567WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
568WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
569WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
570
571SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
572 5, 12, 0, st_tlv),
573SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
574 0, 12, 0, st_tlv),
575SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
576 5, 12, 0, st_tlv),
577SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
578 0, 12, 0, st_tlv),
579SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
580SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
581
582SOC_ENUM("AIF1ADC1 HPF Mode", aif1adc1_hpf),
583SOC_DOUBLE("AIF1ADC1 HPF Switch", WM8994_AIF1_ADC1_FILTERS, 12, 11, 1, 0),
584
585SOC_ENUM("AIF1ADC2 HPF Mode", aif1adc2_hpf),
586SOC_DOUBLE("AIF1ADC2 HPF Switch", WM8994_AIF1_ADC2_FILTERS, 12, 11, 1, 0),
587
588SOC_ENUM("AIF2ADC HPF Mode", aif2adc_hpf),
589SOC_DOUBLE("AIF2ADC HPF Switch", WM8994_AIF2_ADC_FILTERS, 12, 11, 1, 0),
590
591SOC_ENUM("ADC OSR", adc_osr),
592SOC_ENUM("DAC OSR", dac_osr),
593
594SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
595 WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
596SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
597 WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
598
599SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
600 WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
601SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
602 WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
603
604SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
605 6, 1, 1, wm_hubs_spkmix_tlv),
606SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
607 2, 1, 1, wm_hubs_spkmix_tlv),
608
609SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
610 6, 1, 1, wm_hubs_spkmix_tlv),
611SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
612 2, 1, 1, wm_hubs_spkmix_tlv),
613
614SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
615 10, 15, 0, wm8994_3d_tlv),
616SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC1_FILTERS_2,
617 8, 1, 0),
618SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
619 10, 15, 0, wm8994_3d_tlv),
620SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
621 8, 1, 0),
622SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF2_DAC_FILTERS_2,
623 10, 15, 0, wm8994_3d_tlv),
624SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF2_DAC_FILTERS_2,
625 8, 1, 0),
626};
627
628static const struct snd_kcontrol_new wm8994_eq_controls[] = {
629SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
630 eq_tlv),
631SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
632 eq_tlv),
633SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
634 eq_tlv),
635SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
636 eq_tlv),
637SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
638 eq_tlv),
639
640SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
641 eq_tlv),
642SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
643 eq_tlv),
644SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
645 eq_tlv),
646SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
647 eq_tlv),
648SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
649 eq_tlv),
650
651SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
652 eq_tlv),
653SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
654 eq_tlv),
655SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
656 eq_tlv),
657SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
658 eq_tlv),
659SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
660 eq_tlv),
661};
662
663static const struct snd_kcontrol_new wm8958_snd_controls[] = {
664SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
665};
666
667static int clk_sys_event(struct snd_soc_dapm_widget *w,
668 struct snd_kcontrol *kcontrol, int event)
669{
670 struct snd_soc_codec *codec = w->codec;
671
672 switch (event) {
673 case SND_SOC_DAPM_PRE_PMU:
674 return configure_clock(codec);
675
676 case SND_SOC_DAPM_POST_PMD:
677 configure_clock(codec);
678 break;
679 }
680
681 return 0;
682}
683
684static void wm8994_update_class_w(struct snd_soc_codec *codec)
685{
686 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
687 int enable = 1;
688 int source = 0; /* GCC flow analysis can't track enable */
689 int reg, reg_r;
690
691 /* Only support direct DAC->headphone paths */
692 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
693 if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
694 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
695 enable = 0;
696 }
697
698 reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
699 if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
700 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
701 enable = 0;
702 }
703
704 /* We also need the same setting for L/R and only one path */
705 reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
706 switch (reg) {
707 case WM8994_AIF2DACL_TO_DAC1L:
708 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
709 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
710 break;
711 case WM8994_AIF1DAC2L_TO_DAC1L:
712 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
713 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
714 break;
715 case WM8994_AIF1DAC1L_TO_DAC1L:
716 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
717 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
718 break;
719 default:
720 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
721 enable = 0;
722 break;
723 }
724
725 reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
726 if (reg_r != reg) {
727 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
728 enable = 0;
729 }
730
731 if (enable) {
732 dev_dbg(codec->dev, "Class W enabled\n");
733 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
734 WM8994_CP_DYN_PWR |
735 WM8994_CP_DYN_SRC_SEL_MASK,
736 source | WM8994_CP_DYN_PWR);
737 wm8994->hubs.class_w = true;
738
739 } else {
740 dev_dbg(codec->dev, "Class W disabled\n");
741 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
742 WM8994_CP_DYN_PWR, 0);
743 wm8994->hubs.class_w = false;
744 }
745}
746
747static int late_enable_ev(struct snd_soc_dapm_widget *w,
748 struct snd_kcontrol *kcontrol, int event)
749{
750 struct snd_soc_codec *codec = w->codec;
751 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
752
753 switch (event) {
754 case SND_SOC_DAPM_PRE_PMU:
755 if (wm8994->aif1clk_enable) {
756 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
757 WM8994_AIF1CLK_ENA_MASK,
758 WM8994_AIF1CLK_ENA);
759 wm8994->aif1clk_enable = 0;
760 }
761 if (wm8994->aif2clk_enable) {
762 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
763 WM8994_AIF2CLK_ENA_MASK,
764 WM8994_AIF2CLK_ENA);
765 wm8994->aif2clk_enable = 0;
766 }
767 break;
768 }
769
770 /* We may also have postponed startup of DSP, handle that. */
771 wm8958_aif_ev(w, kcontrol, event);
772
773 return 0;
774}
775
776static int late_disable_ev(struct snd_soc_dapm_widget *w,
777 struct snd_kcontrol *kcontrol, int event)
778{
779 struct snd_soc_codec *codec = w->codec;
780 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
781
782 switch (event) {
783 case SND_SOC_DAPM_POST_PMD:
784 if (wm8994->aif1clk_disable) {
785 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
786 WM8994_AIF1CLK_ENA_MASK, 0);
787 wm8994->aif1clk_disable = 0;
788 }
789 if (wm8994->aif2clk_disable) {
790 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
791 WM8994_AIF2CLK_ENA_MASK, 0);
792 wm8994->aif2clk_disable = 0;
793 }
794 break;
795 }
796
797 return 0;
798}
799
800static int aif1clk_ev(struct snd_soc_dapm_widget *w,
801 struct snd_kcontrol *kcontrol, int event)
802{
803 struct snd_soc_codec *codec = w->codec;
804 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
805
806 switch (event) {
807 case SND_SOC_DAPM_PRE_PMU:
808 wm8994->aif1clk_enable = 1;
809 break;
810 case SND_SOC_DAPM_POST_PMD:
811 wm8994->aif1clk_disable = 1;
812 break;
813 }
814
815 return 0;
816}
817
818static int aif2clk_ev(struct snd_soc_dapm_widget *w,
819 struct snd_kcontrol *kcontrol, int event)
820{
821 struct snd_soc_codec *codec = w->codec;
822 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
823
824 switch (event) {
825 case SND_SOC_DAPM_PRE_PMU:
826 wm8994->aif2clk_enable = 1;
827 break;
828 case SND_SOC_DAPM_POST_PMD:
829 wm8994->aif2clk_disable = 1;
830 break;
831 }
832
833 return 0;
834}
835
836static int adc_mux_ev(struct snd_soc_dapm_widget *w,
837 struct snd_kcontrol *kcontrol, int event)
838{
839 late_enable_ev(w, kcontrol, event);
840 return 0;
841}
842
843static int micbias_ev(struct snd_soc_dapm_widget *w,
844 struct snd_kcontrol *kcontrol, int event)
845{
846 late_enable_ev(w, kcontrol, event);
847 return 0;
848}
849
850static int dac_ev(struct snd_soc_dapm_widget *w,
851 struct snd_kcontrol *kcontrol, int event)
852{
853 struct snd_soc_codec *codec = w->codec;
854 unsigned int mask = 1 << w->shift;
855
856 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
857 mask, mask);
858 return 0;
859}
860
861static const char *hp_mux_text[] = {
862 "Mixer",
863 "DAC",
864};
865
866#define WM8994_HP_ENUM(xname, xenum) \
867{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
868 .info = snd_soc_info_enum_double, \
869 .get = snd_soc_dapm_get_enum_double, \
870 .put = wm8994_put_hp_enum, \
871 .private_value = (unsigned long)&xenum }
872
873static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
874 struct snd_ctl_elem_value *ucontrol)
875{
876 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
877 struct snd_soc_dapm_widget *w = wlist->widgets[0];
878 struct snd_soc_codec *codec = w->codec;
879 int ret;
880
881 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
882
883 wm8994_update_class_w(codec);
884
885 return ret;
886}
887
888static const struct soc_enum hpl_enum =
889 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
890
891static const struct snd_kcontrol_new hpl_mux =
892 WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
893
894static const struct soc_enum hpr_enum =
895 SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
896
897static const struct snd_kcontrol_new hpr_mux =
898 WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
899
900static const char *adc_mux_text[] = {
901 "ADC",
902 "DMIC",
903};
904
905static const struct soc_enum adc_enum =
906 SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
907
908static const struct snd_kcontrol_new adcl_mux =
909 SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
910
911static const struct snd_kcontrol_new adcr_mux =
912 SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
913
914static const struct snd_kcontrol_new left_speaker_mixer[] = {
915SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
916SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
917SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
918SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
919SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
920};
921
922static const struct snd_kcontrol_new right_speaker_mixer[] = {
923SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
924SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
925SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
926SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
927SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
928};
929
930/* Debugging; dump chip status after DAPM transitions */
931static int post_ev(struct snd_soc_dapm_widget *w,
932 struct snd_kcontrol *kcontrol, int event)
933{
934 struct snd_soc_codec *codec = w->codec;
935 dev_dbg(codec->dev, "SRC status: %x\n",
936 snd_soc_read(codec,
937 WM8994_RATE_STATUS));
938 return 0;
939}
940
941static const struct snd_kcontrol_new aif1adc1l_mix[] = {
942SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
943 1, 1, 0),
944SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
945 0, 1, 0),
946};
947
948static const struct snd_kcontrol_new aif1adc1r_mix[] = {
949SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
950 1, 1, 0),
951SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
952 0, 1, 0),
953};
954
955static const struct snd_kcontrol_new aif1adc2l_mix[] = {
956SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
957 1, 1, 0),
958SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
959 0, 1, 0),
960};
961
962static const struct snd_kcontrol_new aif1adc2r_mix[] = {
963SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
964 1, 1, 0),
965SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
966 0, 1, 0),
967};
968
969static const struct snd_kcontrol_new aif2dac2l_mix[] = {
970SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
971 5, 1, 0),
972SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
973 4, 1, 0),
974SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
975 2, 1, 0),
976SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
977 1, 1, 0),
978SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
979 0, 1, 0),
980};
981
982static const struct snd_kcontrol_new aif2dac2r_mix[] = {
983SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
984 5, 1, 0),
985SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
986 4, 1, 0),
987SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
988 2, 1, 0),
989SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
990 1, 1, 0),
991SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
992 0, 1, 0),
993};
994
995#define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
996{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
997 .info = snd_soc_info_volsw, \
998 .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
999 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
1000
1001static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1002 struct snd_ctl_elem_value *ucontrol)
1003{
1004 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
1005 struct snd_soc_dapm_widget *w = wlist->widgets[0];
1006 struct snd_soc_codec *codec = w->codec;
1007 int ret;
1008
1009 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1010
1011 wm8994_update_class_w(codec);
1012
1013 return ret;
1014}
1015
1016static const struct snd_kcontrol_new dac1l_mix[] = {
1017WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1018 5, 1, 0),
1019WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1020 4, 1, 0),
1021WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1022 2, 1, 0),
1023WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1024 1, 1, 0),
1025WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1026 0, 1, 0),
1027};
1028
1029static const struct snd_kcontrol_new dac1r_mix[] = {
1030WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1031 5, 1, 0),
1032WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1033 4, 1, 0),
1034WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1035 2, 1, 0),
1036WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1037 1, 1, 0),
1038WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1039 0, 1, 0),
1040};
1041
1042static const char *sidetone_text[] = {
1043 "ADC/DMIC1", "DMIC2",
1044};
1045
1046static const struct soc_enum sidetone1_enum =
1047 SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1048
1049static const struct snd_kcontrol_new sidetone1_mux =
1050 SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1051
1052static const struct soc_enum sidetone2_enum =
1053 SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1054
1055static const struct snd_kcontrol_new sidetone2_mux =
1056 SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1057
1058static const char *aif1dac_text[] = {
1059 "AIF1DACDAT", "AIF3DACDAT",
1060};
1061
1062static const struct soc_enum aif1dac_enum =
1063 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1064
1065static const struct snd_kcontrol_new aif1dac_mux =
1066 SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1067
1068static const char *aif2dac_text[] = {
1069 "AIF2DACDAT", "AIF3DACDAT",
1070};
1071
1072static const struct soc_enum aif2dac_enum =
1073 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1074
1075static const struct snd_kcontrol_new aif2dac_mux =
1076 SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1077
1078static const char *aif2adc_text[] = {
1079 "AIF2ADCDAT", "AIF3DACDAT",
1080};
1081
1082static const struct soc_enum aif2adc_enum =
1083 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1084
1085static const struct snd_kcontrol_new aif2adc_mux =
1086 SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1087
1088static const char *aif3adc_text[] = {
1089 "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1090};
1091
1092static const struct soc_enum wm8994_aif3adc_enum =
1093 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1094
1095static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1096 SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1097
1098static const struct soc_enum wm8958_aif3adc_enum =
1099 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1100
1101static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1102 SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1103
1104static const char *mono_pcm_out_text[] = {
1105 "None", "AIF2ADCL", "AIF2ADCR",
1106};
1107
1108static const struct soc_enum mono_pcm_out_enum =
1109 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1110
1111static const struct snd_kcontrol_new mono_pcm_out_mux =
1112 SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1113
1114static const char *aif2dac_src_text[] = {
1115 "AIF2", "AIF3",
1116};
1117
1118/* Note that these two control shouldn't be simultaneously switched to AIF3 */
1119static const struct soc_enum aif2dacl_src_enum =
1120 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1121
1122static const struct snd_kcontrol_new aif2dacl_src_mux =
1123 SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1124
1125static const struct soc_enum aif2dacr_src_enum =
1126 SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1127
1128static const struct snd_kcontrol_new aif2dacr_src_mux =
1129 SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1130
1131static const struct snd_soc_dapm_widget wm8994_lateclk_revd_widgets[] = {
1132SND_SOC_DAPM_SUPPLY("AIF1CLK", SND_SOC_NOPM, 0, 0, aif1clk_ev,
1133 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1134SND_SOC_DAPM_SUPPLY("AIF2CLK", SND_SOC_NOPM, 0, 0, aif2clk_ev,
1135 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1136
1137SND_SOC_DAPM_PGA_E("Late DAC1L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1138 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1139SND_SOC_DAPM_PGA_E("Late DAC1R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1140 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1141SND_SOC_DAPM_PGA_E("Late DAC2L Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1142 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1143SND_SOC_DAPM_PGA_E("Late DAC2R Enable PGA", SND_SOC_NOPM, 0, 0, NULL, 0,
1144 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1145SND_SOC_DAPM_PGA_E("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0,
1146 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1147
1148SND_SOC_DAPM_MIXER_E("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1149 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer),
1150 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1151SND_SOC_DAPM_MIXER_E("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1152 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer),
1153 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1154SND_SOC_DAPM_MUX_E("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux,
1155 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1156SND_SOC_DAPM_MUX_E("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux,
1157 late_enable_ev, SND_SOC_DAPM_PRE_PMU),
1158
1159SND_SOC_DAPM_POST("Late Disable PGA", late_disable_ev)
1160};
1161
1162static const struct snd_soc_dapm_widget wm8994_lateclk_widgets[] = {
1163SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1164SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1165SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
1166SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1167 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1168SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1169 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1170SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1171SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1172};
1173
1174static const struct snd_soc_dapm_widget wm8994_dac_revd_widgets[] = {
1175SND_SOC_DAPM_DAC_E("DAC2L", NULL, SND_SOC_NOPM, 3, 0,
1176 dac_ev, SND_SOC_DAPM_PRE_PMU),
1177SND_SOC_DAPM_DAC_E("DAC2R", NULL, SND_SOC_NOPM, 2, 0,
1178 dac_ev, SND_SOC_DAPM_PRE_PMU),
1179SND_SOC_DAPM_DAC_E("DAC1L", NULL, SND_SOC_NOPM, 1, 0,
1180 dac_ev, SND_SOC_DAPM_PRE_PMU),
1181SND_SOC_DAPM_DAC_E("DAC1R", NULL, SND_SOC_NOPM, 0, 0,
1182 dac_ev, SND_SOC_DAPM_PRE_PMU),
1183};
1184
1185static const struct snd_soc_dapm_widget wm8994_dac_widgets[] = {
1186SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1187SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1188SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1189SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1190};
1191
1192static const struct snd_soc_dapm_widget wm8994_adc_revd_widgets[] = {
1193SND_SOC_DAPM_MUX_E("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux,
1194 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1195SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1196 adc_mux_ev, SND_SOC_DAPM_PRE_PMU),
1197};
1198
1199static const struct snd_soc_dapm_widget wm8994_adc_widgets[] = {
1200SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1201SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1202};
1203
1204static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1205SND_SOC_DAPM_INPUT("DMIC1DAT"),
1206SND_SOC_DAPM_INPUT("DMIC2DAT"),
1207SND_SOC_DAPM_INPUT("Clock"),
1208
1209SND_SOC_DAPM_SUPPLY_S("MICBIAS Supply", 1, SND_SOC_NOPM, 0, 0, micbias_ev,
1210 SND_SOC_DAPM_PRE_PMU),
1211
1212SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1213 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1214
1215SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1216SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1217SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1218
1219SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", NULL,
1220 0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1221SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", NULL,
1222 0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1223SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1224 WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1225 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1226SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1227 WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1228 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1229
1230SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", NULL,
1231 0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1232SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", NULL,
1233 0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1234SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1235 WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1236 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1237SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1238 WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1239 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1240
1241SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1242 aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1243SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1244 aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1245
1246SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1247 aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1248SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1249 aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1250
1251SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1252 aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1253SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1254 aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1255
1256SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1257SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1258
1259SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1260 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1261SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1262 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1263
1264SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1265 WM8994_POWER_MANAGEMENT_4, 13, 0),
1266SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1267 WM8994_POWER_MANAGEMENT_4, 12, 0),
1268SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1269 WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1270 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1271SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1272 WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1273 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1274
1275SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1276SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1277SND_SOC_DAPM_AIF_OUT("AIF1ADCDAT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1278SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1279
1280SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1281SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1282SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1283
1284SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1285SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1286
1287SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1288
1289SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1290SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1291SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1292SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1293
1294/* Power is done with the muxes since the ADC power also controls the
1295 * downsampling chain, the chip will automatically manage the analogue
1296 * specific portions.
1297 */
1298SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1299SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1300
1301SND_SOC_DAPM_POST("Debug log", post_ev),
1302};
1303
1304static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1305SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1306};
1307
1308static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1309SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1310SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1311SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1312SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1313};
1314
1315static const struct snd_soc_dapm_route intercon[] = {
1316 { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1317 { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1318
1319 { "DSP1CLK", NULL, "CLK_SYS" },
1320 { "DSP2CLK", NULL, "CLK_SYS" },
1321 { "DSPINTCLK", NULL, "CLK_SYS" },
1322
1323 { "AIF1ADC1L", NULL, "AIF1CLK" },
1324 { "AIF1ADC1L", NULL, "DSP1CLK" },
1325 { "AIF1ADC1R", NULL, "AIF1CLK" },
1326 { "AIF1ADC1R", NULL, "DSP1CLK" },
1327 { "AIF1ADC1R", NULL, "DSPINTCLK" },
1328
1329 { "AIF1DAC1L", NULL, "AIF1CLK" },
1330 { "AIF1DAC1L", NULL, "DSP1CLK" },
1331 { "AIF1DAC1R", NULL, "AIF1CLK" },
1332 { "AIF1DAC1R", NULL, "DSP1CLK" },
1333 { "AIF1DAC1R", NULL, "DSPINTCLK" },
1334
1335 { "AIF1ADC2L", NULL, "AIF1CLK" },
1336 { "AIF1ADC2L", NULL, "DSP1CLK" },
1337 { "AIF1ADC2R", NULL, "AIF1CLK" },
1338 { "AIF1ADC2R", NULL, "DSP1CLK" },
1339 { "AIF1ADC2R", NULL, "DSPINTCLK" },
1340
1341 { "AIF1DAC2L", NULL, "AIF1CLK" },
1342 { "AIF1DAC2L", NULL, "DSP1CLK" },
1343 { "AIF1DAC2R", NULL, "AIF1CLK" },
1344 { "AIF1DAC2R", NULL, "DSP1CLK" },
1345 { "AIF1DAC2R", NULL, "DSPINTCLK" },
1346
1347 { "AIF2ADCL", NULL, "AIF2CLK" },
1348 { "AIF2ADCL", NULL, "DSP2CLK" },
1349 { "AIF2ADCR", NULL, "AIF2CLK" },
1350 { "AIF2ADCR", NULL, "DSP2CLK" },
1351 { "AIF2ADCR", NULL, "DSPINTCLK" },
1352
1353 { "AIF2DACL", NULL, "AIF2CLK" },
1354 { "AIF2DACL", NULL, "DSP2CLK" },
1355 { "AIF2DACR", NULL, "AIF2CLK" },
1356 { "AIF2DACR", NULL, "DSP2CLK" },
1357 { "AIF2DACR", NULL, "DSPINTCLK" },
1358
1359 { "DMIC1L", NULL, "DMIC1DAT" },
1360 { "DMIC1L", NULL, "CLK_SYS" },
1361 { "DMIC1R", NULL, "DMIC1DAT" },
1362 { "DMIC1R", NULL, "CLK_SYS" },
1363 { "DMIC2L", NULL, "DMIC2DAT" },
1364 { "DMIC2L", NULL, "CLK_SYS" },
1365 { "DMIC2R", NULL, "DMIC2DAT" },
1366 { "DMIC2R", NULL, "CLK_SYS" },
1367
1368 { "ADCL", NULL, "AIF1CLK" },
1369 { "ADCL", NULL, "DSP1CLK" },
1370 { "ADCL", NULL, "DSPINTCLK" },
1371
1372 { "ADCR", NULL, "AIF1CLK" },
1373 { "ADCR", NULL, "DSP1CLK" },
1374 { "ADCR", NULL, "DSPINTCLK" },
1375
1376 { "ADCL Mux", "ADC", "ADCL" },
1377 { "ADCL Mux", "DMIC", "DMIC1L" },
1378 { "ADCR Mux", "ADC", "ADCR" },
1379 { "ADCR Mux", "DMIC", "DMIC1R" },
1380
1381 { "DAC1L", NULL, "AIF1CLK" },
1382 { "DAC1L", NULL, "DSP1CLK" },
1383 { "DAC1L", NULL, "DSPINTCLK" },
1384
1385 { "DAC1R", NULL, "AIF1CLK" },
1386 { "DAC1R", NULL, "DSP1CLK" },
1387 { "DAC1R", NULL, "DSPINTCLK" },
1388
1389 { "DAC2L", NULL, "AIF2CLK" },
1390 { "DAC2L", NULL, "DSP2CLK" },
1391 { "DAC2L", NULL, "DSPINTCLK" },
1392
1393 { "DAC2R", NULL, "AIF2DACR" },
1394 { "DAC2R", NULL, "AIF2CLK" },
1395 { "DAC2R", NULL, "DSP2CLK" },
1396 { "DAC2R", NULL, "DSPINTCLK" },
1397
1398 { "TOCLK", NULL, "CLK_SYS" },
1399
1400 /* AIF1 outputs */
1401 { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1402 { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1403 { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1404
1405 { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1406 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1407 { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1408
1409 { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1410 { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1411 { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1412
1413 { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1414 { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1415 { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1416
1417 /* Pin level routing for AIF3 */
1418 { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1419 { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1420 { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1421 { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1422
1423 { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1424 { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1425 { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1426 { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1427 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1428 { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1429 { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1430
1431 /* DAC1 inputs */
1432 { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1433 { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1434 { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1435 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1436 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1437
1438 { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1439 { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1440 { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1441 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1442 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1443
1444 /* DAC2/AIF2 outputs */
1445 { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1446 { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1447 { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1448 { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1449 { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1450 { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1451
1452 { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1453 { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1454 { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1455 { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1456 { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1457 { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1458
1459 { "AIF1ADCDAT", NULL, "AIF1ADC1L" },
1460 { "AIF1ADCDAT", NULL, "AIF1ADC1R" },
1461 { "AIF1ADCDAT", NULL, "AIF1ADC2L" },
1462 { "AIF1ADCDAT", NULL, "AIF1ADC2R" },
1463
1464 { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1465
1466 /* AIF3 output */
1467 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1468 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1469 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1470 { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1471 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1472 { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1473 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1474 { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1475
1476 /* Sidetone */
1477 { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1478 { "Left Sidetone", "DMIC2", "DMIC2L" },
1479 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1480 { "Right Sidetone", "DMIC2", "DMIC2R" },
1481
1482 /* Output stages */
1483 { "Left Output Mixer", "DAC Switch", "DAC1L" },
1484 { "Right Output Mixer", "DAC Switch", "DAC1R" },
1485
1486 { "SPKL", "DAC1 Switch", "DAC1L" },
1487 { "SPKL", "DAC2 Switch", "DAC2L" },
1488
1489 { "SPKR", "DAC1 Switch", "DAC1R" },
1490 { "SPKR", "DAC2 Switch", "DAC2R" },
1491
1492 { "Left Headphone Mux", "DAC", "DAC1L" },
1493 { "Right Headphone Mux", "DAC", "DAC1R" },
1494};
1495
1496static const struct snd_soc_dapm_route wm8994_lateclk_revd_intercon[] = {
1497 { "DAC1L", NULL, "Late DAC1L Enable PGA" },
1498 { "Late DAC1L Enable PGA", NULL, "DAC1L Mixer" },
1499 { "DAC1R", NULL, "Late DAC1R Enable PGA" },
1500 { "Late DAC1R Enable PGA", NULL, "DAC1R Mixer" },
1501 { "DAC2L", NULL, "Late DAC2L Enable PGA" },
1502 { "Late DAC2L Enable PGA", NULL, "AIF2DAC2L Mixer" },
1503 { "DAC2R", NULL, "Late DAC2R Enable PGA" },
1504 { "Late DAC2R Enable PGA", NULL, "AIF2DAC2R Mixer" }
1505};
1506
1507static const struct snd_soc_dapm_route wm8994_lateclk_intercon[] = {
1508 { "DAC1L", NULL, "DAC1L Mixer" },
1509 { "DAC1R", NULL, "DAC1R Mixer" },
1510 { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1511 { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1512};
1513
1514static const struct snd_soc_dapm_route wm8994_revd_intercon[] = {
1515 { "AIF1DACDAT", NULL, "AIF2DACDAT" },
1516 { "AIF2DACDAT", NULL, "AIF1DACDAT" },
1517 { "AIF1ADCDAT", NULL, "AIF2ADCDAT" },
1518 { "AIF2ADCDAT", NULL, "AIF1ADCDAT" },
1519 { "MICBIAS1", NULL, "CLK_SYS" },
1520 { "MICBIAS1", NULL, "MICBIAS Supply" },
1521 { "MICBIAS2", NULL, "CLK_SYS" },
1522 { "MICBIAS2", NULL, "MICBIAS Supply" },
1523};
1524
1525static const struct snd_soc_dapm_route wm8994_intercon[] = {
1526 { "AIF2DACL", NULL, "AIF2DAC Mux" },
1527 { "AIF2DACR", NULL, "AIF2DAC Mux" },
1528};
1529
1530static const struct snd_soc_dapm_route wm8958_intercon[] = {
1531 { "AIF2DACL", NULL, "AIF2DACL Mux" },
1532 { "AIF2DACR", NULL, "AIF2DACR Mux" },
1533
1534 { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1535 { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1536 { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1537 { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1538
1539 { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1540 { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1541
1542 { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1543};
1544
1545/* The size in bits of the FLL divide multiplied by 10
1546 * to allow rounding later */
1547#define FIXED_FLL_SIZE ((1 << 16) * 10)
1548
1549struct fll_div {
1550 u16 outdiv;
1551 u16 n;
1552 u16 k;
1553 u16 clk_ref_div;
1554 u16 fll_fratio;
1555};
1556
1557static int wm8994_get_fll_config(struct fll_div *fll,
1558 int freq_in, int freq_out)
1559{
1560 u64 Kpart;
1561 unsigned int K, Ndiv, Nmod;
1562
1563 pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1564
1565 /* Scale the input frequency down to <= 13.5MHz */
1566 fll->clk_ref_div = 0;
1567 while (freq_in > 13500000) {
1568 fll->clk_ref_div++;
1569 freq_in /= 2;
1570
1571 if (fll->clk_ref_div > 3)
1572 return -EINVAL;
1573 }
1574 pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1575
1576 /* Scale the output to give 90MHz<=Fvco<=100MHz */
1577 fll->outdiv = 3;
1578 while (freq_out * (fll->outdiv + 1) < 90000000) {
1579 fll->outdiv++;
1580 if (fll->outdiv > 63)
1581 return -EINVAL;
1582 }
1583 freq_out *= fll->outdiv + 1;
1584 pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1585
1586 if (freq_in > 1000000) {
1587 fll->fll_fratio = 0;
1588 } else if (freq_in > 256000) {
1589 fll->fll_fratio = 1;
1590 freq_in *= 2;
1591 } else if (freq_in > 128000) {
1592 fll->fll_fratio = 2;
1593 freq_in *= 4;
1594 } else if (freq_in > 64000) {
1595 fll->fll_fratio = 3;
1596 freq_in *= 8;
1597 } else {
1598 fll->fll_fratio = 4;
1599 freq_in *= 16;
1600 }
1601 pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1602
1603 /* Now, calculate N.K */
1604 Ndiv = freq_out / freq_in;
1605
1606 fll->n = Ndiv;
1607 Nmod = freq_out % freq_in;
1608 pr_debug("Nmod=%d\n", Nmod);
1609
1610 /* Calculate fractional part - scale up so we can round. */
1611 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1612
1613 do_div(Kpart, freq_in);
1614
1615 K = Kpart & 0xFFFFFFFF;
1616
1617 if ((K % 10) >= 5)
1618 K += 5;
1619
1620 /* Move down to proper range now rounding is done */
1621 fll->k = K / 10;
1622
1623 pr_debug("N=%x K=%x\n", fll->n, fll->k);
1624
1625 return 0;
1626}
1627
1628static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1629 unsigned int freq_in, unsigned int freq_out)
1630{
1631 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1632 int reg_offset, ret;
1633 struct fll_div fll;
1634 u16 reg, aif1, aif2;
1635 unsigned long timeout;
1636
1637 aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1638 & WM8994_AIF1CLK_ENA;
1639
1640 aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1641 & WM8994_AIF2CLK_ENA;
1642
1643 switch (id) {
1644 case WM8994_FLL1:
1645 reg_offset = 0;
1646 id = 0;
1647 break;
1648 case WM8994_FLL2:
1649 reg_offset = 0x20;
1650 id = 1;
1651 break;
1652 default:
1653 return -EINVAL;
1654 }
1655
1656 switch (src) {
1657 case 0:
1658 /* Allow no source specification when stopping */
1659 if (freq_out)
1660 return -EINVAL;
1661 src = wm8994->fll[id].src;
1662 break;
1663 case WM8994_FLL_SRC_MCLK1:
1664 case WM8994_FLL_SRC_MCLK2:
1665 case WM8994_FLL_SRC_LRCLK:
1666 case WM8994_FLL_SRC_BCLK:
1667 break;
1668 default:
1669 return -EINVAL;
1670 }
1671
1672 /* Are we changing anything? */
1673 if (wm8994->fll[id].src == src &&
1674 wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1675 return 0;
1676
1677 /* If we're stopping the FLL redo the old config - no
1678 * registers will actually be written but we avoid GCC flow
1679 * analysis bugs spewing warnings.
1680 */
1681 if (freq_out)
1682 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1683 else
1684 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1685 wm8994->fll[id].out);
1686 if (ret < 0)
1687 return ret;
1688
1689 /* Gate the AIF clocks while we reclock */
1690 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1691 WM8994_AIF1CLK_ENA, 0);
1692 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1693 WM8994_AIF2CLK_ENA, 0);
1694
1695 /* We always need to disable the FLL while reconfiguring */
1696 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1697 WM8994_FLL1_ENA, 0);
1698
1699 reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1700 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1701 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1702 WM8994_FLL1_OUTDIV_MASK |
1703 WM8994_FLL1_FRATIO_MASK, reg);
1704
1705 snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1706
1707 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1708 WM8994_FLL1_N_MASK,
1709 fll.n << WM8994_FLL1_N_SHIFT);
1710
1711 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1712 WM8994_FLL1_REFCLK_DIV_MASK |
1713 WM8994_FLL1_REFCLK_SRC_MASK,
1714 (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1715 (src - 1));
1716
1717 /* Clear any pending completion from a previous failure */
1718 try_wait_for_completion(&wm8994->fll_locked[id]);
1719
1720 /* Enable (with fractional mode if required) */
1721 if (freq_out) {
1722 if (fll.k)
1723 reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1724 else
1725 reg = WM8994_FLL1_ENA;
1726 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1727 WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1728 reg);
1729
1730 if (wm8994->fll_locked_irq) {
1731 timeout = wait_for_completion_timeout(&wm8994->fll_locked[id],
1732 msecs_to_jiffies(10));
1733 if (timeout == 0)
1734 dev_warn(codec->dev,
1735 "Timed out waiting for FLL lock\n");
1736 } else {
1737 msleep(5);
1738 }
1739 }
1740
1741 wm8994->fll[id].in = freq_in;
1742 wm8994->fll[id].out = freq_out;
1743 wm8994->fll[id].src = src;
1744
1745 /* Enable any gated AIF clocks */
1746 snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1747 WM8994_AIF1CLK_ENA, aif1);
1748 snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1749 WM8994_AIF2CLK_ENA, aif2);
1750
1751 configure_clock(codec);
1752
1753 return 0;
1754}
1755
1756static irqreturn_t wm8994_fll_locked_irq(int irq, void *data)
1757{
1758 struct completion *completion = data;
1759
1760 complete(completion);
1761
1762 return IRQ_HANDLED;
1763}
1764
1765static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1766
1767static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1768 unsigned int freq_in, unsigned int freq_out)
1769{
1770 return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1771}
1772
1773static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1774 int clk_id, unsigned int freq, int dir)
1775{
1776 struct snd_soc_codec *codec = dai->codec;
1777 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1778 int i;
1779
1780 switch (dai->id) {
1781 case 1:
1782 case 2:
1783 break;
1784
1785 default:
1786 /* AIF3 shares clocking with AIF1/2 */
1787 return -EINVAL;
1788 }
1789
1790 switch (clk_id) {
1791 case WM8994_SYSCLK_MCLK1:
1792 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1793 wm8994->mclk[0] = freq;
1794 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1795 dai->id, freq);
1796 break;
1797
1798 case WM8994_SYSCLK_MCLK2:
1799 /* TODO: Set GPIO AF */
1800 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1801 wm8994->mclk[1] = freq;
1802 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1803 dai->id, freq);
1804 break;
1805
1806 case WM8994_SYSCLK_FLL1:
1807 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1808 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1809 break;
1810
1811 case WM8994_SYSCLK_FLL2:
1812 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1813 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1814 break;
1815
1816 case WM8994_SYSCLK_OPCLK:
1817 /* Special case - a division (times 10) is given and
1818 * no effect on main clocking.
1819 */
1820 if (freq) {
1821 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1822 if (opclk_divs[i] == freq)
1823 break;
1824 if (i == ARRAY_SIZE(opclk_divs))
1825 return -EINVAL;
1826 snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1827 WM8994_OPCLK_DIV_MASK, i);
1828 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1829 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1830 } else {
1831 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1832 WM8994_OPCLK_ENA, 0);
1833 }
1834
1835 default:
1836 return -EINVAL;
1837 }
1838
1839 configure_clock(codec);
1840
1841 return 0;
1842}
1843
1844static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1845 enum snd_soc_bias_level level)
1846{
1847 struct wm8994 *control = codec->control_data;
1848 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1849
1850 switch (level) {
1851 case SND_SOC_BIAS_ON:
1852 break;
1853
1854 case SND_SOC_BIAS_PREPARE:
1855 /* VMID=2x40k */
1856 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1857 WM8994_VMID_SEL_MASK, 0x2);
1858 break;
1859
1860 case SND_SOC_BIAS_STANDBY:
1861 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1862 pm_runtime_get_sync(codec->dev);
1863
1864 switch (control->type) {
1865 case WM8994:
1866 if (wm8994->revision < 4) {
1867 /* Tweak DC servo and DSP
1868 * configuration for improved
1869 * performance. */
1870 snd_soc_write(codec, 0x102, 0x3);
1871 snd_soc_write(codec, 0x56, 0x3);
1872 snd_soc_write(codec, 0x817, 0);
1873 snd_soc_write(codec, 0x102, 0);
1874 }
1875 break;
1876
1877 case WM8958:
1878 if (wm8994->revision == 0) {
1879 /* Optimise performance for rev A */
1880 snd_soc_write(codec, 0x102, 0x3);
1881 snd_soc_write(codec, 0xcb, 0x81);
1882 snd_soc_write(codec, 0x817, 0);
1883 snd_soc_write(codec, 0x102, 0);
1884
1885 snd_soc_update_bits(codec,
1886 WM8958_CHARGE_PUMP_2,
1887 WM8958_CP_DISCH,
1888 WM8958_CP_DISCH);
1889 }
1890 break;
1891 }
1892
1893 /* Discharge LINEOUT1 & 2 */
1894 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1895 WM8994_LINEOUT1_DISCH |
1896 WM8994_LINEOUT2_DISCH,
1897 WM8994_LINEOUT1_DISCH |
1898 WM8994_LINEOUT2_DISCH);
1899
1900 /* Startup bias, VMID ramp & buffer */
1901 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1902 WM8994_STARTUP_BIAS_ENA |
1903 WM8994_VMID_BUF_ENA |
1904 WM8994_VMID_RAMP_MASK,
1905 WM8994_STARTUP_BIAS_ENA |
1906 WM8994_VMID_BUF_ENA |
1907 (0x11 << WM8994_VMID_RAMP_SHIFT));
1908
1909 /* Main bias enable, VMID=2x40k */
1910 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1911 WM8994_BIAS_ENA |
1912 WM8994_VMID_SEL_MASK,
1913 WM8994_BIAS_ENA | 0x2);
1914
1915 msleep(20);
1916 }
1917
1918 /* VMID=2x500k */
1919 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1920 WM8994_VMID_SEL_MASK, 0x4);
1921
1922 break;
1923
1924 case SND_SOC_BIAS_OFF:
1925 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1926 /* Switch over to startup biases */
1927 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1928 WM8994_BIAS_SRC |
1929 WM8994_STARTUP_BIAS_ENA |
1930 WM8994_VMID_BUF_ENA |
1931 WM8994_VMID_RAMP_MASK,
1932 WM8994_BIAS_SRC |
1933 WM8994_STARTUP_BIAS_ENA |
1934 WM8994_VMID_BUF_ENA |
1935 (1 << WM8994_VMID_RAMP_SHIFT));
1936
1937 /* Disable main biases */
1938 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1939 WM8994_BIAS_ENA |
1940 WM8994_VMID_SEL_MASK, 0);
1941
1942 /* Discharge line */
1943 snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1944 WM8994_LINEOUT1_DISCH |
1945 WM8994_LINEOUT2_DISCH,
1946 WM8994_LINEOUT1_DISCH |
1947 WM8994_LINEOUT2_DISCH);
1948
1949 msleep(5);
1950
1951 /* Switch off startup biases */
1952 snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1953 WM8994_BIAS_SRC |
1954 WM8994_STARTUP_BIAS_ENA |
1955 WM8994_VMID_BUF_ENA |
1956 WM8994_VMID_RAMP_MASK, 0);
1957
1958 wm8994->cur_fw = NULL;
1959
1960 pm_runtime_put(codec->dev);
1961 }
1962 break;
1963 }
1964 codec->dapm.bias_level = level;
1965 return 0;
1966}
1967
1968static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1969{
1970 struct snd_soc_codec *codec = dai->codec;
1971 struct wm8994 *control = codec->control_data;
1972 int ms_reg;
1973 int aif1_reg;
1974 int ms = 0;
1975 int aif1 = 0;
1976
1977 switch (dai->id) {
1978 case 1:
1979 ms_reg = WM8994_AIF1_MASTER_SLAVE;
1980 aif1_reg = WM8994_AIF1_CONTROL_1;
1981 break;
1982 case 2:
1983 ms_reg = WM8994_AIF2_MASTER_SLAVE;
1984 aif1_reg = WM8994_AIF2_CONTROL_1;
1985 break;
1986 default:
1987 return -EINVAL;
1988 }
1989
1990 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1991 case SND_SOC_DAIFMT_CBS_CFS:
1992 break;
1993 case SND_SOC_DAIFMT_CBM_CFM:
1994 ms = WM8994_AIF1_MSTR;
1995 break;
1996 default:
1997 return -EINVAL;
1998 }
1999
2000 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2001 case SND_SOC_DAIFMT_DSP_B:
2002 aif1 |= WM8994_AIF1_LRCLK_INV;
2003 case SND_SOC_DAIFMT_DSP_A:
2004 aif1 |= 0x18;
2005 break;
2006 case SND_SOC_DAIFMT_I2S:
2007 aif1 |= 0x10;
2008 break;
2009 case SND_SOC_DAIFMT_RIGHT_J:
2010 break;
2011 case SND_SOC_DAIFMT_LEFT_J:
2012 aif1 |= 0x8;
2013 break;
2014 default:
2015 return -EINVAL;
2016 }
2017
2018 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2019 case SND_SOC_DAIFMT_DSP_A:
2020 case SND_SOC_DAIFMT_DSP_B:
2021 /* frame inversion not valid for DSP modes */
2022 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2023 case SND_SOC_DAIFMT_NB_NF:
2024 break;
2025 case SND_SOC_DAIFMT_IB_NF:
2026 aif1 |= WM8994_AIF1_BCLK_INV;
2027 break;
2028 default:
2029 return -EINVAL;
2030 }
2031 break;
2032
2033 case SND_SOC_DAIFMT_I2S:
2034 case SND_SOC_DAIFMT_RIGHT_J:
2035 case SND_SOC_DAIFMT_LEFT_J:
2036 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2037 case SND_SOC_DAIFMT_NB_NF:
2038 break;
2039 case SND_SOC_DAIFMT_IB_IF:
2040 aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2041 break;
2042 case SND_SOC_DAIFMT_IB_NF:
2043 aif1 |= WM8994_AIF1_BCLK_INV;
2044 break;
2045 case SND_SOC_DAIFMT_NB_IF:
2046 aif1 |= WM8994_AIF1_LRCLK_INV;
2047 break;
2048 default:
2049 return -EINVAL;
2050 }
2051 break;
2052 default:
2053 return -EINVAL;
2054 }
2055
2056 /* The AIF2 format configuration needs to be mirrored to AIF3
2057 * on WM8958 if it's in use so just do it all the time. */
2058 if (control->type == WM8958 && dai->id == 2)
2059 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2060 WM8994_AIF1_LRCLK_INV |
2061 WM8958_AIF3_FMT_MASK, aif1);
2062
2063 snd_soc_update_bits(codec, aif1_reg,
2064 WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2065 WM8994_AIF1_FMT_MASK,
2066 aif1);
2067 snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2068 ms);
2069
2070 return 0;
2071}
2072
2073static struct {
2074 int val, rate;
2075} srs[] = {
2076 { 0, 8000 },
2077 { 1, 11025 },
2078 { 2, 12000 },
2079 { 3, 16000 },
2080 { 4, 22050 },
2081 { 5, 24000 },
2082 { 6, 32000 },
2083 { 7, 44100 },
2084 { 8, 48000 },
2085 { 9, 88200 },
2086 { 10, 96000 },
2087};
2088
2089static int fs_ratios[] = {
2090 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2091};
2092
2093static int bclk_divs[] = {
2094 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2095 640, 880, 960, 1280, 1760, 1920
2096};
2097
2098static int wm8994_hw_params(struct snd_pcm_substream *substream,
2099 struct snd_pcm_hw_params *params,
2100 struct snd_soc_dai *dai)
2101{
2102 struct snd_soc_codec *codec = dai->codec;
2103 struct wm8994 *control = codec->control_data;
2104 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2105 int aif1_reg;
2106 int aif2_reg;
2107 int bclk_reg;
2108 int lrclk_reg;
2109 int rate_reg;
2110 int aif1 = 0;
2111 int aif2 = 0;
2112 int bclk = 0;
2113 int lrclk = 0;
2114 int rate_val = 0;
2115 int id = dai->id - 1;
2116
2117 int i, cur_val, best_val, bclk_rate, best;
2118
2119 switch (dai->id) {
2120 case 1:
2121 aif1_reg = WM8994_AIF1_CONTROL_1;
2122 aif2_reg = WM8994_AIF1_CONTROL_2;
2123 bclk_reg = WM8994_AIF1_BCLK;
2124 rate_reg = WM8994_AIF1_RATE;
2125 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2126 wm8994->lrclk_shared[0]) {
2127 lrclk_reg = WM8994_AIF1DAC_LRCLK;
2128 } else {
2129 lrclk_reg = WM8994_AIF1ADC_LRCLK;
2130 dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2131 }
2132 break;
2133 case 2:
2134 aif1_reg = WM8994_AIF2_CONTROL_1;
2135 aif2_reg = WM8994_AIF2_CONTROL_2;
2136 bclk_reg = WM8994_AIF2_BCLK;
2137 rate_reg = WM8994_AIF2_RATE;
2138 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2139 wm8994->lrclk_shared[1]) {
2140 lrclk_reg = WM8994_AIF2DAC_LRCLK;
2141 } else {
2142 lrclk_reg = WM8994_AIF2ADC_LRCLK;
2143 dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2144 }
2145 break;
2146 case 3:
2147 switch (control->type) {
2148 case WM8958:
2149 aif1_reg = WM8958_AIF3_CONTROL_1;
2150 break;
2151 default:
2152 return 0;
2153 }
2154 default:
2155 return -EINVAL;
2156 }
2157
2158 bclk_rate = params_rate(params) * 2;
2159 switch (params_format(params)) {
2160 case SNDRV_PCM_FORMAT_S16_LE:
2161 bclk_rate *= 16;
2162 break;
2163 case SNDRV_PCM_FORMAT_S20_3LE:
2164 bclk_rate *= 20;
2165 aif1 |= 0x20;
2166 break;
2167 case SNDRV_PCM_FORMAT_S24_LE:
2168 bclk_rate *= 24;
2169 aif1 |= 0x40;
2170 break;
2171 case SNDRV_PCM_FORMAT_S32_LE:
2172 bclk_rate *= 32;
2173 aif1 |= 0x60;
2174 break;
2175 default:
2176 return -EINVAL;
2177 }
2178
2179 /* Try to find an appropriate sample rate; look for an exact match. */
2180 for (i = 0; i < ARRAY_SIZE(srs); i++)
2181 if (srs[i].rate == params_rate(params))
2182 break;
2183 if (i == ARRAY_SIZE(srs))
2184 return -EINVAL;
2185 rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2186
2187 dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2188 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2189 dai->id, wm8994->aifclk[id], bclk_rate);
2190
2191 if (params_channels(params) == 1 &&
2192 (snd_soc_read(codec, aif1_reg) & 0x18) == 0x18)
2193 aif2 |= WM8994_AIF1_MONO;
2194
2195 if (wm8994->aifclk[id] == 0) {
2196 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2197 return -EINVAL;
2198 }
2199
2200 /* AIFCLK/fs ratio; look for a close match in either direction */
2201 best = 0;
2202 best_val = abs((fs_ratios[0] * params_rate(params))
2203 - wm8994->aifclk[id]);
2204 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2205 cur_val = abs((fs_ratios[i] * params_rate(params))
2206 - wm8994->aifclk[id]);
2207 if (cur_val >= best_val)
2208 continue;
2209 best = i;
2210 best_val = cur_val;
2211 }
2212 dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2213 dai->id, fs_ratios[best]);
2214 rate_val |= best;
2215
2216 /* We may not get quite the right frequency if using
2217 * approximate clocks so look for the closest match that is
2218 * higher than the target (we need to ensure that there enough
2219 * BCLKs to clock out the samples).
2220 */
2221 best = 0;
2222 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2223 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2224 if (cur_val < 0) /* BCLK table is sorted */
2225 break;
2226 best = i;
2227 }
2228 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2229 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2230 bclk_divs[best], bclk_rate);
2231 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2232
2233 lrclk = bclk_rate / params_rate(params);
2234 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2235 lrclk, bclk_rate / lrclk);
2236
2237 snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2238 snd_soc_update_bits(codec, aif2_reg, WM8994_AIF1_MONO, aif2);
2239 snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2240 snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2241 lrclk);
2242 snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2243 WM8994_AIF1CLK_RATE_MASK, rate_val);
2244
2245 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2246 switch (dai->id) {
2247 case 1:
2248 wm8994->dac_rates[0] = params_rate(params);
2249 wm8994_set_retune_mobile(codec, 0);
2250 wm8994_set_retune_mobile(codec, 1);
2251 break;
2252 case 2:
2253 wm8994->dac_rates[1] = params_rate(params);
2254 wm8994_set_retune_mobile(codec, 2);
2255 break;
2256 }
2257 }
2258
2259 return 0;
2260}
2261
2262static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2263 struct snd_pcm_hw_params *params,
2264 struct snd_soc_dai *dai)
2265{
2266 struct snd_soc_codec *codec = dai->codec;
2267 struct wm8994 *control = codec->control_data;
2268 int aif1_reg;
2269 int aif1 = 0;
2270
2271 switch (dai->id) {
2272 case 3:
2273 switch (control->type) {
2274 case WM8958:
2275 aif1_reg = WM8958_AIF3_CONTROL_1;
2276 break;
2277 default:
2278 return 0;
2279 }
2280 default:
2281 return 0;
2282 }
2283
2284 switch (params_format(params)) {
2285 case SNDRV_PCM_FORMAT_S16_LE:
2286 break;
2287 case SNDRV_PCM_FORMAT_S20_3LE:
2288 aif1 |= 0x20;
2289 break;
2290 case SNDRV_PCM_FORMAT_S24_LE:
2291 aif1 |= 0x40;
2292 break;
2293 case SNDRV_PCM_FORMAT_S32_LE:
2294 aif1 |= 0x60;
2295 break;
2296 default:
2297 return -EINVAL;
2298 }
2299
2300 return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2301}
2302
2303static void wm8994_aif_shutdown(struct snd_pcm_substream *substream,
2304 struct snd_soc_dai *dai)
2305{
2306 struct snd_soc_codec *codec = dai->codec;
2307 int rate_reg = 0;
2308
2309 switch (dai->id) {
2310 case 1:
2311 rate_reg = WM8994_AIF1_RATE;
2312 break;
2313 case 2:
2314 rate_reg = WM8994_AIF1_RATE;
2315 break;
2316 default:
2317 break;
2318 }
2319
2320 /* If the DAI is idle then configure the divider tree for the
2321 * lowest output rate to save a little power if the clock is
2322 * still active (eg, because it is system clock).
2323 */
2324 if (rate_reg && !dai->playback_active && !dai->capture_active)
2325 snd_soc_update_bits(codec, rate_reg,
2326 WM8994_AIF1_SR_MASK |
2327 WM8994_AIF1CLK_RATE_MASK, 0x9);
2328}
2329
2330static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2331{
2332 struct snd_soc_codec *codec = codec_dai->codec;
2333 int mute_reg;
2334 int reg;
2335
2336 switch (codec_dai->id) {
2337 case 1:
2338 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2339 break;
2340 case 2:
2341 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2342 break;
2343 default:
2344 return -EINVAL;
2345 }
2346
2347 if (mute)
2348 reg = WM8994_AIF1DAC1_MUTE;
2349 else
2350 reg = 0;
2351
2352 snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2353
2354 return 0;
2355}
2356
2357static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2358{
2359 struct snd_soc_codec *codec = codec_dai->codec;
2360 int reg, val, mask;
2361
2362 switch (codec_dai->id) {
2363 case 1:
2364 reg = WM8994_AIF1_MASTER_SLAVE;
2365 mask = WM8994_AIF1_TRI;
2366 break;
2367 case 2:
2368 reg = WM8994_AIF2_MASTER_SLAVE;
2369 mask = WM8994_AIF2_TRI;
2370 break;
2371 case 3:
2372 reg = WM8994_POWER_MANAGEMENT_6;
2373 mask = WM8994_AIF3_TRI;
2374 break;
2375 default:
2376 return -EINVAL;
2377 }
2378
2379 if (tristate)
2380 val = mask;
2381 else
2382 val = 0;
2383
2384 return snd_soc_update_bits(codec, reg, mask, val);
2385}
2386
2387#define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2388
2389#define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2390 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2391
2392static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2393 .set_sysclk = wm8994_set_dai_sysclk,
2394 .set_fmt = wm8994_set_dai_fmt,
2395 .hw_params = wm8994_hw_params,
2396 .shutdown = wm8994_aif_shutdown,
2397 .digital_mute = wm8994_aif_mute,
2398 .set_pll = wm8994_set_fll,
2399 .set_tristate = wm8994_set_tristate,
2400};
2401
2402static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2403 .set_sysclk = wm8994_set_dai_sysclk,
2404 .set_fmt = wm8994_set_dai_fmt,
2405 .hw_params = wm8994_hw_params,
2406 .shutdown = wm8994_aif_shutdown,
2407 .digital_mute = wm8994_aif_mute,
2408 .set_pll = wm8994_set_fll,
2409 .set_tristate = wm8994_set_tristate,
2410};
2411
2412static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2413 .hw_params = wm8994_aif3_hw_params,
2414 .set_tristate = wm8994_set_tristate,
2415};
2416
2417static struct snd_soc_dai_driver wm8994_dai[] = {
2418 {
2419 .name = "wm8994-aif1",
2420 .id = 1,
2421 .playback = {
2422 .stream_name = "AIF1 Playback",
2423 .channels_min = 1,
2424 .channels_max = 2,
2425 .rates = WM8994_RATES,
2426 .formats = WM8994_FORMATS,
2427 },
2428 .capture = {
2429 .stream_name = "AIF1 Capture",
2430 .channels_min = 1,
2431 .channels_max = 2,
2432 .rates = WM8994_RATES,
2433 .formats = WM8994_FORMATS,
2434 },
2435 .ops = &wm8994_aif1_dai_ops,
2436 },
2437 {
2438 .name = "wm8994-aif2",
2439 .id = 2,
2440 .playback = {
2441 .stream_name = "AIF2 Playback",
2442 .channels_min = 1,
2443 .channels_max = 2,
2444 .rates = WM8994_RATES,
2445 .formats = WM8994_FORMATS,
2446 },
2447 .capture = {
2448 .stream_name = "AIF2 Capture",
2449 .channels_min = 1,
2450 .channels_max = 2,
2451 .rates = WM8994_RATES,
2452 .formats = WM8994_FORMATS,
2453 },
2454 .ops = &wm8994_aif2_dai_ops,
2455 },
2456 {
2457 .name = "wm8994-aif3",
2458 .id = 3,
2459 .playback = {
2460 .stream_name = "AIF3 Playback",
2461 .channels_min = 1,
2462 .channels_max = 2,
2463 .rates = WM8994_RATES,
2464 .formats = WM8994_FORMATS,
2465 },
2466 .capture = {
2467 .stream_name = "AIF3 Capture",
2468 .channels_min = 1,
2469 .channels_max = 2,
2470 .rates = WM8994_RATES,
2471 .formats = WM8994_FORMATS,
2472 },
2473 .ops = &wm8994_aif3_dai_ops,
2474 }
2475};
2476
2477#ifdef CONFIG_PM
2478static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2479{
2480 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2481 struct wm8994 *control = codec->control_data;
2482 int i, ret;
2483
2484 switch (control->type) {
2485 case WM8994:
2486 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, 0);
2487 break;
2488 case WM8958:
2489 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2490 WM8958_MICD_ENA, 0);
2491 break;
2492 }
2493
2494 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2495 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2496 sizeof(struct wm8994_fll_config));
2497 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2498 if (ret < 0)
2499 dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2500 i + 1, ret);
2501 }
2502
2503 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2504
2505 return 0;
2506}
2507
2508static int wm8994_resume(struct snd_soc_codec *codec)
2509{
2510 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2511 struct wm8994 *control = codec->control_data;
2512 int i, ret;
2513 unsigned int val, mask;
2514
2515 if (wm8994->revision < 4) {
2516 /* force a HW read */
2517 val = wm8994_reg_read(codec->control_data,
2518 WM8994_POWER_MANAGEMENT_5);
2519
2520 /* modify the cache only */
2521 codec->cache_only = 1;
2522 mask = WM8994_DAC1R_ENA | WM8994_DAC1L_ENA |
2523 WM8994_DAC2R_ENA | WM8994_DAC2L_ENA;
2524 val &= mask;
2525 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_5,
2526 mask, val);
2527 codec->cache_only = 0;
2528 }
2529
2530 /* Restore the registers */
2531 ret = snd_soc_cache_sync(codec);
2532 if (ret != 0)
2533 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2534
2535 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2536
2537 for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2538 if (!wm8994->fll_suspend[i].out)
2539 continue;
2540
2541 ret = _wm8994_set_fll(codec, i + 1,
2542 wm8994->fll_suspend[i].src,
2543 wm8994->fll_suspend[i].in,
2544 wm8994->fll_suspend[i].out);
2545 if (ret < 0)
2546 dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2547 i + 1, ret);
2548 }
2549
2550 switch (control->type) {
2551 case WM8994:
2552 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2553 snd_soc_update_bits(codec, WM8994_MICBIAS,
2554 WM8994_MICD_ENA, WM8994_MICD_ENA);
2555 break;
2556 case WM8958:
2557 if (wm8994->jack_cb)
2558 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2559 WM8958_MICD_ENA, WM8958_MICD_ENA);
2560 break;
2561 }
2562
2563 return 0;
2564}
2565#else
2566#define wm8994_suspend NULL
2567#define wm8994_resume NULL
2568#endif
2569
2570static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2571{
2572 struct snd_soc_codec *codec = wm8994->codec;
2573 struct wm8994_pdata *pdata = wm8994->pdata;
2574 struct snd_kcontrol_new controls[] = {
2575 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2576 wm8994->retune_mobile_enum,
2577 wm8994_get_retune_mobile_enum,
2578 wm8994_put_retune_mobile_enum),
2579 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2580 wm8994->retune_mobile_enum,
2581 wm8994_get_retune_mobile_enum,
2582 wm8994_put_retune_mobile_enum),
2583 SOC_ENUM_EXT("AIF2 EQ Mode",
2584 wm8994->retune_mobile_enum,
2585 wm8994_get_retune_mobile_enum,
2586 wm8994_put_retune_mobile_enum),
2587 };
2588 int ret, i, j;
2589 const char **t;
2590
2591 /* We need an array of texts for the enum API but the number
2592 * of texts is likely to be less than the number of
2593 * configurations due to the sample rate dependency of the
2594 * configurations. */
2595 wm8994->num_retune_mobile_texts = 0;
2596 wm8994->retune_mobile_texts = NULL;
2597 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2598 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2599 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2600 wm8994->retune_mobile_texts[j]) == 0)
2601 break;
2602 }
2603
2604 if (j != wm8994->num_retune_mobile_texts)
2605 continue;
2606
2607 /* Expand the array... */
2608 t = krealloc(wm8994->retune_mobile_texts,
2609 sizeof(char *) *
2610 (wm8994->num_retune_mobile_texts + 1),
2611 GFP_KERNEL);
2612 if (t == NULL)
2613 continue;
2614
2615 /* ...store the new entry... */
2616 t[wm8994->num_retune_mobile_texts] =
2617 pdata->retune_mobile_cfgs[i].name;
2618
2619 /* ...and remember the new version. */
2620 wm8994->num_retune_mobile_texts++;
2621 wm8994->retune_mobile_texts = t;
2622 }
2623
2624 dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2625 wm8994->num_retune_mobile_texts);
2626
2627 wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2628 wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2629
2630 ret = snd_soc_add_controls(wm8994->codec, controls,
2631 ARRAY_SIZE(controls));
2632 if (ret != 0)
2633 dev_err(wm8994->codec->dev,
2634 "Failed to add ReTune Mobile controls: %d\n", ret);
2635}
2636
2637static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2638{
2639 struct snd_soc_codec *codec = wm8994->codec;
2640 struct wm8994_pdata *pdata = wm8994->pdata;
2641 int ret, i;
2642
2643 if (!pdata)
2644 return;
2645
2646 wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2647 pdata->lineout2_diff,
2648 pdata->lineout1fb,
2649 pdata->lineout2fb,
2650 pdata->jd_scthr,
2651 pdata->jd_thr,
2652 pdata->micbias1_lvl,
2653 pdata->micbias2_lvl);
2654
2655 dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2656
2657 if (pdata->num_drc_cfgs) {
2658 struct snd_kcontrol_new controls[] = {
2659 SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2660 wm8994_get_drc_enum, wm8994_put_drc_enum),
2661 SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2662 wm8994_get_drc_enum, wm8994_put_drc_enum),
2663 SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2664 wm8994_get_drc_enum, wm8994_put_drc_enum),
2665 };
2666
2667 /* We need an array of texts for the enum API */
2668 wm8994->drc_texts = kmalloc(sizeof(char *)
2669 * pdata->num_drc_cfgs, GFP_KERNEL);
2670 if (!wm8994->drc_texts) {
2671 dev_err(wm8994->codec->dev,
2672 "Failed to allocate %d DRC config texts\n",
2673 pdata->num_drc_cfgs);
2674 return;
2675 }
2676
2677 for (i = 0; i < pdata->num_drc_cfgs; i++)
2678 wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2679
2680 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2681 wm8994->drc_enum.texts = wm8994->drc_texts;
2682
2683 ret = snd_soc_add_controls(wm8994->codec, controls,
2684 ARRAY_SIZE(controls));
2685 if (ret != 0)
2686 dev_err(wm8994->codec->dev,
2687 "Failed to add DRC mode controls: %d\n", ret);
2688
2689 for (i = 0; i < WM8994_NUM_DRC; i++)
2690 wm8994_set_drc(codec, i);
2691 }
2692
2693 dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2694 pdata->num_retune_mobile_cfgs);
2695
2696 if (pdata->num_retune_mobile_cfgs)
2697 wm8994_handle_retune_mobile_pdata(wm8994);
2698 else
2699 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2700 ARRAY_SIZE(wm8994_eq_controls));
2701
2702 for (i = 0; i < ARRAY_SIZE(pdata->micbias); i++) {
2703 if (pdata->micbias[i]) {
2704 snd_soc_write(codec, WM8958_MICBIAS1 + i,
2705 pdata->micbias[i] & 0xffff);
2706 }
2707 }
2708}
2709
2710/**
2711 * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2712 *
2713 * @codec: WM8994 codec
2714 * @jack: jack to report detection events on
2715 * @micbias: microphone bias to detect on
2716 * @det: value to report for presence detection
2717 * @shrt: value to report for short detection
2718 *
2719 * Enable microphone detection via IRQ on the WM8994. If GPIOs are
2720 * being used to bring out signals to the processor then only platform
2721 * data configuration is needed for WM8994 and processor GPIOs should
2722 * be configured using snd_soc_jack_add_gpios() instead.
2723 *
2724 * Configuration of detection levels is available via the micbias1_lvl
2725 * and micbias2_lvl platform data members.
2726 */
2727int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2728 int micbias, int det, int shrt)
2729{
2730 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2731 struct wm8994_micdet *micdet;
2732 struct wm8994 *control = codec->control_data;
2733 int reg;
2734
2735 if (control->type != WM8994)
2736 return -EINVAL;
2737
2738 switch (micbias) {
2739 case 1:
2740 micdet = &wm8994->micdet[0];
2741 break;
2742 case 2:
2743 micdet = &wm8994->micdet[1];
2744 break;
2745 default:
2746 return -EINVAL;
2747 }
2748
2749 dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2750 micbias, det, shrt);
2751
2752 /* Store the configuration */
2753 micdet->jack = jack;
2754 micdet->det = det;
2755 micdet->shrt = shrt;
2756
2757 /* If either of the jacks is set up then enable detection */
2758 if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2759 reg = WM8994_MICD_ENA;
2760 else
2761 reg = 0;
2762
2763 snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2764
2765 return 0;
2766}
2767EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2768
2769static irqreturn_t wm8994_mic_irq(int irq, void *data)
2770{
2771 struct wm8994_priv *priv = data;
2772 struct snd_soc_codec *codec = priv->codec;
2773 int reg;
2774 int report;
2775
2776#ifndef CONFIG_SND_SOC_WM8994_MODULE
2777 trace_snd_soc_jack_irq(dev_name(codec->dev));
2778#endif
2779
2780 reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2781 if (reg < 0) {
2782 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2783 reg);
2784 return IRQ_HANDLED;
2785 }
2786
2787 dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2788
2789 report = 0;
2790 if (reg & WM8994_MIC1_DET_STS)
2791 report |= priv->micdet[0].det;
2792 if (reg & WM8994_MIC1_SHRT_STS)
2793 report |= priv->micdet[0].shrt;
2794 snd_soc_jack_report(priv->micdet[0].jack, report,
2795 priv->micdet[0].det | priv->micdet[0].shrt);
2796
2797 report = 0;
2798 if (reg & WM8994_MIC2_DET_STS)
2799 report |= priv->micdet[1].det;
2800 if (reg & WM8994_MIC2_SHRT_STS)
2801 report |= priv->micdet[1].shrt;
2802 snd_soc_jack_report(priv->micdet[1].jack, report,
2803 priv->micdet[1].det | priv->micdet[1].shrt);
2804
2805 return IRQ_HANDLED;
2806}
2807
2808/* Default microphone detection handler for WM8958 - the user can
2809 * override this if they wish.
2810 */
2811static void wm8958_default_micdet(u16 status, void *data)
2812{
2813 struct snd_soc_codec *codec = data;
2814 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2815 int report = 0;
2816
2817 /* If nothing present then clear our statuses */
2818 if (!(status & WM8958_MICD_STS))
2819 goto done;
2820
2821 report = SND_JACK_MICROPHONE;
2822
2823 /* Everything else is buttons; just assign slots */
2824 if (status & 0x1c)
2825 report |= SND_JACK_BTN_0;
2826
2827done:
2828 snd_soc_jack_report(wm8994->micdet[0].jack, report,
2829 SND_JACK_BTN_0 | SND_JACK_MICROPHONE);
2830}
2831
2832/**
2833 * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2834 *
2835 * @codec: WM8958 codec
2836 * @jack: jack to report detection events on
2837 *
2838 * Enable microphone detection functionality for the WM8958. By
2839 * default simple detection which supports the detection of up to 6
2840 * buttons plus video and microphone functionality is supported.
2841 *
2842 * The WM8958 has an advanced jack detection facility which is able to
2843 * support complex accessory detection, especially when used in
2844 * conjunction with external circuitry. In order to provide maximum
2845 * flexiblity a callback is provided which allows a completely custom
2846 * detection algorithm.
2847 */
2848int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2849 wm8958_micdet_cb cb, void *cb_data)
2850{
2851 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2852 struct wm8994 *control = codec->control_data;
2853
2854 if (control->type != WM8958)
2855 return -EINVAL;
2856
2857 if (jack) {
2858 if (!cb) {
2859 dev_dbg(codec->dev, "Using default micdet callback\n");
2860 cb = wm8958_default_micdet;
2861 cb_data = codec;
2862 }
2863
2864 wm8994->micdet[0].jack = jack;
2865 wm8994->jack_cb = cb;
2866 wm8994->jack_cb_data = cb_data;
2867
2868 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2869 WM8958_MICD_ENA, WM8958_MICD_ENA);
2870 } else {
2871 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2872 WM8958_MICD_ENA, 0);
2873 }
2874
2875 return 0;
2876}
2877EXPORT_SYMBOL_GPL(wm8958_mic_detect);
2878
2879static irqreturn_t wm8958_mic_irq(int irq, void *data)
2880{
2881 struct wm8994_priv *wm8994 = data;
2882 struct snd_soc_codec *codec = wm8994->codec;
2883 int reg;
2884
2885 reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2886 if (reg < 0) {
2887 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2888 reg);
2889 return IRQ_NONE;
2890 }
2891
2892 if (!(reg & WM8958_MICD_VALID)) {
2893 dev_dbg(codec->dev, "Mic detect data not valid\n");
2894 goto out;
2895 }
2896
2897#ifndef CONFIG_SND_SOC_WM8994_MODULE
2898 trace_snd_soc_jack_irq(dev_name(codec->dev));
2899#endif
2900
2901 if (wm8994->jack_cb)
2902 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2903 else
2904 dev_warn(codec->dev, "Accessory detection with no callback\n");
2905
2906out:
2907 return IRQ_HANDLED;
2908}
2909
2910static irqreturn_t wm8994_fifo_error(int irq, void *data)
2911{
2912 struct snd_soc_codec *codec = data;
2913
2914 dev_err(codec->dev, "FIFO error\n");
2915
2916 return IRQ_HANDLED;
2917}
2918
2919static int wm8994_codec_probe(struct snd_soc_codec *codec)
2920{
2921 struct wm8994 *control;
2922 struct wm8994_priv *wm8994;
2923 struct snd_soc_dapm_context *dapm = &codec->dapm;
2924 int ret, i;
2925
2926 codec->control_data = dev_get_drvdata(codec->dev->parent);
2927 control = codec->control_data;
2928
2929 wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2930 if (wm8994 == NULL)
2931 return -ENOMEM;
2932 snd_soc_codec_set_drvdata(codec, wm8994);
2933
2934 wm8994->pdata = dev_get_platdata(codec->dev->parent);
2935 wm8994->codec = codec;
2936
2937 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
2938 init_completion(&wm8994->fll_locked[i]);
2939
2940 if (wm8994->pdata && wm8994->pdata->micdet_irq)
2941 wm8994->micdet_irq = wm8994->pdata->micdet_irq;
2942 else if (wm8994->pdata && wm8994->pdata->irq_base)
2943 wm8994->micdet_irq = wm8994->pdata->irq_base +
2944 WM8994_IRQ_MIC1_DET;
2945
2946 pm_runtime_enable(codec->dev);
2947 pm_runtime_resume(codec->dev);
2948
2949 /* Read our current status back from the chip - we don't want to
2950 * reset as this may interfere with the GPIO or LDO operation. */
2951 for (i = 0; i < WM8994_CACHE_SIZE; i++) {
2952 if (!wm8994_readable(codec, i) || wm8994_volatile(codec, i))
2953 continue;
2954
2955 ret = wm8994_reg_read(codec->control_data, i);
2956 if (ret <= 0)
2957 continue;
2958
2959 ret = snd_soc_cache_write(codec, i, ret);
2960 if (ret != 0) {
2961 dev_err(codec->dev,
2962 "Failed to initialise cache for 0x%x: %d\n",
2963 i, ret);
2964 goto err;
2965 }
2966 }
2967
2968 /* Set revision-specific configuration */
2969 wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
2970 switch (control->type) {
2971 case WM8994:
2972 switch (wm8994->revision) {
2973 case 2:
2974 case 3:
2975 wm8994->hubs.dcs_codes = -5;
2976 wm8994->hubs.hp_startup_mode = 1;
2977 wm8994->hubs.dcs_readback_mode = 1;
2978 wm8994->hubs.series_startup = 1;
2979 break;
2980 default:
2981 wm8994->hubs.dcs_readback_mode = 1;
2982 break;
2983 }
2984 break;
2985
2986 case WM8958:
2987 wm8994->hubs.dcs_readback_mode = 1;
2988 break;
2989
2990 default:
2991 break;
2992 }
2993
2994 wm8994_request_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR,
2995 wm8994_fifo_error, "FIFO error", codec);
2996
2997 ret = wm8994_request_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
2998 wm_hubs_dcs_done, "DC servo done",
2999 &wm8994->hubs);
3000 if (ret == 0)
3001 wm8994->hubs.dcs_done_irq = true;
3002
3003 switch (control->type) {
3004 case WM8994:
3005 if (wm8994->micdet_irq) {
3006 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3007 wm8994_mic_irq,
3008 IRQF_TRIGGER_RISING,
3009 "Mic1 detect",
3010 wm8994);
3011 if (ret != 0)
3012 dev_warn(codec->dev,
3013 "Failed to request Mic1 detect IRQ: %d\n",
3014 ret);
3015 }
3016
3017 ret = wm8994_request_irq(codec->control_data,
3018 WM8994_IRQ_MIC1_SHRT,
3019 wm8994_mic_irq, "Mic 1 short",
3020 wm8994);
3021 if (ret != 0)
3022 dev_warn(codec->dev,
3023 "Failed to request Mic1 short IRQ: %d\n",
3024 ret);
3025
3026 ret = wm8994_request_irq(codec->control_data,
3027 WM8994_IRQ_MIC2_DET,
3028 wm8994_mic_irq, "Mic 2 detect",
3029 wm8994);
3030 if (ret != 0)
3031 dev_warn(codec->dev,
3032 "Failed to request Mic2 detect IRQ: %d\n",
3033 ret);
3034
3035 ret = wm8994_request_irq(codec->control_data,
3036 WM8994_IRQ_MIC2_SHRT,
3037 wm8994_mic_irq, "Mic 2 short",
3038 wm8994);
3039 if (ret != 0)
3040 dev_warn(codec->dev,
3041 "Failed to request Mic2 short IRQ: %d\n",
3042 ret);
3043 break;
3044
3045 case WM8958:
3046 if (wm8994->micdet_irq) {
3047 ret = request_threaded_irq(wm8994->micdet_irq, NULL,
3048 wm8958_mic_irq,
3049 IRQF_TRIGGER_RISING,
3050 "Mic detect",
3051 wm8994);
3052 if (ret != 0)
3053 dev_warn(codec->dev,
3054 "Failed to request Mic detect IRQ: %d\n",
3055 ret);
3056 }
3057 }
3058
3059 wm8994->fll_locked_irq = true;
3060 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++) {
3061 ret = wm8994_request_irq(codec->control_data,
3062 WM8994_IRQ_FLL1_LOCK + i,
3063 wm8994_fll_locked_irq, "FLL lock",
3064 &wm8994->fll_locked[i]);
3065 if (ret != 0)
3066 wm8994->fll_locked_irq = false;
3067 }
3068
3069 /* Remember if AIFnLRCLK is configured as a GPIO. This should be
3070 * configured on init - if a system wants to do this dynamically
3071 * at runtime we can deal with that then.
3072 */
3073 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
3074 if (ret < 0) {
3075 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
3076 goto err_irq;
3077 }
3078 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3079 wm8994->lrclk_shared[0] = 1;
3080 wm8994_dai[0].symmetric_rates = 1;
3081 } else {
3082 wm8994->lrclk_shared[0] = 0;
3083 }
3084
3085 ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3086 if (ret < 0) {
3087 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3088 goto err_irq;
3089 }
3090 if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3091 wm8994->lrclk_shared[1] = 1;
3092 wm8994_dai[1].symmetric_rates = 1;
3093 } else {
3094 wm8994->lrclk_shared[1] = 0;
3095 }
3096
3097 wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3098
3099 /* Latch volume updates (right only; we always do left then right). */
3100 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_LEFT_VOLUME,
3101 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3102 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3103 WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3104 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_LEFT_VOLUME,
3105 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3106 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3107 WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3108 snd_soc_update_bits(codec, WM8994_AIF2_DAC_LEFT_VOLUME,
3109 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3110 snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3111 WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3112 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_LEFT_VOLUME,
3113 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3114 snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3115 WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3116 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_LEFT_VOLUME,
3117 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3118 snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3119 WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3120 snd_soc_update_bits(codec, WM8994_AIF2_ADC_LEFT_VOLUME,
3121 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3122 snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3123 WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3124 snd_soc_update_bits(codec, WM8994_DAC1_LEFT_VOLUME,
3125 WM8994_DAC1_VU, WM8994_DAC1_VU);
3126 snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3127 WM8994_DAC1_VU, WM8994_DAC1_VU);
3128 snd_soc_update_bits(codec, WM8994_DAC2_LEFT_VOLUME,
3129 WM8994_DAC2_VU, WM8994_DAC2_VU);
3130 snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3131 WM8994_DAC2_VU, WM8994_DAC2_VU);
3132
3133 /* Set the low bit of the 3D stereo depth so TLV matches */
3134 snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3135 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3136 1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3137 snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3138 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3139 1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3140 snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3141 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3142 1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3143
3144 /* Unconditionally enable AIF1 ADC TDM mode on chips which can
3145 * use this; it only affects behaviour on idle TDM clock
3146 * cycles. */
3147 switch (control->type) {
3148 case WM8994:
3149 case WM8958:
3150 snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3151 WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3152 break;
3153 default:
3154 break;
3155 }
3156
3157 wm8994_update_class_w(codec);
3158
3159 wm8994_handle_pdata(wm8994);
3160
3161 wm_hubs_add_analogue_controls(codec);
3162 snd_soc_add_controls(codec, wm8994_snd_controls,
3163 ARRAY_SIZE(wm8994_snd_controls));
3164 snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3165 ARRAY_SIZE(wm8994_dapm_widgets));
3166
3167 switch (control->type) {
3168 case WM8994:
3169 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3170 ARRAY_SIZE(wm8994_specific_dapm_widgets));
3171 if (wm8994->revision < 4) {
3172 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3173 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3174 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3175 ARRAY_SIZE(wm8994_adc_revd_widgets));
3176 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3177 ARRAY_SIZE(wm8994_dac_revd_widgets));
3178 } else {
3179 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3180 ARRAY_SIZE(wm8994_lateclk_widgets));
3181 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3182 ARRAY_SIZE(wm8994_adc_widgets));
3183 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3184 ARRAY_SIZE(wm8994_dac_widgets));
3185 }
3186 break;
3187 case WM8958:
3188 snd_soc_add_controls(codec, wm8958_snd_controls,
3189 ARRAY_SIZE(wm8958_snd_controls));
3190 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3191 ARRAY_SIZE(wm8958_dapm_widgets));
3192 if (wm8994->revision < 1) {
3193 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_revd_widgets,
3194 ARRAY_SIZE(wm8994_lateclk_revd_widgets));
3195 snd_soc_dapm_new_controls(dapm, wm8994_adc_revd_widgets,
3196 ARRAY_SIZE(wm8994_adc_revd_widgets));
3197 snd_soc_dapm_new_controls(dapm, wm8994_dac_revd_widgets,
3198 ARRAY_SIZE(wm8994_dac_revd_widgets));
3199 } else {
3200 snd_soc_dapm_new_controls(dapm, wm8994_lateclk_widgets,
3201 ARRAY_SIZE(wm8994_lateclk_widgets));
3202 snd_soc_dapm_new_controls(dapm, wm8994_adc_widgets,
3203 ARRAY_SIZE(wm8994_adc_widgets));
3204 snd_soc_dapm_new_controls(dapm, wm8994_dac_widgets,
3205 ARRAY_SIZE(wm8994_dac_widgets));
3206 }
3207 break;
3208 }
3209
3210
3211 wm_hubs_add_analogue_routes(codec, 0, 0);
3212 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3213
3214 switch (control->type) {
3215 case WM8994:
3216 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3217 ARRAY_SIZE(wm8994_intercon));
3218
3219 if (wm8994->revision < 4) {
3220 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3221 ARRAY_SIZE(wm8994_revd_intercon));
3222 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3223 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3224 } else {
3225 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3226 ARRAY_SIZE(wm8994_lateclk_intercon));
3227 }
3228 break;
3229 case WM8958:
3230 if (wm8994->revision < 1) {
3231 snd_soc_dapm_add_routes(dapm, wm8994_revd_intercon,
3232 ARRAY_SIZE(wm8994_revd_intercon));
3233 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_revd_intercon,
3234 ARRAY_SIZE(wm8994_lateclk_revd_intercon));
3235 } else {
3236 snd_soc_dapm_add_routes(dapm, wm8994_lateclk_intercon,
3237 ARRAY_SIZE(wm8994_lateclk_intercon));
3238 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3239 ARRAY_SIZE(wm8958_intercon));
3240 }
3241
3242 wm8958_dsp2_init(codec);
3243 break;
3244 }
3245
3246 return 0;
3247
3248err_irq:
3249 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3250 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3251 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3252 if (wm8994->micdet_irq)
3253 free_irq(wm8994->micdet_irq, wm8994);
3254 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3255 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3256 &wm8994->fll_locked[i]);
3257 wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3258 &wm8994->hubs);
3259 wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3260err:
3261 kfree(wm8994);
3262 return ret;
3263}
3264
3265static int wm8994_codec_remove(struct snd_soc_codec *codec)
3266{
3267 struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3268 struct wm8994 *control = codec->control_data;
3269 int i;
3270
3271 wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3272
3273 pm_runtime_disable(codec->dev);
3274
3275 for (i = 0; i < ARRAY_SIZE(wm8994->fll_locked); i++)
3276 wm8994_free_irq(codec->control_data, WM8994_IRQ_FLL1_LOCK + i,
3277 &wm8994->fll_locked[i]);
3278
3279 wm8994_free_irq(codec->control_data, WM8994_IRQ_DCS_DONE,
3280 &wm8994->hubs);
3281 wm8994_free_irq(codec->control_data, WM8994_IRQ_FIFOS_ERR, codec);
3282
3283 switch (control->type) {
3284 case WM8994:
3285 if (wm8994->micdet_irq)
3286 free_irq(wm8994->micdet_irq, wm8994);
3287 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3288 wm8994);
3289 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3290 wm8994);
3291 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3292 wm8994);
3293 break;
3294
3295 case WM8958:
3296 if (wm8994->micdet_irq)
3297 free_irq(wm8994->micdet_irq, wm8994);
3298 break;
3299 }
3300 if (wm8994->mbc)
3301 release_firmware(wm8994->mbc);
3302 if (wm8994->mbc_vss)
3303 release_firmware(wm8994->mbc_vss);
3304 if (wm8994->enh_eq)
3305 release_firmware(wm8994->enh_eq);
3306 kfree(wm8994->retune_mobile_texts);
3307 kfree(wm8994->drc_texts);
3308 kfree(wm8994);
3309
3310 return 0;
3311}
3312
3313static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3314 .probe = wm8994_codec_probe,
3315 .remove = wm8994_codec_remove,
3316 .suspend = wm8994_suspend,
3317 .resume = wm8994_resume,
3318 .read = wm8994_read,
3319 .write = wm8994_write,
3320 .readable_register = wm8994_readable,
3321 .volatile_register = wm8994_volatile,
3322 .set_bias_level = wm8994_set_bias_level,
3323
3324 .reg_cache_size = WM8994_CACHE_SIZE,
3325 .reg_cache_default = wm8994_reg_defaults,
3326 .reg_word_size = 2,
3327 .compress_type = SND_SOC_RBTREE_COMPRESSION,
3328};
3329
3330static int __devinit wm8994_probe(struct platform_device *pdev)
3331{
3332 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3333 wm8994_dai, ARRAY_SIZE(wm8994_dai));
3334}
3335
3336static int __devexit wm8994_remove(struct platform_device *pdev)
3337{
3338 snd_soc_unregister_codec(&pdev->dev);
3339 return 0;
3340}
3341
3342static struct platform_driver wm8994_codec_driver = {
3343 .driver = {
3344 .name = "wm8994-codec",
3345 .owner = THIS_MODULE,
3346 },
3347 .probe = wm8994_probe,
3348 .remove = __devexit_p(wm8994_remove),
3349};
3350
3351static __init int wm8994_init(void)
3352{
3353 return platform_driver_register(&wm8994_codec_driver);
3354}
3355module_init(wm8994_init);
3356
3357static __exit void wm8994_exit(void)
3358{
3359 platform_driver_unregister(&wm8994_codec_driver);
3360}
3361module_exit(wm8994_exit);
3362
3363
3364MODULE_DESCRIPTION("ASoC WM8994 driver");
3365MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3366MODULE_LICENSE("GPL");
3367MODULE_ALIAS("platform:wm8994-codec");