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1/*
2 * Intel MID GPIO driver
3 *
4 * Copyright (c) 2008-2014 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/* Supports:
17 * Moorestown platform Langwell chip.
18 * Medfield platform Penwell chip.
19 * Clovertrail platform Cloverview chip.
20 * Merrifield platform Tangier chip.
21 */
22
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/platform_device.h>
26#include <linux/kernel.h>
27#include <linux/delay.h>
28#include <linux/stddef.h>
29#include <linux/interrupt.h>
30#include <linux/init.h>
31#include <linux/irq.h>
32#include <linux/io.h>
33#include <linux/gpio.h>
34#include <linux/slab.h>
35#include <linux/pm_runtime.h>
36#include <linux/irqdomain.h>
37
38#define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
39#define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
40
41/*
42 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
43 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
44 * registers to control them, so we only define the order here instead of a
45 * structure, to get a bit offset for a pin (use GPDR as an example):
46 *
47 * nreg = ngpio / 32;
48 * reg = offset / 32;
49 * bit = offset % 32;
50 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
51 *
52 * so the bit of reg_addr is to control pin offset's GPDR feature
53*/
54
55enum GPIO_REG {
56 GPLR = 0, /* pin level read-only */
57 GPDR, /* pin direction */
58 GPSR, /* pin set */
59 GPCR, /* pin clear */
60 GRER, /* rising edge detect */
61 GFER, /* falling edge detect */
62 GEDR, /* edge detect result */
63 GAFR, /* alt function */
64};
65
66/* intel_mid gpio driver data */
67struct intel_mid_gpio_ddata {
68 u16 ngpio; /* number of gpio pins */
69 u32 gplr_offset; /* offset of first GPLR register from base */
70 u32 flis_base; /* base address of FLIS registers */
71 u32 flis_len; /* length of FLIS registers */
72 u32 (*get_flis_offset)(int gpio);
73 u32 chip_irq_type; /* chip interrupt type */
74};
75
76struct intel_mid_gpio {
77 struct gpio_chip chip;
78 void __iomem *reg_base;
79 spinlock_t lock;
80 struct pci_dev *pdev;
81 struct irq_domain *domain;
82};
83
84#define to_intel_gpio_priv(chip) container_of(chip, struct intel_mid_gpio, chip)
85
86static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
87 enum GPIO_REG reg_type)
88{
89 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
90 unsigned nreg = chip->ngpio / 32;
91 u8 reg = offset / 32;
92
93 return priv->reg_base + reg_type * nreg * 4 + reg * 4;
94}
95
96static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
97 enum GPIO_REG reg_type)
98{
99 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
100 unsigned nreg = chip->ngpio / 32;
101 u8 reg = offset / 16;
102
103 return priv->reg_base + reg_type * nreg * 4 + reg * 4;
104}
105
106static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
107{
108 void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
109 u32 value = readl(gafr);
110 int shift = (offset % 16) << 1, af = (value >> shift) & 3;
111
112 if (af) {
113 value &= ~(3 << shift);
114 writel(value, gafr);
115 }
116 return 0;
117}
118
119static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
120{
121 void __iomem *gplr = gpio_reg(chip, offset, GPLR);
122
123 return readl(gplr) & BIT(offset % 32);
124}
125
126static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
127{
128 void __iomem *gpsr, *gpcr;
129
130 if (value) {
131 gpsr = gpio_reg(chip, offset, GPSR);
132 writel(BIT(offset % 32), gpsr);
133 } else {
134 gpcr = gpio_reg(chip, offset, GPCR);
135 writel(BIT(offset % 32), gpcr);
136 }
137}
138
139static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
140{
141 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
142 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
143 u32 value;
144 unsigned long flags;
145
146 if (priv->pdev)
147 pm_runtime_get(&priv->pdev->dev);
148
149 spin_lock_irqsave(&priv->lock, flags);
150 value = readl(gpdr);
151 value &= ~BIT(offset % 32);
152 writel(value, gpdr);
153 spin_unlock_irqrestore(&priv->lock, flags);
154
155 if (priv->pdev)
156 pm_runtime_put(&priv->pdev->dev);
157
158 return 0;
159}
160
161static int intel_gpio_direction_output(struct gpio_chip *chip,
162 unsigned offset, int value)
163{
164 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
165 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
166 unsigned long flags;
167
168 intel_gpio_set(chip, offset, value);
169
170 if (priv->pdev)
171 pm_runtime_get(&priv->pdev->dev);
172
173 spin_lock_irqsave(&priv->lock, flags);
174 value = readl(gpdr);
175 value |= BIT(offset % 32);
176 writel(value, gpdr);
177 spin_unlock_irqrestore(&priv->lock, flags);
178
179 if (priv->pdev)
180 pm_runtime_put(&priv->pdev->dev);
181
182 return 0;
183}
184
185static int intel_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
186{
187 struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
188 return irq_create_mapping(priv->domain, offset);
189}
190
191static int intel_mid_irq_type(struct irq_data *d, unsigned type)
192{
193 struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
194 u32 gpio = irqd_to_hwirq(d);
195 unsigned long flags;
196 u32 value;
197 void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
198 void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
199
200 if (gpio >= priv->chip.ngpio)
201 return -EINVAL;
202
203 if (priv->pdev)
204 pm_runtime_get(&priv->pdev->dev);
205
206 spin_lock_irqsave(&priv->lock, flags);
207 if (type & IRQ_TYPE_EDGE_RISING)
208 value = readl(grer) | BIT(gpio % 32);
209 else
210 value = readl(grer) & (~BIT(gpio % 32));
211 writel(value, grer);
212
213 if (type & IRQ_TYPE_EDGE_FALLING)
214 value = readl(gfer) | BIT(gpio % 32);
215 else
216 value = readl(gfer) & (~BIT(gpio % 32));
217 writel(value, gfer);
218 spin_unlock_irqrestore(&priv->lock, flags);
219
220 if (priv->pdev)
221 pm_runtime_put(&priv->pdev->dev);
222
223 return 0;
224}
225
226static void intel_mid_irq_unmask(struct irq_data *d)
227{
228}
229
230static void intel_mid_irq_mask(struct irq_data *d)
231{
232}
233
234static int intel_mid_irq_reqres(struct irq_data *d)
235{
236 struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
237
238 if (gpio_lock_as_irq(&priv->chip, irqd_to_hwirq(d))) {
239 dev_err(priv->chip.dev,
240 "unable to lock HW IRQ %lu for IRQ\n",
241 irqd_to_hwirq(d));
242 return -EINVAL;
243 }
244 return 0;
245}
246
247static void intel_mid_irq_relres(struct irq_data *d)
248{
249 struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d);
250
251 gpio_unlock_as_irq(&priv->chip, irqd_to_hwirq(d));
252}
253
254static struct irq_chip intel_mid_irqchip = {
255 .name = "INTEL_MID-GPIO",
256 .irq_mask = intel_mid_irq_mask,
257 .irq_unmask = intel_mid_irq_unmask,
258 .irq_set_type = intel_mid_irq_type,
259 .irq_request_resources = intel_mid_irq_reqres,
260 .irq_release_resources = intel_mid_irq_relres,
261};
262
263static const struct intel_mid_gpio_ddata gpio_lincroft = {
264 .ngpio = 64,
265};
266
267static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
268 .ngpio = 96,
269 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
270};
271
272static const struct intel_mid_gpio_ddata gpio_penwell_core = {
273 .ngpio = 96,
274 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
275};
276
277static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
278 .ngpio = 96,
279 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
280};
281
282static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
283 .ngpio = 96,
284 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
285};
286
287static const struct intel_mid_gpio_ddata gpio_tangier = {
288 .ngpio = 192,
289 .gplr_offset = 4,
290 .flis_base = 0xff0c0000,
291 .flis_len = 0x8000,
292 .get_flis_offset = NULL,
293 .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
294};
295
296static const struct pci_device_id intel_gpio_ids[] = {
297 {
298 /* Lincroft */
299 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
300 .driver_data = (kernel_ulong_t)&gpio_lincroft,
301 },
302 {
303 /* Penwell AON */
304 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
305 .driver_data = (kernel_ulong_t)&gpio_penwell_aon,
306 },
307 {
308 /* Penwell Core */
309 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
310 .driver_data = (kernel_ulong_t)&gpio_penwell_core,
311 },
312 {
313 /* Cloverview Aon */
314 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
315 .driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
316 },
317 {
318 /* Cloverview Core */
319 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
320 .driver_data = (kernel_ulong_t)&gpio_cloverview_core,
321 },
322 {
323 /* Tangier */
324 PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199),
325 .driver_data = (kernel_ulong_t)&gpio_tangier,
326 },
327 { 0 }
328};
329MODULE_DEVICE_TABLE(pci, intel_gpio_ids);
330
331static void intel_mid_irq_handler(unsigned irq, struct irq_desc *desc)
332{
333 struct irq_data *data = irq_desc_get_irq_data(desc);
334 struct intel_mid_gpio *priv = irq_data_get_irq_handler_data(data);
335 struct irq_chip *chip = irq_data_get_irq_chip(data);
336 u32 base, gpio, mask;
337 unsigned long pending;
338 void __iomem *gedr;
339
340 /* check GPIO controller to check which pin triggered the interrupt */
341 for (base = 0; base < priv->chip.ngpio; base += 32) {
342 gedr = gpio_reg(&priv->chip, base, GEDR);
343 while ((pending = readl(gedr))) {
344 gpio = __ffs(pending);
345 mask = BIT(gpio);
346 /* Clear before handling so we can't lose an edge */
347 writel(mask, gedr);
348 generic_handle_irq(irq_find_mapping(priv->domain,
349 base + gpio));
350 }
351 }
352
353 chip->irq_eoi(data);
354}
355
356static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
357{
358 void __iomem *reg;
359 unsigned base;
360
361 for (base = 0; base < priv->chip.ngpio; base += 32) {
362 /* Clear the rising-edge detect register */
363 reg = gpio_reg(&priv->chip, base, GRER);
364 writel(0, reg);
365 /* Clear the falling-edge detect register */
366 reg = gpio_reg(&priv->chip, base, GFER);
367 writel(0, reg);
368 /* Clear the edge detect status register */
369 reg = gpio_reg(&priv->chip, base, GEDR);
370 writel(~0, reg);
371 }
372}
373
374static int intel_gpio_irq_map(struct irq_domain *d, unsigned int irq,
375 irq_hw_number_t hwirq)
376{
377 struct intel_mid_gpio *priv = d->host_data;
378
379 irq_set_chip_and_handler(irq, &intel_mid_irqchip, handle_simple_irq);
380 irq_set_chip_data(irq, priv);
381 irq_set_irq_type(irq, IRQ_TYPE_NONE);
382
383 return 0;
384}
385
386static const struct irq_domain_ops intel_gpio_irq_ops = {
387 .map = intel_gpio_irq_map,
388 .xlate = irq_domain_xlate_twocell,
389};
390
391static int intel_gpio_runtime_idle(struct device *dev)
392{
393 int err = pm_schedule_suspend(dev, 500);
394 return err ?: -EBUSY;
395}
396
397static const struct dev_pm_ops intel_gpio_pm_ops = {
398 SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
399};
400
401static int intel_gpio_probe(struct pci_dev *pdev,
402 const struct pci_device_id *id)
403{
404 void __iomem *base;
405 struct intel_mid_gpio *priv;
406 u32 gpio_base;
407 u32 irq_base;
408 int retval;
409 struct intel_mid_gpio_ddata *ddata =
410 (struct intel_mid_gpio_ddata *)id->driver_data;
411
412 retval = pcim_enable_device(pdev);
413 if (retval)
414 return retval;
415
416 retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
417 if (retval) {
418 dev_err(&pdev->dev, "I/O memory mapping error\n");
419 return retval;
420 }
421
422 base = pcim_iomap_table(pdev)[1];
423
424 irq_base = readl(base);
425 gpio_base = readl(sizeof(u32) + base);
426
427 /* release the IO mapping, since we already get the info from bar1 */
428 pcim_iounmap_regions(pdev, 1 << 1);
429
430 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
431 if (!priv) {
432 dev_err(&pdev->dev, "can't allocate chip data\n");
433 return -ENOMEM;
434 }
435
436 priv->reg_base = pcim_iomap_table(pdev)[0];
437 priv->chip.label = dev_name(&pdev->dev);
438 priv->chip.dev = &pdev->dev;
439 priv->chip.request = intel_gpio_request;
440 priv->chip.direction_input = intel_gpio_direction_input;
441 priv->chip.direction_output = intel_gpio_direction_output;
442 priv->chip.get = intel_gpio_get;
443 priv->chip.set = intel_gpio_set;
444 priv->chip.to_irq = intel_gpio_to_irq;
445 priv->chip.base = gpio_base;
446 priv->chip.ngpio = ddata->ngpio;
447 priv->chip.can_sleep = false;
448 priv->pdev = pdev;
449
450 spin_lock_init(&priv->lock);
451
452 priv->domain = irq_domain_add_simple(pdev->dev.of_node, ddata->ngpio,
453 irq_base, &intel_gpio_irq_ops, priv);
454 if (!priv->domain)
455 return -ENOMEM;
456
457 pci_set_drvdata(pdev, priv);
458 retval = gpiochip_add(&priv->chip);
459 if (retval) {
460 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
461 return retval;
462 }
463
464 intel_mid_irq_init_hw(priv);
465
466 irq_set_handler_data(pdev->irq, priv);
467 irq_set_chained_handler(pdev->irq, intel_mid_irq_handler);
468
469 pm_runtime_put_noidle(&pdev->dev);
470 pm_runtime_allow(&pdev->dev);
471
472 return 0;
473}
474
475static struct pci_driver intel_gpio_driver = {
476 .name = "intel_mid_gpio",
477 .id_table = intel_gpio_ids,
478 .probe = intel_gpio_probe,
479 .driver = {
480 .pm = &intel_gpio_pm_ops,
481 },
482};
483
484static int __init intel_gpio_init(void)
485{
486 return pci_register_driver(&intel_gpio_driver);
487}
488
489device_initcall(intel_gpio_init);