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1/*
2 * Driver for the TXx9 SoC DMA Controller
3 *
4 * Copyright (C) 2009 Atsushi Nemoto
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/dma-mapping.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/slab.h>
17#include <linux/scatterlist.h>
18
19#include "dmaengine.h"
20#include "txx9dmac.h"
21
22static struct txx9dmac_chan *to_txx9dmac_chan(struct dma_chan *chan)
23{
24 return container_of(chan, struct txx9dmac_chan, chan);
25}
26
27static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc)
28{
29 return dc->ch_regs;
30}
31
32static struct txx9dmac_cregs32 __iomem *__dma_regs32(
33 const struct txx9dmac_chan *dc)
34{
35 return dc->ch_regs;
36}
37
38#define channel64_readq(dc, name) \
39 __raw_readq(&(__dma_regs(dc)->name))
40#define channel64_writeq(dc, name, val) \
41 __raw_writeq((val), &(__dma_regs(dc)->name))
42#define channel64_readl(dc, name) \
43 __raw_readl(&(__dma_regs(dc)->name))
44#define channel64_writel(dc, name, val) \
45 __raw_writel((val), &(__dma_regs(dc)->name))
46
47#define channel32_readl(dc, name) \
48 __raw_readl(&(__dma_regs32(dc)->name))
49#define channel32_writel(dc, name, val) \
50 __raw_writel((val), &(__dma_regs32(dc)->name))
51
52#define channel_readq(dc, name) channel64_readq(dc, name)
53#define channel_writeq(dc, name, val) channel64_writeq(dc, name, val)
54#define channel_readl(dc, name) \
55 (is_dmac64(dc) ? \
56 channel64_readl(dc, name) : channel32_readl(dc, name))
57#define channel_writel(dc, name, val) \
58 (is_dmac64(dc) ? \
59 channel64_writel(dc, name, val) : channel32_writel(dc, name, val))
60
61static dma_addr_t channel64_read_CHAR(const struct txx9dmac_chan *dc)
62{
63 if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
64 return channel64_readq(dc, CHAR);
65 else
66 return channel64_readl(dc, CHAR);
67}
68
69static void channel64_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
70{
71 if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
72 channel64_writeq(dc, CHAR, val);
73 else
74 channel64_writel(dc, CHAR, val);
75}
76
77static void channel64_clear_CHAR(const struct txx9dmac_chan *dc)
78{
79#if defined(CONFIG_32BIT) && !defined(CONFIG_64BIT_PHYS_ADDR)
80 channel64_writel(dc, CHAR, 0);
81 channel64_writel(dc, __pad_CHAR, 0);
82#else
83 channel64_writeq(dc, CHAR, 0);
84#endif
85}
86
87static dma_addr_t channel_read_CHAR(const struct txx9dmac_chan *dc)
88{
89 if (is_dmac64(dc))
90 return channel64_read_CHAR(dc);
91 else
92 return channel32_readl(dc, CHAR);
93}
94
95static void channel_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
96{
97 if (is_dmac64(dc))
98 channel64_write_CHAR(dc, val);
99 else
100 channel32_writel(dc, CHAR, val);
101}
102
103static struct txx9dmac_regs __iomem *__txx9dmac_regs(
104 const struct txx9dmac_dev *ddev)
105{
106 return ddev->regs;
107}
108
109static struct txx9dmac_regs32 __iomem *__txx9dmac_regs32(
110 const struct txx9dmac_dev *ddev)
111{
112 return ddev->regs;
113}
114
115#define dma64_readl(ddev, name) \
116 __raw_readl(&(__txx9dmac_regs(ddev)->name))
117#define dma64_writel(ddev, name, val) \
118 __raw_writel((val), &(__txx9dmac_regs(ddev)->name))
119
120#define dma32_readl(ddev, name) \
121 __raw_readl(&(__txx9dmac_regs32(ddev)->name))
122#define dma32_writel(ddev, name, val) \
123 __raw_writel((val), &(__txx9dmac_regs32(ddev)->name))
124
125#define dma_readl(ddev, name) \
126 (__is_dmac64(ddev) ? \
127 dma64_readl(ddev, name) : dma32_readl(ddev, name))
128#define dma_writel(ddev, name, val) \
129 (__is_dmac64(ddev) ? \
130 dma64_writel(ddev, name, val) : dma32_writel(ddev, name, val))
131
132static struct device *chan2dev(struct dma_chan *chan)
133{
134 return &chan->dev->device;
135}
136static struct device *chan2parent(struct dma_chan *chan)
137{
138 return chan->dev->device.parent;
139}
140
141static struct txx9dmac_desc *
142txd_to_txx9dmac_desc(struct dma_async_tx_descriptor *txd)
143{
144 return container_of(txd, struct txx9dmac_desc, txd);
145}
146
147static dma_addr_t desc_read_CHAR(const struct txx9dmac_chan *dc,
148 const struct txx9dmac_desc *desc)
149{
150 return is_dmac64(dc) ? desc->hwdesc.CHAR : desc->hwdesc32.CHAR;
151}
152
153static void desc_write_CHAR(const struct txx9dmac_chan *dc,
154 struct txx9dmac_desc *desc, dma_addr_t val)
155{
156 if (is_dmac64(dc))
157 desc->hwdesc.CHAR = val;
158 else
159 desc->hwdesc32.CHAR = val;
160}
161
162#define TXX9_DMA_MAX_COUNT 0x04000000
163
164#define TXX9_DMA_INITIAL_DESC_COUNT 64
165
166static struct txx9dmac_desc *txx9dmac_first_active(struct txx9dmac_chan *dc)
167{
168 return list_entry(dc->active_list.next,
169 struct txx9dmac_desc, desc_node);
170}
171
172static struct txx9dmac_desc *txx9dmac_last_active(struct txx9dmac_chan *dc)
173{
174 return list_entry(dc->active_list.prev,
175 struct txx9dmac_desc, desc_node);
176}
177
178static struct txx9dmac_desc *txx9dmac_first_queued(struct txx9dmac_chan *dc)
179{
180 return list_entry(dc->queue.next, struct txx9dmac_desc, desc_node);
181}
182
183static struct txx9dmac_desc *txx9dmac_last_child(struct txx9dmac_desc *desc)
184{
185 if (!list_empty(&desc->tx_list))
186 desc = list_entry(desc->tx_list.prev, typeof(*desc), desc_node);
187 return desc;
188}
189
190static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx);
191
192static struct txx9dmac_desc *txx9dmac_desc_alloc(struct txx9dmac_chan *dc,
193 gfp_t flags)
194{
195 struct txx9dmac_dev *ddev = dc->ddev;
196 struct txx9dmac_desc *desc;
197
198 desc = kzalloc(sizeof(*desc), flags);
199 if (!desc)
200 return NULL;
201 INIT_LIST_HEAD(&desc->tx_list);
202 dma_async_tx_descriptor_init(&desc->txd, &dc->chan);
203 desc->txd.tx_submit = txx9dmac_tx_submit;
204 /* txd.flags will be overwritten in prep funcs */
205 desc->txd.flags = DMA_CTRL_ACK;
206 desc->txd.phys = dma_map_single(chan2parent(&dc->chan), &desc->hwdesc,
207 ddev->descsize, DMA_TO_DEVICE);
208 return desc;
209}
210
211static struct txx9dmac_desc *txx9dmac_desc_get(struct txx9dmac_chan *dc)
212{
213 struct txx9dmac_desc *desc, *_desc;
214 struct txx9dmac_desc *ret = NULL;
215 unsigned int i = 0;
216
217 spin_lock_bh(&dc->lock);
218 list_for_each_entry_safe(desc, _desc, &dc->free_list, desc_node) {
219 if (async_tx_test_ack(&desc->txd)) {
220 list_del(&desc->desc_node);
221 ret = desc;
222 break;
223 }
224 dev_dbg(chan2dev(&dc->chan), "desc %p not ACKed\n", desc);
225 i++;
226 }
227 spin_unlock_bh(&dc->lock);
228
229 dev_vdbg(chan2dev(&dc->chan), "scanned %u descriptors on freelist\n",
230 i);
231 if (!ret) {
232 ret = txx9dmac_desc_alloc(dc, GFP_ATOMIC);
233 if (ret) {
234 spin_lock_bh(&dc->lock);
235 dc->descs_allocated++;
236 spin_unlock_bh(&dc->lock);
237 } else
238 dev_err(chan2dev(&dc->chan),
239 "not enough descriptors available\n");
240 }
241 return ret;
242}
243
244static void txx9dmac_sync_desc_for_cpu(struct txx9dmac_chan *dc,
245 struct txx9dmac_desc *desc)
246{
247 struct txx9dmac_dev *ddev = dc->ddev;
248 struct txx9dmac_desc *child;
249
250 list_for_each_entry(child, &desc->tx_list, desc_node)
251 dma_sync_single_for_cpu(chan2parent(&dc->chan),
252 child->txd.phys, ddev->descsize,
253 DMA_TO_DEVICE);
254 dma_sync_single_for_cpu(chan2parent(&dc->chan),
255 desc->txd.phys, ddev->descsize,
256 DMA_TO_DEVICE);
257}
258
259/*
260 * Move a descriptor, including any children, to the free list.
261 * `desc' must not be on any lists.
262 */
263static void txx9dmac_desc_put(struct txx9dmac_chan *dc,
264 struct txx9dmac_desc *desc)
265{
266 if (desc) {
267 struct txx9dmac_desc *child;
268
269 txx9dmac_sync_desc_for_cpu(dc, desc);
270
271 spin_lock_bh(&dc->lock);
272 list_for_each_entry(child, &desc->tx_list, desc_node)
273 dev_vdbg(chan2dev(&dc->chan),
274 "moving child desc %p to freelist\n",
275 child);
276 list_splice_init(&desc->tx_list, &dc->free_list);
277 dev_vdbg(chan2dev(&dc->chan), "moving desc %p to freelist\n",
278 desc);
279 list_add(&desc->desc_node, &dc->free_list);
280 spin_unlock_bh(&dc->lock);
281 }
282}
283
284/*----------------------------------------------------------------------*/
285
286static void txx9dmac_dump_regs(struct txx9dmac_chan *dc)
287{
288 if (is_dmac64(dc))
289 dev_err(chan2dev(&dc->chan),
290 " CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x"
291 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
292 (u64)channel64_read_CHAR(dc),
293 channel64_readq(dc, SAR),
294 channel64_readq(dc, DAR),
295 channel64_readl(dc, CNTR),
296 channel64_readl(dc, SAIR),
297 channel64_readl(dc, DAIR),
298 channel64_readl(dc, CCR),
299 channel64_readl(dc, CSR));
300 else
301 dev_err(chan2dev(&dc->chan),
302 " CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x"
303 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
304 channel32_readl(dc, CHAR),
305 channel32_readl(dc, SAR),
306 channel32_readl(dc, DAR),
307 channel32_readl(dc, CNTR),
308 channel32_readl(dc, SAIR),
309 channel32_readl(dc, DAIR),
310 channel32_readl(dc, CCR),
311 channel32_readl(dc, CSR));
312}
313
314static void txx9dmac_reset_chan(struct txx9dmac_chan *dc)
315{
316 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST);
317 if (is_dmac64(dc)) {
318 channel64_clear_CHAR(dc);
319 channel_writeq(dc, SAR, 0);
320 channel_writeq(dc, DAR, 0);
321 } else {
322 channel_writel(dc, CHAR, 0);
323 channel_writel(dc, SAR, 0);
324 channel_writel(dc, DAR, 0);
325 }
326 channel_writel(dc, CNTR, 0);
327 channel_writel(dc, SAIR, 0);
328 channel_writel(dc, DAIR, 0);
329 channel_writel(dc, CCR, 0);
330 mmiowb();
331}
332
333/* Called with dc->lock held and bh disabled */
334static void txx9dmac_dostart(struct txx9dmac_chan *dc,
335 struct txx9dmac_desc *first)
336{
337 struct txx9dmac_slave *ds = dc->chan.private;
338 u32 sai, dai;
339
340 dev_vdbg(chan2dev(&dc->chan), "dostart %u %p\n",
341 first->txd.cookie, first);
342 /* ASSERT: channel is idle */
343 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
344 dev_err(chan2dev(&dc->chan),
345 "BUG: Attempted to start non-idle channel\n");
346 txx9dmac_dump_regs(dc);
347 /* The tasklet will hopefully advance the queue... */
348 return;
349 }
350
351 if (is_dmac64(dc)) {
352 channel64_writel(dc, CNTR, 0);
353 channel64_writel(dc, CSR, 0xffffffff);
354 if (ds) {
355 if (ds->tx_reg) {
356 sai = ds->reg_width;
357 dai = 0;
358 } else {
359 sai = 0;
360 dai = ds->reg_width;
361 }
362 } else {
363 sai = 8;
364 dai = 8;
365 }
366 channel64_writel(dc, SAIR, sai);
367 channel64_writel(dc, DAIR, dai);
368 /* All 64-bit DMAC supports SMPCHN */
369 channel64_writel(dc, CCR, dc->ccr);
370 /* Writing a non zero value to CHAR will assert XFACT */
371 channel64_write_CHAR(dc, first->txd.phys);
372 } else {
373 channel32_writel(dc, CNTR, 0);
374 channel32_writel(dc, CSR, 0xffffffff);
375 if (ds) {
376 if (ds->tx_reg) {
377 sai = ds->reg_width;
378 dai = 0;
379 } else {
380 sai = 0;
381 dai = ds->reg_width;
382 }
383 } else {
384 sai = 4;
385 dai = 4;
386 }
387 channel32_writel(dc, SAIR, sai);
388 channel32_writel(dc, DAIR, dai);
389 if (txx9_dma_have_SMPCHN()) {
390 channel32_writel(dc, CCR, dc->ccr);
391 /* Writing a non zero value to CHAR will assert XFACT */
392 channel32_writel(dc, CHAR, first->txd.phys);
393 } else {
394 channel32_writel(dc, CHAR, first->txd.phys);
395 channel32_writel(dc, CCR, dc->ccr);
396 }
397 }
398}
399
400/*----------------------------------------------------------------------*/
401
402static void
403txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,
404 struct txx9dmac_desc *desc)
405{
406 dma_async_tx_callback callback;
407 void *param;
408 struct dma_async_tx_descriptor *txd = &desc->txd;
409
410 dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",
411 txd->cookie, desc);
412
413 dma_cookie_complete(txd);
414 callback = txd->callback;
415 param = txd->callback_param;
416
417 txx9dmac_sync_desc_for_cpu(dc, desc);
418 list_splice_init(&desc->tx_list, &dc->free_list);
419 list_move(&desc->desc_node, &dc->free_list);
420
421 dma_descriptor_unmap(txd);
422 /*
423 * The API requires that no submissions are done from a
424 * callback, so we don't need to drop the lock here
425 */
426 if (callback)
427 callback(param);
428 dma_run_dependencies(txd);
429}
430
431static void txx9dmac_dequeue(struct txx9dmac_chan *dc, struct list_head *list)
432{
433 struct txx9dmac_dev *ddev = dc->ddev;
434 struct txx9dmac_desc *desc;
435 struct txx9dmac_desc *prev = NULL;
436
437 BUG_ON(!list_empty(list));
438 do {
439 desc = txx9dmac_first_queued(dc);
440 if (prev) {
441 desc_write_CHAR(dc, prev, desc->txd.phys);
442 dma_sync_single_for_device(chan2parent(&dc->chan),
443 prev->txd.phys, ddev->descsize,
444 DMA_TO_DEVICE);
445 }
446 prev = txx9dmac_last_child(desc);
447 list_move_tail(&desc->desc_node, list);
448 /* Make chain-completion interrupt happen */
449 if ((desc->txd.flags & DMA_PREP_INTERRUPT) &&
450 !txx9dmac_chan_INTENT(dc))
451 break;
452 } while (!list_empty(&dc->queue));
453}
454
455static void txx9dmac_complete_all(struct txx9dmac_chan *dc)
456{
457 struct txx9dmac_desc *desc, *_desc;
458 LIST_HEAD(list);
459
460 /*
461 * Submit queued descriptors ASAP, i.e. before we go through
462 * the completed ones.
463 */
464 list_splice_init(&dc->active_list, &list);
465 if (!list_empty(&dc->queue)) {
466 txx9dmac_dequeue(dc, &dc->active_list);
467 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
468 }
469
470 list_for_each_entry_safe(desc, _desc, &list, desc_node)
471 txx9dmac_descriptor_complete(dc, desc);
472}
473
474static void txx9dmac_dump_desc(struct txx9dmac_chan *dc,
475 struct txx9dmac_hwdesc *desc)
476{
477 if (is_dmac64(dc)) {
478#ifdef TXX9_DMA_USE_SIMPLE_CHAIN
479 dev_crit(chan2dev(&dc->chan),
480 " desc: ch%#llx s%#llx d%#llx c%#x\n",
481 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR);
482#else
483 dev_crit(chan2dev(&dc->chan),
484 " desc: ch%#llx s%#llx d%#llx c%#x"
485 " si%#x di%#x cc%#x cs%#x\n",
486 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR,
487 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR);
488#endif
489 } else {
490 struct txx9dmac_hwdesc32 *d = (struct txx9dmac_hwdesc32 *)desc;
491#ifdef TXX9_DMA_USE_SIMPLE_CHAIN
492 dev_crit(chan2dev(&dc->chan),
493 " desc: ch%#x s%#x d%#x c%#x\n",
494 d->CHAR, d->SAR, d->DAR, d->CNTR);
495#else
496 dev_crit(chan2dev(&dc->chan),
497 " desc: ch%#x s%#x d%#x c%#x"
498 " si%#x di%#x cc%#x cs%#x\n",
499 d->CHAR, d->SAR, d->DAR, d->CNTR,
500 d->SAIR, d->DAIR, d->CCR, d->CSR);
501#endif
502 }
503}
504
505static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr)
506{
507 struct txx9dmac_desc *bad_desc;
508 struct txx9dmac_desc *child;
509 u32 errors;
510
511 /*
512 * The descriptor currently at the head of the active list is
513 * borked. Since we don't have any way to report errors, we'll
514 * just have to scream loudly and try to carry on.
515 */
516 dev_crit(chan2dev(&dc->chan), "Abnormal Chain Completion\n");
517 txx9dmac_dump_regs(dc);
518
519 bad_desc = txx9dmac_first_active(dc);
520 list_del_init(&bad_desc->desc_node);
521
522 /* Clear all error flags and try to restart the controller */
523 errors = csr & (TXX9_DMA_CSR_ABCHC |
524 TXX9_DMA_CSR_CFERR | TXX9_DMA_CSR_CHERR |
525 TXX9_DMA_CSR_DESERR | TXX9_DMA_CSR_SORERR);
526 channel_writel(dc, CSR, errors);
527
528 if (list_empty(&dc->active_list) && !list_empty(&dc->queue))
529 txx9dmac_dequeue(dc, &dc->active_list);
530 if (!list_empty(&dc->active_list))
531 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
532
533 dev_crit(chan2dev(&dc->chan),
534 "Bad descriptor submitted for DMA! (cookie: %d)\n",
535 bad_desc->txd.cookie);
536 txx9dmac_dump_desc(dc, &bad_desc->hwdesc);
537 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
538 txx9dmac_dump_desc(dc, &child->hwdesc);
539 /* Pretend the descriptor completed successfully */
540 txx9dmac_descriptor_complete(dc, bad_desc);
541}
542
543static void txx9dmac_scan_descriptors(struct txx9dmac_chan *dc)
544{
545 dma_addr_t chain;
546 struct txx9dmac_desc *desc, *_desc;
547 struct txx9dmac_desc *child;
548 u32 csr;
549
550 if (is_dmac64(dc)) {
551 chain = channel64_read_CHAR(dc);
552 csr = channel64_readl(dc, CSR);
553 channel64_writel(dc, CSR, csr);
554 } else {
555 chain = channel32_readl(dc, CHAR);
556 csr = channel32_readl(dc, CSR);
557 channel32_writel(dc, CSR, csr);
558 }
559 /* For dynamic chain, we should look at XFACT instead of NCHNC */
560 if (!(csr & (TXX9_DMA_CSR_XFACT | TXX9_DMA_CSR_ABCHC))) {
561 /* Everything we've submitted is done */
562 txx9dmac_complete_all(dc);
563 return;
564 }
565 if (!(csr & TXX9_DMA_CSR_CHNEN))
566 chain = 0; /* last descriptor of this chain */
567
568 dev_vdbg(chan2dev(&dc->chan), "scan_descriptors: char=%#llx\n",
569 (u64)chain);
570
571 list_for_each_entry_safe(desc, _desc, &dc->active_list, desc_node) {
572 if (desc_read_CHAR(dc, desc) == chain) {
573 /* This one is currently in progress */
574 if (csr & TXX9_DMA_CSR_ABCHC)
575 goto scan_done;
576 return;
577 }
578
579 list_for_each_entry(child, &desc->tx_list, desc_node)
580 if (desc_read_CHAR(dc, child) == chain) {
581 /* Currently in progress */
582 if (csr & TXX9_DMA_CSR_ABCHC)
583 goto scan_done;
584 return;
585 }
586
587 /*
588 * No descriptors so far seem to be in progress, i.e.
589 * this one must be done.
590 */
591 txx9dmac_descriptor_complete(dc, desc);
592 }
593scan_done:
594 if (csr & TXX9_DMA_CSR_ABCHC) {
595 txx9dmac_handle_error(dc, csr);
596 return;
597 }
598
599 dev_err(chan2dev(&dc->chan),
600 "BUG: All descriptors done, but channel not idle!\n");
601
602 /* Try to continue after resetting the channel... */
603 txx9dmac_reset_chan(dc);
604
605 if (!list_empty(&dc->queue)) {
606 txx9dmac_dequeue(dc, &dc->active_list);
607 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
608 }
609}
610
611static void txx9dmac_chan_tasklet(unsigned long data)
612{
613 int irq;
614 u32 csr;
615 struct txx9dmac_chan *dc;
616
617 dc = (struct txx9dmac_chan *)data;
618 csr = channel_readl(dc, CSR);
619 dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n", csr);
620
621 spin_lock(&dc->lock);
622 if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
623 TXX9_DMA_CSR_NTRNFC))
624 txx9dmac_scan_descriptors(dc);
625 spin_unlock(&dc->lock);
626 irq = dc->irq;
627
628 enable_irq(irq);
629}
630
631static irqreturn_t txx9dmac_chan_interrupt(int irq, void *dev_id)
632{
633 struct txx9dmac_chan *dc = dev_id;
634
635 dev_vdbg(chan2dev(&dc->chan), "interrupt: status=%#x\n",
636 channel_readl(dc, CSR));
637
638 tasklet_schedule(&dc->tasklet);
639 /*
640 * Just disable the interrupts. We'll turn them back on in the
641 * softirq handler.
642 */
643 disable_irq_nosync(irq);
644
645 return IRQ_HANDLED;
646}
647
648static void txx9dmac_tasklet(unsigned long data)
649{
650 int irq;
651 u32 csr;
652 struct txx9dmac_chan *dc;
653
654 struct txx9dmac_dev *ddev = (struct txx9dmac_dev *)data;
655 u32 mcr;
656 int i;
657
658 mcr = dma_readl(ddev, MCR);
659 dev_vdbg(ddev->chan[0]->dma.dev, "tasklet: mcr=%x\n", mcr);
660 for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
661 if ((mcr >> (24 + i)) & 0x11) {
662 dc = ddev->chan[i];
663 csr = channel_readl(dc, CSR);
664 dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n",
665 csr);
666 spin_lock(&dc->lock);
667 if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
668 TXX9_DMA_CSR_NTRNFC))
669 txx9dmac_scan_descriptors(dc);
670 spin_unlock(&dc->lock);
671 }
672 }
673 irq = ddev->irq;
674
675 enable_irq(irq);
676}
677
678static irqreturn_t txx9dmac_interrupt(int irq, void *dev_id)
679{
680 struct txx9dmac_dev *ddev = dev_id;
681
682 dev_vdbg(ddev->chan[0]->dma.dev, "interrupt: status=%#x\n",
683 dma_readl(ddev, MCR));
684
685 tasklet_schedule(&ddev->tasklet);
686 /*
687 * Just disable the interrupts. We'll turn them back on in the
688 * softirq handler.
689 */
690 disable_irq_nosync(irq);
691
692 return IRQ_HANDLED;
693}
694
695/*----------------------------------------------------------------------*/
696
697static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx)
698{
699 struct txx9dmac_desc *desc = txd_to_txx9dmac_desc(tx);
700 struct txx9dmac_chan *dc = to_txx9dmac_chan(tx->chan);
701 dma_cookie_t cookie;
702
703 spin_lock_bh(&dc->lock);
704 cookie = dma_cookie_assign(tx);
705
706 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u %p\n",
707 desc->txd.cookie, desc);
708
709 list_add_tail(&desc->desc_node, &dc->queue);
710 spin_unlock_bh(&dc->lock);
711
712 return cookie;
713}
714
715static struct dma_async_tx_descriptor *
716txx9dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
717 size_t len, unsigned long flags)
718{
719 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
720 struct txx9dmac_dev *ddev = dc->ddev;
721 struct txx9dmac_desc *desc;
722 struct txx9dmac_desc *first;
723 struct txx9dmac_desc *prev;
724 size_t xfer_count;
725 size_t offset;
726
727 dev_vdbg(chan2dev(chan), "prep_dma_memcpy d%#llx s%#llx l%#zx f%#lx\n",
728 (u64)dest, (u64)src, len, flags);
729
730 if (unlikely(!len)) {
731 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
732 return NULL;
733 }
734
735 prev = first = NULL;
736
737 for (offset = 0; offset < len; offset += xfer_count) {
738 xfer_count = min_t(size_t, len - offset, TXX9_DMA_MAX_COUNT);
739 /*
740 * Workaround for ERT-TX49H2-033, ERT-TX49H3-020,
741 * ERT-TX49H4-016 (slightly conservative)
742 */
743 if (__is_dmac64(ddev)) {
744 if (xfer_count > 0x100 &&
745 (xfer_count & 0xff) >= 0xfa &&
746 (xfer_count & 0xff) <= 0xff)
747 xfer_count -= 0x20;
748 } else {
749 if (xfer_count > 0x80 &&
750 (xfer_count & 0x7f) >= 0x7e &&
751 (xfer_count & 0x7f) <= 0x7f)
752 xfer_count -= 0x20;
753 }
754
755 desc = txx9dmac_desc_get(dc);
756 if (!desc) {
757 txx9dmac_desc_put(dc, first);
758 return NULL;
759 }
760
761 if (__is_dmac64(ddev)) {
762 desc->hwdesc.SAR = src + offset;
763 desc->hwdesc.DAR = dest + offset;
764 desc->hwdesc.CNTR = xfer_count;
765 txx9dmac_desc_set_nosimple(ddev, desc, 8, 8,
766 dc->ccr | TXX9_DMA_CCR_XFACT);
767 } else {
768 desc->hwdesc32.SAR = src + offset;
769 desc->hwdesc32.DAR = dest + offset;
770 desc->hwdesc32.CNTR = xfer_count;
771 txx9dmac_desc_set_nosimple(ddev, desc, 4, 4,
772 dc->ccr | TXX9_DMA_CCR_XFACT);
773 }
774
775 /*
776 * The descriptors on tx_list are not reachable from
777 * the dc->queue list or dc->active_list after a
778 * submit. If we put all descriptors on active_list,
779 * calling of callback on the completion will be more
780 * complex.
781 */
782 if (!first) {
783 first = desc;
784 } else {
785 desc_write_CHAR(dc, prev, desc->txd.phys);
786 dma_sync_single_for_device(chan2parent(&dc->chan),
787 prev->txd.phys, ddev->descsize,
788 DMA_TO_DEVICE);
789 list_add_tail(&desc->desc_node, &first->tx_list);
790 }
791 prev = desc;
792 }
793
794 /* Trigger interrupt after last block */
795 if (flags & DMA_PREP_INTERRUPT)
796 txx9dmac_desc_set_INTENT(ddev, prev);
797
798 desc_write_CHAR(dc, prev, 0);
799 dma_sync_single_for_device(chan2parent(&dc->chan),
800 prev->txd.phys, ddev->descsize,
801 DMA_TO_DEVICE);
802
803 first->txd.flags = flags;
804 first->len = len;
805
806 return &first->txd;
807}
808
809static struct dma_async_tx_descriptor *
810txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
811 unsigned int sg_len, enum dma_transfer_direction direction,
812 unsigned long flags, void *context)
813{
814 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
815 struct txx9dmac_dev *ddev = dc->ddev;
816 struct txx9dmac_slave *ds = chan->private;
817 struct txx9dmac_desc *prev;
818 struct txx9dmac_desc *first;
819 unsigned int i;
820 struct scatterlist *sg;
821
822 dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
823
824 BUG_ON(!ds || !ds->reg_width);
825 if (ds->tx_reg)
826 BUG_ON(direction != DMA_MEM_TO_DEV);
827 else
828 BUG_ON(direction != DMA_DEV_TO_MEM);
829 if (unlikely(!sg_len))
830 return NULL;
831
832 prev = first = NULL;
833
834 for_each_sg(sgl, sg, sg_len, i) {
835 struct txx9dmac_desc *desc;
836 dma_addr_t mem;
837 u32 sai, dai;
838
839 desc = txx9dmac_desc_get(dc);
840 if (!desc) {
841 txx9dmac_desc_put(dc, first);
842 return NULL;
843 }
844
845 mem = sg_dma_address(sg);
846
847 if (__is_dmac64(ddev)) {
848 if (direction == DMA_MEM_TO_DEV) {
849 desc->hwdesc.SAR = mem;
850 desc->hwdesc.DAR = ds->tx_reg;
851 } else {
852 desc->hwdesc.SAR = ds->rx_reg;
853 desc->hwdesc.DAR = mem;
854 }
855 desc->hwdesc.CNTR = sg_dma_len(sg);
856 } else {
857 if (direction == DMA_MEM_TO_DEV) {
858 desc->hwdesc32.SAR = mem;
859 desc->hwdesc32.DAR = ds->tx_reg;
860 } else {
861 desc->hwdesc32.SAR = ds->rx_reg;
862 desc->hwdesc32.DAR = mem;
863 }
864 desc->hwdesc32.CNTR = sg_dma_len(sg);
865 }
866 if (direction == DMA_MEM_TO_DEV) {
867 sai = ds->reg_width;
868 dai = 0;
869 } else {
870 sai = 0;
871 dai = ds->reg_width;
872 }
873 txx9dmac_desc_set_nosimple(ddev, desc, sai, dai,
874 dc->ccr | TXX9_DMA_CCR_XFACT);
875
876 if (!first) {
877 first = desc;
878 } else {
879 desc_write_CHAR(dc, prev, desc->txd.phys);
880 dma_sync_single_for_device(chan2parent(&dc->chan),
881 prev->txd.phys,
882 ddev->descsize,
883 DMA_TO_DEVICE);
884 list_add_tail(&desc->desc_node, &first->tx_list);
885 }
886 prev = desc;
887 }
888
889 /* Trigger interrupt after last block */
890 if (flags & DMA_PREP_INTERRUPT)
891 txx9dmac_desc_set_INTENT(ddev, prev);
892
893 desc_write_CHAR(dc, prev, 0);
894 dma_sync_single_for_device(chan2parent(&dc->chan),
895 prev->txd.phys, ddev->descsize,
896 DMA_TO_DEVICE);
897
898 first->txd.flags = flags;
899 first->len = 0;
900
901 return &first->txd;
902}
903
904static int txx9dmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
905 unsigned long arg)
906{
907 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
908 struct txx9dmac_desc *desc, *_desc;
909 LIST_HEAD(list);
910
911 /* Only supports DMA_TERMINATE_ALL */
912 if (cmd != DMA_TERMINATE_ALL)
913 return -EINVAL;
914
915 dev_vdbg(chan2dev(chan), "terminate_all\n");
916 spin_lock_bh(&dc->lock);
917
918 txx9dmac_reset_chan(dc);
919
920 /* active_list entries will end up before queued entries */
921 list_splice_init(&dc->queue, &list);
922 list_splice_init(&dc->active_list, &list);
923
924 spin_unlock_bh(&dc->lock);
925
926 /* Flush all pending and queued descriptors */
927 list_for_each_entry_safe(desc, _desc, &list, desc_node)
928 txx9dmac_descriptor_complete(dc, desc);
929
930 return 0;
931}
932
933static enum dma_status
934txx9dmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
935 struct dma_tx_state *txstate)
936{
937 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
938 enum dma_status ret;
939
940 ret = dma_cookie_status(chan, cookie, txstate);
941 if (ret == DMA_COMPLETE)
942 return DMA_COMPLETE;
943
944 spin_lock_bh(&dc->lock);
945 txx9dmac_scan_descriptors(dc);
946 spin_unlock_bh(&dc->lock);
947
948 return dma_cookie_status(chan, cookie, txstate);
949}
950
951static void txx9dmac_chain_dynamic(struct txx9dmac_chan *dc,
952 struct txx9dmac_desc *prev)
953{
954 struct txx9dmac_dev *ddev = dc->ddev;
955 struct txx9dmac_desc *desc;
956 LIST_HEAD(list);
957
958 prev = txx9dmac_last_child(prev);
959 txx9dmac_dequeue(dc, &list);
960 desc = list_entry(list.next, struct txx9dmac_desc, desc_node);
961 desc_write_CHAR(dc, prev, desc->txd.phys);
962 dma_sync_single_for_device(chan2parent(&dc->chan),
963 prev->txd.phys, ddev->descsize,
964 DMA_TO_DEVICE);
965 mmiowb();
966 if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) &&
967 channel_read_CHAR(dc) == prev->txd.phys)
968 /* Restart chain DMA */
969 channel_write_CHAR(dc, desc->txd.phys);
970 list_splice_tail(&list, &dc->active_list);
971}
972
973static void txx9dmac_issue_pending(struct dma_chan *chan)
974{
975 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
976
977 spin_lock_bh(&dc->lock);
978
979 if (!list_empty(&dc->active_list))
980 txx9dmac_scan_descriptors(dc);
981 if (!list_empty(&dc->queue)) {
982 if (list_empty(&dc->active_list)) {
983 txx9dmac_dequeue(dc, &dc->active_list);
984 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
985 } else if (txx9_dma_have_SMPCHN()) {
986 struct txx9dmac_desc *prev = txx9dmac_last_active(dc);
987
988 if (!(prev->txd.flags & DMA_PREP_INTERRUPT) ||
989 txx9dmac_chan_INTENT(dc))
990 txx9dmac_chain_dynamic(dc, prev);
991 }
992 }
993
994 spin_unlock_bh(&dc->lock);
995}
996
997static int txx9dmac_alloc_chan_resources(struct dma_chan *chan)
998{
999 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1000 struct txx9dmac_slave *ds = chan->private;
1001 struct txx9dmac_desc *desc;
1002 int i;
1003
1004 dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
1005
1006 /* ASSERT: channel is idle */
1007 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
1008 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1009 return -EIO;
1010 }
1011
1012 dma_cookie_init(chan);
1013
1014 dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE;
1015 txx9dmac_chan_set_SMPCHN(dc);
1016 if (!txx9_dma_have_SMPCHN() || (dc->ccr & TXX9_DMA_CCR_SMPCHN))
1017 dc->ccr |= TXX9_DMA_CCR_INTENC;
1018 if (chan->device->device_prep_dma_memcpy) {
1019 if (ds)
1020 return -EINVAL;
1021 dc->ccr |= TXX9_DMA_CCR_XFSZ_X8;
1022 } else {
1023 if (!ds ||
1024 (ds->tx_reg && ds->rx_reg) || (!ds->tx_reg && !ds->rx_reg))
1025 return -EINVAL;
1026 dc->ccr |= TXX9_DMA_CCR_EXTRQ |
1027 TXX9_DMA_CCR_XFSZ(__ffs(ds->reg_width));
1028 txx9dmac_chan_set_INTENT(dc);
1029 }
1030
1031 spin_lock_bh(&dc->lock);
1032 i = dc->descs_allocated;
1033 while (dc->descs_allocated < TXX9_DMA_INITIAL_DESC_COUNT) {
1034 spin_unlock_bh(&dc->lock);
1035
1036 desc = txx9dmac_desc_alloc(dc, GFP_KERNEL);
1037 if (!desc) {
1038 dev_info(chan2dev(chan),
1039 "only allocated %d descriptors\n", i);
1040 spin_lock_bh(&dc->lock);
1041 break;
1042 }
1043 txx9dmac_desc_put(dc, desc);
1044
1045 spin_lock_bh(&dc->lock);
1046 i = ++dc->descs_allocated;
1047 }
1048 spin_unlock_bh(&dc->lock);
1049
1050 dev_dbg(chan2dev(chan),
1051 "alloc_chan_resources allocated %d descriptors\n", i);
1052
1053 return i;
1054}
1055
1056static void txx9dmac_free_chan_resources(struct dma_chan *chan)
1057{
1058 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1059 struct txx9dmac_dev *ddev = dc->ddev;
1060 struct txx9dmac_desc *desc, *_desc;
1061 LIST_HEAD(list);
1062
1063 dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
1064 dc->descs_allocated);
1065
1066 /* ASSERT: channel is idle */
1067 BUG_ON(!list_empty(&dc->active_list));
1068 BUG_ON(!list_empty(&dc->queue));
1069 BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT);
1070
1071 spin_lock_bh(&dc->lock);
1072 list_splice_init(&dc->free_list, &list);
1073 dc->descs_allocated = 0;
1074 spin_unlock_bh(&dc->lock);
1075
1076 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1077 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1078 dma_unmap_single(chan2parent(chan), desc->txd.phys,
1079 ddev->descsize, DMA_TO_DEVICE);
1080 kfree(desc);
1081 }
1082
1083 dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
1084}
1085
1086/*----------------------------------------------------------------------*/
1087
1088static void txx9dmac_off(struct txx9dmac_dev *ddev)
1089{
1090 dma_writel(ddev, MCR, 0);
1091 mmiowb();
1092}
1093
1094static int __init txx9dmac_chan_probe(struct platform_device *pdev)
1095{
1096 struct txx9dmac_chan_platform_data *cpdata =
1097 dev_get_platdata(&pdev->dev);
1098 struct platform_device *dmac_dev = cpdata->dmac_dev;
1099 struct txx9dmac_platform_data *pdata = dev_get_platdata(&dmac_dev->dev);
1100 struct txx9dmac_chan *dc;
1101 int err;
1102 int ch = pdev->id % TXX9_DMA_MAX_NR_CHANNELS;
1103 int irq;
1104
1105 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1106 if (!dc)
1107 return -ENOMEM;
1108
1109 dc->dma.dev = &pdev->dev;
1110 dc->dma.device_alloc_chan_resources = txx9dmac_alloc_chan_resources;
1111 dc->dma.device_free_chan_resources = txx9dmac_free_chan_resources;
1112 dc->dma.device_control = txx9dmac_control;
1113 dc->dma.device_tx_status = txx9dmac_tx_status;
1114 dc->dma.device_issue_pending = txx9dmac_issue_pending;
1115 if (pdata && pdata->memcpy_chan == ch) {
1116 dc->dma.device_prep_dma_memcpy = txx9dmac_prep_dma_memcpy;
1117 dma_cap_set(DMA_MEMCPY, dc->dma.cap_mask);
1118 } else {
1119 dc->dma.device_prep_slave_sg = txx9dmac_prep_slave_sg;
1120 dma_cap_set(DMA_SLAVE, dc->dma.cap_mask);
1121 dma_cap_set(DMA_PRIVATE, dc->dma.cap_mask);
1122 }
1123
1124 INIT_LIST_HEAD(&dc->dma.channels);
1125 dc->ddev = platform_get_drvdata(dmac_dev);
1126 if (dc->ddev->irq < 0) {
1127 irq = platform_get_irq(pdev, 0);
1128 if (irq < 0)
1129 return irq;
1130 tasklet_init(&dc->tasklet, txx9dmac_chan_tasklet,
1131 (unsigned long)dc);
1132 dc->irq = irq;
1133 err = devm_request_irq(&pdev->dev, dc->irq,
1134 txx9dmac_chan_interrupt, 0, dev_name(&pdev->dev), dc);
1135 if (err)
1136 return err;
1137 } else
1138 dc->irq = -1;
1139 dc->ddev->chan[ch] = dc;
1140 dc->chan.device = &dc->dma;
1141 list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);
1142 dma_cookie_init(&dc->chan);
1143
1144 if (is_dmac64(dc))
1145 dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];
1146 else
1147 dc->ch_regs = &__txx9dmac_regs32(dc->ddev)->CHAN[ch];
1148 spin_lock_init(&dc->lock);
1149
1150 INIT_LIST_HEAD(&dc->active_list);
1151 INIT_LIST_HEAD(&dc->queue);
1152 INIT_LIST_HEAD(&dc->free_list);
1153
1154 txx9dmac_reset_chan(dc);
1155
1156 platform_set_drvdata(pdev, dc);
1157
1158 err = dma_async_device_register(&dc->dma);
1159 if (err)
1160 return err;
1161 dev_dbg(&pdev->dev, "TXx9 DMA Channel (dma%d%s%s)\n",
1162 dc->dma.dev_id,
1163 dma_has_cap(DMA_MEMCPY, dc->dma.cap_mask) ? " memcpy" : "",
1164 dma_has_cap(DMA_SLAVE, dc->dma.cap_mask) ? " slave" : "");
1165
1166 return 0;
1167}
1168
1169static int txx9dmac_chan_remove(struct platform_device *pdev)
1170{
1171 struct txx9dmac_chan *dc = platform_get_drvdata(pdev);
1172
1173 dma_async_device_unregister(&dc->dma);
1174 if (dc->irq >= 0)
1175 tasklet_kill(&dc->tasklet);
1176 dc->ddev->chan[pdev->id % TXX9_DMA_MAX_NR_CHANNELS] = NULL;
1177 return 0;
1178}
1179
1180static int __init txx9dmac_probe(struct platform_device *pdev)
1181{
1182 struct txx9dmac_platform_data *pdata = dev_get_platdata(&pdev->dev);
1183 struct resource *io;
1184 struct txx9dmac_dev *ddev;
1185 u32 mcr;
1186 int err;
1187
1188 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1189 if (!io)
1190 return -EINVAL;
1191
1192 ddev = devm_kzalloc(&pdev->dev, sizeof(*ddev), GFP_KERNEL);
1193 if (!ddev)
1194 return -ENOMEM;
1195
1196 if (!devm_request_mem_region(&pdev->dev, io->start, resource_size(io),
1197 dev_name(&pdev->dev)))
1198 return -EBUSY;
1199
1200 ddev->regs = devm_ioremap(&pdev->dev, io->start, resource_size(io));
1201 if (!ddev->regs)
1202 return -ENOMEM;
1203 ddev->have_64bit_regs = pdata->have_64bit_regs;
1204 if (__is_dmac64(ddev))
1205 ddev->descsize = sizeof(struct txx9dmac_hwdesc);
1206 else
1207 ddev->descsize = sizeof(struct txx9dmac_hwdesc32);
1208
1209 /* force dma off, just in case */
1210 txx9dmac_off(ddev);
1211
1212 ddev->irq = platform_get_irq(pdev, 0);
1213 if (ddev->irq >= 0) {
1214 tasklet_init(&ddev->tasklet, txx9dmac_tasklet,
1215 (unsigned long)ddev);
1216 err = devm_request_irq(&pdev->dev, ddev->irq,
1217 txx9dmac_interrupt, 0, dev_name(&pdev->dev), ddev);
1218 if (err)
1219 return err;
1220 }
1221
1222 mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
1223 if (pdata && pdata->memcpy_chan >= 0)
1224 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
1225 dma_writel(ddev, MCR, mcr);
1226
1227 platform_set_drvdata(pdev, ddev);
1228 return 0;
1229}
1230
1231static int txx9dmac_remove(struct platform_device *pdev)
1232{
1233 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1234
1235 txx9dmac_off(ddev);
1236 if (ddev->irq >= 0)
1237 tasklet_kill(&ddev->tasklet);
1238 return 0;
1239}
1240
1241static void txx9dmac_shutdown(struct platform_device *pdev)
1242{
1243 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1244
1245 txx9dmac_off(ddev);
1246}
1247
1248static int txx9dmac_suspend_noirq(struct device *dev)
1249{
1250 struct platform_device *pdev = to_platform_device(dev);
1251 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1252
1253 txx9dmac_off(ddev);
1254 return 0;
1255}
1256
1257static int txx9dmac_resume_noirq(struct device *dev)
1258{
1259 struct platform_device *pdev = to_platform_device(dev);
1260 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1261 struct txx9dmac_platform_data *pdata = dev_get_platdata(&pdev->dev);
1262 u32 mcr;
1263
1264 mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
1265 if (pdata && pdata->memcpy_chan >= 0)
1266 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
1267 dma_writel(ddev, MCR, mcr);
1268 return 0;
1269
1270}
1271
1272static const struct dev_pm_ops txx9dmac_dev_pm_ops = {
1273 .suspend_noirq = txx9dmac_suspend_noirq,
1274 .resume_noirq = txx9dmac_resume_noirq,
1275};
1276
1277static struct platform_driver txx9dmac_chan_driver = {
1278 .remove = txx9dmac_chan_remove,
1279 .driver = {
1280 .name = "txx9dmac-chan",
1281 },
1282};
1283
1284static struct platform_driver txx9dmac_driver = {
1285 .remove = txx9dmac_remove,
1286 .shutdown = txx9dmac_shutdown,
1287 .driver = {
1288 .name = "txx9dmac",
1289 .pm = &txx9dmac_dev_pm_ops,
1290 },
1291};
1292
1293static int __init txx9dmac_init(void)
1294{
1295 int rc;
1296
1297 rc = platform_driver_probe(&txx9dmac_driver, txx9dmac_probe);
1298 if (!rc) {
1299 rc = platform_driver_probe(&txx9dmac_chan_driver,
1300 txx9dmac_chan_probe);
1301 if (rc)
1302 platform_driver_unregister(&txx9dmac_driver);
1303 }
1304 return rc;
1305}
1306module_init(txx9dmac_init);
1307
1308static void __exit txx9dmac_exit(void)
1309{
1310 platform_driver_unregister(&txx9dmac_chan_driver);
1311 platform_driver_unregister(&txx9dmac_driver);
1312}
1313module_exit(txx9dmac_exit);
1314
1315MODULE_LICENSE("GPL");
1316MODULE_DESCRIPTION("TXx9 DMA Controller driver");
1317MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
1318MODULE_ALIAS("platform:txx9dmac");
1319MODULE_ALIAS("platform:txx9dmac-chan");
1/*
2 * Driver for the TXx9 SoC DMA Controller
3 *
4 * Copyright (C) 2009 Atsushi Nemoto
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/dma-mapping.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/slab.h>
17#include <linux/scatterlist.h>
18#include "txx9dmac.h"
19
20static struct txx9dmac_chan *to_txx9dmac_chan(struct dma_chan *chan)
21{
22 return container_of(chan, struct txx9dmac_chan, chan);
23}
24
25static struct txx9dmac_cregs __iomem *__dma_regs(const struct txx9dmac_chan *dc)
26{
27 return dc->ch_regs;
28}
29
30static struct txx9dmac_cregs32 __iomem *__dma_regs32(
31 const struct txx9dmac_chan *dc)
32{
33 return dc->ch_regs;
34}
35
36#define channel64_readq(dc, name) \
37 __raw_readq(&(__dma_regs(dc)->name))
38#define channel64_writeq(dc, name, val) \
39 __raw_writeq((val), &(__dma_regs(dc)->name))
40#define channel64_readl(dc, name) \
41 __raw_readl(&(__dma_regs(dc)->name))
42#define channel64_writel(dc, name, val) \
43 __raw_writel((val), &(__dma_regs(dc)->name))
44
45#define channel32_readl(dc, name) \
46 __raw_readl(&(__dma_regs32(dc)->name))
47#define channel32_writel(dc, name, val) \
48 __raw_writel((val), &(__dma_regs32(dc)->name))
49
50#define channel_readq(dc, name) channel64_readq(dc, name)
51#define channel_writeq(dc, name, val) channel64_writeq(dc, name, val)
52#define channel_readl(dc, name) \
53 (is_dmac64(dc) ? \
54 channel64_readl(dc, name) : channel32_readl(dc, name))
55#define channel_writel(dc, name, val) \
56 (is_dmac64(dc) ? \
57 channel64_writel(dc, name, val) : channel32_writel(dc, name, val))
58
59static dma_addr_t channel64_read_CHAR(const struct txx9dmac_chan *dc)
60{
61 if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
62 return channel64_readq(dc, CHAR);
63 else
64 return channel64_readl(dc, CHAR);
65}
66
67static void channel64_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
68{
69 if (sizeof(__dma_regs(dc)->CHAR) == sizeof(u64))
70 channel64_writeq(dc, CHAR, val);
71 else
72 channel64_writel(dc, CHAR, val);
73}
74
75static void channel64_clear_CHAR(const struct txx9dmac_chan *dc)
76{
77#if defined(CONFIG_32BIT) && !defined(CONFIG_64BIT_PHYS_ADDR)
78 channel64_writel(dc, CHAR, 0);
79 channel64_writel(dc, __pad_CHAR, 0);
80#else
81 channel64_writeq(dc, CHAR, 0);
82#endif
83}
84
85static dma_addr_t channel_read_CHAR(const struct txx9dmac_chan *dc)
86{
87 if (is_dmac64(dc))
88 return channel64_read_CHAR(dc);
89 else
90 return channel32_readl(dc, CHAR);
91}
92
93static void channel_write_CHAR(const struct txx9dmac_chan *dc, dma_addr_t val)
94{
95 if (is_dmac64(dc))
96 channel64_write_CHAR(dc, val);
97 else
98 channel32_writel(dc, CHAR, val);
99}
100
101static struct txx9dmac_regs __iomem *__txx9dmac_regs(
102 const struct txx9dmac_dev *ddev)
103{
104 return ddev->regs;
105}
106
107static struct txx9dmac_regs32 __iomem *__txx9dmac_regs32(
108 const struct txx9dmac_dev *ddev)
109{
110 return ddev->regs;
111}
112
113#define dma64_readl(ddev, name) \
114 __raw_readl(&(__txx9dmac_regs(ddev)->name))
115#define dma64_writel(ddev, name, val) \
116 __raw_writel((val), &(__txx9dmac_regs(ddev)->name))
117
118#define dma32_readl(ddev, name) \
119 __raw_readl(&(__txx9dmac_regs32(ddev)->name))
120#define dma32_writel(ddev, name, val) \
121 __raw_writel((val), &(__txx9dmac_regs32(ddev)->name))
122
123#define dma_readl(ddev, name) \
124 (__is_dmac64(ddev) ? \
125 dma64_readl(ddev, name) : dma32_readl(ddev, name))
126#define dma_writel(ddev, name, val) \
127 (__is_dmac64(ddev) ? \
128 dma64_writel(ddev, name, val) : dma32_writel(ddev, name, val))
129
130static struct device *chan2dev(struct dma_chan *chan)
131{
132 return &chan->dev->device;
133}
134static struct device *chan2parent(struct dma_chan *chan)
135{
136 return chan->dev->device.parent;
137}
138
139static struct txx9dmac_desc *
140txd_to_txx9dmac_desc(struct dma_async_tx_descriptor *txd)
141{
142 return container_of(txd, struct txx9dmac_desc, txd);
143}
144
145static dma_addr_t desc_read_CHAR(const struct txx9dmac_chan *dc,
146 const struct txx9dmac_desc *desc)
147{
148 return is_dmac64(dc) ? desc->hwdesc.CHAR : desc->hwdesc32.CHAR;
149}
150
151static void desc_write_CHAR(const struct txx9dmac_chan *dc,
152 struct txx9dmac_desc *desc, dma_addr_t val)
153{
154 if (is_dmac64(dc))
155 desc->hwdesc.CHAR = val;
156 else
157 desc->hwdesc32.CHAR = val;
158}
159
160#define TXX9_DMA_MAX_COUNT 0x04000000
161
162#define TXX9_DMA_INITIAL_DESC_COUNT 64
163
164static struct txx9dmac_desc *txx9dmac_first_active(struct txx9dmac_chan *dc)
165{
166 return list_entry(dc->active_list.next,
167 struct txx9dmac_desc, desc_node);
168}
169
170static struct txx9dmac_desc *txx9dmac_last_active(struct txx9dmac_chan *dc)
171{
172 return list_entry(dc->active_list.prev,
173 struct txx9dmac_desc, desc_node);
174}
175
176static struct txx9dmac_desc *txx9dmac_first_queued(struct txx9dmac_chan *dc)
177{
178 return list_entry(dc->queue.next, struct txx9dmac_desc, desc_node);
179}
180
181static struct txx9dmac_desc *txx9dmac_last_child(struct txx9dmac_desc *desc)
182{
183 if (!list_empty(&desc->tx_list))
184 desc = list_entry(desc->tx_list.prev, typeof(*desc), desc_node);
185 return desc;
186}
187
188static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx);
189
190static struct txx9dmac_desc *txx9dmac_desc_alloc(struct txx9dmac_chan *dc,
191 gfp_t flags)
192{
193 struct txx9dmac_dev *ddev = dc->ddev;
194 struct txx9dmac_desc *desc;
195
196 desc = kzalloc(sizeof(*desc), flags);
197 if (!desc)
198 return NULL;
199 INIT_LIST_HEAD(&desc->tx_list);
200 dma_async_tx_descriptor_init(&desc->txd, &dc->chan);
201 desc->txd.tx_submit = txx9dmac_tx_submit;
202 /* txd.flags will be overwritten in prep funcs */
203 desc->txd.flags = DMA_CTRL_ACK;
204 desc->txd.phys = dma_map_single(chan2parent(&dc->chan), &desc->hwdesc,
205 ddev->descsize, DMA_TO_DEVICE);
206 return desc;
207}
208
209static struct txx9dmac_desc *txx9dmac_desc_get(struct txx9dmac_chan *dc)
210{
211 struct txx9dmac_desc *desc, *_desc;
212 struct txx9dmac_desc *ret = NULL;
213 unsigned int i = 0;
214
215 spin_lock_bh(&dc->lock);
216 list_for_each_entry_safe(desc, _desc, &dc->free_list, desc_node) {
217 if (async_tx_test_ack(&desc->txd)) {
218 list_del(&desc->desc_node);
219 ret = desc;
220 break;
221 }
222 dev_dbg(chan2dev(&dc->chan), "desc %p not ACKed\n", desc);
223 i++;
224 }
225 spin_unlock_bh(&dc->lock);
226
227 dev_vdbg(chan2dev(&dc->chan), "scanned %u descriptors on freelist\n",
228 i);
229 if (!ret) {
230 ret = txx9dmac_desc_alloc(dc, GFP_ATOMIC);
231 if (ret) {
232 spin_lock_bh(&dc->lock);
233 dc->descs_allocated++;
234 spin_unlock_bh(&dc->lock);
235 } else
236 dev_err(chan2dev(&dc->chan),
237 "not enough descriptors available\n");
238 }
239 return ret;
240}
241
242static void txx9dmac_sync_desc_for_cpu(struct txx9dmac_chan *dc,
243 struct txx9dmac_desc *desc)
244{
245 struct txx9dmac_dev *ddev = dc->ddev;
246 struct txx9dmac_desc *child;
247
248 list_for_each_entry(child, &desc->tx_list, desc_node)
249 dma_sync_single_for_cpu(chan2parent(&dc->chan),
250 child->txd.phys, ddev->descsize,
251 DMA_TO_DEVICE);
252 dma_sync_single_for_cpu(chan2parent(&dc->chan),
253 desc->txd.phys, ddev->descsize,
254 DMA_TO_DEVICE);
255}
256
257/*
258 * Move a descriptor, including any children, to the free list.
259 * `desc' must not be on any lists.
260 */
261static void txx9dmac_desc_put(struct txx9dmac_chan *dc,
262 struct txx9dmac_desc *desc)
263{
264 if (desc) {
265 struct txx9dmac_desc *child;
266
267 txx9dmac_sync_desc_for_cpu(dc, desc);
268
269 spin_lock_bh(&dc->lock);
270 list_for_each_entry(child, &desc->tx_list, desc_node)
271 dev_vdbg(chan2dev(&dc->chan),
272 "moving child desc %p to freelist\n",
273 child);
274 list_splice_init(&desc->tx_list, &dc->free_list);
275 dev_vdbg(chan2dev(&dc->chan), "moving desc %p to freelist\n",
276 desc);
277 list_add(&desc->desc_node, &dc->free_list);
278 spin_unlock_bh(&dc->lock);
279 }
280}
281
282/* Called with dc->lock held and bh disabled */
283static dma_cookie_t
284txx9dmac_assign_cookie(struct txx9dmac_chan *dc, struct txx9dmac_desc *desc)
285{
286 dma_cookie_t cookie = dc->chan.cookie;
287
288 if (++cookie < 0)
289 cookie = 1;
290
291 dc->chan.cookie = cookie;
292 desc->txd.cookie = cookie;
293
294 return cookie;
295}
296
297/*----------------------------------------------------------------------*/
298
299static void txx9dmac_dump_regs(struct txx9dmac_chan *dc)
300{
301 if (is_dmac64(dc))
302 dev_err(chan2dev(&dc->chan),
303 " CHAR: %#llx SAR: %#llx DAR: %#llx CNTR: %#x"
304 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
305 (u64)channel64_read_CHAR(dc),
306 channel64_readq(dc, SAR),
307 channel64_readq(dc, DAR),
308 channel64_readl(dc, CNTR),
309 channel64_readl(dc, SAIR),
310 channel64_readl(dc, DAIR),
311 channel64_readl(dc, CCR),
312 channel64_readl(dc, CSR));
313 else
314 dev_err(chan2dev(&dc->chan),
315 " CHAR: %#x SAR: %#x DAR: %#x CNTR: %#x"
316 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n",
317 channel32_readl(dc, CHAR),
318 channel32_readl(dc, SAR),
319 channel32_readl(dc, DAR),
320 channel32_readl(dc, CNTR),
321 channel32_readl(dc, SAIR),
322 channel32_readl(dc, DAIR),
323 channel32_readl(dc, CCR),
324 channel32_readl(dc, CSR));
325}
326
327static void txx9dmac_reset_chan(struct txx9dmac_chan *dc)
328{
329 channel_writel(dc, CCR, TXX9_DMA_CCR_CHRST);
330 if (is_dmac64(dc)) {
331 channel64_clear_CHAR(dc);
332 channel_writeq(dc, SAR, 0);
333 channel_writeq(dc, DAR, 0);
334 } else {
335 channel_writel(dc, CHAR, 0);
336 channel_writel(dc, SAR, 0);
337 channel_writel(dc, DAR, 0);
338 }
339 channel_writel(dc, CNTR, 0);
340 channel_writel(dc, SAIR, 0);
341 channel_writel(dc, DAIR, 0);
342 channel_writel(dc, CCR, 0);
343 mmiowb();
344}
345
346/* Called with dc->lock held and bh disabled */
347static void txx9dmac_dostart(struct txx9dmac_chan *dc,
348 struct txx9dmac_desc *first)
349{
350 struct txx9dmac_slave *ds = dc->chan.private;
351 u32 sai, dai;
352
353 dev_vdbg(chan2dev(&dc->chan), "dostart %u %p\n",
354 first->txd.cookie, first);
355 /* ASSERT: channel is idle */
356 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
357 dev_err(chan2dev(&dc->chan),
358 "BUG: Attempted to start non-idle channel\n");
359 txx9dmac_dump_regs(dc);
360 /* The tasklet will hopefully advance the queue... */
361 return;
362 }
363
364 if (is_dmac64(dc)) {
365 channel64_writel(dc, CNTR, 0);
366 channel64_writel(dc, CSR, 0xffffffff);
367 if (ds) {
368 if (ds->tx_reg) {
369 sai = ds->reg_width;
370 dai = 0;
371 } else {
372 sai = 0;
373 dai = ds->reg_width;
374 }
375 } else {
376 sai = 8;
377 dai = 8;
378 }
379 channel64_writel(dc, SAIR, sai);
380 channel64_writel(dc, DAIR, dai);
381 /* All 64-bit DMAC supports SMPCHN */
382 channel64_writel(dc, CCR, dc->ccr);
383 /* Writing a non zero value to CHAR will assert XFACT */
384 channel64_write_CHAR(dc, first->txd.phys);
385 } else {
386 channel32_writel(dc, CNTR, 0);
387 channel32_writel(dc, CSR, 0xffffffff);
388 if (ds) {
389 if (ds->tx_reg) {
390 sai = ds->reg_width;
391 dai = 0;
392 } else {
393 sai = 0;
394 dai = ds->reg_width;
395 }
396 } else {
397 sai = 4;
398 dai = 4;
399 }
400 channel32_writel(dc, SAIR, sai);
401 channel32_writel(dc, DAIR, dai);
402 if (txx9_dma_have_SMPCHN()) {
403 channel32_writel(dc, CCR, dc->ccr);
404 /* Writing a non zero value to CHAR will assert XFACT */
405 channel32_writel(dc, CHAR, first->txd.phys);
406 } else {
407 channel32_writel(dc, CHAR, first->txd.phys);
408 channel32_writel(dc, CCR, dc->ccr);
409 }
410 }
411}
412
413/*----------------------------------------------------------------------*/
414
415static void
416txx9dmac_descriptor_complete(struct txx9dmac_chan *dc,
417 struct txx9dmac_desc *desc)
418{
419 dma_async_tx_callback callback;
420 void *param;
421 struct dma_async_tx_descriptor *txd = &desc->txd;
422 struct txx9dmac_slave *ds = dc->chan.private;
423
424 dev_vdbg(chan2dev(&dc->chan), "descriptor %u %p complete\n",
425 txd->cookie, desc);
426
427 dc->completed = txd->cookie;
428 callback = txd->callback;
429 param = txd->callback_param;
430
431 txx9dmac_sync_desc_for_cpu(dc, desc);
432 list_splice_init(&desc->tx_list, &dc->free_list);
433 list_move(&desc->desc_node, &dc->free_list);
434
435 if (!ds) {
436 dma_addr_t dmaaddr;
437 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
438 dmaaddr = is_dmac64(dc) ?
439 desc->hwdesc.DAR : desc->hwdesc32.DAR;
440 if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
441 dma_unmap_single(chan2parent(&dc->chan),
442 dmaaddr, desc->len, DMA_FROM_DEVICE);
443 else
444 dma_unmap_page(chan2parent(&dc->chan),
445 dmaaddr, desc->len, DMA_FROM_DEVICE);
446 }
447 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
448 dmaaddr = is_dmac64(dc) ?
449 desc->hwdesc.SAR : desc->hwdesc32.SAR;
450 if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
451 dma_unmap_single(chan2parent(&dc->chan),
452 dmaaddr, desc->len, DMA_TO_DEVICE);
453 else
454 dma_unmap_page(chan2parent(&dc->chan),
455 dmaaddr, desc->len, DMA_TO_DEVICE);
456 }
457 }
458
459 /*
460 * The API requires that no submissions are done from a
461 * callback, so we don't need to drop the lock here
462 */
463 if (callback)
464 callback(param);
465 dma_run_dependencies(txd);
466}
467
468static void txx9dmac_dequeue(struct txx9dmac_chan *dc, struct list_head *list)
469{
470 struct txx9dmac_dev *ddev = dc->ddev;
471 struct txx9dmac_desc *desc;
472 struct txx9dmac_desc *prev = NULL;
473
474 BUG_ON(!list_empty(list));
475 do {
476 desc = txx9dmac_first_queued(dc);
477 if (prev) {
478 desc_write_CHAR(dc, prev, desc->txd.phys);
479 dma_sync_single_for_device(chan2parent(&dc->chan),
480 prev->txd.phys, ddev->descsize,
481 DMA_TO_DEVICE);
482 }
483 prev = txx9dmac_last_child(desc);
484 list_move_tail(&desc->desc_node, list);
485 /* Make chain-completion interrupt happen */
486 if ((desc->txd.flags & DMA_PREP_INTERRUPT) &&
487 !txx9dmac_chan_INTENT(dc))
488 break;
489 } while (!list_empty(&dc->queue));
490}
491
492static void txx9dmac_complete_all(struct txx9dmac_chan *dc)
493{
494 struct txx9dmac_desc *desc, *_desc;
495 LIST_HEAD(list);
496
497 /*
498 * Submit queued descriptors ASAP, i.e. before we go through
499 * the completed ones.
500 */
501 list_splice_init(&dc->active_list, &list);
502 if (!list_empty(&dc->queue)) {
503 txx9dmac_dequeue(dc, &dc->active_list);
504 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
505 }
506
507 list_for_each_entry_safe(desc, _desc, &list, desc_node)
508 txx9dmac_descriptor_complete(dc, desc);
509}
510
511static void txx9dmac_dump_desc(struct txx9dmac_chan *dc,
512 struct txx9dmac_hwdesc *desc)
513{
514 if (is_dmac64(dc)) {
515#ifdef TXX9_DMA_USE_SIMPLE_CHAIN
516 dev_crit(chan2dev(&dc->chan),
517 " desc: ch%#llx s%#llx d%#llx c%#x\n",
518 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR);
519#else
520 dev_crit(chan2dev(&dc->chan),
521 " desc: ch%#llx s%#llx d%#llx c%#x"
522 " si%#x di%#x cc%#x cs%#x\n",
523 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR,
524 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR);
525#endif
526 } else {
527 struct txx9dmac_hwdesc32 *d = (struct txx9dmac_hwdesc32 *)desc;
528#ifdef TXX9_DMA_USE_SIMPLE_CHAIN
529 dev_crit(chan2dev(&dc->chan),
530 " desc: ch%#x s%#x d%#x c%#x\n",
531 d->CHAR, d->SAR, d->DAR, d->CNTR);
532#else
533 dev_crit(chan2dev(&dc->chan),
534 " desc: ch%#x s%#x d%#x c%#x"
535 " si%#x di%#x cc%#x cs%#x\n",
536 d->CHAR, d->SAR, d->DAR, d->CNTR,
537 d->SAIR, d->DAIR, d->CCR, d->CSR);
538#endif
539 }
540}
541
542static void txx9dmac_handle_error(struct txx9dmac_chan *dc, u32 csr)
543{
544 struct txx9dmac_desc *bad_desc;
545 struct txx9dmac_desc *child;
546 u32 errors;
547
548 /*
549 * The descriptor currently at the head of the active list is
550 * borked. Since we don't have any way to report errors, we'll
551 * just have to scream loudly and try to carry on.
552 */
553 dev_crit(chan2dev(&dc->chan), "Abnormal Chain Completion\n");
554 txx9dmac_dump_regs(dc);
555
556 bad_desc = txx9dmac_first_active(dc);
557 list_del_init(&bad_desc->desc_node);
558
559 /* Clear all error flags and try to restart the controller */
560 errors = csr & (TXX9_DMA_CSR_ABCHC |
561 TXX9_DMA_CSR_CFERR | TXX9_DMA_CSR_CHERR |
562 TXX9_DMA_CSR_DESERR | TXX9_DMA_CSR_SORERR);
563 channel_writel(dc, CSR, errors);
564
565 if (list_empty(&dc->active_list) && !list_empty(&dc->queue))
566 txx9dmac_dequeue(dc, &dc->active_list);
567 if (!list_empty(&dc->active_list))
568 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
569
570 dev_crit(chan2dev(&dc->chan),
571 "Bad descriptor submitted for DMA! (cookie: %d)\n",
572 bad_desc->txd.cookie);
573 txx9dmac_dump_desc(dc, &bad_desc->hwdesc);
574 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
575 txx9dmac_dump_desc(dc, &child->hwdesc);
576 /* Pretend the descriptor completed successfully */
577 txx9dmac_descriptor_complete(dc, bad_desc);
578}
579
580static void txx9dmac_scan_descriptors(struct txx9dmac_chan *dc)
581{
582 dma_addr_t chain;
583 struct txx9dmac_desc *desc, *_desc;
584 struct txx9dmac_desc *child;
585 u32 csr;
586
587 if (is_dmac64(dc)) {
588 chain = channel64_read_CHAR(dc);
589 csr = channel64_readl(dc, CSR);
590 channel64_writel(dc, CSR, csr);
591 } else {
592 chain = channel32_readl(dc, CHAR);
593 csr = channel32_readl(dc, CSR);
594 channel32_writel(dc, CSR, csr);
595 }
596 /* For dynamic chain, we should look at XFACT instead of NCHNC */
597 if (!(csr & (TXX9_DMA_CSR_XFACT | TXX9_DMA_CSR_ABCHC))) {
598 /* Everything we've submitted is done */
599 txx9dmac_complete_all(dc);
600 return;
601 }
602 if (!(csr & TXX9_DMA_CSR_CHNEN))
603 chain = 0; /* last descriptor of this chain */
604
605 dev_vdbg(chan2dev(&dc->chan), "scan_descriptors: char=%#llx\n",
606 (u64)chain);
607
608 list_for_each_entry_safe(desc, _desc, &dc->active_list, desc_node) {
609 if (desc_read_CHAR(dc, desc) == chain) {
610 /* This one is currently in progress */
611 if (csr & TXX9_DMA_CSR_ABCHC)
612 goto scan_done;
613 return;
614 }
615
616 list_for_each_entry(child, &desc->tx_list, desc_node)
617 if (desc_read_CHAR(dc, child) == chain) {
618 /* Currently in progress */
619 if (csr & TXX9_DMA_CSR_ABCHC)
620 goto scan_done;
621 return;
622 }
623
624 /*
625 * No descriptors so far seem to be in progress, i.e.
626 * this one must be done.
627 */
628 txx9dmac_descriptor_complete(dc, desc);
629 }
630scan_done:
631 if (csr & TXX9_DMA_CSR_ABCHC) {
632 txx9dmac_handle_error(dc, csr);
633 return;
634 }
635
636 dev_err(chan2dev(&dc->chan),
637 "BUG: All descriptors done, but channel not idle!\n");
638
639 /* Try to continue after resetting the channel... */
640 txx9dmac_reset_chan(dc);
641
642 if (!list_empty(&dc->queue)) {
643 txx9dmac_dequeue(dc, &dc->active_list);
644 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
645 }
646}
647
648static void txx9dmac_chan_tasklet(unsigned long data)
649{
650 int irq;
651 u32 csr;
652 struct txx9dmac_chan *dc;
653
654 dc = (struct txx9dmac_chan *)data;
655 csr = channel_readl(dc, CSR);
656 dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n", csr);
657
658 spin_lock(&dc->lock);
659 if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
660 TXX9_DMA_CSR_NTRNFC))
661 txx9dmac_scan_descriptors(dc);
662 spin_unlock(&dc->lock);
663 irq = dc->irq;
664
665 enable_irq(irq);
666}
667
668static irqreturn_t txx9dmac_chan_interrupt(int irq, void *dev_id)
669{
670 struct txx9dmac_chan *dc = dev_id;
671
672 dev_vdbg(chan2dev(&dc->chan), "interrupt: status=%#x\n",
673 channel_readl(dc, CSR));
674
675 tasklet_schedule(&dc->tasklet);
676 /*
677 * Just disable the interrupts. We'll turn them back on in the
678 * softirq handler.
679 */
680 disable_irq_nosync(irq);
681
682 return IRQ_HANDLED;
683}
684
685static void txx9dmac_tasklet(unsigned long data)
686{
687 int irq;
688 u32 csr;
689 struct txx9dmac_chan *dc;
690
691 struct txx9dmac_dev *ddev = (struct txx9dmac_dev *)data;
692 u32 mcr;
693 int i;
694
695 mcr = dma_readl(ddev, MCR);
696 dev_vdbg(ddev->chan[0]->dma.dev, "tasklet: mcr=%x\n", mcr);
697 for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
698 if ((mcr >> (24 + i)) & 0x11) {
699 dc = ddev->chan[i];
700 csr = channel_readl(dc, CSR);
701 dev_vdbg(chan2dev(&dc->chan), "tasklet: status=%x\n",
702 csr);
703 spin_lock(&dc->lock);
704 if (csr & (TXX9_DMA_CSR_ABCHC | TXX9_DMA_CSR_NCHNC |
705 TXX9_DMA_CSR_NTRNFC))
706 txx9dmac_scan_descriptors(dc);
707 spin_unlock(&dc->lock);
708 }
709 }
710 irq = ddev->irq;
711
712 enable_irq(irq);
713}
714
715static irqreturn_t txx9dmac_interrupt(int irq, void *dev_id)
716{
717 struct txx9dmac_dev *ddev = dev_id;
718
719 dev_vdbg(ddev->chan[0]->dma.dev, "interrupt: status=%#x\n",
720 dma_readl(ddev, MCR));
721
722 tasklet_schedule(&ddev->tasklet);
723 /*
724 * Just disable the interrupts. We'll turn them back on in the
725 * softirq handler.
726 */
727 disable_irq_nosync(irq);
728
729 return IRQ_HANDLED;
730}
731
732/*----------------------------------------------------------------------*/
733
734static dma_cookie_t txx9dmac_tx_submit(struct dma_async_tx_descriptor *tx)
735{
736 struct txx9dmac_desc *desc = txd_to_txx9dmac_desc(tx);
737 struct txx9dmac_chan *dc = to_txx9dmac_chan(tx->chan);
738 dma_cookie_t cookie;
739
740 spin_lock_bh(&dc->lock);
741 cookie = txx9dmac_assign_cookie(dc, desc);
742
743 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u %p\n",
744 desc->txd.cookie, desc);
745
746 list_add_tail(&desc->desc_node, &dc->queue);
747 spin_unlock_bh(&dc->lock);
748
749 return cookie;
750}
751
752static struct dma_async_tx_descriptor *
753txx9dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
754 size_t len, unsigned long flags)
755{
756 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
757 struct txx9dmac_dev *ddev = dc->ddev;
758 struct txx9dmac_desc *desc;
759 struct txx9dmac_desc *first;
760 struct txx9dmac_desc *prev;
761 size_t xfer_count;
762 size_t offset;
763
764 dev_vdbg(chan2dev(chan), "prep_dma_memcpy d%#llx s%#llx l%#zx f%#lx\n",
765 (u64)dest, (u64)src, len, flags);
766
767 if (unlikely(!len)) {
768 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
769 return NULL;
770 }
771
772 prev = first = NULL;
773
774 for (offset = 0; offset < len; offset += xfer_count) {
775 xfer_count = min_t(size_t, len - offset, TXX9_DMA_MAX_COUNT);
776 /*
777 * Workaround for ERT-TX49H2-033, ERT-TX49H3-020,
778 * ERT-TX49H4-016 (slightly conservative)
779 */
780 if (__is_dmac64(ddev)) {
781 if (xfer_count > 0x100 &&
782 (xfer_count & 0xff) >= 0xfa &&
783 (xfer_count & 0xff) <= 0xff)
784 xfer_count -= 0x20;
785 } else {
786 if (xfer_count > 0x80 &&
787 (xfer_count & 0x7f) >= 0x7e &&
788 (xfer_count & 0x7f) <= 0x7f)
789 xfer_count -= 0x20;
790 }
791
792 desc = txx9dmac_desc_get(dc);
793 if (!desc) {
794 txx9dmac_desc_put(dc, first);
795 return NULL;
796 }
797
798 if (__is_dmac64(ddev)) {
799 desc->hwdesc.SAR = src + offset;
800 desc->hwdesc.DAR = dest + offset;
801 desc->hwdesc.CNTR = xfer_count;
802 txx9dmac_desc_set_nosimple(ddev, desc, 8, 8,
803 dc->ccr | TXX9_DMA_CCR_XFACT);
804 } else {
805 desc->hwdesc32.SAR = src + offset;
806 desc->hwdesc32.DAR = dest + offset;
807 desc->hwdesc32.CNTR = xfer_count;
808 txx9dmac_desc_set_nosimple(ddev, desc, 4, 4,
809 dc->ccr | TXX9_DMA_CCR_XFACT);
810 }
811
812 /*
813 * The descriptors on tx_list are not reachable from
814 * the dc->queue list or dc->active_list after a
815 * submit. If we put all descriptors on active_list,
816 * calling of callback on the completion will be more
817 * complex.
818 */
819 if (!first) {
820 first = desc;
821 } else {
822 desc_write_CHAR(dc, prev, desc->txd.phys);
823 dma_sync_single_for_device(chan2parent(&dc->chan),
824 prev->txd.phys, ddev->descsize,
825 DMA_TO_DEVICE);
826 list_add_tail(&desc->desc_node, &first->tx_list);
827 }
828 prev = desc;
829 }
830
831 /* Trigger interrupt after last block */
832 if (flags & DMA_PREP_INTERRUPT)
833 txx9dmac_desc_set_INTENT(ddev, prev);
834
835 desc_write_CHAR(dc, prev, 0);
836 dma_sync_single_for_device(chan2parent(&dc->chan),
837 prev->txd.phys, ddev->descsize,
838 DMA_TO_DEVICE);
839
840 first->txd.flags = flags;
841 first->len = len;
842
843 return &first->txd;
844}
845
846static struct dma_async_tx_descriptor *
847txx9dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
848 unsigned int sg_len, enum dma_data_direction direction,
849 unsigned long flags)
850{
851 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
852 struct txx9dmac_dev *ddev = dc->ddev;
853 struct txx9dmac_slave *ds = chan->private;
854 struct txx9dmac_desc *prev;
855 struct txx9dmac_desc *first;
856 unsigned int i;
857 struct scatterlist *sg;
858
859 dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
860
861 BUG_ON(!ds || !ds->reg_width);
862 if (ds->tx_reg)
863 BUG_ON(direction != DMA_TO_DEVICE);
864 else
865 BUG_ON(direction != DMA_FROM_DEVICE);
866 if (unlikely(!sg_len))
867 return NULL;
868
869 prev = first = NULL;
870
871 for_each_sg(sgl, sg, sg_len, i) {
872 struct txx9dmac_desc *desc;
873 dma_addr_t mem;
874 u32 sai, dai;
875
876 desc = txx9dmac_desc_get(dc);
877 if (!desc) {
878 txx9dmac_desc_put(dc, first);
879 return NULL;
880 }
881
882 mem = sg_dma_address(sg);
883
884 if (__is_dmac64(ddev)) {
885 if (direction == DMA_TO_DEVICE) {
886 desc->hwdesc.SAR = mem;
887 desc->hwdesc.DAR = ds->tx_reg;
888 } else {
889 desc->hwdesc.SAR = ds->rx_reg;
890 desc->hwdesc.DAR = mem;
891 }
892 desc->hwdesc.CNTR = sg_dma_len(sg);
893 } else {
894 if (direction == DMA_TO_DEVICE) {
895 desc->hwdesc32.SAR = mem;
896 desc->hwdesc32.DAR = ds->tx_reg;
897 } else {
898 desc->hwdesc32.SAR = ds->rx_reg;
899 desc->hwdesc32.DAR = mem;
900 }
901 desc->hwdesc32.CNTR = sg_dma_len(sg);
902 }
903 if (direction == DMA_TO_DEVICE) {
904 sai = ds->reg_width;
905 dai = 0;
906 } else {
907 sai = 0;
908 dai = ds->reg_width;
909 }
910 txx9dmac_desc_set_nosimple(ddev, desc, sai, dai,
911 dc->ccr | TXX9_DMA_CCR_XFACT);
912
913 if (!first) {
914 first = desc;
915 } else {
916 desc_write_CHAR(dc, prev, desc->txd.phys);
917 dma_sync_single_for_device(chan2parent(&dc->chan),
918 prev->txd.phys,
919 ddev->descsize,
920 DMA_TO_DEVICE);
921 list_add_tail(&desc->desc_node, &first->tx_list);
922 }
923 prev = desc;
924 }
925
926 /* Trigger interrupt after last block */
927 if (flags & DMA_PREP_INTERRUPT)
928 txx9dmac_desc_set_INTENT(ddev, prev);
929
930 desc_write_CHAR(dc, prev, 0);
931 dma_sync_single_for_device(chan2parent(&dc->chan),
932 prev->txd.phys, ddev->descsize,
933 DMA_TO_DEVICE);
934
935 first->txd.flags = flags;
936 first->len = 0;
937
938 return &first->txd;
939}
940
941static int txx9dmac_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
942 unsigned long arg)
943{
944 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
945 struct txx9dmac_desc *desc, *_desc;
946 LIST_HEAD(list);
947
948 /* Only supports DMA_TERMINATE_ALL */
949 if (cmd != DMA_TERMINATE_ALL)
950 return -EINVAL;
951
952 dev_vdbg(chan2dev(chan), "terminate_all\n");
953 spin_lock_bh(&dc->lock);
954
955 txx9dmac_reset_chan(dc);
956
957 /* active_list entries will end up before queued entries */
958 list_splice_init(&dc->queue, &list);
959 list_splice_init(&dc->active_list, &list);
960
961 spin_unlock_bh(&dc->lock);
962
963 /* Flush all pending and queued descriptors */
964 list_for_each_entry_safe(desc, _desc, &list, desc_node)
965 txx9dmac_descriptor_complete(dc, desc);
966
967 return 0;
968}
969
970static enum dma_status
971txx9dmac_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
972 struct dma_tx_state *txstate)
973{
974 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
975 dma_cookie_t last_used;
976 dma_cookie_t last_complete;
977 int ret;
978
979 last_complete = dc->completed;
980 last_used = chan->cookie;
981
982 ret = dma_async_is_complete(cookie, last_complete, last_used);
983 if (ret != DMA_SUCCESS) {
984 spin_lock_bh(&dc->lock);
985 txx9dmac_scan_descriptors(dc);
986 spin_unlock_bh(&dc->lock);
987
988 last_complete = dc->completed;
989 last_used = chan->cookie;
990
991 ret = dma_async_is_complete(cookie, last_complete, last_used);
992 }
993
994 dma_set_tx_state(txstate, last_complete, last_used, 0);
995
996 return ret;
997}
998
999static void txx9dmac_chain_dynamic(struct txx9dmac_chan *dc,
1000 struct txx9dmac_desc *prev)
1001{
1002 struct txx9dmac_dev *ddev = dc->ddev;
1003 struct txx9dmac_desc *desc;
1004 LIST_HEAD(list);
1005
1006 prev = txx9dmac_last_child(prev);
1007 txx9dmac_dequeue(dc, &list);
1008 desc = list_entry(list.next, struct txx9dmac_desc, desc_node);
1009 desc_write_CHAR(dc, prev, desc->txd.phys);
1010 dma_sync_single_for_device(chan2parent(&dc->chan),
1011 prev->txd.phys, ddev->descsize,
1012 DMA_TO_DEVICE);
1013 mmiowb();
1014 if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) &&
1015 channel_read_CHAR(dc) == prev->txd.phys)
1016 /* Restart chain DMA */
1017 channel_write_CHAR(dc, desc->txd.phys);
1018 list_splice_tail(&list, &dc->active_list);
1019}
1020
1021static void txx9dmac_issue_pending(struct dma_chan *chan)
1022{
1023 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1024
1025 spin_lock_bh(&dc->lock);
1026
1027 if (!list_empty(&dc->active_list))
1028 txx9dmac_scan_descriptors(dc);
1029 if (!list_empty(&dc->queue)) {
1030 if (list_empty(&dc->active_list)) {
1031 txx9dmac_dequeue(dc, &dc->active_list);
1032 txx9dmac_dostart(dc, txx9dmac_first_active(dc));
1033 } else if (txx9_dma_have_SMPCHN()) {
1034 struct txx9dmac_desc *prev = txx9dmac_last_active(dc);
1035
1036 if (!(prev->txd.flags & DMA_PREP_INTERRUPT) ||
1037 txx9dmac_chan_INTENT(dc))
1038 txx9dmac_chain_dynamic(dc, prev);
1039 }
1040 }
1041
1042 spin_unlock_bh(&dc->lock);
1043}
1044
1045static int txx9dmac_alloc_chan_resources(struct dma_chan *chan)
1046{
1047 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1048 struct txx9dmac_slave *ds = chan->private;
1049 struct txx9dmac_desc *desc;
1050 int i;
1051
1052 dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
1053
1054 /* ASSERT: channel is idle */
1055 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) {
1056 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1057 return -EIO;
1058 }
1059
1060 dc->completed = chan->cookie = 1;
1061
1062 dc->ccr = TXX9_DMA_CCR_IMMCHN | TXX9_DMA_CCR_INTENE | CCR_LE;
1063 txx9dmac_chan_set_SMPCHN(dc);
1064 if (!txx9_dma_have_SMPCHN() || (dc->ccr & TXX9_DMA_CCR_SMPCHN))
1065 dc->ccr |= TXX9_DMA_CCR_INTENC;
1066 if (chan->device->device_prep_dma_memcpy) {
1067 if (ds)
1068 return -EINVAL;
1069 dc->ccr |= TXX9_DMA_CCR_XFSZ_X8;
1070 } else {
1071 if (!ds ||
1072 (ds->tx_reg && ds->rx_reg) || (!ds->tx_reg && !ds->rx_reg))
1073 return -EINVAL;
1074 dc->ccr |= TXX9_DMA_CCR_EXTRQ |
1075 TXX9_DMA_CCR_XFSZ(__ffs(ds->reg_width));
1076 txx9dmac_chan_set_INTENT(dc);
1077 }
1078
1079 spin_lock_bh(&dc->lock);
1080 i = dc->descs_allocated;
1081 while (dc->descs_allocated < TXX9_DMA_INITIAL_DESC_COUNT) {
1082 spin_unlock_bh(&dc->lock);
1083
1084 desc = txx9dmac_desc_alloc(dc, GFP_KERNEL);
1085 if (!desc) {
1086 dev_info(chan2dev(chan),
1087 "only allocated %d descriptors\n", i);
1088 spin_lock_bh(&dc->lock);
1089 break;
1090 }
1091 txx9dmac_desc_put(dc, desc);
1092
1093 spin_lock_bh(&dc->lock);
1094 i = ++dc->descs_allocated;
1095 }
1096 spin_unlock_bh(&dc->lock);
1097
1098 dev_dbg(chan2dev(chan),
1099 "alloc_chan_resources allocated %d descriptors\n", i);
1100
1101 return i;
1102}
1103
1104static void txx9dmac_free_chan_resources(struct dma_chan *chan)
1105{
1106 struct txx9dmac_chan *dc = to_txx9dmac_chan(chan);
1107 struct txx9dmac_dev *ddev = dc->ddev;
1108 struct txx9dmac_desc *desc, *_desc;
1109 LIST_HEAD(list);
1110
1111 dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
1112 dc->descs_allocated);
1113
1114 /* ASSERT: channel is idle */
1115 BUG_ON(!list_empty(&dc->active_list));
1116 BUG_ON(!list_empty(&dc->queue));
1117 BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT);
1118
1119 spin_lock_bh(&dc->lock);
1120 list_splice_init(&dc->free_list, &list);
1121 dc->descs_allocated = 0;
1122 spin_unlock_bh(&dc->lock);
1123
1124 list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1125 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1126 dma_unmap_single(chan2parent(chan), desc->txd.phys,
1127 ddev->descsize, DMA_TO_DEVICE);
1128 kfree(desc);
1129 }
1130
1131 dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
1132}
1133
1134/*----------------------------------------------------------------------*/
1135
1136static void txx9dmac_off(struct txx9dmac_dev *ddev)
1137{
1138 dma_writel(ddev, MCR, 0);
1139 mmiowb();
1140}
1141
1142static int __init txx9dmac_chan_probe(struct platform_device *pdev)
1143{
1144 struct txx9dmac_chan_platform_data *cpdata = pdev->dev.platform_data;
1145 struct platform_device *dmac_dev = cpdata->dmac_dev;
1146 struct txx9dmac_platform_data *pdata = dmac_dev->dev.platform_data;
1147 struct txx9dmac_chan *dc;
1148 int err;
1149 int ch = pdev->id % TXX9_DMA_MAX_NR_CHANNELS;
1150 int irq;
1151
1152 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1153 if (!dc)
1154 return -ENOMEM;
1155
1156 dc->dma.dev = &pdev->dev;
1157 dc->dma.device_alloc_chan_resources = txx9dmac_alloc_chan_resources;
1158 dc->dma.device_free_chan_resources = txx9dmac_free_chan_resources;
1159 dc->dma.device_control = txx9dmac_control;
1160 dc->dma.device_tx_status = txx9dmac_tx_status;
1161 dc->dma.device_issue_pending = txx9dmac_issue_pending;
1162 if (pdata && pdata->memcpy_chan == ch) {
1163 dc->dma.device_prep_dma_memcpy = txx9dmac_prep_dma_memcpy;
1164 dma_cap_set(DMA_MEMCPY, dc->dma.cap_mask);
1165 } else {
1166 dc->dma.device_prep_slave_sg = txx9dmac_prep_slave_sg;
1167 dma_cap_set(DMA_SLAVE, dc->dma.cap_mask);
1168 dma_cap_set(DMA_PRIVATE, dc->dma.cap_mask);
1169 }
1170
1171 INIT_LIST_HEAD(&dc->dma.channels);
1172 dc->ddev = platform_get_drvdata(dmac_dev);
1173 if (dc->ddev->irq < 0) {
1174 irq = platform_get_irq(pdev, 0);
1175 if (irq < 0)
1176 return irq;
1177 tasklet_init(&dc->tasklet, txx9dmac_chan_tasklet,
1178 (unsigned long)dc);
1179 dc->irq = irq;
1180 err = devm_request_irq(&pdev->dev, dc->irq,
1181 txx9dmac_chan_interrupt, 0, dev_name(&pdev->dev), dc);
1182 if (err)
1183 return err;
1184 } else
1185 dc->irq = -1;
1186 dc->ddev->chan[ch] = dc;
1187 dc->chan.device = &dc->dma;
1188 list_add_tail(&dc->chan.device_node, &dc->chan.device->channels);
1189 dc->chan.cookie = dc->completed = 1;
1190
1191 if (is_dmac64(dc))
1192 dc->ch_regs = &__txx9dmac_regs(dc->ddev)->CHAN[ch];
1193 else
1194 dc->ch_regs = &__txx9dmac_regs32(dc->ddev)->CHAN[ch];
1195 spin_lock_init(&dc->lock);
1196
1197 INIT_LIST_HEAD(&dc->active_list);
1198 INIT_LIST_HEAD(&dc->queue);
1199 INIT_LIST_HEAD(&dc->free_list);
1200
1201 txx9dmac_reset_chan(dc);
1202
1203 platform_set_drvdata(pdev, dc);
1204
1205 err = dma_async_device_register(&dc->dma);
1206 if (err)
1207 return err;
1208 dev_dbg(&pdev->dev, "TXx9 DMA Channel (dma%d%s%s)\n",
1209 dc->dma.dev_id,
1210 dma_has_cap(DMA_MEMCPY, dc->dma.cap_mask) ? " memcpy" : "",
1211 dma_has_cap(DMA_SLAVE, dc->dma.cap_mask) ? " slave" : "");
1212
1213 return 0;
1214}
1215
1216static int __exit txx9dmac_chan_remove(struct platform_device *pdev)
1217{
1218 struct txx9dmac_chan *dc = platform_get_drvdata(pdev);
1219
1220 dma_async_device_unregister(&dc->dma);
1221 if (dc->irq >= 0)
1222 tasklet_kill(&dc->tasklet);
1223 dc->ddev->chan[pdev->id % TXX9_DMA_MAX_NR_CHANNELS] = NULL;
1224 return 0;
1225}
1226
1227static int __init txx9dmac_probe(struct platform_device *pdev)
1228{
1229 struct txx9dmac_platform_data *pdata = pdev->dev.platform_data;
1230 struct resource *io;
1231 struct txx9dmac_dev *ddev;
1232 u32 mcr;
1233 int err;
1234
1235 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1236 if (!io)
1237 return -EINVAL;
1238
1239 ddev = devm_kzalloc(&pdev->dev, sizeof(*ddev), GFP_KERNEL);
1240 if (!ddev)
1241 return -ENOMEM;
1242
1243 if (!devm_request_mem_region(&pdev->dev, io->start, resource_size(io),
1244 dev_name(&pdev->dev)))
1245 return -EBUSY;
1246
1247 ddev->regs = devm_ioremap(&pdev->dev, io->start, resource_size(io));
1248 if (!ddev->regs)
1249 return -ENOMEM;
1250 ddev->have_64bit_regs = pdata->have_64bit_regs;
1251 if (__is_dmac64(ddev))
1252 ddev->descsize = sizeof(struct txx9dmac_hwdesc);
1253 else
1254 ddev->descsize = sizeof(struct txx9dmac_hwdesc32);
1255
1256 /* force dma off, just in case */
1257 txx9dmac_off(ddev);
1258
1259 ddev->irq = platform_get_irq(pdev, 0);
1260 if (ddev->irq >= 0) {
1261 tasklet_init(&ddev->tasklet, txx9dmac_tasklet,
1262 (unsigned long)ddev);
1263 err = devm_request_irq(&pdev->dev, ddev->irq,
1264 txx9dmac_interrupt, 0, dev_name(&pdev->dev), ddev);
1265 if (err)
1266 return err;
1267 }
1268
1269 mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
1270 if (pdata && pdata->memcpy_chan >= 0)
1271 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
1272 dma_writel(ddev, MCR, mcr);
1273
1274 platform_set_drvdata(pdev, ddev);
1275 return 0;
1276}
1277
1278static int __exit txx9dmac_remove(struct platform_device *pdev)
1279{
1280 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1281
1282 txx9dmac_off(ddev);
1283 if (ddev->irq >= 0)
1284 tasklet_kill(&ddev->tasklet);
1285 return 0;
1286}
1287
1288static void txx9dmac_shutdown(struct platform_device *pdev)
1289{
1290 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1291
1292 txx9dmac_off(ddev);
1293}
1294
1295static int txx9dmac_suspend_noirq(struct device *dev)
1296{
1297 struct platform_device *pdev = to_platform_device(dev);
1298 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1299
1300 txx9dmac_off(ddev);
1301 return 0;
1302}
1303
1304static int txx9dmac_resume_noirq(struct device *dev)
1305{
1306 struct platform_device *pdev = to_platform_device(dev);
1307 struct txx9dmac_dev *ddev = platform_get_drvdata(pdev);
1308 struct txx9dmac_platform_data *pdata = pdev->dev.platform_data;
1309 u32 mcr;
1310
1311 mcr = TXX9_DMA_MCR_MSTEN | MCR_LE;
1312 if (pdata && pdata->memcpy_chan >= 0)
1313 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan);
1314 dma_writel(ddev, MCR, mcr);
1315 return 0;
1316
1317}
1318
1319static const struct dev_pm_ops txx9dmac_dev_pm_ops = {
1320 .suspend_noirq = txx9dmac_suspend_noirq,
1321 .resume_noirq = txx9dmac_resume_noirq,
1322};
1323
1324static struct platform_driver txx9dmac_chan_driver = {
1325 .remove = __exit_p(txx9dmac_chan_remove),
1326 .driver = {
1327 .name = "txx9dmac-chan",
1328 },
1329};
1330
1331static struct platform_driver txx9dmac_driver = {
1332 .remove = __exit_p(txx9dmac_remove),
1333 .shutdown = txx9dmac_shutdown,
1334 .driver = {
1335 .name = "txx9dmac",
1336 .pm = &txx9dmac_dev_pm_ops,
1337 },
1338};
1339
1340static int __init txx9dmac_init(void)
1341{
1342 int rc;
1343
1344 rc = platform_driver_probe(&txx9dmac_driver, txx9dmac_probe);
1345 if (!rc) {
1346 rc = platform_driver_probe(&txx9dmac_chan_driver,
1347 txx9dmac_chan_probe);
1348 if (rc)
1349 platform_driver_unregister(&txx9dmac_driver);
1350 }
1351 return rc;
1352}
1353module_init(txx9dmac_init);
1354
1355static void __exit txx9dmac_exit(void)
1356{
1357 platform_driver_unregister(&txx9dmac_chan_driver);
1358 platform_driver_unregister(&txx9dmac_driver);
1359}
1360module_exit(txx9dmac_exit);
1361
1362MODULE_LICENSE("GPL");
1363MODULE_DESCRIPTION("TXx9 DMA Controller driver");
1364MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
1365MODULE_ALIAS("platform:txx9dmac");
1366MODULE_ALIAS("platform:txx9dmac-chan");