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1/**
2 * OMAP and TWL PMIC specific intializations.
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated.
5 * Thara Gopinath
6 * Copyright (C) 2009 Texas Instruments Incorporated.
7 * Nishanth Menon
8 * Copyright (C) 2009 Nokia Corporation
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/i2c/twl.h>
20
21#include "soc.h"
22#include "voltage.h"
23
24#include "pm.h"
25
26#define OMAP3_SRI2C_SLAVE_ADDR 0x12
27#define OMAP3_VDD_MPU_SR_CONTROL_REG 0x00
28#define OMAP3_VDD_CORE_SR_CONTROL_REG 0x01
29#define OMAP3_VP_CONFIG_ERROROFFSET 0x00
30#define OMAP3_VP_VSTEPMIN_VSTEPMIN 0x1
31#define OMAP3_VP_VSTEPMAX_VSTEPMAX 0x04
32#define OMAP3_VP_VLIMITTO_TIMEOUT_US 200
33
34#define OMAP4_SRI2C_SLAVE_ADDR 0x12
35#define OMAP4_VDD_MPU_SR_VOLT_REG 0x55
36#define OMAP4_VDD_MPU_SR_CMD_REG 0x56
37#define OMAP4_VDD_IVA_SR_VOLT_REG 0x5B
38#define OMAP4_VDD_IVA_SR_CMD_REG 0x5C
39#define OMAP4_VDD_CORE_SR_VOLT_REG 0x61
40#define OMAP4_VDD_CORE_SR_CMD_REG 0x62
41
42#define OMAP4_VP_CONFIG_ERROROFFSET 0x00
43#define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01
44#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04
45#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200
46
47static bool is_offset_valid;
48static u8 smps_offset;
49/*
50 * Flag to ensure Smartreflex bit in TWL
51 * being cleared in board file is not overwritten.
52 */
53static bool __initdata twl_sr_enable_autoinit;
54
55#define TWL4030_DCDC_GLOBAL_CFG 0x06
56#define REG_SMPS_OFFSET 0xE0
57#define SMARTREFLEX_ENABLE BIT(3)
58
59static unsigned long twl4030_vsel_to_uv(const u8 vsel)
60{
61 return (((vsel * 125) + 6000)) * 100;
62}
63
64static u8 twl4030_uv_to_vsel(unsigned long uv)
65{
66 return DIV_ROUND_UP(uv - 600000, 12500);
67}
68
69static unsigned long twl6030_vsel_to_uv(const u8 vsel)
70{
71 /*
72 * In TWL6030 depending on the value of SMPS_OFFSET
73 * efuse register the voltage range supported in
74 * standard mode can be either between 0.6V - 1.3V or
75 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
76 * is programmed to all 0's where as starting from
77 * TWL6030 ES1.1 the efuse is programmed to 1
78 */
79 if (!is_offset_valid) {
80 twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
81 REG_SMPS_OFFSET);
82 is_offset_valid = true;
83 }
84
85 if (!vsel)
86 return 0;
87 /*
88 * There is no specific formula for voltage to vsel
89 * conversion above 1.3V. There are special hardcoded
90 * values for voltages above 1.3V. Currently we are
91 * hardcoding only for 1.35 V which is used for 1GH OPP for
92 * OMAP4430.
93 */
94 if (vsel == 0x3A)
95 return 1350000;
96
97 if (smps_offset & 0x8)
98 return ((((vsel - 1) * 1266) + 70900)) * 10;
99 else
100 return ((((vsel - 1) * 1266) + 60770)) * 10;
101}
102
103static u8 twl6030_uv_to_vsel(unsigned long uv)
104{
105 /*
106 * In TWL6030 depending on the value of SMPS_OFFSET
107 * efuse register the voltage range supported in
108 * standard mode can be either between 0.6V - 1.3V or
109 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
110 * is programmed to all 0's where as starting from
111 * TWL6030 ES1.1 the efuse is programmed to 1
112 */
113 if (!is_offset_valid) {
114 twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
115 REG_SMPS_OFFSET);
116 is_offset_valid = true;
117 }
118
119 if (!uv)
120 return 0x00;
121 /*
122 * There is no specific formula for voltage to vsel
123 * conversion above 1.3V. There are special hardcoded
124 * values for voltages above 1.3V. Currently we are
125 * hardcoding only for 1.35 V which is used for 1GH OPP for
126 * OMAP4430.
127 */
128 if (uv > twl6030_vsel_to_uv(0x39)) {
129 if (uv == 1350000)
130 return 0x3A;
131 pr_err("%s:OUT OF RANGE! non mapped vsel for %ld Vs max %ld\n",
132 __func__, uv, twl6030_vsel_to_uv(0x39));
133 return 0x3A;
134 }
135
136 if (smps_offset & 0x8)
137 return DIV_ROUND_UP(uv - 709000, 12660) + 1;
138 else
139 return DIV_ROUND_UP(uv - 607700, 12660) + 1;
140}
141
142static struct omap_voltdm_pmic omap3_mpu_pmic = {
143 .slew_rate = 4000,
144 .step_size = 12500,
145 .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET,
146 .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN,
147 .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX,
148 .vddmin = 600000,
149 .vddmax = 1450000,
150 .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
151 .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
152 .volt_reg_addr = OMAP3_VDD_MPU_SR_CONTROL_REG,
153 .i2c_high_speed = true,
154 .vsel_to_uv = twl4030_vsel_to_uv,
155 .uv_to_vsel = twl4030_uv_to_vsel,
156};
157
158static struct omap_voltdm_pmic omap3_core_pmic = {
159 .slew_rate = 4000,
160 .step_size = 12500,
161 .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET,
162 .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN,
163 .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX,
164 .vddmin = 600000,
165 .vddmax = 1450000,
166 .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
167 .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
168 .volt_reg_addr = OMAP3_VDD_CORE_SR_CONTROL_REG,
169 .i2c_high_speed = true,
170 .vsel_to_uv = twl4030_vsel_to_uv,
171 .uv_to_vsel = twl4030_uv_to_vsel,
172};
173
174static struct omap_voltdm_pmic omap4_mpu_pmic = {
175 .slew_rate = 4000,
176 .step_size = 12660,
177 .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
178 .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
179 .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
180 .vddmin = 0,
181 .vddmax = 2100000,
182 .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
183 .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
184 .volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG,
185 .cmd_reg_addr = OMAP4_VDD_MPU_SR_CMD_REG,
186 .i2c_high_speed = true,
187 .i2c_pad_load = 3,
188 .vsel_to_uv = twl6030_vsel_to_uv,
189 .uv_to_vsel = twl6030_uv_to_vsel,
190};
191
192static struct omap_voltdm_pmic omap4_iva_pmic = {
193 .slew_rate = 4000,
194 .step_size = 12660,
195 .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
196 .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
197 .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
198 .vddmin = 0,
199 .vddmax = 2100000,
200 .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
201 .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
202 .volt_reg_addr = OMAP4_VDD_IVA_SR_VOLT_REG,
203 .cmd_reg_addr = OMAP4_VDD_IVA_SR_CMD_REG,
204 .i2c_high_speed = true,
205 .i2c_pad_load = 3,
206 .vsel_to_uv = twl6030_vsel_to_uv,
207 .uv_to_vsel = twl6030_uv_to_vsel,
208};
209
210static struct omap_voltdm_pmic omap4_core_pmic = {
211 .slew_rate = 4000,
212 .step_size = 12660,
213 .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
214 .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
215 .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
216 .vddmin = 0,
217 .vddmax = 2100000,
218 .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
219 .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
220 .volt_reg_addr = OMAP4_VDD_CORE_SR_VOLT_REG,
221 .cmd_reg_addr = OMAP4_VDD_CORE_SR_CMD_REG,
222 .i2c_high_speed = true,
223 .i2c_pad_load = 3,
224 .vsel_to_uv = twl6030_vsel_to_uv,
225 .uv_to_vsel = twl6030_uv_to_vsel,
226};
227
228int __init omap4_twl_init(void)
229{
230 struct voltagedomain *voltdm;
231
232 if (!cpu_is_omap44xx())
233 return -ENODEV;
234
235 voltdm = voltdm_lookup("mpu");
236 omap_voltage_register_pmic(voltdm, &omap4_mpu_pmic);
237
238 voltdm = voltdm_lookup("iva");
239 omap_voltage_register_pmic(voltdm, &omap4_iva_pmic);
240
241 voltdm = voltdm_lookup("core");
242 omap_voltage_register_pmic(voltdm, &omap4_core_pmic);
243
244 return 0;
245}
246
247int __init omap3_twl_init(void)
248{
249 struct voltagedomain *voltdm;
250
251 if (!cpu_is_omap34xx())
252 return -ENODEV;
253
254 /*
255 * The smartreflex bit on twl4030 specifies if the setting of voltage
256 * is done over the I2C_SR path. Since this setting is independent of
257 * the actual usage of smartreflex AVS module, we enable TWL SR bit
258 * by default irrespective of whether smartreflex AVS module is enabled
259 * on the OMAP side or not. This is because without this bit enabled,
260 * the voltage scaling through vp forceupdate/bypass mechanism of
261 * voltage scaling will not function on TWL over I2C_SR.
262 */
263 if (!twl_sr_enable_autoinit)
264 omap3_twl_set_sr_bit(true);
265
266 voltdm = voltdm_lookup("mpu_iva");
267 omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
268
269 voltdm = voltdm_lookup("core");
270 omap_voltage_register_pmic(voltdm, &omap3_core_pmic);
271
272 return 0;
273}
274
275/**
276 * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
277 * @enable: enable SR mode in twl or not
278 *
279 * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
280 * voltage scaling through OMAP SR works. Else, the smartreflex bit
281 * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
282 * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
283 * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
284 * in those scenarios this bit is to be cleared (enable = false).
285 *
286 * Returns 0 on success, error is returned if I2C read/write fails.
287 */
288int __init omap3_twl_set_sr_bit(bool enable)
289{
290 u8 temp;
291 int ret;
292 if (twl_sr_enable_autoinit)
293 pr_warning("%s: unexpected multiple calls\n", __func__);
294
295 ret = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,
296 TWL4030_DCDC_GLOBAL_CFG);
297 if (ret)
298 goto err;
299
300 if (enable)
301 temp |= SMARTREFLEX_ENABLE;
302 else
303 temp &= ~SMARTREFLEX_ENABLE;
304
305 ret = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,
306 TWL4030_DCDC_GLOBAL_CFG);
307 if (!ret) {
308 twl_sr_enable_autoinit = true;
309 return 0;
310 }
311err:
312 pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);
313 return ret;
314}
1/**
2 * OMAP and TWL PMIC specific intializations.
3 *
4 * Copyright (C) 2010 Texas Instruments Incorporated.
5 * Thara Gopinath
6 * Copyright (C) 2009 Texas Instruments Incorporated.
7 * Nishanth Menon
8 * Copyright (C) 2009 Nokia Corporation
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/i2c/twl.h>
20
21#include "voltage.h"
22
23#include "pm.h"
24
25#define OMAP3_SRI2C_SLAVE_ADDR 0x12
26#define OMAP3_VDD_MPU_SR_CONTROL_REG 0x00
27#define OMAP3_VDD_CORE_SR_CONTROL_REG 0x01
28#define OMAP3_VP_CONFIG_ERROROFFSET 0x00
29#define OMAP3_VP_VSTEPMIN_VSTEPMIN 0x1
30#define OMAP3_VP_VSTEPMAX_VSTEPMAX 0x04
31#define OMAP3_VP_VLIMITTO_TIMEOUT_US 200
32
33#define OMAP3430_VP1_VLIMITTO_VDDMIN 0x14
34#define OMAP3430_VP1_VLIMITTO_VDDMAX 0x42
35#define OMAP3430_VP2_VLIMITTO_VDDMIN 0x18
36#define OMAP3430_VP2_VLIMITTO_VDDMAX 0x2c
37
38#define OMAP3630_VP1_VLIMITTO_VDDMIN 0x18
39#define OMAP3630_VP1_VLIMITTO_VDDMAX 0x3c
40#define OMAP3630_VP2_VLIMITTO_VDDMIN 0x18
41#define OMAP3630_VP2_VLIMITTO_VDDMAX 0x30
42
43#define OMAP4_SRI2C_SLAVE_ADDR 0x12
44#define OMAP4_VDD_MPU_SR_VOLT_REG 0x55
45#define OMAP4_VDD_IVA_SR_VOLT_REG 0x5B
46#define OMAP4_VDD_CORE_SR_VOLT_REG 0x61
47
48#define OMAP4_VP_CONFIG_ERROROFFSET 0x00
49#define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01
50#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04
51#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200
52
53#define OMAP4_VP_MPU_VLIMITTO_VDDMIN 0xA
54#define OMAP4_VP_MPU_VLIMITTO_VDDMAX 0x39
55#define OMAP4_VP_IVA_VLIMITTO_VDDMIN 0xA
56#define OMAP4_VP_IVA_VLIMITTO_VDDMAX 0x2D
57#define OMAP4_VP_CORE_VLIMITTO_VDDMIN 0xA
58#define OMAP4_VP_CORE_VLIMITTO_VDDMAX 0x28
59
60static bool is_offset_valid;
61static u8 smps_offset;
62/*
63 * Flag to ensure Smartreflex bit in TWL
64 * being cleared in board file is not overwritten.
65 */
66static bool __initdata twl_sr_enable_autoinit;
67
68#define TWL4030_DCDC_GLOBAL_CFG 0x06
69#define REG_SMPS_OFFSET 0xE0
70#define SMARTREFLEX_ENABLE BIT(3)
71
72static unsigned long twl4030_vsel_to_uv(const u8 vsel)
73{
74 return (((vsel * 125) + 6000)) * 100;
75}
76
77static u8 twl4030_uv_to_vsel(unsigned long uv)
78{
79 return DIV_ROUND_UP(uv - 600000, 12500);
80}
81
82static unsigned long twl6030_vsel_to_uv(const u8 vsel)
83{
84 /*
85 * In TWL6030 depending on the value of SMPS_OFFSET
86 * efuse register the voltage range supported in
87 * standard mode can be either between 0.6V - 1.3V or
88 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
89 * is programmed to all 0's where as starting from
90 * TWL6030 ES1.1 the efuse is programmed to 1
91 */
92 if (!is_offset_valid) {
93 twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
94 REG_SMPS_OFFSET);
95 is_offset_valid = true;
96 }
97
98 /*
99 * There is no specific formula for voltage to vsel
100 * conversion above 1.3V. There are special hardcoded
101 * values for voltages above 1.3V. Currently we are
102 * hardcoding only for 1.35 V which is used for 1GH OPP for
103 * OMAP4430.
104 */
105 if (vsel == 0x3A)
106 return 1350000;
107
108 if (smps_offset & 0x8)
109 return ((((vsel - 1) * 125) + 7000)) * 100;
110 else
111 return ((((vsel - 1) * 125) + 6000)) * 100;
112}
113
114static u8 twl6030_uv_to_vsel(unsigned long uv)
115{
116 /*
117 * In TWL6030 depending on the value of SMPS_OFFSET
118 * efuse register the voltage range supported in
119 * standard mode can be either between 0.6V - 1.3V or
120 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
121 * is programmed to all 0's where as starting from
122 * TWL6030 ES1.1 the efuse is programmed to 1
123 */
124 if (!is_offset_valid) {
125 twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
126 REG_SMPS_OFFSET);
127 is_offset_valid = true;
128 }
129
130 /*
131 * There is no specific formula for voltage to vsel
132 * conversion above 1.3V. There are special hardcoded
133 * values for voltages above 1.3V. Currently we are
134 * hardcoding only for 1.35 V which is used for 1GH OPP for
135 * OMAP4430.
136 */
137 if (uv == 1350000)
138 return 0x3A;
139
140 if (smps_offset & 0x8)
141 return DIV_ROUND_UP(uv - 700000, 12500) + 1;
142 else
143 return DIV_ROUND_UP(uv - 600000, 12500) + 1;
144}
145
146static struct omap_volt_pmic_info omap3_mpu_volt_info = {
147 .slew_rate = 4000,
148 .step_size = 12500,
149 .on_volt = 1200000,
150 .onlp_volt = 1000000,
151 .ret_volt = 975000,
152 .off_volt = 600000,
153 .volt_setup_time = 0xfff,
154 .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET,
155 .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN,
156 .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX,
157 .vp_vddmin = OMAP3430_VP1_VLIMITTO_VDDMIN,
158 .vp_vddmax = OMAP3430_VP1_VLIMITTO_VDDMAX,
159 .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
160 .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
161 .pmic_reg = OMAP3_VDD_MPU_SR_CONTROL_REG,
162 .vsel_to_uv = twl4030_vsel_to_uv,
163 .uv_to_vsel = twl4030_uv_to_vsel,
164};
165
166static struct omap_volt_pmic_info omap3_core_volt_info = {
167 .slew_rate = 4000,
168 .step_size = 12500,
169 .on_volt = 1200000,
170 .onlp_volt = 1000000,
171 .ret_volt = 975000,
172 .off_volt = 600000,
173 .volt_setup_time = 0xfff,
174 .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET,
175 .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN,
176 .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX,
177 .vp_vddmin = OMAP3430_VP2_VLIMITTO_VDDMIN,
178 .vp_vddmax = OMAP3430_VP2_VLIMITTO_VDDMAX,
179 .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
180 .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
181 .pmic_reg = OMAP3_VDD_CORE_SR_CONTROL_REG,
182 .vsel_to_uv = twl4030_vsel_to_uv,
183 .uv_to_vsel = twl4030_uv_to_vsel,
184};
185
186static struct omap_volt_pmic_info omap4_mpu_volt_info = {
187 .slew_rate = 4000,
188 .step_size = 12500,
189 .on_volt = 1350000,
190 .onlp_volt = 1350000,
191 .ret_volt = 837500,
192 .off_volt = 600000,
193 .volt_setup_time = 0,
194 .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
195 .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
196 .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
197 .vp_vddmin = OMAP4_VP_MPU_VLIMITTO_VDDMIN,
198 .vp_vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX,
199 .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
200 .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
201 .pmic_reg = OMAP4_VDD_MPU_SR_VOLT_REG,
202 .vsel_to_uv = twl6030_vsel_to_uv,
203 .uv_to_vsel = twl6030_uv_to_vsel,
204};
205
206static struct omap_volt_pmic_info omap4_iva_volt_info = {
207 .slew_rate = 4000,
208 .step_size = 12500,
209 .on_volt = 1100000,
210 .onlp_volt = 1100000,
211 .ret_volt = 837500,
212 .off_volt = 600000,
213 .volt_setup_time = 0,
214 .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
215 .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
216 .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
217 .vp_vddmin = OMAP4_VP_IVA_VLIMITTO_VDDMIN,
218 .vp_vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX,
219 .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
220 .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
221 .pmic_reg = OMAP4_VDD_IVA_SR_VOLT_REG,
222 .vsel_to_uv = twl6030_vsel_to_uv,
223 .uv_to_vsel = twl6030_uv_to_vsel,
224};
225
226static struct omap_volt_pmic_info omap4_core_volt_info = {
227 .slew_rate = 4000,
228 .step_size = 12500,
229 .on_volt = 1100000,
230 .onlp_volt = 1100000,
231 .ret_volt = 837500,
232 .off_volt = 600000,
233 .volt_setup_time = 0,
234 .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
235 .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
236 .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
237 .vp_vddmin = OMAP4_VP_CORE_VLIMITTO_VDDMIN,
238 .vp_vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX,
239 .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
240 .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
241 .pmic_reg = OMAP4_VDD_CORE_SR_VOLT_REG,
242 .vsel_to_uv = twl6030_vsel_to_uv,
243 .uv_to_vsel = twl6030_uv_to_vsel,
244};
245
246int __init omap4_twl_init(void)
247{
248 struct voltagedomain *voltdm;
249
250 if (!cpu_is_omap44xx())
251 return -ENODEV;
252
253 voltdm = omap_voltage_domain_lookup("mpu");
254 omap_voltage_register_pmic(voltdm, &omap4_mpu_volt_info);
255
256 voltdm = omap_voltage_domain_lookup("iva");
257 omap_voltage_register_pmic(voltdm, &omap4_iva_volt_info);
258
259 voltdm = omap_voltage_domain_lookup("core");
260 omap_voltage_register_pmic(voltdm, &omap4_core_volt_info);
261
262 return 0;
263}
264
265int __init omap3_twl_init(void)
266{
267 struct voltagedomain *voltdm;
268
269 if (!cpu_is_omap34xx())
270 return -ENODEV;
271
272 if (cpu_is_omap3630()) {
273 omap3_mpu_volt_info.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
274 omap3_mpu_volt_info.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
275 omap3_core_volt_info.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
276 omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
277 }
278
279 /*
280 * The smartreflex bit on twl4030 specifies if the setting of voltage
281 * is done over the I2C_SR path. Since this setting is independent of
282 * the actual usage of smartreflex AVS module, we enable TWL SR bit
283 * by default irrespective of whether smartreflex AVS module is enabled
284 * on the OMAP side or not. This is because without this bit enabled,
285 * the voltage scaling through vp forceupdate/bypass mechanism of
286 * voltage scaling will not function on TWL over I2C_SR.
287 */
288 if (!twl_sr_enable_autoinit)
289 omap3_twl_set_sr_bit(true);
290
291 voltdm = omap_voltage_domain_lookup("mpu");
292 omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);
293
294 voltdm = omap_voltage_domain_lookup("core");
295 omap_voltage_register_pmic(voltdm, &omap3_core_volt_info);
296
297 return 0;
298}
299
300/**
301 * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
302 * @enable: enable SR mode in twl or not
303 *
304 * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
305 * voltage scaling through OMAP SR works. Else, the smartreflex bit
306 * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
307 * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
308 * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
309 * in those scenarios this bit is to be cleared (enable = false).
310 *
311 * Returns 0 on success, error is returned if I2C read/write fails.
312 */
313int __init omap3_twl_set_sr_bit(bool enable)
314{
315 u8 temp;
316 int ret;
317 if (twl_sr_enable_autoinit)
318 pr_warning("%s: unexpected multiple calls\n", __func__);
319
320 ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &temp,
321 TWL4030_DCDC_GLOBAL_CFG);
322 if (ret)
323 goto err;
324
325 if (enable)
326 temp |= SMARTREFLEX_ENABLE;
327 else
328 temp &= ~SMARTREFLEX_ENABLE;
329
330 ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
331 TWL4030_DCDC_GLOBAL_CFG);
332 if (!ret) {
333 twl_sr_enable_autoinit = true;
334 return 0;
335 }
336err:
337 pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);
338 return ret;
339}