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1/*
2 * arch/arm/mach-netx/time.c
3 *
4 * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/clocksource.h>
24#include <linux/clockchips.h>
25#include <linux/io.h>
26
27#include <mach/hardware.h>
28#include <asm/mach/time.h>
29#include <mach/netx-regs.h>
30
31#define NETX_CLOCK_FREQ 100000000
32#define NETX_LATCH DIV_ROUND_CLOSEST(NETX_CLOCK_FREQ, HZ)
33
34#define TIMER_CLOCKEVENT 0
35#define TIMER_CLOCKSOURCE 1
36
37static void netx_set_mode(enum clock_event_mode mode,
38 struct clock_event_device *clk)
39{
40 u32 tmode;
41
42 /* disable timer */
43 writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));
44
45 switch (mode) {
46 case CLOCK_EVT_MODE_PERIODIC:
47 writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
48 tmode = NETX_GPIO_COUNTER_CTRL_RST_EN |
49 NETX_GPIO_COUNTER_CTRL_IRQ_EN |
50 NETX_GPIO_COUNTER_CTRL_RUN;
51 break;
52
53 case CLOCK_EVT_MODE_ONESHOT:
54 writel(0, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
55 tmode = NETX_GPIO_COUNTER_CTRL_IRQ_EN |
56 NETX_GPIO_COUNTER_CTRL_RUN;
57 break;
58
59 default:
60 WARN(1, "%s: unhandled mode %d\n", __func__, mode);
61 /* fall through */
62
63 case CLOCK_EVT_MODE_SHUTDOWN:
64 case CLOCK_EVT_MODE_UNUSED:
65 case CLOCK_EVT_MODE_RESUME:
66 tmode = 0;
67 break;
68 }
69
70 writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));
71}
72
73static int netx_set_next_event(unsigned long evt,
74 struct clock_event_device *clk)
75{
76 writel(0 - evt, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKEVENT));
77 return 0;
78}
79
80static struct clock_event_device netx_clockevent = {
81 .name = "netx-timer" __stringify(TIMER_CLOCKEVENT),
82 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
83 .set_next_event = netx_set_next_event,
84 .set_mode = netx_set_mode,
85};
86
87/*
88 * IRQ handler for the timer
89 */
90static irqreturn_t
91netx_timer_interrupt(int irq, void *dev_id)
92{
93 struct clock_event_device *evt = &netx_clockevent;
94
95 /* acknowledge interrupt */
96 writel(COUNTER_BIT(0), NETX_GPIO_IRQ);
97
98 evt->event_handler(evt);
99
100 return IRQ_HANDLED;
101}
102
103static struct irqaction netx_timer_irq = {
104 .name = "NetX Timer Tick",
105 .flags = IRQF_TIMER | IRQF_IRQPOLL,
106 .handler = netx_timer_interrupt,
107};
108
109/*
110 * Set up timer interrupt
111 */
112void __init netx_timer_init(void)
113{
114 /* disable timer initially */
115 writel(0, NETX_GPIO_COUNTER_CTRL(0));
116
117 /* Reset the timer value to zero */
118 writel(0, NETX_GPIO_COUNTER_CURRENT(0));
119
120 writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(0));
121
122 /* acknowledge interrupt */
123 writel(COUNTER_BIT(0), NETX_GPIO_IRQ);
124
125 /* Enable the interrupt in the specific timer
126 * register and start timer
127 */
128 writel(COUNTER_BIT(0), NETX_GPIO_IRQ_ENABLE);
129 writel(NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN,
130 NETX_GPIO_COUNTER_CTRL(0));
131
132 setup_irq(NETX_IRQ_TIMER0, &netx_timer_irq);
133
134 /* Setup timer one for clocksource */
135 writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
136 writel(0, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE));
137 writel(0xffffffff, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKSOURCE));
138
139 writel(NETX_GPIO_COUNTER_CTRL_RUN,
140 NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
141
142 clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE),
143 "netx_timer", NETX_CLOCK_FREQ, 200, 32, clocksource_mmio_readl_up);
144
145 /* with max_delta_ns >= delta2ns(0x800) the system currently runs fine.
146 * Adding some safety ... */
147 netx_clockevent.cpumask = cpumask_of(0);
148 clockevents_config_and_register(&netx_clockevent, NETX_CLOCK_FREQ,
149 0xa00, 0xfffffffe);
150}
1/*
2 * arch/arm/mach-netx/time.c
3 *
4 * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/clocksource.h>
24#include <linux/clockchips.h>
25#include <linux/io.h>
26
27#include <mach/hardware.h>
28#include <asm/mach/time.h>
29#include <mach/netx-regs.h>
30
31#define TIMER_CLOCKEVENT 0
32#define TIMER_CLOCKSOURCE 1
33
34static void netx_set_mode(enum clock_event_mode mode,
35 struct clock_event_device *clk)
36{
37 u32 tmode;
38
39 /* disable timer */
40 writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));
41
42 switch (mode) {
43 case CLOCK_EVT_MODE_PERIODIC:
44 writel(LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
45 tmode = NETX_GPIO_COUNTER_CTRL_RST_EN |
46 NETX_GPIO_COUNTER_CTRL_IRQ_EN |
47 NETX_GPIO_COUNTER_CTRL_RUN;
48 break;
49
50 case CLOCK_EVT_MODE_ONESHOT:
51 writel(0, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
52 tmode = NETX_GPIO_COUNTER_CTRL_IRQ_EN |
53 NETX_GPIO_COUNTER_CTRL_RUN;
54 break;
55
56 default:
57 WARN(1, "%s: unhandled mode %d\n", __func__, mode);
58 /* fall through */
59
60 case CLOCK_EVT_MODE_SHUTDOWN:
61 case CLOCK_EVT_MODE_UNUSED:
62 case CLOCK_EVT_MODE_RESUME:
63 tmode = 0;
64 break;
65 }
66
67 writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));
68}
69
70static int netx_set_next_event(unsigned long evt,
71 struct clock_event_device *clk)
72{
73 writel(0 - evt, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKEVENT));
74 return 0;
75}
76
77static struct clock_event_device netx_clockevent = {
78 .name = "netx-timer" __stringify(TIMER_CLOCKEVENT),
79 .shift = 32,
80 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
81 .set_next_event = netx_set_next_event,
82 .set_mode = netx_set_mode,
83};
84
85/*
86 * IRQ handler for the timer
87 */
88static irqreturn_t
89netx_timer_interrupt(int irq, void *dev_id)
90{
91 struct clock_event_device *evt = &netx_clockevent;
92
93 /* acknowledge interrupt */
94 writel(COUNTER_BIT(0), NETX_GPIO_IRQ);
95
96 evt->event_handler(evt);
97
98 return IRQ_HANDLED;
99}
100
101static struct irqaction netx_timer_irq = {
102 .name = "NetX Timer Tick",
103 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
104 .handler = netx_timer_interrupt,
105};
106
107/*
108 * Set up timer interrupt
109 */
110static void __init netx_timer_init(void)
111{
112 /* disable timer initially */
113 writel(0, NETX_GPIO_COUNTER_CTRL(0));
114
115 /* Reset the timer value to zero */
116 writel(0, NETX_GPIO_COUNTER_CURRENT(0));
117
118 writel(LATCH, NETX_GPIO_COUNTER_MAX(0));
119
120 /* acknowledge interrupt */
121 writel(COUNTER_BIT(0), NETX_GPIO_IRQ);
122
123 /* Enable the interrupt in the specific timer
124 * register and start timer
125 */
126 writel(COUNTER_BIT(0), NETX_GPIO_IRQ_ENABLE);
127 writel(NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN,
128 NETX_GPIO_COUNTER_CTRL(0));
129
130 setup_irq(NETX_IRQ_TIMER0, &netx_timer_irq);
131
132 /* Setup timer one for clocksource */
133 writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
134 writel(0, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE));
135 writel(0xffffffff, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKSOURCE));
136
137 writel(NETX_GPIO_COUNTER_CTRL_RUN,
138 NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
139
140 clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE),
141 "netx_timer", CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up);
142
143 netx_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
144 netx_clockevent.shift);
145 netx_clockevent.max_delta_ns =
146 clockevent_delta2ns(0xfffffffe, &netx_clockevent);
147 /* with max_delta_ns >= delta2ns(0x800) the system currently runs fine.
148 * Adding some safety ... */
149 netx_clockevent.min_delta_ns =
150 clockevent_delta2ns(0xa00, &netx_clockevent);
151 netx_clockevent.cpumask = cpumask_of(0);
152 clockevents_register_device(&netx_clockevent);
153}
154
155struct sys_timer netx_timer = {
156 .init = netx_timer_init,
157};