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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 | /* * Copyright (C) 1999 Niibe Yutaka * Copyright (C) 2003 - 2007 Paul Mundt * * ASID handling idea taken from MIPS implementation. */ #ifndef __ASM_SH_MMU_CONTEXT_H #define __ASM_SH_MMU_CONTEXT_H #ifdef __KERNEL__ #include <cpu/mmu_context.h> #include <asm/tlbflush.h> #include <asm/uaccess.h> #include <asm/io.h> #include <asm-generic/mm_hooks.h> /* * The MMU "context" consists of two things: * (a) TLB cache version (or round, cycle whatever expression you like) * (b) ASID (Address Space IDentifier) */ #ifdef CONFIG_CPU_HAS_PTEAEX #define MMU_CONTEXT_ASID_MASK 0x0000ffff #else #define MMU_CONTEXT_ASID_MASK 0x000000ff #endif #define MMU_CONTEXT_VERSION_MASK (~0UL & ~MMU_CONTEXT_ASID_MASK) #define MMU_CONTEXT_FIRST_VERSION (MMU_CONTEXT_ASID_MASK + 1) /* Impossible ASID value, to differentiate from NO_CONTEXT. */ #define MMU_NO_ASID MMU_CONTEXT_FIRST_VERSION #define NO_CONTEXT 0UL #define asid_cache(cpu) (cpu_data[cpu].asid_cache) #ifdef CONFIG_MMU #define cpu_context(cpu, mm) ((mm)->context.id[cpu]) #define cpu_asid(cpu, mm) \ (cpu_context((cpu), (mm)) & MMU_CONTEXT_ASID_MASK) /* * Virtual Page Number mask */ #define MMU_VPN_MASK 0xfffff000 #if defined(CONFIG_SUPERH32) #include "mmu_context_32.h" #else #include "mmu_context_64.h" #endif /* * Get MMU context if needed. */ static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu) { unsigned long asid = asid_cache(cpu); /* Check if we have old version of context. */ if (((cpu_context(cpu, mm) ^ asid) & MMU_CONTEXT_VERSION_MASK) == 0) /* It's up to date, do nothing */ return; /* It's old, we need to get new context with new version. */ if (!(++asid & MMU_CONTEXT_ASID_MASK)) { /* * We exhaust ASID of this version. * Flush all TLB and start new cycle. */ local_flush_tlb_all(); #ifdef CONFIG_SUPERH64 /* * The SH-5 cache uses the ASIDs, requiring both the I and D * cache to be flushed when the ASID is exhausted. Weak. */ flush_cache_all(); #endif /* * Fix version; Note that we avoid version #0 * to distingush NO_CONTEXT. */ if (!asid) asid = MMU_CONTEXT_FIRST_VERSION; } cpu_context(cpu, mm) = asid_cache(cpu) = asid; } /* * Initialize the context related info for a new mm_struct * instance. */ static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm) { int i; for (i = 0; i < num_online_cpus(); i++) cpu_context(i, mm) = NO_CONTEXT; return 0; } /* * After we have set current->mm to a new value, this activates * the context for the new mm so we see the new mappings. */ static inline void activate_context(struct mm_struct *mm, unsigned int cpu) { get_mmu_context(mm, cpu); set_asid(cpu_asid(cpu, mm)); } static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk) { unsigned int cpu = smp_processor_id(); if (likely(prev != next)) { cpumask_set_cpu(cpu, mm_cpumask(next)); set_TTB(next->pgd); activate_context(next, cpu); } else if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next))) activate_context(next, cpu); } #define activate_mm(prev, next) switch_mm((prev),(next),NULL) #define deactivate_mm(tsk,mm) do { } while (0) #define enter_lazy_tlb(mm,tsk) do { } while (0) #else #define set_asid(asid) do { } while (0) #define get_asid() (0) #define cpu_asid(cpu, mm) ({ (void)cpu; NO_CONTEXT; }) #define switch_and_save_asid(asid) (0) #define set_TTB(pgd) do { } while (0) #define get_TTB() (0) #include <asm-generic/mmu_context.h> #endif /* CONFIG_MMU */ #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4) /* * If this processor has an MMU, we need methods to turn it off/on .. * paging_init() will also have to be updated for the processor in * question. */ static inline void enable_mmu(void) { unsigned int cpu = smp_processor_id(); /* Enable MMU */ __raw_writel(MMU_CONTROL_INIT, MMUCR); ctrl_barrier(); if (asid_cache(cpu) == NO_CONTEXT) asid_cache(cpu) = MMU_CONTEXT_FIRST_VERSION; set_asid(asid_cache(cpu) & MMU_CONTEXT_ASID_MASK); } static inline void disable_mmu(void) { unsigned long cr; cr = __raw_readl(MMUCR); cr &= ~MMU_CONTROL_INIT; __raw_writel(cr, MMUCR); ctrl_barrier(); } #else /* * MMU control handlers for processors lacking memory * management hardware. */ #define enable_mmu() do { } while (0) #define disable_mmu() do { } while (0) #endif #endif /* __KERNEL__ */ #endif /* __ASM_SH_MMU_CONTEXT_H */ |