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1/*
2 * Copyright © 2007-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23#ifndef __DRM_EDID_H__
24#define __DRM_EDID_H__
25
26#include <linux/types.h>
27
28#define EDID_LENGTH 128
29#define DDC_ADDR 0x50
30
31#define CEA_EXT 0x02
32#define VTB_EXT 0x10
33#define DI_EXT 0x40
34#define LS_EXT 0x50
35#define MI_EXT 0x60
36
37struct est_timings {
38 u8 t1;
39 u8 t2;
40 u8 mfg_rsvd;
41} __attribute__((packed));
42
43/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
44#define EDID_TIMING_ASPECT_SHIFT 6
45#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
46
47/* need to add 60 */
48#define EDID_TIMING_VFREQ_SHIFT 0
49#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
50
51struct std_timing {
52 u8 hsize; /* need to multiply by 8 then add 248 */
53 u8 vfreq_aspect;
54} __attribute__((packed));
55
56#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
57#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
58#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
59#define DRM_EDID_PT_STEREO (1 << 5)
60#define DRM_EDID_PT_INTERLACED (1 << 7)
61
62/* If detailed data is pixel timing */
63struct detailed_pixel_timing {
64 u8 hactive_lo;
65 u8 hblank_lo;
66 u8 hactive_hblank_hi;
67 u8 vactive_lo;
68 u8 vblank_lo;
69 u8 vactive_vblank_hi;
70 u8 hsync_offset_lo;
71 u8 hsync_pulse_width_lo;
72 u8 vsync_offset_pulse_width_lo;
73 u8 hsync_vsync_offset_pulse_width_hi;
74 u8 width_mm_lo;
75 u8 height_mm_lo;
76 u8 width_height_mm_hi;
77 u8 hborder;
78 u8 vborder;
79 u8 misc;
80} __attribute__((packed));
81
82/* If it's not pixel timing, it'll be one of the below */
83struct detailed_data_string {
84 u8 str[13];
85} __attribute__((packed));
86
87struct detailed_data_monitor_range {
88 u8 min_vfreq;
89 u8 max_vfreq;
90 u8 min_hfreq_khz;
91 u8 max_hfreq_khz;
92 u8 pixel_clock_mhz; /* need to multiply by 10 */
93 __le16 sec_gtf_toggle; /* A000=use above, 20=use below */
94 u8 hfreq_start_khz; /* need to multiply by 2 */
95 u8 c; /* need to divide by 2 */
96 __le16 m;
97 u8 k;
98 u8 j; /* need to divide by 2 */
99} __attribute__((packed));
100
101struct detailed_data_wpindex {
102 u8 white_yx_lo; /* Lower 2 bits each */
103 u8 white_x_hi;
104 u8 white_y_hi;
105 u8 gamma; /* need to divide by 100 then add 1 */
106} __attribute__((packed));
107
108struct detailed_data_color_point {
109 u8 windex1;
110 u8 wpindex1[3];
111 u8 windex2;
112 u8 wpindex2[3];
113} __attribute__((packed));
114
115struct cvt_timing {
116 u8 code[3];
117} __attribute__((packed));
118
119struct detailed_non_pixel {
120 u8 pad1;
121 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
122 fb=color point data, fa=standard timing data,
123 f9=undefined, f8=mfg. reserved */
124 u8 pad2;
125 union {
126 struct detailed_data_string str;
127 struct detailed_data_monitor_range range;
128 struct detailed_data_wpindex color;
129 struct std_timing timings[6];
130 struct cvt_timing cvt[4];
131 } data;
132} __attribute__((packed));
133
134#define EDID_DETAIL_EST_TIMINGS 0xf7
135#define EDID_DETAIL_CVT_3BYTE 0xf8
136#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
137#define EDID_DETAIL_STD_MODES 0xfa
138#define EDID_DETAIL_MONITOR_CPDATA 0xfb
139#define EDID_DETAIL_MONITOR_NAME 0xfc
140#define EDID_DETAIL_MONITOR_RANGE 0xfd
141#define EDID_DETAIL_MONITOR_STRING 0xfe
142#define EDID_DETAIL_MONITOR_SERIAL 0xff
143
144struct detailed_timing {
145 __le16 pixel_clock; /* need to multiply by 10 KHz */
146 union {
147 struct detailed_pixel_timing pixel_data;
148 struct detailed_non_pixel other_data;
149 } data;
150} __attribute__((packed));
151
152#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
153#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)
154#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)
155#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
156#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
157#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
158#define DRM_EDID_INPUT_DIGITAL (1 << 7)
159#define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4)
160#define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4)
161#define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4)
162#define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4)
163#define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4)
164#define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4)
165#define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4)
166#define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4)
167#define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4)
168#define DRM_EDID_DIGITAL_TYPE_UNDEF (0)
169#define DRM_EDID_DIGITAL_TYPE_DVI (1)
170#define DRM_EDID_DIGITAL_TYPE_HDMI_A (2)
171#define DRM_EDID_DIGITAL_TYPE_HDMI_B (3)
172#define DRM_EDID_DIGITAL_TYPE_MDDI (4)
173#define DRM_EDID_DIGITAL_TYPE_DP (5)
174
175#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0)
176#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
177#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
178/* If analog */
179#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
180/* If digital */
181#define DRM_EDID_FEATURE_COLOR_MASK (3 << 3)
182#define DRM_EDID_FEATURE_RGB (0 << 3)
183#define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3)
184#define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3)
185#define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */
186
187#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
188#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
189#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
190
191struct edid {
192 u8 header[8];
193 /* Vendor & product info */
194 u8 mfg_id[2];
195 u8 prod_code[2];
196 u32 serial; /* FIXME: byte order */
197 u8 mfg_week;
198 u8 mfg_year;
199 /* EDID version */
200 u8 version;
201 u8 revision;
202 /* Display info: */
203 u8 input;
204 u8 width_cm;
205 u8 height_cm;
206 u8 gamma;
207 u8 features;
208 /* Color characteristics */
209 u8 red_green_lo;
210 u8 black_white_lo;
211 u8 red_x;
212 u8 red_y;
213 u8 green_x;
214 u8 green_y;
215 u8 blue_x;
216 u8 blue_y;
217 u8 white_x;
218 u8 white_y;
219 /* Est. timings and mfg rsvd timings*/
220 struct est_timings established_timings;
221 /* Standard timings 1-8*/
222 struct std_timing standard_timings[8];
223 /* Detailing timings 1-4 */
224 struct detailed_timing detailed_timings[4];
225 /* Number of 128 byte ext. blocks */
226 u8 extensions;
227 /* Checksum */
228 u8 checksum;
229} __attribute__((packed));
230
231#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
232
233#endif /* __DRM_EDID_H__ */
1/*
2 * Copyright © 2007-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23#ifndef __DRM_EDID_H__
24#define __DRM_EDID_H__
25
26#include <linux/types.h>
27
28enum hdmi_quantization_range;
29struct drm_connector;
30struct drm_device;
31struct drm_display_mode;
32struct drm_edid;
33struct hdmi_avi_infoframe;
34struct hdmi_vendor_infoframe;
35struct i2c_adapter;
36
37#define EDID_LENGTH 128
38#define DDC_ADDR 0x50
39#define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */
40
41#define CEA_EXT 0x02
42#define VTB_EXT 0x10
43#define DI_EXT 0x40
44#define LS_EXT 0x50
45#define MI_EXT 0x60
46#define DISPLAYID_EXT 0x70
47
48struct est_timings {
49 u8 t1;
50 u8 t2;
51 u8 mfg_rsvd;
52} __packed;
53
54/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
55#define EDID_TIMING_ASPECT_SHIFT 6
56#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
57
58/* need to add 60 */
59#define EDID_TIMING_VFREQ_SHIFT 0
60#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
61
62struct std_timing {
63 u8 hsize; /* need to multiply by 8 then add 248 */
64 u8 vfreq_aspect;
65} __packed;
66
67#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
68#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
69#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
70#define DRM_EDID_PT_STEREO (1 << 5)
71#define DRM_EDID_PT_INTERLACED (1 << 7)
72
73/* If detailed data is pixel timing */
74struct detailed_pixel_timing {
75 u8 hactive_lo;
76 u8 hblank_lo;
77 u8 hactive_hblank_hi;
78 u8 vactive_lo;
79 u8 vblank_lo;
80 u8 vactive_vblank_hi;
81 u8 hsync_offset_lo;
82 u8 hsync_pulse_width_lo;
83 u8 vsync_offset_pulse_width_lo;
84 u8 hsync_vsync_offset_pulse_width_hi;
85 u8 width_mm_lo;
86 u8 height_mm_lo;
87 u8 width_height_mm_hi;
88 u8 hborder;
89 u8 vborder;
90 u8 misc;
91} __packed;
92
93/* If it's not pixel timing, it'll be one of the below */
94struct detailed_data_string {
95 u8 str[13];
96} __packed;
97
98#define DRM_EDID_RANGE_OFFSET_MIN_VFREQ (1 << 0) /* 1.4 */
99#define DRM_EDID_RANGE_OFFSET_MAX_VFREQ (1 << 1) /* 1.4 */
100#define DRM_EDID_RANGE_OFFSET_MIN_HFREQ (1 << 2) /* 1.4 */
101#define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << 3) /* 1.4 */
102
103#define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00 /* 1.3 */
104#define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x01 /* 1.4 */
105#define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02 /* 1.3 */
106#define DRM_EDID_CVT_SUPPORT_FLAG 0x04 /* 1.4 */
107
108#define DRM_EDID_CVT_FLAGS_STANDARD_BLANKING (1 << 3)
109#define DRM_EDID_CVT_FLAGS_REDUCED_BLANKING (1 << 4)
110
111struct detailed_data_monitor_range {
112 u8 min_vfreq;
113 u8 max_vfreq;
114 u8 min_hfreq_khz;
115 u8 max_hfreq_khz;
116 u8 pixel_clock_mhz; /* need to multiply by 10 */
117 u8 flags;
118 union {
119 struct {
120 u8 reserved;
121 u8 hfreq_start_khz; /* need to multiply by 2 */
122 u8 c; /* need to divide by 2 */
123 __le16 m;
124 u8 k;
125 u8 j; /* need to divide by 2 */
126 } __packed gtf2;
127 struct {
128 u8 version;
129 u8 data1; /* high 6 bits: extra clock resolution */
130 u8 data2; /* plus low 2 of above: max hactive */
131 u8 supported_aspects;
132 u8 flags; /* preferred aspect and blanking support */
133 u8 supported_scalings;
134 u8 preferred_refresh;
135 } __packed cvt;
136 } __packed formula;
137} __packed;
138
139struct detailed_data_wpindex {
140 u8 white_yx_lo; /* Lower 2 bits each */
141 u8 white_x_hi;
142 u8 white_y_hi;
143 u8 gamma; /* need to divide by 100 then add 1 */
144} __packed;
145
146struct detailed_data_color_point {
147 u8 windex1;
148 u8 wpindex1[3];
149 u8 windex2;
150 u8 wpindex2[3];
151} __packed;
152
153struct cvt_timing {
154 u8 code[3];
155} __packed;
156
157struct detailed_non_pixel {
158 u8 pad1;
159 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
160 fb=color point data, fa=standard timing data,
161 f9=undefined, f8=mfg. reserved */
162 u8 pad2;
163 union {
164 struct detailed_data_string str;
165 struct detailed_data_monitor_range range;
166 struct detailed_data_wpindex color;
167 struct std_timing timings[6];
168 struct cvt_timing cvt[4];
169 } __packed data;
170} __packed;
171
172#define EDID_DETAIL_EST_TIMINGS 0xf7
173#define EDID_DETAIL_CVT_3BYTE 0xf8
174#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
175#define EDID_DETAIL_STD_MODES 0xfa
176#define EDID_DETAIL_MONITOR_CPDATA 0xfb
177#define EDID_DETAIL_MONITOR_NAME 0xfc
178#define EDID_DETAIL_MONITOR_RANGE 0xfd
179#define EDID_DETAIL_MONITOR_STRING 0xfe
180#define EDID_DETAIL_MONITOR_SERIAL 0xff
181
182struct detailed_timing {
183 __le16 pixel_clock; /* need to multiply by 10 KHz */
184 union {
185 struct detailed_pixel_timing pixel_data;
186 struct detailed_non_pixel other_data;
187 } __packed data;
188} __packed;
189
190#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
191#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)
192#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)
193#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
194#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
195#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
196#define DRM_EDID_INPUT_DIGITAL (1 << 7)
197#define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) /* 1.4 */
198#define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) /* 1.4 */
199#define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) /* 1.4 */
200#define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) /* 1.4 */
201#define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) /* 1.4 */
202#define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) /* 1.4 */
203#define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) /* 1.4 */
204#define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) /* 1.4 */
205#define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) /* 1.4 */
206#define DRM_EDID_DIGITAL_TYPE_MASK (7 << 0) /* 1.4 */
207#define DRM_EDID_DIGITAL_TYPE_UNDEF (0 << 0) /* 1.4 */
208#define DRM_EDID_DIGITAL_TYPE_DVI (1 << 0) /* 1.4 */
209#define DRM_EDID_DIGITAL_TYPE_HDMI_A (2 << 0) /* 1.4 */
210#define DRM_EDID_DIGITAL_TYPE_HDMI_B (3 << 0) /* 1.4 */
211#define DRM_EDID_DIGITAL_TYPE_MDDI (4 << 0) /* 1.4 */
212#define DRM_EDID_DIGITAL_TYPE_DP (5 << 0) /* 1.4 */
213#define DRM_EDID_DIGITAL_DFP_1_X (1 << 0) /* 1.3 */
214
215#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) /* 1.2 */
216#define DRM_EDID_FEATURE_CONTINUOUS_FREQ (1 << 0) /* 1.4 */
217#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
218#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
219/* If analog */
220#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
221/* If digital */
222#define DRM_EDID_FEATURE_COLOR_MASK (3 << 3)
223#define DRM_EDID_FEATURE_RGB (0 << 3)
224#define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3)
225#define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3)
226#define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */
227
228#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
229#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
230#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
231
232#define DRM_EDID_HDMI_DC_48 (1 << 6)
233#define DRM_EDID_HDMI_DC_36 (1 << 5)
234#define DRM_EDID_HDMI_DC_30 (1 << 4)
235#define DRM_EDID_HDMI_DC_Y444 (1 << 3)
236
237/* YCBCR 420 deep color modes */
238#define DRM_EDID_YCBCR420_DC_48 (1 << 2)
239#define DRM_EDID_YCBCR420_DC_36 (1 << 1)
240#define DRM_EDID_YCBCR420_DC_30 (1 << 0)
241#define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \
242 DRM_EDID_YCBCR420_DC_36 | \
243 DRM_EDID_YCBCR420_DC_30)
244
245/* HDMI 2.1 additional fields */
246#define DRM_EDID_MAX_FRL_RATE_MASK 0xf0
247#define DRM_EDID_FAPA_START_LOCATION (1 << 0)
248#define DRM_EDID_ALLM (1 << 1)
249#define DRM_EDID_FVA (1 << 2)
250
251/* Deep Color specific */
252#define DRM_EDID_DC_30BIT_420 (1 << 0)
253#define DRM_EDID_DC_36BIT_420 (1 << 1)
254#define DRM_EDID_DC_48BIT_420 (1 << 2)
255
256/* VRR specific */
257#define DRM_EDID_CNMVRR (1 << 3)
258#define DRM_EDID_CINEMA_VRR (1 << 4)
259#define DRM_EDID_MDELTA (1 << 5)
260#define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0
261#define DRM_EDID_VRR_MAX_LOWER_MASK 0xff
262#define DRM_EDID_VRR_MIN_MASK 0x3f
263
264/* DSC specific */
265#define DRM_EDID_DSC_10BPC (1 << 0)
266#define DRM_EDID_DSC_12BPC (1 << 1)
267#define DRM_EDID_DSC_16BPC (1 << 2)
268#define DRM_EDID_DSC_ALL_BPP (1 << 3)
269#define DRM_EDID_DSC_NATIVE_420 (1 << 6)
270#define DRM_EDID_DSC_1P2 (1 << 7)
271#define DRM_EDID_DSC_MAX_FRL_RATE_MASK 0xf0
272#define DRM_EDID_DSC_MAX_SLICES 0xf
273#define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f
274
275struct edid {
276 u8 header[8];
277 /* Vendor & product info */
278 u8 mfg_id[2];
279 u8 prod_code[2];
280 u32 serial; /* FIXME: byte order */
281 u8 mfg_week;
282 u8 mfg_year;
283 /* EDID version */
284 u8 version;
285 u8 revision;
286 /* Display info: */
287 u8 input;
288 u8 width_cm;
289 u8 height_cm;
290 u8 gamma;
291 u8 features;
292 /* Color characteristics */
293 u8 red_green_lo;
294 u8 blue_white_lo;
295 u8 red_x;
296 u8 red_y;
297 u8 green_x;
298 u8 green_y;
299 u8 blue_x;
300 u8 blue_y;
301 u8 white_x;
302 u8 white_y;
303 /* Est. timings and mfg rsvd timings*/
304 struct est_timings established_timings;
305 /* Standard timings 1-8*/
306 struct std_timing standard_timings[8];
307 /* Detailing timings 1-4 */
308 struct detailed_timing detailed_timings[4];
309 /* Number of 128 byte ext. blocks */
310 u8 extensions;
311 /* Checksum */
312 u8 checksum;
313} __packed;
314
315#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
316
317/* Short Audio Descriptor */
318struct cea_sad {
319 u8 format;
320 u8 channels; /* max number of channels - 1 */
321 u8 freq;
322 u8 byte2; /* meaning depends on format */
323};
324
325int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads);
326int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb);
327int drm_av_sync_delay(struct drm_connector *connector,
328 const struct drm_display_mode *mode);
329
330bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2);
331
332int
333drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
334 const struct drm_connector *connector,
335 const struct drm_display_mode *mode);
336int
337drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
338 const struct drm_connector *connector,
339 const struct drm_display_mode *mode);
340
341void
342drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
343 const struct drm_connector *connector,
344 const struct drm_display_mode *mode,
345 enum hdmi_quantization_range rgb_quant_range);
346
347/**
348 * drm_edid_decode_mfg_id - Decode the manufacturer ID
349 * @mfg_id: The manufacturer ID
350 * @vend: A 4-byte buffer to store the 3-letter vendor string plus a '\0'
351 * termination
352 */
353static inline const char *drm_edid_decode_mfg_id(u16 mfg_id, char vend[4])
354{
355 vend[0] = '@' + ((mfg_id >> 10) & 0x1f);
356 vend[1] = '@' + ((mfg_id >> 5) & 0x1f);
357 vend[2] = '@' + ((mfg_id >> 0) & 0x1f);
358 vend[3] = '\0';
359
360 return vend;
361}
362
363/**
364 * drm_edid_encode_panel_id - Encode an ID for matching against drm_edid_get_panel_id()
365 * @vend_chr_0: First character of the vendor string.
366 * @vend_chr_1: Second character of the vendor string.
367 * @vend_chr_2: Third character of the vendor string.
368 * @product_id: The 16-bit product ID.
369 *
370 * This is a macro so that it can be calculated at compile time and used
371 * as an initializer.
372 *
373 * For instance:
374 * drm_edid_encode_panel_id('B', 'O', 'E', 0x2d08) => 0x09e52d08
375 *
376 * Return: a 32-bit ID per panel.
377 */
378#define drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, product_id) \
379 ((((u32)(vend_chr_0) - '@') & 0x1f) << 26 | \
380 (((u32)(vend_chr_1) - '@') & 0x1f) << 21 | \
381 (((u32)(vend_chr_2) - '@') & 0x1f) << 16 | \
382 ((product_id) & 0xffff))
383
384/**
385 * drm_edid_decode_panel_id - Decode a panel ID from drm_edid_encode_panel_id()
386 * @panel_id: The panel ID to decode.
387 * @vend: A 4-byte buffer to store the 3-letter vendor string plus a '\0'
388 * termination
389 * @product_id: The product ID will be returned here.
390 *
391 * For instance, after:
392 * drm_edid_decode_panel_id(0x09e52d08, vend, &product_id)
393 * These will be true:
394 * vend[0] = 'B'
395 * vend[1] = 'O'
396 * vend[2] = 'E'
397 * vend[3] = '\0'
398 * product_id = 0x2d08
399 */
400static inline void drm_edid_decode_panel_id(u32 panel_id, char vend[4], u16 *product_id)
401{
402 *product_id = (u16)(panel_id & 0xffff);
403 drm_edid_decode_mfg_id(panel_id >> 16, vend);
404}
405
406bool drm_probe_ddc(struct i2c_adapter *adapter);
407struct edid *drm_do_get_edid(struct drm_connector *connector,
408 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
409 size_t len),
410 void *data);
411struct edid *drm_get_edid(struct drm_connector *connector,
412 struct i2c_adapter *adapter);
413u32 drm_edid_get_panel_id(struct i2c_adapter *adapter);
414struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
415 struct i2c_adapter *adapter);
416struct edid *drm_edid_duplicate(const struct edid *edid);
417int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid);
418int drm_edid_override_connector_update(struct drm_connector *connector);
419
420u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
421bool drm_detect_hdmi_monitor(const struct edid *edid);
422bool drm_detect_monitor_audio(const struct edid *edid);
423enum hdmi_quantization_range
424drm_default_rgb_quant_range(const struct drm_display_mode *mode);
425int drm_add_modes_noedid(struct drm_connector *connector,
426 int hdisplay, int vdisplay);
427
428int drm_edid_header_is_valid(const void *edid);
429bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
430 bool *edid_corrupt);
431bool drm_edid_is_valid(struct edid *edid);
432void drm_edid_get_monitor_name(const struct edid *edid, char *name,
433 int buflen);
434struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
435 int hsize, int vsize, int fresh,
436 bool rb);
437struct drm_display_mode *
438drm_display_mode_from_cea_vic(struct drm_device *dev,
439 u8 video_code);
440
441/* Interface based on struct drm_edid */
442const struct drm_edid *drm_edid_alloc(const void *edid, size_t size);
443const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid);
444void drm_edid_free(const struct drm_edid *drm_edid);
445bool drm_edid_valid(const struct drm_edid *drm_edid);
446const struct edid *drm_edid_raw(const struct drm_edid *drm_edid);
447const struct drm_edid *drm_edid_read(struct drm_connector *connector);
448const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
449 struct i2c_adapter *adapter);
450const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
451 int (*read_block)(void *context, u8 *buf, unsigned int block, size_t len),
452 void *context);
453const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector,
454 struct i2c_adapter *adapter);
455int drm_edid_connector_update(struct drm_connector *connector,
456 const struct drm_edid *edid);
457int drm_edid_connector_add_modes(struct drm_connector *connector);
458bool drm_edid_is_digital(const struct drm_edid *drm_edid);
459
460const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
461 int ext_id, int *ext_index);
462
463#endif /* __DRM_EDID_H__ */