1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * OMAP5xxx bandgap registers, bitfields and temperature definitions
  4 *
  5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
  6 * Contact:
  7 *   Eduardo Valentin <eduardo.valentin@ti.com>
  8 */
  9#ifndef __OMAP5XXX_BANDGAP_H
 10#define __OMAP5XXX_BANDGAP_H
 11
 12/**
 13 * *** OMAP5430 ***
 14 *
 15 * Below, in sequence, are the Register definitions,
 16 * the bitfields and the temperature definitions for OMAP5430.
 17 */
 18
 19/**
 20 * OMAP5430 register definitions
 21 *
 22 * Registers are defined as offsets. The offsets are
 23 * relative to FUSE_OPP_BGAP_GPU on 5430.
 24 *
 25 * Register below are grouped by domain (not necessarily in offset order)
 26 */
 27
 28/* OMAP5430.GPU register offsets */
 29#define OMAP5430_FUSE_OPP_BGAP_GPU			0x0
 30#define OMAP5430_TEMP_SENSOR_GPU_OFFSET			0x150
 31#define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET		0x1A8
 32#define OMAP5430_BGAP_TSHUT_GPU_OFFSET			0x1B4
 33#define OMAP5430_BGAP_DTEMP_GPU_1_OFFSET		0x1F8
 34#define OMAP5430_BGAP_DTEMP_GPU_2_OFFSET		0x1FC
 35
 36/* OMAP5430.MPU register offsets */
 37#define OMAP5430_FUSE_OPP_BGAP_MPU			0x4
 38#define OMAP5430_TEMP_SENSOR_MPU_OFFSET			0x14C
 39#define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET		0x1A4
 40#define OMAP5430_BGAP_TSHUT_MPU_OFFSET			0x1B0
 41#define OMAP5430_BGAP_DTEMP_MPU_1_OFFSET		0x1E4
 42#define OMAP5430_BGAP_DTEMP_MPU_2_OFFSET		0x1E8
 43
 44/* OMAP5430.MPU register offsets */
 45#define OMAP5430_FUSE_OPP_BGAP_CORE			0x8
 46#define OMAP5430_TEMP_SENSOR_CORE_OFFSET		0x154
 47#define OMAP5430_BGAP_THRESHOLD_CORE_OFFSET		0x1AC
 48#define OMAP5430_BGAP_TSHUT_CORE_OFFSET			0x1B8
 49#define OMAP5430_BGAP_DTEMP_CORE_1_OFFSET		0x20C
 50#define OMAP5430_BGAP_DTEMP_CORE_2_OFFSET		0x210
 51
 52/* OMAP5430.common register offsets */
 53#define OMAP5430_BGAP_CTRL_OFFSET			0x1A0
 54#define OMAP5430_BGAP_STATUS_OFFSET			0x1C8
 55
 56/**
 57 * Register bitfields for OMAP5430
 58 *
 59 * All the macros bellow define the required bits for
 60 * controlling temperature on OMAP5430. Bit defines are
 61 * grouped by register.
 62 */
 63
 64/* OMAP5430.TEMP_SENSOR */
 65#define OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK		BIT(12)
 66#define OMAP5430_BGAP_TEMPSOFF_MASK			BIT(11)
 67#define OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK		BIT(10)
 68#define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK		(0x3ff << 0)
 69
 70/* OMAP5430.BANDGAP_CTRL */
 71#define OMAP5430_MASK_COUNTER_DELAY_MASK		(0x7 << 27)
 72#define OMAP5430_MASK_FREEZE_CORE_MASK			BIT(23)
 73#define OMAP5430_MASK_FREEZE_GPU_MASK			BIT(22)
 74#define OMAP5430_MASK_FREEZE_MPU_MASK			BIT(21)
 75#define OMAP5430_MASK_HOT_CORE_MASK			BIT(5)
 76#define OMAP5430_MASK_COLD_CORE_MASK			BIT(4)
 77#define OMAP5430_MASK_HOT_GPU_MASK			BIT(3)
 78#define OMAP5430_MASK_COLD_GPU_MASK			BIT(2)
 79#define OMAP5430_MASK_HOT_MPU_MASK			BIT(1)
 80#define OMAP5430_MASK_COLD_MPU_MASK			BIT(0)
 81
 82/* OMAP5430.BANDGAP_COUNTER */
 83#define OMAP5430_COUNTER_MASK				(0xffffff << 0)
 84
 85/* OMAP5430.BANDGAP_THRESHOLD */
 86#define OMAP5430_T_HOT_MASK				(0x3ff << 16)
 87#define OMAP5430_T_COLD_MASK				(0x3ff << 0)
 88
 89/* OMAP5430.TSHUT_THRESHOLD */
 90#define OMAP5430_TSHUT_HOT_MASK				(0x3ff << 16)
 91#define OMAP5430_TSHUT_COLD_MASK			(0x3ff << 0)
 92
 93/* OMAP5430.BANDGAP_STATUS */
 94#define OMAP5430_HOT_CORE_FLAG_MASK			BIT(5)
 95#define OMAP5430_COLD_CORE_FLAG_MASK			BIT(4)
 96#define OMAP5430_HOT_GPU_FLAG_MASK			BIT(3)
 97#define OMAP5430_COLD_GPU_FLAG_MASK			BIT(2)
 98#define OMAP5430_HOT_MPU_FLAG_MASK			BIT(1)
 99#define OMAP5430_COLD_MPU_FLAG_MASK			BIT(0)
100
101/**
102 * Temperature limits and thresholds for OMAP5430
103 *
104 * All the macros bellow are definitions for handling the
105 * ADC conversions and representation of temperature limits
106 * and thresholds for OMAP5430. Definitions are grouped
107 * by temperature domain.
108 */
109
110/* OMAP5430.common temperature definitions */
111/* ADC conversion table limits */
112#define OMAP5430_ADC_START_VALUE			540
113#define OMAP5430_ADC_END_VALUE				945
114
115/* OMAP5430.GPU temperature definitions */
116/* bandgap clock limits */
117#define OMAP5430_GPU_MAX_FREQ				1500000
118#define OMAP5430_GPU_MIN_FREQ				1000000
119/* interrupts thresholds */
120#define OMAP5430_GPU_TSHUT_HOT				915
121#define OMAP5430_GPU_TSHUT_COLD				900
122#define OMAP5430_GPU_T_HOT				800
123#define OMAP5430_GPU_T_COLD				795
124
125/* OMAP5430.MPU temperature definitions */
126/* bandgap clock limits */
127#define OMAP5430_MPU_MAX_FREQ				1500000
128#define OMAP5430_MPU_MIN_FREQ				1000000
129/* interrupts thresholds */
130#define OMAP5430_MPU_TSHUT_HOT				915
131#define OMAP5430_MPU_TSHUT_COLD				900
132#define OMAP5430_MPU_T_HOT				800
133#define OMAP5430_MPU_T_COLD				795
134
135/* OMAP5430.CORE temperature definitions */
136/* bandgap clock limits */
137#define OMAP5430_CORE_MAX_FREQ				1500000
138#define OMAP5430_CORE_MIN_FREQ				1000000
139/* interrupts thresholds */
140#define OMAP5430_CORE_TSHUT_HOT				915
141#define OMAP5430_CORE_TSHUT_COLD			900
142#define OMAP5430_CORE_T_HOT				800
143#define OMAP5430_CORE_T_COLD				795
144
145#endif /* __OMAP5XXX_BANDGAP_H */