Loading...
Note: File does not exist in v6.9.4.
1/***************************************************************************
2 * Copyright (C) 2006-2010 by Marin Mitov *
3 * mitov@issp.bas.bg *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20
21/* DT3155 header file */
22#ifndef _DT3155_H_
23#define _DT3155_H_
24
25#ifdef __KERNEL__
26
27#include <linux/pci.h>
28#include <linux/interrupt.h>
29
30#define DT3155_NAME "dt3155"
31#define DT3155_VER_MAJ 1
32#define DT3155_VER_MIN 1
33#define DT3155_VER_EXT 0
34#define DT3155_VERSION __stringify(DT3155_VER_MAJ) "." \
35 __stringify(DT3155_VER_MIN) "." \
36 __stringify(DT3155_VER_EXT)
37
38/* DT3155 Base Register offsets (memory mapped) */
39#define EVEN_DMA_START 0x00
40#define ODD_DMA_START 0x0C
41#define EVEN_DMA_STRIDE 0x18
42#define ODD_DMA_STRIDE 0x24
43#define EVEN_PIXEL_FMT 0x30
44#define ODD_PIXEL_FMT 0x34
45#define FIFO_TRIGER 0x38
46#define XFER_MODE 0x3C
47#define CSR1 0x40
48#define RETRY_WAIT_CNT 0x44
49#define INT_CSR 0x48
50#define EVEN_FLD_MASK 0x4C
51#define ODD_FLD_MASK 0x50
52#define MASK_LENGTH 0x54
53#define FIFO_FLAG_CNT 0x58
54#define IIC_CLK_DUR 0x5C
55#define IIC_CSR1 0x60
56#define IIC_CSR2 0x64
57
58/* DT3155 Internal Registers indexes (i2c/IIC mapped) */
59#define CSR2 0x10
60#define EVEN_CSR 0x11
61#define ODD_CSR 0x12
62#define CONFIG 0x13
63#define DT_ID 0x1F
64#define X_CLIP_START 0x20
65#define Y_CLIP_START 0x22
66#define X_CLIP_END 0x24
67#define Y_CLIP_END 0x26
68#define AD_ADDR 0x30
69#define AD_LUT 0x31
70#define AD_CMD 0x32
71#define DIG_OUT 0x40
72#define PM_LUT_ADDR 0x50
73#define PM_LUT_DATA 0x51
74
75/* AD command register values */
76#define AD_CMD_REG 0x00
77#define AD_POS_REF 0x01
78#define AD_NEG_REF 0x02
79
80/* CSR1 bit masks */
81#define CRPT_DIS 0x00004000
82#define FLD_CRPT_ODD 0x00000200
83#define FLD_CRPT_EVEN 0x00000100
84#define FIFO_EN 0x00000080
85#define SRST 0x00000040
86#define FLD_DN_ODD 0x00000020
87#define FLD_DN_EVEN 0x00000010
88/* These should not be used.
89 * Use CAP_CONT_ODD/EVEN instead
90#define CAP_SNGL_ODD 0x00000008
91#define CAP_SNGL_EVEN 0x00000004
92*/
93#define CAP_CONT_ODD 0x00000002
94#define CAP_CONT_EVEN 0x00000001
95
96/* INT_CSR bit masks */
97#define FLD_START_EN 0x00000400
98#define FLD_END_ODD_EN 0x00000200
99#define FLD_END_EVEN_EN 0x00000100
100#define FLD_START 0x00000004
101#define FLD_END_ODD 0x00000002
102#define FLD_END_EVEN 0x00000001
103
104/* IIC_CSR1 bit masks */
105#define DIRECT_ABORT 0x00000200
106
107/* IIC_CSR2 bit masks */
108#define NEW_CYCLE 0x01000000
109#define DIR_RD 0x00010000
110#define IIC_READ 0x01010000
111#define IIC_WRITE 0x01000000
112
113/* CSR2 bit masks */
114#define DISP_PASS 0x40
115#define BUSY_ODD 0x20
116#define BUSY_EVEN 0x10
117#define SYNC_PRESENT 0x08
118#define VT_50HZ 0x04
119#define SYNC_SNTL 0x02
120#define CHROM_FILT 0x01
121#define VT_60HZ 0x00
122
123/* CSR_EVEN/ODD bit masks */
124#define CSR_ERROR 0x04
125#define CSR_SNGL 0x02
126#define CSR_DONE 0x01
127
128/* CONFIG bit masks */
129#define PM_LUT_PGM 0x80
130#define PM_LUT_SEL 0x40
131#define CLIP_EN 0x20
132#define HSCALE_EN 0x10
133#define EXT_TRIG_UP 0x0C
134#define EXT_TRIG_DOWN 0x04
135#define ACQ_MODE_NEXT 0x02
136#define ACQ_MODE_ODD 0x01
137#define ACQ_MODE_EVEN 0x00
138
139/* AD_CMD bit masks */
140#define VIDEO_CNL_1 0x00
141#define VIDEO_CNL_2 0x40
142#define VIDEO_CNL_3 0x80
143#define VIDEO_CNL_4 0xC0
144#define SYNC_CNL_1 0x00
145#define SYNC_CNL_2 0x10
146#define SYNC_CNL_3 0x20
147#define SYNC_CNL_4 0x30
148#define SYNC_LVL_1 0x00
149#define SYNC_LVL_2 0x04
150#define SYNC_LVL_3 0x08
151#define SYNC_LVL_4 0x0C
152
153/* DT3155 identificator */
154#define DT3155_ID 0x20
155
156#ifdef CONFIG_DT3155_CCIR
157#define DMA_STRIDE 768
158#else
159#define DMA_STRIDE 640
160#endif
161
162/**
163 * struct dt3155_stats - statistics structure
164 *
165 * @free_bufs_empty: no free image buffers
166 * @corrupted_fields: corrupted fields
167 * @dma_map_failed: dma mapping failed
168 * @start_before_end: new started before old ended
169 */
170struct dt3155_stats {
171 int free_bufs_empty;
172 int corrupted_fields;
173 int dma_map_failed;
174 int start_before_end;
175};
176
177/* per board private data structure */
178/**
179 * struct dt3155_priv - private data structure
180 *
181 * @vdev: pointer to video_device structure
182 * @pdev: pointer to pci_dev structure
183 * @q pointer to vb2_queue structure
184 * @curr_buf: pointer to curren buffer
185 * @mux: mutex to protect the instance
186 * @irq_handler: irq handler for the driver
187 * @dmaq queue for dma buffers
188 * @lock spinlock for dma queue
189 * @field_count fields counter
190 * @stats: statistics structure
191 * @users open count
192 * @regs: local copy of mmio base register
193 * @csr2: local copy of csr2 register
194 * @config: local copy of config register
195 */
196struct dt3155_priv {
197 struct video_device *vdev;
198 struct pci_dev *pdev;
199 struct vb2_queue *q;
200 struct vb2_buffer *curr_buf;
201 struct mutex mux;
202 irq_handler_t irq_handler;
203 struct list_head dmaq;
204 spinlock_t lock;
205 unsigned int field_count;
206 struct dt3155_stats stats;
207 void *regs;
208 int users;
209 u8 csr2, config;
210};
211
212#endif /* __KERNEL__ */
213
214#endif /* _DT3155_H_ */