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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Microsemi/Microchip SoCs serial gpio driver
4 *
5 * Author: Lars Povlsen <lars.povlsen@microchip.com>
6 *
7 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
8 */
9
10#include <linux/bitfield.h>
11#include <linux/bits.h>
12#include <linux/clk.h>
13#include <linux/gpio/driver.h>
14#include <linux/io.h>
15#include <linux/mfd/ocelot.h>
16#include <linux/mod_devicetable.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/property.h>
20#include <linux/regmap.h>
21#include <linux/reset.h>
22#include <linux/spinlock.h>
23
24#include <linux/pinctrl/pinconf.h>
25#include <linux/pinctrl/pinmux.h>
26
27#include "core.h"
28#include "pinconf.h"
29
30#define SGPIO_BITS_PER_WORD 32
31#define SGPIO_MAX_BITS 4
32#define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */
33
34enum {
35 REG_INPUT_DATA,
36 REG_PORT_CONFIG,
37 REG_PORT_ENABLE,
38 REG_SIO_CONFIG,
39 REG_SIO_CLOCK,
40 REG_INT_POLARITY,
41 REG_INT_TRIGGER,
42 REG_INT_ACK,
43 REG_INT_ENABLE,
44 REG_INT_IDENT,
45 MAXREG
46};
47
48enum {
49 SGPIO_ARCH_LUTON,
50 SGPIO_ARCH_OCELOT,
51 SGPIO_ARCH_SPARX5,
52};
53
54enum {
55 SGPIO_FLAGS_HAS_IRQ = BIT(0),
56};
57
58struct sgpio_properties {
59 int arch;
60 int flags;
61 u8 regoff[MAXREG];
62};
63
64#define SGPIO_LUTON_AUTO_REPEAT BIT(5)
65#define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2)
66#define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0)
67#define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0)
68
69#define SGPIO_OCELOT_AUTO_REPEAT BIT(10)
70#define SGPIO_OCELOT_SINGLE_SHOT BIT(11)
71#define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7)
72#define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8)
73#define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12)
74
75#define SGPIO_SPARX5_AUTO_REPEAT BIT(6)
76#define SGPIO_SPARX5_SINGLE_SHOT BIT(7)
77#define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3)
78#define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8)
79#define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12)
80
81#define SGPIO_MASTER_INTR_ENA BIT(0)
82
83#define SGPIO_INT_TRG_LEVEL 0
84#define SGPIO_INT_TRG_EDGE 1
85#define SGPIO_INT_TRG_EDGE_FALL 2
86#define SGPIO_INT_TRG_EDGE_RISE 3
87
88#define SGPIO_TRG_LEVEL_HIGH 0
89#define SGPIO_TRG_LEVEL_LOW 1
90
91static const struct sgpio_properties properties_luton = {
92 .arch = SGPIO_ARCH_LUTON,
93 .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
94};
95
96static const struct sgpio_properties properties_ocelot = {
97 .arch = SGPIO_ARCH_OCELOT,
98 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
99};
100
101static const struct sgpio_properties properties_sparx5 = {
102 .arch = SGPIO_ARCH_SPARX5,
103 .flags = SGPIO_FLAGS_HAS_IRQ,
104 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05, 0x2a, 0x32, 0x3a, 0x3e, 0x42 },
105};
106
107static const char * const functions[] = { "gpio" };
108
109struct sgpio_bank {
110 struct sgpio_priv *priv;
111 bool is_input;
112 struct gpio_chip gpio;
113 struct pinctrl_desc pctl_desc;
114};
115
116struct sgpio_priv {
117 struct device *dev;
118 struct sgpio_bank in;
119 struct sgpio_bank out;
120 u32 bitcount;
121 u32 ports;
122 u32 clock;
123 struct regmap *regs;
124 const struct sgpio_properties *properties;
125 spinlock_t lock;
126 /* protects the config register and single shot mode */
127 struct mutex poll_lock;
128};
129
130struct sgpio_port_addr {
131 u8 port;
132 u8 bit;
133};
134
135static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin,
136 struct sgpio_port_addr *addr)
137{
138 addr->port = pin / priv->bitcount;
139 addr->bit = pin % priv->bitcount;
140}
141
142static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit)
143{
144 return bit + port * priv->bitcount;
145}
146
147static inline u32 sgpio_get_addr(struct sgpio_priv *priv, u32 rno, u32 off)
148{
149 return (priv->properties->regoff[rno] + off) *
150 regmap_get_reg_stride(priv->regs);
151}
152
153static u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off)
154{
155 u32 addr = sgpio_get_addr(priv, rno, off);
156 u32 val = 0;
157 int ret;
158
159 ret = regmap_read(priv->regs, addr, &val);
160 WARN_ONCE(ret, "error reading sgpio reg %d\n", ret);
161
162 return val;
163}
164
165static void sgpio_writel(struct sgpio_priv *priv,
166 u32 val, u32 rno, u32 off)
167{
168 u32 addr = sgpio_get_addr(priv, rno, off);
169 int ret;
170
171 ret = regmap_write(priv->regs, addr, val);
172 WARN_ONCE(ret, "error writing sgpio reg %d\n", ret);
173}
174
175static inline void sgpio_clrsetbits(struct sgpio_priv *priv,
176 u32 rno, u32 off, u32 clear, u32 set)
177{
178 u32 addr = sgpio_get_addr(priv, rno, off);
179 int ret;
180
181 ret = regmap_update_bits(priv->regs, addr, clear | set, set);
182 WARN_ONCE(ret, "error updating sgpio reg %d\n", ret);
183}
184
185static inline void sgpio_configure_bitstream(struct sgpio_priv *priv)
186{
187 int width = priv->bitcount - 1;
188 u32 clr, set;
189
190 switch (priv->properties->arch) {
191 case SGPIO_ARCH_LUTON:
192 clr = SGPIO_LUTON_PORT_WIDTH;
193 set = SGPIO_LUTON_AUTO_REPEAT |
194 FIELD_PREP(SGPIO_LUTON_PORT_WIDTH, width);
195 break;
196 case SGPIO_ARCH_OCELOT:
197 clr = SGPIO_OCELOT_PORT_WIDTH;
198 set = SGPIO_OCELOT_AUTO_REPEAT |
199 FIELD_PREP(SGPIO_OCELOT_PORT_WIDTH, width);
200 break;
201 case SGPIO_ARCH_SPARX5:
202 clr = SGPIO_SPARX5_PORT_WIDTH;
203 set = SGPIO_SPARX5_AUTO_REPEAT |
204 FIELD_PREP(SGPIO_SPARX5_PORT_WIDTH, width);
205 break;
206 default:
207 return;
208 }
209 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set);
210}
211
212static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq)
213{
214 u32 clr, set;
215
216 switch (priv->properties->arch) {
217 case SGPIO_ARCH_LUTON:
218 clr = SGPIO_LUTON_CLK_FREQ;
219 set = FIELD_PREP(SGPIO_LUTON_CLK_FREQ, clkfrq);
220 break;
221 case SGPIO_ARCH_OCELOT:
222 clr = SGPIO_OCELOT_CLK_FREQ;
223 set = FIELD_PREP(SGPIO_OCELOT_CLK_FREQ, clkfrq);
224 break;
225 case SGPIO_ARCH_SPARX5:
226 clr = SGPIO_SPARX5_CLK_FREQ;
227 set = FIELD_PREP(SGPIO_SPARX5_CLK_FREQ, clkfrq);
228 break;
229 default:
230 return;
231 }
232 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set);
233}
234
235static int sgpio_single_shot(struct sgpio_priv *priv)
236{
237 u32 addr = sgpio_get_addr(priv, REG_SIO_CONFIG, 0);
238 int ret, ret2;
239 u32 ctrl;
240 unsigned int single_shot;
241 unsigned int auto_repeat;
242
243 switch (priv->properties->arch) {
244 case SGPIO_ARCH_LUTON:
245 /* not supported for now */
246 return 0;
247 case SGPIO_ARCH_OCELOT:
248 single_shot = SGPIO_OCELOT_SINGLE_SHOT;
249 auto_repeat = SGPIO_OCELOT_AUTO_REPEAT;
250 break;
251 case SGPIO_ARCH_SPARX5:
252 single_shot = SGPIO_SPARX5_SINGLE_SHOT;
253 auto_repeat = SGPIO_SPARX5_AUTO_REPEAT;
254 break;
255 default:
256 return -EINVAL;
257 }
258
259 /*
260 * Trigger immediate burst. This only works when auto repeat is turned
261 * off. Otherwise, the single shot bit will never be cleared by the
262 * hardware. Measurements showed that an update might take as long as
263 * the burst gap. On a LAN9668 this is about 50ms for the largest
264 * setting.
265 * After the manual burst, reenable the auto repeat mode again.
266 */
267 mutex_lock(&priv->poll_lock);
268 ret = regmap_update_bits(priv->regs, addr, single_shot | auto_repeat,
269 single_shot);
270 if (ret)
271 goto out;
272
273 ret = regmap_read_poll_timeout(priv->regs, addr, ctrl,
274 !(ctrl & single_shot), 100, 60000);
275
276 /* reenable auto repeat mode even if there was an error */
277 ret2 = regmap_update_bits(priv->regs, addr, auto_repeat, auto_repeat);
278out:
279 mutex_unlock(&priv->poll_lock);
280
281 return ret ?: ret2;
282}
283
284static int sgpio_output_set(struct sgpio_priv *priv,
285 struct sgpio_port_addr *addr,
286 int value)
287{
288 unsigned int bit = SGPIO_SRC_BITS * addr->bit;
289 u32 reg = sgpio_get_addr(priv, REG_PORT_CONFIG, addr->port);
290 bool changed;
291 u32 clr, set;
292 int ret;
293
294 switch (priv->properties->arch) {
295 case SGPIO_ARCH_LUTON:
296 clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit));
297 set = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, value << bit);
298 break;
299 case SGPIO_ARCH_OCELOT:
300 clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit));
301 set = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, value << bit);
302 break;
303 case SGPIO_ARCH_SPARX5:
304 clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit));
305 set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit);
306 break;
307 default:
308 return -EINVAL;
309 }
310
311 ret = regmap_update_bits_check(priv->regs, reg, clr | set, set,
312 &changed);
313 if (ret)
314 return ret;
315
316 if (changed) {
317 ret = sgpio_single_shot(priv);
318 if (ret)
319 return ret;
320 }
321
322 return 0;
323}
324
325static int sgpio_output_get(struct sgpio_priv *priv,
326 struct sgpio_port_addr *addr)
327{
328 u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port);
329 unsigned int bit = SGPIO_SRC_BITS * addr->bit;
330
331 switch (priv->properties->arch) {
332 case SGPIO_ARCH_LUTON:
333 val = FIELD_GET(SGPIO_LUTON_BIT_SOURCE, portval);
334 break;
335 case SGPIO_ARCH_OCELOT:
336 val = FIELD_GET(SGPIO_OCELOT_BIT_SOURCE, portval);
337 break;
338 case SGPIO_ARCH_SPARX5:
339 val = FIELD_GET(SGPIO_SPARX5_BIT_SOURCE, portval);
340 break;
341 default:
342 val = 0;
343 break;
344 }
345 return !!(val & BIT(bit));
346}
347
348static int sgpio_input_get(struct sgpio_priv *priv,
349 struct sgpio_port_addr *addr)
350{
351 return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port));
352}
353
354static int sgpio_pinconf_get(struct pinctrl_dev *pctldev,
355 unsigned int pin, unsigned long *config)
356{
357 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
358 u32 param = pinconf_to_config_param(*config);
359 struct sgpio_priv *priv = bank->priv;
360 struct sgpio_port_addr addr;
361 int val;
362
363 sgpio_pin_to_addr(priv, pin, &addr);
364
365 switch (param) {
366 case PIN_CONFIG_INPUT_ENABLE:
367 val = bank->is_input;
368 break;
369
370 case PIN_CONFIG_OUTPUT_ENABLE:
371 val = !bank->is_input;
372 break;
373
374 case PIN_CONFIG_OUTPUT:
375 if (bank->is_input)
376 return -EINVAL;
377 val = sgpio_output_get(priv, &addr);
378 break;
379
380 default:
381 return -ENOTSUPP;
382 }
383
384 *config = pinconf_to_config_packed(param, val);
385
386 return 0;
387}
388
389static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
390 unsigned long *configs, unsigned int num_configs)
391{
392 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
393 struct sgpio_priv *priv = bank->priv;
394 struct sgpio_port_addr addr;
395 int cfg, err = 0;
396 u32 param, arg;
397
398 sgpio_pin_to_addr(priv, pin, &addr);
399
400 for (cfg = 0; cfg < num_configs; cfg++) {
401 param = pinconf_to_config_param(configs[cfg]);
402 arg = pinconf_to_config_argument(configs[cfg]);
403
404 switch (param) {
405 case PIN_CONFIG_OUTPUT:
406 if (bank->is_input)
407 return -EINVAL;
408 err = sgpio_output_set(priv, &addr, arg);
409 break;
410
411 default:
412 err = -ENOTSUPP;
413 }
414 }
415
416 return err;
417}
418
419static const struct pinconf_ops sgpio_confops = {
420 .is_generic = true,
421 .pin_config_get = sgpio_pinconf_get,
422 .pin_config_set = sgpio_pinconf_set,
423 .pin_config_config_dbg_show = pinconf_generic_dump_config,
424};
425
426static int sgpio_get_functions_count(struct pinctrl_dev *pctldev)
427{
428 return 1;
429}
430
431static const char *sgpio_get_function_name(struct pinctrl_dev *pctldev,
432 unsigned int function)
433{
434 return functions[0];
435}
436
437static int sgpio_get_function_groups(struct pinctrl_dev *pctldev,
438 unsigned int function,
439 const char *const **groups,
440 unsigned *const num_groups)
441{
442 *groups = functions;
443 *num_groups = ARRAY_SIZE(functions);
444
445 return 0;
446}
447
448static int sgpio_pinmux_set_mux(struct pinctrl_dev *pctldev,
449 unsigned int selector, unsigned int group)
450{
451 return 0;
452}
453
454static int sgpio_gpio_set_direction(struct pinctrl_dev *pctldev,
455 struct pinctrl_gpio_range *range,
456 unsigned int pin, bool input)
457{
458 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
459
460 return (input == bank->is_input) ? 0 : -EINVAL;
461}
462
463static int sgpio_gpio_request_enable(struct pinctrl_dev *pctldev,
464 struct pinctrl_gpio_range *range,
465 unsigned int offset)
466{
467 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
468 struct sgpio_priv *priv = bank->priv;
469 struct sgpio_port_addr addr;
470
471 sgpio_pin_to_addr(priv, offset, &addr);
472
473 if ((priv->ports & BIT(addr.port)) == 0) {
474 dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n",
475 addr.port, addr.bit);
476 return -EINVAL;
477 }
478
479 return 0;
480}
481
482static const struct pinmux_ops sgpio_pmx_ops = {
483 .get_functions_count = sgpio_get_functions_count,
484 .get_function_name = sgpio_get_function_name,
485 .get_function_groups = sgpio_get_function_groups,
486 .set_mux = sgpio_pinmux_set_mux,
487 .gpio_set_direction = sgpio_gpio_set_direction,
488 .gpio_request_enable = sgpio_gpio_request_enable,
489};
490
491static int sgpio_pctl_get_groups_count(struct pinctrl_dev *pctldev)
492{
493 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
494
495 return bank->pctl_desc.npins;
496}
497
498static const char *sgpio_pctl_get_group_name(struct pinctrl_dev *pctldev,
499 unsigned int group)
500{
501 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
502
503 return bank->pctl_desc.pins[group].name;
504}
505
506static int sgpio_pctl_get_group_pins(struct pinctrl_dev *pctldev,
507 unsigned int group,
508 const unsigned int **pins,
509 unsigned int *num_pins)
510{
511 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev);
512
513 *pins = &bank->pctl_desc.pins[group].number;
514 *num_pins = 1;
515
516 return 0;
517}
518
519static const struct pinctrl_ops sgpio_pctl_ops = {
520 .get_groups_count = sgpio_pctl_get_groups_count,
521 .get_group_name = sgpio_pctl_get_group_name,
522 .get_group_pins = sgpio_pctl_get_group_pins,
523 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
524 .dt_free_map = pinconf_generic_dt_free_map,
525};
526
527static int microchip_sgpio_direction_input(struct gpio_chip *gc, unsigned int gpio)
528{
529 struct sgpio_bank *bank = gpiochip_get_data(gc);
530
531 /* Fixed-position function */
532 return bank->is_input ? 0 : -EINVAL;
533}
534
535static int microchip_sgpio_direction_output(struct gpio_chip *gc,
536 unsigned int gpio, int value)
537{
538 struct sgpio_bank *bank = gpiochip_get_data(gc);
539 struct sgpio_priv *priv = bank->priv;
540 struct sgpio_port_addr addr;
541
542 /* Fixed-position function */
543 if (bank->is_input)
544 return -EINVAL;
545
546 sgpio_pin_to_addr(priv, gpio, &addr);
547
548 return sgpio_output_set(priv, &addr, value);
549}
550
551static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
552{
553 struct sgpio_bank *bank = gpiochip_get_data(gc);
554
555 return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
556}
557
558static void microchip_sgpio_set_value(struct gpio_chip *gc,
559 unsigned int gpio, int value)
560{
561 microchip_sgpio_direction_output(gc, gpio, value);
562}
563
564static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio)
565{
566 struct sgpio_bank *bank = gpiochip_get_data(gc);
567 struct sgpio_priv *priv = bank->priv;
568 struct sgpio_port_addr addr;
569
570 sgpio_pin_to_addr(priv, gpio, &addr);
571
572 return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr);
573}
574
575static int microchip_sgpio_of_xlate(struct gpio_chip *gc,
576 const struct of_phandle_args *gpiospec,
577 u32 *flags)
578{
579 struct sgpio_bank *bank = gpiochip_get_data(gc);
580 struct sgpio_priv *priv = bank->priv;
581 int pin;
582
583 /*
584 * Note that the SGIO pin is defined by *2* numbers, a port
585 * number between 0 and 31, and a bit index, 0 to 3.
586 */
587 if (gpiospec->args[0] > SGPIO_BITS_PER_WORD ||
588 gpiospec->args[1] > priv->bitcount)
589 return -EINVAL;
590
591 pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]);
592
593 if (pin > gc->ngpio)
594 return -EINVAL;
595
596 if (flags)
597 *flags = gpiospec->args[2];
598
599 return pin;
600}
601
602static int microchip_sgpio_get_ports(struct sgpio_priv *priv)
603{
604 const char *range_property_name = "microchip,sgpio-port-ranges";
605 struct device *dev = priv->dev;
606 u32 range_params[64];
607 int i, nranges, ret;
608
609 /* Calculate port mask */
610 nranges = device_property_count_u32(dev, range_property_name);
611 if (nranges < 2 || nranges % 2 || nranges > ARRAY_SIZE(range_params)) {
612 dev_err(dev, "%s port range: '%s' property\n",
613 nranges == -EINVAL ? "Missing" : "Invalid",
614 range_property_name);
615 return -EINVAL;
616 }
617
618 ret = device_property_read_u32_array(dev, range_property_name,
619 range_params, nranges);
620 if (ret) {
621 dev_err(dev, "failed to parse '%s' property: %d\n",
622 range_property_name, ret);
623 return ret;
624 }
625 for (i = 0; i < nranges; i += 2) {
626 int start, end;
627
628 start = range_params[i];
629 end = range_params[i + 1];
630 if (start > end || end >= SGPIO_BITS_PER_WORD) {
631 dev_err(dev, "Ill-formed port-range [%d:%d]\n",
632 start, end);
633 }
634 priv->ports |= GENMASK(end, start);
635 }
636
637 return 0;
638}
639
640static void microchip_sgpio_irq_settype(struct irq_data *data,
641 int type,
642 int polarity)
643{
644 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
645 struct sgpio_bank *bank = gpiochip_get_data(chip);
646 unsigned int gpio = irqd_to_hwirq(data);
647 struct sgpio_port_addr addr;
648 unsigned long flags;
649 u32 ena;
650
651 sgpio_pin_to_addr(bank->priv, gpio, &addr);
652
653 spin_lock_irqsave(&bank->priv->lock, flags);
654
655 /* Disable interrupt while changing type */
656 ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit);
657 sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit);
658
659 /* Type value spread over 2 registers sets: low, high bit */
660 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit,
661 BIT(addr.port), (!!(type & 0x1)) << addr.port);
662 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit,
663 BIT(addr.port), (!!(type & 0x2)) << addr.port);
664
665 if (type == SGPIO_INT_TRG_LEVEL)
666 sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit,
667 BIT(addr.port), polarity << addr.port);
668
669 /* Possibly re-enable interrupts */
670 sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit);
671
672 spin_unlock_irqrestore(&bank->priv->lock, flags);
673}
674
675static void microchip_sgpio_irq_setreg(struct irq_data *data,
676 int reg,
677 bool clear)
678{
679 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
680 struct sgpio_bank *bank = gpiochip_get_data(chip);
681 unsigned int gpio = irqd_to_hwirq(data);
682 struct sgpio_port_addr addr;
683
684 sgpio_pin_to_addr(bank->priv, gpio, &addr);
685
686 if (clear)
687 sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0);
688 else
689 sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port));
690}
691
692static void microchip_sgpio_irq_mask(struct irq_data *data)
693{
694 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
695
696 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true);
697 gpiochip_disable_irq(chip, data->hwirq);
698}
699
700static void microchip_sgpio_irq_unmask(struct irq_data *data)
701{
702 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
703
704 gpiochip_enable_irq(chip, data->hwirq);
705 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false);
706}
707
708static void microchip_sgpio_irq_ack(struct irq_data *data)
709{
710 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
711 struct sgpio_bank *bank = gpiochip_get_data(chip);
712 unsigned int gpio = irqd_to_hwirq(data);
713 struct sgpio_port_addr addr;
714
715 sgpio_pin_to_addr(bank->priv, gpio, &addr);
716
717 sgpio_writel(bank->priv, BIT(addr.port), REG_INT_ACK, addr.bit);
718}
719
720static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type)
721{
722 switch (type) {
723 case IRQ_TYPE_EDGE_BOTH:
724 irq_set_handler_locked(data, handle_edge_irq);
725 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE, 0);
726 break;
727 case IRQ_TYPE_EDGE_RISING:
728 irq_set_handler_locked(data, handle_edge_irq);
729 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_RISE, 0);
730 break;
731 case IRQ_TYPE_EDGE_FALLING:
732 irq_set_handler_locked(data, handle_edge_irq);
733 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_FALL, 0);
734 break;
735 case IRQ_TYPE_LEVEL_HIGH:
736 irq_set_handler_locked(data, handle_level_irq);
737 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_HIGH);
738 break;
739 case IRQ_TYPE_LEVEL_LOW:
740 irq_set_handler_locked(data, handle_level_irq);
741 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_LOW);
742 break;
743 default:
744 return -EINVAL;
745 }
746
747 return 0;
748}
749
750static const struct irq_chip microchip_sgpio_irqchip = {
751 .name = "gpio",
752 .irq_mask = microchip_sgpio_irq_mask,
753 .irq_ack = microchip_sgpio_irq_ack,
754 .irq_unmask = microchip_sgpio_irq_unmask,
755 .irq_set_type = microchip_sgpio_irq_set_type,
756 .flags = IRQCHIP_IMMUTABLE,
757 GPIOCHIP_IRQ_RESOURCE_HELPERS,
758};
759
760static void sgpio_irq_handler(struct irq_desc *desc)
761{
762 struct irq_chip *parent_chip = irq_desc_get_chip(desc);
763 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
764 struct sgpio_bank *bank = gpiochip_get_data(chip);
765 struct sgpio_priv *priv = bank->priv;
766 int bit, port, gpio;
767 long val;
768
769 for (bit = 0; bit < priv->bitcount; bit++) {
770 val = sgpio_readl(priv, REG_INT_IDENT, bit);
771 if (!val)
772 continue;
773
774 chained_irq_enter(parent_chip, desc);
775
776 for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) {
777 gpio = sgpio_addr_to_pin(priv, port, bit);
778 generic_handle_domain_irq(chip->irq.domain, gpio);
779 }
780
781 chained_irq_exit(parent_chip, desc);
782 }
783}
784
785static int microchip_sgpio_register_bank(struct device *dev,
786 struct sgpio_priv *priv,
787 struct fwnode_handle *fwnode,
788 int bankno)
789{
790 struct pinctrl_pin_desc *pins;
791 struct pinctrl_desc *pctl_desc;
792 struct pinctrl_dev *pctldev;
793 struct sgpio_bank *bank;
794 struct gpio_chip *gc;
795 u32 ngpios;
796 int i, ret;
797
798 /* Get overall bank struct */
799 bank = (bankno == 0) ? &priv->in : &priv->out;
800 bank->priv = priv;
801
802 if (fwnode_property_read_u32(fwnode, "ngpios", &ngpios)) {
803 dev_info(dev, "failed to get number of gpios for bank%d\n",
804 bankno);
805 ngpios = 64;
806 }
807
808 priv->bitcount = ngpios / SGPIO_BITS_PER_WORD;
809 if (priv->bitcount > SGPIO_MAX_BITS) {
810 dev_err(dev, "Bit width exceeds maximum (%d)\n",
811 SGPIO_MAX_BITS);
812 return -EINVAL;
813 }
814
815 pctl_desc = &bank->pctl_desc;
816 pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput",
817 dev_name(dev),
818 bank->is_input ? "in" : "out");
819 if (!pctl_desc->name)
820 return -ENOMEM;
821
822 pctl_desc->pctlops = &sgpio_pctl_ops;
823 pctl_desc->pmxops = &sgpio_pmx_ops;
824 pctl_desc->confops = &sgpio_confops;
825 pctl_desc->owner = THIS_MODULE;
826
827 pins = devm_kzalloc(dev, sizeof(*pins)*ngpios, GFP_KERNEL);
828 if (!pins)
829 return -ENOMEM;
830
831 pctl_desc->npins = ngpios;
832 pctl_desc->pins = pins;
833
834 for (i = 0; i < ngpios; i++) {
835 struct sgpio_port_addr addr;
836
837 sgpio_pin_to_addr(priv, i, &addr);
838
839 pins[i].number = i;
840 pins[i].name = devm_kasprintf(dev, GFP_KERNEL,
841 "SGPIO_%c_p%db%d",
842 bank->is_input ? 'I' : 'O',
843 addr.port, addr.bit);
844 if (!pins[i].name)
845 return -ENOMEM;
846 }
847
848 pctldev = devm_pinctrl_register(dev, pctl_desc, bank);
849 if (IS_ERR(pctldev))
850 return dev_err_probe(dev, PTR_ERR(pctldev), "Failed to register pinctrl\n");
851
852 gc = &bank->gpio;
853 gc->label = pctl_desc->name;
854 gc->parent = dev;
855 gc->fwnode = fwnode;
856 gc->owner = THIS_MODULE;
857 gc->get_direction = microchip_sgpio_get_direction;
858 gc->direction_input = microchip_sgpio_direction_input;
859 gc->direction_output = microchip_sgpio_direction_output;
860 gc->get = microchip_sgpio_get_value;
861 gc->set = microchip_sgpio_set_value;
862 gc->request = gpiochip_generic_request;
863 gc->free = gpiochip_generic_free;
864 gc->of_xlate = microchip_sgpio_of_xlate;
865 gc->of_gpio_n_cells = 3;
866 gc->base = -1;
867 gc->ngpio = ngpios;
868 gc->can_sleep = !bank->is_input;
869
870 if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) {
871 int irq;
872
873 irq = fwnode_irq_get(fwnode, 0);
874 if (irq > 0) {
875 struct gpio_irq_chip *girq = &gc->irq;
876
877 gpio_irq_chip_set_chip(girq, µchip_sgpio_irqchip);
878 girq->parent_handler = sgpio_irq_handler;
879 girq->num_parents = 1;
880 girq->parents = devm_kcalloc(dev, 1,
881 sizeof(*girq->parents),
882 GFP_KERNEL);
883 if (!girq->parents)
884 return -ENOMEM;
885 girq->parents[0] = irq;
886 girq->default_type = IRQ_TYPE_NONE;
887 girq->handler = handle_bad_irq;
888
889 /* Disable all individual pins */
890 for (i = 0; i < SGPIO_MAX_BITS; i++)
891 sgpio_writel(priv, 0, REG_INT_ENABLE, i);
892 /* Master enable */
893 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, 0, SGPIO_MASTER_INTR_ENA);
894 }
895 }
896
897 ret = devm_gpiochip_add_data(dev, gc, bank);
898 if (ret)
899 dev_err(dev, "Failed to register: ret %d\n", ret);
900
901 return ret;
902}
903
904static int microchip_sgpio_probe(struct platform_device *pdev)
905{
906 int div_clock = 0, ret, port, i, nbanks;
907 struct device *dev = &pdev->dev;
908 struct fwnode_handle *fwnode;
909 struct reset_control *reset;
910 struct sgpio_priv *priv;
911 struct clk *clk;
912 u32 val;
913 struct regmap_config regmap_config = {
914 .reg_bits = 32,
915 .val_bits = 32,
916 .reg_stride = 4,
917 };
918
919 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
920 if (!priv)
921 return -ENOMEM;
922
923 priv->dev = dev;
924 spin_lock_init(&priv->lock);
925 mutex_init(&priv->poll_lock);
926
927 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
928 if (IS_ERR(reset))
929 return dev_err_probe(dev, PTR_ERR(reset), "Failed to get reset\n");
930 reset_control_reset(reset);
931
932 clk = devm_clk_get(dev, NULL);
933 if (IS_ERR(clk))
934 return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n");
935
936 div_clock = clk_get_rate(clk);
937 if (device_property_read_u32(dev, "bus-frequency", &priv->clock))
938 priv->clock = 12500000;
939 if (priv->clock == 0 || priv->clock > (div_clock / 2)) {
940 dev_err(dev, "Invalid frequency %d\n", priv->clock);
941 return -EINVAL;
942 }
943
944 priv->regs = ocelot_regmap_from_resource(pdev, 0, ®map_config);
945 if (IS_ERR(priv->regs))
946 return PTR_ERR(priv->regs);
947
948 priv->properties = device_get_match_data(dev);
949 priv->in.is_input = true;
950
951 /* Get rest of device properties */
952 ret = microchip_sgpio_get_ports(priv);
953 if (ret)
954 return ret;
955
956 nbanks = device_get_child_node_count(dev);
957 if (nbanks != 2) {
958 dev_err(dev, "Must have 2 banks (have %d)\n", nbanks);
959 return -EINVAL;
960 }
961
962 i = 0;
963 device_for_each_child_node(dev, fwnode) {
964 ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++);
965 if (ret) {
966 fwnode_handle_put(fwnode);
967 return ret;
968 }
969 }
970
971 if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) {
972 dev_err(dev, "Banks must have same GPIO count\n");
973 return -ERANGE;
974 }
975
976 sgpio_configure_bitstream(priv);
977
978 val = max(2U, div_clock / priv->clock);
979 sgpio_configure_clock(priv, val);
980
981 for (port = 0; port < SGPIO_BITS_PER_WORD; port++)
982 sgpio_writel(priv, 0, REG_PORT_CONFIG, port);
983 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0);
984
985 return 0;
986}
987
988static const struct of_device_id microchip_sgpio_gpio_of_match[] = {
989 {
990 .compatible = "microchip,sparx5-sgpio",
991 .data = &properties_sparx5,
992 }, {
993 .compatible = "mscc,luton-sgpio",
994 .data = &properties_luton,
995 }, {
996 .compatible = "mscc,ocelot-sgpio",
997 .data = &properties_ocelot,
998 }, {
999 /* sentinel */
1000 }
1001};
1002MODULE_DEVICE_TABLE(of, microchip_sgpio_gpio_of_match);
1003
1004static struct platform_driver microchip_sgpio_pinctrl_driver = {
1005 .driver = {
1006 .name = "pinctrl-microchip-sgpio",
1007 .of_match_table = microchip_sgpio_gpio_of_match,
1008 .suppress_bind_attrs = true,
1009 },
1010 .probe = microchip_sgpio_probe,
1011};
1012module_platform_driver(microchip_sgpio_pinctrl_driver);
1013
1014MODULE_DESCRIPTION("Microchip SGPIO Pinctrl Driver");
1015MODULE_LICENSE("GPL");