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1// SPDX-License-Identifier: ISC
2/*
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
7 */
8
9#include <linux/module.h>
10#include <linux/firmware.h>
11#include <linux/of.h>
12#include <linux/property.h>
13#include <linux/dmi.h>
14#include <linux/ctype.h>
15#include <linux/pm_qos.h>
16#include <linux/nvmem-consumer.h>
17#include <asm/byteorder.h>
18
19#include "core.h"
20#include "mac.h"
21#include "htc.h"
22#include "hif.h"
23#include "wmi.h"
24#include "bmi.h"
25#include "debug.h"
26#include "htt.h"
27#include "testmode.h"
28#include "wmi-ops.h"
29#include "coredump.h"
30
31unsigned int ath10k_debug_mask;
32EXPORT_SYMBOL(ath10k_debug_mask);
33
34static unsigned int ath10k_cryptmode_param;
35static bool uart_print;
36static bool skip_otp;
37static bool fw_diag_log;
38
39/* frame mode values are mapped as per enum ath10k_hw_txrx_mode */
40unsigned int ath10k_frame_mode = ATH10K_HW_TXRX_NATIVE_WIFI;
41
42unsigned long ath10k_coredump_mask = BIT(ATH10K_FW_CRASH_DUMP_REGISTERS) |
43 BIT(ATH10K_FW_CRASH_DUMP_CE_DATA);
44
45/* FIXME: most of these should be readonly */
46module_param_named(debug_mask, ath10k_debug_mask, uint, 0644);
47module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644);
48module_param(uart_print, bool, 0644);
49module_param(skip_otp, bool, 0644);
50module_param(fw_diag_log, bool, 0644);
51module_param_named(frame_mode, ath10k_frame_mode, uint, 0644);
52module_param_named(coredump_mask, ath10k_coredump_mask, ulong, 0444);
53
54MODULE_PARM_DESC(debug_mask, "Debugging mask");
55MODULE_PARM_DESC(uart_print, "Uart target debugging");
56MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode");
57MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
58MODULE_PARM_DESC(frame_mode,
59 "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)");
60MODULE_PARM_DESC(coredump_mask, "Bitfield of what to include in firmware crash file");
61MODULE_PARM_DESC(fw_diag_log, "Diag based fw log debugging");
62
63static const struct ath10k_hw_params ath10k_hw_params_list[] = {
64 {
65 .id = QCA988X_HW_2_0_VERSION,
66 .dev_id = QCA988X_2_0_DEVICE_ID,
67 .bus = ATH10K_BUS_PCI,
68 .name = "qca988x hw2.0",
69 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
70 .uart_pin = 7,
71 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
72 .otp_exe_param = 0,
73 .channel_counters_freq_hz = 88000,
74 .max_probe_resp_desc_thres = 0,
75 .cal_data_len = 2116,
76 .fw = {
77 .dir = QCA988X_HW_2_0_FW_DIR,
78 .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
79 .board_size = QCA988X_BOARD_DATA_SZ,
80 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
81 },
82 .rx_desc_ops = &qca988x_rx_desc_ops,
83 .hw_ops = &qca988x_ops,
84 .decap_align_bytes = 4,
85 .spectral_bin_discard = 0,
86 .spectral_bin_offset = 0,
87 .vht160_mcs_rx_highest = 0,
88 .vht160_mcs_tx_highest = 0,
89 .n_cipher_suites = 8,
90 .ast_skid_limit = 0x10,
91 .num_wds_entries = 0x20,
92 .target_64bit = false,
93 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
94 .shadow_reg_support = false,
95 .rri_on_ddr = false,
96 .hw_filter_reset_required = true,
97 .fw_diag_ce_download = false,
98 .credit_size_workaround = false,
99 .tx_stats_over_pktlog = true,
100 .dynamic_sar_support = false,
101 .hw_restart_disconnect = false,
102 .use_fw_tx_credits = true,
103 .delay_unmap_buffer = false,
104 .mcast_frame_registration = false,
105 },
106 {
107 .id = QCA988X_HW_2_0_VERSION,
108 .dev_id = QCA988X_2_0_DEVICE_ID_UBNT,
109 .name = "qca988x hw2.0 ubiquiti",
110 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
111 .uart_pin = 7,
112 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
113 .otp_exe_param = 0,
114 .channel_counters_freq_hz = 88000,
115 .max_probe_resp_desc_thres = 0,
116 .cal_data_len = 2116,
117 .fw = {
118 .dir = QCA988X_HW_2_0_FW_DIR,
119 .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
120 .board_size = QCA988X_BOARD_DATA_SZ,
121 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
122 },
123 .rx_desc_ops = &qca988x_rx_desc_ops,
124 .hw_ops = &qca988x_ops,
125 .decap_align_bytes = 4,
126 .spectral_bin_discard = 0,
127 .spectral_bin_offset = 0,
128 .vht160_mcs_rx_highest = 0,
129 .vht160_mcs_tx_highest = 0,
130 .n_cipher_suites = 8,
131 .ast_skid_limit = 0x10,
132 .num_wds_entries = 0x20,
133 .target_64bit = false,
134 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
135 .shadow_reg_support = false,
136 .rri_on_ddr = false,
137 .hw_filter_reset_required = true,
138 .fw_diag_ce_download = false,
139 .credit_size_workaround = false,
140 .tx_stats_over_pktlog = true,
141 .dynamic_sar_support = false,
142 .hw_restart_disconnect = false,
143 .use_fw_tx_credits = true,
144 .delay_unmap_buffer = false,
145 .mcast_frame_registration = false,
146 },
147 {
148 .id = QCA9887_HW_1_0_VERSION,
149 .dev_id = QCA9887_1_0_DEVICE_ID,
150 .bus = ATH10K_BUS_PCI,
151 .name = "qca9887 hw1.0",
152 .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR,
153 .uart_pin = 7,
154 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
155 .otp_exe_param = 0,
156 .channel_counters_freq_hz = 88000,
157 .max_probe_resp_desc_thres = 0,
158 .cal_data_len = 2116,
159 .fw = {
160 .dir = QCA9887_HW_1_0_FW_DIR,
161 .board = QCA9887_HW_1_0_BOARD_DATA_FILE,
162 .board_size = QCA9887_BOARD_DATA_SZ,
163 .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ,
164 },
165 .rx_desc_ops = &qca988x_rx_desc_ops,
166 .hw_ops = &qca988x_ops,
167 .decap_align_bytes = 4,
168 .spectral_bin_discard = 0,
169 .spectral_bin_offset = 0,
170 .vht160_mcs_rx_highest = 0,
171 .vht160_mcs_tx_highest = 0,
172 .n_cipher_suites = 8,
173 .ast_skid_limit = 0x10,
174 .num_wds_entries = 0x20,
175 .target_64bit = false,
176 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
177 .shadow_reg_support = false,
178 .rri_on_ddr = false,
179 .hw_filter_reset_required = true,
180 .fw_diag_ce_download = false,
181 .credit_size_workaround = false,
182 .tx_stats_over_pktlog = false,
183 .dynamic_sar_support = false,
184 .hw_restart_disconnect = false,
185 .use_fw_tx_credits = true,
186 .delay_unmap_buffer = false,
187 .mcast_frame_registration = false,
188 },
189 {
190 .id = QCA6174_HW_3_2_VERSION,
191 .dev_id = QCA6174_3_2_DEVICE_ID,
192 .bus = ATH10K_BUS_SDIO,
193 .name = "qca6174 hw3.2 sdio",
194 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
195 .uart_pin = 19,
196 .otp_exe_param = 0,
197 .channel_counters_freq_hz = 88000,
198 .max_probe_resp_desc_thres = 0,
199 .cal_data_len = 0,
200 .fw = {
201 .dir = QCA6174_HW_3_0_FW_DIR,
202 .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
203 .board_size = QCA6174_BOARD_DATA_SZ,
204 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
205 },
206 .rx_desc_ops = &qca988x_rx_desc_ops,
207 .hw_ops = &qca6174_sdio_ops,
208 .hw_clk = qca6174_clk,
209 .target_cpu_freq = 176000000,
210 .decap_align_bytes = 4,
211 .n_cipher_suites = 8,
212 .num_peers = 10,
213 .ast_skid_limit = 0x10,
214 .num_wds_entries = 0x20,
215 .uart_pin_workaround = true,
216 .tx_stats_over_pktlog = false,
217 .credit_size_workaround = false,
218 .bmi_large_size_download = true,
219 .supports_peer_stats_info = true,
220 .dynamic_sar_support = true,
221 .hw_restart_disconnect = false,
222 .use_fw_tx_credits = true,
223 .delay_unmap_buffer = false,
224 .mcast_frame_registration = false,
225 },
226 {
227 .id = QCA6174_HW_2_1_VERSION,
228 .dev_id = QCA6164_2_1_DEVICE_ID,
229 .bus = ATH10K_BUS_PCI,
230 .name = "qca6164 hw2.1",
231 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
232 .uart_pin = 6,
233 .otp_exe_param = 0,
234 .channel_counters_freq_hz = 88000,
235 .max_probe_resp_desc_thres = 0,
236 .cal_data_len = 8124,
237 .fw = {
238 .dir = QCA6174_HW_2_1_FW_DIR,
239 .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
240 .board_size = QCA6174_BOARD_DATA_SZ,
241 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
242 },
243 .rx_desc_ops = &qca988x_rx_desc_ops,
244 .hw_ops = &qca988x_ops,
245 .decap_align_bytes = 4,
246 .spectral_bin_discard = 0,
247 .spectral_bin_offset = 0,
248 .vht160_mcs_rx_highest = 0,
249 .vht160_mcs_tx_highest = 0,
250 .n_cipher_suites = 8,
251 .ast_skid_limit = 0x10,
252 .num_wds_entries = 0x20,
253 .target_64bit = false,
254 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
255 .shadow_reg_support = false,
256 .rri_on_ddr = false,
257 .hw_filter_reset_required = true,
258 .fw_diag_ce_download = false,
259 .credit_size_workaround = false,
260 .tx_stats_over_pktlog = false,
261 .dynamic_sar_support = false,
262 .hw_restart_disconnect = false,
263 .use_fw_tx_credits = true,
264 .delay_unmap_buffer = false,
265 .mcast_frame_registration = false,
266 },
267 {
268 .id = QCA6174_HW_2_1_VERSION,
269 .dev_id = QCA6174_2_1_DEVICE_ID,
270 .bus = ATH10K_BUS_PCI,
271 .name = "qca6174 hw2.1",
272 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
273 .uart_pin = 6,
274 .otp_exe_param = 0,
275 .channel_counters_freq_hz = 88000,
276 .max_probe_resp_desc_thres = 0,
277 .cal_data_len = 8124,
278 .fw = {
279 .dir = QCA6174_HW_2_1_FW_DIR,
280 .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
281 .board_size = QCA6174_BOARD_DATA_SZ,
282 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
283 },
284 .rx_desc_ops = &qca988x_rx_desc_ops,
285 .hw_ops = &qca988x_ops,
286 .decap_align_bytes = 4,
287 .spectral_bin_discard = 0,
288 .spectral_bin_offset = 0,
289 .vht160_mcs_rx_highest = 0,
290 .vht160_mcs_tx_highest = 0,
291 .n_cipher_suites = 8,
292 .ast_skid_limit = 0x10,
293 .num_wds_entries = 0x20,
294 .target_64bit = false,
295 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
296 .shadow_reg_support = false,
297 .rri_on_ddr = false,
298 .hw_filter_reset_required = true,
299 .fw_diag_ce_download = false,
300 .credit_size_workaround = false,
301 .tx_stats_over_pktlog = false,
302 .dynamic_sar_support = false,
303 .hw_restart_disconnect = false,
304 .use_fw_tx_credits = true,
305 .delay_unmap_buffer = false,
306 .mcast_frame_registration = false,
307 },
308 {
309 .id = QCA6174_HW_3_0_VERSION,
310 .dev_id = QCA6174_2_1_DEVICE_ID,
311 .bus = ATH10K_BUS_PCI,
312 .name = "qca6174 hw3.0",
313 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
314 .uart_pin = 6,
315 .otp_exe_param = 0,
316 .channel_counters_freq_hz = 88000,
317 .max_probe_resp_desc_thres = 0,
318 .cal_data_len = 8124,
319 .fw = {
320 .dir = QCA6174_HW_3_0_FW_DIR,
321 .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
322 .board_size = QCA6174_BOARD_DATA_SZ,
323 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
324 },
325 .rx_desc_ops = &qca988x_rx_desc_ops,
326 .hw_ops = &qca988x_ops,
327 .decap_align_bytes = 4,
328 .spectral_bin_discard = 0,
329 .spectral_bin_offset = 0,
330 .vht160_mcs_rx_highest = 0,
331 .vht160_mcs_tx_highest = 0,
332 .n_cipher_suites = 8,
333 .ast_skid_limit = 0x10,
334 .num_wds_entries = 0x20,
335 .target_64bit = false,
336 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
337 .shadow_reg_support = false,
338 .rri_on_ddr = false,
339 .hw_filter_reset_required = true,
340 .fw_diag_ce_download = false,
341 .credit_size_workaround = false,
342 .tx_stats_over_pktlog = false,
343 .dynamic_sar_support = false,
344 .hw_restart_disconnect = false,
345 .use_fw_tx_credits = true,
346 .delay_unmap_buffer = false,
347 .mcast_frame_registration = false,
348 },
349 {
350 .id = QCA6174_HW_3_2_VERSION,
351 .dev_id = QCA6174_2_1_DEVICE_ID,
352 .bus = ATH10K_BUS_PCI,
353 .name = "qca6174 hw3.2",
354 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
355 .uart_pin = 6,
356 .otp_exe_param = 0,
357 .channel_counters_freq_hz = 88000,
358 .max_probe_resp_desc_thres = 0,
359 .cal_data_len = 8124,
360 .fw = {
361 /* uses same binaries as hw3.0 */
362 .dir = QCA6174_HW_3_0_FW_DIR,
363 .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
364 .board_size = QCA6174_BOARD_DATA_SZ,
365 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
366 },
367 .rx_desc_ops = &qca988x_rx_desc_ops,
368 .hw_ops = &qca6174_ops,
369 .hw_clk = qca6174_clk,
370 .target_cpu_freq = 176000000,
371 .decap_align_bytes = 4,
372 .spectral_bin_discard = 0,
373 .spectral_bin_offset = 0,
374 .vht160_mcs_rx_highest = 0,
375 .vht160_mcs_tx_highest = 0,
376 .n_cipher_suites = 8,
377 .ast_skid_limit = 0x10,
378 .num_wds_entries = 0x20,
379 .target_64bit = false,
380 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
381 .shadow_reg_support = false,
382 .rri_on_ddr = false,
383 .hw_filter_reset_required = true,
384 .fw_diag_ce_download = true,
385 .credit_size_workaround = false,
386 .tx_stats_over_pktlog = false,
387 .supports_peer_stats_info = true,
388 .dynamic_sar_support = true,
389 .hw_restart_disconnect = false,
390 .use_fw_tx_credits = true,
391 .delay_unmap_buffer = false,
392 .mcast_frame_registration = true,
393 },
394 {
395 .id = QCA99X0_HW_2_0_DEV_VERSION,
396 .dev_id = QCA99X0_2_0_DEVICE_ID,
397 .bus = ATH10K_BUS_PCI,
398 .name = "qca99x0 hw2.0",
399 .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
400 .uart_pin = 7,
401 .otp_exe_param = 0x00000700,
402 .continuous_frag_desc = true,
403 .cck_rate_map_rev2 = true,
404 .channel_counters_freq_hz = 150000,
405 .max_probe_resp_desc_thres = 24,
406 .tx_chain_mask = 0xf,
407 .rx_chain_mask = 0xf,
408 .max_spatial_stream = 4,
409 .cal_data_len = 12064,
410 .fw = {
411 .dir = QCA99X0_HW_2_0_FW_DIR,
412 .board = QCA99X0_HW_2_0_BOARD_DATA_FILE,
413 .board_size = QCA99X0_BOARD_DATA_SZ,
414 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
415 },
416 .sw_decrypt_mcast_mgmt = true,
417 .rx_desc_ops = &qca99x0_rx_desc_ops,
418 .hw_ops = &qca99x0_ops,
419 .decap_align_bytes = 1,
420 .spectral_bin_discard = 4,
421 .spectral_bin_offset = 0,
422 .vht160_mcs_rx_highest = 0,
423 .vht160_mcs_tx_highest = 0,
424 .n_cipher_suites = 11,
425 .ast_skid_limit = 0x10,
426 .num_wds_entries = 0x20,
427 .target_64bit = false,
428 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
429 .shadow_reg_support = false,
430 .rri_on_ddr = false,
431 .hw_filter_reset_required = true,
432 .fw_diag_ce_download = false,
433 .credit_size_workaround = false,
434 .tx_stats_over_pktlog = false,
435 .dynamic_sar_support = false,
436 .hw_restart_disconnect = false,
437 .use_fw_tx_credits = true,
438 .delay_unmap_buffer = false,
439 .mcast_frame_registration = false,
440 },
441 {
442 .id = QCA9984_HW_1_0_DEV_VERSION,
443 .dev_id = QCA9984_1_0_DEVICE_ID,
444 .bus = ATH10K_BUS_PCI,
445 .name = "qca9984/qca9994 hw1.0",
446 .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR,
447 .uart_pin = 7,
448 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
449 .otp_exe_param = 0x00000700,
450 .continuous_frag_desc = true,
451 .cck_rate_map_rev2 = true,
452 .channel_counters_freq_hz = 150000,
453 .max_probe_resp_desc_thres = 24,
454 .tx_chain_mask = 0xf,
455 .rx_chain_mask = 0xf,
456 .max_spatial_stream = 4,
457 .cal_data_len = 12064,
458 .fw = {
459 .dir = QCA9984_HW_1_0_FW_DIR,
460 .board = QCA9984_HW_1_0_BOARD_DATA_FILE,
461 .eboard = QCA9984_HW_1_0_EBOARD_DATA_FILE,
462 .board_size = QCA99X0_BOARD_DATA_SZ,
463 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
464 .ext_board_size = QCA99X0_EXT_BOARD_DATA_SZ,
465 },
466 .sw_decrypt_mcast_mgmt = true,
467 .rx_desc_ops = &qca99x0_rx_desc_ops,
468 .hw_ops = &qca99x0_ops,
469 .decap_align_bytes = 1,
470 .spectral_bin_discard = 12,
471 .spectral_bin_offset = 8,
472
473 /* Can do only 2x2 VHT160 or 80+80. 1560Mbps is 4x4 80Mhz
474 * or 2x2 160Mhz, long-guard-interval.
475 */
476 .vht160_mcs_rx_highest = 1560,
477 .vht160_mcs_tx_highest = 1560,
478 .n_cipher_suites = 11,
479 .ast_skid_limit = 0x10,
480 .num_wds_entries = 0x20,
481 .target_64bit = false,
482 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
483 .shadow_reg_support = false,
484 .rri_on_ddr = false,
485 .hw_filter_reset_required = true,
486 .fw_diag_ce_download = false,
487 .credit_size_workaround = false,
488 .tx_stats_over_pktlog = false,
489 .dynamic_sar_support = false,
490 .hw_restart_disconnect = false,
491 .use_fw_tx_credits = true,
492 .delay_unmap_buffer = false,
493 .mcast_frame_registration = false,
494 },
495 {
496 .id = QCA9888_HW_2_0_DEV_VERSION,
497 .dev_id = QCA9888_2_0_DEVICE_ID,
498 .bus = ATH10K_BUS_PCI,
499 .name = "qca9888 hw2.0",
500 .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR,
501 .uart_pin = 7,
502 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
503 .otp_exe_param = 0x00000700,
504 .continuous_frag_desc = true,
505 .channel_counters_freq_hz = 150000,
506 .max_probe_resp_desc_thres = 24,
507 .tx_chain_mask = 3,
508 .rx_chain_mask = 3,
509 .max_spatial_stream = 2,
510 .cal_data_len = 12064,
511 .fw = {
512 .dir = QCA9888_HW_2_0_FW_DIR,
513 .board = QCA9888_HW_2_0_BOARD_DATA_FILE,
514 .board_size = QCA99X0_BOARD_DATA_SZ,
515 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
516 },
517 .sw_decrypt_mcast_mgmt = true,
518 .rx_desc_ops = &qca99x0_rx_desc_ops,
519 .hw_ops = &qca99x0_ops,
520 .decap_align_bytes = 1,
521 .spectral_bin_discard = 12,
522 .spectral_bin_offset = 8,
523
524 /* Can do only 1x1 VHT160 or 80+80. 780Mbps is 2x2 80Mhz or
525 * 1x1 160Mhz, long-guard-interval.
526 */
527 .vht160_mcs_rx_highest = 780,
528 .vht160_mcs_tx_highest = 780,
529 .n_cipher_suites = 11,
530 .ast_skid_limit = 0x10,
531 .num_wds_entries = 0x20,
532 .target_64bit = false,
533 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
534 .shadow_reg_support = false,
535 .rri_on_ddr = false,
536 .hw_filter_reset_required = true,
537 .fw_diag_ce_download = false,
538 .credit_size_workaround = false,
539 .tx_stats_over_pktlog = false,
540 .dynamic_sar_support = false,
541 .hw_restart_disconnect = false,
542 .use_fw_tx_credits = true,
543 .delay_unmap_buffer = false,
544 .mcast_frame_registration = false,
545 },
546 {
547 .id = QCA9377_HW_1_0_DEV_VERSION,
548 .dev_id = QCA9377_1_0_DEVICE_ID,
549 .bus = ATH10K_BUS_PCI,
550 .name = "qca9377 hw1.0",
551 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
552 .uart_pin = 6,
553 .otp_exe_param = 0,
554 .channel_counters_freq_hz = 88000,
555 .max_probe_resp_desc_thres = 0,
556 .cal_data_len = 8124,
557 .fw = {
558 .dir = QCA9377_HW_1_0_FW_DIR,
559 .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
560 .board_size = QCA9377_BOARD_DATA_SZ,
561 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
562 },
563 .rx_desc_ops = &qca988x_rx_desc_ops,
564 .hw_ops = &qca988x_ops,
565 .decap_align_bytes = 4,
566 .spectral_bin_discard = 0,
567 .spectral_bin_offset = 0,
568 .vht160_mcs_rx_highest = 0,
569 .vht160_mcs_tx_highest = 0,
570 .n_cipher_suites = 8,
571 .ast_skid_limit = 0x10,
572 .num_wds_entries = 0x20,
573 .target_64bit = false,
574 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
575 .shadow_reg_support = false,
576 .rri_on_ddr = false,
577 .hw_filter_reset_required = true,
578 .fw_diag_ce_download = false,
579 .credit_size_workaround = false,
580 .tx_stats_over_pktlog = false,
581 .dynamic_sar_support = false,
582 .hw_restart_disconnect = false,
583 .use_fw_tx_credits = true,
584 .delay_unmap_buffer = false,
585 .mcast_frame_registration = false,
586 },
587 {
588 .id = QCA9377_HW_1_1_DEV_VERSION,
589 .dev_id = QCA9377_1_0_DEVICE_ID,
590 .bus = ATH10K_BUS_PCI,
591 .name = "qca9377 hw1.1",
592 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
593 .uart_pin = 6,
594 .otp_exe_param = 0,
595 .channel_counters_freq_hz = 88000,
596 .max_probe_resp_desc_thres = 0,
597 .cal_data_len = 8124,
598 .fw = {
599 .dir = QCA9377_HW_1_0_FW_DIR,
600 .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
601 .board_size = QCA9377_BOARD_DATA_SZ,
602 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
603 },
604 .rx_desc_ops = &qca988x_rx_desc_ops,
605 .hw_ops = &qca6174_ops,
606 .hw_clk = qca6174_clk,
607 .target_cpu_freq = 176000000,
608 .decap_align_bytes = 4,
609 .spectral_bin_discard = 0,
610 .spectral_bin_offset = 0,
611 .vht160_mcs_rx_highest = 0,
612 .vht160_mcs_tx_highest = 0,
613 .n_cipher_suites = 8,
614 .ast_skid_limit = 0x10,
615 .num_wds_entries = 0x20,
616 .target_64bit = false,
617 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
618 .shadow_reg_support = false,
619 .rri_on_ddr = false,
620 .hw_filter_reset_required = true,
621 .fw_diag_ce_download = true,
622 .credit_size_workaround = false,
623 .tx_stats_over_pktlog = false,
624 .dynamic_sar_support = false,
625 .hw_restart_disconnect = false,
626 .use_fw_tx_credits = true,
627 .delay_unmap_buffer = false,
628 .mcast_frame_registration = false,
629 },
630 {
631 .id = QCA9377_HW_1_1_DEV_VERSION,
632 .dev_id = QCA9377_1_0_DEVICE_ID,
633 .bus = ATH10K_BUS_SDIO,
634 .name = "qca9377 hw1.1 sdio",
635 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
636 .uart_pin = 19,
637 .otp_exe_param = 0,
638 .channel_counters_freq_hz = 88000,
639 .max_probe_resp_desc_thres = 0,
640 .cal_data_len = 8124,
641 .fw = {
642 .dir = QCA9377_HW_1_0_FW_DIR,
643 .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
644 .board_size = QCA9377_BOARD_DATA_SZ,
645 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
646 },
647 .rx_desc_ops = &qca988x_rx_desc_ops,
648 .hw_ops = &qca6174_ops,
649 .hw_clk = qca6174_clk,
650 .target_cpu_freq = 176000000,
651 .decap_align_bytes = 4,
652 .n_cipher_suites = 8,
653 .num_peers = TARGET_QCA9377_HL_NUM_PEERS,
654 .ast_skid_limit = 0x10,
655 .num_wds_entries = 0x20,
656 .uart_pin_workaround = true,
657 .credit_size_workaround = true,
658 .dynamic_sar_support = false,
659 .hw_restart_disconnect = false,
660 .use_fw_tx_credits = true,
661 .delay_unmap_buffer = false,
662 .mcast_frame_registration = false,
663 },
664 {
665 .id = QCA4019_HW_1_0_DEV_VERSION,
666 .dev_id = 0,
667 .bus = ATH10K_BUS_AHB,
668 .name = "qca4019 hw1.0",
669 .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR,
670 .uart_pin = 7,
671 .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH,
672 .otp_exe_param = 0x0010000,
673 .continuous_frag_desc = true,
674 .cck_rate_map_rev2 = true,
675 .channel_counters_freq_hz = 125000,
676 .max_probe_resp_desc_thres = 24,
677 .tx_chain_mask = 0x3,
678 .rx_chain_mask = 0x3,
679 .max_spatial_stream = 2,
680 .cal_data_len = 12064,
681 .fw = {
682 .dir = QCA4019_HW_1_0_FW_DIR,
683 .board = QCA4019_HW_1_0_BOARD_DATA_FILE,
684 .board_size = QCA4019_BOARD_DATA_SZ,
685 .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ,
686 },
687 .sw_decrypt_mcast_mgmt = true,
688 .rx_desc_ops = &qca99x0_rx_desc_ops,
689 .hw_ops = &qca99x0_ops,
690 .decap_align_bytes = 1,
691 .spectral_bin_discard = 4,
692 .spectral_bin_offset = 0,
693 .vht160_mcs_rx_highest = 0,
694 .vht160_mcs_tx_highest = 0,
695 .n_cipher_suites = 11,
696 .ast_skid_limit = 0x10,
697 .num_wds_entries = 0x20,
698 .target_64bit = false,
699 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL,
700 .shadow_reg_support = false,
701 .rri_on_ddr = false,
702 .hw_filter_reset_required = true,
703 .fw_diag_ce_download = false,
704 .credit_size_workaround = false,
705 .tx_stats_over_pktlog = false,
706 .dynamic_sar_support = false,
707 .hw_restart_disconnect = false,
708 .use_fw_tx_credits = true,
709 .delay_unmap_buffer = false,
710 .mcast_frame_registration = false,
711 },
712 {
713 .id = WCN3990_HW_1_0_DEV_VERSION,
714 .dev_id = 0,
715 .bus = ATH10K_BUS_SNOC,
716 .name = "wcn3990 hw1.0",
717 .continuous_frag_desc = true,
718 .tx_chain_mask = 0x7,
719 .rx_chain_mask = 0x7,
720 .max_spatial_stream = 4,
721 .fw = {
722 .dir = WCN3990_HW_1_0_FW_DIR,
723 .board = WCN3990_HW_1_0_BOARD_DATA_FILE,
724 .board_size = WCN3990_BOARD_DATA_SZ,
725 .board_ext_size = WCN3990_BOARD_EXT_DATA_SZ,
726 },
727 .sw_decrypt_mcast_mgmt = true,
728 .rx_desc_ops = &wcn3990_rx_desc_ops,
729 .hw_ops = &wcn3990_ops,
730 .decap_align_bytes = 1,
731 .num_peers = TARGET_HL_TLV_NUM_PEERS,
732 .n_cipher_suites = 11,
733 .ast_skid_limit = TARGET_HL_TLV_AST_SKID_LIMIT,
734 .num_wds_entries = TARGET_HL_TLV_NUM_WDS_ENTRIES,
735 .target_64bit = true,
736 .rx_ring_fill_level = HTT_RX_RING_FILL_LEVEL_DUAL_MAC,
737 .shadow_reg_support = true,
738 .rri_on_ddr = true,
739 .hw_filter_reset_required = false,
740 .fw_diag_ce_download = false,
741 .credit_size_workaround = false,
742 .tx_stats_over_pktlog = false,
743 .dynamic_sar_support = true,
744 .hw_restart_disconnect = true,
745 .use_fw_tx_credits = false,
746 .delay_unmap_buffer = true,
747 .mcast_frame_registration = false,
748 },
749};
750
751static const char *const ath10k_core_fw_feature_str[] = {
752 [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx",
753 [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x",
754 [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx",
755 [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p",
756 [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2",
757 [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps",
758 [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan",
759 [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp",
760 [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad",
761 [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init",
762 [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode",
763 [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca",
764 [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp",
765 [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl",
766 [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param",
767 [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war",
768 [ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST] = "allows-mesh-bcast",
769 [ATH10K_FW_FEATURE_NO_PS] = "no-ps",
770 [ATH10K_FW_FEATURE_MGMT_TX_BY_REF] = "mgmt-tx-by-reference",
771 [ATH10K_FW_FEATURE_NON_BMI] = "non-bmi",
772 [ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL] = "single-chan-info-per-channel",
773 [ATH10K_FW_FEATURE_PEER_FIXED_RATE] = "peer-fixed-rate",
774 [ATH10K_FW_FEATURE_IRAM_RECOVERY] = "iram-recovery",
775};
776
777static unsigned int ath10k_core_get_fw_feature_str(char *buf,
778 size_t buf_len,
779 enum ath10k_fw_features feat)
780{
781 /* make sure that ath10k_core_fw_feature_str[] gets updated */
782 BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) !=
783 ATH10K_FW_FEATURE_COUNT);
784
785 if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) ||
786 WARN_ON(!ath10k_core_fw_feature_str[feat])) {
787 return scnprintf(buf, buf_len, "bit%d", feat);
788 }
789
790 return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]);
791}
792
793void ath10k_core_get_fw_features_str(struct ath10k *ar,
794 char *buf,
795 size_t buf_len)
796{
797 size_t len = 0;
798 int i;
799
800 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
801 if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) {
802 if (len > 0)
803 len += scnprintf(buf + len, buf_len - len, ",");
804
805 len += ath10k_core_get_fw_feature_str(buf + len,
806 buf_len - len,
807 i);
808 }
809 }
810}
811
812static void ath10k_send_suspend_complete(struct ath10k *ar)
813{
814 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n");
815
816 complete(&ar->target_suspend);
817}
818
819static int ath10k_init_sdio(struct ath10k *ar, enum ath10k_firmware_mode mode)
820{
821 bool mtu_workaround = ar->hw_params.credit_size_workaround;
822 int ret;
823 u32 param = 0;
824
825 ret = ath10k_bmi_write32(ar, hi_mbox_io_block_sz, 256);
826 if (ret)
827 return ret;
828
829 ret = ath10k_bmi_write32(ar, hi_mbox_isr_yield_limit, 99);
830 if (ret)
831 return ret;
832
833 ret = ath10k_bmi_read32(ar, hi_acs_flags, ¶m);
834 if (ret)
835 return ret;
836
837 param |= HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET;
838
839 if (mode == ATH10K_FIRMWARE_MODE_NORMAL && !mtu_workaround)
840 param |= HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
841 else
842 param &= ~HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE;
843
844 if (mode == ATH10K_FIRMWARE_MODE_UTF)
845 param &= ~HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET;
846 else
847 param |= HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET;
848
849 ret = ath10k_bmi_write32(ar, hi_acs_flags, param);
850 if (ret)
851 return ret;
852
853 ret = ath10k_bmi_read32(ar, hi_option_flag2, ¶m);
854 if (ret)
855 return ret;
856
857 param |= HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST;
858
859 ret = ath10k_bmi_write32(ar, hi_option_flag2, param);
860 if (ret)
861 return ret;
862
863 return 0;
864}
865
866static int ath10k_init_configure_target(struct ath10k *ar)
867{
868 u32 param_host;
869 int ret;
870
871 /* tell target which HTC version it is used*/
872 ret = ath10k_bmi_write32(ar, hi_app_host_interest,
873 HTC_PROTOCOL_VERSION);
874 if (ret) {
875 ath10k_err(ar, "settings HTC version failed\n");
876 return ret;
877 }
878
879 /* set the firmware mode to STA/IBSS/AP */
880 ret = ath10k_bmi_read32(ar, hi_option_flag, ¶m_host);
881 if (ret) {
882 ath10k_err(ar, "setting firmware mode (1/2) failed\n");
883 return ret;
884 }
885
886 /* TODO following parameters need to be re-visited. */
887 /* num_device */
888 param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT);
889 /* Firmware mode */
890 /* FIXME: Why FW_MODE_AP ??.*/
891 param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT);
892 /* mac_addr_method */
893 param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
894 /* firmware_bridge */
895 param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
896 /* fwsubmode */
897 param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT);
898
899 ret = ath10k_bmi_write32(ar, hi_option_flag, param_host);
900 if (ret) {
901 ath10k_err(ar, "setting firmware mode (2/2) failed\n");
902 return ret;
903 }
904
905 /* We do all byte-swapping on the host */
906 ret = ath10k_bmi_write32(ar, hi_be, 0);
907 if (ret) {
908 ath10k_err(ar, "setting host CPU BE mode failed\n");
909 return ret;
910 }
911
912 /* FW descriptor/Data swap flags */
913 ret = ath10k_bmi_write32(ar, hi_fw_swap, 0);
914
915 if (ret) {
916 ath10k_err(ar, "setting FW data/desc swap flags failed\n");
917 return ret;
918 }
919
920 /* Some devices have a special sanity check that verifies the PCI
921 * Device ID is written to this host interest var. It is known to be
922 * required to boot QCA6164.
923 */
924 ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext,
925 ar->dev_id);
926 if (ret) {
927 ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret);
928 return ret;
929 }
930
931 return 0;
932}
933
934static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar,
935 const char *dir,
936 const char *file)
937{
938 char filename[100];
939 const struct firmware *fw;
940 int ret;
941
942 if (file == NULL)
943 return ERR_PTR(-ENOENT);
944
945 if (dir == NULL)
946 dir = ".";
947
948 snprintf(filename, sizeof(filename), "%s/%s", dir, file);
949 ret = firmware_request_nowarn(&fw, filename, ar->dev);
950 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot fw request '%s': %d\n",
951 filename, ret);
952
953 if (ret)
954 return ERR_PTR(ret);
955
956 return fw;
957}
958
959static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data,
960 size_t data_len)
961{
962 u32 board_data_size = ar->hw_params.fw.board_size;
963 u32 board_ext_data_size = ar->hw_params.fw.board_ext_size;
964 u32 board_ext_data_addr;
965 int ret;
966
967 ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr);
968 if (ret) {
969 ath10k_err(ar, "could not read board ext data addr (%d)\n",
970 ret);
971 return ret;
972 }
973
974 ath10k_dbg(ar, ATH10K_DBG_BOOT,
975 "boot push board extended data addr 0x%x\n",
976 board_ext_data_addr);
977
978 if (board_ext_data_addr == 0)
979 return 0;
980
981 if (data_len != (board_data_size + board_ext_data_size)) {
982 ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n",
983 data_len, board_data_size, board_ext_data_size);
984 return -EINVAL;
985 }
986
987 ret = ath10k_bmi_write_memory(ar, board_ext_data_addr,
988 data + board_data_size,
989 board_ext_data_size);
990 if (ret) {
991 ath10k_err(ar, "could not write board ext data (%d)\n", ret);
992 return ret;
993 }
994
995 ret = ath10k_bmi_write32(ar, hi_board_ext_data_config,
996 (board_ext_data_size << 16) | 1);
997 if (ret) {
998 ath10k_err(ar, "could not write board ext data bit (%d)\n",
999 ret);
1000 return ret;
1001 }
1002
1003 return 0;
1004}
1005
1006static int ath10k_core_get_board_id_from_otp(struct ath10k *ar)
1007{
1008 u32 result, address;
1009 u8 board_id, chip_id;
1010 bool ext_bid_support;
1011 int ret, bmi_board_id_param;
1012
1013 address = ar->hw_params.patch_load_addr;
1014
1015 if (!ar->normal_mode_fw.fw_file.otp_data ||
1016 !ar->normal_mode_fw.fw_file.otp_len) {
1017 ath10k_warn(ar,
1018 "failed to retrieve board id because of invalid otp\n");
1019 return -ENODATA;
1020 }
1021
1022 if (ar->id.bmi_ids_valid) {
1023 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1024 "boot already acquired valid otp board id,skip download, board_id %d chip_id %d\n",
1025 ar->id.bmi_board_id, ar->id.bmi_chip_id);
1026 goto skip_otp_download;
1027 }
1028
1029 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1030 "boot upload otp to 0x%x len %zd for board id\n",
1031 address, ar->normal_mode_fw.fw_file.otp_len);
1032
1033 ret = ath10k_bmi_fast_download(ar, address,
1034 ar->normal_mode_fw.fw_file.otp_data,
1035 ar->normal_mode_fw.fw_file.otp_len);
1036 if (ret) {
1037 ath10k_err(ar, "could not write otp for board id check: %d\n",
1038 ret);
1039 return ret;
1040 }
1041
1042 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||
1043 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE ||
1044 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM)
1045 bmi_board_id_param = BMI_PARAM_GET_FLASH_BOARD_ID;
1046 else
1047 bmi_board_id_param = BMI_PARAM_GET_EEPROM_BOARD_ID;
1048
1049 ret = ath10k_bmi_execute(ar, address, bmi_board_id_param, &result);
1050 if (ret) {
1051 ath10k_err(ar, "could not execute otp for board id check: %d\n",
1052 ret);
1053 return ret;
1054 }
1055
1056 board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP);
1057 chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP);
1058 ext_bid_support = (result & ATH10K_BMI_EXT_BOARD_ID_SUPPORT);
1059
1060 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1061 "boot get otp board id result 0x%08x board_id %d chip_id %d ext_bid_support %d\n",
1062 result, board_id, chip_id, ext_bid_support);
1063
1064 ar->id.ext_bid_supported = ext_bid_support;
1065
1066 if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0 ||
1067 (board_id == 0)) {
1068 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1069 "board id does not exist in otp, ignore it\n");
1070 return -EOPNOTSUPP;
1071 }
1072
1073 ar->id.bmi_ids_valid = true;
1074 ar->id.bmi_board_id = board_id;
1075 ar->id.bmi_chip_id = chip_id;
1076
1077skip_otp_download:
1078
1079 return 0;
1080}
1081
1082static void ath10k_core_check_bdfext(const struct dmi_header *hdr, void *data)
1083{
1084 struct ath10k *ar = data;
1085 const char *bdf_ext;
1086 const char *magic = ATH10K_SMBIOS_BDF_EXT_MAGIC;
1087 u8 bdf_enabled;
1088 int i;
1089
1090 if (hdr->type != ATH10K_SMBIOS_BDF_EXT_TYPE)
1091 return;
1092
1093 if (hdr->length != ATH10K_SMBIOS_BDF_EXT_LENGTH) {
1094 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1095 "wrong smbios bdf ext type length (%d).\n",
1096 hdr->length);
1097 return;
1098 }
1099
1100 bdf_enabled = *((u8 *)hdr + ATH10K_SMBIOS_BDF_EXT_OFFSET);
1101 if (!bdf_enabled) {
1102 ath10k_dbg(ar, ATH10K_DBG_BOOT, "bdf variant name not found.\n");
1103 return;
1104 }
1105
1106 /* Only one string exists (per spec) */
1107 bdf_ext = (char *)hdr + hdr->length;
1108
1109 if (memcmp(bdf_ext, magic, strlen(magic)) != 0) {
1110 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1111 "bdf variant magic does not match.\n");
1112 return;
1113 }
1114
1115 for (i = 0; i < strlen(bdf_ext); i++) {
1116 if (!isascii(bdf_ext[i]) || !isprint(bdf_ext[i])) {
1117 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1118 "bdf variant name contains non ascii chars.\n");
1119 return;
1120 }
1121 }
1122
1123 /* Copy extension name without magic suffix */
1124 if (strscpy(ar->id.bdf_ext, bdf_ext + strlen(magic),
1125 sizeof(ar->id.bdf_ext)) < 0) {
1126 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1127 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1128 bdf_ext);
1129 return;
1130 }
1131
1132 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1133 "found and validated bdf variant smbios_type 0x%x bdf %s\n",
1134 ATH10K_SMBIOS_BDF_EXT_TYPE, bdf_ext);
1135}
1136
1137static int ath10k_core_check_smbios(struct ath10k *ar)
1138{
1139 ar->id.bdf_ext[0] = '\0';
1140 dmi_walk(ath10k_core_check_bdfext, ar);
1141
1142 if (ar->id.bdf_ext[0] == '\0')
1143 return -ENODATA;
1144
1145 return 0;
1146}
1147
1148int ath10k_core_check_dt(struct ath10k *ar)
1149{
1150 struct device_node *node;
1151 const char *variant = NULL;
1152
1153 node = ar->dev->of_node;
1154 if (!node)
1155 return -ENOENT;
1156
1157 of_property_read_string(node, "qcom,ath10k-calibration-variant",
1158 &variant);
1159 if (!variant)
1160 return -ENODATA;
1161
1162 if (strscpy(ar->id.bdf_ext, variant, sizeof(ar->id.bdf_ext)) < 0)
1163 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1164 "bdf variant string is longer than the buffer can accommodate (variant: %s)\n",
1165 variant);
1166
1167 return 0;
1168}
1169EXPORT_SYMBOL(ath10k_core_check_dt);
1170
1171static int ath10k_download_fw(struct ath10k *ar)
1172{
1173 u32 address, data_len;
1174 const void *data;
1175 int ret;
1176 struct pm_qos_request latency_qos;
1177
1178 address = ar->hw_params.patch_load_addr;
1179
1180 data = ar->running_fw->fw_file.firmware_data;
1181 data_len = ar->running_fw->fw_file.firmware_len;
1182
1183 ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file);
1184 if (ret) {
1185 ath10k_err(ar, "failed to configure fw code swap: %d\n",
1186 ret);
1187 return ret;
1188 }
1189
1190 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1191 "boot uploading firmware image %pK len %d\n",
1192 data, data_len);
1193
1194 /* Check if device supports to download firmware via
1195 * diag copy engine. Downloading firmware via diag CE
1196 * greatly reduces the time to download firmware.
1197 */
1198 if (ar->hw_params.fw_diag_ce_download) {
1199 ret = ath10k_hw_diag_fast_download(ar, address,
1200 data, data_len);
1201 if (ret == 0)
1202 /* firmware upload via diag ce was successful */
1203 return 0;
1204
1205 ath10k_warn(ar,
1206 "failed to upload firmware via diag ce, trying BMI: %d",
1207 ret);
1208 }
1209
1210 memset(&latency_qos, 0, sizeof(latency_qos));
1211 cpu_latency_qos_add_request(&latency_qos, 0);
1212
1213 ret = ath10k_bmi_fast_download(ar, address, data, data_len);
1214
1215 cpu_latency_qos_remove_request(&latency_qos);
1216
1217 return ret;
1218}
1219
1220void ath10k_core_free_board_files(struct ath10k *ar)
1221{
1222 if (!IS_ERR(ar->normal_mode_fw.board))
1223 release_firmware(ar->normal_mode_fw.board);
1224
1225 if (!IS_ERR(ar->normal_mode_fw.ext_board))
1226 release_firmware(ar->normal_mode_fw.ext_board);
1227
1228 ar->normal_mode_fw.board = NULL;
1229 ar->normal_mode_fw.board_data = NULL;
1230 ar->normal_mode_fw.board_len = 0;
1231 ar->normal_mode_fw.ext_board = NULL;
1232 ar->normal_mode_fw.ext_board_data = NULL;
1233 ar->normal_mode_fw.ext_board_len = 0;
1234}
1235EXPORT_SYMBOL(ath10k_core_free_board_files);
1236
1237static void ath10k_core_free_firmware_files(struct ath10k *ar)
1238{
1239 if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware))
1240 release_firmware(ar->normal_mode_fw.fw_file.firmware);
1241
1242 if (!IS_ERR(ar->cal_file))
1243 release_firmware(ar->cal_file);
1244
1245 if (!IS_ERR(ar->pre_cal_file))
1246 release_firmware(ar->pre_cal_file);
1247
1248 ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file);
1249
1250 ar->normal_mode_fw.fw_file.otp_data = NULL;
1251 ar->normal_mode_fw.fw_file.otp_len = 0;
1252
1253 ar->normal_mode_fw.fw_file.firmware = NULL;
1254 ar->normal_mode_fw.fw_file.firmware_data = NULL;
1255 ar->normal_mode_fw.fw_file.firmware_len = 0;
1256
1257 ar->cal_file = NULL;
1258 ar->pre_cal_file = NULL;
1259}
1260
1261static int ath10k_fetch_cal_file(struct ath10k *ar)
1262{
1263 char filename[100];
1264
1265 /* pre-cal-<bus>-<id>.bin */
1266 scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin",
1267 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
1268
1269 ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
1270 if (!IS_ERR(ar->pre_cal_file))
1271 goto success;
1272
1273 /* cal-<bus>-<id>.bin */
1274 scnprintf(filename, sizeof(filename), "cal-%s-%s.bin",
1275 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
1276
1277 ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
1278 if (IS_ERR(ar->cal_file))
1279 /* calibration file is optional, don't print any warnings */
1280 return PTR_ERR(ar->cal_file);
1281success:
1282 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n",
1283 ATH10K_FW_DIR, filename);
1284
1285 return 0;
1286}
1287
1288static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar, int bd_ie_type)
1289{
1290 const struct firmware *fw;
1291 char boardname[100];
1292
1293 if (bd_ie_type == ATH10K_BD_IE_BOARD) {
1294 if (!ar->hw_params.fw.board) {
1295 ath10k_err(ar, "failed to find board file fw entry\n");
1296 return -EINVAL;
1297 }
1298
1299 scnprintf(boardname, sizeof(boardname), "board-%s-%s.bin",
1300 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
1301
1302 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
1303 ar->hw_params.fw.dir,
1304 boardname);
1305 if (IS_ERR(ar->normal_mode_fw.board)) {
1306 fw = ath10k_fetch_fw_file(ar,
1307 ar->hw_params.fw.dir,
1308 ar->hw_params.fw.board);
1309 ar->normal_mode_fw.board = fw;
1310 }
1311
1312 if (IS_ERR(ar->normal_mode_fw.board))
1313 return PTR_ERR(ar->normal_mode_fw.board);
1314
1315 ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data;
1316 ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size;
1317 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) {
1318 if (!ar->hw_params.fw.eboard) {
1319 ath10k_err(ar, "failed to find eboard file fw entry\n");
1320 return -EINVAL;
1321 }
1322
1323 fw = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir,
1324 ar->hw_params.fw.eboard);
1325 ar->normal_mode_fw.ext_board = fw;
1326 if (IS_ERR(ar->normal_mode_fw.ext_board))
1327 return PTR_ERR(ar->normal_mode_fw.ext_board);
1328
1329 ar->normal_mode_fw.ext_board_data = ar->normal_mode_fw.ext_board->data;
1330 ar->normal_mode_fw.ext_board_len = ar->normal_mode_fw.ext_board->size;
1331 }
1332
1333 return 0;
1334}
1335
1336static int ath10k_core_parse_bd_ie_board(struct ath10k *ar,
1337 const void *buf, size_t buf_len,
1338 const char *boardname,
1339 int bd_ie_type)
1340{
1341 const struct ath10k_fw_ie *hdr;
1342 bool name_match_found;
1343 int ret, board_ie_id;
1344 size_t board_ie_len;
1345 const void *board_ie_data;
1346
1347 name_match_found = false;
1348
1349 /* go through ATH10K_BD_IE_BOARD_ elements */
1350 while (buf_len > sizeof(struct ath10k_fw_ie)) {
1351 hdr = buf;
1352 board_ie_id = le32_to_cpu(hdr->id);
1353 board_ie_len = le32_to_cpu(hdr->len);
1354 board_ie_data = hdr->data;
1355
1356 buf_len -= sizeof(*hdr);
1357 buf += sizeof(*hdr);
1358
1359 if (buf_len < ALIGN(board_ie_len, 4)) {
1360 ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n",
1361 buf_len, ALIGN(board_ie_len, 4));
1362 ret = -EINVAL;
1363 goto out;
1364 }
1365
1366 switch (board_ie_id) {
1367 case ATH10K_BD_IE_BOARD_NAME:
1368 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "",
1369 board_ie_data, board_ie_len);
1370
1371 if (board_ie_len != strlen(boardname))
1372 break;
1373
1374 ret = memcmp(board_ie_data, boardname, strlen(boardname));
1375 if (ret)
1376 break;
1377
1378 name_match_found = true;
1379 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1380 "boot found match for name '%s'",
1381 boardname);
1382 break;
1383 case ATH10K_BD_IE_BOARD_DATA:
1384 if (!name_match_found)
1385 /* no match found */
1386 break;
1387
1388 if (bd_ie_type == ATH10K_BD_IE_BOARD) {
1389 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1390 "boot found board data for '%s'",
1391 boardname);
1392
1393 ar->normal_mode_fw.board_data = board_ie_data;
1394 ar->normal_mode_fw.board_len = board_ie_len;
1395 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) {
1396 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1397 "boot found eboard data for '%s'",
1398 boardname);
1399
1400 ar->normal_mode_fw.ext_board_data = board_ie_data;
1401 ar->normal_mode_fw.ext_board_len = board_ie_len;
1402 }
1403
1404 ret = 0;
1405 goto out;
1406 default:
1407 ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n",
1408 board_ie_id);
1409 break;
1410 }
1411
1412 /* jump over the padding */
1413 board_ie_len = ALIGN(board_ie_len, 4);
1414
1415 buf_len -= board_ie_len;
1416 buf += board_ie_len;
1417 }
1418
1419 /* no match found */
1420 ret = -ENOENT;
1421
1422out:
1423 return ret;
1424}
1425
1426static int ath10k_core_search_bd(struct ath10k *ar,
1427 const char *boardname,
1428 const u8 *data,
1429 size_t len)
1430{
1431 size_t ie_len;
1432 struct ath10k_fw_ie *hdr;
1433 int ret = -ENOENT, ie_id;
1434
1435 while (len > sizeof(struct ath10k_fw_ie)) {
1436 hdr = (struct ath10k_fw_ie *)data;
1437 ie_id = le32_to_cpu(hdr->id);
1438 ie_len = le32_to_cpu(hdr->len);
1439
1440 len -= sizeof(*hdr);
1441 data = hdr->data;
1442
1443 if (len < ALIGN(ie_len, 4)) {
1444 ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n",
1445 ie_id, ie_len, len);
1446 return -EINVAL;
1447 }
1448
1449 switch (ie_id) {
1450 case ATH10K_BD_IE_BOARD:
1451 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
1452 boardname,
1453 ATH10K_BD_IE_BOARD);
1454 if (ret == -ENOENT)
1455 /* no match found, continue */
1456 break;
1457
1458 /* either found or error, so stop searching */
1459 goto out;
1460 case ATH10K_BD_IE_BOARD_EXT:
1461 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
1462 boardname,
1463 ATH10K_BD_IE_BOARD_EXT);
1464 if (ret == -ENOENT)
1465 /* no match found, continue */
1466 break;
1467
1468 /* either found or error, so stop searching */
1469 goto out;
1470 }
1471
1472 /* jump over the padding */
1473 ie_len = ALIGN(ie_len, 4);
1474
1475 len -= ie_len;
1476 data += ie_len;
1477 }
1478
1479out:
1480 /* return result of parse_bd_ie_board() or -ENOENT */
1481 return ret;
1482}
1483
1484static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar,
1485 const char *boardname,
1486 const char *fallback_boardname1,
1487 const char *fallback_boardname2,
1488 const char *filename)
1489{
1490 size_t len, magic_len;
1491 const u8 *data;
1492 int ret;
1493
1494 /* Skip if already fetched during board data download */
1495 if (!ar->normal_mode_fw.board)
1496 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
1497 ar->hw_params.fw.dir,
1498 filename);
1499 if (IS_ERR(ar->normal_mode_fw.board))
1500 return PTR_ERR(ar->normal_mode_fw.board);
1501
1502 data = ar->normal_mode_fw.board->data;
1503 len = ar->normal_mode_fw.board->size;
1504
1505 /* magic has extra null byte padded */
1506 magic_len = strlen(ATH10K_BOARD_MAGIC) + 1;
1507 if (len < magic_len) {
1508 ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n",
1509 ar->hw_params.fw.dir, filename, len);
1510 ret = -EINVAL;
1511 goto err;
1512 }
1513
1514 if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) {
1515 ath10k_err(ar, "found invalid board magic\n");
1516 ret = -EINVAL;
1517 goto err;
1518 }
1519
1520 /* magic is padded to 4 bytes */
1521 magic_len = ALIGN(magic_len, 4);
1522 if (len < magic_len) {
1523 ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n",
1524 ar->hw_params.fw.dir, filename, len);
1525 ret = -EINVAL;
1526 goto err;
1527 }
1528
1529 data += magic_len;
1530 len -= magic_len;
1531
1532 /* attempt to find boardname in the IE list */
1533 ret = ath10k_core_search_bd(ar, boardname, data, len);
1534
1535 /* if we didn't find it and have a fallback name, try that */
1536 if (ret == -ENOENT && fallback_boardname1)
1537 ret = ath10k_core_search_bd(ar, fallback_boardname1, data, len);
1538
1539 if (ret == -ENOENT && fallback_boardname2)
1540 ret = ath10k_core_search_bd(ar, fallback_boardname2, data, len);
1541
1542 if (ret == -ENOENT) {
1543 ath10k_err(ar,
1544 "failed to fetch board data for %s from %s/%s\n",
1545 boardname, ar->hw_params.fw.dir, filename);
1546 ret = -ENODATA;
1547 }
1548
1549 if (ret)
1550 goto err;
1551
1552 return 0;
1553
1554err:
1555 ath10k_core_free_board_files(ar);
1556 return ret;
1557}
1558
1559static int ath10k_core_create_board_name(struct ath10k *ar, char *name,
1560 size_t name_len, bool with_variant,
1561 bool with_chip_id)
1562{
1563 /* strlen(',variant=') + strlen(ar->id.bdf_ext) */
1564 char variant[9 + ATH10K_SMBIOS_BDF_EXT_STR_LENGTH] = { 0 };
1565
1566 if (with_variant && ar->id.bdf_ext[0] != '\0')
1567 scnprintf(variant, sizeof(variant), ",variant=%s",
1568 ar->id.bdf_ext);
1569
1570 if (ar->id.bmi_ids_valid) {
1571 scnprintf(name, name_len,
1572 "bus=%s,bmi-chip-id=%d,bmi-board-id=%d%s",
1573 ath10k_bus_str(ar->hif.bus),
1574 ar->id.bmi_chip_id,
1575 ar->id.bmi_board_id, variant);
1576 goto out;
1577 }
1578
1579 if (ar->id.qmi_ids_valid) {
1580 if (with_chip_id)
1581 scnprintf(name, name_len,
1582 "bus=%s,qmi-board-id=%x,qmi-chip-id=%x%s",
1583 ath10k_bus_str(ar->hif.bus),
1584 ar->id.qmi_board_id, ar->id.qmi_chip_id,
1585 variant);
1586 else
1587 scnprintf(name, name_len,
1588 "bus=%s,qmi-board-id=%x",
1589 ath10k_bus_str(ar->hif.bus),
1590 ar->id.qmi_board_id);
1591 goto out;
1592 }
1593
1594 scnprintf(name, name_len,
1595 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x%s",
1596 ath10k_bus_str(ar->hif.bus),
1597 ar->id.vendor, ar->id.device,
1598 ar->id.subsystem_vendor, ar->id.subsystem_device, variant);
1599out:
1600 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name);
1601
1602 return 0;
1603}
1604
1605static int ath10k_core_create_eboard_name(struct ath10k *ar, char *name,
1606 size_t name_len)
1607{
1608 if (ar->id.bmi_ids_valid) {
1609 scnprintf(name, name_len,
1610 "bus=%s,bmi-chip-id=%d,bmi-eboard-id=%d",
1611 ath10k_bus_str(ar->hif.bus),
1612 ar->id.bmi_chip_id,
1613 ar->id.bmi_eboard_id);
1614
1615 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using eboard name '%s'\n", name);
1616 return 0;
1617 }
1618 /* Fallback if returned board id is zero */
1619 return -1;
1620}
1621
1622int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type)
1623{
1624 char boardname[100], fallback_boardname1[100], fallback_boardname2[100];
1625 int ret;
1626
1627 if (bd_ie_type == ATH10K_BD_IE_BOARD) {
1628 /* With variant and chip id */
1629 ret = ath10k_core_create_board_name(ar, boardname,
1630 sizeof(boardname), true,
1631 true);
1632 if (ret) {
1633 ath10k_err(ar, "failed to create board name: %d", ret);
1634 return ret;
1635 }
1636
1637 /* Without variant and only chip-id */
1638 ret = ath10k_core_create_board_name(ar, fallback_boardname1,
1639 sizeof(boardname), false,
1640 true);
1641 if (ret) {
1642 ath10k_err(ar, "failed to create 1st fallback board name: %d",
1643 ret);
1644 return ret;
1645 }
1646
1647 /* Without variant and without chip-id */
1648 ret = ath10k_core_create_board_name(ar, fallback_boardname2,
1649 sizeof(boardname), false,
1650 false);
1651 if (ret) {
1652 ath10k_err(ar, "failed to create 2nd fallback board name: %d",
1653 ret);
1654 return ret;
1655 }
1656 } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) {
1657 ret = ath10k_core_create_eboard_name(ar, boardname,
1658 sizeof(boardname));
1659 if (ret) {
1660 ath10k_err(ar, "fallback to eboard.bin since board id 0");
1661 goto fallback;
1662 }
1663 }
1664
1665 ar->bd_api = 2;
1666 ret = ath10k_core_fetch_board_data_api_n(ar, boardname,
1667 fallback_boardname1,
1668 fallback_boardname2,
1669 ATH10K_BOARD_API2_FILE);
1670 if (!ret)
1671 goto success;
1672
1673fallback:
1674 ar->bd_api = 1;
1675 ret = ath10k_core_fetch_board_data_api_1(ar, bd_ie_type);
1676 if (ret) {
1677 ath10k_err(ar, "failed to fetch board-2.bin or board.bin from %s\n",
1678 ar->hw_params.fw.dir);
1679 return ret;
1680 }
1681
1682success:
1683 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api);
1684 return 0;
1685}
1686EXPORT_SYMBOL(ath10k_core_fetch_board_file);
1687
1688static int ath10k_core_get_ext_board_id_from_otp(struct ath10k *ar)
1689{
1690 u32 result, address;
1691 u8 ext_board_id;
1692 int ret;
1693
1694 address = ar->hw_params.patch_load_addr;
1695
1696 if (!ar->normal_mode_fw.fw_file.otp_data ||
1697 !ar->normal_mode_fw.fw_file.otp_len) {
1698 ath10k_warn(ar,
1699 "failed to retrieve extended board id due to otp binary missing\n");
1700 return -ENODATA;
1701 }
1702
1703 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1704 "boot upload otp to 0x%x len %zd for ext board id\n",
1705 address, ar->normal_mode_fw.fw_file.otp_len);
1706
1707 ret = ath10k_bmi_fast_download(ar, address,
1708 ar->normal_mode_fw.fw_file.otp_data,
1709 ar->normal_mode_fw.fw_file.otp_len);
1710 if (ret) {
1711 ath10k_err(ar, "could not write otp for ext board id check: %d\n",
1712 ret);
1713 return ret;
1714 }
1715
1716 ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EXT_BOARD_ID, &result);
1717 if (ret) {
1718 ath10k_err(ar, "could not execute otp for ext board id check: %d\n",
1719 ret);
1720 return ret;
1721 }
1722
1723 if (!result) {
1724 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1725 "ext board id does not exist in otp, ignore it\n");
1726 return -EOPNOTSUPP;
1727 }
1728
1729 ext_board_id = result & ATH10K_BMI_EBOARD_ID_STATUS_MASK;
1730
1731 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1732 "boot get otp ext board id result 0x%08x ext_board_id %d\n",
1733 result, ext_board_id);
1734
1735 ar->id.bmi_eboard_id = ext_board_id;
1736
1737 return 0;
1738}
1739
1740static int ath10k_download_board_data(struct ath10k *ar, const void *data,
1741 size_t data_len)
1742{
1743 u32 board_data_size = ar->hw_params.fw.board_size;
1744 u32 eboard_data_size = ar->hw_params.fw.ext_board_size;
1745 u32 board_address;
1746 u32 ext_board_address;
1747 int ret;
1748
1749 ret = ath10k_push_board_ext_data(ar, data, data_len);
1750 if (ret) {
1751 ath10k_err(ar, "could not push board ext data (%d)\n", ret);
1752 goto exit;
1753 }
1754
1755 ret = ath10k_bmi_read32(ar, hi_board_data, &board_address);
1756 if (ret) {
1757 ath10k_err(ar, "could not read board data addr (%d)\n", ret);
1758 goto exit;
1759 }
1760
1761 ret = ath10k_bmi_write_memory(ar, board_address, data,
1762 min_t(u32, board_data_size,
1763 data_len));
1764 if (ret) {
1765 ath10k_err(ar, "could not write board data (%d)\n", ret);
1766 goto exit;
1767 }
1768
1769 ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1);
1770 if (ret) {
1771 ath10k_err(ar, "could not write board data bit (%d)\n", ret);
1772 goto exit;
1773 }
1774
1775 if (!ar->id.ext_bid_supported)
1776 goto exit;
1777
1778 /* Extended board data download */
1779 ret = ath10k_core_get_ext_board_id_from_otp(ar);
1780 if (ret == -EOPNOTSUPP) {
1781 /* Not fetching ext_board_data if ext board id is 0 */
1782 ath10k_dbg(ar, ATH10K_DBG_BOOT, "otp returned ext board id 0\n");
1783 return 0;
1784 } else if (ret) {
1785 ath10k_err(ar, "failed to get extended board id: %d\n", ret);
1786 goto exit;
1787 }
1788
1789 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD_EXT);
1790 if (ret)
1791 goto exit;
1792
1793 if (ar->normal_mode_fw.ext_board_data) {
1794 ext_board_address = board_address + EXT_BOARD_ADDRESS_OFFSET;
1795 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1796 "boot writing ext board data to addr 0x%x",
1797 ext_board_address);
1798 ret = ath10k_bmi_write_memory(ar, ext_board_address,
1799 ar->normal_mode_fw.ext_board_data,
1800 min_t(u32, eboard_data_size, data_len));
1801 if (ret)
1802 ath10k_err(ar, "failed to write ext board data: %d\n", ret);
1803 }
1804
1805exit:
1806 return ret;
1807}
1808
1809static int ath10k_download_and_run_otp(struct ath10k *ar)
1810{
1811 u32 result, address = ar->hw_params.patch_load_addr;
1812 u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param;
1813 int ret;
1814
1815 ret = ath10k_download_board_data(ar,
1816 ar->running_fw->board_data,
1817 ar->running_fw->board_len);
1818 if (ret) {
1819 ath10k_err(ar, "failed to download board data: %d\n", ret);
1820 return ret;
1821 }
1822
1823 /* OTP is optional */
1824
1825 if (!ar->running_fw->fw_file.otp_data ||
1826 !ar->running_fw->fw_file.otp_len) {
1827 ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %pK otp_len %zd)!\n",
1828 ar->running_fw->fw_file.otp_data,
1829 ar->running_fw->fw_file.otp_len);
1830 return 0;
1831 }
1832
1833 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n",
1834 address, ar->running_fw->fw_file.otp_len);
1835
1836 ret = ath10k_bmi_fast_download(ar, address,
1837 ar->running_fw->fw_file.otp_data,
1838 ar->running_fw->fw_file.otp_len);
1839 if (ret) {
1840 ath10k_err(ar, "could not write otp (%d)\n", ret);
1841 return ret;
1842 }
1843
1844 /* As of now pre-cal is valid for 10_4 variants */
1845 if (ar->cal_mode == ATH10K_PRE_CAL_MODE_DT ||
1846 ar->cal_mode == ATH10K_PRE_CAL_MODE_FILE ||
1847 ar->cal_mode == ATH10K_PRE_CAL_MODE_NVMEM)
1848 bmi_otp_exe_param = BMI_PARAM_FLASH_SECTION_ALL;
1849
1850 ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);
1851 if (ret) {
1852 ath10k_err(ar, "could not execute otp (%d)\n", ret);
1853 return ret;
1854 }
1855
1856 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result);
1857
1858 if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT,
1859 ar->running_fw->fw_file.fw_features)) &&
1860 result != 0) {
1861 ath10k_err(ar, "otp calibration failed: %d", result);
1862 return -EINVAL;
1863 }
1864
1865 return 0;
1866}
1867
1868static int ath10k_download_cal_file(struct ath10k *ar,
1869 const struct firmware *file)
1870{
1871 int ret;
1872
1873 if (!file)
1874 return -ENOENT;
1875
1876 if (IS_ERR(file))
1877 return PTR_ERR(file);
1878
1879 ret = ath10k_download_board_data(ar, file->data, file->size);
1880 if (ret) {
1881 ath10k_err(ar, "failed to download cal_file data: %d\n", ret);
1882 return ret;
1883 }
1884
1885 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n");
1886
1887 return 0;
1888}
1889
1890static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name)
1891{
1892 struct device_node *node;
1893 int data_len;
1894 void *data;
1895 int ret;
1896
1897 node = ar->dev->of_node;
1898 if (!node)
1899 /* Device Tree is optional, don't print any warnings if
1900 * there's no node for ath10k.
1901 */
1902 return -ENOENT;
1903
1904 if (!of_get_property(node, dt_name, &data_len)) {
1905 /* The calibration data node is optional */
1906 return -ENOENT;
1907 }
1908
1909 if (data_len != ar->hw_params.cal_data_len) {
1910 ath10k_warn(ar, "invalid calibration data length in DT: %d\n",
1911 data_len);
1912 ret = -EMSGSIZE;
1913 goto out;
1914 }
1915
1916 data = kmalloc(data_len, GFP_KERNEL);
1917 if (!data) {
1918 ret = -ENOMEM;
1919 goto out;
1920 }
1921
1922 ret = of_property_read_u8_array(node, dt_name, data, data_len);
1923 if (ret) {
1924 ath10k_warn(ar, "failed to read calibration data from DT: %d\n",
1925 ret);
1926 goto out_free;
1927 }
1928
1929 ret = ath10k_download_board_data(ar, data, data_len);
1930 if (ret) {
1931 ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n",
1932 ret);
1933 goto out_free;
1934 }
1935
1936 ret = 0;
1937
1938out_free:
1939 kfree(data);
1940
1941out:
1942 return ret;
1943}
1944
1945static int ath10k_download_cal_eeprom(struct ath10k *ar)
1946{
1947 size_t data_len;
1948 void *data = NULL;
1949 int ret;
1950
1951 ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len);
1952 if (ret) {
1953 if (ret != -EOPNOTSUPP)
1954 ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n",
1955 ret);
1956 goto out_free;
1957 }
1958
1959 ret = ath10k_download_board_data(ar, data, data_len);
1960 if (ret) {
1961 ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n",
1962 ret);
1963 goto out_free;
1964 }
1965
1966 ret = 0;
1967
1968out_free:
1969 kfree(data);
1970
1971 return ret;
1972}
1973
1974static int ath10k_download_cal_nvmem(struct ath10k *ar, const char *cell_name)
1975{
1976 struct nvmem_cell *cell;
1977 void *buf;
1978 size_t len;
1979 int ret;
1980
1981 cell = devm_nvmem_cell_get(ar->dev, cell_name);
1982 if (IS_ERR(cell)) {
1983 ret = PTR_ERR(cell);
1984 return ret;
1985 }
1986
1987 buf = nvmem_cell_read(cell, &len);
1988 if (IS_ERR(buf))
1989 return PTR_ERR(buf);
1990
1991 if (ar->hw_params.cal_data_len != len) {
1992 kfree(buf);
1993 ath10k_warn(ar, "invalid calibration data length in nvmem-cell '%s': %zu != %u\n",
1994 cell_name, len, ar->hw_params.cal_data_len);
1995 return -EMSGSIZE;
1996 }
1997
1998 ret = ath10k_download_board_data(ar, buf, len);
1999 kfree(buf);
2000 if (ret)
2001 ath10k_warn(ar, "failed to download calibration data from nvmem-cell '%s': %d\n",
2002 cell_name, ret);
2003
2004 return ret;
2005}
2006
2007int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
2008 struct ath10k_fw_file *fw_file)
2009{
2010 size_t magic_len, len, ie_len;
2011 int ie_id, i, index, bit, ret;
2012 struct ath10k_fw_ie *hdr;
2013 const u8 *data;
2014 __le32 *timestamp, *version;
2015
2016 /* first fetch the firmware file (firmware-*.bin) */
2017 fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir,
2018 name);
2019 if (IS_ERR(fw_file->firmware))
2020 return PTR_ERR(fw_file->firmware);
2021
2022 data = fw_file->firmware->data;
2023 len = fw_file->firmware->size;
2024
2025 /* magic also includes the null byte, check that as well */
2026 magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1;
2027
2028 if (len < magic_len) {
2029 ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n",
2030 ar->hw_params.fw.dir, name, len);
2031 ret = -EINVAL;
2032 goto err;
2033 }
2034
2035 if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) {
2036 ath10k_err(ar, "invalid firmware magic\n");
2037 ret = -EINVAL;
2038 goto err;
2039 }
2040
2041 /* jump over the padding */
2042 magic_len = ALIGN(magic_len, 4);
2043
2044 len -= magic_len;
2045 data += magic_len;
2046
2047 /* loop elements */
2048 while (len > sizeof(struct ath10k_fw_ie)) {
2049 hdr = (struct ath10k_fw_ie *)data;
2050
2051 ie_id = le32_to_cpu(hdr->id);
2052 ie_len = le32_to_cpu(hdr->len);
2053
2054 len -= sizeof(*hdr);
2055 data += sizeof(*hdr);
2056
2057 if (len < ie_len) {
2058 ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n",
2059 ie_id, len, ie_len);
2060 ret = -EINVAL;
2061 goto err;
2062 }
2063
2064 switch (ie_id) {
2065 case ATH10K_FW_IE_FW_VERSION:
2066 if (ie_len > sizeof(fw_file->fw_version) - 1)
2067 break;
2068
2069 memcpy(fw_file->fw_version, data, ie_len);
2070 fw_file->fw_version[ie_len] = '\0';
2071
2072 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2073 "found fw version %s\n",
2074 fw_file->fw_version);
2075 break;
2076 case ATH10K_FW_IE_TIMESTAMP:
2077 if (ie_len != sizeof(u32))
2078 break;
2079
2080 timestamp = (__le32 *)data;
2081
2082 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n",
2083 le32_to_cpup(timestamp));
2084 break;
2085 case ATH10K_FW_IE_FEATURES:
2086 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2087 "found firmware features ie (%zd B)\n",
2088 ie_len);
2089
2090 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
2091 index = i / 8;
2092 bit = i % 8;
2093
2094 if (index == ie_len)
2095 break;
2096
2097 if (data[index] & (1 << bit)) {
2098 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2099 "Enabling feature bit: %i\n",
2100 i);
2101 __set_bit(i, fw_file->fw_features);
2102 }
2103 }
2104
2105 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "",
2106 fw_file->fw_features,
2107 sizeof(fw_file->fw_features));
2108 break;
2109 case ATH10K_FW_IE_FW_IMAGE:
2110 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2111 "found fw image ie (%zd B)\n",
2112 ie_len);
2113
2114 fw_file->firmware_data = data;
2115 fw_file->firmware_len = ie_len;
2116
2117 break;
2118 case ATH10K_FW_IE_OTP_IMAGE:
2119 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2120 "found otp image ie (%zd B)\n",
2121 ie_len);
2122
2123 fw_file->otp_data = data;
2124 fw_file->otp_len = ie_len;
2125
2126 break;
2127 case ATH10K_FW_IE_WMI_OP_VERSION:
2128 if (ie_len != sizeof(u32))
2129 break;
2130
2131 version = (__le32 *)data;
2132
2133 fw_file->wmi_op_version = le32_to_cpup(version);
2134
2135 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n",
2136 fw_file->wmi_op_version);
2137 break;
2138 case ATH10K_FW_IE_HTT_OP_VERSION:
2139 if (ie_len != sizeof(u32))
2140 break;
2141
2142 version = (__le32 *)data;
2143
2144 fw_file->htt_op_version = le32_to_cpup(version);
2145
2146 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n",
2147 fw_file->htt_op_version);
2148 break;
2149 case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE:
2150 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2151 "found fw code swap image ie (%zd B)\n",
2152 ie_len);
2153 fw_file->codeswap_data = data;
2154 fw_file->codeswap_len = ie_len;
2155 break;
2156 default:
2157 ath10k_warn(ar, "Unknown FW IE: %u\n",
2158 le32_to_cpu(hdr->id));
2159 break;
2160 }
2161
2162 /* jump over the padding */
2163 ie_len = ALIGN(ie_len, 4);
2164
2165 len -= ie_len;
2166 data += ie_len;
2167 }
2168
2169 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI, fw_file->fw_features) &&
2170 (!fw_file->firmware_data || !fw_file->firmware_len)) {
2171 ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n",
2172 ar->hw_params.fw.dir, name);
2173 ret = -ENOMEDIUM;
2174 goto err;
2175 }
2176
2177 return 0;
2178
2179err:
2180 ath10k_core_free_firmware_files(ar);
2181 return ret;
2182}
2183
2184static void ath10k_core_get_fw_name(struct ath10k *ar, char *fw_name,
2185 size_t fw_name_len, int fw_api)
2186{
2187 switch (ar->hif.bus) {
2188 case ATH10K_BUS_SDIO:
2189 case ATH10K_BUS_USB:
2190 scnprintf(fw_name, fw_name_len, "%s-%s-%d.bin",
2191 ATH10K_FW_FILE_BASE, ath10k_bus_str(ar->hif.bus),
2192 fw_api);
2193 break;
2194 case ATH10K_BUS_PCI:
2195 case ATH10K_BUS_AHB:
2196 case ATH10K_BUS_SNOC:
2197 scnprintf(fw_name, fw_name_len, "%s-%d.bin",
2198 ATH10K_FW_FILE_BASE, fw_api);
2199 break;
2200 }
2201}
2202
2203static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
2204{
2205 int ret, i;
2206 char fw_name[100];
2207
2208 /* calibration file is optional, don't check for any errors */
2209 ath10k_fetch_cal_file(ar);
2210
2211 for (i = ATH10K_FW_API_MAX; i >= ATH10K_FW_API_MIN; i--) {
2212 ar->fw_api = i;
2213 ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n",
2214 ar->fw_api);
2215
2216 ath10k_core_get_fw_name(ar, fw_name, sizeof(fw_name), ar->fw_api);
2217 ret = ath10k_core_fetch_firmware_api_n(ar, fw_name,
2218 &ar->normal_mode_fw.fw_file);
2219 if (!ret)
2220 goto success;
2221 }
2222
2223 /* we end up here if we couldn't fetch any firmware */
2224
2225 ath10k_err(ar, "Failed to find firmware-N.bin (N between %d and %d) from %s: %d",
2226 ATH10K_FW_API_MIN, ATH10K_FW_API_MAX, ar->hw_params.fw.dir,
2227 ret);
2228
2229 return ret;
2230
2231success:
2232 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api);
2233
2234 return 0;
2235}
2236
2237static int ath10k_core_pre_cal_download(struct ath10k *ar)
2238{
2239 int ret;
2240
2241 ret = ath10k_download_cal_nvmem(ar, "pre-calibration");
2242 if (ret == 0) {
2243 ar->cal_mode = ATH10K_PRE_CAL_MODE_NVMEM;
2244 goto success;
2245 } else if (ret == -EPROBE_DEFER) {
2246 return ret;
2247 }
2248
2249 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2250 "boot did not find a pre-calibration nvmem-cell, try file next: %d\n",
2251 ret);
2252
2253 ret = ath10k_download_cal_file(ar, ar->pre_cal_file);
2254 if (ret == 0) {
2255 ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE;
2256 goto success;
2257 }
2258
2259 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2260 "boot did not find a pre calibration file, try DT next: %d\n",
2261 ret);
2262
2263 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data");
2264 if (ret) {
2265 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2266 "unable to load pre cal data from DT: %d\n", ret);
2267 return ret;
2268 }
2269 ar->cal_mode = ATH10K_PRE_CAL_MODE_DT;
2270
2271success:
2272 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
2273 ath10k_cal_mode_str(ar->cal_mode));
2274
2275 return 0;
2276}
2277
2278static int ath10k_core_pre_cal_config(struct ath10k *ar)
2279{
2280 int ret;
2281
2282 ret = ath10k_core_pre_cal_download(ar);
2283 if (ret) {
2284 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2285 "failed to load pre cal data: %d\n", ret);
2286 return ret;
2287 }
2288
2289 ret = ath10k_core_get_board_id_from_otp(ar);
2290 if (ret) {
2291 ath10k_err(ar, "failed to get board id: %d\n", ret);
2292 return ret;
2293 }
2294
2295 ret = ath10k_download_and_run_otp(ar);
2296 if (ret) {
2297 ath10k_err(ar, "failed to run otp: %d\n", ret);
2298 return ret;
2299 }
2300
2301 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2302 "pre cal configuration done successfully\n");
2303
2304 return 0;
2305}
2306
2307static int ath10k_download_cal_data(struct ath10k *ar)
2308{
2309 int ret;
2310
2311 ret = ath10k_core_pre_cal_config(ar);
2312 if (ret == 0)
2313 return 0;
2314
2315 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2316 "pre cal download procedure failed, try cal file: %d\n",
2317 ret);
2318
2319 ret = ath10k_download_cal_nvmem(ar, "calibration");
2320 if (ret == 0) {
2321 ar->cal_mode = ATH10K_CAL_MODE_NVMEM;
2322 goto done;
2323 } else if (ret == -EPROBE_DEFER) {
2324 return ret;
2325 }
2326
2327 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2328 "boot did not find a calibration nvmem-cell, try file next: %d\n",
2329 ret);
2330
2331 ret = ath10k_download_cal_file(ar, ar->cal_file);
2332 if (ret == 0) {
2333 ar->cal_mode = ATH10K_CAL_MODE_FILE;
2334 goto done;
2335 }
2336
2337 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2338 "boot did not find a calibration file, try DT next: %d\n",
2339 ret);
2340
2341 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data");
2342 if (ret == 0) {
2343 ar->cal_mode = ATH10K_CAL_MODE_DT;
2344 goto done;
2345 }
2346
2347 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2348 "boot did not find DT entry, try target EEPROM next: %d\n",
2349 ret);
2350
2351 ret = ath10k_download_cal_eeprom(ar);
2352 if (ret == 0) {
2353 ar->cal_mode = ATH10K_CAL_MODE_EEPROM;
2354 goto done;
2355 }
2356
2357 ath10k_dbg(ar, ATH10K_DBG_BOOT,
2358 "boot did not find target EEPROM entry, try OTP next: %d\n",
2359 ret);
2360
2361 ret = ath10k_download_and_run_otp(ar);
2362 if (ret) {
2363 ath10k_err(ar, "failed to run otp: %d\n", ret);
2364 return ret;
2365 }
2366
2367 ar->cal_mode = ATH10K_CAL_MODE_OTP;
2368
2369done:
2370 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
2371 ath10k_cal_mode_str(ar->cal_mode));
2372 return 0;
2373}
2374
2375static void ath10k_core_fetch_btcoex_dt(struct ath10k *ar)
2376{
2377 struct device_node *node;
2378 u8 coex_support = 0;
2379 int ret;
2380
2381 node = ar->dev->of_node;
2382 if (!node)
2383 goto out;
2384
2385 ret = of_property_read_u8(node, "qcom,coexist-support", &coex_support);
2386 if (ret) {
2387 ar->coex_support = true;
2388 goto out;
2389 }
2390
2391 if (coex_support) {
2392 ar->coex_support = true;
2393 } else {
2394 ar->coex_support = false;
2395 ar->coex_gpio_pin = -1;
2396 goto out;
2397 }
2398
2399 ret = of_property_read_u32(node, "qcom,coexist-gpio-pin",
2400 &ar->coex_gpio_pin);
2401 if (ret)
2402 ar->coex_gpio_pin = -1;
2403
2404out:
2405 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot coex_support %d coex_gpio_pin %d\n",
2406 ar->coex_support, ar->coex_gpio_pin);
2407}
2408
2409static int ath10k_init_uart(struct ath10k *ar)
2410{
2411 int ret;
2412
2413 /*
2414 * Explicitly setting UART prints to zero as target turns it on
2415 * based on scratch registers.
2416 */
2417 ret = ath10k_bmi_write32(ar, hi_serial_enable, 0);
2418 if (ret) {
2419 ath10k_warn(ar, "could not disable UART prints (%d)\n", ret);
2420 return ret;
2421 }
2422
2423 if (!uart_print) {
2424 if (ar->hw_params.uart_pin_workaround) {
2425 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin,
2426 ar->hw_params.uart_pin);
2427 if (ret) {
2428 ath10k_warn(ar, "failed to set UART TX pin: %d",
2429 ret);
2430 return ret;
2431 }
2432 }
2433
2434 return 0;
2435 }
2436
2437 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin);
2438 if (ret) {
2439 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
2440 return ret;
2441 }
2442
2443 ret = ath10k_bmi_write32(ar, hi_serial_enable, 1);
2444 if (ret) {
2445 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
2446 return ret;
2447 }
2448
2449 /* Set the UART baud rate to 19200. */
2450 ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200);
2451 if (ret) {
2452 ath10k_warn(ar, "could not set the baud rate (%d)\n", ret);
2453 return ret;
2454 }
2455
2456 ath10k_info(ar, "UART prints enabled\n");
2457 return 0;
2458}
2459
2460static int ath10k_init_hw_params(struct ath10k *ar)
2461{
2462 const struct ath10k_hw_params *hw_params;
2463 int i;
2464
2465 for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
2466 hw_params = &ath10k_hw_params_list[i];
2467
2468 if (hw_params->bus == ar->hif.bus &&
2469 hw_params->id == ar->target_version &&
2470 hw_params->dev_id == ar->dev_id)
2471 break;
2472 }
2473
2474 if (i == ARRAY_SIZE(ath10k_hw_params_list)) {
2475 ath10k_err(ar, "Unsupported hardware version: 0x%x\n",
2476 ar->target_version);
2477 return -EINVAL;
2478 }
2479
2480 ar->hw_params = *hw_params;
2481
2482 ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n",
2483 ar->hw_params.name, ar->target_version);
2484
2485 return 0;
2486}
2487
2488void ath10k_core_start_recovery(struct ath10k *ar)
2489{
2490 if (test_and_set_bit(ATH10K_FLAG_RESTARTING, &ar->dev_flags)) {
2491 ath10k_warn(ar, "already restarting\n");
2492 return;
2493 }
2494
2495 queue_work(ar->workqueue, &ar->restart_work);
2496}
2497EXPORT_SYMBOL(ath10k_core_start_recovery);
2498
2499void ath10k_core_napi_enable(struct ath10k *ar)
2500{
2501 lockdep_assert_held(&ar->conf_mutex);
2502
2503 if (test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags))
2504 return;
2505
2506 napi_enable(&ar->napi);
2507 set_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags);
2508}
2509EXPORT_SYMBOL(ath10k_core_napi_enable);
2510
2511void ath10k_core_napi_sync_disable(struct ath10k *ar)
2512{
2513 lockdep_assert_held(&ar->conf_mutex);
2514
2515 if (!test_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags))
2516 return;
2517
2518 napi_synchronize(&ar->napi);
2519 napi_disable(&ar->napi);
2520 clear_bit(ATH10K_FLAG_NAPI_ENABLED, &ar->dev_flags);
2521}
2522EXPORT_SYMBOL(ath10k_core_napi_sync_disable);
2523
2524static void ath10k_core_restart(struct work_struct *work)
2525{
2526 struct ath10k *ar = container_of(work, struct ath10k, restart_work);
2527 int ret;
2528
2529 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
2530
2531 /* Place a barrier to make sure the compiler doesn't reorder
2532 * CRASH_FLUSH and calling other functions.
2533 */
2534 barrier();
2535
2536 ieee80211_stop_queues(ar->hw);
2537 ath10k_drain_tx(ar);
2538 complete(&ar->scan.started);
2539 complete(&ar->scan.completed);
2540 complete(&ar->scan.on_channel);
2541 complete(&ar->offchan_tx_completed);
2542 complete(&ar->install_key_done);
2543 complete(&ar->vdev_setup_done);
2544 complete(&ar->vdev_delete_done);
2545 complete(&ar->thermal.wmi_sync);
2546 complete(&ar->bss_survey_done);
2547 wake_up(&ar->htt.empty_tx_wq);
2548 wake_up(&ar->wmi.tx_credits_wq);
2549 wake_up(&ar->peer_mapping_wq);
2550
2551 /* TODO: We can have one instance of cancelling coverage_class_work by
2552 * moving it to ath10k_halt(), so that both stop() and restart() would
2553 * call that but it takes conf_mutex() and if we call cancel_work_sync()
2554 * with conf_mutex it will deadlock.
2555 */
2556 cancel_work_sync(&ar->set_coverage_class_work);
2557
2558 mutex_lock(&ar->conf_mutex);
2559
2560 switch (ar->state) {
2561 case ATH10K_STATE_ON:
2562 ar->state = ATH10K_STATE_RESTARTING;
2563 ath10k_halt(ar);
2564 ath10k_scan_finish(ar);
2565 ieee80211_restart_hw(ar->hw);
2566 break;
2567 case ATH10K_STATE_OFF:
2568 /* this can happen if driver is being unloaded
2569 * or if the crash happens during FW probing
2570 */
2571 ath10k_warn(ar, "cannot restart a device that hasn't been started\n");
2572 break;
2573 case ATH10K_STATE_RESTARTING:
2574 /* hw restart might be requested from multiple places */
2575 break;
2576 case ATH10K_STATE_RESTARTED:
2577 ar->state = ATH10K_STATE_WEDGED;
2578 fallthrough;
2579 case ATH10K_STATE_WEDGED:
2580 ath10k_warn(ar, "device is wedged, will not restart\n");
2581 break;
2582 case ATH10K_STATE_UTF:
2583 ath10k_warn(ar, "firmware restart in UTF mode not supported\n");
2584 break;
2585 }
2586
2587 mutex_unlock(&ar->conf_mutex);
2588
2589 ret = ath10k_coredump_submit(ar);
2590 if (ret)
2591 ath10k_warn(ar, "failed to send firmware crash dump via devcoredump: %d",
2592 ret);
2593
2594 complete(&ar->driver_recovery);
2595}
2596
2597static void ath10k_core_set_coverage_class_work(struct work_struct *work)
2598{
2599 struct ath10k *ar = container_of(work, struct ath10k,
2600 set_coverage_class_work);
2601
2602 if (ar->hw_params.hw_ops->set_coverage_class)
2603 ar->hw_params.hw_ops->set_coverage_class(ar, -1);
2604}
2605
2606static int ath10k_core_init_firmware_features(struct ath10k *ar)
2607{
2608 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file;
2609 int max_num_peers;
2610
2611 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) &&
2612 !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
2613 ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well");
2614 return -EINVAL;
2615 }
2616
2617 if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) {
2618 ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n",
2619 ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version);
2620 return -EINVAL;
2621 }
2622
2623 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI;
2624 switch (ath10k_cryptmode_param) {
2625 case ATH10K_CRYPT_MODE_HW:
2626 clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
2627 clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
2628 break;
2629 case ATH10K_CRYPT_MODE_SW:
2630 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
2631 fw_file->fw_features)) {
2632 ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware");
2633 return -EINVAL;
2634 }
2635
2636 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
2637 set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
2638 break;
2639 default:
2640 ath10k_info(ar, "invalid cryptmode: %d\n",
2641 ath10k_cryptmode_param);
2642 return -EINVAL;
2643 }
2644
2645 ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT;
2646 ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT;
2647
2648 if (ath10k_frame_mode == ATH10K_HW_TXRX_RAW) {
2649 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
2650 fw_file->fw_features)) {
2651 ath10k_err(ar, "rawmode = 1 requires support from firmware");
2652 return -EINVAL;
2653 }
2654 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
2655 }
2656
2657 if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
2658 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW;
2659
2660 /* Workaround:
2661 *
2662 * Firmware A-MSDU aggregation breaks with RAW Tx encap mode
2663 * and causes enormous performance issues (malformed frames,
2664 * etc).
2665 *
2666 * Disabling A-MSDU makes RAW mode stable with heavy traffic
2667 * albeit a bit slower compared to regular operation.
2668 */
2669 ar->htt.max_num_amsdu = 1;
2670 }
2671
2672 /* Backwards compatibility for firmwares without
2673 * ATH10K_FW_IE_WMI_OP_VERSION.
2674 */
2675 if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) {
2676 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
2677 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2,
2678 fw_file->fw_features))
2679 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2;
2680 else
2681 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1;
2682 } else {
2683 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN;
2684 }
2685 }
2686
2687 switch (fw_file->wmi_op_version) {
2688 case ATH10K_FW_WMI_OP_VERSION_MAIN:
2689 max_num_peers = TARGET_NUM_PEERS;
2690 ar->max_num_stations = TARGET_NUM_STATIONS;
2691 ar->max_num_vdevs = TARGET_NUM_VDEVS;
2692 ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC;
2693 ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
2694 WMI_STAT_PEER;
2695 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
2696 break;
2697 case ATH10K_FW_WMI_OP_VERSION_10_1:
2698 case ATH10K_FW_WMI_OP_VERSION_10_2:
2699 case ATH10K_FW_WMI_OP_VERSION_10_2_4:
2700 if (ath10k_peer_stats_enabled(ar)) {
2701 max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS;
2702 ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS;
2703 } else {
2704 max_num_peers = TARGET_10X_NUM_PEERS;
2705 ar->max_num_stations = TARGET_10X_NUM_STATIONS;
2706 }
2707 ar->max_num_vdevs = TARGET_10X_NUM_VDEVS;
2708 ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
2709 ar->fw_stats_req_mask = WMI_STAT_PEER;
2710 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
2711 break;
2712 case ATH10K_FW_WMI_OP_VERSION_TLV:
2713 max_num_peers = TARGET_TLV_NUM_PEERS;
2714 ar->max_num_stations = TARGET_TLV_NUM_STATIONS;
2715 ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS;
2716 ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS;
2717 if (ar->hif.bus == ATH10K_BUS_SDIO)
2718 ar->htt.max_num_pending_tx =
2719 TARGET_TLV_NUM_MSDU_DESC_HL;
2720 else
2721 ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC;
2722 ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS;
2723 ar->fw_stats_req_mask = WMI_TLV_STAT_PDEV | WMI_TLV_STAT_VDEV |
2724 WMI_TLV_STAT_PEER | WMI_TLV_STAT_PEER_EXTD;
2725 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
2726 ar->wmi.mgmt_max_num_pending_tx = TARGET_TLV_MGMT_NUM_MSDU_DESC;
2727 break;
2728 case ATH10K_FW_WMI_OP_VERSION_10_4:
2729 max_num_peers = TARGET_10_4_NUM_PEERS;
2730 ar->max_num_stations = TARGET_10_4_NUM_STATIONS;
2731 ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS;
2732 ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS;
2733 ar->num_tids = TARGET_10_4_TGT_NUM_TIDS;
2734 ar->fw_stats_req_mask = WMI_10_4_STAT_PEER |
2735 WMI_10_4_STAT_PEER_EXTD |
2736 WMI_10_4_STAT_VDEV_EXTD;
2737 ar->max_spatial_stream = ar->hw_params.max_spatial_stream;
2738 ar->max_num_tdls_vdevs = TARGET_10_4_NUM_TDLS_VDEVS;
2739
2740 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
2741 fw_file->fw_features))
2742 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC;
2743 else
2744 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC;
2745 break;
2746 case ATH10K_FW_WMI_OP_VERSION_UNSET:
2747 case ATH10K_FW_WMI_OP_VERSION_MAX:
2748 default:
2749 WARN_ON(1);
2750 return -EINVAL;
2751 }
2752
2753 if (ar->hw_params.num_peers)
2754 ar->max_num_peers = ar->hw_params.num_peers;
2755 else
2756 ar->max_num_peers = max_num_peers;
2757
2758 /* Backwards compatibility for firmwares without
2759 * ATH10K_FW_IE_HTT_OP_VERSION.
2760 */
2761 if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) {
2762 switch (fw_file->wmi_op_version) {
2763 case ATH10K_FW_WMI_OP_VERSION_MAIN:
2764 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN;
2765 break;
2766 case ATH10K_FW_WMI_OP_VERSION_10_1:
2767 case ATH10K_FW_WMI_OP_VERSION_10_2:
2768 case ATH10K_FW_WMI_OP_VERSION_10_2_4:
2769 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1;
2770 break;
2771 case ATH10K_FW_WMI_OP_VERSION_TLV:
2772 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV;
2773 break;
2774 case ATH10K_FW_WMI_OP_VERSION_10_4:
2775 case ATH10K_FW_WMI_OP_VERSION_UNSET:
2776 case ATH10K_FW_WMI_OP_VERSION_MAX:
2777 ath10k_err(ar, "htt op version not found from fw meta data");
2778 return -EINVAL;
2779 }
2780 }
2781
2782 return 0;
2783}
2784
2785static int ath10k_core_reset_rx_filter(struct ath10k *ar)
2786{
2787 int ret;
2788 int vdev_id;
2789 int vdev_type;
2790 int vdev_subtype;
2791 const u8 *vdev_addr;
2792
2793 vdev_id = 0;
2794 vdev_type = WMI_VDEV_TYPE_STA;
2795 vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE);
2796 vdev_addr = ar->mac_addr;
2797
2798 ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype,
2799 vdev_addr);
2800 if (ret) {
2801 ath10k_err(ar, "failed to create dummy vdev: %d\n", ret);
2802 return ret;
2803 }
2804
2805 ret = ath10k_wmi_vdev_delete(ar, vdev_id);
2806 if (ret) {
2807 ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret);
2808 return ret;
2809 }
2810
2811 /* WMI and HTT may use separate HIF pipes and are not guaranteed to be
2812 * serialized properly implicitly.
2813 *
2814 * Moreover (most) WMI commands have no explicit acknowledges. It is
2815 * possible to infer it implicitly by poking firmware with echo
2816 * command - getting a reply means all preceding comments have been
2817 * (mostly) processed.
2818 *
2819 * In case of vdev create/delete this is sufficient.
2820 *
2821 * Without this it's possible to end up with a race when HTT Rx ring is
2822 * started before vdev create/delete hack is complete allowing a short
2823 * window of opportunity to receive (and Tx ACK) a bunch of frames.
2824 */
2825 ret = ath10k_wmi_barrier(ar);
2826 if (ret) {
2827 ath10k_err(ar, "failed to ping firmware: %d\n", ret);
2828 return ret;
2829 }
2830
2831 return 0;
2832}
2833
2834static int ath10k_core_compat_services(struct ath10k *ar)
2835{
2836 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file;
2837
2838 /* all 10.x firmware versions support thermal throttling but don't
2839 * advertise the support via service flags so we have to hardcode
2840 * it here
2841 */
2842 switch (fw_file->wmi_op_version) {
2843 case ATH10K_FW_WMI_OP_VERSION_10_1:
2844 case ATH10K_FW_WMI_OP_VERSION_10_2:
2845 case ATH10K_FW_WMI_OP_VERSION_10_2_4:
2846 case ATH10K_FW_WMI_OP_VERSION_10_4:
2847 set_bit(WMI_SERVICE_THERM_THROT, ar->wmi.svc_map);
2848 break;
2849 default:
2850 break;
2851 }
2852
2853 return 0;
2854}
2855
2856#define TGT_IRAM_READ_PER_ITR (8 * 1024)
2857
2858static int ath10k_core_copy_target_iram(struct ath10k *ar)
2859{
2860 const struct ath10k_hw_mem_layout *hw_mem;
2861 const struct ath10k_mem_region *tmp, *mem_region = NULL;
2862 dma_addr_t paddr;
2863 void *vaddr = NULL;
2864 u8 num_read_itr;
2865 int i, ret;
2866 u32 len, remaining_len;
2867
2868 /* copy target iram feature must work also when
2869 * ATH10K_FW_CRASH_DUMP_RAM_DATA is disabled, so
2870 * _ath10k_coredump_get_mem_layout() to accomplist that
2871 */
2872 hw_mem = _ath10k_coredump_get_mem_layout(ar);
2873 if (!hw_mem)
2874 /* if CONFIG_DEV_COREDUMP is disabled we get NULL, then
2875 * just silently disable the feature by doing nothing
2876 */
2877 return 0;
2878
2879 for (i = 0; i < hw_mem->region_table.size; i++) {
2880 tmp = &hw_mem->region_table.regions[i];
2881 if (tmp->type == ATH10K_MEM_REGION_TYPE_REG) {
2882 mem_region = tmp;
2883 break;
2884 }
2885 }
2886
2887 if (!mem_region)
2888 return -ENOMEM;
2889
2890 for (i = 0; i < ar->wmi.num_mem_chunks; i++) {
2891 if (ar->wmi.mem_chunks[i].req_id ==
2892 WMI_IRAM_RECOVERY_HOST_MEM_REQ_ID) {
2893 vaddr = ar->wmi.mem_chunks[i].vaddr;
2894 len = ar->wmi.mem_chunks[i].len;
2895 break;
2896 }
2897 }
2898
2899 if (!vaddr || !len) {
2900 ath10k_warn(ar, "No allocated memory for IRAM back up");
2901 return -ENOMEM;
2902 }
2903
2904 len = (len < mem_region->len) ? len : mem_region->len;
2905 paddr = mem_region->start;
2906 num_read_itr = len / TGT_IRAM_READ_PER_ITR;
2907 remaining_len = len % TGT_IRAM_READ_PER_ITR;
2908 for (i = 0; i < num_read_itr; i++) {
2909 ret = ath10k_hif_diag_read(ar, paddr, vaddr,
2910 TGT_IRAM_READ_PER_ITR);
2911 if (ret) {
2912 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d",
2913 ret);
2914 return ret;
2915 }
2916
2917 paddr += TGT_IRAM_READ_PER_ITR;
2918 vaddr += TGT_IRAM_READ_PER_ITR;
2919 }
2920
2921 if (remaining_len) {
2922 ret = ath10k_hif_diag_read(ar, paddr, vaddr, remaining_len);
2923 if (ret) {
2924 ath10k_warn(ar, "failed to copy firmware IRAM contents: %d",
2925 ret);
2926 return ret;
2927 }
2928 }
2929
2930 ath10k_dbg(ar, ATH10K_DBG_BOOT, "target IRAM back up completed\n");
2931
2932 return 0;
2933}
2934
2935int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
2936 const struct ath10k_fw_components *fw)
2937{
2938 int status;
2939 u32 val;
2940
2941 lockdep_assert_held(&ar->conf_mutex);
2942
2943 clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
2944
2945 ar->running_fw = fw;
2946
2947 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
2948 ar->running_fw->fw_file.fw_features)) {
2949 ath10k_bmi_start(ar);
2950
2951 /* Enable hardware clock to speed up firmware download */
2952 if (ar->hw_params.hw_ops->enable_pll_clk) {
2953 status = ar->hw_params.hw_ops->enable_pll_clk(ar);
2954 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot enable pll ret %d\n",
2955 status);
2956 }
2957
2958 if (ath10k_init_configure_target(ar)) {
2959 status = -EINVAL;
2960 goto err;
2961 }
2962
2963 status = ath10k_download_cal_data(ar);
2964 if (status)
2965 goto err;
2966
2967 /* Some of qca988x solutions are having global reset issue
2968 * during target initialization. Bypassing PLL setting before
2969 * downloading firmware and letting the SoC run on REF_CLK is
2970 * fixing the problem. Corresponding firmware change is also
2971 * needed to set the clock source once the target is
2972 * initialized.
2973 */
2974 if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT,
2975 ar->running_fw->fw_file.fw_features)) {
2976 status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1);
2977 if (status) {
2978 ath10k_err(ar, "could not write to skip_clock_init: %d\n",
2979 status);
2980 goto err;
2981 }
2982 }
2983
2984 status = ath10k_download_fw(ar);
2985 if (status)
2986 goto err;
2987
2988 status = ath10k_init_uart(ar);
2989 if (status)
2990 goto err;
2991
2992 if (ar->hif.bus == ATH10K_BUS_SDIO) {
2993 status = ath10k_init_sdio(ar, mode);
2994 if (status) {
2995 ath10k_err(ar, "failed to init SDIO: %d\n", status);
2996 goto err;
2997 }
2998 }
2999 }
3000
3001 ar->htc.htc_ops.target_send_suspend_complete =
3002 ath10k_send_suspend_complete;
3003
3004 status = ath10k_htc_init(ar);
3005 if (status) {
3006 ath10k_err(ar, "could not init HTC (%d)\n", status);
3007 goto err;
3008 }
3009
3010 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
3011 ar->running_fw->fw_file.fw_features)) {
3012 status = ath10k_bmi_done(ar);
3013 if (status)
3014 goto err;
3015 }
3016
3017 status = ath10k_wmi_attach(ar);
3018 if (status) {
3019 ath10k_err(ar, "WMI attach failed: %d\n", status);
3020 goto err;
3021 }
3022
3023 status = ath10k_htt_init(ar);
3024 if (status) {
3025 ath10k_err(ar, "failed to init htt: %d\n", status);
3026 goto err_wmi_detach;
3027 }
3028
3029 status = ath10k_htt_tx_start(&ar->htt);
3030 if (status) {
3031 ath10k_err(ar, "failed to alloc htt tx: %d\n", status);
3032 goto err_wmi_detach;
3033 }
3034
3035 /* If firmware indicates Full Rx Reorder support it must be used in a
3036 * slightly different manner. Let HTT code know.
3037 */
3038 ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER,
3039 ar->wmi.svc_map));
3040
3041 status = ath10k_htt_rx_alloc(&ar->htt);
3042 if (status) {
3043 ath10k_err(ar, "failed to alloc htt rx: %d\n", status);
3044 goto err_htt_tx_detach;
3045 }
3046
3047 status = ath10k_hif_start(ar);
3048 if (status) {
3049 ath10k_err(ar, "could not start HIF: %d\n", status);
3050 goto err_htt_rx_detach;
3051 }
3052
3053 status = ath10k_htc_wait_target(&ar->htc);
3054 if (status) {
3055 ath10k_err(ar, "failed to connect to HTC: %d\n", status);
3056 goto err_hif_stop;
3057 }
3058
3059 status = ath10k_hif_start_post(ar);
3060 if (status) {
3061 ath10k_err(ar, "failed to swap mailbox: %d\n", status);
3062 goto err_hif_stop;
3063 }
3064
3065 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
3066 status = ath10k_htt_connect(&ar->htt);
3067 if (status) {
3068 ath10k_err(ar, "failed to connect htt (%d)\n", status);
3069 goto err_hif_stop;
3070 }
3071 }
3072
3073 status = ath10k_wmi_connect(ar);
3074 if (status) {
3075 ath10k_err(ar, "could not connect wmi: %d\n", status);
3076 goto err_hif_stop;
3077 }
3078
3079 status = ath10k_htc_start(&ar->htc);
3080 if (status) {
3081 ath10k_err(ar, "failed to start htc: %d\n", status);
3082 goto err_hif_stop;
3083 }
3084
3085 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
3086 status = ath10k_wmi_wait_for_service_ready(ar);
3087 if (status) {
3088 ath10k_warn(ar, "wmi service ready event not received");
3089 goto err_hif_stop;
3090 }
3091 }
3092
3093 ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n",
3094 ar->hw->wiphy->fw_version);
3095
3096 if (test_bit(ATH10K_FW_FEATURE_IRAM_RECOVERY,
3097 ar->running_fw->fw_file.fw_features)) {
3098 status = ath10k_core_copy_target_iram(ar);
3099 if (status) {
3100 ath10k_warn(ar, "failed to copy target iram contents: %d",
3101 status);
3102 goto err_hif_stop;
3103 }
3104 }
3105
3106 if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map) &&
3107 mode == ATH10K_FIRMWARE_MODE_NORMAL) {
3108 val = 0;
3109 if (ath10k_peer_stats_enabled(ar))
3110 val = WMI_10_4_PEER_STATS;
3111
3112 /* Enable vdev stats by default */
3113 val |= WMI_10_4_VDEV_STATS;
3114
3115 if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map))
3116 val |= WMI_10_4_BSS_CHANNEL_INFO_64;
3117
3118 ath10k_core_fetch_btcoex_dt(ar);
3119
3120 /* 10.4 firmware supports BT-Coex without reloading firmware
3121 * via pdev param. To support Bluetooth coexistence pdev param,
3122 * WMI_COEX_GPIO_SUPPORT of extended resource config should be
3123 * enabled always.
3124 *
3125 * We can still enable BTCOEX if firmware has the support
3126 * even though btceox_support value is
3127 * ATH10K_DT_BTCOEX_NOT_FOUND
3128 */
3129
3130 if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) &&
3131 test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM,
3132 ar->running_fw->fw_file.fw_features) &&
3133 ar->coex_support)
3134 val |= WMI_10_4_COEX_GPIO_SUPPORT;
3135
3136 if (test_bit(WMI_SERVICE_TDLS_EXPLICIT_MODE_ONLY,
3137 ar->wmi.svc_map))
3138 val |= WMI_10_4_TDLS_EXPLICIT_MODE_ONLY;
3139
3140 if (test_bit(WMI_SERVICE_TDLS_UAPSD_BUFFER_STA,
3141 ar->wmi.svc_map))
3142 val |= WMI_10_4_TDLS_UAPSD_BUFFER_STA;
3143
3144 if (test_bit(WMI_SERVICE_TX_DATA_ACK_RSSI,
3145 ar->wmi.svc_map))
3146 val |= WMI_10_4_TX_DATA_ACK_RSSI;
3147
3148 if (test_bit(WMI_SERVICE_REPORT_AIRTIME, ar->wmi.svc_map))
3149 val |= WMI_10_4_REPORT_AIRTIME;
3150
3151 if (test_bit(WMI_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT,
3152 ar->wmi.svc_map))
3153 val |= WMI_10_4_EXT_PEER_TID_CONFIGS_SUPPORT;
3154
3155 status = ath10k_mac_ext_resource_config(ar, val);
3156 if (status) {
3157 ath10k_err(ar,
3158 "failed to send ext resource cfg command : %d\n",
3159 status);
3160 goto err_hif_stop;
3161 }
3162 }
3163
3164 status = ath10k_wmi_cmd_init(ar);
3165 if (status) {
3166 ath10k_err(ar, "could not send WMI init command (%d)\n",
3167 status);
3168 goto err_hif_stop;
3169 }
3170
3171 status = ath10k_wmi_wait_for_unified_ready(ar);
3172 if (status) {
3173 ath10k_err(ar, "wmi unified ready event not received\n");
3174 goto err_hif_stop;
3175 }
3176
3177 status = ath10k_core_compat_services(ar);
3178 if (status) {
3179 ath10k_err(ar, "compat services failed: %d\n", status);
3180 goto err_hif_stop;
3181 }
3182
3183 status = ath10k_wmi_pdev_set_base_macaddr(ar, ar->mac_addr);
3184 if (status && status != -EOPNOTSUPP) {
3185 ath10k_err(ar,
3186 "failed to set base mac address: %d\n", status);
3187 goto err_hif_stop;
3188 }
3189
3190 /* Some firmware revisions do not properly set up hardware rx filter
3191 * registers.
3192 *
3193 * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK
3194 * is filled with 0s instead of 1s allowing HW to respond with ACKs to
3195 * any frames that matches MAC_PCU_RX_FILTER which is also
3196 * misconfigured to accept anything.
3197 *
3198 * The ADDR1 is programmed using internal firmware structure field and
3199 * can't be (easily/sanely) reached from the driver explicitly. It is
3200 * possible to implicitly make it correct by creating a dummy vdev and
3201 * then deleting it.
3202 */
3203 if (ar->hw_params.hw_filter_reset_required &&
3204 mode == ATH10K_FIRMWARE_MODE_NORMAL) {
3205 status = ath10k_core_reset_rx_filter(ar);
3206 if (status) {
3207 ath10k_err(ar,
3208 "failed to reset rx filter: %d\n", status);
3209 goto err_hif_stop;
3210 }
3211 }
3212
3213 status = ath10k_htt_rx_ring_refill(ar);
3214 if (status) {
3215 ath10k_err(ar, "failed to refill htt rx ring: %d\n", status);
3216 goto err_hif_stop;
3217 }
3218
3219 if (ar->max_num_vdevs >= 64)
3220 ar->free_vdev_map = 0xFFFFFFFFFFFFFFFFLL;
3221 else
3222 ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1;
3223
3224 INIT_LIST_HEAD(&ar->arvifs);
3225
3226 /* we don't care about HTT in UTF mode */
3227 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
3228 status = ath10k_htt_setup(&ar->htt);
3229 if (status) {
3230 ath10k_err(ar, "failed to setup htt: %d\n", status);
3231 goto err_hif_stop;
3232 }
3233 }
3234
3235 status = ath10k_debug_start(ar);
3236 if (status)
3237 goto err_hif_stop;
3238
3239 status = ath10k_hif_set_target_log_mode(ar, fw_diag_log);
3240 if (status && status != -EOPNOTSUPP) {
3241 ath10k_warn(ar, "set target log mode failed: %d\n", status);
3242 goto err_hif_stop;
3243 }
3244
3245 return 0;
3246
3247err_hif_stop:
3248 ath10k_hif_stop(ar);
3249err_htt_rx_detach:
3250 ath10k_htt_rx_free(&ar->htt);
3251err_htt_tx_detach:
3252 ath10k_htt_tx_free(&ar->htt);
3253err_wmi_detach:
3254 ath10k_wmi_detach(ar);
3255err:
3256 return status;
3257}
3258EXPORT_SYMBOL(ath10k_core_start);
3259
3260int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt)
3261{
3262 int ret;
3263 unsigned long time_left;
3264
3265 reinit_completion(&ar->target_suspend);
3266
3267 ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt);
3268 if (ret) {
3269 ath10k_warn(ar, "could not suspend target (%d)\n", ret);
3270 return ret;
3271 }
3272
3273 time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ);
3274
3275 if (!time_left) {
3276 ath10k_warn(ar, "suspend timed out - target pause event never came\n");
3277 return -ETIMEDOUT;
3278 }
3279
3280 return 0;
3281}
3282
3283void ath10k_core_stop(struct ath10k *ar)
3284{
3285 lockdep_assert_held(&ar->conf_mutex);
3286 ath10k_debug_stop(ar);
3287
3288 /* try to suspend target */
3289 if (ar->state != ATH10K_STATE_RESTARTING &&
3290 ar->state != ATH10K_STATE_UTF)
3291 ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR);
3292
3293 ath10k_hif_stop(ar);
3294 ath10k_htt_tx_stop(&ar->htt);
3295 ath10k_htt_rx_free(&ar->htt);
3296 ath10k_wmi_detach(ar);
3297
3298 ar->id.bmi_ids_valid = false;
3299}
3300EXPORT_SYMBOL(ath10k_core_stop);
3301
3302/* mac80211 manages fw/hw initialization through start/stop hooks. However in
3303 * order to know what hw capabilities should be advertised to mac80211 it is
3304 * necessary to load the firmware (and tear it down immediately since start
3305 * hook will try to init it again) before registering
3306 */
3307static int ath10k_core_probe_fw(struct ath10k *ar)
3308{
3309 struct bmi_target_info target_info;
3310 int ret = 0;
3311
3312 ret = ath10k_hif_power_up(ar, ATH10K_FIRMWARE_MODE_NORMAL);
3313 if (ret) {
3314 ath10k_err(ar, "could not power on hif bus (%d)\n", ret);
3315 return ret;
3316 }
3317
3318 switch (ar->hif.bus) {
3319 case ATH10K_BUS_SDIO:
3320 memset(&target_info, 0, sizeof(target_info));
3321 ret = ath10k_bmi_get_target_info_sdio(ar, &target_info);
3322 if (ret) {
3323 ath10k_err(ar, "could not get target info (%d)\n", ret);
3324 goto err_power_down;
3325 }
3326 ar->target_version = target_info.version;
3327 ar->hw->wiphy->hw_version = target_info.version;
3328 break;
3329 case ATH10K_BUS_PCI:
3330 case ATH10K_BUS_AHB:
3331 case ATH10K_BUS_USB:
3332 memset(&target_info, 0, sizeof(target_info));
3333 ret = ath10k_bmi_get_target_info(ar, &target_info);
3334 if (ret) {
3335 ath10k_err(ar, "could not get target info (%d)\n", ret);
3336 goto err_power_down;
3337 }
3338 ar->target_version = target_info.version;
3339 ar->hw->wiphy->hw_version = target_info.version;
3340 break;
3341 case ATH10K_BUS_SNOC:
3342 memset(&target_info, 0, sizeof(target_info));
3343 ret = ath10k_hif_get_target_info(ar, &target_info);
3344 if (ret) {
3345 ath10k_err(ar, "could not get target info (%d)\n", ret);
3346 goto err_power_down;
3347 }
3348 ar->target_version = target_info.version;
3349 ar->hw->wiphy->hw_version = target_info.version;
3350 break;
3351 default:
3352 ath10k_err(ar, "incorrect hif bus type: %d\n", ar->hif.bus);
3353 }
3354
3355 ret = ath10k_init_hw_params(ar);
3356 if (ret) {
3357 ath10k_err(ar, "could not get hw params (%d)\n", ret);
3358 goto err_power_down;
3359 }
3360
3361 ret = ath10k_core_fetch_firmware_files(ar);
3362 if (ret) {
3363 ath10k_err(ar, "could not fetch firmware files (%d)\n", ret);
3364 goto err_power_down;
3365 }
3366
3367 BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) !=
3368 sizeof(ar->normal_mode_fw.fw_file.fw_version));
3369 memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version,
3370 sizeof(ar->hw->wiphy->fw_version));
3371
3372 ath10k_debug_print_hwfw_info(ar);
3373
3374 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
3375 ar->normal_mode_fw.fw_file.fw_features)) {
3376 ret = ath10k_core_pre_cal_download(ar);
3377 if (ret) {
3378 /* pre calibration data download is not necessary
3379 * for all the chipsets. Ignore failures and continue.
3380 */
3381 ath10k_dbg(ar, ATH10K_DBG_BOOT,
3382 "could not load pre cal data: %d\n", ret);
3383 }
3384
3385 ret = ath10k_core_get_board_id_from_otp(ar);
3386 if (ret && ret != -EOPNOTSUPP) {
3387 ath10k_err(ar, "failed to get board id from otp: %d\n",
3388 ret);
3389 goto err_free_firmware_files;
3390 }
3391
3392 ret = ath10k_core_check_smbios(ar);
3393 if (ret)
3394 ath10k_dbg(ar, ATH10K_DBG_BOOT, "SMBIOS bdf variant name not set.\n");
3395
3396 ret = ath10k_core_check_dt(ar);
3397 if (ret)
3398 ath10k_dbg(ar, ATH10K_DBG_BOOT, "DT bdf variant name not set.\n");
3399
3400 ret = ath10k_core_fetch_board_file(ar, ATH10K_BD_IE_BOARD);
3401 if (ret) {
3402 ath10k_err(ar, "failed to fetch board file: %d\n", ret);
3403 goto err_free_firmware_files;
3404 }
3405
3406 ath10k_debug_print_board_info(ar);
3407 }
3408
3409 device_get_mac_address(ar->dev, ar->mac_addr);
3410
3411 ret = ath10k_core_init_firmware_features(ar);
3412 if (ret) {
3413 ath10k_err(ar, "fatal problem with firmware features: %d\n",
3414 ret);
3415 goto err_free_firmware_files;
3416 }
3417
3418 if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
3419 ar->normal_mode_fw.fw_file.fw_features)) {
3420 ret = ath10k_swap_code_seg_init(ar,
3421 &ar->normal_mode_fw.fw_file);
3422 if (ret) {
3423 ath10k_err(ar, "failed to initialize code swap segment: %d\n",
3424 ret);
3425 goto err_free_firmware_files;
3426 }
3427 }
3428
3429 mutex_lock(&ar->conf_mutex);
3430
3431 ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL,
3432 &ar->normal_mode_fw);
3433 if (ret) {
3434 ath10k_err(ar, "could not init core (%d)\n", ret);
3435 goto err_unlock;
3436 }
3437
3438 ath10k_debug_print_boot_info(ar);
3439 ath10k_core_stop(ar);
3440
3441 mutex_unlock(&ar->conf_mutex);
3442
3443 ath10k_hif_power_down(ar);
3444 return 0;
3445
3446err_unlock:
3447 mutex_unlock(&ar->conf_mutex);
3448
3449err_free_firmware_files:
3450 ath10k_core_free_firmware_files(ar);
3451
3452err_power_down:
3453 ath10k_hif_power_down(ar);
3454
3455 return ret;
3456}
3457
3458static void ath10k_core_register_work(struct work_struct *work)
3459{
3460 struct ath10k *ar = container_of(work, struct ath10k, register_work);
3461 int status;
3462
3463 /* peer stats are enabled by default */
3464 set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags);
3465
3466 status = ath10k_core_probe_fw(ar);
3467 if (status) {
3468 ath10k_err(ar, "could not probe fw (%d)\n", status);
3469 goto err;
3470 }
3471
3472 status = ath10k_mac_register(ar);
3473 if (status) {
3474 ath10k_err(ar, "could not register to mac80211 (%d)\n", status);
3475 goto err_release_fw;
3476 }
3477
3478 status = ath10k_coredump_register(ar);
3479 if (status) {
3480 ath10k_err(ar, "unable to register coredump\n");
3481 goto err_unregister_mac;
3482 }
3483
3484 status = ath10k_debug_register(ar);
3485 if (status) {
3486 ath10k_err(ar, "unable to initialize debugfs\n");
3487 goto err_unregister_coredump;
3488 }
3489
3490 status = ath10k_spectral_create(ar);
3491 if (status) {
3492 ath10k_err(ar, "failed to initialize spectral\n");
3493 goto err_debug_destroy;
3494 }
3495
3496 status = ath10k_thermal_register(ar);
3497 if (status) {
3498 ath10k_err(ar, "could not register thermal device: %d\n",
3499 status);
3500 goto err_spectral_destroy;
3501 }
3502
3503 set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags);
3504 return;
3505
3506err_spectral_destroy:
3507 ath10k_spectral_destroy(ar);
3508err_debug_destroy:
3509 ath10k_debug_destroy(ar);
3510err_unregister_coredump:
3511 ath10k_coredump_unregister(ar);
3512err_unregister_mac:
3513 ath10k_mac_unregister(ar);
3514err_release_fw:
3515 ath10k_core_free_firmware_files(ar);
3516err:
3517 /* TODO: It's probably a good idea to release device from the driver
3518 * but calling device_release_driver() here will cause a deadlock.
3519 */
3520 return;
3521}
3522
3523int ath10k_core_register(struct ath10k *ar,
3524 const struct ath10k_bus_params *bus_params)
3525{
3526 ar->bus_param = *bus_params;
3527
3528 queue_work(ar->workqueue, &ar->register_work);
3529
3530 return 0;
3531}
3532EXPORT_SYMBOL(ath10k_core_register);
3533
3534void ath10k_core_unregister(struct ath10k *ar)
3535{
3536 cancel_work_sync(&ar->register_work);
3537
3538 if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))
3539 return;
3540
3541 ath10k_thermal_unregister(ar);
3542 /* Stop spectral before unregistering from mac80211 to remove the
3543 * relayfs debugfs file cleanly. Otherwise the parent debugfs tree
3544 * would be already be free'd recursively, leading to a double free.
3545 */
3546 ath10k_spectral_destroy(ar);
3547
3548 /* We must unregister from mac80211 before we stop HTC and HIF.
3549 * Otherwise we will fail to submit commands to FW and mac80211 will be
3550 * unhappy about callback failures.
3551 */
3552 ath10k_mac_unregister(ar);
3553
3554 ath10k_testmode_destroy(ar);
3555
3556 ath10k_core_free_firmware_files(ar);
3557 ath10k_core_free_board_files(ar);
3558
3559 ath10k_debug_unregister(ar);
3560}
3561EXPORT_SYMBOL(ath10k_core_unregister);
3562
3563struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
3564 enum ath10k_bus bus,
3565 enum ath10k_hw_rev hw_rev,
3566 const struct ath10k_hif_ops *hif_ops)
3567{
3568 struct ath10k *ar;
3569 int ret;
3570
3571 ar = ath10k_mac_create(priv_size);
3572 if (!ar)
3573 return NULL;
3574
3575 ar->ath_common.priv = ar;
3576 ar->ath_common.hw = ar->hw;
3577 ar->dev = dev;
3578 ar->hw_rev = hw_rev;
3579 ar->hif.ops = hif_ops;
3580 ar->hif.bus = bus;
3581
3582 switch (hw_rev) {
3583 case ATH10K_HW_QCA988X:
3584 case ATH10K_HW_QCA9887:
3585 ar->regs = &qca988x_regs;
3586 ar->hw_ce_regs = &qcax_ce_regs;
3587 ar->hw_values = &qca988x_values;
3588 break;
3589 case ATH10K_HW_QCA6174:
3590 case ATH10K_HW_QCA9377:
3591 ar->regs = &qca6174_regs;
3592 ar->hw_ce_regs = &qcax_ce_regs;
3593 ar->hw_values = &qca6174_values;
3594 break;
3595 case ATH10K_HW_QCA99X0:
3596 case ATH10K_HW_QCA9984:
3597 ar->regs = &qca99x0_regs;
3598 ar->hw_ce_regs = &qcax_ce_regs;
3599 ar->hw_values = &qca99x0_values;
3600 break;
3601 case ATH10K_HW_QCA9888:
3602 ar->regs = &qca99x0_regs;
3603 ar->hw_ce_regs = &qcax_ce_regs;
3604 ar->hw_values = &qca9888_values;
3605 break;
3606 case ATH10K_HW_QCA4019:
3607 ar->regs = &qca4019_regs;
3608 ar->hw_ce_regs = &qcax_ce_regs;
3609 ar->hw_values = &qca4019_values;
3610 break;
3611 case ATH10K_HW_WCN3990:
3612 ar->regs = &wcn3990_regs;
3613 ar->hw_ce_regs = &wcn3990_ce_regs;
3614 ar->hw_values = &wcn3990_values;
3615 break;
3616 default:
3617 ath10k_err(ar, "unsupported core hardware revision %d\n",
3618 hw_rev);
3619 ret = -EOPNOTSUPP;
3620 goto err_free_mac;
3621 }
3622
3623 init_completion(&ar->scan.started);
3624 init_completion(&ar->scan.completed);
3625 init_completion(&ar->scan.on_channel);
3626 init_completion(&ar->target_suspend);
3627 init_completion(&ar->driver_recovery);
3628 init_completion(&ar->wow.wakeup_completed);
3629
3630 init_completion(&ar->install_key_done);
3631 init_completion(&ar->vdev_setup_done);
3632 init_completion(&ar->vdev_delete_done);
3633 init_completion(&ar->thermal.wmi_sync);
3634 init_completion(&ar->bss_survey_done);
3635 init_completion(&ar->peer_delete_done);
3636 init_completion(&ar->peer_stats_info_complete);
3637
3638 INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work);
3639
3640 ar->workqueue = create_singlethread_workqueue("ath10k_wq");
3641 if (!ar->workqueue)
3642 goto err_free_mac;
3643
3644 ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq");
3645 if (!ar->workqueue_aux)
3646 goto err_free_wq;
3647
3648 ar->workqueue_tx_complete =
3649 create_singlethread_workqueue("ath10k_tx_complete_wq");
3650 if (!ar->workqueue_tx_complete)
3651 goto err_free_aux_wq;
3652
3653 mutex_init(&ar->conf_mutex);
3654 mutex_init(&ar->dump_mutex);
3655 spin_lock_init(&ar->data_lock);
3656
3657 for (int ac = 0; ac < IEEE80211_NUM_ACS; ac++)
3658 spin_lock_init(&ar->queue_lock[ac]);
3659
3660 INIT_LIST_HEAD(&ar->peers);
3661 init_waitqueue_head(&ar->peer_mapping_wq);
3662 init_waitqueue_head(&ar->htt.empty_tx_wq);
3663 init_waitqueue_head(&ar->wmi.tx_credits_wq);
3664
3665 skb_queue_head_init(&ar->htt.rx_indication_head);
3666
3667 init_completion(&ar->offchan_tx_completed);
3668 INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work);
3669 skb_queue_head_init(&ar->offchan_tx_queue);
3670
3671 INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work);
3672 skb_queue_head_init(&ar->wmi_mgmt_tx_queue);
3673
3674 INIT_WORK(&ar->register_work, ath10k_core_register_work);
3675 INIT_WORK(&ar->restart_work, ath10k_core_restart);
3676 INIT_WORK(&ar->set_coverage_class_work,
3677 ath10k_core_set_coverage_class_work);
3678
3679 init_dummy_netdev(&ar->napi_dev);
3680
3681 ret = ath10k_coredump_create(ar);
3682 if (ret)
3683 goto err_free_tx_complete;
3684
3685 ret = ath10k_debug_create(ar);
3686 if (ret)
3687 goto err_free_coredump;
3688
3689 return ar;
3690
3691err_free_coredump:
3692 ath10k_coredump_destroy(ar);
3693err_free_tx_complete:
3694 destroy_workqueue(ar->workqueue_tx_complete);
3695err_free_aux_wq:
3696 destroy_workqueue(ar->workqueue_aux);
3697err_free_wq:
3698 destroy_workqueue(ar->workqueue);
3699err_free_mac:
3700 ath10k_mac_destroy(ar);
3701
3702 return NULL;
3703}
3704EXPORT_SYMBOL(ath10k_core_create);
3705
3706void ath10k_core_destroy(struct ath10k *ar)
3707{
3708 destroy_workqueue(ar->workqueue);
3709
3710 destroy_workqueue(ar->workqueue_aux);
3711
3712 destroy_workqueue(ar->workqueue_tx_complete);
3713
3714 ath10k_debug_destroy(ar);
3715 ath10k_coredump_destroy(ar);
3716 ath10k_htt_tx_destroy(&ar->htt);
3717 ath10k_wmi_free_host_mem(ar);
3718 ath10k_mac_destroy(ar);
3719}
3720EXPORT_SYMBOL(ath10k_core_destroy);
3721
3722MODULE_AUTHOR("Qualcomm Atheros");
3723MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards.");
3724MODULE_LICENSE("Dual BSD/GPL");