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1/*
2 * drivers/net/phy/micrel.c
3 *
4 * Driver for Micrel PHYs
5 *
6 * Author: David J. Choi
7 *
8 * Copyright (c) 2010 Micrel, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * Support : ksz9021 1000/100/10 phy from Micrel
16 * ks8001, ks8737, ks8721, ks8041, ks8051 100/10 phy
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/phy.h>
22#include <linux/micrel_phy.h>
23
24/* general Interrupt control/status reg in vendor specific block. */
25#define MII_KSZPHY_INTCS 0x1B
26#define KSZPHY_INTCS_JABBER (1 << 15)
27#define KSZPHY_INTCS_RECEIVE_ERR (1 << 14)
28#define KSZPHY_INTCS_PAGE_RECEIVE (1 << 13)
29#define KSZPHY_INTCS_PARELLEL (1 << 12)
30#define KSZPHY_INTCS_LINK_PARTNER_ACK (1 << 11)
31#define KSZPHY_INTCS_LINK_DOWN (1 << 10)
32#define KSZPHY_INTCS_REMOTE_FAULT (1 << 9)
33#define KSZPHY_INTCS_LINK_UP (1 << 8)
34#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
35 KSZPHY_INTCS_LINK_DOWN)
36
37/* general PHY control reg in vendor specific block. */
38#define MII_KSZPHY_CTRL 0x1F
39/* bitmap of PHY register to set interrupt mode */
40#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9)
41#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14)
42#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
43#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
44
45static int kszphy_ack_interrupt(struct phy_device *phydev)
46{
47 /* bit[7..0] int status, which is a read and clear register. */
48 int rc;
49
50 rc = phy_read(phydev, MII_KSZPHY_INTCS);
51
52 return (rc < 0) ? rc : 0;
53}
54
55static int kszphy_set_interrupt(struct phy_device *phydev)
56{
57 int temp;
58 temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
59 KSZPHY_INTCS_ALL : 0;
60 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
61}
62
63static int kszphy_config_intr(struct phy_device *phydev)
64{
65 int temp, rc;
66
67 /* set the interrupt pin active low */
68 temp = phy_read(phydev, MII_KSZPHY_CTRL);
69 temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
70 phy_write(phydev, MII_KSZPHY_CTRL, temp);
71 rc = kszphy_set_interrupt(phydev);
72 return rc < 0 ? rc : 0;
73}
74
75static int ksz9021_config_intr(struct phy_device *phydev)
76{
77 int temp, rc;
78
79 /* set the interrupt pin active low */
80 temp = phy_read(phydev, MII_KSZPHY_CTRL);
81 temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
82 phy_write(phydev, MII_KSZPHY_CTRL, temp);
83 rc = kszphy_set_interrupt(phydev);
84 return rc < 0 ? rc : 0;
85}
86
87static int ks8737_config_intr(struct phy_device *phydev)
88{
89 int temp, rc;
90
91 /* set the interrupt pin active low */
92 temp = phy_read(phydev, MII_KSZPHY_CTRL);
93 temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
94 phy_write(phydev, MII_KSZPHY_CTRL, temp);
95 rc = kszphy_set_interrupt(phydev);
96 return rc < 0 ? rc : 0;
97}
98
99static int kszphy_config_init(struct phy_device *phydev)
100{
101 return 0;
102}
103
104static int ks8051_config_init(struct phy_device *phydev)
105{
106 int regval;
107
108 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
109 regval = phy_read(phydev, MII_KSZPHY_CTRL);
110 regval |= KSZ8051_RMII_50MHZ_CLK;
111 phy_write(phydev, MII_KSZPHY_CTRL, regval);
112 }
113
114 return 0;
115}
116
117static struct phy_driver ks8737_driver = {
118 .phy_id = PHY_ID_KS8737,
119 .phy_id_mask = 0x00fffff0,
120 .name = "Micrel KS8737",
121 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
122 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
123 .config_init = kszphy_config_init,
124 .config_aneg = genphy_config_aneg,
125 .read_status = genphy_read_status,
126 .ack_interrupt = kszphy_ack_interrupt,
127 .config_intr = ks8737_config_intr,
128 .driver = { .owner = THIS_MODULE,},
129};
130
131static struct phy_driver ks8041_driver = {
132 .phy_id = PHY_ID_KS8041,
133 .phy_id_mask = 0x00fffff0,
134 .name = "Micrel KS8041",
135 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
136 | SUPPORTED_Asym_Pause),
137 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
138 .config_init = kszphy_config_init,
139 .config_aneg = genphy_config_aneg,
140 .read_status = genphy_read_status,
141 .ack_interrupt = kszphy_ack_interrupt,
142 .config_intr = kszphy_config_intr,
143 .driver = { .owner = THIS_MODULE,},
144};
145
146static struct phy_driver ks8051_driver = {
147 .phy_id = PHY_ID_KS8051,
148 .phy_id_mask = 0x00fffff0,
149 .name = "Micrel KS8051",
150 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
151 | SUPPORTED_Asym_Pause),
152 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
153 .config_init = ks8051_config_init,
154 .config_aneg = genphy_config_aneg,
155 .read_status = genphy_read_status,
156 .ack_interrupt = kszphy_ack_interrupt,
157 .config_intr = kszphy_config_intr,
158 .driver = { .owner = THIS_MODULE,},
159};
160
161static struct phy_driver ks8001_driver = {
162 .phy_id = PHY_ID_KS8001,
163 .name = "Micrel KS8001 or KS8721",
164 .phy_id_mask = 0x00fffff0,
165 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
166 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
167 .config_init = kszphy_config_init,
168 .config_aneg = genphy_config_aneg,
169 .read_status = genphy_read_status,
170 .ack_interrupt = kszphy_ack_interrupt,
171 .config_intr = kszphy_config_intr,
172 .driver = { .owner = THIS_MODULE,},
173};
174
175static struct phy_driver ksz9021_driver = {
176 .phy_id = PHY_ID_KSZ9021,
177 .phy_id_mask = 0x000fff10,
178 .name = "Micrel KSZ9021 Gigabit PHY",
179 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause
180 | SUPPORTED_Asym_Pause),
181 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
182 .config_init = kszphy_config_init,
183 .config_aneg = genphy_config_aneg,
184 .read_status = genphy_read_status,
185 .ack_interrupt = kszphy_ack_interrupt,
186 .config_intr = ksz9021_config_intr,
187 .driver = { .owner = THIS_MODULE, },
188};
189
190static int __init ksphy_init(void)
191{
192 int ret;
193
194 ret = phy_driver_register(&ks8001_driver);
195 if (ret)
196 goto err1;
197
198 ret = phy_driver_register(&ksz9021_driver);
199 if (ret)
200 goto err2;
201
202 ret = phy_driver_register(&ks8737_driver);
203 if (ret)
204 goto err3;
205 ret = phy_driver_register(&ks8041_driver);
206 if (ret)
207 goto err4;
208 ret = phy_driver_register(&ks8051_driver);
209 if (ret)
210 goto err5;
211
212 return 0;
213
214err5:
215 phy_driver_unregister(&ks8041_driver);
216err4:
217 phy_driver_unregister(&ks8737_driver);
218err3:
219 phy_driver_unregister(&ksz9021_driver);
220err2:
221 phy_driver_unregister(&ks8001_driver);
222err1:
223 return ret;
224}
225
226static void __exit ksphy_exit(void)
227{
228 phy_driver_unregister(&ks8001_driver);
229 phy_driver_unregister(&ks8737_driver);
230 phy_driver_unregister(&ksz9021_driver);
231 phy_driver_unregister(&ks8041_driver);
232 phy_driver_unregister(&ks8051_driver);
233}
234
235module_init(ksphy_init);
236module_exit(ksphy_exit);
237
238MODULE_DESCRIPTION("Micrel PHY driver");
239MODULE_AUTHOR("David J. Choi");
240MODULE_LICENSE("GPL");
241
242static struct mdio_device_id __maybe_unused micrel_tbl[] = {
243 { PHY_ID_KSZ9021, 0x000fff10 },
244 { PHY_ID_KS8001, 0x00fffff0 },
245 { PHY_ID_KS8737, 0x00fffff0 },
246 { PHY_ID_KS8041, 0x00fffff0 },
247 { PHY_ID_KS8051, 0x00fffff0 },
248 { }
249};
250
251MODULE_DEVICE_TABLE(mdio, micrel_tbl);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/micrel.c
4 *
5 * Driver for Micrel PHYs
6 *
7 * Author: David J. Choi
8 *
9 * Copyright (c) 2010-2013 Micrel, Inc.
10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11 *
12 * Support : Micrel Phys:
13 * Giga phys: ksz9021, ksz9031, ksz9131, lan8841, lan8814
14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
15 * ksz8021, ksz8031, ksz8051,
16 * ksz8081, ksz8091,
17 * ksz8061,
18 * Switch : ksz8873, ksz886x
19 * ksz9477, lan8804
20 */
21
22#include <linux/bitfield.h>
23#include <linux/ethtool_netlink.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/phy.h>
27#include <linux/micrel_phy.h>
28#include <linux/of.h>
29#include <linux/clk.h>
30#include <linux/delay.h>
31#include <linux/ptp_clock_kernel.h>
32#include <linux/ptp_clock.h>
33#include <linux/ptp_classify.h>
34#include <linux/net_tstamp.h>
35#include <linux/gpio/consumer.h>
36
37/* Operation Mode Strap Override */
38#define MII_KSZPHY_OMSO 0x16
39#define KSZPHY_OMSO_FACTORY_TEST BIT(15)
40#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
41#define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
42#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
43#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
44
45/* general Interrupt control/status reg in vendor specific block. */
46#define MII_KSZPHY_INTCS 0x1B
47#define KSZPHY_INTCS_JABBER BIT(15)
48#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
49#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
50#define KSZPHY_INTCS_PARELLEL BIT(12)
51#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
52#define KSZPHY_INTCS_LINK_DOWN BIT(10)
53#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
54#define KSZPHY_INTCS_LINK_UP BIT(8)
55#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
56 KSZPHY_INTCS_LINK_DOWN)
57#define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2)
58#define KSZPHY_INTCS_LINK_UP_STATUS BIT(0)
59#define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\
60 KSZPHY_INTCS_LINK_UP_STATUS)
61
62/* LinkMD Control/Status */
63#define KSZ8081_LMD 0x1d
64#define KSZ8081_LMD_ENABLE_TEST BIT(15)
65#define KSZ8081_LMD_STAT_NORMAL 0
66#define KSZ8081_LMD_STAT_OPEN 1
67#define KSZ8081_LMD_STAT_SHORT 2
68#define KSZ8081_LMD_STAT_FAIL 3
69#define KSZ8081_LMD_STAT_MASK GENMASK(14, 13)
70/* Short cable (<10 meter) has been detected by LinkMD */
71#define KSZ8081_LMD_SHORT_INDICATOR BIT(12)
72#define KSZ8081_LMD_DELTA_TIME_MASK GENMASK(8, 0)
73
74#define KSZ9x31_LMD 0x12
75#define KSZ9x31_LMD_VCT_EN BIT(15)
76#define KSZ9x31_LMD_VCT_DIS_TX BIT(14)
77#define KSZ9x31_LMD_VCT_PAIR(n) (((n) & 0x3) << 12)
78#define KSZ9x31_LMD_VCT_SEL_RESULT 0
79#define KSZ9x31_LMD_VCT_SEL_THRES_HI BIT(10)
80#define KSZ9x31_LMD_VCT_SEL_THRES_LO BIT(11)
81#define KSZ9x31_LMD_VCT_SEL_MASK GENMASK(11, 10)
82#define KSZ9x31_LMD_VCT_ST_NORMAL 0
83#define KSZ9x31_LMD_VCT_ST_OPEN 1
84#define KSZ9x31_LMD_VCT_ST_SHORT 2
85#define KSZ9x31_LMD_VCT_ST_FAIL 3
86#define KSZ9x31_LMD_VCT_ST_MASK GENMASK(9, 8)
87#define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID BIT(7)
88#define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG BIT(6)
89#define KSZ9x31_LMD_VCT_DATA_MASK100 BIT(5)
90#define KSZ9x31_LMD_VCT_DATA_NLP_FLP BIT(4)
91#define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK GENMASK(3, 2)
92#define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK GENMASK(1, 0)
93#define KSZ9x31_LMD_VCT_DATA_MASK GENMASK(7, 0)
94
95#define KSZPHY_WIRE_PAIR_MASK 0x3
96
97#define LAN8814_CABLE_DIAG 0x12
98#define LAN8814_CABLE_DIAG_STAT_MASK GENMASK(9, 8)
99#define LAN8814_CABLE_DIAG_VCT_DATA_MASK GENMASK(7, 0)
100#define LAN8814_PAIR_BIT_SHIFT 12
101
102#define LAN8814_WIRE_PAIR_MASK 0xF
103
104/* Lan8814 general Interrupt control/status reg in GPHY specific block. */
105#define LAN8814_INTC 0x18
106#define LAN8814_INTS 0x1B
107
108#define LAN8814_INT_LINK_DOWN BIT(2)
109#define LAN8814_INT_LINK_UP BIT(0)
110#define LAN8814_INT_LINK (LAN8814_INT_LINK_UP |\
111 LAN8814_INT_LINK_DOWN)
112
113#define LAN8814_INTR_CTRL_REG 0x34
114#define LAN8814_INTR_CTRL_REG_POLARITY BIT(1)
115#define LAN8814_INTR_CTRL_REG_INTR_ENABLE BIT(0)
116
117#define LAN8814_EEE_STATE 0x38
118#define LAN8814_EEE_STATE_MASK2P5P BIT(10)
119
120#define LAN8814_PD_CONTROLS 0x9d
121#define LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK GENMASK(3, 0)
122#define LAN8814_PD_CONTROLS_PD_MEAS_TIME_VAL 0xb
123
124/* Represents 1ppm adjustment in 2^32 format with
125 * each nsec contains 4 clock cycles.
126 * The value is calculated as following: (1/1000000)/((2^-32)/4)
127 */
128#define LAN8814_1PPM_FORMAT 17179
129
130/* Represents 1ppm adjustment in 2^32 format with
131 * each nsec contains 8 clock cycles.
132 * The value is calculated as following: (1/1000000)/((2^-32)/8)
133 */
134#define LAN8841_1PPM_FORMAT 34360
135
136#define PTP_RX_VERSION 0x0248
137#define PTP_TX_VERSION 0x0288
138#define PTP_MAX_VERSION(x) (((x) & GENMASK(7, 0)) << 8)
139#define PTP_MIN_VERSION(x) ((x) & GENMASK(7, 0))
140
141#define PTP_RX_MOD 0x024F
142#define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
143#define PTP_RX_TIMESTAMP_EN 0x024D
144#define PTP_TX_TIMESTAMP_EN 0x028D
145
146#define PTP_TIMESTAMP_EN_SYNC_ BIT(0)
147#define PTP_TIMESTAMP_EN_DREQ_ BIT(1)
148#define PTP_TIMESTAMP_EN_PDREQ_ BIT(2)
149#define PTP_TIMESTAMP_EN_PDRES_ BIT(3)
150
151#define PTP_TX_PARSE_L2_ADDR_EN 0x0284
152#define PTP_RX_PARSE_L2_ADDR_EN 0x0244
153
154#define PTP_TX_PARSE_IP_ADDR_EN 0x0285
155#define PTP_RX_PARSE_IP_ADDR_EN 0x0245
156#define LTC_HARD_RESET 0x023F
157#define LTC_HARD_RESET_ BIT(0)
158
159#define TSU_HARD_RESET 0x02C1
160#define TSU_HARD_RESET_ BIT(0)
161
162#define PTP_CMD_CTL 0x0200
163#define PTP_CMD_CTL_PTP_DISABLE_ BIT(0)
164#define PTP_CMD_CTL_PTP_ENABLE_ BIT(1)
165#define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3)
166#define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)
167#define PTP_CMD_CTL_PTP_LTC_STEP_SEC_ BIT(5)
168#define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_ BIT(6)
169
170#define PTP_CLOCK_SET_SEC_HI 0x0205
171#define PTP_CLOCK_SET_SEC_MID 0x0206
172#define PTP_CLOCK_SET_SEC_LO 0x0207
173#define PTP_CLOCK_SET_NS_HI 0x0208
174#define PTP_CLOCK_SET_NS_LO 0x0209
175
176#define PTP_CLOCK_READ_SEC_HI 0x0229
177#define PTP_CLOCK_READ_SEC_MID 0x022A
178#define PTP_CLOCK_READ_SEC_LO 0x022B
179#define PTP_CLOCK_READ_NS_HI 0x022C
180#define PTP_CLOCK_READ_NS_LO 0x022D
181
182#define PTP_OPERATING_MODE 0x0241
183#define PTP_OPERATING_MODE_STANDALONE_ BIT(0)
184
185#define PTP_TX_MOD 0x028F
186#define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ BIT(12)
187#define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
188
189#define PTP_RX_PARSE_CONFIG 0x0242
190#define PTP_RX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
191#define PTP_RX_PARSE_CONFIG_IPV4_EN_ BIT(1)
192#define PTP_RX_PARSE_CONFIG_IPV6_EN_ BIT(2)
193
194#define PTP_TX_PARSE_CONFIG 0x0282
195#define PTP_TX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
196#define PTP_TX_PARSE_CONFIG_IPV4_EN_ BIT(1)
197#define PTP_TX_PARSE_CONFIG_IPV6_EN_ BIT(2)
198
199#define PTP_CLOCK_RATE_ADJ_HI 0x020C
200#define PTP_CLOCK_RATE_ADJ_LO 0x020D
201#define PTP_CLOCK_RATE_ADJ_DIR_ BIT(15)
202
203#define PTP_LTC_STEP_ADJ_HI 0x0212
204#define PTP_LTC_STEP_ADJ_LO 0x0213
205#define PTP_LTC_STEP_ADJ_DIR_ BIT(15)
206
207#define LAN8814_INTR_STS_REG 0x0033
208#define LAN8814_INTR_STS_REG_1588_TSU0_ BIT(0)
209#define LAN8814_INTR_STS_REG_1588_TSU1_ BIT(1)
210#define LAN8814_INTR_STS_REG_1588_TSU2_ BIT(2)
211#define LAN8814_INTR_STS_REG_1588_TSU3_ BIT(3)
212
213#define PTP_CAP_INFO 0x022A
214#define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x0f00) >> 8)
215#define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val) ((reg_val) & 0x000f)
216
217#define PTP_TX_EGRESS_SEC_HI 0x0296
218#define PTP_TX_EGRESS_SEC_LO 0x0297
219#define PTP_TX_EGRESS_NS_HI 0x0294
220#define PTP_TX_EGRESS_NS_LO 0x0295
221#define PTP_TX_MSG_HEADER2 0x0299
222
223#define PTP_RX_INGRESS_SEC_HI 0x0256
224#define PTP_RX_INGRESS_SEC_LO 0x0257
225#define PTP_RX_INGRESS_NS_HI 0x0254
226#define PTP_RX_INGRESS_NS_LO 0x0255
227#define PTP_RX_MSG_HEADER2 0x0259
228
229#define PTP_TSU_INT_EN 0x0200
230#define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ BIT(3)
231#define PTP_TSU_INT_EN_PTP_TX_TS_EN_ BIT(2)
232#define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_ BIT(1)
233#define PTP_TSU_INT_EN_PTP_RX_TS_EN_ BIT(0)
234
235#define PTP_TSU_INT_STS 0x0201
236#define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_ BIT(3)
237#define PTP_TSU_INT_STS_PTP_TX_TS_EN_ BIT(2)
238#define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_ BIT(1)
239#define PTP_TSU_INT_STS_PTP_RX_TS_EN_ BIT(0)
240
241#define LAN8814_LED_CTRL_1 0x0
242#define LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_ BIT(6)
243
244/* PHY Control 1 */
245#define MII_KSZPHY_CTRL_1 0x1e
246#define KSZ8081_CTRL1_MDIX_STAT BIT(4)
247
248/* PHY Control 2 / PHY Control (if no PHY Control 1) */
249#define MII_KSZPHY_CTRL_2 0x1f
250#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
251/* bitmap of PHY register to set interrupt mode */
252#define KSZ8081_CTRL2_HP_MDIX BIT(15)
253#define KSZ8081_CTRL2_MDI_MDI_X_SELECT BIT(14)
254#define KSZ8081_CTRL2_DISABLE_AUTO_MDIX BIT(13)
255#define KSZ8081_CTRL2_FORCE_LINK BIT(11)
256#define KSZ8081_CTRL2_POWER_SAVING BIT(10)
257#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
258#define KSZPHY_RMII_REF_CLK_SEL BIT(7)
259
260/* Write/read to/from extended registers */
261#define MII_KSZPHY_EXTREG 0x0b
262#define KSZPHY_EXTREG_WRITE 0x8000
263
264#define MII_KSZPHY_EXTREG_WRITE 0x0c
265#define MII_KSZPHY_EXTREG_READ 0x0d
266
267/* Extended registers */
268#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
269#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
270#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
271
272#define PS_TO_REG 200
273#define FIFO_SIZE 8
274
275/* Delay used to get the second part from the LTC */
276#define LAN8841_GET_SEC_LTC_DELAY (500 * NSEC_PER_MSEC)
277
278struct kszphy_hw_stat {
279 const char *string;
280 u8 reg;
281 u8 bits;
282};
283
284static struct kszphy_hw_stat kszphy_hw_stats[] = {
285 { "phy_receive_errors", 21, 16},
286 { "phy_idle_errors", 10, 8 },
287};
288
289struct kszphy_type {
290 u32 led_mode_reg;
291 u16 interrupt_level_mask;
292 u16 cable_diag_reg;
293 unsigned long pair_mask;
294 u16 disable_dll_tx_bit;
295 u16 disable_dll_rx_bit;
296 u16 disable_dll_mask;
297 bool has_broadcast_disable;
298 bool has_nand_tree_disable;
299 bool has_rmii_ref_clk_sel;
300};
301
302/* Shared structure between the PHYs of the same package. */
303struct lan8814_shared_priv {
304 struct phy_device *phydev;
305 struct ptp_clock *ptp_clock;
306 struct ptp_clock_info ptp_clock_info;
307
308 /* Reference counter to how many ports in the package are enabling the
309 * timestamping
310 */
311 u8 ref;
312
313 /* Lock for ptp_clock and ref */
314 struct mutex shared_lock;
315};
316
317struct lan8814_ptp_rx_ts {
318 struct list_head list;
319 u32 seconds;
320 u32 nsec;
321 u16 seq_id;
322};
323
324struct kszphy_ptp_priv {
325 struct mii_timestamper mii_ts;
326 struct phy_device *phydev;
327
328 struct sk_buff_head tx_queue;
329 struct sk_buff_head rx_queue;
330
331 struct list_head rx_ts_list;
332 /* Lock for Rx ts fifo */
333 spinlock_t rx_ts_lock;
334
335 int hwts_tx_type;
336 enum hwtstamp_rx_filters rx_filter;
337 int layer;
338 int version;
339
340 struct ptp_clock *ptp_clock;
341 struct ptp_clock_info ptp_clock_info;
342 /* Lock for ptp_clock */
343 struct mutex ptp_lock;
344 struct ptp_pin_desc *pin_config;
345
346 s64 seconds;
347 /* Lock for accessing seconds */
348 spinlock_t seconds_lock;
349};
350
351struct kszphy_priv {
352 struct kszphy_ptp_priv ptp_priv;
353 const struct kszphy_type *type;
354 int led_mode;
355 u16 vct_ctrl1000;
356 bool rmii_ref_clk_sel;
357 bool rmii_ref_clk_sel_val;
358 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
359};
360
361static const struct kszphy_type lan8814_type = {
362 .led_mode_reg = ~LAN8814_LED_CTRL_1,
363 .cable_diag_reg = LAN8814_CABLE_DIAG,
364 .pair_mask = LAN8814_WIRE_PAIR_MASK,
365};
366
367static const struct kszphy_type ksz886x_type = {
368 .cable_diag_reg = KSZ8081_LMD,
369 .pair_mask = KSZPHY_WIRE_PAIR_MASK,
370};
371
372static const struct kszphy_type ksz8021_type = {
373 .led_mode_reg = MII_KSZPHY_CTRL_2,
374 .has_broadcast_disable = true,
375 .has_nand_tree_disable = true,
376 .has_rmii_ref_clk_sel = true,
377};
378
379static const struct kszphy_type ksz8041_type = {
380 .led_mode_reg = MII_KSZPHY_CTRL_1,
381};
382
383static const struct kszphy_type ksz8051_type = {
384 .led_mode_reg = MII_KSZPHY_CTRL_2,
385 .has_nand_tree_disable = true,
386};
387
388static const struct kszphy_type ksz8081_type = {
389 .led_mode_reg = MII_KSZPHY_CTRL_2,
390 .has_broadcast_disable = true,
391 .has_nand_tree_disable = true,
392 .has_rmii_ref_clk_sel = true,
393};
394
395static const struct kszphy_type ks8737_type = {
396 .interrupt_level_mask = BIT(14),
397};
398
399static const struct kszphy_type ksz9021_type = {
400 .interrupt_level_mask = BIT(14),
401};
402
403static const struct kszphy_type ksz9131_type = {
404 .interrupt_level_mask = BIT(14),
405 .disable_dll_tx_bit = BIT(12),
406 .disable_dll_rx_bit = BIT(12),
407 .disable_dll_mask = BIT_MASK(12),
408};
409
410static const struct kszphy_type lan8841_type = {
411 .disable_dll_tx_bit = BIT(14),
412 .disable_dll_rx_bit = BIT(14),
413 .disable_dll_mask = BIT_MASK(14),
414 .cable_diag_reg = LAN8814_CABLE_DIAG,
415 .pair_mask = LAN8814_WIRE_PAIR_MASK,
416};
417
418static int kszphy_extended_write(struct phy_device *phydev,
419 u32 regnum, u16 val)
420{
421 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
422 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
423}
424
425static int kszphy_extended_read(struct phy_device *phydev,
426 u32 regnum)
427{
428 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
429 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
430}
431
432static int kszphy_ack_interrupt(struct phy_device *phydev)
433{
434 /* bit[7..0] int status, which is a read and clear register. */
435 int rc;
436
437 rc = phy_read(phydev, MII_KSZPHY_INTCS);
438
439 return (rc < 0) ? rc : 0;
440}
441
442static int kszphy_config_intr(struct phy_device *phydev)
443{
444 const struct kszphy_type *type = phydev->drv->driver_data;
445 int temp, err;
446 u16 mask;
447
448 if (type && type->interrupt_level_mask)
449 mask = type->interrupt_level_mask;
450 else
451 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
452
453 /* set the interrupt pin active low */
454 temp = phy_read(phydev, MII_KSZPHY_CTRL);
455 if (temp < 0)
456 return temp;
457 temp &= ~mask;
458 phy_write(phydev, MII_KSZPHY_CTRL, temp);
459
460 /* enable / disable interrupts */
461 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
462 err = kszphy_ack_interrupt(phydev);
463 if (err)
464 return err;
465
466 err = phy_write(phydev, MII_KSZPHY_INTCS, KSZPHY_INTCS_ALL);
467 } else {
468 err = phy_write(phydev, MII_KSZPHY_INTCS, 0);
469 if (err)
470 return err;
471
472 err = kszphy_ack_interrupt(phydev);
473 }
474
475 return err;
476}
477
478static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
479{
480 int irq_status;
481
482 irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
483 if (irq_status < 0) {
484 phy_error(phydev);
485 return IRQ_NONE;
486 }
487
488 if (!(irq_status & KSZPHY_INTCS_STATUS))
489 return IRQ_NONE;
490
491 phy_trigger_machine(phydev);
492
493 return IRQ_HANDLED;
494}
495
496static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
497{
498 int ctrl;
499
500 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
501 if (ctrl < 0)
502 return ctrl;
503
504 if (val)
505 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
506 else
507 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
508
509 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
510}
511
512static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
513{
514 int rc, temp, shift;
515
516 switch (reg) {
517 case MII_KSZPHY_CTRL_1:
518 shift = 14;
519 break;
520 case MII_KSZPHY_CTRL_2:
521 shift = 4;
522 break;
523 default:
524 return -EINVAL;
525 }
526
527 temp = phy_read(phydev, reg);
528 if (temp < 0) {
529 rc = temp;
530 goto out;
531 }
532
533 temp &= ~(3 << shift);
534 temp |= val << shift;
535 rc = phy_write(phydev, reg, temp);
536out:
537 if (rc < 0)
538 phydev_err(phydev, "failed to set led mode\n");
539
540 return rc;
541}
542
543/* Disable PHY address 0 as the broadcast address, so that it can be used as a
544 * unique (non-broadcast) address on a shared bus.
545 */
546static int kszphy_broadcast_disable(struct phy_device *phydev)
547{
548 int ret;
549
550 ret = phy_read(phydev, MII_KSZPHY_OMSO);
551 if (ret < 0)
552 goto out;
553
554 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
555out:
556 if (ret)
557 phydev_err(phydev, "failed to disable broadcast address\n");
558
559 return ret;
560}
561
562static int kszphy_nand_tree_disable(struct phy_device *phydev)
563{
564 int ret;
565
566 ret = phy_read(phydev, MII_KSZPHY_OMSO);
567 if (ret < 0)
568 goto out;
569
570 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
571 return 0;
572
573 ret = phy_write(phydev, MII_KSZPHY_OMSO,
574 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
575out:
576 if (ret)
577 phydev_err(phydev, "failed to disable NAND tree mode\n");
578
579 return ret;
580}
581
582/* Some config bits need to be set again on resume, handle them here. */
583static int kszphy_config_reset(struct phy_device *phydev)
584{
585 struct kszphy_priv *priv = phydev->priv;
586 int ret;
587
588 if (priv->rmii_ref_clk_sel) {
589 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
590 if (ret) {
591 phydev_err(phydev,
592 "failed to set rmii reference clock\n");
593 return ret;
594 }
595 }
596
597 if (priv->type && priv->led_mode >= 0)
598 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
599
600 return 0;
601}
602
603static int kszphy_config_init(struct phy_device *phydev)
604{
605 struct kszphy_priv *priv = phydev->priv;
606 const struct kszphy_type *type;
607
608 if (!priv)
609 return 0;
610
611 type = priv->type;
612
613 if (type && type->has_broadcast_disable)
614 kszphy_broadcast_disable(phydev);
615
616 if (type && type->has_nand_tree_disable)
617 kszphy_nand_tree_disable(phydev);
618
619 return kszphy_config_reset(phydev);
620}
621
622static int ksz8041_fiber_mode(struct phy_device *phydev)
623{
624 struct device_node *of_node = phydev->mdio.dev.of_node;
625
626 return of_property_read_bool(of_node, "micrel,fiber-mode");
627}
628
629static int ksz8041_config_init(struct phy_device *phydev)
630{
631 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
632
633 /* Limit supported and advertised modes in fiber mode */
634 if (ksz8041_fiber_mode(phydev)) {
635 phydev->dev_flags |= MICREL_PHY_FXEN;
636 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
637 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
638
639 linkmode_and(phydev->supported, phydev->supported, mask);
640 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
641 phydev->supported);
642 linkmode_and(phydev->advertising, phydev->advertising, mask);
643 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
644 phydev->advertising);
645 phydev->autoneg = AUTONEG_DISABLE;
646 }
647
648 return kszphy_config_init(phydev);
649}
650
651static int ksz8041_config_aneg(struct phy_device *phydev)
652{
653 /* Skip auto-negotiation in fiber mode */
654 if (phydev->dev_flags & MICREL_PHY_FXEN) {
655 phydev->speed = SPEED_100;
656 return 0;
657 }
658
659 return genphy_config_aneg(phydev);
660}
661
662static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
663 const bool ksz_8051)
664{
665 int ret;
666
667 if (!phy_id_compare(phydev->phy_id, PHY_ID_KSZ8051, MICREL_PHY_ID_MASK))
668 return 0;
669
670 ret = phy_read(phydev, MII_BMSR);
671 if (ret < 0)
672 return ret;
673
674 /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
675 * exact PHY ID. However, they can be told apart by the extended
676 * capability registers presence. The KSZ8051 PHY has them while
677 * the switch does not.
678 */
679 ret &= BMSR_ERCAP;
680 if (ksz_8051)
681 return ret;
682 else
683 return !ret;
684}
685
686static int ksz8051_match_phy_device(struct phy_device *phydev)
687{
688 return ksz8051_ksz8795_match_phy_device(phydev, true);
689}
690
691static int ksz8081_config_init(struct phy_device *phydev)
692{
693 /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
694 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
695 * pull-down is missing, the factory test mode should be cleared by
696 * manually writing a 0.
697 */
698 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
699
700 return kszphy_config_init(phydev);
701}
702
703static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
704{
705 u16 val;
706
707 switch (ctrl) {
708 case ETH_TP_MDI:
709 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
710 break;
711 case ETH_TP_MDI_X:
712 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
713 KSZ8081_CTRL2_MDI_MDI_X_SELECT;
714 break;
715 case ETH_TP_MDI_AUTO:
716 val = 0;
717 break;
718 default:
719 return 0;
720 }
721
722 return phy_modify(phydev, MII_KSZPHY_CTRL_2,
723 KSZ8081_CTRL2_HP_MDIX |
724 KSZ8081_CTRL2_MDI_MDI_X_SELECT |
725 KSZ8081_CTRL2_DISABLE_AUTO_MDIX,
726 KSZ8081_CTRL2_HP_MDIX | val);
727}
728
729static int ksz8081_config_aneg(struct phy_device *phydev)
730{
731 int ret;
732
733 ret = genphy_config_aneg(phydev);
734 if (ret)
735 return ret;
736
737 /* The MDI-X configuration is automatically changed by the PHY after
738 * switching from autoneg off to on. So, take MDI-X configuration under
739 * own control and set it after autoneg configuration was done.
740 */
741 return ksz8081_config_mdix(phydev, phydev->mdix_ctrl);
742}
743
744static int ksz8081_mdix_update(struct phy_device *phydev)
745{
746 int ret;
747
748 ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
749 if (ret < 0)
750 return ret;
751
752 if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {
753 if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)
754 phydev->mdix_ctrl = ETH_TP_MDI_X;
755 else
756 phydev->mdix_ctrl = ETH_TP_MDI;
757 } else {
758 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
759 }
760
761 ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
762 if (ret < 0)
763 return ret;
764
765 if (ret & KSZ8081_CTRL1_MDIX_STAT)
766 phydev->mdix = ETH_TP_MDI;
767 else
768 phydev->mdix = ETH_TP_MDI_X;
769
770 return 0;
771}
772
773static int ksz8081_read_status(struct phy_device *phydev)
774{
775 int ret;
776
777 ret = ksz8081_mdix_update(phydev);
778 if (ret < 0)
779 return ret;
780
781 return genphy_read_status(phydev);
782}
783
784static int ksz8061_config_init(struct phy_device *phydev)
785{
786 int ret;
787
788 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
789 if (ret)
790 return ret;
791
792 return kszphy_config_init(phydev);
793}
794
795static int ksz8795_match_phy_device(struct phy_device *phydev)
796{
797 return ksz8051_ksz8795_match_phy_device(phydev, false);
798}
799
800static int ksz9021_load_values_from_of(struct phy_device *phydev,
801 const struct device_node *of_node,
802 u16 reg,
803 const char *field1, const char *field2,
804 const char *field3, const char *field4)
805{
806 int val1 = -1;
807 int val2 = -2;
808 int val3 = -3;
809 int val4 = -4;
810 int newval;
811 int matches = 0;
812
813 if (!of_property_read_u32(of_node, field1, &val1))
814 matches++;
815
816 if (!of_property_read_u32(of_node, field2, &val2))
817 matches++;
818
819 if (!of_property_read_u32(of_node, field3, &val3))
820 matches++;
821
822 if (!of_property_read_u32(of_node, field4, &val4))
823 matches++;
824
825 if (!matches)
826 return 0;
827
828 if (matches < 4)
829 newval = kszphy_extended_read(phydev, reg);
830 else
831 newval = 0;
832
833 if (val1 != -1)
834 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
835
836 if (val2 != -2)
837 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
838
839 if (val3 != -3)
840 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
841
842 if (val4 != -4)
843 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
844
845 return kszphy_extended_write(phydev, reg, newval);
846}
847
848static int ksz9021_config_init(struct phy_device *phydev)
849{
850 const struct device_node *of_node;
851 const struct device *dev_walker;
852
853 /* The Micrel driver has a deprecated option to place phy OF
854 * properties in the MAC node. Walk up the tree of devices to
855 * find a device with an OF node.
856 */
857 dev_walker = &phydev->mdio.dev;
858 do {
859 of_node = dev_walker->of_node;
860 dev_walker = dev_walker->parent;
861
862 } while (!of_node && dev_walker);
863
864 if (of_node) {
865 ksz9021_load_values_from_of(phydev, of_node,
866 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
867 "txen-skew-ps", "txc-skew-ps",
868 "rxdv-skew-ps", "rxc-skew-ps");
869 ksz9021_load_values_from_of(phydev, of_node,
870 MII_KSZPHY_RX_DATA_PAD_SKEW,
871 "rxd0-skew-ps", "rxd1-skew-ps",
872 "rxd2-skew-ps", "rxd3-skew-ps");
873 ksz9021_load_values_from_of(phydev, of_node,
874 MII_KSZPHY_TX_DATA_PAD_SKEW,
875 "txd0-skew-ps", "txd1-skew-ps",
876 "txd2-skew-ps", "txd3-skew-ps");
877 }
878 return 0;
879}
880
881#define KSZ9031_PS_TO_REG 60
882
883/* Extended registers */
884/* MMD Address 0x0 */
885#define MII_KSZ9031RN_FLP_BURST_TX_LO 3
886#define MII_KSZ9031RN_FLP_BURST_TX_HI 4
887
888/* MMD Address 0x2 */
889#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
890#define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4)
891#define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0)
892
893#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
894#define MII_KSZ9031RN_RXD3 GENMASK(15, 12)
895#define MII_KSZ9031RN_RXD2 GENMASK(11, 8)
896#define MII_KSZ9031RN_RXD1 GENMASK(7, 4)
897#define MII_KSZ9031RN_RXD0 GENMASK(3, 0)
898
899#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
900#define MII_KSZ9031RN_TXD3 GENMASK(15, 12)
901#define MII_KSZ9031RN_TXD2 GENMASK(11, 8)
902#define MII_KSZ9031RN_TXD1 GENMASK(7, 4)
903#define MII_KSZ9031RN_TXD0 GENMASK(3, 0)
904
905#define MII_KSZ9031RN_CLK_PAD_SKEW 8
906#define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5)
907#define MII_KSZ9031RN_RX_CLK GENMASK(4, 0)
908
909/* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
910 * provide different RGMII options we need to configure delay offset
911 * for each pad relative to build in delay.
912 */
913/* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
914 * 1.80ns
915 */
916#define RX_ID 0x7
917#define RX_CLK_ID 0x19
918
919/* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
920 * internal 1.2ns delay.
921 */
922#define RX_ND 0xc
923#define RX_CLK_ND 0x0
924
925/* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
926#define TX_ID 0x0
927#define TX_CLK_ID 0x1f
928
929/* set tx and tx_clk to "No delay adjustment" to keep 0ns
930 * dealy
931 */
932#define TX_ND 0x7
933#define TX_CLK_ND 0xf
934
935/* MMD Address 0x1C */
936#define MII_KSZ9031RN_EDPD 0x23
937#define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
938
939static int ksz9031_of_load_skew_values(struct phy_device *phydev,
940 const struct device_node *of_node,
941 u16 reg, size_t field_sz,
942 const char *field[], u8 numfields,
943 bool *update)
944{
945 int val[4] = {-1, -2, -3, -4};
946 int matches = 0;
947 u16 mask;
948 u16 maxval;
949 u16 newval;
950 int i;
951
952 for (i = 0; i < numfields; i++)
953 if (!of_property_read_u32(of_node, field[i], val + i))
954 matches++;
955
956 if (!matches)
957 return 0;
958
959 *update |= true;
960
961 if (matches < numfields)
962 newval = phy_read_mmd(phydev, 2, reg);
963 else
964 newval = 0;
965
966 maxval = (field_sz == 4) ? 0xf : 0x1f;
967 for (i = 0; i < numfields; i++)
968 if (val[i] != -(i + 1)) {
969 mask = 0xffff;
970 mask ^= maxval << (field_sz * i);
971 newval = (newval & mask) |
972 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
973 << (field_sz * i));
974 }
975
976 return phy_write_mmd(phydev, 2, reg, newval);
977}
978
979/* Center KSZ9031RNX FLP timing at 16ms. */
980static int ksz9031_center_flp_timing(struct phy_device *phydev)
981{
982 int result;
983
984 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
985 0x0006);
986 if (result)
987 return result;
988
989 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
990 0x1A80);
991 if (result)
992 return result;
993
994 return genphy_restart_aneg(phydev);
995}
996
997/* Enable energy-detect power-down mode */
998static int ksz9031_enable_edpd(struct phy_device *phydev)
999{
1000 int reg;
1001
1002 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
1003 if (reg < 0)
1004 return reg;
1005 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
1006 reg | MII_KSZ9031RN_EDPD_ENABLE);
1007}
1008
1009static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
1010{
1011 u16 rx, tx, rx_clk, tx_clk;
1012 int ret;
1013
1014 switch (phydev->interface) {
1015 case PHY_INTERFACE_MODE_RGMII:
1016 tx = TX_ND;
1017 tx_clk = TX_CLK_ND;
1018 rx = RX_ND;
1019 rx_clk = RX_CLK_ND;
1020 break;
1021 case PHY_INTERFACE_MODE_RGMII_ID:
1022 tx = TX_ID;
1023 tx_clk = TX_CLK_ID;
1024 rx = RX_ID;
1025 rx_clk = RX_CLK_ID;
1026 break;
1027 case PHY_INTERFACE_MODE_RGMII_RXID:
1028 tx = TX_ND;
1029 tx_clk = TX_CLK_ND;
1030 rx = RX_ID;
1031 rx_clk = RX_CLK_ID;
1032 break;
1033 case PHY_INTERFACE_MODE_RGMII_TXID:
1034 tx = TX_ID;
1035 tx_clk = TX_CLK_ID;
1036 rx = RX_ND;
1037 rx_clk = RX_CLK_ND;
1038 break;
1039 default:
1040 return 0;
1041 }
1042
1043 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
1044 FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
1045 FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
1046 if (ret < 0)
1047 return ret;
1048
1049 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
1050 FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
1051 FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
1052 FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
1053 FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
1054 if (ret < 0)
1055 return ret;
1056
1057 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
1058 FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
1059 FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
1060 FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
1061 FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
1062 if (ret < 0)
1063 return ret;
1064
1065 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
1066 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
1067 FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
1068}
1069
1070static int ksz9031_config_init(struct phy_device *phydev)
1071{
1072 const struct device_node *of_node;
1073 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
1074 static const char *rx_data_skews[4] = {
1075 "rxd0-skew-ps", "rxd1-skew-ps",
1076 "rxd2-skew-ps", "rxd3-skew-ps"
1077 };
1078 static const char *tx_data_skews[4] = {
1079 "txd0-skew-ps", "txd1-skew-ps",
1080 "txd2-skew-ps", "txd3-skew-ps"
1081 };
1082 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
1083 const struct device *dev_walker;
1084 int result;
1085
1086 result = ksz9031_enable_edpd(phydev);
1087 if (result < 0)
1088 return result;
1089
1090 /* The Micrel driver has a deprecated option to place phy OF
1091 * properties in the MAC node. Walk up the tree of devices to
1092 * find a device with an OF node.
1093 */
1094 dev_walker = &phydev->mdio.dev;
1095 do {
1096 of_node = dev_walker->of_node;
1097 dev_walker = dev_walker->parent;
1098 } while (!of_node && dev_walker);
1099
1100 if (of_node) {
1101 bool update = false;
1102
1103 if (phy_interface_is_rgmii(phydev)) {
1104 result = ksz9031_config_rgmii_delay(phydev);
1105 if (result < 0)
1106 return result;
1107 }
1108
1109 ksz9031_of_load_skew_values(phydev, of_node,
1110 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1111 clk_skews, 2, &update);
1112
1113 ksz9031_of_load_skew_values(phydev, of_node,
1114 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1115 control_skews, 2, &update);
1116
1117 ksz9031_of_load_skew_values(phydev, of_node,
1118 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1119 rx_data_skews, 4, &update);
1120
1121 ksz9031_of_load_skew_values(phydev, of_node,
1122 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1123 tx_data_skews, 4, &update);
1124
1125 if (update && !phy_interface_is_rgmii(phydev))
1126 phydev_warn(phydev,
1127 "*-skew-ps values should be used only with RGMII PHY modes\n");
1128
1129 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1130 * When the device links in the 1000BASE-T slave mode only,
1131 * the optional 125MHz reference output clock (CLK125_NDO)
1132 * has wide duty cycle variation.
1133 *
1134 * The optional CLK125_NDO clock does not meet the RGMII
1135 * 45/55 percent (min/max) duty cycle requirement and therefore
1136 * cannot be used directly by the MAC side for clocking
1137 * applications that have setup/hold time requirements on
1138 * rising and falling clock edges.
1139 *
1140 * Workaround:
1141 * Force the phy to be the master to receive a stable clock
1142 * which meets the duty cycle requirement.
1143 */
1144 if (of_property_read_bool(of_node, "micrel,force-master")) {
1145 result = phy_read(phydev, MII_CTRL1000);
1146 if (result < 0)
1147 goto err_force_master;
1148
1149 /* enable master mode, config & prefer master */
1150 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
1151 result = phy_write(phydev, MII_CTRL1000, result);
1152 if (result < 0)
1153 goto err_force_master;
1154 }
1155 }
1156
1157 return ksz9031_center_flp_timing(phydev);
1158
1159err_force_master:
1160 phydev_err(phydev, "failed to force the phy to master mode\n");
1161 return result;
1162}
1163
1164#define KSZ9131_SKEW_5BIT_MAX 2400
1165#define KSZ9131_SKEW_4BIT_MAX 800
1166#define KSZ9131_OFFSET 700
1167#define KSZ9131_STEP 100
1168
1169static int ksz9131_of_load_skew_values(struct phy_device *phydev,
1170 struct device_node *of_node,
1171 u16 reg, size_t field_sz,
1172 char *field[], u8 numfields)
1173{
1174 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
1175 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
1176 int skewval, skewmax = 0;
1177 int matches = 0;
1178 u16 maxval;
1179 u16 newval;
1180 u16 mask;
1181 int i;
1182
1183 /* psec properties in dts should mean x pico seconds */
1184 if (field_sz == 5)
1185 skewmax = KSZ9131_SKEW_5BIT_MAX;
1186 else
1187 skewmax = KSZ9131_SKEW_4BIT_MAX;
1188
1189 for (i = 0; i < numfields; i++)
1190 if (!of_property_read_s32(of_node, field[i], &skewval)) {
1191 if (skewval < -KSZ9131_OFFSET)
1192 skewval = -KSZ9131_OFFSET;
1193 else if (skewval > skewmax)
1194 skewval = skewmax;
1195
1196 val[i] = skewval + KSZ9131_OFFSET;
1197 matches++;
1198 }
1199
1200 if (!matches)
1201 return 0;
1202
1203 if (matches < numfields)
1204 newval = phy_read_mmd(phydev, 2, reg);
1205 else
1206 newval = 0;
1207
1208 maxval = (field_sz == 4) ? 0xf : 0x1f;
1209 for (i = 0; i < numfields; i++)
1210 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
1211 mask = 0xffff;
1212 mask ^= maxval << (field_sz * i);
1213 newval = (newval & mask) |
1214 (((val[i] / KSZ9131_STEP) & maxval)
1215 << (field_sz * i));
1216 }
1217
1218 return phy_write_mmd(phydev, 2, reg, newval);
1219}
1220
1221#define KSZ9131RN_MMD_COMMON_CTRL_REG 2
1222#define KSZ9131RN_RXC_DLL_CTRL 76
1223#define KSZ9131RN_TXC_DLL_CTRL 77
1224#define KSZ9131RN_DLL_ENABLE_DELAY 0
1225
1226static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1227{
1228 const struct kszphy_type *type = phydev->drv->driver_data;
1229 u16 rxcdll_val, txcdll_val;
1230 int ret;
1231
1232 switch (phydev->interface) {
1233 case PHY_INTERFACE_MODE_RGMII:
1234 rxcdll_val = type->disable_dll_rx_bit;
1235 txcdll_val = type->disable_dll_tx_bit;
1236 break;
1237 case PHY_INTERFACE_MODE_RGMII_ID:
1238 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1239 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1240 break;
1241 case PHY_INTERFACE_MODE_RGMII_RXID:
1242 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1243 txcdll_val = type->disable_dll_tx_bit;
1244 break;
1245 case PHY_INTERFACE_MODE_RGMII_TXID:
1246 rxcdll_val = type->disable_dll_rx_bit;
1247 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1248 break;
1249 default:
1250 return 0;
1251 }
1252
1253 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1254 KSZ9131RN_RXC_DLL_CTRL, type->disable_dll_mask,
1255 rxcdll_val);
1256 if (ret < 0)
1257 return ret;
1258
1259 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1260 KSZ9131RN_TXC_DLL_CTRL, type->disable_dll_mask,
1261 txcdll_val);
1262}
1263
1264/* Silicon Errata DS80000693B
1265 *
1266 * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
1267 * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
1268 * according to the datasheet (off if there is no link).
1269 */
1270static int ksz9131_led_errata(struct phy_device *phydev)
1271{
1272 int reg;
1273
1274 reg = phy_read_mmd(phydev, 2, 0);
1275 if (reg < 0)
1276 return reg;
1277
1278 if (!(reg & BIT(4)))
1279 return 0;
1280
1281 return phy_set_bits(phydev, 0x1e, BIT(9));
1282}
1283
1284static int ksz9131_config_init(struct phy_device *phydev)
1285{
1286 struct device_node *of_node;
1287 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
1288 char *rx_data_skews[4] = {
1289 "rxd0-skew-psec", "rxd1-skew-psec",
1290 "rxd2-skew-psec", "rxd3-skew-psec"
1291 };
1292 char *tx_data_skews[4] = {
1293 "txd0-skew-psec", "txd1-skew-psec",
1294 "txd2-skew-psec", "txd3-skew-psec"
1295 };
1296 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
1297 const struct device *dev_walker;
1298 int ret;
1299
1300 dev_walker = &phydev->mdio.dev;
1301 do {
1302 of_node = dev_walker->of_node;
1303 dev_walker = dev_walker->parent;
1304 } while (!of_node && dev_walker);
1305
1306 if (!of_node)
1307 return 0;
1308
1309 if (phy_interface_is_rgmii(phydev)) {
1310 ret = ksz9131_config_rgmii_delay(phydev);
1311 if (ret < 0)
1312 return ret;
1313 }
1314
1315 ret = ksz9131_of_load_skew_values(phydev, of_node,
1316 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1317 clk_skews, 2);
1318 if (ret < 0)
1319 return ret;
1320
1321 ret = ksz9131_of_load_skew_values(phydev, of_node,
1322 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1323 control_skews, 2);
1324 if (ret < 0)
1325 return ret;
1326
1327 ret = ksz9131_of_load_skew_values(phydev, of_node,
1328 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1329 rx_data_skews, 4);
1330 if (ret < 0)
1331 return ret;
1332
1333 ret = ksz9131_of_load_skew_values(phydev, of_node,
1334 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1335 tx_data_skews, 4);
1336 if (ret < 0)
1337 return ret;
1338
1339 ret = ksz9131_led_errata(phydev);
1340 if (ret < 0)
1341 return ret;
1342
1343 return 0;
1344}
1345
1346#define MII_KSZ9131_AUTO_MDIX 0x1C
1347#define MII_KSZ9131_AUTO_MDI_SET BIT(7)
1348#define MII_KSZ9131_AUTO_MDIX_SWAP_OFF BIT(6)
1349
1350static int ksz9131_mdix_update(struct phy_device *phydev)
1351{
1352 int ret;
1353
1354 ret = phy_read(phydev, MII_KSZ9131_AUTO_MDIX);
1355 if (ret < 0)
1356 return ret;
1357
1358 if (ret & MII_KSZ9131_AUTO_MDIX_SWAP_OFF) {
1359 if (ret & MII_KSZ9131_AUTO_MDI_SET)
1360 phydev->mdix_ctrl = ETH_TP_MDI;
1361 else
1362 phydev->mdix_ctrl = ETH_TP_MDI_X;
1363 } else {
1364 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1365 }
1366
1367 if (ret & MII_KSZ9131_AUTO_MDI_SET)
1368 phydev->mdix = ETH_TP_MDI;
1369 else
1370 phydev->mdix = ETH_TP_MDI_X;
1371
1372 return 0;
1373}
1374
1375static int ksz9131_config_mdix(struct phy_device *phydev, u8 ctrl)
1376{
1377 u16 val;
1378
1379 switch (ctrl) {
1380 case ETH_TP_MDI:
1381 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1382 MII_KSZ9131_AUTO_MDI_SET;
1383 break;
1384 case ETH_TP_MDI_X:
1385 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF;
1386 break;
1387 case ETH_TP_MDI_AUTO:
1388 val = 0;
1389 break;
1390 default:
1391 return 0;
1392 }
1393
1394 return phy_modify(phydev, MII_KSZ9131_AUTO_MDIX,
1395 MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1396 MII_KSZ9131_AUTO_MDI_SET, val);
1397}
1398
1399static int ksz9131_read_status(struct phy_device *phydev)
1400{
1401 int ret;
1402
1403 ret = ksz9131_mdix_update(phydev);
1404 if (ret < 0)
1405 return ret;
1406
1407 return genphy_read_status(phydev);
1408}
1409
1410static int ksz9131_config_aneg(struct phy_device *phydev)
1411{
1412 int ret;
1413
1414 ret = ksz9131_config_mdix(phydev, phydev->mdix_ctrl);
1415 if (ret)
1416 return ret;
1417
1418 return genphy_config_aneg(phydev);
1419}
1420
1421static int ksz9477_get_features(struct phy_device *phydev)
1422{
1423 int ret;
1424
1425 ret = genphy_read_abilities(phydev);
1426 if (ret)
1427 return ret;
1428
1429 /* The "EEE control and capability 1" (Register 3.20) seems to be
1430 * influenced by the "EEE advertisement 1" (Register 7.60). Changes
1431 * on the 7.60 will affect 3.20. So, we need to construct our own list
1432 * of caps.
1433 * KSZ8563R should have 100BaseTX/Full only.
1434 */
1435 linkmode_and(phydev->supported_eee, phydev->supported,
1436 PHY_EEE_CAP1_FEATURES);
1437
1438 return 0;
1439}
1440
1441#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
1442#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
1443#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
1444static int ksz8873mll_read_status(struct phy_device *phydev)
1445{
1446 int regval;
1447
1448 /* dummy read */
1449 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1450
1451 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1452
1453 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
1454 phydev->duplex = DUPLEX_HALF;
1455 else
1456 phydev->duplex = DUPLEX_FULL;
1457
1458 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
1459 phydev->speed = SPEED_10;
1460 else
1461 phydev->speed = SPEED_100;
1462
1463 phydev->link = 1;
1464 phydev->pause = phydev->asym_pause = 0;
1465
1466 return 0;
1467}
1468
1469static int ksz9031_get_features(struct phy_device *phydev)
1470{
1471 int ret;
1472
1473 ret = genphy_read_abilities(phydev);
1474 if (ret < 0)
1475 return ret;
1476
1477 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1478 * Whenever the device's Asymmetric Pause capability is set to 1,
1479 * link-up may fail after a link-up to link-down transition.
1480 *
1481 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
1482 *
1483 * Workaround:
1484 * Do not enable the Asymmetric Pause capability bit.
1485 */
1486 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1487
1488 /* We force setting the Pause capability as the core will force the
1489 * Asymmetric Pause capability to 1 otherwise.
1490 */
1491 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1492
1493 return 0;
1494}
1495
1496static int ksz9031_read_status(struct phy_device *phydev)
1497{
1498 int err;
1499 int regval;
1500
1501 err = genphy_read_status(phydev);
1502 if (err)
1503 return err;
1504
1505 /* Make sure the PHY is not broken. Read idle error count,
1506 * and reset the PHY if it is maxed out.
1507 */
1508 regval = phy_read(phydev, MII_STAT1000);
1509 if ((regval & 0xFF) == 0xFF) {
1510 phy_init_hw(phydev);
1511 phydev->link = 0;
1512 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1513 phydev->drv->config_intr(phydev);
1514 return genphy_config_aneg(phydev);
1515 }
1516
1517 return 0;
1518}
1519
1520static int ksz9x31_cable_test_start(struct phy_device *phydev)
1521{
1522 struct kszphy_priv *priv = phydev->priv;
1523 int ret;
1524
1525 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1526 * Prior to running the cable diagnostics, Auto-negotiation should
1527 * be disabled, full duplex set and the link speed set to 1000Mbps
1528 * via the Basic Control Register.
1529 */
1530 ret = phy_modify(phydev, MII_BMCR,
1531 BMCR_SPEED1000 | BMCR_FULLDPLX |
1532 BMCR_ANENABLE | BMCR_SPEED100,
1533 BMCR_SPEED1000 | BMCR_FULLDPLX);
1534 if (ret)
1535 return ret;
1536
1537 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1538 * The Master-Slave configuration should be set to Slave by writing
1539 * a value of 0x1000 to the Auto-Negotiation Master Slave Control
1540 * Register.
1541 */
1542 ret = phy_read(phydev, MII_CTRL1000);
1543 if (ret < 0)
1544 return ret;
1545
1546 /* Cache these bits, they need to be restored once LinkMD finishes. */
1547 priv->vct_ctrl1000 = ret & (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1548 ret &= ~(CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1549 ret |= CTL1000_ENABLE_MASTER;
1550
1551 return phy_write(phydev, MII_CTRL1000, ret);
1552}
1553
1554static int ksz9x31_cable_test_result_trans(u16 status)
1555{
1556 switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1557 case KSZ9x31_LMD_VCT_ST_NORMAL:
1558 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1559 case KSZ9x31_LMD_VCT_ST_OPEN:
1560 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1561 case KSZ9x31_LMD_VCT_ST_SHORT:
1562 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1563 case KSZ9x31_LMD_VCT_ST_FAIL:
1564 fallthrough;
1565 default:
1566 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1567 }
1568}
1569
1570static bool ksz9x31_cable_test_failed(u16 status)
1571{
1572 int stat = FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status);
1573
1574 return stat == KSZ9x31_LMD_VCT_ST_FAIL;
1575}
1576
1577static bool ksz9x31_cable_test_fault_length_valid(u16 status)
1578{
1579 switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1580 case KSZ9x31_LMD_VCT_ST_OPEN:
1581 fallthrough;
1582 case KSZ9x31_LMD_VCT_ST_SHORT:
1583 return true;
1584 }
1585 return false;
1586}
1587
1588static int ksz9x31_cable_test_fault_length(struct phy_device *phydev, u16 stat)
1589{
1590 int dt = FIELD_GET(KSZ9x31_LMD_VCT_DATA_MASK, stat);
1591
1592 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1593 *
1594 * distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity
1595 */
1596 if (phydev_id_compare(phydev, PHY_ID_KSZ9131))
1597 dt = clamp(dt - 22, 0, 255);
1598
1599 return (dt * 400) / 10;
1600}
1601
1602static int ksz9x31_cable_test_wait_for_completion(struct phy_device *phydev)
1603{
1604 int val, ret;
1605
1606 ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val,
1607 !(val & KSZ9x31_LMD_VCT_EN),
1608 30000, 100000, true);
1609
1610 return ret < 0 ? ret : 0;
1611}
1612
1613static int ksz9x31_cable_test_get_pair(int pair)
1614{
1615 static const int ethtool_pair[] = {
1616 ETHTOOL_A_CABLE_PAIR_A,
1617 ETHTOOL_A_CABLE_PAIR_B,
1618 ETHTOOL_A_CABLE_PAIR_C,
1619 ETHTOOL_A_CABLE_PAIR_D,
1620 };
1621
1622 return ethtool_pair[pair];
1623}
1624
1625static int ksz9x31_cable_test_one_pair(struct phy_device *phydev, int pair)
1626{
1627 int ret, val;
1628
1629 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1630 * To test each individual cable pair, set the cable pair in the Cable
1631 * Diagnostics Test Pair (VCT_PAIR[1:0]) field of the LinkMD Cable
1632 * Diagnostic Register, along with setting the Cable Diagnostics Test
1633 * Enable (VCT_EN) bit. The Cable Diagnostics Test Enable (VCT_EN) bit
1634 * will self clear when the test is concluded.
1635 */
1636 ret = phy_write(phydev, KSZ9x31_LMD,
1637 KSZ9x31_LMD_VCT_EN | KSZ9x31_LMD_VCT_PAIR(pair));
1638 if (ret)
1639 return ret;
1640
1641 ret = ksz9x31_cable_test_wait_for_completion(phydev);
1642 if (ret)
1643 return ret;
1644
1645 val = phy_read(phydev, KSZ9x31_LMD);
1646 if (val < 0)
1647 return val;
1648
1649 if (ksz9x31_cable_test_failed(val))
1650 return -EAGAIN;
1651
1652 ret = ethnl_cable_test_result(phydev,
1653 ksz9x31_cable_test_get_pair(pair),
1654 ksz9x31_cable_test_result_trans(val));
1655 if (ret)
1656 return ret;
1657
1658 if (!ksz9x31_cable_test_fault_length_valid(val))
1659 return 0;
1660
1661 return ethnl_cable_test_fault_length(phydev,
1662 ksz9x31_cable_test_get_pair(pair),
1663 ksz9x31_cable_test_fault_length(phydev, val));
1664}
1665
1666static int ksz9x31_cable_test_get_status(struct phy_device *phydev,
1667 bool *finished)
1668{
1669 struct kszphy_priv *priv = phydev->priv;
1670 unsigned long pair_mask = 0xf;
1671 int retries = 20;
1672 int pair, ret, rv;
1673
1674 *finished = false;
1675
1676 /* Try harder if link partner is active */
1677 while (pair_mask && retries--) {
1678 for_each_set_bit(pair, &pair_mask, 4) {
1679 ret = ksz9x31_cable_test_one_pair(phydev, pair);
1680 if (ret == -EAGAIN)
1681 continue;
1682 if (ret < 0)
1683 return ret;
1684 clear_bit(pair, &pair_mask);
1685 }
1686 /* If link partner is in autonegotiation mode it will send 2ms
1687 * of FLPs with at least 6ms of silence.
1688 * Add 2ms sleep to have better chances to hit this silence.
1689 */
1690 if (pair_mask)
1691 usleep_range(2000, 3000);
1692 }
1693
1694 /* Report remaining unfinished pair result as unknown. */
1695 for_each_set_bit(pair, &pair_mask, 4) {
1696 ret = ethnl_cable_test_result(phydev,
1697 ksz9x31_cable_test_get_pair(pair),
1698 ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC);
1699 }
1700
1701 *finished = true;
1702
1703 /* Restore cached bits from before LinkMD got started. */
1704 rv = phy_modify(phydev, MII_CTRL1000,
1705 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER,
1706 priv->vct_ctrl1000);
1707 if (rv)
1708 return rv;
1709
1710 return ret;
1711}
1712
1713static int ksz8873mll_config_aneg(struct phy_device *phydev)
1714{
1715 return 0;
1716}
1717
1718static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1719{
1720 u16 val;
1721
1722 switch (ctrl) {
1723 case ETH_TP_MDI:
1724 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1725 break;
1726 case ETH_TP_MDI_X:
1727 /* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit
1728 * counter intuitive, the "-X" in "1 = Force MDI" in the data
1729 * sheet seems to be missing:
1730 * 1 = Force MDI (sic!) (transmit on RX+/RX- pins)
1731 * 0 = Normal operation (transmit on TX+/TX- pins)
1732 */
1733 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1734 break;
1735 case ETH_TP_MDI_AUTO:
1736 val = 0;
1737 break;
1738 default:
1739 return 0;
1740 }
1741
1742 return phy_modify(phydev, MII_BMCR,
1743 KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |
1744 KSZ886X_BMCR_DISABLE_AUTO_MDIX,
1745 KSZ886X_BMCR_HP_MDIX | val);
1746}
1747
1748static int ksz886x_config_aneg(struct phy_device *phydev)
1749{
1750 int ret;
1751
1752 ret = genphy_config_aneg(phydev);
1753 if (ret)
1754 return ret;
1755
1756 if (phydev->autoneg != AUTONEG_ENABLE) {
1757 /* When autonegotation is disabled, we need to manually force
1758 * the link state. If we don't do this, the PHY will keep
1759 * sending Fast Link Pulses (FLPs) which are part of the
1760 * autonegotiation process. This is not desired when
1761 * autonegotiation is off.
1762 */
1763 ret = phy_set_bits(phydev, MII_KSZPHY_CTRL,
1764 KSZ886X_CTRL_FORCE_LINK);
1765 if (ret)
1766 return ret;
1767 } else {
1768 /* If we had previously forced the link state, we need to
1769 * clear KSZ886X_CTRL_FORCE_LINK bit now. Otherwise, the PHY
1770 * will not perform autonegotiation.
1771 */
1772 ret = phy_clear_bits(phydev, MII_KSZPHY_CTRL,
1773 KSZ886X_CTRL_FORCE_LINK);
1774 if (ret)
1775 return ret;
1776 }
1777
1778 /* The MDI-X configuration is automatically changed by the PHY after
1779 * switching from autoneg off to on. So, take MDI-X configuration under
1780 * own control and set it after autoneg configuration was done.
1781 */
1782 return ksz886x_config_mdix(phydev, phydev->mdix_ctrl);
1783}
1784
1785static int ksz886x_mdix_update(struct phy_device *phydev)
1786{
1787 int ret;
1788
1789 ret = phy_read(phydev, MII_BMCR);
1790 if (ret < 0)
1791 return ret;
1792
1793 if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {
1794 if (ret & KSZ886X_BMCR_FORCE_MDI)
1795 phydev->mdix_ctrl = ETH_TP_MDI_X;
1796 else
1797 phydev->mdix_ctrl = ETH_TP_MDI;
1798 } else {
1799 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1800 }
1801
1802 ret = phy_read(phydev, MII_KSZPHY_CTRL);
1803 if (ret < 0)
1804 return ret;
1805
1806 /* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */
1807 if (ret & KSZ886X_CTRL_MDIX_STAT)
1808 phydev->mdix = ETH_TP_MDI_X;
1809 else
1810 phydev->mdix = ETH_TP_MDI;
1811
1812 return 0;
1813}
1814
1815static int ksz886x_read_status(struct phy_device *phydev)
1816{
1817 int ret;
1818
1819 ret = ksz886x_mdix_update(phydev);
1820 if (ret < 0)
1821 return ret;
1822
1823 return genphy_read_status(phydev);
1824}
1825
1826struct ksz9477_errata_write {
1827 u8 dev_addr;
1828 u8 reg_addr;
1829 u16 val;
1830};
1831
1832static const struct ksz9477_errata_write ksz9477_errata_writes[] = {
1833 /* Register settings are needed to improve PHY receive performance */
1834 {0x01, 0x6f, 0xdd0b},
1835 {0x01, 0x8f, 0x6032},
1836 {0x01, 0x9d, 0x248c},
1837 {0x01, 0x75, 0x0060},
1838 {0x01, 0xd3, 0x7777},
1839 {0x1c, 0x06, 0x3008},
1840 {0x1c, 0x08, 0x2000},
1841
1842 /* Transmit waveform amplitude can be improved (1000BASE-T, 100BASE-TX, 10BASE-Te) */
1843 {0x1c, 0x04, 0x00d0},
1844
1845 /* Register settings are required to meet data sheet supply current specifications */
1846 {0x1c, 0x13, 0x6eff},
1847 {0x1c, 0x14, 0xe6ff},
1848 {0x1c, 0x15, 0x6eff},
1849 {0x1c, 0x16, 0xe6ff},
1850 {0x1c, 0x17, 0x00ff},
1851 {0x1c, 0x18, 0x43ff},
1852 {0x1c, 0x19, 0xc3ff},
1853 {0x1c, 0x1a, 0x6fff},
1854 {0x1c, 0x1b, 0x07ff},
1855 {0x1c, 0x1c, 0x0fff},
1856 {0x1c, 0x1d, 0xe7ff},
1857 {0x1c, 0x1e, 0xefff},
1858 {0x1c, 0x20, 0xeeee},
1859};
1860
1861static int ksz9477_config_init(struct phy_device *phydev)
1862{
1863 int err;
1864 int i;
1865
1866 /* Apply PHY settings to address errata listed in
1867 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
1868 * Silicon Errata and Data Sheet Clarification documents.
1869 *
1870 * Document notes: Before configuring the PHY MMD registers, it is
1871 * necessary to set the PHY to 100 Mbps speed with auto-negotiation
1872 * disabled by writing to register 0xN100-0xN101. After writing the
1873 * MMD registers, and after all errata workarounds that involve PHY
1874 * register settings, write register 0xN100-0xN101 again to enable
1875 * and restart auto-negotiation.
1876 */
1877 err = phy_write(phydev, MII_BMCR, BMCR_SPEED100 | BMCR_FULLDPLX);
1878 if (err)
1879 return err;
1880
1881 for (i = 0; i < ARRAY_SIZE(ksz9477_errata_writes); ++i) {
1882 const struct ksz9477_errata_write *errata = &ksz9477_errata_writes[i];
1883
1884 err = phy_write_mmd(phydev, errata->dev_addr, errata->reg_addr, errata->val);
1885 if (err)
1886 return err;
1887 }
1888
1889 /* According to KSZ9477 Errata DS80000754C (Module 4) all EEE modes
1890 * in this switch shall be regarded as broken.
1891 */
1892 if (phydev->dev_flags & MICREL_NO_EEE)
1893 phydev->eee_broken_modes = -1;
1894
1895 err = genphy_restart_aneg(phydev);
1896 if (err)
1897 return err;
1898
1899 return kszphy_config_init(phydev);
1900}
1901
1902static int kszphy_get_sset_count(struct phy_device *phydev)
1903{
1904 return ARRAY_SIZE(kszphy_hw_stats);
1905}
1906
1907static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
1908{
1909 int i;
1910
1911 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
1912 strscpy(data + i * ETH_GSTRING_LEN,
1913 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
1914 }
1915}
1916
1917static u64 kszphy_get_stat(struct phy_device *phydev, int i)
1918{
1919 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
1920 struct kszphy_priv *priv = phydev->priv;
1921 int val;
1922 u64 ret;
1923
1924 val = phy_read(phydev, stat.reg);
1925 if (val < 0) {
1926 ret = U64_MAX;
1927 } else {
1928 val = val & ((1 << stat.bits) - 1);
1929 priv->stats[i] += val;
1930 ret = priv->stats[i];
1931 }
1932
1933 return ret;
1934}
1935
1936static void kszphy_get_stats(struct phy_device *phydev,
1937 struct ethtool_stats *stats, u64 *data)
1938{
1939 int i;
1940
1941 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
1942 data[i] = kszphy_get_stat(phydev, i);
1943}
1944
1945static int kszphy_suspend(struct phy_device *phydev)
1946{
1947 /* Disable PHY Interrupts */
1948 if (phy_interrupt_is_valid(phydev)) {
1949 phydev->interrupts = PHY_INTERRUPT_DISABLED;
1950 if (phydev->drv->config_intr)
1951 phydev->drv->config_intr(phydev);
1952 }
1953
1954 return genphy_suspend(phydev);
1955}
1956
1957static void kszphy_parse_led_mode(struct phy_device *phydev)
1958{
1959 const struct kszphy_type *type = phydev->drv->driver_data;
1960 const struct device_node *np = phydev->mdio.dev.of_node;
1961 struct kszphy_priv *priv = phydev->priv;
1962 int ret;
1963
1964 if (type && type->led_mode_reg) {
1965 ret = of_property_read_u32(np, "micrel,led-mode",
1966 &priv->led_mode);
1967
1968 if (ret)
1969 priv->led_mode = -1;
1970
1971 if (priv->led_mode > 3) {
1972 phydev_err(phydev, "invalid led mode: 0x%02x\n",
1973 priv->led_mode);
1974 priv->led_mode = -1;
1975 }
1976 } else {
1977 priv->led_mode = -1;
1978 }
1979}
1980
1981static int kszphy_resume(struct phy_device *phydev)
1982{
1983 int ret;
1984
1985 genphy_resume(phydev);
1986
1987 /* After switching from power-down to normal mode, an internal global
1988 * reset is automatically generated. Wait a minimum of 1 ms before
1989 * read/write access to the PHY registers.
1990 */
1991 usleep_range(1000, 2000);
1992
1993 ret = kszphy_config_reset(phydev);
1994 if (ret)
1995 return ret;
1996
1997 /* Enable PHY Interrupts */
1998 if (phy_interrupt_is_valid(phydev)) {
1999 phydev->interrupts = PHY_INTERRUPT_ENABLED;
2000 if (phydev->drv->config_intr)
2001 phydev->drv->config_intr(phydev);
2002 }
2003
2004 return 0;
2005}
2006
2007static int kszphy_probe(struct phy_device *phydev)
2008{
2009 const struct kszphy_type *type = phydev->drv->driver_data;
2010 const struct device_node *np = phydev->mdio.dev.of_node;
2011 struct kszphy_priv *priv;
2012 struct clk *clk;
2013
2014 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2015 if (!priv)
2016 return -ENOMEM;
2017
2018 phydev->priv = priv;
2019
2020 priv->type = type;
2021
2022 kszphy_parse_led_mode(phydev);
2023
2024 clk = devm_clk_get_optional_enabled(&phydev->mdio.dev, "rmii-ref");
2025 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
2026 if (!IS_ERR_OR_NULL(clk)) {
2027 unsigned long rate = clk_get_rate(clk);
2028 bool rmii_ref_clk_sel_25_mhz;
2029
2030 if (type)
2031 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
2032 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
2033 "micrel,rmii-reference-clock-select-25-mhz");
2034
2035 if (rate > 24500000 && rate < 25500000) {
2036 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
2037 } else if (rate > 49500000 && rate < 50500000) {
2038 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
2039 } else {
2040 phydev_err(phydev, "Clock rate out of range: %ld\n",
2041 rate);
2042 return -EINVAL;
2043 }
2044 } else if (!clk) {
2045 /* unnamed clock from the generic ethernet-phy binding */
2046 clk = devm_clk_get_optional_enabled(&phydev->mdio.dev, NULL);
2047 if (IS_ERR(clk))
2048 return PTR_ERR(clk);
2049 }
2050
2051 if (ksz8041_fiber_mode(phydev))
2052 phydev->port = PORT_FIBRE;
2053
2054 /* Support legacy board-file configuration */
2055 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
2056 priv->rmii_ref_clk_sel = true;
2057 priv->rmii_ref_clk_sel_val = true;
2058 }
2059
2060 return 0;
2061}
2062
2063static int lan8814_cable_test_start(struct phy_device *phydev)
2064{
2065 /* If autoneg is enabled, we won't be able to test cross pair
2066 * short. In this case, the PHY will "detect" a link and
2067 * confuse the internal state machine - disable auto neg here.
2068 * Set the speed to 1000mbit and full duplex.
2069 */
2070 return phy_modify(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100,
2071 BMCR_SPEED1000 | BMCR_FULLDPLX);
2072}
2073
2074static int ksz886x_cable_test_start(struct phy_device *phydev)
2075{
2076 if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
2077 return -EOPNOTSUPP;
2078
2079 /* If autoneg is enabled, we won't be able to test cross pair
2080 * short. In this case, the PHY will "detect" a link and
2081 * confuse the internal state machine - disable auto neg here.
2082 * If autoneg is disabled, we should set the speed to 10mbit.
2083 */
2084 return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
2085}
2086
2087static __always_inline int ksz886x_cable_test_result_trans(u16 status, u16 mask)
2088{
2089 switch (FIELD_GET(mask, status)) {
2090 case KSZ8081_LMD_STAT_NORMAL:
2091 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2092 case KSZ8081_LMD_STAT_SHORT:
2093 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2094 case KSZ8081_LMD_STAT_OPEN:
2095 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2096 case KSZ8081_LMD_STAT_FAIL:
2097 fallthrough;
2098 default:
2099 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2100 }
2101}
2102
2103static __always_inline bool ksz886x_cable_test_failed(u16 status, u16 mask)
2104{
2105 return FIELD_GET(mask, status) ==
2106 KSZ8081_LMD_STAT_FAIL;
2107}
2108
2109static __always_inline bool ksz886x_cable_test_fault_length_valid(u16 status, u16 mask)
2110{
2111 switch (FIELD_GET(mask, status)) {
2112 case KSZ8081_LMD_STAT_OPEN:
2113 fallthrough;
2114 case KSZ8081_LMD_STAT_SHORT:
2115 return true;
2116 }
2117 return false;
2118}
2119
2120static __always_inline int ksz886x_cable_test_fault_length(struct phy_device *phydev,
2121 u16 status, u16 data_mask)
2122{
2123 int dt;
2124
2125 /* According to the data sheet the distance to the fault is
2126 * DELTA_TIME * 0.4 meters for ksz phys.
2127 * (DELTA_TIME - 22) * 0.8 for lan8814 phy.
2128 */
2129 dt = FIELD_GET(data_mask, status);
2130
2131 if (phydev_id_compare(phydev, PHY_ID_LAN8814))
2132 return ((dt - 22) * 800) / 10;
2133 else
2134 return (dt * 400) / 10;
2135}
2136
2137static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
2138{
2139 const struct kszphy_type *type = phydev->drv->driver_data;
2140 int val, ret;
2141
2142 ret = phy_read_poll_timeout(phydev, type->cable_diag_reg, val,
2143 !(val & KSZ8081_LMD_ENABLE_TEST),
2144 30000, 100000, true);
2145
2146 return ret < 0 ? ret : 0;
2147}
2148
2149static int lan8814_cable_test_one_pair(struct phy_device *phydev, int pair)
2150{
2151 static const int ethtool_pair[] = { ETHTOOL_A_CABLE_PAIR_A,
2152 ETHTOOL_A_CABLE_PAIR_B,
2153 ETHTOOL_A_CABLE_PAIR_C,
2154 ETHTOOL_A_CABLE_PAIR_D,
2155 };
2156 u32 fault_length;
2157 int ret;
2158 int val;
2159
2160 val = KSZ8081_LMD_ENABLE_TEST;
2161 val = val | (pair << LAN8814_PAIR_BIT_SHIFT);
2162
2163 ret = phy_write(phydev, LAN8814_CABLE_DIAG, val);
2164 if (ret < 0)
2165 return ret;
2166
2167 ret = ksz886x_cable_test_wait_for_completion(phydev);
2168 if (ret)
2169 return ret;
2170
2171 val = phy_read(phydev, LAN8814_CABLE_DIAG);
2172 if (val < 0)
2173 return val;
2174
2175 if (ksz886x_cable_test_failed(val, LAN8814_CABLE_DIAG_STAT_MASK))
2176 return -EAGAIN;
2177
2178 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2179 ksz886x_cable_test_result_trans(val,
2180 LAN8814_CABLE_DIAG_STAT_MASK
2181 ));
2182 if (ret)
2183 return ret;
2184
2185 if (!ksz886x_cable_test_fault_length_valid(val, LAN8814_CABLE_DIAG_STAT_MASK))
2186 return 0;
2187
2188 fault_length = ksz886x_cable_test_fault_length(phydev, val,
2189 LAN8814_CABLE_DIAG_VCT_DATA_MASK);
2190
2191 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2192}
2193
2194static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
2195{
2196 static const int ethtool_pair[] = {
2197 ETHTOOL_A_CABLE_PAIR_A,
2198 ETHTOOL_A_CABLE_PAIR_B,
2199 };
2200 int ret, val, mdix;
2201 u32 fault_length;
2202
2203 /* There is no way to choice the pair, like we do one ksz9031.
2204 * We can workaround this limitation by using the MDI-X functionality.
2205 */
2206 if (pair == 0)
2207 mdix = ETH_TP_MDI;
2208 else
2209 mdix = ETH_TP_MDI_X;
2210
2211 switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
2212 case PHY_ID_KSZ8081:
2213 ret = ksz8081_config_mdix(phydev, mdix);
2214 break;
2215 case PHY_ID_KSZ886X:
2216 ret = ksz886x_config_mdix(phydev, mdix);
2217 break;
2218 default:
2219 ret = -ENODEV;
2220 }
2221
2222 if (ret)
2223 return ret;
2224
2225 /* Now we are ready to fire. This command will send a 100ns pulse
2226 * to the pair.
2227 */
2228 ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
2229 if (ret)
2230 return ret;
2231
2232 ret = ksz886x_cable_test_wait_for_completion(phydev);
2233 if (ret)
2234 return ret;
2235
2236 val = phy_read(phydev, KSZ8081_LMD);
2237 if (val < 0)
2238 return val;
2239
2240 if (ksz886x_cable_test_failed(val, KSZ8081_LMD_STAT_MASK))
2241 return -EAGAIN;
2242
2243 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2244 ksz886x_cable_test_result_trans(val, KSZ8081_LMD_STAT_MASK));
2245 if (ret)
2246 return ret;
2247
2248 if (!ksz886x_cable_test_fault_length_valid(val, KSZ8081_LMD_STAT_MASK))
2249 return 0;
2250
2251 fault_length = ksz886x_cable_test_fault_length(phydev, val, KSZ8081_LMD_DELTA_TIME_MASK);
2252
2253 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2254}
2255
2256static int ksz886x_cable_test_get_status(struct phy_device *phydev,
2257 bool *finished)
2258{
2259 const struct kszphy_type *type = phydev->drv->driver_data;
2260 unsigned long pair_mask = type->pair_mask;
2261 int retries = 20;
2262 int ret = 0;
2263 int pair;
2264
2265 *finished = false;
2266
2267 /* Try harder if link partner is active */
2268 while (pair_mask && retries--) {
2269 for_each_set_bit(pair, &pair_mask, 4) {
2270 if (type->cable_diag_reg == LAN8814_CABLE_DIAG)
2271 ret = lan8814_cable_test_one_pair(phydev, pair);
2272 else
2273 ret = ksz886x_cable_test_one_pair(phydev, pair);
2274 if (ret == -EAGAIN)
2275 continue;
2276 if (ret < 0)
2277 return ret;
2278 clear_bit(pair, &pair_mask);
2279 }
2280 /* If link partner is in autonegotiation mode it will send 2ms
2281 * of FLPs with at least 6ms of silence.
2282 * Add 2ms sleep to have better chances to hit this silence.
2283 */
2284 if (pair_mask)
2285 msleep(2);
2286 }
2287
2288 *finished = true;
2289
2290 return ret;
2291}
2292
2293#define LAN_EXT_PAGE_ACCESS_CONTROL 0x16
2294#define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA 0x17
2295#define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC 0x4000
2296
2297#define LAN8814_QSGMII_SOFT_RESET 0x43
2298#define LAN8814_QSGMII_SOFT_RESET_BIT BIT(0)
2299#define LAN8814_QSGMII_PCS1G_ANEG_CONFIG 0x13
2300#define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA BIT(3)
2301#define LAN8814_ALIGN_SWAP 0x4a
2302#define LAN8814_ALIGN_TX_A_B_SWAP 0x1
2303#define LAN8814_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
2304
2305#define LAN8804_ALIGN_SWAP 0x4a
2306#define LAN8804_ALIGN_TX_A_B_SWAP 0x1
2307#define LAN8804_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
2308#define LAN8814_CLOCK_MANAGEMENT 0xd
2309#define LAN8814_LINK_QUALITY 0x8e
2310
2311static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
2312{
2313 int data;
2314
2315 phy_lock_mdio_bus(phydev);
2316 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2317 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2318 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2319 (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
2320 data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);
2321 phy_unlock_mdio_bus(phydev);
2322
2323 return data;
2324}
2325
2326static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,
2327 u16 val)
2328{
2329 phy_lock_mdio_bus(phydev);
2330 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2331 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2332 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2333 page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC);
2334
2335 val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
2336 if (val != 0)
2337 phydev_err(phydev, "Error: phy_write has returned error %d\n",
2338 val);
2339 phy_unlock_mdio_bus(phydev);
2340 return val;
2341}
2342
2343static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)
2344{
2345 u16 val = 0;
2346
2347 if (enable)
2348 val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ |
2349 PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ |
2350 PTP_TSU_INT_EN_PTP_RX_TS_EN_ |
2351 PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_;
2352
2353 return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val);
2354}
2355
2356static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,
2357 u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2358{
2359 *seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI);
2360 *seconds = (*seconds << 16) |
2361 lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO);
2362
2363 *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI);
2364 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2365 lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO);
2366
2367 *seq_id = lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2);
2368}
2369
2370static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,
2371 u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2372{
2373 *seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI);
2374 *seconds = *seconds << 16 |
2375 lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO);
2376
2377 *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI);
2378 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2379 lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO);
2380
2381 *seq_id = lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2);
2382}
2383
2384static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct ethtool_ts_info *info)
2385{
2386 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2387 struct phy_device *phydev = ptp_priv->phydev;
2388 struct lan8814_shared_priv *shared = phydev->shared->priv;
2389
2390 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
2391 SOF_TIMESTAMPING_RX_HARDWARE |
2392 SOF_TIMESTAMPING_RAW_HARDWARE;
2393
2394 info->phc_index = ptp_clock_index(shared->ptp_clock);
2395
2396 info->tx_types =
2397 (1 << HWTSTAMP_TX_OFF) |
2398 (1 << HWTSTAMP_TX_ON) |
2399 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
2400
2401 info->rx_filters =
2402 (1 << HWTSTAMP_FILTER_NONE) |
2403 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2404 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2405 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2406 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2407
2408 return 0;
2409}
2410
2411static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)
2412{
2413 int i;
2414
2415 for (i = 0; i < FIFO_SIZE; ++i)
2416 lanphy_read_page_reg(phydev, 5,
2417 egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2);
2418
2419 /* Read to clear overflow status bit */
2420 lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2421}
2422
2423static int lan8814_hwtstamp(struct mii_timestamper *mii_ts,
2424 struct kernel_hwtstamp_config *config,
2425 struct netlink_ext_ack *extack)
2426{
2427 struct kszphy_ptp_priv *ptp_priv =
2428 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2429 struct phy_device *phydev = ptp_priv->phydev;
2430 struct lan8814_shared_priv *shared = phydev->shared->priv;
2431 struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2432 int txcfg = 0, rxcfg = 0;
2433 int pkt_ts_enable;
2434 int tx_mod;
2435
2436 ptp_priv->hwts_tx_type = config->tx_type;
2437 ptp_priv->rx_filter = config->rx_filter;
2438
2439 switch (config->rx_filter) {
2440 case HWTSTAMP_FILTER_NONE:
2441 ptp_priv->layer = 0;
2442 ptp_priv->version = 0;
2443 break;
2444 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2445 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2446 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2447 ptp_priv->layer = PTP_CLASS_L4;
2448 ptp_priv->version = PTP_CLASS_V2;
2449 break;
2450 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2451 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2452 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2453 ptp_priv->layer = PTP_CLASS_L2;
2454 ptp_priv->version = PTP_CLASS_V2;
2455 break;
2456 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2457 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2458 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2459 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
2460 ptp_priv->version = PTP_CLASS_V2;
2461 break;
2462 default:
2463 return -ERANGE;
2464 }
2465
2466 if (ptp_priv->layer & PTP_CLASS_L2) {
2467 rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_;
2468 txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_;
2469 } else if (ptp_priv->layer & PTP_CLASS_L4) {
2470 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
2471 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
2472 }
2473 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg);
2474 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg);
2475
2476 pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
2477 PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
2478 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
2479 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
2480
2481 tx_mod = lanphy_read_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD);
2482 if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC) {
2483 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2484 tx_mod | PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2485 } else if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ON) {
2486 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2487 tx_mod & ~PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2488 }
2489
2490 if (config->rx_filter != HWTSTAMP_FILTER_NONE)
2491 lan8814_config_ts_intr(ptp_priv->phydev, true);
2492 else
2493 lan8814_config_ts_intr(ptp_priv->phydev, false);
2494
2495 mutex_lock(&shared->shared_lock);
2496 if (config->rx_filter != HWTSTAMP_FILTER_NONE)
2497 shared->ref++;
2498 else
2499 shared->ref--;
2500
2501 if (shared->ref)
2502 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2503 PTP_CMD_CTL_PTP_ENABLE_);
2504 else
2505 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2506 PTP_CMD_CTL_PTP_DISABLE_);
2507 mutex_unlock(&shared->shared_lock);
2508
2509 /* In case of multiple starts and stops, these needs to be cleared */
2510 list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2511 list_del(&rx_ts->list);
2512 kfree(rx_ts);
2513 }
2514 skb_queue_purge(&ptp_priv->rx_queue);
2515 skb_queue_purge(&ptp_priv->tx_queue);
2516
2517 lan8814_flush_fifo(ptp_priv->phydev, false);
2518 lan8814_flush_fifo(ptp_priv->phydev, true);
2519
2520 return 0;
2521}
2522
2523static void lan8814_txtstamp(struct mii_timestamper *mii_ts,
2524 struct sk_buff *skb, int type)
2525{
2526 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2527
2528 switch (ptp_priv->hwts_tx_type) {
2529 case HWTSTAMP_TX_ONESTEP_SYNC:
2530 if (ptp_msg_is_sync(skb, type)) {
2531 kfree_skb(skb);
2532 return;
2533 }
2534 fallthrough;
2535 case HWTSTAMP_TX_ON:
2536 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2537 skb_queue_tail(&ptp_priv->tx_queue, skb);
2538 break;
2539 case HWTSTAMP_TX_OFF:
2540 default:
2541 kfree_skb(skb);
2542 break;
2543 }
2544}
2545
2546static bool lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig)
2547{
2548 struct ptp_header *ptp_header;
2549 u32 type;
2550
2551 skb_push(skb, ETH_HLEN);
2552 type = ptp_classify_raw(skb);
2553 ptp_header = ptp_parse_header(skb, type);
2554 skb_pull_inline(skb, ETH_HLEN);
2555
2556 if (!ptp_header)
2557 return false;
2558
2559 *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2560 return true;
2561}
2562
2563static bool lan8814_match_rx_skb(struct kszphy_ptp_priv *ptp_priv,
2564 struct sk_buff *skb)
2565{
2566 struct skb_shared_hwtstamps *shhwtstamps;
2567 struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2568 unsigned long flags;
2569 bool ret = false;
2570 u16 skb_sig;
2571
2572 if (!lan8814_get_sig_rx(skb, &skb_sig))
2573 return ret;
2574
2575 /* Iterate over all RX timestamps and match it with the received skbs */
2576 spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2577 list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2578 /* Check if we found the signature we were looking for. */
2579 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2580 continue;
2581
2582 shhwtstamps = skb_hwtstamps(skb);
2583 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2584 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds,
2585 rx_ts->nsec);
2586 list_del(&rx_ts->list);
2587 kfree(rx_ts);
2588
2589 ret = true;
2590 break;
2591 }
2592 spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2593
2594 if (ret)
2595 netif_rx(skb);
2596 return ret;
2597}
2598
2599static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type)
2600{
2601 struct kszphy_ptp_priv *ptp_priv =
2602 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2603
2604 if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
2605 type == PTP_CLASS_NONE)
2606 return false;
2607
2608 if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
2609 return false;
2610
2611 /* If we failed to match then add it to the queue for when the timestamp
2612 * will come
2613 */
2614 if (!lan8814_match_rx_skb(ptp_priv, skb))
2615 skb_queue_tail(&ptp_priv->rx_queue, skb);
2616
2617 return true;
2618}
2619
2620static void lan8814_ptp_clock_set(struct phy_device *phydev,
2621 time64_t sec, u32 nsec)
2622{
2623 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, lower_16_bits(sec));
2624 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, upper_16_bits(sec));
2625 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_HI, upper_32_bits(sec));
2626 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, lower_16_bits(nsec));
2627 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, upper_16_bits(nsec));
2628
2629 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_);
2630}
2631
2632static void lan8814_ptp_clock_get(struct phy_device *phydev,
2633 time64_t *sec, u32 *nsec)
2634{
2635 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_);
2636
2637 *sec = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_HI);
2638 *sec <<= 16;
2639 *sec |= lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID);
2640 *sec <<= 16;
2641 *sec |= lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO);
2642
2643 *nsec = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI);
2644 *nsec <<= 16;
2645 *nsec |= lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO);
2646}
2647
2648static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci,
2649 struct timespec64 *ts)
2650{
2651 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2652 ptp_clock_info);
2653 struct phy_device *phydev = shared->phydev;
2654 u32 nano_seconds;
2655 time64_t seconds;
2656
2657 mutex_lock(&shared->shared_lock);
2658 lan8814_ptp_clock_get(phydev, &seconds, &nano_seconds);
2659 mutex_unlock(&shared->shared_lock);
2660 ts->tv_sec = seconds;
2661 ts->tv_nsec = nano_seconds;
2662
2663 return 0;
2664}
2665
2666static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci,
2667 const struct timespec64 *ts)
2668{
2669 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2670 ptp_clock_info);
2671 struct phy_device *phydev = shared->phydev;
2672
2673 mutex_lock(&shared->shared_lock);
2674 lan8814_ptp_clock_set(phydev, ts->tv_sec, ts->tv_nsec);
2675 mutex_unlock(&shared->shared_lock);
2676
2677 return 0;
2678}
2679
2680static void lan8814_ptp_clock_step(struct phy_device *phydev,
2681 s64 time_step_ns)
2682{
2683 u32 nano_seconds_step;
2684 u64 abs_time_step_ns;
2685 time64_t set_seconds;
2686 u32 nano_seconds;
2687 u32 remainder;
2688 s32 seconds;
2689
2690 if (time_step_ns > 15000000000LL) {
2691 /* convert to clock set */
2692 lan8814_ptp_clock_get(phydev, &set_seconds, &nano_seconds);
2693 set_seconds += div_u64_rem(time_step_ns, 1000000000LL,
2694 &remainder);
2695 nano_seconds += remainder;
2696 if (nano_seconds >= 1000000000) {
2697 set_seconds++;
2698 nano_seconds -= 1000000000;
2699 }
2700 lan8814_ptp_clock_set(phydev, set_seconds, nano_seconds);
2701 return;
2702 } else if (time_step_ns < -15000000000LL) {
2703 /* convert to clock set */
2704 time_step_ns = -time_step_ns;
2705
2706 lan8814_ptp_clock_get(phydev, &set_seconds, &nano_seconds);
2707 set_seconds -= div_u64_rem(time_step_ns, 1000000000LL,
2708 &remainder);
2709 nano_seconds_step = remainder;
2710 if (nano_seconds < nano_seconds_step) {
2711 set_seconds--;
2712 nano_seconds += 1000000000;
2713 }
2714 nano_seconds -= nano_seconds_step;
2715 lan8814_ptp_clock_set(phydev, set_seconds, nano_seconds);
2716 return;
2717 }
2718
2719 /* do clock step */
2720 if (time_step_ns >= 0) {
2721 abs_time_step_ns = (u64)time_step_ns;
2722 seconds = (s32)div_u64_rem(abs_time_step_ns, 1000000000,
2723 &remainder);
2724 nano_seconds = remainder;
2725 } else {
2726 abs_time_step_ns = (u64)(-time_step_ns);
2727 seconds = -((s32)div_u64_rem(abs_time_step_ns, 1000000000,
2728 &remainder));
2729 nano_seconds = remainder;
2730 if (nano_seconds > 0) {
2731 /* subtracting nano seconds is not allowed
2732 * convert to subtracting from seconds,
2733 * and adding to nanoseconds
2734 */
2735 seconds--;
2736 nano_seconds = (1000000000 - nano_seconds);
2737 }
2738 }
2739
2740 if (nano_seconds > 0) {
2741 /* add 8 ns to cover the likely normal increment */
2742 nano_seconds += 8;
2743 }
2744
2745 if (nano_seconds >= 1000000000) {
2746 /* carry into seconds */
2747 seconds++;
2748 nano_seconds -= 1000000000;
2749 }
2750
2751 while (seconds) {
2752 if (seconds > 0) {
2753 u32 adjustment_value = (u32)seconds;
2754 u16 adjustment_value_lo, adjustment_value_hi;
2755
2756 if (adjustment_value > 0xF)
2757 adjustment_value = 0xF;
2758
2759 adjustment_value_lo = adjustment_value & 0xffff;
2760 adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2761
2762 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2763 adjustment_value_lo);
2764 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2765 PTP_LTC_STEP_ADJ_DIR_ |
2766 adjustment_value_hi);
2767 seconds -= ((s32)adjustment_value);
2768 } else {
2769 u32 adjustment_value = (u32)(-seconds);
2770 u16 adjustment_value_lo, adjustment_value_hi;
2771
2772 if (adjustment_value > 0xF)
2773 adjustment_value = 0xF;
2774
2775 adjustment_value_lo = adjustment_value & 0xffff;
2776 adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2777
2778 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2779 adjustment_value_lo);
2780 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2781 adjustment_value_hi);
2782 seconds += ((s32)adjustment_value);
2783 }
2784 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2785 PTP_CMD_CTL_PTP_LTC_STEP_SEC_);
2786 }
2787 if (nano_seconds) {
2788 u16 nano_seconds_lo;
2789 u16 nano_seconds_hi;
2790
2791 nano_seconds_lo = nano_seconds & 0xffff;
2792 nano_seconds_hi = (nano_seconds >> 16) & 0x3fff;
2793
2794 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2795 nano_seconds_lo);
2796 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2797 PTP_LTC_STEP_ADJ_DIR_ |
2798 nano_seconds_hi);
2799 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2800 PTP_CMD_CTL_PTP_LTC_STEP_NSEC_);
2801 }
2802}
2803
2804static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta)
2805{
2806 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2807 ptp_clock_info);
2808 struct phy_device *phydev = shared->phydev;
2809
2810 mutex_lock(&shared->shared_lock);
2811 lan8814_ptp_clock_step(phydev, delta);
2812 mutex_unlock(&shared->shared_lock);
2813
2814 return 0;
2815}
2816
2817static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm)
2818{
2819 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2820 ptp_clock_info);
2821 struct phy_device *phydev = shared->phydev;
2822 u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi;
2823 bool positive = true;
2824 u32 kszphy_rate_adj;
2825
2826 if (scaled_ppm < 0) {
2827 scaled_ppm = -scaled_ppm;
2828 positive = false;
2829 }
2830
2831 kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16);
2832 kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16;
2833
2834 kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff;
2835 kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff;
2836
2837 if (positive)
2838 kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_;
2839
2840 mutex_lock(&shared->shared_lock);
2841 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_hi);
2842 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_lo);
2843 mutex_unlock(&shared->shared_lock);
2844
2845 return 0;
2846}
2847
2848static bool lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig)
2849{
2850 struct ptp_header *ptp_header;
2851 u32 type;
2852
2853 type = ptp_classify_raw(skb);
2854 ptp_header = ptp_parse_header(skb, type);
2855
2856 if (!ptp_header)
2857 return false;
2858
2859 *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2860 return true;
2861}
2862
2863static void lan8814_match_tx_skb(struct kszphy_ptp_priv *ptp_priv,
2864 u32 seconds, u32 nsec, u16 seq_id)
2865{
2866 struct skb_shared_hwtstamps shhwtstamps;
2867 struct sk_buff *skb, *skb_tmp;
2868 unsigned long flags;
2869 bool ret = false;
2870 u16 skb_sig;
2871
2872 spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags);
2873 skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) {
2874 if (!lan8814_get_sig_tx(skb, &skb_sig))
2875 continue;
2876
2877 if (memcmp(&skb_sig, &seq_id, sizeof(seq_id)))
2878 continue;
2879
2880 __skb_unlink(skb, &ptp_priv->tx_queue);
2881 ret = true;
2882 break;
2883 }
2884 spin_unlock_irqrestore(&ptp_priv->tx_queue.lock, flags);
2885
2886 if (ret) {
2887 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2888 shhwtstamps.hwtstamp = ktime_set(seconds, nsec);
2889 skb_complete_tx_timestamp(skb, &shhwtstamps);
2890 }
2891}
2892
2893static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv)
2894{
2895 struct phy_device *phydev = ptp_priv->phydev;
2896 u32 seconds, nsec;
2897 u16 seq_id;
2898
2899 lan8814_ptp_tx_ts_get(phydev, &seconds, &nsec, &seq_id);
2900 lan8814_match_tx_skb(ptp_priv, seconds, nsec, seq_id);
2901}
2902
2903static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv)
2904{
2905 struct phy_device *phydev = ptp_priv->phydev;
2906 u32 reg;
2907
2908 do {
2909 lan8814_dequeue_tx_skb(ptp_priv);
2910
2911 /* If other timestamps are available in the FIFO,
2912 * process them.
2913 */
2914 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2915 } while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0);
2916}
2917
2918static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv,
2919 struct lan8814_ptp_rx_ts *rx_ts)
2920{
2921 struct skb_shared_hwtstamps *shhwtstamps;
2922 struct sk_buff *skb, *skb_tmp;
2923 unsigned long flags;
2924 bool ret = false;
2925 u16 skb_sig;
2926
2927 spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags);
2928 skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) {
2929 if (!lan8814_get_sig_rx(skb, &skb_sig))
2930 continue;
2931
2932 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2933 continue;
2934
2935 __skb_unlink(skb, &ptp_priv->rx_queue);
2936
2937 ret = true;
2938 break;
2939 }
2940 spin_unlock_irqrestore(&ptp_priv->rx_queue.lock, flags);
2941
2942 if (ret) {
2943 shhwtstamps = skb_hwtstamps(skb);
2944 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2945 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds, rx_ts->nsec);
2946 netif_rx(skb);
2947 }
2948
2949 return ret;
2950}
2951
2952static void lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv,
2953 struct lan8814_ptp_rx_ts *rx_ts)
2954{
2955 unsigned long flags;
2956
2957 /* If we failed to match the skb add it to the queue for when
2958 * the frame will come
2959 */
2960 if (!lan8814_match_skb(ptp_priv, rx_ts)) {
2961 spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2962 list_add(&rx_ts->list, &ptp_priv->rx_ts_list);
2963 spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2964 } else {
2965 kfree(rx_ts);
2966 }
2967}
2968
2969static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv)
2970{
2971 struct phy_device *phydev = ptp_priv->phydev;
2972 struct lan8814_ptp_rx_ts *rx_ts;
2973 u32 reg;
2974
2975 do {
2976 rx_ts = kzalloc(sizeof(*rx_ts), GFP_KERNEL);
2977 if (!rx_ts)
2978 return;
2979
2980 lan8814_ptp_rx_ts_get(phydev, &rx_ts->seconds, &rx_ts->nsec,
2981 &rx_ts->seq_id);
2982 lan8814_match_rx_ts(ptp_priv, rx_ts);
2983
2984 /* If other timestamps are available in the FIFO,
2985 * process them.
2986 */
2987 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2988 } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
2989}
2990
2991static void lan8814_handle_ptp_interrupt(struct phy_device *phydev, u16 status)
2992{
2993 struct kszphy_priv *priv = phydev->priv;
2994 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2995
2996 if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
2997 lan8814_get_tx_ts(ptp_priv);
2998
2999 if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
3000 lan8814_get_rx_ts(ptp_priv);
3001
3002 if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
3003 lan8814_flush_fifo(phydev, true);
3004 skb_queue_purge(&ptp_priv->tx_queue);
3005 }
3006
3007 if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) {
3008 lan8814_flush_fifo(phydev, false);
3009 skb_queue_purge(&ptp_priv->rx_queue);
3010 }
3011}
3012
3013static int lan8804_config_init(struct phy_device *phydev)
3014{
3015 int val;
3016
3017 /* MDI-X setting for swap A,B transmit */
3018 val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);
3019 val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;
3020 val |= LAN8804_ALIGN_TX_A_B_SWAP;
3021 lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);
3022
3023 /* Make sure that the PHY will not stop generating the clock when the
3024 * link partner goes down
3025 */
3026 lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e);
3027 lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY);
3028
3029 return 0;
3030}
3031
3032static irqreturn_t lan8804_handle_interrupt(struct phy_device *phydev)
3033{
3034 int status;
3035
3036 status = phy_read(phydev, LAN8814_INTS);
3037 if (status < 0) {
3038 phy_error(phydev);
3039 return IRQ_NONE;
3040 }
3041
3042 if (status > 0)
3043 phy_trigger_machine(phydev);
3044
3045 return IRQ_HANDLED;
3046}
3047
3048#define LAN8804_OUTPUT_CONTROL 25
3049#define LAN8804_OUTPUT_CONTROL_INTR_BUFFER BIT(14)
3050#define LAN8804_CONTROL 31
3051#define LAN8804_CONTROL_INTR_POLARITY BIT(14)
3052
3053static int lan8804_config_intr(struct phy_device *phydev)
3054{
3055 int err;
3056
3057 /* This is an internal PHY of lan966x and is not possible to change the
3058 * polarity on the GIC found in lan966x, therefore change the polarity
3059 * of the interrupt in the PHY from being active low instead of active
3060 * high.
3061 */
3062 phy_write(phydev, LAN8804_CONTROL, LAN8804_CONTROL_INTR_POLARITY);
3063
3064 /* By default interrupt buffer is open-drain in which case the interrupt
3065 * can be active only low. Therefore change the interrupt buffer to be
3066 * push-pull to be able to change interrupt polarity
3067 */
3068 phy_write(phydev, LAN8804_OUTPUT_CONTROL,
3069 LAN8804_OUTPUT_CONTROL_INTR_BUFFER);
3070
3071 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3072 err = phy_read(phydev, LAN8814_INTS);
3073 if (err < 0)
3074 return err;
3075
3076 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3077 if (err)
3078 return err;
3079 } else {
3080 err = phy_write(phydev, LAN8814_INTC, 0);
3081 if (err)
3082 return err;
3083
3084 err = phy_read(phydev, LAN8814_INTS);
3085 if (err < 0)
3086 return err;
3087 }
3088
3089 return 0;
3090}
3091
3092static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
3093{
3094 int ret = IRQ_NONE;
3095 int irq_status;
3096
3097 irq_status = phy_read(phydev, LAN8814_INTS);
3098 if (irq_status < 0) {
3099 phy_error(phydev);
3100 return IRQ_NONE;
3101 }
3102
3103 if (irq_status & LAN8814_INT_LINK) {
3104 phy_trigger_machine(phydev);
3105 ret = IRQ_HANDLED;
3106 }
3107
3108 while (true) {
3109 irq_status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
3110 if (!irq_status)
3111 break;
3112
3113 lan8814_handle_ptp_interrupt(phydev, irq_status);
3114 ret = IRQ_HANDLED;
3115 }
3116
3117 return ret;
3118}
3119
3120static int lan8814_ack_interrupt(struct phy_device *phydev)
3121{
3122 /* bit[12..0] int status, which is a read and clear register. */
3123 int rc;
3124
3125 rc = phy_read(phydev, LAN8814_INTS);
3126
3127 return (rc < 0) ? rc : 0;
3128}
3129
3130static int lan8814_config_intr(struct phy_device *phydev)
3131{
3132 int err;
3133
3134 lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG,
3135 LAN8814_INTR_CTRL_REG_POLARITY |
3136 LAN8814_INTR_CTRL_REG_INTR_ENABLE);
3137
3138 /* enable / disable interrupts */
3139 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3140 err = lan8814_ack_interrupt(phydev);
3141 if (err)
3142 return err;
3143
3144 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3145 } else {
3146 err = phy_write(phydev, LAN8814_INTC, 0);
3147 if (err)
3148 return err;
3149
3150 err = lan8814_ack_interrupt(phydev);
3151 }
3152
3153 return err;
3154}
3155
3156static void lan8814_ptp_init(struct phy_device *phydev)
3157{
3158 struct kszphy_priv *priv = phydev->priv;
3159 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3160 u32 temp;
3161
3162 if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
3163 !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
3164 return;
3165
3166 lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_);
3167
3168 temp = lanphy_read_page_reg(phydev, 5, PTP_TX_MOD);
3169 temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
3170 lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp);
3171
3172 temp = lanphy_read_page_reg(phydev, 5, PTP_RX_MOD);
3173 temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
3174 lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp);
3175
3176 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0);
3177 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0);
3178
3179 /* Removing default registers configs related to L2 and IP */
3180 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0);
3181 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0);
3182 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0);
3183 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0);
3184
3185 /* Disable checking for minorVersionPTP field */
3186 lanphy_write_page_reg(phydev, 5, PTP_RX_VERSION,
3187 PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));
3188 lanphy_write_page_reg(phydev, 5, PTP_TX_VERSION,
3189 PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));
3190
3191 skb_queue_head_init(&ptp_priv->tx_queue);
3192 skb_queue_head_init(&ptp_priv->rx_queue);
3193 INIT_LIST_HEAD(&ptp_priv->rx_ts_list);
3194 spin_lock_init(&ptp_priv->rx_ts_lock);
3195
3196 ptp_priv->phydev = phydev;
3197
3198 ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp;
3199 ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
3200 ptp_priv->mii_ts.hwtstamp = lan8814_hwtstamp;
3201 ptp_priv->mii_ts.ts_info = lan8814_ts_info;
3202
3203 phydev->mii_ts = &ptp_priv->mii_ts;
3204}
3205
3206static int lan8814_ptp_probe_once(struct phy_device *phydev)
3207{
3208 struct lan8814_shared_priv *shared = phydev->shared->priv;
3209
3210 /* Initialise shared lock for clock*/
3211 mutex_init(&shared->shared_lock);
3212
3213 shared->ptp_clock_info.owner = THIS_MODULE;
3214 snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name);
3215 shared->ptp_clock_info.max_adj = 31249999;
3216 shared->ptp_clock_info.n_alarm = 0;
3217 shared->ptp_clock_info.n_ext_ts = 0;
3218 shared->ptp_clock_info.n_pins = 0;
3219 shared->ptp_clock_info.pps = 0;
3220 shared->ptp_clock_info.pin_config = NULL;
3221 shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;
3222 shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;
3223 shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;
3224 shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;
3225 shared->ptp_clock_info.getcrosststamp = NULL;
3226
3227 shared->ptp_clock = ptp_clock_register(&shared->ptp_clock_info,
3228 &phydev->mdio.dev);
3229 if (IS_ERR(shared->ptp_clock)) {
3230 phydev_err(phydev, "ptp_clock_register failed %lu\n",
3231 PTR_ERR(shared->ptp_clock));
3232 return -EINVAL;
3233 }
3234
3235 /* Check if PHC support is missing at the configuration level */
3236 if (!shared->ptp_clock)
3237 return 0;
3238
3239 phydev_dbg(phydev, "successfully registered ptp clock\n");
3240
3241 shared->phydev = phydev;
3242
3243 /* The EP.4 is shared between all the PHYs in the package and also it
3244 * can be accessed by any of the PHYs
3245 */
3246 lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);
3247 lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE,
3248 PTP_OPERATING_MODE_STANDALONE_);
3249
3250 return 0;
3251}
3252
3253static void lan8814_setup_led(struct phy_device *phydev, int val)
3254{
3255 int temp;
3256
3257 temp = lanphy_read_page_reg(phydev, 5, LAN8814_LED_CTRL_1);
3258
3259 if (val)
3260 temp |= LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3261 else
3262 temp &= ~LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3263
3264 lanphy_write_page_reg(phydev, 5, LAN8814_LED_CTRL_1, temp);
3265}
3266
3267static int lan8814_config_init(struct phy_device *phydev)
3268{
3269 struct kszphy_priv *lan8814 = phydev->priv;
3270 int val;
3271
3272 /* Reset the PHY */
3273 val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET);
3274 val |= LAN8814_QSGMII_SOFT_RESET_BIT;
3275 lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val);
3276
3277 /* Disable ANEG with QSGMII PCS Host side */
3278 val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);
3279 val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA;
3280 lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);
3281
3282 /* MDI-X setting for swap A,B transmit */
3283 val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP);
3284 val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK;
3285 val |= LAN8814_ALIGN_TX_A_B_SWAP;
3286 lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val);
3287
3288 if (lan8814->led_mode >= 0)
3289 lan8814_setup_led(phydev, lan8814->led_mode);
3290
3291 return 0;
3292}
3293
3294/* It is expected that there will not be any 'lan8814_take_coma_mode'
3295 * function called in suspend. Because the GPIO line can be shared, so if one of
3296 * the phys goes back in coma mode, then all the other PHYs will go, which is
3297 * wrong.
3298 */
3299static int lan8814_release_coma_mode(struct phy_device *phydev)
3300{
3301 struct gpio_desc *gpiod;
3302
3303 gpiod = devm_gpiod_get_optional(&phydev->mdio.dev, "coma-mode",
3304 GPIOD_OUT_HIGH_OPEN_DRAIN |
3305 GPIOD_FLAGS_BIT_NONEXCLUSIVE);
3306 if (IS_ERR(gpiod))
3307 return PTR_ERR(gpiod);
3308
3309 gpiod_set_consumer_name(gpiod, "LAN8814 coma mode");
3310 gpiod_set_value_cansleep(gpiod, 0);
3311
3312 return 0;
3313}
3314
3315static void lan8814_clear_2psp_bit(struct phy_device *phydev)
3316{
3317 u16 val;
3318
3319 /* It was noticed that when traffic is passing through the PHY and the
3320 * cable is removed then the LED was still one even though there is no
3321 * link
3322 */
3323 val = lanphy_read_page_reg(phydev, 2, LAN8814_EEE_STATE);
3324 val &= ~LAN8814_EEE_STATE_MASK2P5P;
3325 lanphy_write_page_reg(phydev, 2, LAN8814_EEE_STATE, val);
3326}
3327
3328static void lan8814_update_meas_time(struct phy_device *phydev)
3329{
3330 u16 val;
3331
3332 /* By setting the measure time to a value of 0xb this will allow cables
3333 * longer than 100m to be used. This configuration can be used
3334 * regardless of the mode of operation of the PHY
3335 */
3336 val = lanphy_read_page_reg(phydev, 1, LAN8814_PD_CONTROLS);
3337 val &= ~LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK;
3338 val |= LAN8814_PD_CONTROLS_PD_MEAS_TIME_VAL;
3339 lanphy_write_page_reg(phydev, 1, LAN8814_PD_CONTROLS, val);
3340}
3341
3342static int lan8814_probe(struct phy_device *phydev)
3343{
3344 const struct kszphy_type *type = phydev->drv->driver_data;
3345 struct kszphy_priv *priv;
3346 u16 addr;
3347 int err;
3348
3349 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
3350 if (!priv)
3351 return -ENOMEM;
3352
3353 phydev->priv = priv;
3354
3355 priv->type = type;
3356
3357 kszphy_parse_led_mode(phydev);
3358
3359 /* Strap-in value for PHY address, below register read gives starting
3360 * phy address value
3361 */
3362 addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F;
3363 devm_phy_package_join(&phydev->mdio.dev, phydev,
3364 addr, sizeof(struct lan8814_shared_priv));
3365
3366 if (phy_package_init_once(phydev)) {
3367 err = lan8814_release_coma_mode(phydev);
3368 if (err)
3369 return err;
3370
3371 err = lan8814_ptp_probe_once(phydev);
3372 if (err)
3373 return err;
3374 }
3375
3376 lan8814_ptp_init(phydev);
3377
3378 /* Errata workarounds */
3379 lan8814_clear_2psp_bit(phydev);
3380 lan8814_update_meas_time(phydev);
3381
3382 return 0;
3383}
3384
3385#define LAN8841_MMD_TIMER_REG 0
3386#define LAN8841_MMD0_REGISTER_17 17
3387#define LAN8841_MMD0_REGISTER_17_DROP_OPT(x) ((x) & 0x3)
3388#define LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS BIT(3)
3389#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG 2
3390#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK BIT(14)
3391#define LAN8841_MMD_ANALOG_REG 28
3392#define LAN8841_ANALOG_CONTROL_1 1
3393#define LAN8841_ANALOG_CONTROL_1_PLL_TRIM(x) (((x) & 0x3) << 5)
3394#define LAN8841_ANALOG_CONTROL_10 13
3395#define LAN8841_ANALOG_CONTROL_10_PLL_DIV(x) ((x) & 0x3)
3396#define LAN8841_ANALOG_CONTROL_11 14
3397#define LAN8841_ANALOG_CONTROL_11_LDO_REF(x) (((x) & 0x7) << 12)
3398#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT 69
3399#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL 0xbffc
3400#define LAN8841_BTRX_POWER_DOWN 70
3401#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A BIT(0)
3402#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_A BIT(1)
3403#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B BIT(2)
3404#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_B BIT(3)
3405#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C BIT(5)
3406#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D BIT(7)
3407#define LAN8841_ADC_CHANNEL_MASK 198
3408#define LAN8841_PTP_RX_PARSE_L2_ADDR_EN 370
3409#define LAN8841_PTP_RX_PARSE_IP_ADDR_EN 371
3410#define LAN8841_PTP_RX_VERSION 374
3411#define LAN8841_PTP_TX_PARSE_L2_ADDR_EN 434
3412#define LAN8841_PTP_TX_PARSE_IP_ADDR_EN 435
3413#define LAN8841_PTP_TX_VERSION 438
3414#define LAN8841_PTP_CMD_CTL 256
3415#define LAN8841_PTP_CMD_CTL_PTP_ENABLE BIT(2)
3416#define LAN8841_PTP_CMD_CTL_PTP_DISABLE BIT(1)
3417#define LAN8841_PTP_CMD_CTL_PTP_RESET BIT(0)
3418#define LAN8841_PTP_RX_PARSE_CONFIG 368
3419#define LAN8841_PTP_TX_PARSE_CONFIG 432
3420#define LAN8841_PTP_RX_MODE 381
3421#define LAN8841_PTP_INSERT_TS_EN BIT(0)
3422#define LAN8841_PTP_INSERT_TS_32BIT BIT(1)
3423
3424static int lan8841_config_init(struct phy_device *phydev)
3425{
3426 int ret;
3427
3428 ret = ksz9131_config_init(phydev);
3429 if (ret)
3430 return ret;
3431
3432 /* Initialize the HW by resetting everything */
3433 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3434 LAN8841_PTP_CMD_CTL,
3435 LAN8841_PTP_CMD_CTL_PTP_RESET,
3436 LAN8841_PTP_CMD_CTL_PTP_RESET);
3437
3438 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3439 LAN8841_PTP_CMD_CTL,
3440 LAN8841_PTP_CMD_CTL_PTP_ENABLE,
3441 LAN8841_PTP_CMD_CTL_PTP_ENABLE);
3442
3443 /* Don't process any frames */
3444 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3445 LAN8841_PTP_RX_PARSE_CONFIG, 0);
3446 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3447 LAN8841_PTP_TX_PARSE_CONFIG, 0);
3448 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3449 LAN8841_PTP_TX_PARSE_L2_ADDR_EN, 0);
3450 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3451 LAN8841_PTP_RX_PARSE_L2_ADDR_EN, 0);
3452 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3453 LAN8841_PTP_TX_PARSE_IP_ADDR_EN, 0);
3454 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3455 LAN8841_PTP_RX_PARSE_IP_ADDR_EN, 0);
3456
3457 /* Disable checking for minorVersionPTP field */
3458 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3459 LAN8841_PTP_RX_VERSION, 0xff00);
3460 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3461 LAN8841_PTP_TX_VERSION, 0xff00);
3462
3463 /* 100BT Clause 40 improvenent errata */
3464 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3465 LAN8841_ANALOG_CONTROL_1,
3466 LAN8841_ANALOG_CONTROL_1_PLL_TRIM(0x2));
3467 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3468 LAN8841_ANALOG_CONTROL_10,
3469 LAN8841_ANALOG_CONTROL_10_PLL_DIV(0x1));
3470
3471 /* 10M/100M Ethernet Signal Tuning Errata for Shorted-Center Tap
3472 * Magnetics
3473 */
3474 ret = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3475 LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG);
3476 if (ret & LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK) {
3477 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3478 LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT,
3479 LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL);
3480 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3481 LAN8841_BTRX_POWER_DOWN,
3482 LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A |
3483 LAN8841_BTRX_POWER_DOWN_BTRX_CH_A |
3484 LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B |
3485 LAN8841_BTRX_POWER_DOWN_BTRX_CH_B |
3486 LAN8841_BTRX_POWER_DOWN_BTRX_CH_C |
3487 LAN8841_BTRX_POWER_DOWN_BTRX_CH_D);
3488 }
3489
3490 /* LDO Adjustment errata */
3491 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
3492 LAN8841_ANALOG_CONTROL_11,
3493 LAN8841_ANALOG_CONTROL_11_LDO_REF(1));
3494
3495 /* 100BT RGMII latency tuning errata */
3496 phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
3497 LAN8841_ADC_CHANNEL_MASK, 0x0);
3498 phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG,
3499 LAN8841_MMD0_REGISTER_17,
3500 LAN8841_MMD0_REGISTER_17_DROP_OPT(2) |
3501 LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS);
3502
3503 return 0;
3504}
3505
3506#define LAN8841_OUTPUT_CTRL 25
3507#define LAN8841_OUTPUT_CTRL_INT_BUFFER BIT(14)
3508#define LAN8841_INT_PTP BIT(9)
3509
3510static int lan8841_config_intr(struct phy_device *phydev)
3511{
3512 int err;
3513
3514 phy_modify(phydev, LAN8841_OUTPUT_CTRL,
3515 LAN8841_OUTPUT_CTRL_INT_BUFFER, 0);
3516
3517 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3518 err = phy_read(phydev, LAN8814_INTS);
3519 if (err < 0)
3520 return err;
3521
3522 /* Enable / disable interrupts. It is OK to enable PTP interrupt
3523 * even if it PTP is not enabled. Because the underneath blocks
3524 * will not enable the PTP so we will never get the PTP
3525 * interrupt.
3526 */
3527 err = phy_write(phydev, LAN8814_INTC,
3528 LAN8814_INT_LINK | LAN8841_INT_PTP);
3529 } else {
3530 err = phy_write(phydev, LAN8814_INTC, 0);
3531 if (err)
3532 return err;
3533
3534 err = phy_read(phydev, LAN8814_INTS);
3535 if (err < 0)
3536 return err;
3537
3538 /* Getting a positive value doesn't mean that is an error, it
3539 * just indicates what was the status. Therefore make sure to
3540 * clear the value and say that there is no error.
3541 */
3542 err = 0;
3543 }
3544
3545 return err;
3546}
3547
3548#define LAN8841_PTP_TX_EGRESS_SEC_LO 453
3549#define LAN8841_PTP_TX_EGRESS_SEC_HI 452
3550#define LAN8841_PTP_TX_EGRESS_NS_LO 451
3551#define LAN8841_PTP_TX_EGRESS_NS_HI 450
3552#define LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID BIT(15)
3553#define LAN8841_PTP_TX_MSG_HEADER2 455
3554
3555static bool lan8841_ptp_get_tx_ts(struct kszphy_ptp_priv *ptp_priv,
3556 u32 *sec, u32 *nsec, u16 *seq)
3557{
3558 struct phy_device *phydev = ptp_priv->phydev;
3559
3560 *nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_HI);
3561 if (!(*nsec & LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID))
3562 return false;
3563
3564 *nsec = ((*nsec & 0x3fff) << 16);
3565 *nsec = *nsec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_LO);
3566
3567 *sec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_HI);
3568 *sec = *sec << 16;
3569 *sec = *sec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_LO);
3570
3571 *seq = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);
3572
3573 return true;
3574}
3575
3576static void lan8841_ptp_process_tx_ts(struct kszphy_ptp_priv *ptp_priv)
3577{
3578 u32 sec, nsec;
3579 u16 seq;
3580
3581 while (lan8841_ptp_get_tx_ts(ptp_priv, &sec, &nsec, &seq))
3582 lan8814_match_tx_skb(ptp_priv, sec, nsec, seq);
3583}
3584
3585#define LAN8841_PTP_INT_STS 259
3586#define LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT BIT(13)
3587#define LAN8841_PTP_INT_STS_PTP_TX_TS_INT BIT(12)
3588#define LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT BIT(2)
3589
3590static void lan8841_ptp_flush_fifo(struct kszphy_ptp_priv *ptp_priv)
3591{
3592 struct phy_device *phydev = ptp_priv->phydev;
3593 int i;
3594
3595 for (i = 0; i < FIFO_SIZE; ++i)
3596 phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);
3597
3598 phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);
3599}
3600
3601#define LAN8841_PTP_GPIO_CAP_STS 506
3602#define LAN8841_PTP_GPIO_SEL 327
3603#define LAN8841_PTP_GPIO_SEL_GPIO_SEL(gpio) ((gpio) << 8)
3604#define LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP 498
3605#define LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP 499
3606#define LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP 500
3607#define LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP 501
3608#define LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP 502
3609#define LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP 503
3610#define LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP 504
3611#define LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP 505
3612
3613static void lan8841_gpio_process_cap(struct kszphy_ptp_priv *ptp_priv)
3614{
3615 struct phy_device *phydev = ptp_priv->phydev;
3616 struct ptp_clock_event ptp_event = {0};
3617 int pin, ret, tmp;
3618 s32 sec, nsec;
3619
3620 pin = ptp_find_pin_unlocked(ptp_priv->ptp_clock, PTP_PF_EXTTS, 0);
3621 if (pin == -1)
3622 return;
3623
3624 tmp = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_STS);
3625 if (tmp < 0)
3626 return;
3627
3628 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL,
3629 LAN8841_PTP_GPIO_SEL_GPIO_SEL(pin));
3630 if (ret)
3631 return;
3632
3633 mutex_lock(&ptp_priv->ptp_lock);
3634 if (tmp & BIT(pin)) {
3635 sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP);
3636 sec <<= 16;
3637 sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP);
3638
3639 nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;
3640 nsec <<= 16;
3641 nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP);
3642 } else {
3643 sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP);
3644 sec <<= 16;
3645 sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP);
3646
3647 nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;
3648 nsec <<= 16;
3649 nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP);
3650 }
3651 mutex_unlock(&ptp_priv->ptp_lock);
3652 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL, 0);
3653 if (ret)
3654 return;
3655
3656 ptp_event.index = 0;
3657 ptp_event.timestamp = ktime_set(sec, nsec);
3658 ptp_event.type = PTP_CLOCK_EXTTS;
3659 ptp_clock_event(ptp_priv->ptp_clock, &ptp_event);
3660}
3661
3662static void lan8841_handle_ptp_interrupt(struct phy_device *phydev)
3663{
3664 struct kszphy_priv *priv = phydev->priv;
3665 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3666 u16 status;
3667
3668 do {
3669 status = phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);
3670
3671 if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_INT)
3672 lan8841_ptp_process_tx_ts(ptp_priv);
3673
3674 if (status & LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT)
3675 lan8841_gpio_process_cap(ptp_priv);
3676
3677 if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT) {
3678 lan8841_ptp_flush_fifo(ptp_priv);
3679 skb_queue_purge(&ptp_priv->tx_queue);
3680 }
3681
3682 } while (status & (LAN8841_PTP_INT_STS_PTP_TX_TS_INT |
3683 LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT |
3684 LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT));
3685}
3686
3687#define LAN8841_INTS_PTP BIT(9)
3688
3689static irqreturn_t lan8841_handle_interrupt(struct phy_device *phydev)
3690{
3691 irqreturn_t ret = IRQ_NONE;
3692 int irq_status;
3693
3694 irq_status = phy_read(phydev, LAN8814_INTS);
3695 if (irq_status < 0) {
3696 phy_error(phydev);
3697 return IRQ_NONE;
3698 }
3699
3700 if (irq_status & LAN8814_INT_LINK) {
3701 phy_trigger_machine(phydev);
3702 ret = IRQ_HANDLED;
3703 }
3704
3705 if (irq_status & LAN8841_INTS_PTP) {
3706 lan8841_handle_ptp_interrupt(phydev);
3707 ret = IRQ_HANDLED;
3708 }
3709
3710 return ret;
3711}
3712
3713static int lan8841_ts_info(struct mii_timestamper *mii_ts,
3714 struct ethtool_ts_info *info)
3715{
3716 struct kszphy_ptp_priv *ptp_priv;
3717
3718 ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3719
3720 info->phc_index = ptp_priv->ptp_clock ?
3721 ptp_clock_index(ptp_priv->ptp_clock) : -1;
3722 if (info->phc_index == -1)
3723 return 0;
3724
3725 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
3726 SOF_TIMESTAMPING_RX_HARDWARE |
3727 SOF_TIMESTAMPING_RAW_HARDWARE;
3728
3729 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
3730 (1 << HWTSTAMP_TX_ON) |
3731 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
3732
3733 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3734 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3735 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
3736 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
3737
3738 return 0;
3739}
3740
3741#define LAN8841_PTP_INT_EN 260
3742#define LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN BIT(13)
3743#define LAN8841_PTP_INT_EN_PTP_TX_TS_EN BIT(12)
3744
3745static void lan8841_ptp_enable_processing(struct kszphy_ptp_priv *ptp_priv,
3746 bool enable)
3747{
3748 struct phy_device *phydev = ptp_priv->phydev;
3749
3750 if (enable) {
3751 /* Enable interrupts on the TX side */
3752 phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
3753 LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
3754 LAN8841_PTP_INT_EN_PTP_TX_TS_EN,
3755 LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
3756 LAN8841_PTP_INT_EN_PTP_TX_TS_EN);
3757
3758 /* Enable the modification of the frame on RX side,
3759 * this will add the ns and 2 bits of sec in the reserved field
3760 * of the PTP header
3761 */
3762 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3763 LAN8841_PTP_RX_MODE,
3764 LAN8841_PTP_INSERT_TS_EN |
3765 LAN8841_PTP_INSERT_TS_32BIT,
3766 LAN8841_PTP_INSERT_TS_EN |
3767 LAN8841_PTP_INSERT_TS_32BIT);
3768
3769 ptp_schedule_worker(ptp_priv->ptp_clock, 0);
3770 } else {
3771 /* Disable interrupts on the TX side */
3772 phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
3773 LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
3774 LAN8841_PTP_INT_EN_PTP_TX_TS_EN, 0);
3775
3776 /* Disable modification of the RX frames */
3777 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
3778 LAN8841_PTP_RX_MODE,
3779 LAN8841_PTP_INSERT_TS_EN |
3780 LAN8841_PTP_INSERT_TS_32BIT, 0);
3781
3782 ptp_cancel_worker_sync(ptp_priv->ptp_clock);
3783 }
3784}
3785
3786#define LAN8841_PTP_RX_TIMESTAMP_EN 379
3787#define LAN8841_PTP_TX_TIMESTAMP_EN 443
3788#define LAN8841_PTP_TX_MOD 445
3789
3790static int lan8841_hwtstamp(struct mii_timestamper *mii_ts,
3791 struct kernel_hwtstamp_config *config,
3792 struct netlink_ext_ack *extack)
3793{
3794 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3795 struct phy_device *phydev = ptp_priv->phydev;
3796 int txcfg = 0, rxcfg = 0;
3797 int pkt_ts_enable;
3798
3799 ptp_priv->hwts_tx_type = config->tx_type;
3800 ptp_priv->rx_filter = config->rx_filter;
3801
3802 switch (config->rx_filter) {
3803 case HWTSTAMP_FILTER_NONE:
3804 ptp_priv->layer = 0;
3805 ptp_priv->version = 0;
3806 break;
3807 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3808 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3809 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3810 ptp_priv->layer = PTP_CLASS_L4;
3811 ptp_priv->version = PTP_CLASS_V2;
3812 break;
3813 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3814 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3815 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3816 ptp_priv->layer = PTP_CLASS_L2;
3817 ptp_priv->version = PTP_CLASS_V2;
3818 break;
3819 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3820 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3821 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3822 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
3823 ptp_priv->version = PTP_CLASS_V2;
3824 break;
3825 default:
3826 return -ERANGE;
3827 }
3828
3829 /* Setup parsing of the frames and enable the timestamping for ptp
3830 * frames
3831 */
3832 if (ptp_priv->layer & PTP_CLASS_L2) {
3833 rxcfg |= PTP_RX_PARSE_CONFIG_LAYER2_EN_;
3834 txcfg |= PTP_TX_PARSE_CONFIG_LAYER2_EN_;
3835 } else if (ptp_priv->layer & PTP_CLASS_L4) {
3836 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
3837 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
3838 }
3839
3840 phy_write_mmd(phydev, 2, LAN8841_PTP_RX_PARSE_CONFIG, rxcfg);
3841 phy_write_mmd(phydev, 2, LAN8841_PTP_TX_PARSE_CONFIG, txcfg);
3842
3843 pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
3844 PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
3845 phy_write_mmd(phydev, 2, LAN8841_PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
3846 phy_write_mmd(phydev, 2, LAN8841_PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
3847
3848 /* Enable / disable of the TX timestamp in the SYNC frames */
3849 phy_modify_mmd(phydev, 2, LAN8841_PTP_TX_MOD,
3850 PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_,
3851 ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC ?
3852 PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ : 0);
3853
3854 /* Now enable/disable the timestamping */
3855 lan8841_ptp_enable_processing(ptp_priv,
3856 config->rx_filter != HWTSTAMP_FILTER_NONE);
3857
3858 skb_queue_purge(&ptp_priv->tx_queue);
3859
3860 lan8841_ptp_flush_fifo(ptp_priv);
3861
3862 return 0;
3863}
3864
3865static bool lan8841_rxtstamp(struct mii_timestamper *mii_ts,
3866 struct sk_buff *skb, int type)
3867{
3868 struct kszphy_ptp_priv *ptp_priv =
3869 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
3870 struct ptp_header *header = ptp_parse_header(skb, type);
3871 struct skb_shared_hwtstamps *shhwtstamps;
3872 struct timespec64 ts;
3873 unsigned long flags;
3874 u32 ts_header;
3875
3876 if (!header)
3877 return false;
3878
3879 if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
3880 type == PTP_CLASS_NONE)
3881 return false;
3882
3883 if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
3884 return false;
3885
3886 spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
3887 ts.tv_sec = ptp_priv->seconds;
3888 spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
3889 ts_header = __be32_to_cpu(header->reserved2);
3890
3891 shhwtstamps = skb_hwtstamps(skb);
3892 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3893
3894 /* Check for any wrap arounds for the second part */
3895 if ((ts.tv_sec & GENMASK(1, 0)) == 0 && (ts_header >> 30) == 3)
3896 ts.tv_sec -= GENMASK(1, 0) + 1;
3897 else if ((ts.tv_sec & GENMASK(1, 0)) == 3 && (ts_header >> 30) == 0)
3898 ts.tv_sec += 1;
3899
3900 shhwtstamps->hwtstamp =
3901 ktime_set((ts.tv_sec & ~(GENMASK(1, 0))) | ts_header >> 30,
3902 ts_header & GENMASK(29, 0));
3903 header->reserved2 = 0;
3904
3905 netif_rx(skb);
3906
3907 return true;
3908}
3909
3910#define LAN8841_EVENT_A 0
3911#define LAN8841_EVENT_B 1
3912#define LAN8841_PTP_LTC_TARGET_SEC_HI(event) ((event) == LAN8841_EVENT_A ? 278 : 288)
3913#define LAN8841_PTP_LTC_TARGET_SEC_LO(event) ((event) == LAN8841_EVENT_A ? 279 : 289)
3914#define LAN8841_PTP_LTC_TARGET_NS_HI(event) ((event) == LAN8841_EVENT_A ? 280 : 290)
3915#define LAN8841_PTP_LTC_TARGET_NS_LO(event) ((event) == LAN8841_EVENT_A ? 281 : 291)
3916
3917static int lan8841_ptp_set_target(struct kszphy_ptp_priv *ptp_priv, u8 event,
3918 s64 sec, u32 nsec)
3919{
3920 struct phy_device *phydev = ptp_priv->phydev;
3921 int ret;
3922
3923 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_HI(event),
3924 upper_16_bits(sec));
3925 if (ret)
3926 return ret;
3927
3928 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_LO(event),
3929 lower_16_bits(sec));
3930 if (ret)
3931 return ret;
3932
3933 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_HI(event) & 0x3fff,
3934 upper_16_bits(nsec));
3935 if (ret)
3936 return ret;
3937
3938 return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_LO(event),
3939 lower_16_bits(nsec));
3940}
3941
3942#define LAN8841_BUFFER_TIME 2
3943
3944static int lan8841_ptp_update_target(struct kszphy_ptp_priv *ptp_priv,
3945 const struct timespec64 *ts)
3946{
3947 return lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A,
3948 ts->tv_sec + LAN8841_BUFFER_TIME, 0);
3949}
3950
3951#define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event) ((event) == LAN8841_EVENT_A ? 282 : 292)
3952#define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event) ((event) == LAN8841_EVENT_A ? 283 : 293)
3953#define LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) ((event) == LAN8841_EVENT_A ? 284 : 294)
3954#define LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event) ((event) == LAN8841_EVENT_A ? 285 : 295)
3955
3956static int lan8841_ptp_set_reload(struct kszphy_ptp_priv *ptp_priv, u8 event,
3957 s64 sec, u32 nsec)
3958{
3959 struct phy_device *phydev = ptp_priv->phydev;
3960 int ret;
3961
3962 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event),
3963 upper_16_bits(sec));
3964 if (ret)
3965 return ret;
3966
3967 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event),
3968 lower_16_bits(sec));
3969 if (ret)
3970 return ret;
3971
3972 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) & 0x3fff,
3973 upper_16_bits(nsec));
3974 if (ret)
3975 return ret;
3976
3977 return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event),
3978 lower_16_bits(nsec));
3979}
3980
3981#define LAN8841_PTP_LTC_SET_SEC_HI 262
3982#define LAN8841_PTP_LTC_SET_SEC_MID 263
3983#define LAN8841_PTP_LTC_SET_SEC_LO 264
3984#define LAN8841_PTP_LTC_SET_NS_HI 265
3985#define LAN8841_PTP_LTC_SET_NS_LO 266
3986#define LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD BIT(4)
3987
3988static int lan8841_ptp_settime64(struct ptp_clock_info *ptp,
3989 const struct timespec64 *ts)
3990{
3991 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
3992 ptp_clock_info);
3993 struct phy_device *phydev = ptp_priv->phydev;
3994 unsigned long flags;
3995 int ret;
3996
3997 /* Set the value to be stored */
3998 mutex_lock(&ptp_priv->ptp_lock);
3999 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_LO, lower_16_bits(ts->tv_sec));
4000 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_MID, upper_16_bits(ts->tv_sec));
4001 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_HI, upper_32_bits(ts->tv_sec) & 0xffff);
4002 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_LO, lower_16_bits(ts->tv_nsec));
4003 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_HI, upper_16_bits(ts->tv_nsec) & 0x3fff);
4004
4005 /* Set the command to load the LTC */
4006 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4007 LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD);
4008 ret = lan8841_ptp_update_target(ptp_priv, ts);
4009 mutex_unlock(&ptp_priv->ptp_lock);
4010
4011 spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
4012 ptp_priv->seconds = ts->tv_sec;
4013 spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
4014
4015 return ret;
4016}
4017
4018#define LAN8841_PTP_LTC_RD_SEC_HI 358
4019#define LAN8841_PTP_LTC_RD_SEC_MID 359
4020#define LAN8841_PTP_LTC_RD_SEC_LO 360
4021#define LAN8841_PTP_LTC_RD_NS_HI 361
4022#define LAN8841_PTP_LTC_RD_NS_LO 362
4023#define LAN8841_PTP_CMD_CTL_PTP_LTC_READ BIT(3)
4024
4025static int lan8841_ptp_gettime64(struct ptp_clock_info *ptp,
4026 struct timespec64 *ts)
4027{
4028 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4029 ptp_clock_info);
4030 struct phy_device *phydev = ptp_priv->phydev;
4031 time64_t s;
4032 s64 ns;
4033
4034 mutex_lock(&ptp_priv->ptp_lock);
4035 /* Issue the command to read the LTC */
4036 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4037 LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
4038
4039 /* Read the LTC */
4040 s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);
4041 s <<= 16;
4042 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);
4043 s <<= 16;
4044 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);
4045
4046 ns = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_HI) & 0x3fff;
4047 ns <<= 16;
4048 ns |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_LO);
4049 mutex_unlock(&ptp_priv->ptp_lock);
4050
4051 set_normalized_timespec64(ts, s, ns);
4052 return 0;
4053}
4054
4055static void lan8841_ptp_getseconds(struct ptp_clock_info *ptp,
4056 struct timespec64 *ts)
4057{
4058 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4059 ptp_clock_info);
4060 struct phy_device *phydev = ptp_priv->phydev;
4061 time64_t s;
4062
4063 mutex_lock(&ptp_priv->ptp_lock);
4064 /* Issue the command to read the LTC */
4065 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4066 LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
4067
4068 /* Read the LTC */
4069 s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);
4070 s <<= 16;
4071 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);
4072 s <<= 16;
4073 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);
4074 mutex_unlock(&ptp_priv->ptp_lock);
4075
4076 set_normalized_timespec64(ts, s, 0);
4077}
4078
4079#define LAN8841_PTP_LTC_STEP_ADJ_LO 276
4080#define LAN8841_PTP_LTC_STEP_ADJ_HI 275
4081#define LAN8841_PTP_LTC_STEP_ADJ_DIR BIT(15)
4082#define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS BIT(5)
4083#define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS BIT(6)
4084
4085static int lan8841_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
4086{
4087 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4088 ptp_clock_info);
4089 struct phy_device *phydev = ptp_priv->phydev;
4090 struct timespec64 ts;
4091 bool add = true;
4092 u32 nsec;
4093 s32 sec;
4094 int ret;
4095
4096 /* The HW allows up to 15 sec to adjust the time, but here we limit to
4097 * 10 sec the adjustment. The reason is, in case the adjustment is 14
4098 * sec and 999999999 nsec, then we add 8ns to compansate the actual
4099 * increment so the value can be bigger than 15 sec. Therefore limit the
4100 * possible adjustments so we will not have these corner cases
4101 */
4102 if (delta > 10000000000LL || delta < -10000000000LL) {
4103 /* The timeadjustment is too big, so fall back using set time */
4104 u64 now;
4105
4106 ptp->gettime64(ptp, &ts);
4107
4108 now = ktime_to_ns(timespec64_to_ktime(ts));
4109 ts = ns_to_timespec64(now + delta);
4110
4111 ptp->settime64(ptp, &ts);
4112 return 0;
4113 }
4114
4115 sec = div_u64_rem(delta < 0 ? -delta : delta, NSEC_PER_SEC, &nsec);
4116 if (delta < 0 && nsec != 0) {
4117 /* It is not allowed to adjust low the nsec part, therefore
4118 * subtract more from second part and add to nanosecond such
4119 * that would roll over, so the second part will increase
4120 */
4121 sec--;
4122 nsec = NSEC_PER_SEC - nsec;
4123 }
4124
4125 /* Calculate the adjustments and the direction */
4126 if (delta < 0)
4127 add = false;
4128
4129 if (nsec > 0)
4130 /* add 8 ns to cover the likely normal increment */
4131 nsec += 8;
4132
4133 if (nsec >= NSEC_PER_SEC) {
4134 /* carry into seconds */
4135 sec++;
4136 nsec -= NSEC_PER_SEC;
4137 }
4138
4139 mutex_lock(&ptp_priv->ptp_lock);
4140 if (sec) {
4141 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO, sec);
4142 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4143 add ? LAN8841_PTP_LTC_STEP_ADJ_DIR : 0);
4144 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4145 LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS);
4146 }
4147
4148 if (nsec) {
4149 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO,
4150 nsec & 0xffff);
4151 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4152 (nsec >> 16) & 0x3fff);
4153 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4154 LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS);
4155 }
4156 mutex_unlock(&ptp_priv->ptp_lock);
4157
4158 /* Update the target clock */
4159 ptp->gettime64(ptp, &ts);
4160 mutex_lock(&ptp_priv->ptp_lock);
4161 ret = lan8841_ptp_update_target(ptp_priv, &ts);
4162 mutex_unlock(&ptp_priv->ptp_lock);
4163
4164 return ret;
4165}
4166
4167#define LAN8841_PTP_LTC_RATE_ADJ_HI 269
4168#define LAN8841_PTP_LTC_RATE_ADJ_HI_DIR BIT(15)
4169#define LAN8841_PTP_LTC_RATE_ADJ_LO 270
4170
4171static int lan8841_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
4172{
4173 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4174 ptp_clock_info);
4175 struct phy_device *phydev = ptp_priv->phydev;
4176 bool faster = true;
4177 u32 rate;
4178
4179 if (!scaled_ppm)
4180 return 0;
4181
4182 if (scaled_ppm < 0) {
4183 scaled_ppm = -scaled_ppm;
4184 faster = false;
4185 }
4186
4187 rate = LAN8841_1PPM_FORMAT * (upper_16_bits(scaled_ppm));
4188 rate += (LAN8841_1PPM_FORMAT * (lower_16_bits(scaled_ppm))) >> 16;
4189
4190 mutex_lock(&ptp_priv->ptp_lock);
4191 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_HI,
4192 faster ? LAN8841_PTP_LTC_RATE_ADJ_HI_DIR | (upper_16_bits(rate) & 0x3fff)
4193 : upper_16_bits(rate) & 0x3fff);
4194 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_LO, lower_16_bits(rate));
4195 mutex_unlock(&ptp_priv->ptp_lock);
4196
4197 return 0;
4198}
4199
4200static int lan8841_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
4201 enum ptp_pin_function func, unsigned int chan)
4202{
4203 switch (func) {
4204 case PTP_PF_NONE:
4205 case PTP_PF_PEROUT:
4206 case PTP_PF_EXTTS:
4207 break;
4208 default:
4209 return -1;
4210 }
4211
4212 return 0;
4213}
4214
4215#define LAN8841_PTP_GPIO_NUM 10
4216#define LAN8841_GPIO_EN 128
4217#define LAN8841_GPIO_DIR 129
4218#define LAN8841_GPIO_BUF 130
4219
4220static int lan8841_ptp_perout_off(struct kszphy_ptp_priv *ptp_priv, int pin)
4221{
4222 struct phy_device *phydev = ptp_priv->phydev;
4223 int ret;
4224
4225 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4226 if (ret)
4227 return ret;
4228
4229 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
4230 if (ret)
4231 return ret;
4232
4233 return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4234}
4235
4236static int lan8841_ptp_perout_on(struct kszphy_ptp_priv *ptp_priv, int pin)
4237{
4238 struct phy_device *phydev = ptp_priv->phydev;
4239 int ret;
4240
4241 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4242 if (ret)
4243 return ret;
4244
4245 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
4246 if (ret)
4247 return ret;
4248
4249 return phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4250}
4251
4252#define LAN8841_GPIO_DATA_SEL1 131
4253#define LAN8841_GPIO_DATA_SEL2 132
4254#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK GENMASK(2, 0)
4255#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A 1
4256#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B 2
4257#define LAN8841_PTP_GENERAL_CONFIG 257
4258#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A BIT(1)
4259#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B BIT(3)
4260#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK GENMASK(7, 4)
4261#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK GENMASK(11, 8)
4262#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A 4
4263#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B 7
4264
4265static int lan8841_ptp_remove_event(struct kszphy_ptp_priv *ptp_priv, int pin,
4266 u8 event)
4267{
4268 struct phy_device *phydev = ptp_priv->phydev;
4269 u16 tmp;
4270 int ret;
4271
4272 /* Now remove pin from the event. GPIO_DATA_SEL1 contains the GPIO
4273 * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
4274 * depending on the pin, it requires to read a different register
4275 */
4276 if (pin < 5) {
4277 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * pin);
4278 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1, tmp);
4279 } else {
4280 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * (pin - 5));
4281 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2, tmp);
4282 }
4283 if (ret)
4284 return ret;
4285
4286 /* Disable the event */
4287 if (event == LAN8841_EVENT_A)
4288 tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4289 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK;
4290 else
4291 tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4292 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK;
4293 return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, tmp);
4294}
4295
4296static int lan8841_ptp_enable_event(struct kszphy_ptp_priv *ptp_priv, int pin,
4297 u8 event, int pulse_width)
4298{
4299 struct phy_device *phydev = ptp_priv->phydev;
4300 u16 tmp;
4301 int ret;
4302
4303 /* Enable the event */
4304 if (event == LAN8841_EVENT_A)
4305 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
4306 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4307 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK,
4308 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4309 pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A);
4310 else
4311 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
4312 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4313 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK,
4314 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4315 pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B);
4316 if (ret)
4317 return ret;
4318
4319 /* Now connect the pin to the event. GPIO_DATA_SEL1 contains the GPIO
4320 * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
4321 * depending on the pin, it requires to read a different register
4322 */
4323 if (event == LAN8841_EVENT_A)
4324 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A;
4325 else
4326 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B;
4327
4328 if (pin < 5)
4329 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1,
4330 tmp << (3 * pin));
4331 else
4332 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2,
4333 tmp << (3 * (pin - 5)));
4334
4335 return ret;
4336}
4337
4338#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS 13
4339#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS 12
4340#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS 11
4341#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS 10
4342#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS 9
4343#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS 8
4344#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US 7
4345#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US 6
4346#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US 5
4347#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US 4
4348#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US 3
4349#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US 2
4350#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS 1
4351#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS 0
4352
4353static int lan8841_ptp_perout(struct ptp_clock_info *ptp,
4354 struct ptp_clock_request *rq, int on)
4355{
4356 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4357 ptp_clock_info);
4358 struct phy_device *phydev = ptp_priv->phydev;
4359 struct timespec64 ts_on, ts_period;
4360 s64 on_nsec, period_nsec;
4361 int pulse_width;
4362 int pin;
4363 int ret;
4364
4365 if (rq->perout.flags & ~PTP_PEROUT_DUTY_CYCLE)
4366 return -EOPNOTSUPP;
4367
4368 pin = ptp_find_pin(ptp_priv->ptp_clock, PTP_PF_PEROUT, rq->perout.index);
4369 if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
4370 return -EINVAL;
4371
4372 if (!on) {
4373 ret = lan8841_ptp_perout_off(ptp_priv, pin);
4374 if (ret)
4375 return ret;
4376
4377 return lan8841_ptp_remove_event(ptp_priv, LAN8841_EVENT_A, pin);
4378 }
4379
4380 ts_on.tv_sec = rq->perout.on.sec;
4381 ts_on.tv_nsec = rq->perout.on.nsec;
4382 on_nsec = timespec64_to_ns(&ts_on);
4383
4384 ts_period.tv_sec = rq->perout.period.sec;
4385 ts_period.tv_nsec = rq->perout.period.nsec;
4386 period_nsec = timespec64_to_ns(&ts_period);
4387
4388 if (period_nsec < 200) {
4389 pr_warn_ratelimited("%s: perout period too small, minimum is 200 nsec\n",
4390 phydev_name(phydev));
4391 return -EOPNOTSUPP;
4392 }
4393
4394 if (on_nsec >= period_nsec) {
4395 pr_warn_ratelimited("%s: pulse width must be smaller than period\n",
4396 phydev_name(phydev));
4397 return -EINVAL;
4398 }
4399
4400 switch (on_nsec) {
4401 case 200000000:
4402 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS;
4403 break;
4404 case 100000000:
4405 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS;
4406 break;
4407 case 50000000:
4408 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS;
4409 break;
4410 case 10000000:
4411 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS;
4412 break;
4413 case 5000000:
4414 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS;
4415 break;
4416 case 1000000:
4417 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS;
4418 break;
4419 case 500000:
4420 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US;
4421 break;
4422 case 100000:
4423 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US;
4424 break;
4425 case 50000:
4426 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US;
4427 break;
4428 case 10000:
4429 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US;
4430 break;
4431 case 5000:
4432 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US;
4433 break;
4434 case 1000:
4435 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US;
4436 break;
4437 case 500:
4438 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS;
4439 break;
4440 case 100:
4441 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
4442 break;
4443 default:
4444 pr_warn_ratelimited("%s: Use default duty cycle of 100ns\n",
4445 phydev_name(phydev));
4446 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
4447 break;
4448 }
4449
4450 mutex_lock(&ptp_priv->ptp_lock);
4451 ret = lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A, rq->perout.start.sec,
4452 rq->perout.start.nsec);
4453 mutex_unlock(&ptp_priv->ptp_lock);
4454 if (ret)
4455 return ret;
4456
4457 ret = lan8841_ptp_set_reload(ptp_priv, LAN8841_EVENT_A, rq->perout.period.sec,
4458 rq->perout.period.nsec);
4459 if (ret)
4460 return ret;
4461
4462 ret = lan8841_ptp_enable_event(ptp_priv, pin, LAN8841_EVENT_A,
4463 pulse_width);
4464 if (ret)
4465 return ret;
4466
4467 ret = lan8841_ptp_perout_on(ptp_priv, pin);
4468 if (ret)
4469 lan8841_ptp_remove_event(ptp_priv, pin, LAN8841_EVENT_A);
4470
4471 return ret;
4472}
4473
4474#define LAN8841_PTP_GPIO_CAP_EN 496
4475#define LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio) (BIT(gpio))
4476#define LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio) (BIT(gpio) << 8)
4477#define LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN BIT(2)
4478
4479static int lan8841_ptp_extts_on(struct kszphy_ptp_priv *ptp_priv, int pin,
4480 u32 flags)
4481{
4482 struct phy_device *phydev = ptp_priv->phydev;
4483 u16 tmp = 0;
4484 int ret;
4485
4486 /* Set GPIO to be intput */
4487 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4488 if (ret)
4489 return ret;
4490
4491 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4492 if (ret)
4493 return ret;
4494
4495 /* Enable capture on the edges of the pin */
4496 if (flags & PTP_RISING_EDGE)
4497 tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin);
4498 if (flags & PTP_FALLING_EDGE)
4499 tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin);
4500 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN, tmp);
4501 if (ret)
4502 return ret;
4503
4504 /* Enable interrupt */
4505 return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
4506 LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
4507 LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN);
4508}
4509
4510static int lan8841_ptp_extts_off(struct kszphy_ptp_priv *ptp_priv, int pin)
4511{
4512 struct phy_device *phydev = ptp_priv->phydev;
4513 int ret;
4514
4515 /* Set GPIO to be output */
4516 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4517 if (ret)
4518 return ret;
4519
4520 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4521 if (ret)
4522 return ret;
4523
4524 /* Disable capture on both of the edges */
4525 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN,
4526 LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin) |
4527 LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin),
4528 0);
4529 if (ret)
4530 return ret;
4531
4532 /* Disable interrupt */
4533 return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
4534 LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
4535 0);
4536}
4537
4538static int lan8841_ptp_extts(struct ptp_clock_info *ptp,
4539 struct ptp_clock_request *rq, int on)
4540{
4541 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4542 ptp_clock_info);
4543 int pin;
4544 int ret;
4545
4546 /* Reject requests with unsupported flags */
4547 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
4548 PTP_EXTTS_EDGES |
4549 PTP_STRICT_FLAGS))
4550 return -EOPNOTSUPP;
4551
4552 pin = ptp_find_pin(ptp_priv->ptp_clock, PTP_PF_EXTTS, rq->extts.index);
4553 if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
4554 return -EINVAL;
4555
4556 mutex_lock(&ptp_priv->ptp_lock);
4557 if (on)
4558 ret = lan8841_ptp_extts_on(ptp_priv, pin, rq->extts.flags);
4559 else
4560 ret = lan8841_ptp_extts_off(ptp_priv, pin);
4561 mutex_unlock(&ptp_priv->ptp_lock);
4562
4563 return ret;
4564}
4565
4566static int lan8841_ptp_enable(struct ptp_clock_info *ptp,
4567 struct ptp_clock_request *rq, int on)
4568{
4569 switch (rq->type) {
4570 case PTP_CLK_REQ_EXTTS:
4571 return lan8841_ptp_extts(ptp, rq, on);
4572 case PTP_CLK_REQ_PEROUT:
4573 return lan8841_ptp_perout(ptp, rq, on);
4574 default:
4575 return -EOPNOTSUPP;
4576 }
4577
4578 return 0;
4579}
4580
4581static long lan8841_ptp_do_aux_work(struct ptp_clock_info *ptp)
4582{
4583 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4584 ptp_clock_info);
4585 struct timespec64 ts;
4586 unsigned long flags;
4587
4588 lan8841_ptp_getseconds(&ptp_priv->ptp_clock_info, &ts);
4589
4590 spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
4591 ptp_priv->seconds = ts.tv_sec;
4592 spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
4593
4594 return nsecs_to_jiffies(LAN8841_GET_SEC_LTC_DELAY);
4595}
4596
4597static struct ptp_clock_info lan8841_ptp_clock_info = {
4598 .owner = THIS_MODULE,
4599 .name = "lan8841 ptp",
4600 .max_adj = 31249999,
4601 .gettime64 = lan8841_ptp_gettime64,
4602 .settime64 = lan8841_ptp_settime64,
4603 .adjtime = lan8841_ptp_adjtime,
4604 .adjfine = lan8841_ptp_adjfine,
4605 .verify = lan8841_ptp_verify,
4606 .enable = lan8841_ptp_enable,
4607 .do_aux_work = lan8841_ptp_do_aux_work,
4608 .n_per_out = LAN8841_PTP_GPIO_NUM,
4609 .n_ext_ts = LAN8841_PTP_GPIO_NUM,
4610 .n_pins = LAN8841_PTP_GPIO_NUM,
4611};
4612
4613#define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER 3
4614#define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN BIT(0)
4615
4616static int lan8841_probe(struct phy_device *phydev)
4617{
4618 struct kszphy_ptp_priv *ptp_priv;
4619 struct kszphy_priv *priv;
4620 int err;
4621
4622 err = kszphy_probe(phydev);
4623 if (err)
4624 return err;
4625
4626 if (phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4627 LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER) &
4628 LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN)
4629 phydev->interface = PHY_INTERFACE_MODE_RGMII_RXID;
4630
4631 /* Register the clock */
4632 if (!IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
4633 return 0;
4634
4635 priv = phydev->priv;
4636 ptp_priv = &priv->ptp_priv;
4637
4638 ptp_priv->pin_config = devm_kcalloc(&phydev->mdio.dev,
4639 LAN8841_PTP_GPIO_NUM,
4640 sizeof(*ptp_priv->pin_config),
4641 GFP_KERNEL);
4642 if (!ptp_priv->pin_config)
4643 return -ENOMEM;
4644
4645 for (int i = 0; i < LAN8841_PTP_GPIO_NUM; ++i) {
4646 struct ptp_pin_desc *p = &ptp_priv->pin_config[i];
4647
4648 snprintf(p->name, sizeof(p->name), "pin%d", i);
4649 p->index = i;
4650 p->func = PTP_PF_NONE;
4651 }
4652
4653 ptp_priv->ptp_clock_info = lan8841_ptp_clock_info;
4654 ptp_priv->ptp_clock_info.pin_config = ptp_priv->pin_config;
4655 ptp_priv->ptp_clock = ptp_clock_register(&ptp_priv->ptp_clock_info,
4656 &phydev->mdio.dev);
4657 if (IS_ERR(ptp_priv->ptp_clock)) {
4658 phydev_err(phydev, "ptp_clock_register failed: %lu\n",
4659 PTR_ERR(ptp_priv->ptp_clock));
4660 return -EINVAL;
4661 }
4662
4663 if (!ptp_priv->ptp_clock)
4664 return 0;
4665
4666 /* Initialize the SW */
4667 skb_queue_head_init(&ptp_priv->tx_queue);
4668 ptp_priv->phydev = phydev;
4669 mutex_init(&ptp_priv->ptp_lock);
4670 spin_lock_init(&ptp_priv->seconds_lock);
4671
4672 ptp_priv->mii_ts.rxtstamp = lan8841_rxtstamp;
4673 ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
4674 ptp_priv->mii_ts.hwtstamp = lan8841_hwtstamp;
4675 ptp_priv->mii_ts.ts_info = lan8841_ts_info;
4676
4677 phydev->mii_ts = &ptp_priv->mii_ts;
4678
4679 return 0;
4680}
4681
4682static int lan8841_suspend(struct phy_device *phydev)
4683{
4684 struct kszphy_priv *priv = phydev->priv;
4685 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
4686
4687 if (ptp_priv->ptp_clock)
4688 ptp_cancel_worker_sync(ptp_priv->ptp_clock);
4689
4690 return genphy_suspend(phydev);
4691}
4692
4693static struct phy_driver ksphy_driver[] = {
4694{
4695 .phy_id = PHY_ID_KS8737,
4696 .phy_id_mask = MICREL_PHY_ID_MASK,
4697 .name = "Micrel KS8737",
4698 /* PHY_BASIC_FEATURES */
4699 .driver_data = &ks8737_type,
4700 .probe = kszphy_probe,
4701 .config_init = kszphy_config_init,
4702 .config_intr = kszphy_config_intr,
4703 .handle_interrupt = kszphy_handle_interrupt,
4704 .suspend = kszphy_suspend,
4705 .resume = kszphy_resume,
4706}, {
4707 .phy_id = PHY_ID_KSZ8021,
4708 .phy_id_mask = 0x00ffffff,
4709 .name = "Micrel KSZ8021 or KSZ8031",
4710 /* PHY_BASIC_FEATURES */
4711 .driver_data = &ksz8021_type,
4712 .probe = kszphy_probe,
4713 .config_init = kszphy_config_init,
4714 .config_intr = kszphy_config_intr,
4715 .handle_interrupt = kszphy_handle_interrupt,
4716 .get_sset_count = kszphy_get_sset_count,
4717 .get_strings = kszphy_get_strings,
4718 .get_stats = kszphy_get_stats,
4719 .suspend = kszphy_suspend,
4720 .resume = kszphy_resume,
4721}, {
4722 .phy_id = PHY_ID_KSZ8031,
4723 .phy_id_mask = 0x00ffffff,
4724 .name = "Micrel KSZ8031",
4725 /* PHY_BASIC_FEATURES */
4726 .driver_data = &ksz8021_type,
4727 .probe = kszphy_probe,
4728 .config_init = kszphy_config_init,
4729 .config_intr = kszphy_config_intr,
4730 .handle_interrupt = kszphy_handle_interrupt,
4731 .get_sset_count = kszphy_get_sset_count,
4732 .get_strings = kszphy_get_strings,
4733 .get_stats = kszphy_get_stats,
4734 .suspend = kszphy_suspend,
4735 .resume = kszphy_resume,
4736}, {
4737 .phy_id = PHY_ID_KSZ8041,
4738 .phy_id_mask = MICREL_PHY_ID_MASK,
4739 .name = "Micrel KSZ8041",
4740 /* PHY_BASIC_FEATURES */
4741 .driver_data = &ksz8041_type,
4742 .probe = kszphy_probe,
4743 .config_init = ksz8041_config_init,
4744 .config_aneg = ksz8041_config_aneg,
4745 .config_intr = kszphy_config_intr,
4746 .handle_interrupt = kszphy_handle_interrupt,
4747 .get_sset_count = kszphy_get_sset_count,
4748 .get_strings = kszphy_get_strings,
4749 .get_stats = kszphy_get_stats,
4750 /* No suspend/resume callbacks because of errata DS80000700A,
4751 * receiver error following software power down.
4752 */
4753}, {
4754 .phy_id = PHY_ID_KSZ8041RNLI,
4755 .phy_id_mask = MICREL_PHY_ID_MASK,
4756 .name = "Micrel KSZ8041RNLI",
4757 /* PHY_BASIC_FEATURES */
4758 .driver_data = &ksz8041_type,
4759 .probe = kszphy_probe,
4760 .config_init = kszphy_config_init,
4761 .config_intr = kszphy_config_intr,
4762 .handle_interrupt = kszphy_handle_interrupt,
4763 .get_sset_count = kszphy_get_sset_count,
4764 .get_strings = kszphy_get_strings,
4765 .get_stats = kszphy_get_stats,
4766 .suspend = kszphy_suspend,
4767 .resume = kszphy_resume,
4768}, {
4769 .name = "Micrel KSZ8051",
4770 /* PHY_BASIC_FEATURES */
4771 .driver_data = &ksz8051_type,
4772 .probe = kszphy_probe,
4773 .config_init = kszphy_config_init,
4774 .config_intr = kszphy_config_intr,
4775 .handle_interrupt = kszphy_handle_interrupt,
4776 .get_sset_count = kszphy_get_sset_count,
4777 .get_strings = kszphy_get_strings,
4778 .get_stats = kszphy_get_stats,
4779 .match_phy_device = ksz8051_match_phy_device,
4780 .suspend = kszphy_suspend,
4781 .resume = kszphy_resume,
4782}, {
4783 .phy_id = PHY_ID_KSZ8001,
4784 .name = "Micrel KSZ8001 or KS8721",
4785 .phy_id_mask = 0x00fffffc,
4786 /* PHY_BASIC_FEATURES */
4787 .driver_data = &ksz8041_type,
4788 .probe = kszphy_probe,
4789 .config_init = kszphy_config_init,
4790 .config_intr = kszphy_config_intr,
4791 .handle_interrupt = kszphy_handle_interrupt,
4792 .get_sset_count = kszphy_get_sset_count,
4793 .get_strings = kszphy_get_strings,
4794 .get_stats = kszphy_get_stats,
4795 .suspend = kszphy_suspend,
4796 .resume = kszphy_resume,
4797}, {
4798 .phy_id = PHY_ID_KSZ8081,
4799 .name = "Micrel KSZ8081 or KSZ8091",
4800 .phy_id_mask = MICREL_PHY_ID_MASK,
4801 .flags = PHY_POLL_CABLE_TEST,
4802 /* PHY_BASIC_FEATURES */
4803 .driver_data = &ksz8081_type,
4804 .probe = kszphy_probe,
4805 .config_init = ksz8081_config_init,
4806 .soft_reset = genphy_soft_reset,
4807 .config_aneg = ksz8081_config_aneg,
4808 .read_status = ksz8081_read_status,
4809 .config_intr = kszphy_config_intr,
4810 .handle_interrupt = kszphy_handle_interrupt,
4811 .get_sset_count = kszphy_get_sset_count,
4812 .get_strings = kszphy_get_strings,
4813 .get_stats = kszphy_get_stats,
4814 .suspend = kszphy_suspend,
4815 .resume = kszphy_resume,
4816 .cable_test_start = ksz886x_cable_test_start,
4817 .cable_test_get_status = ksz886x_cable_test_get_status,
4818}, {
4819 .phy_id = PHY_ID_KSZ8061,
4820 .name = "Micrel KSZ8061",
4821 .phy_id_mask = MICREL_PHY_ID_MASK,
4822 /* PHY_BASIC_FEATURES */
4823 .probe = kszphy_probe,
4824 .config_init = ksz8061_config_init,
4825 .soft_reset = genphy_soft_reset,
4826 .config_intr = kszphy_config_intr,
4827 .handle_interrupt = kszphy_handle_interrupt,
4828 .suspend = kszphy_suspend,
4829 .resume = kszphy_resume,
4830}, {
4831 .phy_id = PHY_ID_KSZ9021,
4832 .phy_id_mask = 0x000ffffe,
4833 .name = "Micrel KSZ9021 Gigabit PHY",
4834 /* PHY_GBIT_FEATURES */
4835 .driver_data = &ksz9021_type,
4836 .probe = kszphy_probe,
4837 .get_features = ksz9031_get_features,
4838 .config_init = ksz9021_config_init,
4839 .config_intr = kszphy_config_intr,
4840 .handle_interrupt = kszphy_handle_interrupt,
4841 .get_sset_count = kszphy_get_sset_count,
4842 .get_strings = kszphy_get_strings,
4843 .get_stats = kszphy_get_stats,
4844 .suspend = kszphy_suspend,
4845 .resume = kszphy_resume,
4846 .read_mmd = genphy_read_mmd_unsupported,
4847 .write_mmd = genphy_write_mmd_unsupported,
4848}, {
4849 .phy_id = PHY_ID_KSZ9031,
4850 .phy_id_mask = MICREL_PHY_ID_MASK,
4851 .name = "Micrel KSZ9031 Gigabit PHY",
4852 .flags = PHY_POLL_CABLE_TEST,
4853 .driver_data = &ksz9021_type,
4854 .probe = kszphy_probe,
4855 .get_features = ksz9031_get_features,
4856 .config_init = ksz9031_config_init,
4857 .soft_reset = genphy_soft_reset,
4858 .read_status = ksz9031_read_status,
4859 .config_intr = kszphy_config_intr,
4860 .handle_interrupt = kszphy_handle_interrupt,
4861 .get_sset_count = kszphy_get_sset_count,
4862 .get_strings = kszphy_get_strings,
4863 .get_stats = kszphy_get_stats,
4864 .suspend = kszphy_suspend,
4865 .resume = kszphy_resume,
4866 .cable_test_start = ksz9x31_cable_test_start,
4867 .cable_test_get_status = ksz9x31_cable_test_get_status,
4868}, {
4869 .phy_id = PHY_ID_LAN8814,
4870 .phy_id_mask = MICREL_PHY_ID_MASK,
4871 .name = "Microchip INDY Gigabit Quad PHY",
4872 .flags = PHY_POLL_CABLE_TEST,
4873 .config_init = lan8814_config_init,
4874 .driver_data = &lan8814_type,
4875 .probe = lan8814_probe,
4876 .soft_reset = genphy_soft_reset,
4877 .read_status = ksz9031_read_status,
4878 .get_sset_count = kszphy_get_sset_count,
4879 .get_strings = kszphy_get_strings,
4880 .get_stats = kszphy_get_stats,
4881 .suspend = genphy_suspend,
4882 .resume = kszphy_resume,
4883 .config_intr = lan8814_config_intr,
4884 .handle_interrupt = lan8814_handle_interrupt,
4885 .cable_test_start = lan8814_cable_test_start,
4886 .cable_test_get_status = ksz886x_cable_test_get_status,
4887}, {
4888 .phy_id = PHY_ID_LAN8804,
4889 .phy_id_mask = MICREL_PHY_ID_MASK,
4890 .name = "Microchip LAN966X Gigabit PHY",
4891 .config_init = lan8804_config_init,
4892 .driver_data = &ksz9021_type,
4893 .probe = kszphy_probe,
4894 .soft_reset = genphy_soft_reset,
4895 .read_status = ksz9031_read_status,
4896 .get_sset_count = kszphy_get_sset_count,
4897 .get_strings = kszphy_get_strings,
4898 .get_stats = kszphy_get_stats,
4899 .suspend = genphy_suspend,
4900 .resume = kszphy_resume,
4901 .config_intr = lan8804_config_intr,
4902 .handle_interrupt = lan8804_handle_interrupt,
4903}, {
4904 .phy_id = PHY_ID_LAN8841,
4905 .phy_id_mask = MICREL_PHY_ID_MASK,
4906 .name = "Microchip LAN8841 Gigabit PHY",
4907 .flags = PHY_POLL_CABLE_TEST,
4908 .driver_data = &lan8841_type,
4909 .config_init = lan8841_config_init,
4910 .probe = lan8841_probe,
4911 .soft_reset = genphy_soft_reset,
4912 .config_intr = lan8841_config_intr,
4913 .handle_interrupt = lan8841_handle_interrupt,
4914 .get_sset_count = kszphy_get_sset_count,
4915 .get_strings = kszphy_get_strings,
4916 .get_stats = kszphy_get_stats,
4917 .suspend = lan8841_suspend,
4918 .resume = genphy_resume,
4919 .cable_test_start = lan8814_cable_test_start,
4920 .cable_test_get_status = ksz886x_cable_test_get_status,
4921}, {
4922 .phy_id = PHY_ID_KSZ9131,
4923 .phy_id_mask = MICREL_PHY_ID_MASK,
4924 .name = "Microchip KSZ9131 Gigabit PHY",
4925 /* PHY_GBIT_FEATURES */
4926 .flags = PHY_POLL_CABLE_TEST,
4927 .driver_data = &ksz9131_type,
4928 .probe = kszphy_probe,
4929 .soft_reset = genphy_soft_reset,
4930 .config_init = ksz9131_config_init,
4931 .config_intr = kszphy_config_intr,
4932 .config_aneg = ksz9131_config_aneg,
4933 .read_status = ksz9131_read_status,
4934 .handle_interrupt = kszphy_handle_interrupt,
4935 .get_sset_count = kszphy_get_sset_count,
4936 .get_strings = kszphy_get_strings,
4937 .get_stats = kszphy_get_stats,
4938 .suspend = kszphy_suspend,
4939 .resume = kszphy_resume,
4940 .cable_test_start = ksz9x31_cable_test_start,
4941 .cable_test_get_status = ksz9x31_cable_test_get_status,
4942 .get_features = ksz9477_get_features,
4943}, {
4944 .phy_id = PHY_ID_KSZ8873MLL,
4945 .phy_id_mask = MICREL_PHY_ID_MASK,
4946 .name = "Micrel KSZ8873MLL Switch",
4947 /* PHY_BASIC_FEATURES */
4948 .config_init = kszphy_config_init,
4949 .config_aneg = ksz8873mll_config_aneg,
4950 .read_status = ksz8873mll_read_status,
4951 .suspend = genphy_suspend,
4952 .resume = genphy_resume,
4953}, {
4954 .phy_id = PHY_ID_KSZ886X,
4955 .phy_id_mask = MICREL_PHY_ID_MASK,
4956 .name = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",
4957 .driver_data = &ksz886x_type,
4958 /* PHY_BASIC_FEATURES */
4959 .flags = PHY_POLL_CABLE_TEST,
4960 .config_init = kszphy_config_init,
4961 .config_aneg = ksz886x_config_aneg,
4962 .read_status = ksz886x_read_status,
4963 .suspend = genphy_suspend,
4964 .resume = genphy_resume,
4965 .cable_test_start = ksz886x_cable_test_start,
4966 .cable_test_get_status = ksz886x_cable_test_get_status,
4967}, {
4968 .name = "Micrel KSZ87XX Switch",
4969 /* PHY_BASIC_FEATURES */
4970 .config_init = kszphy_config_init,
4971 .match_phy_device = ksz8795_match_phy_device,
4972 .suspend = genphy_suspend,
4973 .resume = genphy_resume,
4974}, {
4975 .phy_id = PHY_ID_KSZ9477,
4976 .phy_id_mask = MICREL_PHY_ID_MASK,
4977 .name = "Microchip KSZ9477",
4978 /* PHY_GBIT_FEATURES */
4979 .config_init = ksz9477_config_init,
4980 .config_intr = kszphy_config_intr,
4981 .handle_interrupt = kszphy_handle_interrupt,
4982 .suspend = genphy_suspend,
4983 .resume = genphy_resume,
4984 .get_features = ksz9477_get_features,
4985} };
4986
4987module_phy_driver(ksphy_driver);
4988
4989MODULE_DESCRIPTION("Micrel PHY driver");
4990MODULE_AUTHOR("David J. Choi");
4991MODULE_LICENSE("GPL");
4992
4993static struct mdio_device_id __maybe_unused micrel_tbl[] = {
4994 { PHY_ID_KSZ9021, 0x000ffffe },
4995 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
4996 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
4997 { PHY_ID_KSZ8001, 0x00fffffc },
4998 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
4999 { PHY_ID_KSZ8021, 0x00ffffff },
5000 { PHY_ID_KSZ8031, 0x00ffffff },
5001 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
5002 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
5003 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
5004 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
5005 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
5006 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
5007 { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
5008 { PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
5009 { PHY_ID_LAN8841, MICREL_PHY_ID_MASK },
5010 { }
5011};
5012
5013MODULE_DEVICE_TABLE(mdio, micrel_tbl);