1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
  4 *
  5 * Copyright (C) 2014-2024 Broadcom
  6 */
  7
  8#define pr_fmt(fmt)	KBUILD_MODNAME	": " fmt
  9
 10#include <linux/init.h>
 11#include <linux/slab.h>
 12#include <linux/module.h>
 13#include <linux/platform_device.h>
 14#include <linux/spinlock.h>
 15#include <linux/of.h>
 16#include <linux/of_irq.h>
 17#include <linux/of_address.h>
 18#include <linux/interrupt.h>
 19#include <linux/irq.h>
 20#include <linux/io.h>
 21#include <linux/irqdomain.h>
 22#include <linux/irqchip.h>
 23#include <linux/irqchip/chained_irq.h>
 24
 25struct brcmstb_intc_init_params {
 26	irq_flow_handler_t handler;
 27	int cpu_status;
 28	int cpu_clear;
 29	int cpu_mask_status;
 30	int cpu_mask_set;
 31	int cpu_mask_clear;
 32};
 33
 34/* Register offsets in the L2 latched interrupt controller */
 35static const struct brcmstb_intc_init_params l2_edge_intc_init = {
 36	.handler		= handle_edge_irq,
 37	.cpu_status		= 0x00,
 38	.cpu_clear		= 0x08,
 39	.cpu_mask_status	= 0x0c,
 40	.cpu_mask_set		= 0x10,
 41	.cpu_mask_clear		= 0x14
 42};
 43
 44/* Register offsets in the L2 level interrupt controller */
 45static const struct brcmstb_intc_init_params l2_lvl_intc_init = {
 46	.handler		= handle_level_irq,
 47	.cpu_status		= 0x00,
 48	.cpu_clear		= -1, /* Register not present */
 49	.cpu_mask_status	= 0x04,
 50	.cpu_mask_set		= 0x08,
 51	.cpu_mask_clear		= 0x0C
 52};
 53
 54/* L2 intc private data structure */
 55struct brcmstb_l2_intc_data {
 56	struct irq_domain *domain;
 57	struct irq_chip_generic *gc;
 58	int status_offset;
 59	int mask_offset;
 60	bool can_wake;
 61	u32 saved_mask; /* for suspend/resume */
 62};
 63
 64/**
 65 * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
 66 * @d: irq_data
 67 *
 68 * Chip has separate enable/disable registers instead of a single mask
 69 * register and pending interrupt is acknowledged by setting a bit.
 70 *
 71 * Note: This function is generic and could easily be added to the
 72 * generic irqchip implementation if there ever becomes a will to do so.
 73 * Perhaps with a name like irq_gc_mask_disable_and_ack_set().
 74 *
 75 * e.g.: https://patchwork.kernel.org/patch/9831047/
 76 */
 77static void brcmstb_l2_mask_and_ack(struct irq_data *d)
 78{
 79	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 80	struct irq_chip_type *ct = irq_data_get_chip_type(d);
 81	u32 mask = d->mask;
 82
 83	irq_gc_lock(gc);
 84	irq_reg_writel(gc, mask, ct->regs.disable);
 85	*ct->mask_cache &= ~mask;
 86	irq_reg_writel(gc, mask, ct->regs.ack);
 87	irq_gc_unlock(gc);
 88}
 89
 90static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc)
 91{
 92	struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
 93	struct irq_chip *chip = irq_desc_get_chip(desc);
 94	unsigned int irq;
 95	u32 status;
 96
 97	chained_irq_enter(chip, desc);
 98
 99	status = irq_reg_readl(b->gc, b->status_offset) &
100		~(irq_reg_readl(b->gc, b->mask_offset));
101
102	if (status == 0) {
103		raw_spin_lock(&desc->lock);
104		handle_bad_irq(desc);
105		raw_spin_unlock(&desc->lock);
106		goto out;
107	}
108
109	do {
110		irq = ffs(status) - 1;
111		status &= ~(1 << irq);
112		generic_handle_domain_irq(b->domain, irq);
113	} while (status);
114out:
115	/* Don't ack parent before all device writes are done */
116	wmb();
117
118	chained_irq_exit(chip, desc);
119}
120
121static void brcmstb_l2_intc_suspend(struct irq_data *d)
122{
123	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
124	struct irq_chip_type *ct = irq_data_get_chip_type(d);
125	struct brcmstb_l2_intc_data *b = gc->private;
126	unsigned long flags;
127
128	irq_gc_lock_irqsave(gc, flags);
129	/* Save the current mask */
130	b->saved_mask = irq_reg_readl(gc, ct->regs.mask);
131
132	if (b->can_wake) {
133		/* Program the wakeup mask */
134		irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);
135		irq_reg_writel(gc, gc->wake_active, ct->regs.enable);
136	}
137	irq_gc_unlock_irqrestore(gc, flags);
138}
139
140static void brcmstb_l2_intc_resume(struct irq_data *d)
141{
142	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
143	struct irq_chip_type *ct = irq_data_get_chip_type(d);
144	struct brcmstb_l2_intc_data *b = gc->private;
145	unsigned long flags;
146
147	irq_gc_lock_irqsave(gc, flags);
148	if (ct->chip.irq_ack) {
149		/* Clear unmasked non-wakeup interrupts */
150		irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,
151				ct->regs.ack);
152	}
153
154	/* Restore the saved mask */
155	irq_reg_writel(gc, b->saved_mask, ct->regs.disable);
156	irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);
157	irq_gc_unlock_irqrestore(gc, flags);
158}
159
160static int __init brcmstb_l2_intc_of_init(struct device_node *np,
161					  struct device_node *parent,
162					  const struct brcmstb_intc_init_params
163					  *init_params)
164{
165	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
166	unsigned int set = 0;
167	struct brcmstb_l2_intc_data *data;
168	struct irq_chip_type *ct;
169	int ret;
170	unsigned int flags;
171	int parent_irq;
172	void __iomem *base;
173
174	data = kzalloc(sizeof(*data), GFP_KERNEL);
175	if (!data)
176		return -ENOMEM;
177
178	base = of_iomap(np, 0);
179	if (!base) {
180		pr_err("failed to remap intc L2 registers\n");
181		ret = -ENOMEM;
182		goto out_free;
183	}
184
185	/* Disable all interrupts by default */
186	writel(0xffffffff, base + init_params->cpu_mask_set);
187
188	/* Wakeup interrupts may be retained from S5 (cold boot) */
189	data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");
190	if (!data->can_wake && (init_params->cpu_clear >= 0))
191		writel(0xffffffff, base + init_params->cpu_clear);
192
193	parent_irq = irq_of_parse_and_map(np, 0);
194	if (!parent_irq) {
195		pr_err("failed to find parent interrupt\n");
196		ret = -EINVAL;
197		goto out_unmap;
198	}
199
200	data->domain = irq_domain_add_linear(np, 32,
201				&irq_generic_chip_ops, NULL);
202	if (!data->domain) {
203		ret = -ENOMEM;
204		goto out_unmap;
205	}
206
207	/* MIPS chips strapped for BE will automagically configure the
208	 * peripheral registers for CPU-native byte order.
209	 */
210	flags = 0;
211	if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
212		flags |= IRQ_GC_BE_IO;
213
214	if (init_params->handler == handle_level_irq)
215		set |= IRQ_LEVEL;
216
217	/* Allocate a single Generic IRQ chip for this node */
218	ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
219			np->full_name, init_params->handler, clr, set, flags);
220	if (ret) {
221		pr_err("failed to allocate generic irq chip\n");
222		goto out_free_domain;
223	}
224
225	/* Set the IRQ chaining logic */
226	irq_set_chained_handler_and_data(parent_irq,
227					 brcmstb_l2_intc_irq_handle, data);
228
229	data->gc = irq_get_domain_generic_chip(data->domain, 0);
230	data->gc->reg_base = base;
231	data->gc->private = data;
232	data->status_offset = init_params->cpu_status;
233	data->mask_offset = init_params->cpu_mask_status;
234
235	ct = data->gc->chip_types;
236
237	if (init_params->cpu_clear >= 0) {
238		ct->regs.ack = init_params->cpu_clear;
239		ct->chip.irq_ack = irq_gc_ack_set_bit;
240		ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;
241	} else {
242		/* No Ack - but still slightly more efficient to define this */
243		ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
244	}
245
246	ct->chip.irq_mask = irq_gc_mask_disable_reg;
247	ct->regs.disable = init_params->cpu_mask_set;
248	ct->regs.mask = init_params->cpu_mask_status;
249
250	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
251	ct->regs.enable = init_params->cpu_mask_clear;
252
253	ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
254	ct->chip.irq_resume = brcmstb_l2_intc_resume;
255	ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend;
256
257	if (data->can_wake) {
258		/* This IRQ chip can wake the system, set all child interrupts
259		 * in wake_enabled mask
260		 */
261		data->gc->wake_enabled = 0xffffffff;
262		ct->chip.irq_set_wake = irq_gc_set_wake;
263		enable_irq_wake(parent_irq);
264	}
265
266	pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq);
267
268	return 0;
269
270out_free_domain:
271	irq_domain_remove(data->domain);
272out_unmap:
273	iounmap(base);
274out_free:
275	kfree(data);
276	return ret;
277}
278
279static int __init brcmstb_l2_edge_intc_of_init(struct device_node *np,
280	struct device_node *parent)
281{
282	return brcmstb_l2_intc_of_init(np, parent, &l2_edge_intc_init);
283}
284
285static int __init brcmstb_l2_lvl_intc_of_init(struct device_node *np,
286	struct device_node *parent)
287{
288	return brcmstb_l2_intc_of_init(np, parent, &l2_lvl_intc_init);
289}
290
291IRQCHIP_PLATFORM_DRIVER_BEGIN(brcmstb_l2)
292IRQCHIP_MATCH("brcm,l2-intc", brcmstb_l2_edge_intc_of_init)
293IRQCHIP_MATCH("brcm,hif-spi-l2-intc", brcmstb_l2_edge_intc_of_init)
294IRQCHIP_MATCH("brcm,upg-aux-aon-l2-intc", brcmstb_l2_edge_intc_of_init)
295IRQCHIP_MATCH("brcm,bcm7271-l2-intc", brcmstb_l2_lvl_intc_of_init)
296IRQCHIP_PLATFORM_DRIVER_END(brcmstb_l2)
297MODULE_DESCRIPTION("Broadcom STB generic L2 interrupt controller");
298MODULE_LICENSE("GPL v2");