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1/*
2 * SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation
4 */
5
6#include <linux/bitfield.h>
7#include <linux/clk.h>
8#include <linux/delay.h>
9#include <linux/interconnect.h>
10#include <linux/irq.h>
11#include <linux/irqchip.h>
12#include <linux/irqdesc.h>
13#include <linux/irqchip/chained_irq.h>
14#include <linux/of_platform.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/reset.h>
18
19#include "msm_mdss.h"
20#include "msm_kms.h"
21
22#define HW_REV 0x0
23#define HW_INTR_STATUS 0x0010
24
25#define UBWC_DEC_HW_VERSION 0x58
26#define UBWC_STATIC 0x144
27#define UBWC_CTRL_2 0x150
28#define UBWC_PREDICTION_MODE 0x154
29
30#define MIN_IB_BW 400000000UL /* Min ib vote 400MB */
31
32#define DEFAULT_REG_BW 153600 /* Used in mdss fbdev driver */
33
34struct msm_mdss {
35 struct device *dev;
36
37 void __iomem *mmio;
38 struct clk_bulk_data *clocks;
39 size_t num_clocks;
40 bool is_mdp5;
41 struct {
42 unsigned long enabled_mask;
43 struct irq_domain *domain;
44 } irq_controller;
45 const struct msm_mdss_data *mdss_data;
46 struct icc_path *mdp_path[2];
47 u32 num_mdp_paths;
48 struct icc_path *reg_bus_path;
49};
50
51static int msm_mdss_parse_data_bus_icc_path(struct device *dev,
52 struct msm_mdss *msm_mdss)
53{
54 struct icc_path *path0;
55 struct icc_path *path1;
56 struct icc_path *reg_bus_path;
57
58 path0 = devm_of_icc_get(dev, "mdp0-mem");
59 if (IS_ERR_OR_NULL(path0))
60 return PTR_ERR_OR_ZERO(path0);
61
62 msm_mdss->mdp_path[0] = path0;
63 msm_mdss->num_mdp_paths = 1;
64
65 path1 = devm_of_icc_get(dev, "mdp1-mem");
66 if (!IS_ERR_OR_NULL(path1)) {
67 msm_mdss->mdp_path[1] = path1;
68 msm_mdss->num_mdp_paths++;
69 }
70
71 reg_bus_path = of_icc_get(dev, "cpu-cfg");
72 if (!IS_ERR_OR_NULL(reg_bus_path))
73 msm_mdss->reg_bus_path = reg_bus_path;
74
75 return 0;
76}
77
78static void msm_mdss_irq(struct irq_desc *desc)
79{
80 struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc);
81 struct irq_chip *chip = irq_desc_get_chip(desc);
82 u32 interrupts;
83
84 chained_irq_enter(chip, desc);
85
86 interrupts = readl_relaxed(msm_mdss->mmio + HW_INTR_STATUS);
87
88 while (interrupts) {
89 irq_hw_number_t hwirq = fls(interrupts) - 1;
90 int rc;
91
92 rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain,
93 hwirq);
94 if (rc < 0) {
95 dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n",
96 hwirq, rc);
97 break;
98 }
99
100 interrupts &= ~(1 << hwirq);
101 }
102
103 chained_irq_exit(chip, desc);
104}
105
106static void msm_mdss_irq_mask(struct irq_data *irqd)
107{
108 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd);
109
110 /* memory barrier */
111 smp_mb__before_atomic();
112 clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);
113 /* memory barrier */
114 smp_mb__after_atomic();
115}
116
117static void msm_mdss_irq_unmask(struct irq_data *irqd)
118{
119 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd);
120
121 /* memory barrier */
122 smp_mb__before_atomic();
123 set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask);
124 /* memory barrier */
125 smp_mb__after_atomic();
126}
127
128static struct irq_chip msm_mdss_irq_chip = {
129 .name = "msm_mdss",
130 .irq_mask = msm_mdss_irq_mask,
131 .irq_unmask = msm_mdss_irq_unmask,
132};
133
134static struct lock_class_key msm_mdss_lock_key, msm_mdss_request_key;
135
136static int msm_mdss_irqdomain_map(struct irq_domain *domain,
137 unsigned int irq, irq_hw_number_t hwirq)
138{
139 struct msm_mdss *msm_mdss = domain->host_data;
140
141 irq_set_lockdep_class(irq, &msm_mdss_lock_key, &msm_mdss_request_key);
142 irq_set_chip_and_handler(irq, &msm_mdss_irq_chip, handle_level_irq);
143
144 return irq_set_chip_data(irq, msm_mdss);
145}
146
147static const struct irq_domain_ops msm_mdss_irqdomain_ops = {
148 .map = msm_mdss_irqdomain_map,
149 .xlate = irq_domain_xlate_onecell,
150};
151
152static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss)
153{
154 struct device *dev;
155 struct irq_domain *domain;
156
157 dev = msm_mdss->dev;
158
159 domain = irq_domain_add_linear(dev->of_node, 32,
160 &msm_mdss_irqdomain_ops, msm_mdss);
161 if (!domain) {
162 dev_err(dev, "failed to add irq_domain\n");
163 return -EINVAL;
164 }
165
166 msm_mdss->irq_controller.enabled_mask = 0;
167 msm_mdss->irq_controller.domain = domain;
168
169 return 0;
170}
171
172static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss)
173{
174 const struct msm_mdss_data *data = msm_mdss->mdss_data;
175
176 writel_relaxed(data->ubwc_static, msm_mdss->mmio + UBWC_STATIC);
177}
178
179static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss)
180{
181 const struct msm_mdss_data *data = msm_mdss->mdss_data;
182 u32 value = (data->ubwc_swizzle & 0x1) |
183 (data->highest_bank_bit & 0x3) << 4 |
184 (data->macrotile_mode & 0x1) << 12;
185
186 if (data->ubwc_enc_version == UBWC_3_0)
187 value |= BIT(10);
188
189 if (data->ubwc_enc_version == UBWC_1_0)
190 value |= BIT(8);
191
192 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
193}
194
195static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss)
196{
197 const struct msm_mdss_data *data = msm_mdss->mdss_data;
198 u32 value = (data->ubwc_swizzle & 0x7) |
199 (data->ubwc_static & 0x1) << 3 |
200 (data->highest_bank_bit & 0x7) << 4 |
201 (data->macrotile_mode & 0x1) << 12;
202
203 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC);
204
205 if (data->ubwc_enc_version == UBWC_3_0) {
206 writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2);
207 writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE);
208 } else {
209 if (data->ubwc_dec_version == UBWC_4_3)
210 writel_relaxed(3, msm_mdss->mmio + UBWC_CTRL_2);
211 else
212 writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2);
213 writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE);
214 }
215}
216
217#define MDSS_HW_MAJ_MIN GENMASK(31, 16)
218
219#define MDSS_HW_MSM8996 0x1007
220#define MDSS_HW_MSM8937 0x100e
221#define MDSS_HW_MSM8953 0x1010
222#define MDSS_HW_MSM8998 0x3000
223#define MDSS_HW_SDM660 0x3002
224#define MDSS_HW_SDM630 0x3003
225
226/*
227 * MDP5 platforms use generic qcom,mdp5 compat string, so we have to generate this data
228 */
229static const struct msm_mdss_data *msm_mdss_generate_mdp5_mdss_data(struct msm_mdss *mdss)
230{
231 struct msm_mdss_data *data;
232 u32 hw_rev;
233
234 data = devm_kzalloc(mdss->dev, sizeof(*data), GFP_KERNEL);
235 if (!data)
236 return NULL;
237
238 hw_rev = readl_relaxed(mdss->mmio + HW_REV);
239 hw_rev = FIELD_GET(MDSS_HW_MAJ_MIN, hw_rev);
240
241 if (hw_rev == MDSS_HW_MSM8996 ||
242 hw_rev == MDSS_HW_MSM8937 ||
243 hw_rev == MDSS_HW_MSM8953 ||
244 hw_rev == MDSS_HW_MSM8998 ||
245 hw_rev == MDSS_HW_SDM660 ||
246 hw_rev == MDSS_HW_SDM630) {
247 data->ubwc_dec_version = UBWC_1_0;
248 data->ubwc_enc_version = UBWC_1_0;
249 }
250
251 if (hw_rev == MDSS_HW_MSM8996 ||
252 hw_rev == MDSS_HW_MSM8998)
253 data->highest_bank_bit = 2;
254 else
255 data->highest_bank_bit = 1;
256
257 return data;
258}
259
260const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev)
261{
262 struct msm_mdss *mdss;
263
264 if (!dev)
265 return ERR_PTR(-EINVAL);
266
267 mdss = dev_get_drvdata(dev);
268
269 /*
270 * We could not do it at the probe time, since hw revision register was
271 * not readable. Fill data structure now for the MDP5 platforms.
272 */
273 if (!mdss->mdss_data && mdss->is_mdp5)
274 mdss->mdss_data = msm_mdss_generate_mdp5_mdss_data(mdss);
275
276 return mdss->mdss_data;
277}
278
279static int msm_mdss_enable(struct msm_mdss *msm_mdss)
280{
281 int ret, i;
282
283 /*
284 * Several components have AXI clocks that can only be turned on if
285 * the interconnect is enabled (non-zero bandwidth). Let's make sure
286 * that the interconnects are at least at a minimum amount.
287 */
288 for (i = 0; i < msm_mdss->num_mdp_paths; i++)
289 icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW));
290
291 if (msm_mdss->mdss_data && msm_mdss->mdss_data->reg_bus_bw)
292 icc_set_bw(msm_mdss->reg_bus_path, 0,
293 msm_mdss->mdss_data->reg_bus_bw);
294 else
295 icc_set_bw(msm_mdss->reg_bus_path, 0,
296 DEFAULT_REG_BW);
297
298 ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks);
299 if (ret) {
300 dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret);
301 return ret;
302 }
303
304 /*
305 * Register access requires MDSS_MDP_CLK, which is not enabled by the
306 * mdss on mdp5 hardware. Skip it for now.
307 */
308 if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data)
309 return 0;
310
311 /*
312 * ubwc config is part of the "mdss" region which is not accessible
313 * from the rest of the driver. hardcode known configurations here
314 *
315 * Decoder version can be read from the UBWC_DEC_HW_VERSION reg,
316 * UBWC_n and the rest of params comes from hw data.
317 */
318 switch (msm_mdss->mdss_data->ubwc_dec_version) {
319 case 0: /* no UBWC */
320 case UBWC_1_0:
321 /* do nothing */
322 break;
323 case UBWC_2_0:
324 msm_mdss_setup_ubwc_dec_20(msm_mdss);
325 break;
326 case UBWC_3_0:
327 msm_mdss_setup_ubwc_dec_30(msm_mdss);
328 break;
329 case UBWC_4_0:
330 case UBWC_4_3:
331 msm_mdss_setup_ubwc_dec_40(msm_mdss);
332 break;
333 default:
334 dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n",
335 msm_mdss->mdss_data->ubwc_dec_version);
336 dev_err(msm_mdss->dev, "HW_REV: 0x%x\n",
337 readl_relaxed(msm_mdss->mmio + HW_REV));
338 dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n",
339 readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION));
340 break;
341 }
342
343 return ret;
344}
345
346static int msm_mdss_disable(struct msm_mdss *msm_mdss)
347{
348 int i;
349
350 clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks);
351
352 for (i = 0; i < msm_mdss->num_mdp_paths; i++)
353 icc_set_bw(msm_mdss->mdp_path[i], 0, 0);
354
355 if (msm_mdss->reg_bus_path)
356 icc_set_bw(msm_mdss->reg_bus_path, 0, 0);
357
358 return 0;
359}
360
361static void msm_mdss_destroy(struct msm_mdss *msm_mdss)
362{
363 struct platform_device *pdev = to_platform_device(msm_mdss->dev);
364 int irq;
365
366 pm_runtime_suspend(msm_mdss->dev);
367 pm_runtime_disable(msm_mdss->dev);
368 irq_domain_remove(msm_mdss->irq_controller.domain);
369 msm_mdss->irq_controller.domain = NULL;
370 irq = platform_get_irq(pdev, 0);
371 irq_set_chained_handler_and_data(irq, NULL, NULL);
372}
373
374static int msm_mdss_reset(struct device *dev)
375{
376 struct reset_control *reset;
377
378 reset = reset_control_get_optional_exclusive(dev, NULL);
379 if (!reset) {
380 /* Optional reset not specified */
381 return 0;
382 } else if (IS_ERR(reset)) {
383 return dev_err_probe(dev, PTR_ERR(reset),
384 "failed to acquire mdss reset\n");
385 }
386
387 reset_control_assert(reset);
388 /*
389 * Tests indicate that reset has to be held for some period of time,
390 * make it one frame in a typical system
391 */
392 msleep(20);
393 reset_control_deassert(reset);
394
395 reset_control_put(reset);
396
397 return 0;
398}
399
400/*
401 * MDP5 MDSS uses at most three specified clocks.
402 */
403#define MDP5_MDSS_NUM_CLOCKS 3
404static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_data **clocks)
405{
406 struct clk_bulk_data *bulk;
407 int num_clocks = 0;
408 int ret;
409
410 if (!pdev)
411 return -EINVAL;
412
413 bulk = devm_kcalloc(&pdev->dev, MDP5_MDSS_NUM_CLOCKS, sizeof(struct clk_bulk_data), GFP_KERNEL);
414 if (!bulk)
415 return -ENOMEM;
416
417 bulk[num_clocks++].id = "iface";
418 bulk[num_clocks++].id = "bus";
419 bulk[num_clocks++].id = "vsync";
420
421 ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk);
422 if (ret)
423 return ret;
424
425 *clocks = bulk;
426
427 return num_clocks;
428}
429
430static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5)
431{
432 struct msm_mdss *msm_mdss;
433 int ret;
434 int irq;
435
436 ret = msm_mdss_reset(&pdev->dev);
437 if (ret)
438 return ERR_PTR(ret);
439
440 msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL);
441 if (!msm_mdss)
442 return ERR_PTR(-ENOMEM);
443
444 msm_mdss->mdss_data = of_device_get_match_data(&pdev->dev);
445
446 msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss");
447 if (IS_ERR(msm_mdss->mmio))
448 return ERR_CAST(msm_mdss->mmio);
449
450 dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio);
451
452 ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss);
453 if (ret)
454 return ERR_PTR(ret);
455
456 if (is_mdp5)
457 ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks);
458 else
459 ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks);
460 if (ret < 0) {
461 dev_err(&pdev->dev, "failed to parse clocks, ret=%d\n", ret);
462 return ERR_PTR(ret);
463 }
464 msm_mdss->num_clocks = ret;
465 msm_mdss->is_mdp5 = is_mdp5;
466
467 msm_mdss->dev = &pdev->dev;
468
469 irq = platform_get_irq(pdev, 0);
470 if (irq < 0)
471 return ERR_PTR(irq);
472
473 ret = _msm_mdss_irq_domain_add(msm_mdss);
474 if (ret)
475 return ERR_PTR(ret);
476
477 irq_set_chained_handler_and_data(irq, msm_mdss_irq,
478 msm_mdss);
479
480 pm_runtime_enable(&pdev->dev);
481
482 return msm_mdss;
483}
484
485static int __maybe_unused mdss_runtime_suspend(struct device *dev)
486{
487 struct msm_mdss *mdss = dev_get_drvdata(dev);
488
489 DBG("");
490
491 return msm_mdss_disable(mdss);
492}
493
494static int __maybe_unused mdss_runtime_resume(struct device *dev)
495{
496 struct msm_mdss *mdss = dev_get_drvdata(dev);
497
498 DBG("");
499
500 return msm_mdss_enable(mdss);
501}
502
503static int __maybe_unused mdss_pm_suspend(struct device *dev)
504{
505
506 if (pm_runtime_suspended(dev))
507 return 0;
508
509 return mdss_runtime_suspend(dev);
510}
511
512static int __maybe_unused mdss_pm_resume(struct device *dev)
513{
514 if (pm_runtime_suspended(dev))
515 return 0;
516
517 return mdss_runtime_resume(dev);
518}
519
520static const struct dev_pm_ops mdss_pm_ops = {
521 SET_SYSTEM_SLEEP_PM_OPS(mdss_pm_suspend, mdss_pm_resume)
522 SET_RUNTIME_PM_OPS(mdss_runtime_suspend, mdss_runtime_resume, NULL)
523};
524
525static int mdss_probe(struct platform_device *pdev)
526{
527 struct msm_mdss *mdss;
528 bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss");
529 struct device *dev = &pdev->dev;
530 int ret;
531
532 mdss = msm_mdss_init(pdev, is_mdp5);
533 if (IS_ERR(mdss))
534 return PTR_ERR(mdss);
535
536 platform_set_drvdata(pdev, mdss);
537
538 /*
539 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
540 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
541 * Populate the children devices, find the MDP5/DPU node, and then add
542 * the interfaces to our components list.
543 */
544 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
545 if (ret) {
546 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
547 msm_mdss_destroy(mdss);
548 return ret;
549 }
550
551 return 0;
552}
553
554static void mdss_remove(struct platform_device *pdev)
555{
556 struct msm_mdss *mdss = platform_get_drvdata(pdev);
557
558 of_platform_depopulate(&pdev->dev);
559
560 msm_mdss_destroy(mdss);
561}
562
563static const struct msm_mdss_data msm8998_data = {
564 .ubwc_enc_version = UBWC_1_0,
565 .ubwc_dec_version = UBWC_1_0,
566 .highest_bank_bit = 2,
567 .reg_bus_bw = 76800,
568};
569
570static const struct msm_mdss_data qcm2290_data = {
571 /* no UBWC */
572 .highest_bank_bit = 0x2,
573 .reg_bus_bw = 76800,
574};
575
576static const struct msm_mdss_data sc7180_data = {
577 .ubwc_enc_version = UBWC_2_0,
578 .ubwc_dec_version = UBWC_2_0,
579 .ubwc_static = 0x1e,
580 .highest_bank_bit = 0x3,
581 .reg_bus_bw = 76800,
582};
583
584static const struct msm_mdss_data sc7280_data = {
585 .ubwc_enc_version = UBWC_3_0,
586 .ubwc_dec_version = UBWC_4_0,
587 .ubwc_swizzle = 6,
588 .ubwc_static = 1,
589 .highest_bank_bit = 1,
590 .macrotile_mode = 1,
591 .reg_bus_bw = 74000,
592};
593
594static const struct msm_mdss_data sc8180x_data = {
595 .ubwc_enc_version = UBWC_3_0,
596 .ubwc_dec_version = UBWC_3_0,
597 .highest_bank_bit = 3,
598 .macrotile_mode = 1,
599 .reg_bus_bw = 76800,
600};
601
602static const struct msm_mdss_data sc8280xp_data = {
603 .ubwc_enc_version = UBWC_4_0,
604 .ubwc_dec_version = UBWC_4_0,
605 .ubwc_swizzle = 6,
606 .ubwc_static = 1,
607 .highest_bank_bit = 3,
608 .macrotile_mode = 1,
609 .reg_bus_bw = 76800,
610};
611
612static const struct msm_mdss_data sdm670_data = {
613 .ubwc_enc_version = UBWC_2_0,
614 .ubwc_dec_version = UBWC_2_0,
615 .highest_bank_bit = 1,
616 .reg_bus_bw = 76800,
617};
618
619static const struct msm_mdss_data sdm845_data = {
620 .ubwc_enc_version = UBWC_2_0,
621 .ubwc_dec_version = UBWC_2_0,
622 .highest_bank_bit = 2,
623 .reg_bus_bw = 76800,
624};
625
626static const struct msm_mdss_data sm6350_data = {
627 .ubwc_enc_version = UBWC_2_0,
628 .ubwc_dec_version = UBWC_2_0,
629 .ubwc_swizzle = 6,
630 .ubwc_static = 0x1e,
631 .highest_bank_bit = 1,
632 .reg_bus_bw = 76800,
633};
634
635static const struct msm_mdss_data sm8150_data = {
636 .ubwc_enc_version = UBWC_3_0,
637 .ubwc_dec_version = UBWC_3_0,
638 .highest_bank_bit = 2,
639 .reg_bus_bw = 76800,
640};
641
642static const struct msm_mdss_data sm6115_data = {
643 .ubwc_enc_version = UBWC_1_0,
644 .ubwc_dec_version = UBWC_2_0,
645 .ubwc_swizzle = 7,
646 .ubwc_static = 0x11f,
647 .highest_bank_bit = 0x1,
648 .reg_bus_bw = 76800,
649};
650
651static const struct msm_mdss_data sm6125_data = {
652 .ubwc_enc_version = UBWC_1_0,
653 .ubwc_dec_version = UBWC_3_0,
654 .ubwc_swizzle = 1,
655 .highest_bank_bit = 1,
656};
657
658static const struct msm_mdss_data sm8250_data = {
659 .ubwc_enc_version = UBWC_4_0,
660 .ubwc_dec_version = UBWC_4_0,
661 .ubwc_swizzle = 6,
662 .ubwc_static = 1,
663 /* TODO: highest_bank_bit = 2 for LP_DDR4 */
664 .highest_bank_bit = 3,
665 .macrotile_mode = 1,
666 .reg_bus_bw = 76800,
667};
668
669static const struct msm_mdss_data sm8350_data = {
670 .ubwc_enc_version = UBWC_4_0,
671 .ubwc_dec_version = UBWC_4_0,
672 .ubwc_swizzle = 6,
673 .ubwc_static = 1,
674 /* TODO: highest_bank_bit = 2 for LP_DDR4 */
675 .highest_bank_bit = 3,
676 .macrotile_mode = 1,
677 .reg_bus_bw = 74000,
678};
679
680static const struct msm_mdss_data sm8550_data = {
681 .ubwc_enc_version = UBWC_4_0,
682 .ubwc_dec_version = UBWC_4_3,
683 .ubwc_swizzle = 6,
684 .ubwc_static = 1,
685 /* TODO: highest_bank_bit = 2 for LP_DDR4 */
686 .highest_bank_bit = 3,
687 .macrotile_mode = 1,
688 .reg_bus_bw = 57000,
689};
690
691static const struct msm_mdss_data x1e80100_data = {
692 .ubwc_enc_version = UBWC_4_0,
693 .ubwc_dec_version = UBWC_4_3,
694 .ubwc_swizzle = 6,
695 .ubwc_static = 1,
696 /* TODO: highest_bank_bit = 2 for LP_DDR4 */
697 .highest_bank_bit = 3,
698 .macrotile_mode = 1,
699 /* TODO: Add reg_bus_bw with real value */
700};
701
702static const struct of_device_id mdss_dt_match[] = {
703 { .compatible = "qcom,mdss" },
704 { .compatible = "qcom,msm8998-mdss", .data = &msm8998_data },
705 { .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data },
706 { .compatible = "qcom,sdm670-mdss", .data = &sdm670_data },
707 { .compatible = "qcom,sdm845-mdss", .data = &sdm845_data },
708 { .compatible = "qcom,sc7180-mdss", .data = &sc7180_data },
709 { .compatible = "qcom,sc7280-mdss", .data = &sc7280_data },
710 { .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data },
711 { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data },
712 { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data },
713 { .compatible = "qcom,sm6125-mdss", .data = &sm6125_data },
714 { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data },
715 { .compatible = "qcom,sm6375-mdss", .data = &sm6350_data },
716 { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data },
717 { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data },
718 { .compatible = "qcom,sm8350-mdss", .data = &sm8350_data },
719 { .compatible = "qcom,sm8450-mdss", .data = &sm8350_data },
720 { .compatible = "qcom,sm8550-mdss", .data = &sm8550_data },
721 { .compatible = "qcom,sm8650-mdss", .data = &sm8550_data},
722 { .compatible = "qcom,x1e80100-mdss", .data = &x1e80100_data},
723 {}
724};
725MODULE_DEVICE_TABLE(of, mdss_dt_match);
726
727static struct platform_driver mdss_platform_driver = {
728 .probe = mdss_probe,
729 .remove_new = mdss_remove,
730 .driver = {
731 .name = "msm-mdss",
732 .of_match_table = mdss_dt_match,
733 .pm = &mdss_pm_ops,
734 },
735};
736
737void __init msm_mdss_register(void)
738{
739 platform_driver_register(&mdss_platform_driver);
740}
741
742void __exit msm_mdss_unregister(void)
743{
744 platform_driver_unregister(&mdss_platform_driver);
745}