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1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
28#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29
30/*
31 * The Bridge device's PCI config space has information about the
32 * fb aperture size and the amount of pre-reserved memory.
33 * This is all handled in the intel-gtt.ko module. i915.ko only
34 * cares about the vga bit for the vga rbiter.
35 */
36#define INTEL_GMCH_CTRL 0x52
37#define INTEL_GMCH_VGA_DISABLE (1 << 1)
38
39/* PCI config space */
40
41#define HPLLCC 0xc0 /* 855 only */
42#define GC_CLOCK_CONTROL_MASK (0xf << 0)
43#define GC_CLOCK_133_200 (0 << 0)
44#define GC_CLOCK_100_200 (1 << 0)
45#define GC_CLOCK_100_133 (2 << 0)
46#define GC_CLOCK_166_250 (3 << 0)
47#define GCFGC2 0xda
48#define GCFGC 0xf0 /* 915+ only */
49#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
50#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
51#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
52#define GC_DISPLAY_CLOCK_MASK (7 << 4)
53#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
54#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
55#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
56#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
57#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
58#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
59#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
60#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
61#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
62#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
63#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
64#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
65#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
66#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
67#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
68#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
69#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
70#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
71#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
72#define LBB 0xf4
73
74/* Graphics reset regs */
75#define I965_GDRST 0xc0 /* PCI config register */
76#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
77#define GRDOM_FULL (0<<2)
78#define GRDOM_RENDER (1<<2)
79#define GRDOM_MEDIA (3<<2)
80
81#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
82#define GEN6_MBC_SNPCR_SHIFT 21
83#define GEN6_MBC_SNPCR_MASK (3<<21)
84#define GEN6_MBC_SNPCR_MAX (0<<21)
85#define GEN6_MBC_SNPCR_MED (1<<21)
86#define GEN6_MBC_SNPCR_LOW (2<<21)
87#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
88
89#define GEN6_GDRST 0x941c
90#define GEN6_GRDOM_FULL (1 << 0)
91#define GEN6_GRDOM_RENDER (1 << 1)
92#define GEN6_GRDOM_MEDIA (1 << 2)
93#define GEN6_GRDOM_BLT (1 << 3)
94
95/* VGA stuff */
96
97#define VGA_ST01_MDA 0x3ba
98#define VGA_ST01_CGA 0x3da
99
100#define VGA_MSR_WRITE 0x3c2
101#define VGA_MSR_READ 0x3cc
102#define VGA_MSR_MEM_EN (1<<1)
103#define VGA_MSR_CGA_MODE (1<<0)
104
105#define VGA_SR_INDEX 0x3c4
106#define VGA_SR_DATA 0x3c5
107
108#define VGA_AR_INDEX 0x3c0
109#define VGA_AR_VID_EN (1<<5)
110#define VGA_AR_DATA_WRITE 0x3c0
111#define VGA_AR_DATA_READ 0x3c1
112
113#define VGA_GR_INDEX 0x3ce
114#define VGA_GR_DATA 0x3cf
115/* GR05 */
116#define VGA_GR_MEM_READ_MODE_SHIFT 3
117#define VGA_GR_MEM_READ_MODE_PLANE 1
118/* GR06 */
119#define VGA_GR_MEM_MODE_MASK 0xc
120#define VGA_GR_MEM_MODE_SHIFT 2
121#define VGA_GR_MEM_A0000_AFFFF 0
122#define VGA_GR_MEM_A0000_BFFFF 1
123#define VGA_GR_MEM_B0000_B7FFF 2
124#define VGA_GR_MEM_B0000_BFFFF 3
125
126#define VGA_DACMASK 0x3c6
127#define VGA_DACRX 0x3c7
128#define VGA_DACWX 0x3c8
129#define VGA_DACDATA 0x3c9
130
131#define VGA_CR_INDEX_MDA 0x3b4
132#define VGA_CR_DATA_MDA 0x3b5
133#define VGA_CR_INDEX_CGA 0x3d4
134#define VGA_CR_DATA_CGA 0x3d5
135
136/*
137 * Memory interface instructions used by the kernel
138 */
139#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
140
141#define MI_NOOP MI_INSTR(0, 0)
142#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
143#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
144#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
145#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
146#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
147#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
148#define MI_FLUSH MI_INSTR(0x04, 0)
149#define MI_READ_FLUSH (1 << 0)
150#define MI_EXE_FLUSH (1 << 1)
151#define MI_NO_WRITE_FLUSH (1 << 2)
152#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
153#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
154#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
155#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
156#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
157#define MI_SUSPEND_FLUSH_EN (1<<0)
158#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
159#define MI_OVERLAY_FLIP MI_INSTR(0x11,0)
160#define MI_OVERLAY_CONTINUE (0x0<<21)
161#define MI_OVERLAY_ON (0x1<<21)
162#define MI_OVERLAY_OFF (0x2<<21)
163#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
164#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
165#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
166#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
167#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
168#define MI_MM_SPACE_GTT (1<<8)
169#define MI_MM_SPACE_PHYSICAL (0<<8)
170#define MI_SAVE_EXT_STATE_EN (1<<3)
171#define MI_RESTORE_EXT_STATE_EN (1<<2)
172#define MI_FORCE_RESTORE (1<<1)
173#define MI_RESTORE_INHIBIT (1<<0)
174#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
175#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
176#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
177#define MI_STORE_DWORD_INDEX_SHIFT 2
178/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
179 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
180 * simply ignores the register load under certain conditions.
181 * - One can actually load arbitrary many arbitrary registers: Simply issue x
182 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
183 */
184#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
185#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
186#define MI_INVALIDATE_TLB (1<<18)
187#define MI_INVALIDATE_BSD (1<<7)
188#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
189#define MI_BATCH_NON_SECURE (1)
190#define MI_BATCH_NON_SECURE_I965 (1<<8)
191#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
192#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
193#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
194#define MI_SEMAPHORE_UPDATE (1<<21)
195#define MI_SEMAPHORE_COMPARE (1<<20)
196#define MI_SEMAPHORE_REGISTER (1<<18)
197/*
198 * 3D instructions used by the kernel
199 */
200#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
201
202#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
203#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
204#define SC_UPDATE_SCISSOR (0x1<<1)
205#define SC_ENABLE_MASK (0x1<<0)
206#define SC_ENABLE (0x1<<0)
207#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
208#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
209#define SCI_YMIN_MASK (0xffff<<16)
210#define SCI_XMIN_MASK (0xffff<<0)
211#define SCI_YMAX_MASK (0xffff<<16)
212#define SCI_XMAX_MASK (0xffff<<0)
213#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
214#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
215#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
216#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
217#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
218#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
219#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
220#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
221#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
222#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
223#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
224#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
225#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
226#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
227#define BLT_DEPTH_8 (0<<24)
228#define BLT_DEPTH_16_565 (1<<24)
229#define BLT_DEPTH_16_1555 (2<<24)
230#define BLT_DEPTH_32 (3<<24)
231#define BLT_ROP_GXCOPY (0xcc<<16)
232#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
233#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
234#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
235#define ASYNC_FLIP (1<<22)
236#define DISPLAY_PLANE_A (0<<20)
237#define DISPLAY_PLANE_B (1<<20)
238#define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
239#define PIPE_CONTROL_QW_WRITE (1<<14)
240#define PIPE_CONTROL_DEPTH_STALL (1<<13)
241#define PIPE_CONTROL_WC_FLUSH (1<<12)
242#define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
243#define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
244#define PIPE_CONTROL_ISP_DIS (1<<9)
245#define PIPE_CONTROL_NOTIFY (1<<8)
246#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
247#define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */
248
249
250/*
251 * Reset registers
252 */
253#define DEBUG_RESET_I830 0x6070
254#define DEBUG_RESET_FULL (1<<7)
255#define DEBUG_RESET_RENDER (1<<8)
256#define DEBUG_RESET_DISPLAY (1<<9)
257
258
259/*
260 * Fence registers
261 */
262#define FENCE_REG_830_0 0x2000
263#define FENCE_REG_945_8 0x3000
264#define I830_FENCE_START_MASK 0x07f80000
265#define I830_FENCE_TILING_Y_SHIFT 12
266#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
267#define I830_FENCE_PITCH_SHIFT 4
268#define I830_FENCE_REG_VALID (1<<0)
269#define I915_FENCE_MAX_PITCH_VAL 4
270#define I830_FENCE_MAX_PITCH_VAL 6
271#define I830_FENCE_MAX_SIZE_VAL (1<<8)
272
273#define I915_FENCE_START_MASK 0x0ff00000
274#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
275
276#define FENCE_REG_965_0 0x03000
277#define I965_FENCE_PITCH_SHIFT 2
278#define I965_FENCE_TILING_Y_SHIFT 1
279#define I965_FENCE_REG_VALID (1<<0)
280#define I965_FENCE_MAX_PITCH_VAL 0x0400
281
282#define FENCE_REG_SANDYBRIDGE_0 0x100000
283#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
284
285/*
286 * Instruction and interrupt control regs
287 */
288#define PGTBL_ER 0x02024
289#define RENDER_RING_BASE 0x02000
290#define BSD_RING_BASE 0x04000
291#define GEN6_BSD_RING_BASE 0x12000
292#define BLT_RING_BASE 0x22000
293#define RING_TAIL(base) ((base)+0x30)
294#define RING_HEAD(base) ((base)+0x34)
295#define RING_START(base) ((base)+0x38)
296#define RING_CTL(base) ((base)+0x3c)
297#define RING_SYNC_0(base) ((base)+0x40)
298#define RING_SYNC_1(base) ((base)+0x44)
299#define RING_MAX_IDLE(base) ((base)+0x54)
300#define RING_HWS_PGA(base) ((base)+0x80)
301#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
302#define RENDER_HWS_PGA_GEN7 (0x04080)
303#define BSD_HWS_PGA_GEN7 (0x04180)
304#define BLT_HWS_PGA_GEN7 (0x04280)
305#define RING_ACTHD(base) ((base)+0x74)
306#define RING_NOPID(base) ((base)+0x94)
307#define RING_IMR(base) ((base)+0xa8)
308#define TAIL_ADDR 0x001FFFF8
309#define HEAD_WRAP_COUNT 0xFFE00000
310#define HEAD_WRAP_ONE 0x00200000
311#define HEAD_ADDR 0x001FFFFC
312#define RING_NR_PAGES 0x001FF000
313#define RING_REPORT_MASK 0x00000006
314#define RING_REPORT_64K 0x00000002
315#define RING_REPORT_128K 0x00000004
316#define RING_NO_REPORT 0x00000000
317#define RING_VALID_MASK 0x00000001
318#define RING_VALID 0x00000001
319#define RING_INVALID 0x00000000
320#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
321#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
322#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
323#if 0
324#define PRB0_TAIL 0x02030
325#define PRB0_HEAD 0x02034
326#define PRB0_START 0x02038
327#define PRB0_CTL 0x0203c
328#define PRB1_TAIL 0x02040 /* 915+ only */
329#define PRB1_HEAD 0x02044 /* 915+ only */
330#define PRB1_START 0x02048 /* 915+ only */
331#define PRB1_CTL 0x0204c /* 915+ only */
332#endif
333#define IPEIR_I965 0x02064
334#define IPEHR_I965 0x02068
335#define INSTDONE_I965 0x0206c
336#define INSTPS 0x02070 /* 965+ only */
337#define INSTDONE1 0x0207c /* 965+ only */
338#define ACTHD_I965 0x02074
339#define HWS_PGA 0x02080
340#define HWS_ADDRESS_MASK 0xfffff000
341#define HWS_START_ADDRESS_SHIFT 4
342#define PWRCTXA 0x2088 /* 965GM+ only */
343#define PWRCTX_EN (1<<0)
344#define IPEIR 0x02088
345#define IPEHR 0x0208c
346#define INSTDONE 0x02090
347#define NOPID 0x02094
348#define HWSTAM 0x02098
349#define VCS_INSTDONE 0x1206C
350#define VCS_IPEIR 0x12064
351#define VCS_IPEHR 0x12068
352#define VCS_ACTHD 0x12074
353#define BCS_INSTDONE 0x2206C
354#define BCS_IPEIR 0x22064
355#define BCS_IPEHR 0x22068
356#define BCS_ACTHD 0x22074
357
358#define ERROR_GEN6 0x040a0
359
360/* GM45+ chicken bits -- debug workaround bits that may be required
361 * for various sorts of correct behavior. The top 16 bits of each are
362 * the enables for writing to the corresponding low bit.
363 */
364#define _3D_CHICKEN 0x02084
365#define _3D_CHICKEN2 0x0208c
366/* Disables pipelining of read flushes past the SF-WIZ interface.
367 * Required on all Ironlake steppings according to the B-Spec, but the
368 * particular danger of not doing so is not specified.
369 */
370# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
371#define _3D_CHICKEN3 0x02090
372
373#define MI_MODE 0x0209c
374# define VS_TIMER_DISPATCH (1 << 6)
375# define MI_FLUSH_ENABLE (1 << 11)
376
377#define GFX_MODE 0x02520
378#define GFX_MODE_GEN7 0x0229c
379#define GFX_RUN_LIST_ENABLE (1<<15)
380#define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
381#define GFX_SURFACE_FAULT_ENABLE (1<<12)
382#define GFX_REPLAY_MODE (1<<11)
383#define GFX_PSMI_GRANULARITY (1<<10)
384#define GFX_PPGTT_ENABLE (1<<9)
385
386#define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit))
387#define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0))
388
389#define SCPD0 0x0209c /* 915+ only */
390#define IER 0x020a0
391#define IIR 0x020a4
392#define IMR 0x020a8
393#define ISR 0x020ac
394#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
395#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
396#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
397#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
398#define I915_HWB_OOM_INTERRUPT (1<<13)
399#define I915_SYNC_STATUS_INTERRUPT (1<<12)
400#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
401#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
402#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
403#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
404#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
405#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
406#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
407#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
408#define I915_DEBUG_INTERRUPT (1<<2)
409#define I915_USER_INTERRUPT (1<<1)
410#define I915_ASLE_INTERRUPT (1<<0)
411#define I915_BSD_USER_INTERRUPT (1<<25)
412#define EIR 0x020b0
413#define EMR 0x020b4
414#define ESR 0x020b8
415#define GM45_ERROR_PAGE_TABLE (1<<5)
416#define GM45_ERROR_MEM_PRIV (1<<4)
417#define I915_ERROR_PAGE_TABLE (1<<4)
418#define GM45_ERROR_CP_PRIV (1<<3)
419#define I915_ERROR_MEMORY_REFRESH (1<<1)
420#define I915_ERROR_INSTRUCTION (1<<0)
421#define INSTPM 0x020c0
422#define INSTPM_SELF_EN (1<<12) /* 915GM only */
423#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
424 will not assert AGPBUSY# and will only
425 be delivered when out of C3. */
426#define ACTHD 0x020c8
427#define FW_BLC 0x020d8
428#define FW_BLC2 0x020dc
429#define FW_BLC_SELF 0x020e0 /* 915+ only */
430#define FW_BLC_SELF_EN_MASK (1<<31)
431#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
432#define FW_BLC_SELF_EN (1<<15) /* 945 only */
433#define MM_BURST_LENGTH 0x00700000
434#define MM_FIFO_WATERMARK 0x0001F000
435#define LM_BURST_LENGTH 0x00000700
436#define LM_FIFO_WATERMARK 0x0000001F
437#define MI_ARB_STATE 0x020e4 /* 915+ only */
438#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
439
440/* Make render/texture TLB fetches lower priorty than associated data
441 * fetches. This is not turned on by default
442 */
443#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
444
445/* Isoch request wait on GTT enable (Display A/B/C streams).
446 * Make isoch requests stall on the TLB update. May cause
447 * display underruns (test mode only)
448 */
449#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
450
451/* Block grant count for isoch requests when block count is
452 * set to a finite value.
453 */
454#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
455#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
456#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
457#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
458#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
459
460/* Enable render writes to complete in C2/C3/C4 power states.
461 * If this isn't enabled, render writes are prevented in low
462 * power states. That seems bad to me.
463 */
464#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
465
466/* This acknowledges an async flip immediately instead
467 * of waiting for 2TLB fetches.
468 */
469#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
470
471/* Enables non-sequential data reads through arbiter
472 */
473#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
474
475/* Disable FSB snooping of cacheable write cycles from binner/render
476 * command stream
477 */
478#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
479
480/* Arbiter time slice for non-isoch streams */
481#define MI_ARB_TIME_SLICE_MASK (7 << 5)
482#define MI_ARB_TIME_SLICE_1 (0 << 5)
483#define MI_ARB_TIME_SLICE_2 (1 << 5)
484#define MI_ARB_TIME_SLICE_4 (2 << 5)
485#define MI_ARB_TIME_SLICE_6 (3 << 5)
486#define MI_ARB_TIME_SLICE_8 (4 << 5)
487#define MI_ARB_TIME_SLICE_10 (5 << 5)
488#define MI_ARB_TIME_SLICE_14 (6 << 5)
489#define MI_ARB_TIME_SLICE_16 (7 << 5)
490
491/* Low priority grace period page size */
492#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
493#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
494
495/* Disable display A/B trickle feed */
496#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
497
498/* Set display plane priority */
499#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
500#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
501
502#define CACHE_MODE_0 0x02120 /* 915+ only */
503#define CM0_MASK_SHIFT 16
504#define CM0_IZ_OPT_DISABLE (1<<6)
505#define CM0_ZR_OPT_DISABLE (1<<5)
506#define CM0_DEPTH_EVICT_DISABLE (1<<4)
507#define CM0_COLOR_EVICT_DISABLE (1<<3)
508#define CM0_DEPTH_WRITE_DISABLE (1<<1)
509#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
510#define BB_ADDR 0x02140 /* 8 bytes */
511#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
512#define ECOSKPD 0x021d0
513#define ECO_GATING_CX_ONLY (1<<3)
514#define ECO_FLIP_DONE (1<<0)
515
516/* GEN6 interrupt control */
517#define GEN6_RENDER_HWSTAM 0x2098
518#define GEN6_RENDER_IMR 0x20a8
519#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
520#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
521#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
522#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
523#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
524#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
525#define GEN6_RENDER_SYNC_STATUS (1 << 2)
526#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
527#define GEN6_RENDER_USER_INTERRUPT (1 << 0)
528
529#define GEN6_BLITTER_HWSTAM 0x22098
530#define GEN6_BLITTER_IMR 0x220a8
531#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
532#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
533#define GEN6_BLITTER_SYNC_STATUS (1 << 24)
534#define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
535
536#define GEN6_BLITTER_ECOSKPD 0x221d0
537#define GEN6_BLITTER_LOCK_SHIFT 16
538#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
539
540#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
541#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16)
542#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0)
543#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0
544#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3)
545
546#define GEN6_BSD_HWSTAM 0x12098
547#define GEN6_BSD_IMR 0x120a8
548#define GEN6_BSD_USER_INTERRUPT (1 << 12)
549
550#define GEN6_BSD_RNCID 0x12198
551
552/*
553 * Framebuffer compression (915+ only)
554 */
555
556#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
557#define FBC_LL_BASE 0x03204 /* 4k page aligned */
558#define FBC_CONTROL 0x03208
559#define FBC_CTL_EN (1<<31)
560#define FBC_CTL_PERIODIC (1<<30)
561#define FBC_CTL_INTERVAL_SHIFT (16)
562#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
563#define FBC_CTL_C3_IDLE (1<<13)
564#define FBC_CTL_STRIDE_SHIFT (5)
565#define FBC_CTL_FENCENO (1<<0)
566#define FBC_COMMAND 0x0320c
567#define FBC_CMD_COMPRESS (1<<0)
568#define FBC_STATUS 0x03210
569#define FBC_STAT_COMPRESSING (1<<31)
570#define FBC_STAT_COMPRESSED (1<<30)
571#define FBC_STAT_MODIFIED (1<<29)
572#define FBC_STAT_CURRENT_LINE (1<<0)
573#define FBC_CONTROL2 0x03214
574#define FBC_CTL_FENCE_DBL (0<<4)
575#define FBC_CTL_IDLE_IMM (0<<2)
576#define FBC_CTL_IDLE_FULL (1<<2)
577#define FBC_CTL_IDLE_LINE (2<<2)
578#define FBC_CTL_IDLE_DEBUG (3<<2)
579#define FBC_CTL_CPU_FENCE (1<<1)
580#define FBC_CTL_PLANEA (0<<0)
581#define FBC_CTL_PLANEB (1<<0)
582#define FBC_FENCE_OFF 0x0321b
583#define FBC_TAG 0x03300
584
585#define FBC_LL_SIZE (1536)
586
587/* Framebuffer compression for GM45+ */
588#define DPFC_CB_BASE 0x3200
589#define DPFC_CONTROL 0x3208
590#define DPFC_CTL_EN (1<<31)
591#define DPFC_CTL_PLANEA (0<<30)
592#define DPFC_CTL_PLANEB (1<<30)
593#define DPFC_CTL_FENCE_EN (1<<29)
594#define DPFC_CTL_PERSISTENT_MODE (1<<25)
595#define DPFC_SR_EN (1<<10)
596#define DPFC_CTL_LIMIT_1X (0<<6)
597#define DPFC_CTL_LIMIT_2X (1<<6)
598#define DPFC_CTL_LIMIT_4X (2<<6)
599#define DPFC_RECOMP_CTL 0x320c
600#define DPFC_RECOMP_STALL_EN (1<<27)
601#define DPFC_RECOMP_STALL_WM_SHIFT (16)
602#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
603#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
604#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
605#define DPFC_STATUS 0x3210
606#define DPFC_INVAL_SEG_SHIFT (16)
607#define DPFC_INVAL_SEG_MASK (0x07ff0000)
608#define DPFC_COMP_SEG_SHIFT (0)
609#define DPFC_COMP_SEG_MASK (0x000003ff)
610#define DPFC_STATUS2 0x3214
611#define DPFC_FENCE_YOFF 0x3218
612#define DPFC_CHICKEN 0x3224
613#define DPFC_HT_MODIFY (1<<31)
614
615/* Framebuffer compression for Ironlake */
616#define ILK_DPFC_CB_BASE 0x43200
617#define ILK_DPFC_CONTROL 0x43208
618/* The bit 28-8 is reserved */
619#define DPFC_RESERVED (0x1FFFFF00)
620#define ILK_DPFC_RECOMP_CTL 0x4320c
621#define ILK_DPFC_STATUS 0x43210
622#define ILK_DPFC_FENCE_YOFF 0x43218
623#define ILK_DPFC_CHICKEN 0x43224
624#define ILK_FBC_RT_BASE 0x2128
625#define ILK_FBC_RT_VALID (1<<0)
626
627#define ILK_DISPLAY_CHICKEN1 0x42000
628#define ILK_FBCQ_DIS (1<<22)
629#define ILK_PABSTRETCH_DIS (1<<21)
630
631
632/*
633 * Framebuffer compression for Sandybridge
634 *
635 * The following two registers are of type GTTMMADR
636 */
637#define SNB_DPFC_CTL_SA 0x100100
638#define SNB_CPU_FENCE_ENABLE (1<<29)
639#define DPFC_CPU_FENCE_OFFSET 0x100104
640
641
642/*
643 * GPIO regs
644 */
645#define GPIOA 0x5010
646#define GPIOB 0x5014
647#define GPIOC 0x5018
648#define GPIOD 0x501c
649#define GPIOE 0x5020
650#define GPIOF 0x5024
651#define GPIOG 0x5028
652#define GPIOH 0x502c
653# define GPIO_CLOCK_DIR_MASK (1 << 0)
654# define GPIO_CLOCK_DIR_IN (0 << 1)
655# define GPIO_CLOCK_DIR_OUT (1 << 1)
656# define GPIO_CLOCK_VAL_MASK (1 << 2)
657# define GPIO_CLOCK_VAL_OUT (1 << 3)
658# define GPIO_CLOCK_VAL_IN (1 << 4)
659# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
660# define GPIO_DATA_DIR_MASK (1 << 8)
661# define GPIO_DATA_DIR_IN (0 << 9)
662# define GPIO_DATA_DIR_OUT (1 << 9)
663# define GPIO_DATA_VAL_MASK (1 << 10)
664# define GPIO_DATA_VAL_OUT (1 << 11)
665# define GPIO_DATA_VAL_IN (1 << 12)
666# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
667
668#define GMBUS0 0x5100 /* clock/port select */
669#define GMBUS_RATE_100KHZ (0<<8)
670#define GMBUS_RATE_50KHZ (1<<8)
671#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
672#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
673#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
674#define GMBUS_PORT_DISABLED 0
675#define GMBUS_PORT_SSC 1
676#define GMBUS_PORT_VGADDC 2
677#define GMBUS_PORT_PANEL 3
678#define GMBUS_PORT_DPC 4 /* HDMIC */
679#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
680 /* 6 reserved */
681#define GMBUS_PORT_DPD 7 /* HDMID */
682#define GMBUS_NUM_PORTS 8
683#define GMBUS1 0x5104 /* command/status */
684#define GMBUS_SW_CLR_INT (1<<31)
685#define GMBUS_SW_RDY (1<<30)
686#define GMBUS_ENT (1<<29) /* enable timeout */
687#define GMBUS_CYCLE_NONE (0<<25)
688#define GMBUS_CYCLE_WAIT (1<<25)
689#define GMBUS_CYCLE_INDEX (2<<25)
690#define GMBUS_CYCLE_STOP (4<<25)
691#define GMBUS_BYTE_COUNT_SHIFT 16
692#define GMBUS_SLAVE_INDEX_SHIFT 8
693#define GMBUS_SLAVE_ADDR_SHIFT 1
694#define GMBUS_SLAVE_READ (1<<0)
695#define GMBUS_SLAVE_WRITE (0<<0)
696#define GMBUS2 0x5108 /* status */
697#define GMBUS_INUSE (1<<15)
698#define GMBUS_HW_WAIT_PHASE (1<<14)
699#define GMBUS_STALL_TIMEOUT (1<<13)
700#define GMBUS_INT (1<<12)
701#define GMBUS_HW_RDY (1<<11)
702#define GMBUS_SATOER (1<<10)
703#define GMBUS_ACTIVE (1<<9)
704#define GMBUS3 0x510c /* data buffer bytes 3-0 */
705#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
706#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
707#define GMBUS_NAK_EN (1<<3)
708#define GMBUS_IDLE_EN (1<<2)
709#define GMBUS_HW_WAIT_EN (1<<1)
710#define GMBUS_HW_RDY_EN (1<<0)
711#define GMBUS5 0x5120 /* byte index */
712#define GMBUS_2BYTE_INDEX_EN (1<<31)
713
714/*
715 * Clock control & power management
716 */
717
718#define VGA0 0x6000
719#define VGA1 0x6004
720#define VGA_PD 0x6010
721#define VGA0_PD_P2_DIV_4 (1 << 7)
722#define VGA0_PD_P1_DIV_2 (1 << 5)
723#define VGA0_PD_P1_SHIFT 0
724#define VGA0_PD_P1_MASK (0x1f << 0)
725#define VGA1_PD_P2_DIV_4 (1 << 15)
726#define VGA1_PD_P1_DIV_2 (1 << 13)
727#define VGA1_PD_P1_SHIFT 8
728#define VGA1_PD_P1_MASK (0x1f << 8)
729#define _DPLL_A 0x06014
730#define _DPLL_B 0x06018
731#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
732#define DPLL_VCO_ENABLE (1 << 31)
733#define DPLL_DVO_HIGH_SPEED (1 << 30)
734#define DPLL_SYNCLOCK_ENABLE (1 << 29)
735#define DPLL_VGA_MODE_DIS (1 << 28)
736#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
737#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
738#define DPLL_MODE_MASK (3 << 26)
739#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
740#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
741#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
742#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
743#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
744#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
745#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
746
747#define SRX_INDEX 0x3c4
748#define SRX_DATA 0x3c5
749#define SR01 1
750#define SR01_SCREEN_OFF (1<<5)
751
752#define PPCR 0x61204
753#define PPCR_ON (1<<0)
754
755#define DVOB 0x61140
756#define DVOB_ON (1<<31)
757#define DVOC 0x61160
758#define DVOC_ON (1<<31)
759#define LVDS 0x61180
760#define LVDS_ON (1<<31)
761
762/* Scratch pad debug 0 reg:
763 */
764#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
765/*
766 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
767 * this field (only one bit may be set).
768 */
769#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
770#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
771#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
772/* i830, required in DVO non-gang */
773#define PLL_P2_DIVIDE_BY_4 (1 << 23)
774#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
775#define PLL_REF_INPUT_DREFCLK (0 << 13)
776#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
777#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
778#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
779#define PLL_REF_INPUT_MASK (3 << 13)
780#define PLL_LOAD_PULSE_PHASE_SHIFT 9
781/* Ironlake */
782# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
783# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
784# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
785# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
786# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
787
788/*
789 * Parallel to Serial Load Pulse phase selection.
790 * Selects the phase for the 10X DPLL clock for the PCIe
791 * digital display port. The range is 4 to 13; 10 or more
792 * is just a flip delay. The default is 6
793 */
794#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
795#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
796/*
797 * SDVO multiplier for 945G/GM. Not used on 965.
798 */
799#define SDVO_MULTIPLIER_MASK 0x000000ff
800#define SDVO_MULTIPLIER_SHIFT_HIRES 4
801#define SDVO_MULTIPLIER_SHIFT_VGA 0
802#define _DPLL_A_MD 0x0601c /* 965+ only */
803/*
804 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
805 *
806 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
807 */
808#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
809#define DPLL_MD_UDI_DIVIDER_SHIFT 24
810/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
811#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
812#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
813/*
814 * SDVO/UDI pixel multiplier.
815 *
816 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
817 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
818 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
819 * dummy bytes in the datastream at an increased clock rate, with both sides of
820 * the link knowing how many bytes are fill.
821 *
822 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
823 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
824 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
825 * through an SDVO command.
826 *
827 * This register field has values of multiplication factor minus 1, with
828 * a maximum multiplier of 5 for SDVO.
829 */
830#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
831#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
832/*
833 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
834 * This best be set to the default value (3) or the CRT won't work. No,
835 * I don't entirely understand what this does...
836 */
837#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
838#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
839#define _DPLL_B_MD 0x06020 /* 965+ only */
840#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
841#define _FPA0 0x06040
842#define _FPA1 0x06044
843#define _FPB0 0x06048
844#define _FPB1 0x0604c
845#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
846#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
847#define FP_N_DIV_MASK 0x003f0000
848#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
849#define FP_N_DIV_SHIFT 16
850#define FP_M1_DIV_MASK 0x00003f00
851#define FP_M1_DIV_SHIFT 8
852#define FP_M2_DIV_MASK 0x0000003f
853#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
854#define FP_M2_DIV_SHIFT 0
855#define DPLL_TEST 0x606c
856#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
857#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
858#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
859#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
860#define DPLLB_TEST_N_BYPASS (1 << 19)
861#define DPLLB_TEST_M_BYPASS (1 << 18)
862#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
863#define DPLLA_TEST_N_BYPASS (1 << 3)
864#define DPLLA_TEST_M_BYPASS (1 << 2)
865#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
866#define D_STATE 0x6104
867#define DSTATE_GFX_RESET_I830 (1<<6)
868#define DSTATE_PLL_D3_OFF (1<<3)
869#define DSTATE_GFX_CLOCK_GATING (1<<1)
870#define DSTATE_DOT_CLOCK_GATING (1<<0)
871#define DSPCLK_GATE_D 0x6200
872# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
873# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
874# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
875# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
876# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
877# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
878# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
879# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
880# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
881# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
882# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
883# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
884# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
885# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
886# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
887# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
888# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
889# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
890# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
891# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
892# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
893# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
894# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
895# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
896# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
897# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
898# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
899# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
900/**
901 * This bit must be set on the 830 to prevent hangs when turning off the
902 * overlay scaler.
903 */
904# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
905# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
906# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
907# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
908# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
909
910#define RENCLK_GATE_D1 0x6204
911# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
912# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
913# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
914# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
915# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
916# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
917# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
918# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
919# define MAG_CLOCK_GATE_DISABLE (1 << 5)
920/** This bit must be unset on 855,865 */
921# define MECI_CLOCK_GATE_DISABLE (1 << 4)
922# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
923# define MEC_CLOCK_GATE_DISABLE (1 << 2)
924# define MECO_CLOCK_GATE_DISABLE (1 << 1)
925/** This bit must be set on 855,865. */
926# define SV_CLOCK_GATE_DISABLE (1 << 0)
927# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
928# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
929# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
930# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
931# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
932# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
933# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
934# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
935# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
936# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
937# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
938# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
939# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
940# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
941# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
942# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
943# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
944
945# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
946/** This bit must always be set on 965G/965GM */
947# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
948# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
949# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
950# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
951# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
952# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
953/** This bit must always be set on 965G */
954# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
955# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
956# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
957# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
958# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
959# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
960# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
961# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
962# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
963# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
964# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
965# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
966# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
967# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
968# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
969# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
970# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
971# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
972# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
973
974#define RENCLK_GATE_D2 0x6208
975#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
976#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
977#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
978#define RAMCLK_GATE_D 0x6210 /* CRL only */
979#define DEUC 0x6214 /* CRL only */
980
981/*
982 * Palette regs
983 */
984
985#define _PALETTE_A 0x0a000
986#define _PALETTE_B 0x0a800
987#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
988
989/* MCH MMIO space */
990
991/*
992 * MCHBAR mirror.
993 *
994 * This mirrors the MCHBAR MMIO space whose location is determined by
995 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
996 * every way. It is not accessible from the CP register read instructions.
997 *
998 */
999#define MCHBAR_MIRROR_BASE 0x10000
1000
1001#define MCHBAR_MIRROR_BASE_SNB 0x140000
1002
1003/** 915-945 and GM965 MCH register controlling DRAM channel access */
1004#define DCC 0x10200
1005#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1006#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1007#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1008#define DCC_ADDRESSING_MODE_MASK (3 << 0)
1009#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
1010#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
1011
1012/** Pineview MCH register contains DDR3 setting */
1013#define CSHRDDR3CTL 0x101a8
1014#define CSHRDDR3CTL_DDR3 (1 << 2)
1015
1016/** 965 MCH register controlling DRAM channel configuration */
1017#define C0DRB3 0x10206
1018#define C1DRB3 0x10606
1019
1020/* Clocking configuration register */
1021#define CLKCFG 0x10c00
1022#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
1023#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
1024#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
1025#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
1026#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
1027#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
1028/* Note, below two are guess */
1029#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
1030#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
1031#define CLKCFG_FSB_MASK (7 << 0)
1032#define CLKCFG_MEM_533 (1 << 4)
1033#define CLKCFG_MEM_667 (2 << 4)
1034#define CLKCFG_MEM_800 (3 << 4)
1035#define CLKCFG_MEM_MASK (7 << 4)
1036
1037#define TSC1 0x11001
1038#define TSE (1<<0)
1039#define TR1 0x11006
1040#define TSFS 0x11020
1041#define TSFS_SLOPE_MASK 0x0000ff00
1042#define TSFS_SLOPE_SHIFT 8
1043#define TSFS_INTR_MASK 0x000000ff
1044
1045#define CRSTANDVID 0x11100
1046#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1047#define PXVFREQ_PX_MASK 0x7f000000
1048#define PXVFREQ_PX_SHIFT 24
1049#define VIDFREQ_BASE 0x11110
1050#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1051#define VIDFREQ2 0x11114
1052#define VIDFREQ3 0x11118
1053#define VIDFREQ4 0x1111c
1054#define VIDFREQ_P0_MASK 0x1f000000
1055#define VIDFREQ_P0_SHIFT 24
1056#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1057#define VIDFREQ_P0_CSCLK_SHIFT 20
1058#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1059#define VIDFREQ_P0_CRCLK_SHIFT 16
1060#define VIDFREQ_P1_MASK 0x00001f00
1061#define VIDFREQ_P1_SHIFT 8
1062#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1063#define VIDFREQ_P1_CSCLK_SHIFT 4
1064#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1065#define INTTOEXT_BASE_ILK 0x11300
1066#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
1067#define INTTOEXT_MAP3_SHIFT 24
1068#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1069#define INTTOEXT_MAP2_SHIFT 16
1070#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1071#define INTTOEXT_MAP1_SHIFT 8
1072#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1073#define INTTOEXT_MAP0_SHIFT 0
1074#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1075#define MEMSWCTL 0x11170 /* Ironlake only */
1076#define MEMCTL_CMD_MASK 0xe000
1077#define MEMCTL_CMD_SHIFT 13
1078#define MEMCTL_CMD_RCLK_OFF 0
1079#define MEMCTL_CMD_RCLK_ON 1
1080#define MEMCTL_CMD_CHFREQ 2
1081#define MEMCTL_CMD_CHVID 3
1082#define MEMCTL_CMD_VMMOFF 4
1083#define MEMCTL_CMD_VMMON 5
1084#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
1085 when command complete */
1086#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1087#define MEMCTL_FREQ_SHIFT 8
1088#define MEMCTL_SFCAVM (1<<7)
1089#define MEMCTL_TGT_VID_MASK 0x007f
1090#define MEMIHYST 0x1117c
1091#define MEMINTREN 0x11180 /* 16 bits */
1092#define MEMINT_RSEXIT_EN (1<<8)
1093#define MEMINT_CX_SUPR_EN (1<<7)
1094#define MEMINT_CONT_BUSY_EN (1<<6)
1095#define MEMINT_AVG_BUSY_EN (1<<5)
1096#define MEMINT_EVAL_CHG_EN (1<<4)
1097#define MEMINT_MON_IDLE_EN (1<<3)
1098#define MEMINT_UP_EVAL_EN (1<<2)
1099#define MEMINT_DOWN_EVAL_EN (1<<1)
1100#define MEMINT_SW_CMD_EN (1<<0)
1101#define MEMINTRSTR 0x11182 /* 16 bits */
1102#define MEM_RSEXIT_MASK 0xc000
1103#define MEM_RSEXIT_SHIFT 14
1104#define MEM_CONT_BUSY_MASK 0x3000
1105#define MEM_CONT_BUSY_SHIFT 12
1106#define MEM_AVG_BUSY_MASK 0x0c00
1107#define MEM_AVG_BUSY_SHIFT 10
1108#define MEM_EVAL_CHG_MASK 0x0300
1109#define MEM_EVAL_BUSY_SHIFT 8
1110#define MEM_MON_IDLE_MASK 0x00c0
1111#define MEM_MON_IDLE_SHIFT 6
1112#define MEM_UP_EVAL_MASK 0x0030
1113#define MEM_UP_EVAL_SHIFT 4
1114#define MEM_DOWN_EVAL_MASK 0x000c
1115#define MEM_DOWN_EVAL_SHIFT 2
1116#define MEM_SW_CMD_MASK 0x0003
1117#define MEM_INT_STEER_GFX 0
1118#define MEM_INT_STEER_CMR 1
1119#define MEM_INT_STEER_SMI 2
1120#define MEM_INT_STEER_SCI 3
1121#define MEMINTRSTS 0x11184
1122#define MEMINT_RSEXIT (1<<7)
1123#define MEMINT_CONT_BUSY (1<<6)
1124#define MEMINT_AVG_BUSY (1<<5)
1125#define MEMINT_EVAL_CHG (1<<4)
1126#define MEMINT_MON_IDLE (1<<3)
1127#define MEMINT_UP_EVAL (1<<2)
1128#define MEMINT_DOWN_EVAL (1<<1)
1129#define MEMINT_SW_CMD (1<<0)
1130#define MEMMODECTL 0x11190
1131#define MEMMODE_BOOST_EN (1<<31)
1132#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1133#define MEMMODE_BOOST_FREQ_SHIFT 24
1134#define MEMMODE_IDLE_MODE_MASK 0x00030000
1135#define MEMMODE_IDLE_MODE_SHIFT 16
1136#define MEMMODE_IDLE_MODE_EVAL 0
1137#define MEMMODE_IDLE_MODE_CONT 1
1138#define MEMMODE_HWIDLE_EN (1<<15)
1139#define MEMMODE_SWMODE_EN (1<<14)
1140#define MEMMODE_RCLK_GATE (1<<13)
1141#define MEMMODE_HW_UPDATE (1<<12)
1142#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1143#define MEMMODE_FSTART_SHIFT 8
1144#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1145#define MEMMODE_FMAX_SHIFT 4
1146#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1147#define RCBMAXAVG 0x1119c
1148#define MEMSWCTL2 0x1119e /* Cantiga only */
1149#define SWMEMCMD_RENDER_OFF (0 << 13)
1150#define SWMEMCMD_RENDER_ON (1 << 13)
1151#define SWMEMCMD_SWFREQ (2 << 13)
1152#define SWMEMCMD_TARVID (3 << 13)
1153#define SWMEMCMD_VRM_OFF (4 << 13)
1154#define SWMEMCMD_VRM_ON (5 << 13)
1155#define CMDSTS (1<<12)
1156#define SFCAVM (1<<11)
1157#define SWFREQ_MASK 0x0380 /* P0-7 */
1158#define SWFREQ_SHIFT 7
1159#define TARVID_MASK 0x001f
1160#define MEMSTAT_CTG 0x111a0
1161#define RCBMINAVG 0x111a0
1162#define RCUPEI 0x111b0
1163#define RCDNEI 0x111b4
1164#define RSTDBYCTL 0x111b8
1165#define RS1EN (1<<31)
1166#define RS2EN (1<<30)
1167#define RS3EN (1<<29)
1168#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
1169#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
1170#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
1171#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
1172#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
1173#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
1174#define RSX_STATUS_MASK (7<<20)
1175#define RSX_STATUS_ON (0<<20)
1176#define RSX_STATUS_RC1 (1<<20)
1177#define RSX_STATUS_RC1E (2<<20)
1178#define RSX_STATUS_RS1 (3<<20)
1179#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
1180#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
1181#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
1182#define RSX_STATUS_RSVD2 (7<<20)
1183#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
1184#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
1185#define JRSC (1<<17) /* rsx coupled to cpu c-state */
1186#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
1187#define RS1CONTSAV_MASK (3<<14)
1188#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
1189#define RS1CONTSAV_RSVD (1<<14)
1190#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
1191#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
1192#define NORMSLEXLAT_MASK (3<<12)
1193#define SLOW_RS123 (0<<12)
1194#define SLOW_RS23 (1<<12)
1195#define SLOW_RS3 (2<<12)
1196#define NORMAL_RS123 (3<<12)
1197#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
1198#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1199#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
1200#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
1201#define RS_CSTATE_MASK (3<<4)
1202#define RS_CSTATE_C367_RS1 (0<<4)
1203#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1204#define RS_CSTATE_RSVD (2<<4)
1205#define RS_CSTATE_C367_RS2 (3<<4)
1206#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
1207#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
1208#define VIDCTL 0x111c0
1209#define VIDSTS 0x111c8
1210#define VIDSTART 0x111cc /* 8 bits */
1211#define MEMSTAT_ILK 0x111f8
1212#define MEMSTAT_VID_MASK 0x7f00
1213#define MEMSTAT_VID_SHIFT 8
1214#define MEMSTAT_PSTATE_MASK 0x00f8
1215#define MEMSTAT_PSTATE_SHIFT 3
1216#define MEMSTAT_MON_ACTV (1<<2)
1217#define MEMSTAT_SRC_CTL_MASK 0x0003
1218#define MEMSTAT_SRC_CTL_CORE 0
1219#define MEMSTAT_SRC_CTL_TRB 1
1220#define MEMSTAT_SRC_CTL_THM 2
1221#define MEMSTAT_SRC_CTL_STDBY 3
1222#define RCPREVBSYTUPAVG 0x113b8
1223#define RCPREVBSYTDNAVG 0x113bc
1224#define PMMISC 0x11214
1225#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
1226#define SDEW 0x1124c
1227#define CSIEW0 0x11250
1228#define CSIEW1 0x11254
1229#define CSIEW2 0x11258
1230#define PEW 0x1125c
1231#define DEW 0x11270
1232#define MCHAFE 0x112c0
1233#define CSIEC 0x112e0
1234#define DMIEC 0x112e4
1235#define DDREC 0x112e8
1236#define PEG0EC 0x112ec
1237#define PEG1EC 0x112f0
1238#define GFXEC 0x112f4
1239#define RPPREVBSYTUPAVG 0x113b8
1240#define RPPREVBSYTDNAVG 0x113bc
1241#define ECR 0x11600
1242#define ECR_GPFE (1<<31)
1243#define ECR_IMONE (1<<30)
1244#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1245#define OGW0 0x11608
1246#define OGW1 0x1160c
1247#define EG0 0x11610
1248#define EG1 0x11614
1249#define EG2 0x11618
1250#define EG3 0x1161c
1251#define EG4 0x11620
1252#define EG5 0x11624
1253#define EG6 0x11628
1254#define EG7 0x1162c
1255#define PXW 0x11664
1256#define PXWL 0x11680
1257#define LCFUSE02 0x116c0
1258#define LCFUSE_HIV_MASK 0x000000ff
1259#define CSIPLL0 0x12c10
1260#define DDRMPLL1 0X12c20
1261#define PEG_BAND_GAP_DATA 0x14d68
1262
1263#define GEN6_GT_PERF_STATUS 0x145948
1264#define GEN6_RP_STATE_LIMITS 0x145994
1265#define GEN6_RP_STATE_CAP 0x145998
1266
1267/*
1268 * Logical Context regs
1269 */
1270#define CCID 0x2180
1271#define CCID_EN (1<<0)
1272/*
1273 * Overlay regs
1274 */
1275
1276#define OVADD 0x30000
1277#define DOVSTA 0x30008
1278#define OC_BUF (0x3<<20)
1279#define OGAMC5 0x30010
1280#define OGAMC4 0x30014
1281#define OGAMC3 0x30018
1282#define OGAMC2 0x3001c
1283#define OGAMC1 0x30020
1284#define OGAMC0 0x30024
1285
1286/*
1287 * Display engine regs
1288 */
1289
1290/* Pipe A timing regs */
1291#define _HTOTAL_A 0x60000
1292#define _HBLANK_A 0x60004
1293#define _HSYNC_A 0x60008
1294#define _VTOTAL_A 0x6000c
1295#define _VBLANK_A 0x60010
1296#define _VSYNC_A 0x60014
1297#define _PIPEASRC 0x6001c
1298#define _BCLRPAT_A 0x60020
1299
1300/* Pipe B timing regs */
1301#define _HTOTAL_B 0x61000
1302#define _HBLANK_B 0x61004
1303#define _HSYNC_B 0x61008
1304#define _VTOTAL_B 0x6100c
1305#define _VBLANK_B 0x61010
1306#define _VSYNC_B 0x61014
1307#define _PIPEBSRC 0x6101c
1308#define _BCLRPAT_B 0x61020
1309
1310#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
1311#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
1312#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
1313#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
1314#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
1315#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
1316#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1317
1318/* VGA port control */
1319#define ADPA 0x61100
1320#define ADPA_DAC_ENABLE (1<<31)
1321#define ADPA_DAC_DISABLE 0
1322#define ADPA_PIPE_SELECT_MASK (1<<30)
1323#define ADPA_PIPE_A_SELECT 0
1324#define ADPA_PIPE_B_SELECT (1<<30)
1325#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
1326#define ADPA_USE_VGA_HVPOLARITY (1<<15)
1327#define ADPA_SETS_HVPOLARITY 0
1328#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1329#define ADPA_VSYNC_CNTL_ENABLE 0
1330#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1331#define ADPA_HSYNC_CNTL_ENABLE 0
1332#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1333#define ADPA_VSYNC_ACTIVE_LOW 0
1334#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1335#define ADPA_HSYNC_ACTIVE_LOW 0
1336#define ADPA_DPMS_MASK (~(3<<10))
1337#define ADPA_DPMS_ON (0<<10)
1338#define ADPA_DPMS_SUSPEND (1<<10)
1339#define ADPA_DPMS_STANDBY (2<<10)
1340#define ADPA_DPMS_OFF (3<<10)
1341
1342
1343/* Hotplug control (945+ only) */
1344#define PORT_HOTPLUG_EN 0x61110
1345#define HDMIB_HOTPLUG_INT_EN (1 << 29)
1346#define DPB_HOTPLUG_INT_EN (1 << 29)
1347#define HDMIC_HOTPLUG_INT_EN (1 << 28)
1348#define DPC_HOTPLUG_INT_EN (1 << 28)
1349#define HDMID_HOTPLUG_INT_EN (1 << 27)
1350#define DPD_HOTPLUG_INT_EN (1 << 27)
1351#define SDVOB_HOTPLUG_INT_EN (1 << 26)
1352#define SDVOC_HOTPLUG_INT_EN (1 << 25)
1353#define TV_HOTPLUG_INT_EN (1 << 18)
1354#define CRT_HOTPLUG_INT_EN (1 << 9)
1355#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1356#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1357/* must use period 64 on GM45 according to docs */
1358#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1359#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1360#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1361#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1362#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1363#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1364#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1365#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1366#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1367#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1368#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1369#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1370
1371#define PORT_HOTPLUG_STAT 0x61114
1372#define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
1373#define DPB_HOTPLUG_INT_STATUS (1 << 29)
1374#define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
1375#define DPC_HOTPLUG_INT_STATUS (1 << 28)
1376#define HDMID_HOTPLUG_INT_STATUS (1 << 27)
1377#define DPD_HOTPLUG_INT_STATUS (1 << 27)
1378#define CRT_HOTPLUG_INT_STATUS (1 << 11)
1379#define TV_HOTPLUG_INT_STATUS (1 << 10)
1380#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1381#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1382#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1383#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1384#define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
1385#define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1386
1387/* SDVO port control */
1388#define SDVOB 0x61140
1389#define SDVOC 0x61160
1390#define SDVO_ENABLE (1 << 31)
1391#define SDVO_PIPE_B_SELECT (1 << 30)
1392#define SDVO_STALL_SELECT (1 << 29)
1393#define SDVO_INTERRUPT_ENABLE (1 << 26)
1394/**
1395 * 915G/GM SDVO pixel multiplier.
1396 *
1397 * Programmed value is multiplier - 1, up to 5x.
1398 *
1399 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1400 */
1401#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1402#define SDVO_PORT_MULTIPLY_SHIFT 23
1403#define SDVO_PHASE_SELECT_MASK (15 << 19)
1404#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1405#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1406#define SDVOC_GANG_MODE (1 << 16)
1407#define SDVO_ENCODING_SDVO (0x0 << 10)
1408#define SDVO_ENCODING_HDMI (0x2 << 10)
1409/** Requird for HDMI operation */
1410#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1411#define SDVO_COLOR_RANGE_16_235 (1 << 8)
1412#define SDVO_BORDER_ENABLE (1 << 7)
1413#define SDVO_AUDIO_ENABLE (1 << 6)
1414/** New with 965, default is to be set */
1415#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1416/** New with 965, default is to be set */
1417#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1418#define SDVOB_PCIE_CONCURRENCY (1 << 3)
1419#define SDVO_DETECTED (1 << 2)
1420/* Bits to be preserved when writing */
1421#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1422#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1423
1424/* DVO port control */
1425#define DVOA 0x61120
1426#define DVOB 0x61140
1427#define DVOC 0x61160
1428#define DVO_ENABLE (1 << 31)
1429#define DVO_PIPE_B_SELECT (1 << 30)
1430#define DVO_PIPE_STALL_UNUSED (0 << 28)
1431#define DVO_PIPE_STALL (1 << 28)
1432#define DVO_PIPE_STALL_TV (2 << 28)
1433#define DVO_PIPE_STALL_MASK (3 << 28)
1434#define DVO_USE_VGA_SYNC (1 << 15)
1435#define DVO_DATA_ORDER_I740 (0 << 14)
1436#define DVO_DATA_ORDER_FP (1 << 14)
1437#define DVO_VSYNC_DISABLE (1 << 11)
1438#define DVO_HSYNC_DISABLE (1 << 10)
1439#define DVO_VSYNC_TRISTATE (1 << 9)
1440#define DVO_HSYNC_TRISTATE (1 << 8)
1441#define DVO_BORDER_ENABLE (1 << 7)
1442#define DVO_DATA_ORDER_GBRG (1 << 6)
1443#define DVO_DATA_ORDER_RGGB (0 << 6)
1444#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1445#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1446#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1447#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1448#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1449#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1450#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1451#define DVO_PRESERVE_MASK (0x7<<24)
1452#define DVOA_SRCDIM 0x61124
1453#define DVOB_SRCDIM 0x61144
1454#define DVOC_SRCDIM 0x61164
1455#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1456#define DVO_SRCDIM_VERTICAL_SHIFT 0
1457
1458/* LVDS port control */
1459#define LVDS 0x61180
1460/*
1461 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1462 * the DPLL semantics change when the LVDS is assigned to that pipe.
1463 */
1464#define LVDS_PORT_EN (1 << 31)
1465/* Selects pipe B for LVDS data. Must be set on pre-965. */
1466#define LVDS_PIPEB_SELECT (1 << 30)
1467#define LVDS_PIPE_MASK (1 << 30)
1468#define LVDS_PIPE(pipe) ((pipe) << 30)
1469/* LVDS dithering flag on 965/g4x platform */
1470#define LVDS_ENABLE_DITHER (1 << 25)
1471/* LVDS sync polarity flags. Set to invert (i.e. negative) */
1472#define LVDS_VSYNC_POLARITY (1 << 21)
1473#define LVDS_HSYNC_POLARITY (1 << 20)
1474
1475/* Enable border for unscaled (or aspect-scaled) display */
1476#define LVDS_BORDER_ENABLE (1 << 15)
1477/*
1478 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1479 * pixel.
1480 */
1481#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1482#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1483#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1484/*
1485 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1486 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1487 * on.
1488 */
1489#define LVDS_A3_POWER_MASK (3 << 6)
1490#define LVDS_A3_POWER_DOWN (0 << 6)
1491#define LVDS_A3_POWER_UP (3 << 6)
1492/*
1493 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1494 * is set.
1495 */
1496#define LVDS_CLKB_POWER_MASK (3 << 4)
1497#define LVDS_CLKB_POWER_DOWN (0 << 4)
1498#define LVDS_CLKB_POWER_UP (3 << 4)
1499/*
1500 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1501 * setting for whether we are in dual-channel mode. The B3 pair will
1502 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1503 */
1504#define LVDS_B0B3_POWER_MASK (3 << 2)
1505#define LVDS_B0B3_POWER_DOWN (0 << 2)
1506#define LVDS_B0B3_POWER_UP (3 << 2)
1507
1508/* Video Data Island Packet control */
1509#define VIDEO_DIP_DATA 0x61178
1510#define VIDEO_DIP_CTL 0x61170
1511#define VIDEO_DIP_ENABLE (1 << 31)
1512#define VIDEO_DIP_PORT_B (1 << 29)
1513#define VIDEO_DIP_PORT_C (2 << 29)
1514#define VIDEO_DIP_ENABLE_AVI (1 << 21)
1515#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
1516#define VIDEO_DIP_ENABLE_SPD (8 << 21)
1517#define VIDEO_DIP_SELECT_AVI (0 << 19)
1518#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
1519#define VIDEO_DIP_SELECT_SPD (3 << 19)
1520#define VIDEO_DIP_SELECT_MASK (3 << 19)
1521#define VIDEO_DIP_FREQ_ONCE (0 << 16)
1522#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
1523#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
1524
1525/* Panel power sequencing */
1526#define PP_STATUS 0x61200
1527#define PP_ON (1 << 31)
1528/*
1529 * Indicates that all dependencies of the panel are on:
1530 *
1531 * - PLL enabled
1532 * - pipe enabled
1533 * - LVDS/DVOB/DVOC on
1534 */
1535#define PP_READY (1 << 30)
1536#define PP_SEQUENCE_NONE (0 << 28)
1537#define PP_SEQUENCE_ON (1 << 28)
1538#define PP_SEQUENCE_OFF (2 << 28)
1539#define PP_SEQUENCE_MASK 0x30000000
1540#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
1541#define PP_SEQUENCE_STATE_ON_IDLE (1 << 3)
1542#define PP_SEQUENCE_STATE_MASK 0x0000000f
1543#define PP_CONTROL 0x61204
1544#define POWER_TARGET_ON (1 << 0)
1545#define PP_ON_DELAYS 0x61208
1546#define PP_OFF_DELAYS 0x6120c
1547#define PP_DIVISOR 0x61210
1548
1549/* Panel fitting */
1550#define PFIT_CONTROL 0x61230
1551#define PFIT_ENABLE (1 << 31)
1552#define PFIT_PIPE_MASK (3 << 29)
1553#define PFIT_PIPE_SHIFT 29
1554#define VERT_INTERP_DISABLE (0 << 10)
1555#define VERT_INTERP_BILINEAR (1 << 10)
1556#define VERT_INTERP_MASK (3 << 10)
1557#define VERT_AUTO_SCALE (1 << 9)
1558#define HORIZ_INTERP_DISABLE (0 << 6)
1559#define HORIZ_INTERP_BILINEAR (1 << 6)
1560#define HORIZ_INTERP_MASK (3 << 6)
1561#define HORIZ_AUTO_SCALE (1 << 5)
1562#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1563#define PFIT_FILTER_FUZZY (0 << 24)
1564#define PFIT_SCALING_AUTO (0 << 26)
1565#define PFIT_SCALING_PROGRAMMED (1 << 26)
1566#define PFIT_SCALING_PILLAR (2 << 26)
1567#define PFIT_SCALING_LETTER (3 << 26)
1568#define PFIT_PGM_RATIOS 0x61234
1569#define PFIT_VERT_SCALE_MASK 0xfff00000
1570#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1571/* Pre-965 */
1572#define PFIT_VERT_SCALE_SHIFT 20
1573#define PFIT_VERT_SCALE_MASK 0xfff00000
1574#define PFIT_HORIZ_SCALE_SHIFT 4
1575#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1576/* 965+ */
1577#define PFIT_VERT_SCALE_SHIFT_965 16
1578#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1579#define PFIT_HORIZ_SCALE_SHIFT_965 0
1580#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1581
1582#define PFIT_AUTO_RATIOS 0x61238
1583
1584/* Backlight control */
1585#define BLC_PWM_CTL 0x61254
1586#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1587#define BLC_PWM_CTL2 0x61250 /* 965+ only */
1588#define BLM_COMBINATION_MODE (1 << 30)
1589/*
1590 * This is the most significant 15 bits of the number of backlight cycles in a
1591 * complete cycle of the modulated backlight control.
1592 *
1593 * The actual value is this field multiplied by two.
1594 */
1595#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1596#define BLM_LEGACY_MODE (1 << 16)
1597/*
1598 * This is the number of cycles out of the backlight modulation cycle for which
1599 * the backlight is on.
1600 *
1601 * This field must be no greater than the number of cycles in the complete
1602 * backlight modulation cycle.
1603 */
1604#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1605#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1606
1607#define BLC_HIST_CTL 0x61260
1608
1609/* TV port control */
1610#define TV_CTL 0x68000
1611/** Enables the TV encoder */
1612# define TV_ENC_ENABLE (1 << 31)
1613/** Sources the TV encoder input from pipe B instead of A. */
1614# define TV_ENC_PIPEB_SELECT (1 << 30)
1615/** Outputs composite video (DAC A only) */
1616# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1617/** Outputs SVideo video (DAC B/C) */
1618# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1619/** Outputs Component video (DAC A/B/C) */
1620# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1621/** Outputs Composite and SVideo (DAC A/B/C) */
1622# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1623# define TV_TRILEVEL_SYNC (1 << 21)
1624/** Enables slow sync generation (945GM only) */
1625# define TV_SLOW_SYNC (1 << 20)
1626/** Selects 4x oversampling for 480i and 576p */
1627# define TV_OVERSAMPLE_4X (0 << 18)
1628/** Selects 2x oversampling for 720p and 1080i */
1629# define TV_OVERSAMPLE_2X (1 << 18)
1630/** Selects no oversampling for 1080p */
1631# define TV_OVERSAMPLE_NONE (2 << 18)
1632/** Selects 8x oversampling */
1633# define TV_OVERSAMPLE_8X (3 << 18)
1634/** Selects progressive mode rather than interlaced */
1635# define TV_PROGRESSIVE (1 << 17)
1636/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
1637# define TV_PAL_BURST (1 << 16)
1638/** Field for setting delay of Y compared to C */
1639# define TV_YC_SKEW_MASK (7 << 12)
1640/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1641# define TV_ENC_SDP_FIX (1 << 11)
1642/**
1643 * Enables a fix for the 915GM only.
1644 *
1645 * Not sure what it does.
1646 */
1647# define TV_ENC_C0_FIX (1 << 10)
1648/** Bits that must be preserved by software */
1649# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
1650# define TV_FUSE_STATE_MASK (3 << 4)
1651/** Read-only state that reports all features enabled */
1652# define TV_FUSE_STATE_ENABLED (0 << 4)
1653/** Read-only state that reports that Macrovision is disabled in hardware*/
1654# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
1655/** Read-only state that reports that TV-out is disabled in hardware. */
1656# define TV_FUSE_STATE_DISABLED (2 << 4)
1657/** Normal operation */
1658# define TV_TEST_MODE_NORMAL (0 << 0)
1659/** Encoder test pattern 1 - combo pattern */
1660# define TV_TEST_MODE_PATTERN_1 (1 << 0)
1661/** Encoder test pattern 2 - full screen vertical 75% color bars */
1662# define TV_TEST_MODE_PATTERN_2 (2 << 0)
1663/** Encoder test pattern 3 - full screen horizontal 75% color bars */
1664# define TV_TEST_MODE_PATTERN_3 (3 << 0)
1665/** Encoder test pattern 4 - random noise */
1666# define TV_TEST_MODE_PATTERN_4 (4 << 0)
1667/** Encoder test pattern 5 - linear color ramps */
1668# define TV_TEST_MODE_PATTERN_5 (5 << 0)
1669/**
1670 * This test mode forces the DACs to 50% of full output.
1671 *
1672 * This is used for load detection in combination with TVDAC_SENSE_MASK
1673 */
1674# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
1675# define TV_TEST_MODE_MASK (7 << 0)
1676
1677#define TV_DAC 0x68004
1678# define TV_DAC_SAVE 0x00ffff00
1679/**
1680 * Reports that DAC state change logic has reported change (RO).
1681 *
1682 * This gets cleared when TV_DAC_STATE_EN is cleared
1683*/
1684# define TVDAC_STATE_CHG (1 << 31)
1685# define TVDAC_SENSE_MASK (7 << 28)
1686/** Reports that DAC A voltage is above the detect threshold */
1687# define TVDAC_A_SENSE (1 << 30)
1688/** Reports that DAC B voltage is above the detect threshold */
1689# define TVDAC_B_SENSE (1 << 29)
1690/** Reports that DAC C voltage is above the detect threshold */
1691# define TVDAC_C_SENSE (1 << 28)
1692/**
1693 * Enables DAC state detection logic, for load-based TV detection.
1694 *
1695 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
1696 * to off, for load detection to work.
1697 */
1698# define TVDAC_STATE_CHG_EN (1 << 27)
1699/** Sets the DAC A sense value to high */
1700# define TVDAC_A_SENSE_CTL (1 << 26)
1701/** Sets the DAC B sense value to high */
1702# define TVDAC_B_SENSE_CTL (1 << 25)
1703/** Sets the DAC C sense value to high */
1704# define TVDAC_C_SENSE_CTL (1 << 24)
1705/** Overrides the ENC_ENABLE and DAC voltage levels */
1706# define DAC_CTL_OVERRIDE (1 << 7)
1707/** Sets the slew rate. Must be preserved in software */
1708# define ENC_TVDAC_SLEW_FAST (1 << 6)
1709# define DAC_A_1_3_V (0 << 4)
1710# define DAC_A_1_1_V (1 << 4)
1711# define DAC_A_0_7_V (2 << 4)
1712# define DAC_A_MASK (3 << 4)
1713# define DAC_B_1_3_V (0 << 2)
1714# define DAC_B_1_1_V (1 << 2)
1715# define DAC_B_0_7_V (2 << 2)
1716# define DAC_B_MASK (3 << 2)
1717# define DAC_C_1_3_V (0 << 0)
1718# define DAC_C_1_1_V (1 << 0)
1719# define DAC_C_0_7_V (2 << 0)
1720# define DAC_C_MASK (3 << 0)
1721
1722/**
1723 * CSC coefficients are stored in a floating point format with 9 bits of
1724 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
1725 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1726 * -1 (0x3) being the only legal negative value.
1727 */
1728#define TV_CSC_Y 0x68010
1729# define TV_RY_MASK 0x07ff0000
1730# define TV_RY_SHIFT 16
1731# define TV_GY_MASK 0x00000fff
1732# define TV_GY_SHIFT 0
1733
1734#define TV_CSC_Y2 0x68014
1735# define TV_BY_MASK 0x07ff0000
1736# define TV_BY_SHIFT 16
1737/**
1738 * Y attenuation for component video.
1739 *
1740 * Stored in 1.9 fixed point.
1741 */
1742# define TV_AY_MASK 0x000003ff
1743# define TV_AY_SHIFT 0
1744
1745#define TV_CSC_U 0x68018
1746# define TV_RU_MASK 0x07ff0000
1747# define TV_RU_SHIFT 16
1748# define TV_GU_MASK 0x000007ff
1749# define TV_GU_SHIFT 0
1750
1751#define TV_CSC_U2 0x6801c
1752# define TV_BU_MASK 0x07ff0000
1753# define TV_BU_SHIFT 16
1754/**
1755 * U attenuation for component video.
1756 *
1757 * Stored in 1.9 fixed point.
1758 */
1759# define TV_AU_MASK 0x000003ff
1760# define TV_AU_SHIFT 0
1761
1762#define TV_CSC_V 0x68020
1763# define TV_RV_MASK 0x0fff0000
1764# define TV_RV_SHIFT 16
1765# define TV_GV_MASK 0x000007ff
1766# define TV_GV_SHIFT 0
1767
1768#define TV_CSC_V2 0x68024
1769# define TV_BV_MASK 0x07ff0000
1770# define TV_BV_SHIFT 16
1771/**
1772 * V attenuation for component video.
1773 *
1774 * Stored in 1.9 fixed point.
1775 */
1776# define TV_AV_MASK 0x000007ff
1777# define TV_AV_SHIFT 0
1778
1779#define TV_CLR_KNOBS 0x68028
1780/** 2s-complement brightness adjustment */
1781# define TV_BRIGHTNESS_MASK 0xff000000
1782# define TV_BRIGHTNESS_SHIFT 24
1783/** Contrast adjustment, as a 2.6 unsigned floating point number */
1784# define TV_CONTRAST_MASK 0x00ff0000
1785# define TV_CONTRAST_SHIFT 16
1786/** Saturation adjustment, as a 2.6 unsigned floating point number */
1787# define TV_SATURATION_MASK 0x0000ff00
1788# define TV_SATURATION_SHIFT 8
1789/** Hue adjustment, as an integer phase angle in degrees */
1790# define TV_HUE_MASK 0x000000ff
1791# define TV_HUE_SHIFT 0
1792
1793#define TV_CLR_LEVEL 0x6802c
1794/** Controls the DAC level for black */
1795# define TV_BLACK_LEVEL_MASK 0x01ff0000
1796# define TV_BLACK_LEVEL_SHIFT 16
1797/** Controls the DAC level for blanking */
1798# define TV_BLANK_LEVEL_MASK 0x000001ff
1799# define TV_BLANK_LEVEL_SHIFT 0
1800
1801#define TV_H_CTL_1 0x68030
1802/** Number of pixels in the hsync. */
1803# define TV_HSYNC_END_MASK 0x1fff0000
1804# define TV_HSYNC_END_SHIFT 16
1805/** Total number of pixels minus one in the line (display and blanking). */
1806# define TV_HTOTAL_MASK 0x00001fff
1807# define TV_HTOTAL_SHIFT 0
1808
1809#define TV_H_CTL_2 0x68034
1810/** Enables the colorburst (needed for non-component color) */
1811# define TV_BURST_ENA (1 << 31)
1812/** Offset of the colorburst from the start of hsync, in pixels minus one. */
1813# define TV_HBURST_START_SHIFT 16
1814# define TV_HBURST_START_MASK 0x1fff0000
1815/** Length of the colorburst */
1816# define TV_HBURST_LEN_SHIFT 0
1817# define TV_HBURST_LEN_MASK 0x0001fff
1818
1819#define TV_H_CTL_3 0x68038
1820/** End of hblank, measured in pixels minus one from start of hsync */
1821# define TV_HBLANK_END_SHIFT 16
1822# define TV_HBLANK_END_MASK 0x1fff0000
1823/** Start of hblank, measured in pixels minus one from start of hsync */
1824# define TV_HBLANK_START_SHIFT 0
1825# define TV_HBLANK_START_MASK 0x0001fff
1826
1827#define TV_V_CTL_1 0x6803c
1828/** XXX */
1829# define TV_NBR_END_SHIFT 16
1830# define TV_NBR_END_MASK 0x07ff0000
1831/** XXX */
1832# define TV_VI_END_F1_SHIFT 8
1833# define TV_VI_END_F1_MASK 0x00003f00
1834/** XXX */
1835# define TV_VI_END_F2_SHIFT 0
1836# define TV_VI_END_F2_MASK 0x0000003f
1837
1838#define TV_V_CTL_2 0x68040
1839/** Length of vsync, in half lines */
1840# define TV_VSYNC_LEN_MASK 0x07ff0000
1841# define TV_VSYNC_LEN_SHIFT 16
1842/** Offset of the start of vsync in field 1, measured in one less than the
1843 * number of half lines.
1844 */
1845# define TV_VSYNC_START_F1_MASK 0x00007f00
1846# define TV_VSYNC_START_F1_SHIFT 8
1847/**
1848 * Offset of the start of vsync in field 2, measured in one less than the
1849 * number of half lines.
1850 */
1851# define TV_VSYNC_START_F2_MASK 0x0000007f
1852# define TV_VSYNC_START_F2_SHIFT 0
1853
1854#define TV_V_CTL_3 0x68044
1855/** Enables generation of the equalization signal */
1856# define TV_EQUAL_ENA (1 << 31)
1857/** Length of vsync, in half lines */
1858# define TV_VEQ_LEN_MASK 0x007f0000
1859# define TV_VEQ_LEN_SHIFT 16
1860/** Offset of the start of equalization in field 1, measured in one less than
1861 * the number of half lines.
1862 */
1863# define TV_VEQ_START_F1_MASK 0x0007f00
1864# define TV_VEQ_START_F1_SHIFT 8
1865/**
1866 * Offset of the start of equalization in field 2, measured in one less than
1867 * the number of half lines.
1868 */
1869# define TV_VEQ_START_F2_MASK 0x000007f
1870# define TV_VEQ_START_F2_SHIFT 0
1871
1872#define TV_V_CTL_4 0x68048
1873/**
1874 * Offset to start of vertical colorburst, measured in one less than the
1875 * number of lines from vertical start.
1876 */
1877# define TV_VBURST_START_F1_MASK 0x003f0000
1878# define TV_VBURST_START_F1_SHIFT 16
1879/**
1880 * Offset to the end of vertical colorburst, measured in one less than the
1881 * number of lines from the start of NBR.
1882 */
1883# define TV_VBURST_END_F1_MASK 0x000000ff
1884# define TV_VBURST_END_F1_SHIFT 0
1885
1886#define TV_V_CTL_5 0x6804c
1887/**
1888 * Offset to start of vertical colorburst, measured in one less than the
1889 * number of lines from vertical start.
1890 */
1891# define TV_VBURST_START_F2_MASK 0x003f0000
1892# define TV_VBURST_START_F2_SHIFT 16
1893/**
1894 * Offset to the end of vertical colorburst, measured in one less than the
1895 * number of lines from the start of NBR.
1896 */
1897# define TV_VBURST_END_F2_MASK 0x000000ff
1898# define TV_VBURST_END_F2_SHIFT 0
1899
1900#define TV_V_CTL_6 0x68050
1901/**
1902 * Offset to start of vertical colorburst, measured in one less than the
1903 * number of lines from vertical start.
1904 */
1905# define TV_VBURST_START_F3_MASK 0x003f0000
1906# define TV_VBURST_START_F3_SHIFT 16
1907/**
1908 * Offset to the end of vertical colorburst, measured in one less than the
1909 * number of lines from the start of NBR.
1910 */
1911# define TV_VBURST_END_F3_MASK 0x000000ff
1912# define TV_VBURST_END_F3_SHIFT 0
1913
1914#define TV_V_CTL_7 0x68054
1915/**
1916 * Offset to start of vertical colorburst, measured in one less than the
1917 * number of lines from vertical start.
1918 */
1919# define TV_VBURST_START_F4_MASK 0x003f0000
1920# define TV_VBURST_START_F4_SHIFT 16
1921/**
1922 * Offset to the end of vertical colorburst, measured in one less than the
1923 * number of lines from the start of NBR.
1924 */
1925# define TV_VBURST_END_F4_MASK 0x000000ff
1926# define TV_VBURST_END_F4_SHIFT 0
1927
1928#define TV_SC_CTL_1 0x68060
1929/** Turns on the first subcarrier phase generation DDA */
1930# define TV_SC_DDA1_EN (1 << 31)
1931/** Turns on the first subcarrier phase generation DDA */
1932# define TV_SC_DDA2_EN (1 << 30)
1933/** Turns on the first subcarrier phase generation DDA */
1934# define TV_SC_DDA3_EN (1 << 29)
1935/** Sets the subcarrier DDA to reset frequency every other field */
1936# define TV_SC_RESET_EVERY_2 (0 << 24)
1937/** Sets the subcarrier DDA to reset frequency every fourth field */
1938# define TV_SC_RESET_EVERY_4 (1 << 24)
1939/** Sets the subcarrier DDA to reset frequency every eighth field */
1940# define TV_SC_RESET_EVERY_8 (2 << 24)
1941/** Sets the subcarrier DDA to never reset the frequency */
1942# define TV_SC_RESET_NEVER (3 << 24)
1943/** Sets the peak amplitude of the colorburst.*/
1944# define TV_BURST_LEVEL_MASK 0x00ff0000
1945# define TV_BURST_LEVEL_SHIFT 16
1946/** Sets the increment of the first subcarrier phase generation DDA */
1947# define TV_SCDDA1_INC_MASK 0x00000fff
1948# define TV_SCDDA1_INC_SHIFT 0
1949
1950#define TV_SC_CTL_2 0x68064
1951/** Sets the rollover for the second subcarrier phase generation DDA */
1952# define TV_SCDDA2_SIZE_MASK 0x7fff0000
1953# define TV_SCDDA2_SIZE_SHIFT 16
1954/** Sets the increent of the second subcarrier phase generation DDA */
1955# define TV_SCDDA2_INC_MASK 0x00007fff
1956# define TV_SCDDA2_INC_SHIFT 0
1957
1958#define TV_SC_CTL_3 0x68068
1959/** Sets the rollover for the third subcarrier phase generation DDA */
1960# define TV_SCDDA3_SIZE_MASK 0x7fff0000
1961# define TV_SCDDA3_SIZE_SHIFT 16
1962/** Sets the increent of the third subcarrier phase generation DDA */
1963# define TV_SCDDA3_INC_MASK 0x00007fff
1964# define TV_SCDDA3_INC_SHIFT 0
1965
1966#define TV_WIN_POS 0x68070
1967/** X coordinate of the display from the start of horizontal active */
1968# define TV_XPOS_MASK 0x1fff0000
1969# define TV_XPOS_SHIFT 16
1970/** Y coordinate of the display from the start of vertical active (NBR) */
1971# define TV_YPOS_MASK 0x00000fff
1972# define TV_YPOS_SHIFT 0
1973
1974#define TV_WIN_SIZE 0x68074
1975/** Horizontal size of the display window, measured in pixels*/
1976# define TV_XSIZE_MASK 0x1fff0000
1977# define TV_XSIZE_SHIFT 16
1978/**
1979 * Vertical size of the display window, measured in pixels.
1980 *
1981 * Must be even for interlaced modes.
1982 */
1983# define TV_YSIZE_MASK 0x00000fff
1984# define TV_YSIZE_SHIFT 0
1985
1986#define TV_FILTER_CTL_1 0x68080
1987/**
1988 * Enables automatic scaling calculation.
1989 *
1990 * If set, the rest of the registers are ignored, and the calculated values can
1991 * be read back from the register.
1992 */
1993# define TV_AUTO_SCALE (1 << 31)
1994/**
1995 * Disables the vertical filter.
1996 *
1997 * This is required on modes more than 1024 pixels wide */
1998# define TV_V_FILTER_BYPASS (1 << 29)
1999/** Enables adaptive vertical filtering */
2000# define TV_VADAPT (1 << 28)
2001# define TV_VADAPT_MODE_MASK (3 << 26)
2002/** Selects the least adaptive vertical filtering mode */
2003# define TV_VADAPT_MODE_LEAST (0 << 26)
2004/** Selects the moderately adaptive vertical filtering mode */
2005# define TV_VADAPT_MODE_MODERATE (1 << 26)
2006/** Selects the most adaptive vertical filtering mode */
2007# define TV_VADAPT_MODE_MOST (3 << 26)
2008/**
2009 * Sets the horizontal scaling factor.
2010 *
2011 * This should be the fractional part of the horizontal scaling factor divided
2012 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
2013 *
2014 * (src width - 1) / ((oversample * dest width) - 1)
2015 */
2016# define TV_HSCALE_FRAC_MASK 0x00003fff
2017# define TV_HSCALE_FRAC_SHIFT 0
2018
2019#define TV_FILTER_CTL_2 0x68084
2020/**
2021 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2022 *
2023 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2024 */
2025# define TV_VSCALE_INT_MASK 0x00038000
2026# define TV_VSCALE_INT_SHIFT 15
2027/**
2028 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2029 *
2030 * \sa TV_VSCALE_INT_MASK
2031 */
2032# define TV_VSCALE_FRAC_MASK 0x00007fff
2033# define TV_VSCALE_FRAC_SHIFT 0
2034
2035#define TV_FILTER_CTL_3 0x68088
2036/**
2037 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2038 *
2039 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2040 *
2041 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2042 */
2043# define TV_VSCALE_IP_INT_MASK 0x00038000
2044# define TV_VSCALE_IP_INT_SHIFT 15
2045/**
2046 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2047 *
2048 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2049 *
2050 * \sa TV_VSCALE_IP_INT_MASK
2051 */
2052# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2053# define TV_VSCALE_IP_FRAC_SHIFT 0
2054
2055#define TV_CC_CONTROL 0x68090
2056# define TV_CC_ENABLE (1 << 31)
2057/**
2058 * Specifies which field to send the CC data in.
2059 *
2060 * CC data is usually sent in field 0.
2061 */
2062# define TV_CC_FID_MASK (1 << 27)
2063# define TV_CC_FID_SHIFT 27
2064/** Sets the horizontal position of the CC data. Usually 135. */
2065# define TV_CC_HOFF_MASK 0x03ff0000
2066# define TV_CC_HOFF_SHIFT 16
2067/** Sets the vertical position of the CC data. Usually 21 */
2068# define TV_CC_LINE_MASK 0x0000003f
2069# define TV_CC_LINE_SHIFT 0
2070
2071#define TV_CC_DATA 0x68094
2072# define TV_CC_RDY (1 << 31)
2073/** Second word of CC data to be transmitted. */
2074# define TV_CC_DATA_2_MASK 0x007f0000
2075# define TV_CC_DATA_2_SHIFT 16
2076/** First word of CC data to be transmitted. */
2077# define TV_CC_DATA_1_MASK 0x0000007f
2078# define TV_CC_DATA_1_SHIFT 0
2079
2080#define TV_H_LUMA_0 0x68100
2081#define TV_H_LUMA_59 0x681ec
2082#define TV_H_CHROMA_0 0x68200
2083#define TV_H_CHROMA_59 0x682ec
2084#define TV_V_LUMA_0 0x68300
2085#define TV_V_LUMA_42 0x683a8
2086#define TV_V_CHROMA_0 0x68400
2087#define TV_V_CHROMA_42 0x684a8
2088
2089/* Display Port */
2090#define DP_A 0x64000 /* eDP */
2091#define DP_B 0x64100
2092#define DP_C 0x64200
2093#define DP_D 0x64300
2094
2095#define DP_PORT_EN (1 << 31)
2096#define DP_PIPEB_SELECT (1 << 30)
2097#define DP_PIPE_MASK (1 << 30)
2098
2099/* Link training mode - select a suitable mode for each stage */
2100#define DP_LINK_TRAIN_PAT_1 (0 << 28)
2101#define DP_LINK_TRAIN_PAT_2 (1 << 28)
2102#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
2103#define DP_LINK_TRAIN_OFF (3 << 28)
2104#define DP_LINK_TRAIN_MASK (3 << 28)
2105#define DP_LINK_TRAIN_SHIFT 28
2106
2107/* CPT Link training mode */
2108#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
2109#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
2110#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
2111#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
2112#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
2113#define DP_LINK_TRAIN_SHIFT_CPT 8
2114
2115/* Signal voltages. These are mostly controlled by the other end */
2116#define DP_VOLTAGE_0_4 (0 << 25)
2117#define DP_VOLTAGE_0_6 (1 << 25)
2118#define DP_VOLTAGE_0_8 (2 << 25)
2119#define DP_VOLTAGE_1_2 (3 << 25)
2120#define DP_VOLTAGE_MASK (7 << 25)
2121#define DP_VOLTAGE_SHIFT 25
2122
2123/* Signal pre-emphasis levels, like voltages, the other end tells us what
2124 * they want
2125 */
2126#define DP_PRE_EMPHASIS_0 (0 << 22)
2127#define DP_PRE_EMPHASIS_3_5 (1 << 22)
2128#define DP_PRE_EMPHASIS_6 (2 << 22)
2129#define DP_PRE_EMPHASIS_9_5 (3 << 22)
2130#define DP_PRE_EMPHASIS_MASK (7 << 22)
2131#define DP_PRE_EMPHASIS_SHIFT 22
2132
2133/* How many wires to use. I guess 3 was too hard */
2134#define DP_PORT_WIDTH_1 (0 << 19)
2135#define DP_PORT_WIDTH_2 (1 << 19)
2136#define DP_PORT_WIDTH_4 (3 << 19)
2137#define DP_PORT_WIDTH_MASK (7 << 19)
2138
2139/* Mystic DPCD version 1.1 special mode */
2140#define DP_ENHANCED_FRAMING (1 << 18)
2141
2142/* eDP */
2143#define DP_PLL_FREQ_270MHZ (0 << 16)
2144#define DP_PLL_FREQ_160MHZ (1 << 16)
2145#define DP_PLL_FREQ_MASK (3 << 16)
2146
2147/** locked once port is enabled */
2148#define DP_PORT_REVERSAL (1 << 15)
2149
2150/* eDP */
2151#define DP_PLL_ENABLE (1 << 14)
2152
2153/** sends the clock on lane 15 of the PEG for debug */
2154#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
2155
2156#define DP_SCRAMBLING_DISABLE (1 << 12)
2157#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
2158
2159/** limit RGB values to avoid confusing TVs */
2160#define DP_COLOR_RANGE_16_235 (1 << 8)
2161
2162/** Turn on the audio link */
2163#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
2164
2165/** vs and hs sync polarity */
2166#define DP_SYNC_VS_HIGH (1 << 4)
2167#define DP_SYNC_HS_HIGH (1 << 3)
2168
2169/** A fantasy */
2170#define DP_DETECTED (1 << 2)
2171
2172/** The aux channel provides a way to talk to the
2173 * signal sink for DDC etc. Max packet size supported
2174 * is 20 bytes in each direction, hence the 5 fixed
2175 * data registers
2176 */
2177#define DPA_AUX_CH_CTL 0x64010
2178#define DPA_AUX_CH_DATA1 0x64014
2179#define DPA_AUX_CH_DATA2 0x64018
2180#define DPA_AUX_CH_DATA3 0x6401c
2181#define DPA_AUX_CH_DATA4 0x64020
2182#define DPA_AUX_CH_DATA5 0x64024
2183
2184#define DPB_AUX_CH_CTL 0x64110
2185#define DPB_AUX_CH_DATA1 0x64114
2186#define DPB_AUX_CH_DATA2 0x64118
2187#define DPB_AUX_CH_DATA3 0x6411c
2188#define DPB_AUX_CH_DATA4 0x64120
2189#define DPB_AUX_CH_DATA5 0x64124
2190
2191#define DPC_AUX_CH_CTL 0x64210
2192#define DPC_AUX_CH_DATA1 0x64214
2193#define DPC_AUX_CH_DATA2 0x64218
2194#define DPC_AUX_CH_DATA3 0x6421c
2195#define DPC_AUX_CH_DATA4 0x64220
2196#define DPC_AUX_CH_DATA5 0x64224
2197
2198#define DPD_AUX_CH_CTL 0x64310
2199#define DPD_AUX_CH_DATA1 0x64314
2200#define DPD_AUX_CH_DATA2 0x64318
2201#define DPD_AUX_CH_DATA3 0x6431c
2202#define DPD_AUX_CH_DATA4 0x64320
2203#define DPD_AUX_CH_DATA5 0x64324
2204
2205#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
2206#define DP_AUX_CH_CTL_DONE (1 << 30)
2207#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
2208#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
2209#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
2210#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
2211#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
2212#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
2213#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
2214#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
2215#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
2216#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
2217#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
2218#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
2219#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
2220#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
2221#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
2222#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
2223#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
2224#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
2225#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
2226
2227/*
2228 * Computing GMCH M and N values for the Display Port link
2229 *
2230 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2231 *
2232 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2233 *
2234 * The GMCH value is used internally
2235 *
2236 * bytes_per_pixel is the number of bytes coming out of the plane,
2237 * which is after the LUTs, so we want the bytes for our color format.
2238 * For our current usage, this is always 3, one byte for R, G and B.
2239 */
2240#define _PIPEA_GMCH_DATA_M 0x70050
2241#define _PIPEB_GMCH_DATA_M 0x71050
2242
2243/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2244#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
2245#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
2246
2247#define PIPE_GMCH_DATA_M_MASK (0xffffff)
2248
2249#define _PIPEA_GMCH_DATA_N 0x70054
2250#define _PIPEB_GMCH_DATA_N 0x71054
2251#define PIPE_GMCH_DATA_N_MASK (0xffffff)
2252
2253/*
2254 * Computing Link M and N values for the Display Port link
2255 *
2256 * Link M / N = pixel_clock / ls_clk
2257 *
2258 * (the DP spec calls pixel_clock the 'strm_clk')
2259 *
2260 * The Link value is transmitted in the Main Stream
2261 * Attributes and VB-ID.
2262 */
2263
2264#define _PIPEA_DP_LINK_M 0x70060
2265#define _PIPEB_DP_LINK_M 0x71060
2266#define PIPEA_DP_LINK_M_MASK (0xffffff)
2267
2268#define _PIPEA_DP_LINK_N 0x70064
2269#define _PIPEB_DP_LINK_N 0x71064
2270#define PIPEA_DP_LINK_N_MASK (0xffffff)
2271
2272#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
2273#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
2274#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
2275#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
2276
2277/* Display & cursor control */
2278
2279/* Pipe A */
2280#define _PIPEADSL 0x70000
2281#define DSL_LINEMASK 0x00000fff
2282#define _PIPEACONF 0x70008
2283#define PIPECONF_ENABLE (1<<31)
2284#define PIPECONF_DISABLE 0
2285#define PIPECONF_DOUBLE_WIDE (1<<30)
2286#define I965_PIPECONF_ACTIVE (1<<30)
2287#define PIPECONF_SINGLE_WIDE 0
2288#define PIPECONF_PIPE_UNLOCKED 0
2289#define PIPECONF_PIPE_LOCKED (1<<25)
2290#define PIPECONF_PALETTE 0
2291#define PIPECONF_GAMMA (1<<24)
2292#define PIPECONF_FORCE_BORDER (1<<25)
2293#define PIPECONF_PROGRESSIVE (0 << 21)
2294#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2295#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
2296#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
2297#define PIPECONF_BPP_MASK (0x000000e0)
2298#define PIPECONF_BPP_8 (0<<5)
2299#define PIPECONF_BPP_10 (1<<5)
2300#define PIPECONF_BPP_6 (2<<5)
2301#define PIPECONF_BPP_12 (3<<5)
2302#define PIPECONF_DITHER_EN (1<<4)
2303#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
2304#define PIPECONF_DITHER_TYPE_SP (0<<2)
2305#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
2306#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
2307#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
2308#define _PIPEASTAT 0x70024
2309#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
2310#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
2311#define PIPE_CRC_DONE_ENABLE (1UL<<28)
2312#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
2313#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
2314#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
2315#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
2316#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
2317#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
2318#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
2319#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
2320#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
2321#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
2322#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
2323#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
2324#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
2325#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
2326#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
2327#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
2328#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
2329#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
2330#define PIPE_DPST_EVENT_STATUS (1UL<<7)
2331#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
2332#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
2333#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
2334#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
2335#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
2336#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
2337#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
2338#define PIPE_BPC_MASK (7 << 5) /* Ironlake */
2339#define PIPE_8BPC (0 << 5)
2340#define PIPE_10BPC (1 << 5)
2341#define PIPE_6BPC (2 << 5)
2342#define PIPE_12BPC (3 << 5)
2343
2344#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
2345#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
2346#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
2347#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
2348#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
2349#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
2350
2351#define DSPARB 0x70030
2352#define DSPARB_CSTART_MASK (0x7f << 7)
2353#define DSPARB_CSTART_SHIFT 7
2354#define DSPARB_BSTART_MASK (0x7f)
2355#define DSPARB_BSTART_SHIFT 0
2356#define DSPARB_BEND_SHIFT 9 /* on 855 */
2357#define DSPARB_AEND_SHIFT 0
2358
2359#define DSPFW1 0x70034
2360#define DSPFW_SR_SHIFT 23
2361#define DSPFW_SR_MASK (0x1ff<<23)
2362#define DSPFW_CURSORB_SHIFT 16
2363#define DSPFW_CURSORB_MASK (0x3f<<16)
2364#define DSPFW_PLANEB_SHIFT 8
2365#define DSPFW_PLANEB_MASK (0x7f<<8)
2366#define DSPFW_PLANEA_MASK (0x7f)
2367#define DSPFW2 0x70038
2368#define DSPFW_CURSORA_MASK 0x00003f00
2369#define DSPFW_CURSORA_SHIFT 8
2370#define DSPFW_PLANEC_MASK (0x7f)
2371#define DSPFW3 0x7003c
2372#define DSPFW_HPLL_SR_EN (1<<31)
2373#define DSPFW_CURSOR_SR_SHIFT 24
2374#define PINEVIEW_SELF_REFRESH_EN (1<<30)
2375#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
2376#define DSPFW_HPLL_CURSOR_SHIFT 16
2377#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
2378#define DSPFW_HPLL_SR_MASK (0x1ff)
2379
2380/* FIFO watermark sizes etc */
2381#define G4X_FIFO_LINE_SIZE 64
2382#define I915_FIFO_LINE_SIZE 64
2383#define I830_FIFO_LINE_SIZE 32
2384
2385#define G4X_FIFO_SIZE 127
2386#define I965_FIFO_SIZE 512
2387#define I945_FIFO_SIZE 127
2388#define I915_FIFO_SIZE 95
2389#define I855GM_FIFO_SIZE 127 /* In cachelines */
2390#define I830_FIFO_SIZE 95
2391
2392#define G4X_MAX_WM 0x3f
2393#define I915_MAX_WM 0x3f
2394
2395#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
2396#define PINEVIEW_FIFO_LINE_SIZE 64
2397#define PINEVIEW_MAX_WM 0x1ff
2398#define PINEVIEW_DFT_WM 0x3f
2399#define PINEVIEW_DFT_HPLLOFF_WM 0
2400#define PINEVIEW_GUARD_WM 10
2401#define PINEVIEW_CURSOR_FIFO 64
2402#define PINEVIEW_CURSOR_MAX_WM 0x3f
2403#define PINEVIEW_CURSOR_DFT_WM 0
2404#define PINEVIEW_CURSOR_GUARD_WM 5
2405
2406#define I965_CURSOR_FIFO 64
2407#define I965_CURSOR_MAX_WM 32
2408#define I965_CURSOR_DFT_WM 8
2409
2410/* define the Watermark register on Ironlake */
2411#define WM0_PIPEA_ILK 0x45100
2412#define WM0_PIPE_PLANE_MASK (0x7f<<16)
2413#define WM0_PIPE_PLANE_SHIFT 16
2414#define WM0_PIPE_SPRITE_MASK (0x3f<<8)
2415#define WM0_PIPE_SPRITE_SHIFT 8
2416#define WM0_PIPE_CURSOR_MASK (0x1f)
2417
2418#define WM0_PIPEB_ILK 0x45104
2419#define WM1_LP_ILK 0x45108
2420#define WM1_LP_SR_EN (1<<31)
2421#define WM1_LP_LATENCY_SHIFT 24
2422#define WM1_LP_LATENCY_MASK (0x7f<<24)
2423#define WM1_LP_FBC_MASK (0xf<<20)
2424#define WM1_LP_FBC_SHIFT 20
2425#define WM1_LP_SR_MASK (0x1ff<<8)
2426#define WM1_LP_SR_SHIFT 8
2427#define WM1_LP_CURSOR_MASK (0x3f)
2428#define WM2_LP_ILK 0x4510c
2429#define WM2_LP_EN (1<<31)
2430#define WM3_LP_ILK 0x45110
2431#define WM3_LP_EN (1<<31)
2432#define WM1S_LP_ILK 0x45120
2433#define WM1S_LP_EN (1<<31)
2434
2435/* Memory latency timer register */
2436#define MLTR_ILK 0x11222
2437#define MLTR_WM1_SHIFT 0
2438#define MLTR_WM2_SHIFT 8
2439/* the unit of memory self-refresh latency time is 0.5us */
2440#define ILK_SRLT_MASK 0x3f
2441#define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
2442#define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT)
2443#define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT)
2444
2445/* define the fifo size on Ironlake */
2446#define ILK_DISPLAY_FIFO 128
2447#define ILK_DISPLAY_MAXWM 64
2448#define ILK_DISPLAY_DFTWM 8
2449#define ILK_CURSOR_FIFO 32
2450#define ILK_CURSOR_MAXWM 16
2451#define ILK_CURSOR_DFTWM 8
2452
2453#define ILK_DISPLAY_SR_FIFO 512
2454#define ILK_DISPLAY_MAX_SRWM 0x1ff
2455#define ILK_DISPLAY_DFT_SRWM 0x3f
2456#define ILK_CURSOR_SR_FIFO 64
2457#define ILK_CURSOR_MAX_SRWM 0x3f
2458#define ILK_CURSOR_DFT_SRWM 8
2459
2460#define ILK_FIFO_LINE_SIZE 64
2461
2462/* define the WM info on Sandybridge */
2463#define SNB_DISPLAY_FIFO 128
2464#define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */
2465#define SNB_DISPLAY_DFTWM 8
2466#define SNB_CURSOR_FIFO 32
2467#define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */
2468#define SNB_CURSOR_DFTWM 8
2469
2470#define SNB_DISPLAY_SR_FIFO 512
2471#define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */
2472#define SNB_DISPLAY_DFT_SRWM 0x3f
2473#define SNB_CURSOR_SR_FIFO 64
2474#define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */
2475#define SNB_CURSOR_DFT_SRWM 8
2476
2477#define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */
2478
2479#define SNB_FIFO_LINE_SIZE 64
2480
2481
2482/* the address where we get all kinds of latency value */
2483#define SSKPD 0x5d10
2484#define SSKPD_WM_MASK 0x3f
2485#define SSKPD_WM0_SHIFT 0
2486#define SSKPD_WM1_SHIFT 8
2487#define SSKPD_WM2_SHIFT 16
2488#define SSKPD_WM3_SHIFT 24
2489
2490#define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
2491#define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT)
2492#define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT)
2493#define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT)
2494#define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT)
2495
2496/*
2497 * The two pipe frame counter registers are not synchronized, so
2498 * reading a stable value is somewhat tricky. The following code
2499 * should work:
2500 *
2501 * do {
2502 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2503 * PIPE_FRAME_HIGH_SHIFT;
2504 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2505 * PIPE_FRAME_LOW_SHIFT);
2506 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2507 * PIPE_FRAME_HIGH_SHIFT);
2508 * } while (high1 != high2);
2509 * frame = (high1 << 8) | low1;
2510 */
2511#define _PIPEAFRAMEHIGH 0x70040
2512#define PIPE_FRAME_HIGH_MASK 0x0000ffff
2513#define PIPE_FRAME_HIGH_SHIFT 0
2514#define _PIPEAFRAMEPIXEL 0x70044
2515#define PIPE_FRAME_LOW_MASK 0xff000000
2516#define PIPE_FRAME_LOW_SHIFT 24
2517#define PIPE_PIXEL_MASK 0x00ffffff
2518#define PIPE_PIXEL_SHIFT 0
2519/* GM45+ just has to be different */
2520#define _PIPEA_FRMCOUNT_GM45 0x70040
2521#define _PIPEA_FLIPCOUNT_GM45 0x70044
2522#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
2523
2524/* Cursor A & B regs */
2525#define _CURACNTR 0x70080
2526/* Old style CUR*CNTR flags (desktop 8xx) */
2527#define CURSOR_ENABLE 0x80000000
2528#define CURSOR_GAMMA_ENABLE 0x40000000
2529#define CURSOR_STRIDE_MASK 0x30000000
2530#define CURSOR_FORMAT_SHIFT 24
2531#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
2532#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
2533#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
2534#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
2535#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
2536#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
2537/* New style CUR*CNTR flags */
2538#define CURSOR_MODE 0x27
2539#define CURSOR_MODE_DISABLE 0x00
2540#define CURSOR_MODE_64_32B_AX 0x07
2541#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2542#define MCURSOR_PIPE_SELECT (1 << 28)
2543#define MCURSOR_PIPE_A 0x00
2544#define MCURSOR_PIPE_B (1 << 28)
2545#define MCURSOR_GAMMA_ENABLE (1 << 26)
2546#define _CURABASE 0x70084
2547#define _CURAPOS 0x70088
2548#define CURSOR_POS_MASK 0x007FF
2549#define CURSOR_POS_SIGN 0x8000
2550#define CURSOR_X_SHIFT 0
2551#define CURSOR_Y_SHIFT 16
2552#define CURSIZE 0x700a0
2553#define _CURBCNTR 0x700c0
2554#define _CURBBASE 0x700c4
2555#define _CURBPOS 0x700c8
2556
2557#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
2558#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
2559#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
2560
2561/* Display A control */
2562#define _DSPACNTR 0x70180
2563#define DISPLAY_PLANE_ENABLE (1<<31)
2564#define DISPLAY_PLANE_DISABLE 0
2565#define DISPPLANE_GAMMA_ENABLE (1<<30)
2566#define DISPPLANE_GAMMA_DISABLE 0
2567#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
2568#define DISPPLANE_8BPP (0x2<<26)
2569#define DISPPLANE_15_16BPP (0x4<<26)
2570#define DISPPLANE_16BPP (0x5<<26)
2571#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
2572#define DISPPLANE_32BPP (0x7<<26)
2573#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
2574#define DISPPLANE_STEREO_ENABLE (1<<25)
2575#define DISPPLANE_STEREO_DISABLE 0
2576#define DISPPLANE_SEL_PIPE_SHIFT 24
2577#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
2578#define DISPPLANE_SEL_PIPE_A 0
2579#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
2580#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2581#define DISPPLANE_SRC_KEY_DISABLE 0
2582#define DISPPLANE_LINE_DOUBLE (1<<20)
2583#define DISPPLANE_NO_LINE_DOUBLE 0
2584#define DISPPLANE_STEREO_POLARITY_FIRST 0
2585#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2586#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
2587#define DISPPLANE_TILED (1<<10)
2588#define _DSPAADDR 0x70184
2589#define _DSPASTRIDE 0x70188
2590#define _DSPAPOS 0x7018C /* reserved */
2591#define _DSPASIZE 0x70190
2592#define _DSPASURF 0x7019C /* 965+ only */
2593#define _DSPATILEOFF 0x701A4 /* 965+ only */
2594
2595#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
2596#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
2597#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
2598#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
2599#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
2600#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
2601#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
2602
2603/* VBIOS flags */
2604#define SWF00 0x71410
2605#define SWF01 0x71414
2606#define SWF02 0x71418
2607#define SWF03 0x7141c
2608#define SWF04 0x71420
2609#define SWF05 0x71424
2610#define SWF06 0x71428
2611#define SWF10 0x70410
2612#define SWF11 0x70414
2613#define SWF14 0x71420
2614#define SWF30 0x72414
2615#define SWF31 0x72418
2616#define SWF32 0x7241c
2617
2618/* Pipe B */
2619#define _PIPEBDSL 0x71000
2620#define _PIPEBCONF 0x71008
2621#define _PIPEBSTAT 0x71024
2622#define _PIPEBFRAMEHIGH 0x71040
2623#define _PIPEBFRAMEPIXEL 0x71044
2624#define _PIPEB_FRMCOUNT_GM45 0x71040
2625#define _PIPEB_FLIPCOUNT_GM45 0x71044
2626
2627
2628/* Display B control */
2629#define _DSPBCNTR 0x71180
2630#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2631#define DISPPLANE_ALPHA_TRANS_DISABLE 0
2632#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
2633#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2634#define _DSPBADDR 0x71184
2635#define _DSPBSTRIDE 0x71188
2636#define _DSPBPOS 0x7118C
2637#define _DSPBSIZE 0x71190
2638#define _DSPBSURF 0x7119C
2639#define _DSPBTILEOFF 0x711A4
2640
2641/* VBIOS regs */
2642#define VGACNTRL 0x71400
2643# define VGA_DISP_DISABLE (1 << 31)
2644# define VGA_2X_MODE (1 << 30)
2645# define VGA_PIPE_B_SELECT (1 << 29)
2646
2647/* Ironlake */
2648
2649#define CPU_VGACNTRL 0x41000
2650
2651#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
2652#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
2653#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
2654#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
2655#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
2656#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
2657#define DIGITAL_PORTA_NO_DETECT (0 << 0)
2658#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
2659#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
2660
2661/* refresh rate hardware control */
2662#define RR_HW_CTL 0x45300
2663#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
2664#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2665
2666#define FDI_PLL_BIOS_0 0x46000
2667#define FDI_PLL_FB_CLOCK_MASK 0xff
2668#define FDI_PLL_BIOS_1 0x46004
2669#define FDI_PLL_BIOS_2 0x46008
2670#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
2671#define DISPLAY_PORT_PLL_BIOS_1 0x46010
2672#define DISPLAY_PORT_PLL_BIOS_2 0x46014
2673
2674#define PCH_DSPCLK_GATE_D 0x42020
2675# define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
2676# define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
2677# define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
2678# define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
2679
2680#define PCH_3DCGDIS0 0x46020
2681# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
2682# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
2683
2684#define PCH_3DCGDIS1 0x46024
2685# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
2686
2687#define FDI_PLL_FREQ_CTL 0x46030
2688#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
2689#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
2690#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
2691
2692
2693#define _PIPEA_DATA_M1 0x60030
2694#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2695#define TU_SIZE_MASK 0x7e000000
2696#define PIPE_DATA_M1_OFFSET 0
2697#define _PIPEA_DATA_N1 0x60034
2698#define PIPE_DATA_N1_OFFSET 0
2699
2700#define _PIPEA_DATA_M2 0x60038
2701#define PIPE_DATA_M2_OFFSET 0
2702#define _PIPEA_DATA_N2 0x6003c
2703#define PIPE_DATA_N2_OFFSET 0
2704
2705#define _PIPEA_LINK_M1 0x60040
2706#define PIPE_LINK_M1_OFFSET 0
2707#define _PIPEA_LINK_N1 0x60044
2708#define PIPE_LINK_N1_OFFSET 0
2709
2710#define _PIPEA_LINK_M2 0x60048
2711#define PIPE_LINK_M2_OFFSET 0
2712#define _PIPEA_LINK_N2 0x6004c
2713#define PIPE_LINK_N2_OFFSET 0
2714
2715/* PIPEB timing regs are same start from 0x61000 */
2716
2717#define _PIPEB_DATA_M1 0x61030
2718#define _PIPEB_DATA_N1 0x61034
2719
2720#define _PIPEB_DATA_M2 0x61038
2721#define _PIPEB_DATA_N2 0x6103c
2722
2723#define _PIPEB_LINK_M1 0x61040
2724#define _PIPEB_LINK_N1 0x61044
2725
2726#define _PIPEB_LINK_M2 0x61048
2727#define _PIPEB_LINK_N2 0x6104c
2728
2729#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
2730#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
2731#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
2732#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
2733#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
2734#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
2735#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
2736#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
2737
2738/* CPU panel fitter */
2739/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
2740#define _PFA_CTL_1 0x68080
2741#define _PFB_CTL_1 0x68880
2742#define PF_ENABLE (1<<31)
2743#define PF_FILTER_MASK (3<<23)
2744#define PF_FILTER_PROGRAMMED (0<<23)
2745#define PF_FILTER_MED_3x3 (1<<23)
2746#define PF_FILTER_EDGE_ENHANCE (2<<23)
2747#define PF_FILTER_EDGE_SOFTEN (3<<23)
2748#define _PFA_WIN_SZ 0x68074
2749#define _PFB_WIN_SZ 0x68874
2750#define _PFA_WIN_POS 0x68070
2751#define _PFB_WIN_POS 0x68870
2752#define _PFA_VSCALE 0x68084
2753#define _PFB_VSCALE 0x68884
2754#define _PFA_HSCALE 0x68090
2755#define _PFB_HSCALE 0x68890
2756
2757#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
2758#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
2759#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
2760#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
2761#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
2762
2763/* legacy palette */
2764#define _LGC_PALETTE_A 0x4a000
2765#define _LGC_PALETTE_B 0x4a800
2766#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
2767
2768/* interrupts */
2769#define DE_MASTER_IRQ_CONTROL (1 << 31)
2770#define DE_SPRITEB_FLIP_DONE (1 << 29)
2771#define DE_SPRITEA_FLIP_DONE (1 << 28)
2772#define DE_PLANEB_FLIP_DONE (1 << 27)
2773#define DE_PLANEA_FLIP_DONE (1 << 26)
2774#define DE_PCU_EVENT (1 << 25)
2775#define DE_GTT_FAULT (1 << 24)
2776#define DE_POISON (1 << 23)
2777#define DE_PERFORM_COUNTER (1 << 22)
2778#define DE_PCH_EVENT (1 << 21)
2779#define DE_AUX_CHANNEL_A (1 << 20)
2780#define DE_DP_A_HOTPLUG (1 << 19)
2781#define DE_GSE (1 << 18)
2782#define DE_PIPEB_VBLANK (1 << 15)
2783#define DE_PIPEB_EVEN_FIELD (1 << 14)
2784#define DE_PIPEB_ODD_FIELD (1 << 13)
2785#define DE_PIPEB_LINE_COMPARE (1 << 12)
2786#define DE_PIPEB_VSYNC (1 << 11)
2787#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
2788#define DE_PIPEA_VBLANK (1 << 7)
2789#define DE_PIPEA_EVEN_FIELD (1 << 6)
2790#define DE_PIPEA_ODD_FIELD (1 << 5)
2791#define DE_PIPEA_LINE_COMPARE (1 << 4)
2792#define DE_PIPEA_VSYNC (1 << 3)
2793#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2794
2795/* More Ivybridge lolz */
2796#define DE_ERR_DEBUG_IVB (1<<30)
2797#define DE_GSE_IVB (1<<29)
2798#define DE_PCH_EVENT_IVB (1<<28)
2799#define DE_DP_A_HOTPLUG_IVB (1<<27)
2800#define DE_AUX_CHANNEL_A_IVB (1<<26)
2801#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
2802#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
2803#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
2804#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
2805#define DE_PIPEB_VBLANK_IVB (1<<5)
2806#define DE_PIPEA_VBLANK_IVB (1<<0)
2807
2808#define DEISR 0x44000
2809#define DEIMR 0x44004
2810#define DEIIR 0x44008
2811#define DEIER 0x4400c
2812
2813/* GT interrupt */
2814#define GT_PIPE_NOTIFY (1 << 4)
2815#define GT_SYNC_STATUS (1 << 2)
2816#define GT_USER_INTERRUPT (1 << 0)
2817#define GT_BSD_USER_INTERRUPT (1 << 5)
2818#define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
2819#define GT_BLT_USER_INTERRUPT (1 << 22)
2820
2821#define GTISR 0x44010
2822#define GTIMR 0x44014
2823#define GTIIR 0x44018
2824#define GTIER 0x4401c
2825
2826#define ILK_DISPLAY_CHICKEN2 0x42004
2827/* Required on all Ironlake and Sandybridge according to the B-Spec. */
2828#define ILK_ELPIN_409_SELECT (1 << 25)
2829#define ILK_DPARB_GATE (1<<22)
2830#define ILK_VSDPFD_FULL (1<<21)
2831#define ILK_DISPLAY_CHICKEN_FUSES 0x42014
2832#define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)
2833#define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)
2834#define ILK_DISPLAY_DEBUG_DISABLE (1<<29)
2835#define ILK_HDCP_DISABLE (1<<25)
2836#define ILK_eDP_A_DISABLE (1<<24)
2837#define ILK_DESKTOP (1<<23)
2838#define ILK_DSPCLK_GATE 0x42020
2839#define IVB_VRHUNIT_CLK_GATE (1<<28)
2840#define ILK_DPARB_CLK_GATE (1<<5)
2841#define ILK_DPFD_CLK_GATE (1<<7)
2842
2843/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
2844#define ILK_CLK_FBC (1<<7)
2845#define ILK_DPFC_DIS1 (1<<8)
2846#define ILK_DPFC_DIS2 (1<<9)
2847
2848#define DISP_ARB_CTL 0x45000
2849#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
2850#define DISP_FBC_WM_DIS (1<<15)
2851
2852/* PCH */
2853
2854/* south display engine interrupt */
2855#define SDE_AUDIO_POWER_D (1 << 27)
2856#define SDE_AUDIO_POWER_C (1 << 26)
2857#define SDE_AUDIO_POWER_B (1 << 25)
2858#define SDE_AUDIO_POWER_SHIFT (25)
2859#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
2860#define SDE_GMBUS (1 << 24)
2861#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
2862#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
2863#define SDE_AUDIO_HDCP_MASK (3 << 22)
2864#define SDE_AUDIO_TRANSB (1 << 21)
2865#define SDE_AUDIO_TRANSA (1 << 20)
2866#define SDE_AUDIO_TRANS_MASK (3 << 20)
2867#define SDE_POISON (1 << 19)
2868/* 18 reserved */
2869#define SDE_FDI_RXB (1 << 17)
2870#define SDE_FDI_RXA (1 << 16)
2871#define SDE_FDI_MASK (3 << 16)
2872#define SDE_AUXD (1 << 15)
2873#define SDE_AUXC (1 << 14)
2874#define SDE_AUXB (1 << 13)
2875#define SDE_AUX_MASK (7 << 13)
2876/* 12 reserved */
2877#define SDE_CRT_HOTPLUG (1 << 11)
2878#define SDE_PORTD_HOTPLUG (1 << 10)
2879#define SDE_PORTC_HOTPLUG (1 << 9)
2880#define SDE_PORTB_HOTPLUG (1 << 8)
2881#define SDE_SDVOB_HOTPLUG (1 << 6)
2882#define SDE_HOTPLUG_MASK (0xf << 8)
2883#define SDE_TRANSB_CRC_DONE (1 << 5)
2884#define SDE_TRANSB_CRC_ERR (1 << 4)
2885#define SDE_TRANSB_FIFO_UNDER (1 << 3)
2886#define SDE_TRANSA_CRC_DONE (1 << 2)
2887#define SDE_TRANSA_CRC_ERR (1 << 1)
2888#define SDE_TRANSA_FIFO_UNDER (1 << 0)
2889#define SDE_TRANS_MASK (0x3f)
2890/* CPT */
2891#define SDE_CRT_HOTPLUG_CPT (1 << 19)
2892#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
2893#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
2894#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
2895#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
2896 SDE_PORTD_HOTPLUG_CPT | \
2897 SDE_PORTC_HOTPLUG_CPT | \
2898 SDE_PORTB_HOTPLUG_CPT)
2899
2900#define SDEISR 0xc4000
2901#define SDEIMR 0xc4004
2902#define SDEIIR 0xc4008
2903#define SDEIER 0xc400c
2904
2905/* digital port hotplug */
2906#define PCH_PORT_HOTPLUG 0xc4030
2907#define PORTD_HOTPLUG_ENABLE (1 << 20)
2908#define PORTD_PULSE_DURATION_2ms (0)
2909#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
2910#define PORTD_PULSE_DURATION_6ms (2 << 18)
2911#define PORTD_PULSE_DURATION_100ms (3 << 18)
2912#define PORTD_HOTPLUG_NO_DETECT (0)
2913#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
2914#define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
2915#define PORTC_HOTPLUG_ENABLE (1 << 12)
2916#define PORTC_PULSE_DURATION_2ms (0)
2917#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
2918#define PORTC_PULSE_DURATION_6ms (2 << 10)
2919#define PORTC_PULSE_DURATION_100ms (3 << 10)
2920#define PORTC_HOTPLUG_NO_DETECT (0)
2921#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
2922#define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
2923#define PORTB_HOTPLUG_ENABLE (1 << 4)
2924#define PORTB_PULSE_DURATION_2ms (0)
2925#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
2926#define PORTB_PULSE_DURATION_6ms (2 << 2)
2927#define PORTB_PULSE_DURATION_100ms (3 << 2)
2928#define PORTB_HOTPLUG_NO_DETECT (0)
2929#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
2930#define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
2931
2932#define PCH_GPIOA 0xc5010
2933#define PCH_GPIOB 0xc5014
2934#define PCH_GPIOC 0xc5018
2935#define PCH_GPIOD 0xc501c
2936#define PCH_GPIOE 0xc5020
2937#define PCH_GPIOF 0xc5024
2938
2939#define PCH_GMBUS0 0xc5100
2940#define PCH_GMBUS1 0xc5104
2941#define PCH_GMBUS2 0xc5108
2942#define PCH_GMBUS3 0xc510c
2943#define PCH_GMBUS4 0xc5110
2944#define PCH_GMBUS5 0xc5120
2945
2946#define _PCH_DPLL_A 0xc6014
2947#define _PCH_DPLL_B 0xc6018
2948#define PCH_DPLL(pipe) _PIPE(pipe, _PCH_DPLL_A, _PCH_DPLL_B)
2949
2950#define _PCH_FPA0 0xc6040
2951#define FP_CB_TUNE (0x3<<22)
2952#define _PCH_FPA1 0xc6044
2953#define _PCH_FPB0 0xc6048
2954#define _PCH_FPB1 0xc604c
2955#define PCH_FP0(pipe) _PIPE(pipe, _PCH_FPA0, _PCH_FPB0)
2956#define PCH_FP1(pipe) _PIPE(pipe, _PCH_FPA1, _PCH_FPB1)
2957
2958#define PCH_DPLL_TEST 0xc606c
2959
2960#define PCH_DREF_CONTROL 0xC6200
2961#define DREF_CONTROL_MASK 0x7fc3
2962#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
2963#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
2964#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
2965#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
2966#define DREF_SSC_SOURCE_DISABLE (0<<11)
2967#define DREF_SSC_SOURCE_ENABLE (2<<11)
2968#define DREF_SSC_SOURCE_MASK (3<<11)
2969#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
2970#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
2971#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
2972#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
2973#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
2974#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
2975#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
2976#define DREF_SSC4_DOWNSPREAD (0<<6)
2977#define DREF_SSC4_CENTERSPREAD (1<<6)
2978#define DREF_SSC1_DISABLE (0<<1)
2979#define DREF_SSC1_ENABLE (1<<1)
2980#define DREF_SSC4_DISABLE (0)
2981#define DREF_SSC4_ENABLE (1)
2982
2983#define PCH_RAWCLK_FREQ 0xc6204
2984#define FDL_TP1_TIMER_SHIFT 12
2985#define FDL_TP1_TIMER_MASK (3<<12)
2986#define FDL_TP2_TIMER_SHIFT 10
2987#define FDL_TP2_TIMER_MASK (3<<10)
2988#define RAWCLK_FREQ_MASK 0x3ff
2989
2990#define PCH_DPLL_TMR_CFG 0xc6208
2991
2992#define PCH_SSC4_PARMS 0xc6210
2993#define PCH_SSC4_AUX_PARMS 0xc6214
2994
2995#define PCH_DPLL_SEL 0xc7000
2996#define TRANSA_DPLL_ENABLE (1<<3)
2997#define TRANSA_DPLLB_SEL (1<<0)
2998#define TRANSA_DPLLA_SEL 0
2999#define TRANSB_DPLL_ENABLE (1<<7)
3000#define TRANSB_DPLLB_SEL (1<<4)
3001#define TRANSB_DPLLA_SEL (0)
3002#define TRANSC_DPLL_ENABLE (1<<11)
3003#define TRANSC_DPLLB_SEL (1<<8)
3004#define TRANSC_DPLLA_SEL (0)
3005
3006/* transcoder */
3007
3008#define _TRANS_HTOTAL_A 0xe0000
3009#define TRANS_HTOTAL_SHIFT 16
3010#define TRANS_HACTIVE_SHIFT 0
3011#define _TRANS_HBLANK_A 0xe0004
3012#define TRANS_HBLANK_END_SHIFT 16
3013#define TRANS_HBLANK_START_SHIFT 0
3014#define _TRANS_HSYNC_A 0xe0008
3015#define TRANS_HSYNC_END_SHIFT 16
3016#define TRANS_HSYNC_START_SHIFT 0
3017#define _TRANS_VTOTAL_A 0xe000c
3018#define TRANS_VTOTAL_SHIFT 16
3019#define TRANS_VACTIVE_SHIFT 0
3020#define _TRANS_VBLANK_A 0xe0010
3021#define TRANS_VBLANK_END_SHIFT 16
3022#define TRANS_VBLANK_START_SHIFT 0
3023#define _TRANS_VSYNC_A 0xe0014
3024#define TRANS_VSYNC_END_SHIFT 16
3025#define TRANS_VSYNC_START_SHIFT 0
3026
3027#define _TRANSA_DATA_M1 0xe0030
3028#define _TRANSA_DATA_N1 0xe0034
3029#define _TRANSA_DATA_M2 0xe0038
3030#define _TRANSA_DATA_N2 0xe003c
3031#define _TRANSA_DP_LINK_M1 0xe0040
3032#define _TRANSA_DP_LINK_N1 0xe0044
3033#define _TRANSA_DP_LINK_M2 0xe0048
3034#define _TRANSA_DP_LINK_N2 0xe004c
3035
3036/* Per-transcoder DIP controls */
3037
3038#define _VIDEO_DIP_CTL_A 0xe0200
3039#define _VIDEO_DIP_DATA_A 0xe0208
3040#define _VIDEO_DIP_GCP_A 0xe0210
3041
3042#define _VIDEO_DIP_CTL_B 0xe1200
3043#define _VIDEO_DIP_DATA_B 0xe1208
3044#define _VIDEO_DIP_GCP_B 0xe1210
3045
3046#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
3047#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
3048#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
3049
3050#define _TRANS_HTOTAL_B 0xe1000
3051#define _TRANS_HBLANK_B 0xe1004
3052#define _TRANS_HSYNC_B 0xe1008
3053#define _TRANS_VTOTAL_B 0xe100c
3054#define _TRANS_VBLANK_B 0xe1010
3055#define _TRANS_VSYNC_B 0xe1014
3056
3057#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
3058#define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
3059#define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
3060#define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
3061#define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
3062#define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
3063
3064#define _TRANSB_DATA_M1 0xe1030
3065#define _TRANSB_DATA_N1 0xe1034
3066#define _TRANSB_DATA_M2 0xe1038
3067#define _TRANSB_DATA_N2 0xe103c
3068#define _TRANSB_DP_LINK_M1 0xe1040
3069#define _TRANSB_DP_LINK_N1 0xe1044
3070#define _TRANSB_DP_LINK_M2 0xe1048
3071#define _TRANSB_DP_LINK_N2 0xe104c
3072
3073#define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
3074#define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
3075#define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
3076#define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
3077#define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
3078#define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
3079#define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
3080#define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
3081
3082#define _TRANSACONF 0xf0008
3083#define _TRANSBCONF 0xf1008
3084#define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
3085#define TRANS_DISABLE (0<<31)
3086#define TRANS_ENABLE (1<<31)
3087#define TRANS_STATE_MASK (1<<30)
3088#define TRANS_STATE_DISABLE (0<<30)
3089#define TRANS_STATE_ENABLE (1<<30)
3090#define TRANS_FSYNC_DELAY_HB1 (0<<27)
3091#define TRANS_FSYNC_DELAY_HB2 (1<<27)
3092#define TRANS_FSYNC_DELAY_HB3 (2<<27)
3093#define TRANS_FSYNC_DELAY_HB4 (3<<27)
3094#define TRANS_DP_AUDIO_ONLY (1<<26)
3095#define TRANS_DP_VIDEO_AUDIO (0<<26)
3096#define TRANS_PROGRESSIVE (0<<21)
3097#define TRANS_8BPC (0<<5)
3098#define TRANS_10BPC (1<<5)
3099#define TRANS_6BPC (2<<5)
3100#define TRANS_12BPC (3<<5)
3101
3102#define _TRANSA_CHICKEN2 0xf0064
3103#define _TRANSB_CHICKEN2 0xf1064
3104#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3105#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
3106
3107#define SOUTH_CHICKEN1 0xc2000
3108#define FDIA_PHASE_SYNC_SHIFT_OVR 19
3109#define FDIA_PHASE_SYNC_SHIFT_EN 18
3110#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3111#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3112#define SOUTH_CHICKEN2 0xc2004
3113#define DPLS_EDP_PPS_FIX_DIS (1<<0)
3114
3115#define _FDI_RXA_CHICKEN 0xc200c
3116#define _FDI_RXB_CHICKEN 0xc2010
3117#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
3118#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
3119#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
3120
3121#define SOUTH_DSPCLK_GATE_D 0xc2020
3122#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
3123
3124/* CPU: FDI_TX */
3125#define _FDI_TXA_CTL 0x60100
3126#define _FDI_TXB_CTL 0x61100
3127#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
3128#define FDI_TX_DISABLE (0<<31)
3129#define FDI_TX_ENABLE (1<<31)
3130#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
3131#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
3132#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
3133#define FDI_LINK_TRAIN_NONE (3<<28)
3134#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
3135#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
3136#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
3137#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
3138#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
3139#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
3140#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
3141#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
3142/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
3143 SNB has different settings. */
3144/* SNB A-stepping */
3145#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3146#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3147#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3148#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3149/* SNB B-stepping */
3150#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
3151#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
3152#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
3153#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
3154#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
3155#define FDI_DP_PORT_WIDTH_X1 (0<<19)
3156#define FDI_DP_PORT_WIDTH_X2 (1<<19)
3157#define FDI_DP_PORT_WIDTH_X3 (2<<19)
3158#define FDI_DP_PORT_WIDTH_X4 (3<<19)
3159#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
3160/* Ironlake: hardwired to 1 */
3161#define FDI_TX_PLL_ENABLE (1<<14)
3162
3163/* Ivybridge has different bits for lolz */
3164#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
3165#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
3166#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
3167#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
3168
3169/* both Tx and Rx */
3170#define FDI_LINK_TRAIN_AUTO (1<<10)
3171#define FDI_SCRAMBLING_ENABLE (0<<7)
3172#define FDI_SCRAMBLING_DISABLE (1<<7)
3173
3174/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
3175#define _FDI_RXA_CTL 0xf000c
3176#define _FDI_RXB_CTL 0xf100c
3177#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
3178#define FDI_RX_ENABLE (1<<31)
3179/* train, dp width same as FDI_TX */
3180#define FDI_FS_ERRC_ENABLE (1<<27)
3181#define FDI_FE_ERRC_ENABLE (1<<26)
3182#define FDI_DP_PORT_WIDTH_X8 (7<<19)
3183#define FDI_8BPC (0<<16)
3184#define FDI_10BPC (1<<16)
3185#define FDI_6BPC (2<<16)
3186#define FDI_12BPC (3<<16)
3187#define FDI_LINK_REVERSE_OVERWRITE (1<<15)
3188#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
3189#define FDI_RX_PLL_ENABLE (1<<13)
3190#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
3191#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
3192#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
3193#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
3194#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
3195#define FDI_PCDCLK (1<<4)
3196/* CPT */
3197#define FDI_AUTO_TRAINING (1<<10)
3198#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
3199#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
3200#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
3201#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
3202#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
3203
3204#define _FDI_RXA_MISC 0xf0010
3205#define _FDI_RXB_MISC 0xf1010
3206#define _FDI_RXA_TUSIZE1 0xf0030
3207#define _FDI_RXA_TUSIZE2 0xf0038
3208#define _FDI_RXB_TUSIZE1 0xf1030
3209#define _FDI_RXB_TUSIZE2 0xf1038
3210#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
3211#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
3212#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
3213
3214/* FDI_RX interrupt register format */
3215#define FDI_RX_INTER_LANE_ALIGN (1<<10)
3216#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
3217#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
3218#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
3219#define FDI_RX_FS_CODE_ERR (1<<6)
3220#define FDI_RX_FE_CODE_ERR (1<<5)
3221#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
3222#define FDI_RX_HDCP_LINK_FAIL (1<<3)
3223#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
3224#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
3225#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
3226
3227#define _FDI_RXA_IIR 0xf0014
3228#define _FDI_RXA_IMR 0xf0018
3229#define _FDI_RXB_IIR 0xf1014
3230#define _FDI_RXB_IMR 0xf1018
3231#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
3232#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
3233
3234#define FDI_PLL_CTL_1 0xfe000
3235#define FDI_PLL_CTL_2 0xfe004
3236
3237/* CRT */
3238#define PCH_ADPA 0xe1100
3239#define ADPA_TRANS_SELECT_MASK (1<<30)
3240#define ADPA_TRANS_A_SELECT 0
3241#define ADPA_TRANS_B_SELECT (1<<30)
3242#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
3243#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
3244#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
3245#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3246#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
3247#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
3248#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
3249#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
3250#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
3251#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
3252#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
3253#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
3254#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
3255#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
3256#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
3257#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
3258#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
3259#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3260#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3261
3262/* or SDVOB */
3263#define HDMIB 0xe1140
3264#define PORT_ENABLE (1 << 31)
3265#define TRANSCODER_A (0)
3266#define TRANSCODER_B (1 << 30)
3267#define TRANSCODER(pipe) ((pipe) << 30)
3268#define TRANSCODER_MASK (1 << 30)
3269#define COLOR_FORMAT_8bpc (0)
3270#define COLOR_FORMAT_12bpc (3 << 26)
3271#define SDVOB_HOTPLUG_ENABLE (1 << 23)
3272#define SDVO_ENCODING (0)
3273#define TMDS_ENCODING (2 << 10)
3274#define NULL_PACKET_VSYNC_ENABLE (1 << 9)
3275/* CPT */
3276#define HDMI_MODE_SELECT (1 << 9)
3277#define DVI_MODE_SELECT (0)
3278#define SDVOB_BORDER_ENABLE (1 << 7)
3279#define AUDIO_ENABLE (1 << 6)
3280#define VSYNC_ACTIVE_HIGH (1 << 4)
3281#define HSYNC_ACTIVE_HIGH (1 << 3)
3282#define PORT_DETECTED (1 << 2)
3283
3284/* PCH SDVOB multiplex with HDMIB */
3285#define PCH_SDVOB HDMIB
3286
3287#define HDMIC 0xe1150
3288#define HDMID 0xe1160
3289
3290#define PCH_LVDS 0xe1180
3291#define LVDS_DETECTED (1 << 1)
3292
3293#define BLC_PWM_CPU_CTL2 0x48250
3294#define PWM_ENABLE (1 << 31)
3295#define PWM_PIPE_A (0 << 29)
3296#define PWM_PIPE_B (1 << 29)
3297#define BLC_PWM_CPU_CTL 0x48254
3298
3299#define BLC_PWM_PCH_CTL1 0xc8250
3300#define PWM_PCH_ENABLE (1 << 31)
3301#define PWM_POLARITY_ACTIVE_LOW (1 << 29)
3302#define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
3303#define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
3304#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
3305
3306#define BLC_PWM_PCH_CTL2 0xc8254
3307
3308#define PCH_PP_STATUS 0xc7200
3309#define PCH_PP_CONTROL 0xc7204
3310#define PANEL_UNLOCK_REGS (0xabcd << 16)
3311#define EDP_FORCE_VDD (1 << 3)
3312#define EDP_BLC_ENABLE (1 << 2)
3313#define PANEL_POWER_RESET (1 << 1)
3314#define PANEL_POWER_OFF (0 << 0)
3315#define PANEL_POWER_ON (1 << 0)
3316#define PCH_PP_ON_DELAYS 0xc7208
3317#define EDP_PANEL (1 << 30)
3318#define PCH_PP_OFF_DELAYS 0xc720c
3319#define PCH_PP_DIVISOR 0xc7210
3320
3321#define PCH_DP_B 0xe4100
3322#define PCH_DPB_AUX_CH_CTL 0xe4110
3323#define PCH_DPB_AUX_CH_DATA1 0xe4114
3324#define PCH_DPB_AUX_CH_DATA2 0xe4118
3325#define PCH_DPB_AUX_CH_DATA3 0xe411c
3326#define PCH_DPB_AUX_CH_DATA4 0xe4120
3327#define PCH_DPB_AUX_CH_DATA5 0xe4124
3328
3329#define PCH_DP_C 0xe4200
3330#define PCH_DPC_AUX_CH_CTL 0xe4210
3331#define PCH_DPC_AUX_CH_DATA1 0xe4214
3332#define PCH_DPC_AUX_CH_DATA2 0xe4218
3333#define PCH_DPC_AUX_CH_DATA3 0xe421c
3334#define PCH_DPC_AUX_CH_DATA4 0xe4220
3335#define PCH_DPC_AUX_CH_DATA5 0xe4224
3336
3337#define PCH_DP_D 0xe4300
3338#define PCH_DPD_AUX_CH_CTL 0xe4310
3339#define PCH_DPD_AUX_CH_DATA1 0xe4314
3340#define PCH_DPD_AUX_CH_DATA2 0xe4318
3341#define PCH_DPD_AUX_CH_DATA3 0xe431c
3342#define PCH_DPD_AUX_CH_DATA4 0xe4320
3343#define PCH_DPD_AUX_CH_DATA5 0xe4324
3344
3345/* CPT */
3346#define PORT_TRANS_A_SEL_CPT 0
3347#define PORT_TRANS_B_SEL_CPT (1<<29)
3348#define PORT_TRANS_C_SEL_CPT (2<<29)
3349#define PORT_TRANS_SEL_MASK (3<<29)
3350#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
3351
3352#define TRANS_DP_CTL_A 0xe0300
3353#define TRANS_DP_CTL_B 0xe1300
3354#define TRANS_DP_CTL_C 0xe2300
3355#define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
3356#define TRANS_DP_OUTPUT_ENABLE (1<<31)
3357#define TRANS_DP_PORT_SEL_B (0<<29)
3358#define TRANS_DP_PORT_SEL_C (1<<29)
3359#define TRANS_DP_PORT_SEL_D (2<<29)
3360#define TRANS_DP_PORT_SEL_NONE (3<<29)
3361#define TRANS_DP_PORT_SEL_MASK (3<<29)
3362#define TRANS_DP_AUDIO_ONLY (1<<26)
3363#define TRANS_DP_ENH_FRAMING (1<<18)
3364#define TRANS_DP_8BPC (0<<9)
3365#define TRANS_DP_10BPC (1<<9)
3366#define TRANS_DP_6BPC (2<<9)
3367#define TRANS_DP_12BPC (3<<9)
3368#define TRANS_DP_BPC_MASK (3<<9)
3369#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
3370#define TRANS_DP_VSYNC_ACTIVE_LOW 0
3371#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
3372#define TRANS_DP_HSYNC_ACTIVE_LOW 0
3373#define TRANS_DP_SYNC_MASK (3<<3)
3374
3375/* SNB eDP training params */
3376/* SNB A-stepping */
3377#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3378#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3379#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3380#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3381/* SNB B-stepping */
3382#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
3383#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
3384#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
3385#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
3386#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
3387#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
3388
3389#define FORCEWAKE 0xA18C
3390#define FORCEWAKE_ACK 0x130090
3391
3392#define GT_FIFO_FREE_ENTRIES 0x120008
3393#define GT_FIFO_NUM_RESERVED_ENTRIES 20
3394
3395#define GEN6_RPNSWREQ 0xA008
3396#define GEN6_TURBO_DISABLE (1<<31)
3397#define GEN6_FREQUENCY(x) ((x)<<25)
3398#define GEN6_OFFSET(x) ((x)<<19)
3399#define GEN6_AGGRESSIVE_TURBO (0<<15)
3400#define GEN6_RC_VIDEO_FREQ 0xA00C
3401#define GEN6_RC_CONTROL 0xA090
3402#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
3403#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
3404#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
3405#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
3406#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
3407#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
3408#define GEN6_RC_CTL_HW_ENABLE (1<<31)
3409#define GEN6_RP_DOWN_TIMEOUT 0xA010
3410#define GEN6_RP_INTERRUPT_LIMITS 0xA014
3411#define GEN6_RPSTAT1 0xA01C
3412#define GEN6_CAGF_SHIFT 8
3413#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
3414#define GEN6_RP_CONTROL 0xA024
3415#define GEN6_RP_MEDIA_TURBO (1<<11)
3416#define GEN6_RP_USE_NORMAL_FREQ (1<<9)
3417#define GEN6_RP_MEDIA_IS_GFX (1<<8)
3418#define GEN6_RP_ENABLE (1<<7)
3419#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
3420#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
3421#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
3422#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
3423#define GEN6_RP_UP_THRESHOLD 0xA02C
3424#define GEN6_RP_DOWN_THRESHOLD 0xA030
3425#define GEN6_RP_CUR_UP_EI 0xA050
3426#define GEN6_CURICONT_MASK 0xffffff
3427#define GEN6_RP_CUR_UP 0xA054
3428#define GEN6_CURBSYTAVG_MASK 0xffffff
3429#define GEN6_RP_PREV_UP 0xA058
3430#define GEN6_RP_CUR_DOWN_EI 0xA05C
3431#define GEN6_CURIAVG_MASK 0xffffff
3432#define GEN6_RP_CUR_DOWN 0xA060
3433#define GEN6_RP_PREV_DOWN 0xA064
3434#define GEN6_RP_UP_EI 0xA068
3435#define GEN6_RP_DOWN_EI 0xA06C
3436#define GEN6_RP_IDLE_HYSTERSIS 0xA070
3437#define GEN6_RC_STATE 0xA094
3438#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
3439#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
3440#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
3441#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
3442#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
3443#define GEN6_RC_SLEEP 0xA0B0
3444#define GEN6_RC1e_THRESHOLD 0xA0B4
3445#define GEN6_RC6_THRESHOLD 0xA0B8
3446#define GEN6_RC6p_THRESHOLD 0xA0BC
3447#define GEN6_RC6pp_THRESHOLD 0xA0C0
3448#define GEN6_PMINTRMSK 0xA168
3449
3450#define GEN6_PMISR 0x44020
3451#define GEN6_PMIMR 0x44024 /* rps_lock */
3452#define GEN6_PMIIR 0x44028
3453#define GEN6_PMIER 0x4402C
3454#define GEN6_PM_MBOX_EVENT (1<<25)
3455#define GEN6_PM_THERMAL_EVENT (1<<24)
3456#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
3457#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
3458#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
3459#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
3460#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
3461#define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
3462 GEN6_PM_RP_DOWN_THRESHOLD | \
3463 GEN6_PM_RP_DOWN_TIMEOUT)
3464
3465#define GEN6_PCODE_MAILBOX 0x138124
3466#define GEN6_PCODE_READY (1<<31)
3467#define GEN6_READ_OC_PARAMS 0xc
3468#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
3469#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
3470#define GEN6_PCODE_DATA 0x138128
3471#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
3472
3473#endif /* _I915_REG_H_ */
1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
28#include "i915_reg_defs.h"
29#include "display/intel_display_reg_defs.h"
30
31/**
32 * DOC: The i915 register macro definition style guide
33 *
34 * Follow the style described here for new macros, and while changing existing
35 * macros. Do **not** mass change existing definitions just to update the style.
36 *
37 * File Layout
38 * ~~~~~~~~~~~
39 *
40 * Keep helper macros near the top. For example, _PIPE() and friends.
41 *
42 * Prefix macros that generally should not be used outside of this file with
43 * underscore '_'. For example, _PIPE() and friends, single instances of
44 * registers that are defined solely for the use by function-like macros.
45 *
46 * Avoid using the underscore prefixed macros outside of this file. There are
47 * exceptions, but keep them to a minimum.
48 *
49 * There are two basic types of register definitions: Single registers and
50 * register groups. Register groups are registers which have two or more
51 * instances, for example one per pipe, port, transcoder, etc. Register groups
52 * should be defined using function-like macros.
53 *
54 * For single registers, define the register offset first, followed by register
55 * contents.
56 *
57 * For register groups, define the register instance offsets first, prefixed
58 * with underscore, followed by a function-like macro choosing the right
59 * instance based on the parameter, followed by register contents.
60 *
61 * Define the register contents (i.e. bit and bit field macros) from most
62 * significant to least significant bit. Indent the register content macros
63 * using two extra spaces between ``#define`` and the macro name.
64 *
65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
66 * using ``REG_FIELD_PREP(mask, value)``. This will define the values already
67 * shifted in place, so they can be directly OR'd together. For convenience,
68 * function-like macros may be used to define bit fields, but do note that the
69 * macros may be needed to read as well as write the register contents.
70 *
71 * Define bits using ``REG_BIT(N)``. Do **not** add ``_BIT`` suffix to the name.
72 *
73 * Group the register and its contents together without blank lines, separate
74 * from other registers and their contents with one blank line.
75 *
76 * Indent macro values from macro names using TABs. Align values vertically. Use
77 * braces in macro values as needed to avoid unintended precedence after macro
78 * substitution. Use spaces in macro values according to kernel coding
79 * style. Use lower case in hexadecimal values.
80 *
81 * Naming
82 * ~~~~~~
83 *
84 * Try to name registers according to the specs. If the register name changes in
85 * the specs from platform to another, stick to the original name.
86 *
87 * Try to re-use existing register macro definitions. Only add new macros for
88 * new register offsets, or when the register contents have changed enough to
89 * warrant a full redefinition.
90 *
91 * When a register macro changes for a new platform, prefix the new macro using
92 * the platform acronym or generation. For example, ``SKL_`` or ``GEN8_``. The
93 * prefix signifies the start platform/generation using the register.
94 *
95 * When a bit (field) macro changes or gets added for a new platform, while
96 * retaining the existing register macro, add a platform acronym or generation
97 * suffix to the name. For example, ``_SKL`` or ``_GEN8``.
98 *
99 * Examples
100 * ~~~~~~~~
101 *
102 * (Note that the values in the example are indented using spaces instead of
103 * TABs to avoid misalignment in generated documentation. Use TABs in the
104 * definitions.)::
105 *
106 * #define _FOO_A 0xf000
107 * #define _FOO_B 0xf001
108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
109 * #define FOO_ENABLE REG_BIT(31)
110 * #define FOO_MODE_MASK REG_GENMASK(19, 16)
111 * #define FOO_MODE_BAR REG_FIELD_PREP(FOO_MODE_MASK, 0)
112 * #define FOO_MODE_BAZ REG_FIELD_PREP(FOO_MODE_MASK, 1)
113 * #define FOO_MODE_QUX_SNB REG_FIELD_PREP(FOO_MODE_MASK, 2)
114 *
115 * #define BAR _MMIO(0xb000)
116 * #define GEN8_BAR _MMIO(0xb888)
117 */
118
119#define GU_CNTL_PROTECTED _MMIO(0x10100C)
120#define DEPRESENT REG_BIT(9)
121
122#define GU_CNTL _MMIO(0x101010)
123#define LMEM_INIT REG_BIT(7)
124#define DRIVERFLR REG_BIT(31)
125#define GU_DEBUG _MMIO(0x101018)
126#define DRIVERFLR_STATUS REG_BIT(31)
127
128#define GEN6_STOLEN_RESERVED _MMIO(0x1082C0)
129#define GEN6_STOLEN_RESERVED_ADDR_MASK (0xFFF << 20)
130#define GEN7_STOLEN_RESERVED_ADDR_MASK (0x3FFF << 18)
131#define GEN6_STOLEN_RESERVED_SIZE_MASK (3 << 4)
132#define GEN6_STOLEN_RESERVED_1M (0 << 4)
133#define GEN6_STOLEN_RESERVED_512K (1 << 4)
134#define GEN6_STOLEN_RESERVED_256K (2 << 4)
135#define GEN6_STOLEN_RESERVED_128K (3 << 4)
136#define GEN7_STOLEN_RESERVED_SIZE_MASK (1 << 5)
137#define GEN7_STOLEN_RESERVED_1M (0 << 5)
138#define GEN7_STOLEN_RESERVED_256K (1 << 5)
139#define GEN8_STOLEN_RESERVED_SIZE_MASK (3 << 7)
140#define GEN8_STOLEN_RESERVED_1M (0 << 7)
141#define GEN8_STOLEN_RESERVED_2M (1 << 7)
142#define GEN8_STOLEN_RESERVED_4M (2 << 7)
143#define GEN8_STOLEN_RESERVED_8M (3 << 7)
144#define GEN6_STOLEN_RESERVED_ENABLE (1 << 0)
145#define GEN11_STOLEN_RESERVED_ADDR_MASK (0xFFFFFFFFFFFULL << 20)
146
147#define _VGA_MSR_WRITE _MMIO(0x3c2)
148
149#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
150#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
151#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
152
153/*
154 * Reset registers
155 */
156#define DEBUG_RESET_I830 _MMIO(0x6070)
157#define DEBUG_RESET_FULL (1 << 7)
158#define DEBUG_RESET_RENDER (1 << 8)
159#define DEBUG_RESET_DISPLAY (1 << 9)
160
161/*
162 * IOSF sideband
163 */
164#define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
165#define IOSF_DEVFN_SHIFT 24
166#define IOSF_OPCODE_SHIFT 16
167#define IOSF_PORT_SHIFT 8
168#define IOSF_BYTE_ENABLES_SHIFT 4
169#define IOSF_BAR_SHIFT 1
170#define IOSF_SB_BUSY (1 << 0)
171#define IOSF_PORT_BUNIT 0x03
172#define IOSF_PORT_PUNIT 0x04
173#define IOSF_PORT_NC 0x11
174#define IOSF_PORT_DPIO 0x12
175#define IOSF_PORT_GPIO_NC 0x13
176#define IOSF_PORT_CCK 0x14
177#define IOSF_PORT_DPIO_2 0x1a
178#define IOSF_PORT_FLISDSI 0x1b
179#define IOSF_PORT_GPIO_SC 0x48
180#define IOSF_PORT_GPIO_SUS 0xa8
181#define IOSF_PORT_CCU 0xa9
182#define CHV_IOSF_PORT_GPIO_N 0x13
183#define CHV_IOSF_PORT_GPIO_SE 0x48
184#define CHV_IOSF_PORT_GPIO_E 0xa8
185#define CHV_IOSF_PORT_GPIO_SW 0xb2
186#define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
187#define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
188
189/* DPIO registers */
190#define DPIO_DEVFN 0
191
192#define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
193#define DPIO_MODSEL1 (1 << 3) /* if ref clk b == 27 */
194#define DPIO_MODSEL0 (1 << 2) /* if ref clk a == 27 */
195#define DPIO_SFR_BYPASS (1 << 1)
196#define DPIO_CMNRST (1 << 0)
197
198/*
199 * Per pipe/PLL DPIO regs
200 */
201#define _VLV_PLL_DW3_CH0 0x800c
202#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
203#define DPIO_POST_DIV_DAC 0
204#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
205#define DPIO_POST_DIV_LVDS1 2
206#define DPIO_POST_DIV_LVDS2 3
207#define DPIO_K_SHIFT (24) /* 4 bits */
208#define DPIO_P1_SHIFT (21) /* 3 bits */
209#define DPIO_P2_SHIFT (16) /* 5 bits */
210#define DPIO_N_SHIFT (12) /* 4 bits */
211#define DPIO_ENABLE_CALIBRATION (1 << 11)
212#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
213#define DPIO_M2DIV_MASK 0xff
214#define _VLV_PLL_DW3_CH1 0x802c
215#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
216
217#define _VLV_PLL_DW5_CH0 0x8014
218#define DPIO_REFSEL_OVERRIDE 27
219#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
220#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
221#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
222#define DPIO_PLL_REFCLK_SEL_MASK 3
223#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
224#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
225#define _VLV_PLL_DW5_CH1 0x8034
226#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
227
228#define _VLV_PLL_DW7_CH0 0x801c
229#define _VLV_PLL_DW7_CH1 0x803c
230#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
231
232#define _VLV_PLL_DW8_CH0 0x8040
233#define _VLV_PLL_DW8_CH1 0x8060
234#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
235
236#define VLV_PLL_DW9_BCAST 0xc044
237#define _VLV_PLL_DW9_CH0 0x8044
238#define _VLV_PLL_DW9_CH1 0x8064
239#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
240
241#define _VLV_PLL_DW10_CH0 0x8048
242#define _VLV_PLL_DW10_CH1 0x8068
243#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
244
245#define _VLV_PLL_DW11_CH0 0x804c
246#define _VLV_PLL_DW11_CH1 0x806c
247#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
248
249/* Spec for ref block start counts at DW10 */
250#define VLV_REF_DW13 0x80ac
251
252#define VLV_CMN_DW0 0x8100
253
254/*
255 * Per DDI channel DPIO regs
256 */
257
258#define _VLV_PCS_DW0_CH0 0x8200
259#define _VLV_PCS_DW0_CH1 0x8400
260#define DPIO_PCS_TX_LANE2_RESET (1 << 16)
261#define DPIO_PCS_TX_LANE1_RESET (1 << 7)
262#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4)
263#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3)
264#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
265
266#define _VLV_PCS01_DW0_CH0 0x200
267#define _VLV_PCS23_DW0_CH0 0x400
268#define _VLV_PCS01_DW0_CH1 0x2600
269#define _VLV_PCS23_DW0_CH1 0x2800
270#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1)
271#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1)
272
273#define _VLV_PCS_DW1_CH0 0x8204
274#define _VLV_PCS_DW1_CH1 0x8404
275#define CHV_PCS_REQ_SOFTRESET_EN (1 << 23)
276#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22)
277#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21)
278#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
279#define DPIO_PCS_CLK_SOFT_RESET (1 << 5)
280#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
281
282#define _VLV_PCS01_DW1_CH0 0x204
283#define _VLV_PCS23_DW1_CH0 0x404
284#define _VLV_PCS01_DW1_CH1 0x2604
285#define _VLV_PCS23_DW1_CH1 0x2804
286#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1)
287#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1)
288
289#define _VLV_PCS_DW8_CH0 0x8220
290#define _VLV_PCS_DW8_CH1 0x8420
291#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20)
292#define CHV_PCS_USEDCLKCHANNEL (1 << 21)
293#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
294
295#define _VLV_PCS01_DW8_CH0 0x0220
296#define _VLV_PCS23_DW8_CH0 0x0420
297#define _VLV_PCS01_DW8_CH1 0x2620
298#define _VLV_PCS23_DW8_CH1 0x2820
299#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
300#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
301
302#define _VLV_PCS_DW9_CH0 0x8224
303#define _VLV_PCS_DW9_CH1 0x8424
304#define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13)
305#define DPIO_PCS_TX2MARGIN_000 (0 << 13)
306#define DPIO_PCS_TX2MARGIN_101 (1 << 13)
307#define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10)
308#define DPIO_PCS_TX1MARGIN_000 (0 << 10)
309#define DPIO_PCS_TX1MARGIN_101 (1 << 10)
310#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
311
312#define _VLV_PCS01_DW9_CH0 0x224
313#define _VLV_PCS23_DW9_CH0 0x424
314#define _VLV_PCS01_DW9_CH1 0x2624
315#define _VLV_PCS23_DW9_CH1 0x2824
316#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1)
317#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1)
318
319#define _CHV_PCS_DW10_CH0 0x8228
320#define _CHV_PCS_DW10_CH1 0x8428
321#define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30)
322#define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31)
323#define DPIO_PCS_TX2DEEMP_MASK (0xf << 24)
324#define DPIO_PCS_TX2DEEMP_9P5 (0 << 24)
325#define DPIO_PCS_TX2DEEMP_6P0 (2 << 24)
326#define DPIO_PCS_TX1DEEMP_MASK (0xf << 16)
327#define DPIO_PCS_TX1DEEMP_9P5 (0 << 16)
328#define DPIO_PCS_TX1DEEMP_6P0 (2 << 16)
329#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1)
330
331#define _VLV_PCS01_DW10_CH0 0x0228
332#define _VLV_PCS23_DW10_CH0 0x0428
333#define _VLV_PCS01_DW10_CH1 0x2628
334#define _VLV_PCS23_DW10_CH1 0x2828
335#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1)
336#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1)
337
338#define _VLV_PCS_DW11_CH0 0x822c
339#define _VLV_PCS_DW11_CH1 0x842c
340#define DPIO_TX2_STAGGER_MASK(x) ((x) << 24)
341#define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3)
342#define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1)
343#define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0)
344#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
345
346#define _VLV_PCS01_DW11_CH0 0x022c
347#define _VLV_PCS23_DW11_CH0 0x042c
348#define _VLV_PCS01_DW11_CH1 0x262c
349#define _VLV_PCS23_DW11_CH1 0x282c
350#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1)
351#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1)
352
353#define _VLV_PCS01_DW12_CH0 0x0230
354#define _VLV_PCS23_DW12_CH0 0x0430
355#define _VLV_PCS01_DW12_CH1 0x2630
356#define _VLV_PCS23_DW12_CH1 0x2830
357#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1)
358#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1)
359
360#define _VLV_PCS_DW12_CH0 0x8230
361#define _VLV_PCS_DW12_CH1 0x8430
362#define DPIO_TX2_STAGGER_MULT(x) ((x) << 20)
363#define DPIO_TX1_STAGGER_MULT(x) ((x) << 16)
364#define DPIO_TX1_STAGGER_MASK(x) ((x) << 8)
365#define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6)
366#define DPIO_LANESTAGGER_STRAP(x) ((x) << 0)
367#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
368
369#define _VLV_PCS_DW14_CH0 0x8238
370#define _VLV_PCS_DW14_CH1 0x8438
371#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
372
373#define _VLV_PCS_DW23_CH0 0x825c
374#define _VLV_PCS_DW23_CH1 0x845c
375#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
376
377#define _VLV_TX_DW2_CH0 0x8288
378#define _VLV_TX_DW2_CH1 0x8488
379#define DPIO_SWING_MARGIN000_SHIFT 16
380#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT)
381#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8
382#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
383
384#define _VLV_TX_DW3_CH0 0x828c
385#define _VLV_TX_DW3_CH1 0x848c
386/* The following bit for CHV phy */
387#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27)
388#define DPIO_SWING_MARGIN101_SHIFT 16
389#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT)
390#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
391
392#define _VLV_TX_DW4_CH0 0x8290
393#define _VLV_TX_DW4_CH1 0x8490
394#define DPIO_SWING_DEEMPH9P5_SHIFT 24
395#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
396#define DPIO_SWING_DEEMPH6P0_SHIFT 16
397#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
398#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
399
400#define _VLV_TX3_DW4_CH0 0x690
401#define _VLV_TX3_DW4_CH1 0x2a90
402#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
403
404#define _VLV_TX_DW5_CH0 0x8294
405#define _VLV_TX_DW5_CH1 0x8494
406#define DPIO_TX_OCALINIT_EN (1 << 31)
407#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
408
409#define _VLV_TX_DW11_CH0 0x82ac
410#define _VLV_TX_DW11_CH1 0x84ac
411#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
412
413#define _VLV_TX_DW14_CH0 0x82b8
414#define _VLV_TX_DW14_CH1 0x84b8
415#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
416
417/* CHV dpPhy registers */
418#define _CHV_PLL_DW0_CH0 0x8000
419#define _CHV_PLL_DW0_CH1 0x8180
420#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1)
421
422#define _CHV_PLL_DW1_CH0 0x8004
423#define _CHV_PLL_DW1_CH1 0x8184
424#define DPIO_CHV_N_DIV_SHIFT 8
425#define DPIO_CHV_M1_DIV_BY_2 (0 << 0)
426#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1)
427
428#define _CHV_PLL_DW2_CH0 0x8008
429#define _CHV_PLL_DW2_CH1 0x8188
430#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1)
431
432#define _CHV_PLL_DW3_CH0 0x800c
433#define _CHV_PLL_DW3_CH1 0x818c
434#define DPIO_CHV_FRAC_DIV_EN (1 << 16)
435#define DPIO_CHV_FIRST_MOD (0 << 8)
436#define DPIO_CHV_SECOND_MOD (1 << 8)
437#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0
438#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0)
439#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1)
440
441#define _CHV_PLL_DW6_CH0 0x8018
442#define _CHV_PLL_DW6_CH1 0x8198
443#define DPIO_CHV_GAIN_CTRL_SHIFT 16
444#define DPIO_CHV_INT_COEFF_SHIFT 8
445#define DPIO_CHV_PROP_COEFF_SHIFT 0
446#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1)
447
448#define _CHV_PLL_DW8_CH0 0x8020
449#define _CHV_PLL_DW8_CH1 0x81A0
450#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
451#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0)
452#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1)
453
454#define _CHV_PLL_DW9_CH0 0x8024
455#define _CHV_PLL_DW9_CH1 0x81A4
456#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */
457#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1)
458#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */
459#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1)
460
461#define _CHV_CMN_DW0_CH0 0x8100
462#define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19
463#define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18
464#define DPIO_ALLDL_POWERDOWN (1 << 1)
465#define DPIO_ANYDL_POWERDOWN (1 << 0)
466
467#define _CHV_CMN_DW5_CH0 0x8114
468#define CHV_BUFRIGHTENA1_DISABLE (0 << 20)
469#define CHV_BUFRIGHTENA1_NORMAL (1 << 20)
470#define CHV_BUFRIGHTENA1_FORCE (3 << 20)
471#define CHV_BUFRIGHTENA1_MASK (3 << 20)
472#define CHV_BUFLEFTENA1_DISABLE (0 << 22)
473#define CHV_BUFLEFTENA1_NORMAL (1 << 22)
474#define CHV_BUFLEFTENA1_FORCE (3 << 22)
475#define CHV_BUFLEFTENA1_MASK (3 << 22)
476
477#define _CHV_CMN_DW13_CH0 0x8134
478#define _CHV_CMN_DW0_CH1 0x8080
479#define DPIO_CHV_S1_DIV_SHIFT 21
480#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */
481#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */
482#define DPIO_CHV_K_DIV_SHIFT 4
483#define DPIO_PLL_FREQLOCK (1 << 1)
484#define DPIO_PLL_LOCK (1 << 0)
485#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1)
486
487#define _CHV_CMN_DW14_CH0 0x8138
488#define _CHV_CMN_DW1_CH1 0x8084
489#define DPIO_AFC_RECAL (1 << 14)
490#define DPIO_DCLKP_EN (1 << 13)
491#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */
492#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */
493#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */
494#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */
495#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */
496#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */
497#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */
498#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */
499#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1)
500
501#define _CHV_CMN_DW19_CH0 0x814c
502#define _CHV_CMN_DW6_CH1 0x8098
503#define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */
504#define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */
505#define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */
506#define CHV_CMN_USEDCLKCHANNEL (1 << 13)
507
508#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1)
509
510#define CHV_CMN_DW28 0x8170
511#define DPIO_CL1POWERDOWNEN (1 << 23)
512#define DPIO_DYNPWRDOWNEN_CH0 (1 << 22)
513#define DPIO_SUS_CLK_CONFIG_ON (0 << 0)
514#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0)
515#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0)
516#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0)
517
518#define CHV_CMN_DW30 0x8178
519#define DPIO_CL2_LDOFUSE_PWRENB (1 << 6)
520#define DPIO_LRC_BYPASS (1 << 3)
521
522#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
523 (lane) * 0x200 + (offset))
524
525#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
526#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
527#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
528#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
529#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
530#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
531#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
532#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
533#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
534#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
535#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
536#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
537#define DPIO_FRC_LATENCY_SHFIT 8
538#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
539#define DPIO_UPAR_SHIFT 30
540
541/* BXT PHY registers */
542#define _BXT_PHY0_BASE 0x6C000
543#define _BXT_PHY1_BASE 0x162000
544#define _BXT_PHY2_BASE 0x163000
545#define BXT_PHY_BASE(phy) \
546 _PICK_EVEN_2RANGES(phy, 1, \
547 _BXT_PHY0_BASE, _BXT_PHY0_BASE, \
548 _BXT_PHY1_BASE, _BXT_PHY2_BASE)
549
550#define _BXT_PHY(phy, reg) \
551 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
552
553#define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
554 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
555 (reg_ch1) - _BXT_PHY0_BASE))
556#define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
557 _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
558
559#define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090)
560#define MIPIO_RST_CTRL (1 << 2)
561
562#define _BXT_PHY_CTL_DDI_A 0x64C00
563#define _BXT_PHY_CTL_DDI_B 0x64C10
564#define _BXT_PHY_CTL_DDI_C 0x64C20
565#define BXT_PHY_CMNLANE_POWERDOWN_ACK (1 << 10)
566#define BXT_PHY_LANE_POWERDOWN_ACK (1 << 9)
567#define BXT_PHY_LANE_ENABLED (1 << 8)
568#define BXT_PHY_CTL(port) _MMIO_PORT(port, _BXT_PHY_CTL_DDI_A, \
569 _BXT_PHY_CTL_DDI_B)
570
571#define _PHY_CTL_FAMILY_DDI 0x64C90
572#define _PHY_CTL_FAMILY_EDP 0x64C80
573#define _PHY_CTL_FAMILY_DDI_C 0x64CA0
574#define COMMON_RESET_DIS (1 << 31)
575#define BXT_PHY_CTL_FAMILY(phy) \
576 _MMIO(_PICK_EVEN_2RANGES(phy, 1, \
577 _PHY_CTL_FAMILY_DDI, _PHY_CTL_FAMILY_DDI, \
578 _PHY_CTL_FAMILY_EDP, _PHY_CTL_FAMILY_DDI_C))
579
580/* BXT PHY PLL registers */
581#define _PORT_PLL_A 0x46074
582#define _PORT_PLL_B 0x46078
583#define _PORT_PLL_C 0x4607c
584#define PORT_PLL_ENABLE REG_BIT(31)
585#define PORT_PLL_LOCK REG_BIT(30)
586#define PORT_PLL_REF_SEL REG_BIT(27)
587#define PORT_PLL_POWER_ENABLE REG_BIT(26)
588#define PORT_PLL_POWER_STATE REG_BIT(25)
589#define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B)
590
591#define _PORT_PLL_EBB_0_A 0x162034
592#define _PORT_PLL_EBB_0_B 0x6C034
593#define _PORT_PLL_EBB_0_C 0x6C340
594#define PORT_PLL_P1_MASK REG_GENMASK(15, 13)
595#define PORT_PLL_P1(p1) REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1))
596#define PORT_PLL_P2_MASK REG_GENMASK(12, 8)
597#define PORT_PLL_P2(p2) REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2))
598#define BXT_PORT_PLL_EBB_0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
599 _PORT_PLL_EBB_0_B, \
600 _PORT_PLL_EBB_0_C)
601
602#define _PORT_PLL_EBB_4_A 0x162038
603#define _PORT_PLL_EBB_4_B 0x6C038
604#define _PORT_PLL_EBB_4_C 0x6C344
605#define PORT_PLL_RECALIBRATE REG_BIT(14)
606#define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13)
607#define BXT_PORT_PLL_EBB_4(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
608 _PORT_PLL_EBB_4_B, \
609 _PORT_PLL_EBB_4_C)
610
611#define _PORT_PLL_0_A 0x162100
612#define _PORT_PLL_0_B 0x6C100
613#define _PORT_PLL_0_C 0x6C380
614/* PORT_PLL_0_A */
615#define PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0)
616#define PORT_PLL_M2_INT(m2_int) REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, (m2_int))
617/* PORT_PLL_1_A */
618#define PORT_PLL_N_MASK REG_GENMASK(11, 8)
619#define PORT_PLL_N(n) REG_FIELD_PREP(PORT_PLL_N_MASK, (n))
620/* PORT_PLL_2_A */
621#define PORT_PLL_M2_FRAC_MASK REG_GENMASK(21, 0)
622#define PORT_PLL_M2_FRAC(m2_frac) REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, (m2_frac))
623/* PORT_PLL_3_A */
624#define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16)
625/* PORT_PLL_6_A */
626#define PORT_PLL_GAIN_CTL_MASK REG_GENMASK(18, 16)
627#define PORT_PLL_GAIN_CTL(x) REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, (x))
628#define PORT_PLL_INT_COEFF_MASK REG_GENMASK(12, 8)
629#define PORT_PLL_INT_COEFF(x) REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x))
630#define PORT_PLL_PROP_COEFF_MASK REG_GENMASK(3, 0)
631#define PORT_PLL_PROP_COEFF(x) REG_FIELD_PREP(PORT_PLL_PROP_COEFF_MASK, (x))
632/* PORT_PLL_8_A */
633#define PORT_PLL_TARGET_CNT_MASK REG_GENMASK(9, 0)
634#define PORT_PLL_TARGET_CNT(x) REG_FIELD_PREP(PORT_PLL_TARGET_CNT_MASK, (x))
635/* PORT_PLL_9_A */
636#define PORT_PLL_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1)
637#define PORT_PLL_LOCK_THRESHOLD(x) REG_FIELD_PREP(PORT_PLL_LOCK_THRESHOLD_MASK, (x))
638/* PORT_PLL_10_A */
639#define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27)
640#define PORT_PLL_DCO_AMP_MASK REG_GENMASK(13, 10)
641#define PORT_PLL_DCO_AMP(x) REG_FIELD_PREP(PORT_PLL_DCO_AMP_MASK, (x))
642#define _PORT_PLL_BASE(phy, ch) _BXT_PHY_CH(phy, ch, \
643 _PORT_PLL_0_B, \
644 _PORT_PLL_0_C)
645#define BXT_PORT_PLL(phy, ch, idx) _MMIO(_PORT_PLL_BASE(phy, ch) + \
646 (idx) * 4)
647
648/* BXT PHY common lane registers */
649#define _PORT_CL1CM_DW0_A 0x162000
650#define _PORT_CL1CM_DW0_BC 0x6C000
651#define PHY_POWER_GOOD (1 << 16)
652#define PHY_RESERVED (1 << 7)
653#define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), _PORT_CL1CM_DW0_BC)
654
655#define _PORT_CL1CM_DW9_A 0x162024
656#define _PORT_CL1CM_DW9_BC 0x6C024
657#define IREF0RC_OFFSET_SHIFT 8
658#define IREF0RC_OFFSET_MASK (0xFF << IREF0RC_OFFSET_SHIFT)
659#define BXT_PORT_CL1CM_DW9(phy) _BXT_PHY((phy), _PORT_CL1CM_DW9_BC)
660
661#define _PORT_CL1CM_DW10_A 0x162028
662#define _PORT_CL1CM_DW10_BC 0x6C028
663#define IREF1RC_OFFSET_SHIFT 8
664#define IREF1RC_OFFSET_MASK (0xFF << IREF1RC_OFFSET_SHIFT)
665#define BXT_PORT_CL1CM_DW10(phy) _BXT_PHY((phy), _PORT_CL1CM_DW10_BC)
666
667#define _PORT_CL1CM_DW28_A 0x162070
668#define _PORT_CL1CM_DW28_BC 0x6C070
669#define OCL1_POWER_DOWN_EN (1 << 23)
670#define DW28_OLDO_DYN_PWR_DOWN_EN (1 << 22)
671#define SUS_CLK_CONFIG 0x3
672#define BXT_PORT_CL1CM_DW28(phy) _BXT_PHY((phy), _PORT_CL1CM_DW28_BC)
673
674#define _PORT_CL1CM_DW30_A 0x162078
675#define _PORT_CL1CM_DW30_BC 0x6C078
676#define OCL2_LDOFUSE_PWR_DIS (1 << 6)
677#define BXT_PORT_CL1CM_DW30(phy) _BXT_PHY((phy), _PORT_CL1CM_DW30_BC)
678
679/* The spec defines this only for BXT PHY0, but lets assume that this
680 * would exist for PHY1 too if it had a second channel.
681 */
682#define _PORT_CL2CM_DW6_A 0x162358
683#define _PORT_CL2CM_DW6_BC 0x6C358
684#define BXT_PORT_CL2CM_DW6(phy) _BXT_PHY((phy), _PORT_CL2CM_DW6_BC)
685#define DW6_OLDO_DYN_PWR_DOWN_EN (1 << 28)
686
687/* BXT PHY Ref registers */
688#define _PORT_REF_DW3_A 0x16218C
689#define _PORT_REF_DW3_BC 0x6C18C
690#define GRC_DONE (1 << 22)
691#define BXT_PORT_REF_DW3(phy) _BXT_PHY((phy), _PORT_REF_DW3_BC)
692
693#define _PORT_REF_DW6_A 0x162198
694#define _PORT_REF_DW6_BC 0x6C198
695#define GRC_CODE_SHIFT 24
696#define GRC_CODE_MASK (0xFF << GRC_CODE_SHIFT)
697#define GRC_CODE_FAST_SHIFT 16
698#define GRC_CODE_FAST_MASK (0xFF << GRC_CODE_FAST_SHIFT)
699#define GRC_CODE_SLOW_SHIFT 8
700#define GRC_CODE_SLOW_MASK (0xFF << GRC_CODE_SLOW_SHIFT)
701#define GRC_CODE_NOM_MASK 0xFF
702#define BXT_PORT_REF_DW6(phy) _BXT_PHY((phy), _PORT_REF_DW6_BC)
703
704#define _PORT_REF_DW8_A 0x1621A0
705#define _PORT_REF_DW8_BC 0x6C1A0
706#define GRC_DIS (1 << 15)
707#define GRC_RDY_OVRD (1 << 1)
708#define BXT_PORT_REF_DW8(phy) _BXT_PHY((phy), _PORT_REF_DW8_BC)
709
710/* BXT PHY PCS registers */
711#define _PORT_PCS_DW10_LN01_A 0x162428
712#define _PORT_PCS_DW10_LN01_B 0x6C428
713#define _PORT_PCS_DW10_LN01_C 0x6C828
714#define _PORT_PCS_DW10_GRP_A 0x162C28
715#define _PORT_PCS_DW10_GRP_B 0x6CC28
716#define _PORT_PCS_DW10_GRP_C 0x6CE28
717#define BXT_PORT_PCS_DW10_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
718 _PORT_PCS_DW10_LN01_B, \
719 _PORT_PCS_DW10_LN01_C)
720#define BXT_PORT_PCS_DW10_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
721 _PORT_PCS_DW10_GRP_B, \
722 _PORT_PCS_DW10_GRP_C)
723
724#define TX2_SWING_CALC_INIT (1 << 31)
725#define TX1_SWING_CALC_INIT (1 << 30)
726
727#define _PORT_PCS_DW12_LN01_A 0x162430
728#define _PORT_PCS_DW12_LN01_B 0x6C430
729#define _PORT_PCS_DW12_LN01_C 0x6C830
730#define _PORT_PCS_DW12_LN23_A 0x162630
731#define _PORT_PCS_DW12_LN23_B 0x6C630
732#define _PORT_PCS_DW12_LN23_C 0x6CA30
733#define _PORT_PCS_DW12_GRP_A 0x162c30
734#define _PORT_PCS_DW12_GRP_B 0x6CC30
735#define _PORT_PCS_DW12_GRP_C 0x6CE30
736#define LANESTAGGER_STRAP_OVRD (1 << 6)
737#define LANE_STAGGER_MASK 0x1F
738#define BXT_PORT_PCS_DW12_LN01(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
739 _PORT_PCS_DW12_LN01_B, \
740 _PORT_PCS_DW12_LN01_C)
741#define BXT_PORT_PCS_DW12_LN23(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
742 _PORT_PCS_DW12_LN23_B, \
743 _PORT_PCS_DW12_LN23_C)
744#define BXT_PORT_PCS_DW12_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
745 _PORT_PCS_DW12_GRP_B, \
746 _PORT_PCS_DW12_GRP_C)
747
748/* BXT PHY TX registers */
749#define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \
750 ((lane) & 1) * 0x80)
751
752#define _PORT_TX_DW2_LN0_A 0x162508
753#define _PORT_TX_DW2_LN0_B 0x6C508
754#define _PORT_TX_DW2_LN0_C 0x6C908
755#define _PORT_TX_DW2_GRP_A 0x162D08
756#define _PORT_TX_DW2_GRP_B 0x6CD08
757#define _PORT_TX_DW2_GRP_C 0x6CF08
758#define BXT_PORT_TX_DW2_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
759 _PORT_TX_DW2_LN0_B, \
760 _PORT_TX_DW2_LN0_C)
761#define BXT_PORT_TX_DW2_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
762 _PORT_TX_DW2_GRP_B, \
763 _PORT_TX_DW2_GRP_C)
764#define MARGIN_000_SHIFT 16
765#define MARGIN_000 (0xFF << MARGIN_000_SHIFT)
766#define UNIQ_TRANS_SCALE_SHIFT 8
767#define UNIQ_TRANS_SCALE (0xFF << UNIQ_TRANS_SCALE_SHIFT)
768
769#define _PORT_TX_DW3_LN0_A 0x16250C
770#define _PORT_TX_DW3_LN0_B 0x6C50C
771#define _PORT_TX_DW3_LN0_C 0x6C90C
772#define _PORT_TX_DW3_GRP_A 0x162D0C
773#define _PORT_TX_DW3_GRP_B 0x6CD0C
774#define _PORT_TX_DW3_GRP_C 0x6CF0C
775#define BXT_PORT_TX_DW3_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
776 _PORT_TX_DW3_LN0_B, \
777 _PORT_TX_DW3_LN0_C)
778#define BXT_PORT_TX_DW3_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
779 _PORT_TX_DW3_GRP_B, \
780 _PORT_TX_DW3_GRP_C)
781#define SCALE_DCOMP_METHOD (1 << 26)
782#define UNIQUE_TRANGE_EN_METHOD (1 << 27)
783
784#define _PORT_TX_DW4_LN0_A 0x162510
785#define _PORT_TX_DW4_LN0_B 0x6C510
786#define _PORT_TX_DW4_LN0_C 0x6C910
787#define _PORT_TX_DW4_GRP_A 0x162D10
788#define _PORT_TX_DW4_GRP_B 0x6CD10
789#define _PORT_TX_DW4_GRP_C 0x6CF10
790#define BXT_PORT_TX_DW4_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
791 _PORT_TX_DW4_LN0_B, \
792 _PORT_TX_DW4_LN0_C)
793#define BXT_PORT_TX_DW4_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
794 _PORT_TX_DW4_GRP_B, \
795 _PORT_TX_DW4_GRP_C)
796#define DEEMPH_SHIFT 24
797#define DE_EMPHASIS (0xFF << DEEMPH_SHIFT)
798
799#define _PORT_TX_DW5_LN0_A 0x162514
800#define _PORT_TX_DW5_LN0_B 0x6C514
801#define _PORT_TX_DW5_LN0_C 0x6C914
802#define _PORT_TX_DW5_GRP_A 0x162D14
803#define _PORT_TX_DW5_GRP_B 0x6CD14
804#define _PORT_TX_DW5_GRP_C 0x6CF14
805#define BXT_PORT_TX_DW5_LN0(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
806 _PORT_TX_DW5_LN0_B, \
807 _PORT_TX_DW5_LN0_C)
808#define BXT_PORT_TX_DW5_GRP(phy, ch) _MMIO_BXT_PHY_CH(phy, ch, \
809 _PORT_TX_DW5_GRP_B, \
810 _PORT_TX_DW5_GRP_C)
811#define DCC_DELAY_RANGE_1 (1 << 9)
812#define DCC_DELAY_RANGE_2 (1 << 8)
813
814#define _PORT_TX_DW14_LN0_A 0x162538
815#define _PORT_TX_DW14_LN0_B 0x6C538
816#define _PORT_TX_DW14_LN0_C 0x6C938
817#define LATENCY_OPTIM_SHIFT 30
818#define LATENCY_OPTIM (1 << LATENCY_OPTIM_SHIFT)
819#define BXT_PORT_TX_DW14_LN(phy, ch, lane) \
820 _MMIO(_BXT_PHY_CH(phy, ch, _PORT_TX_DW14_LN0_B, \
821 _PORT_TX_DW14_LN0_C) + \
822 _BXT_LANE_OFFSET(lane))
823
824/* UAIMI scratch pad register 1 */
825#define UAIMI_SPR1 _MMIO(0x4F074)
826/* SKL VccIO mask */
827#define SKL_VCCIO_MASK 0x1
828/* SKL balance leg register */
829#define DISPIO_CR_TX_BMU_CR0 _MMIO(0x6C00C)
830/* I_boost values */
831#define BALANCE_LEG_SHIFT(port) (8 + 3 * (port))
832#define BALANCE_LEG_MASK(port) (7 << (8 + 3 * (port)))
833/* Balance leg disable bits */
834#define BALANCE_LEG_DISABLE_SHIFT 23
835#define BALANCE_LEG_DISABLE(port) (1 << (23 + (port)))
836
837/*
838 * Fence registers
839 * [0-7] @ 0x2000 gen2,gen3
840 * [8-15] @ 0x3000 945,g33,pnv
841 *
842 * [0-15] @ 0x3000 gen4,gen5
843 *
844 * [0-15] @ 0x100000 gen6,vlv,chv
845 * [0-31] @ 0x100000 gen7+
846 */
847#define FENCE_REG(i) _MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
848#define I830_FENCE_START_MASK 0x07f80000
849#define I830_FENCE_TILING_Y_SHIFT 12
850#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
851#define I830_FENCE_PITCH_SHIFT 4
852#define I830_FENCE_REG_VALID (1 << 0)
853#define I915_FENCE_MAX_PITCH_VAL 4
854#define I830_FENCE_MAX_PITCH_VAL 6
855#define I830_FENCE_MAX_SIZE_VAL (1 << 8)
856
857#define I915_FENCE_START_MASK 0x0ff00000
858#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
859
860#define FENCE_REG_965_LO(i) _MMIO(0x03000 + (i) * 8)
861#define FENCE_REG_965_HI(i) _MMIO(0x03000 + (i) * 8 + 4)
862#define I965_FENCE_PITCH_SHIFT 2
863#define I965_FENCE_TILING_Y_SHIFT 1
864#define I965_FENCE_REG_VALID (1 << 0)
865#define I965_FENCE_MAX_PITCH_VAL 0x0400
866
867#define FENCE_REG_GEN6_LO(i) _MMIO(0x100000 + (i) * 8)
868#define FENCE_REG_GEN6_HI(i) _MMIO(0x100000 + (i) * 8 + 4)
869#define GEN6_FENCE_PITCH_SHIFT 32
870#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
871
872
873/* control register for cpu gtt access */
874#define TILECTL _MMIO(0x101000)
875#define TILECTL_SWZCTL (1 << 0)
876#define TILECTL_TLBPF (1 << 1)
877#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
878#define TILECTL_BACKSNOOP_DIS (1 << 3)
879
880/*
881 * Instruction and interrupt control regs
882 */
883#define PGTBL_CTL _MMIO(0x02020)
884#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
885#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
886#define PGTBL_ER _MMIO(0x02024)
887#define PRB0_BASE (0x2030 - 0x30)
888#define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
889#define PRB2_BASE (0x2050 - 0x30) /* gen3 */
890#define SRB0_BASE (0x2100 - 0x30) /* gen2 */
891#define SRB1_BASE (0x2110 - 0x30) /* gen2 */
892#define SRB2_BASE (0x2120 - 0x30) /* 830 */
893#define SRB3_BASE (0x2130 - 0x30) /* 830 */
894#define RENDER_RING_BASE 0x02000
895#define BSD_RING_BASE 0x04000
896#define GEN6_BSD_RING_BASE 0x12000
897#define GEN8_BSD2_RING_BASE 0x1c000
898#define GEN11_BSD_RING_BASE 0x1c0000
899#define GEN11_BSD2_RING_BASE 0x1c4000
900#define GEN11_BSD3_RING_BASE 0x1d0000
901#define GEN11_BSD4_RING_BASE 0x1d4000
902#define XEHP_BSD5_RING_BASE 0x1e0000
903#define XEHP_BSD6_RING_BASE 0x1e4000
904#define XEHP_BSD7_RING_BASE 0x1f0000
905#define XEHP_BSD8_RING_BASE 0x1f4000
906#define VEBOX_RING_BASE 0x1a000
907#define GEN11_VEBOX_RING_BASE 0x1c8000
908#define GEN11_VEBOX2_RING_BASE 0x1d8000
909#define XEHP_VEBOX3_RING_BASE 0x1e8000
910#define XEHP_VEBOX4_RING_BASE 0x1f8000
911#define MTL_GSC_RING_BASE 0x11a000
912#define GEN12_COMPUTE0_RING_BASE 0x1a000
913#define GEN12_COMPUTE1_RING_BASE 0x1c000
914#define GEN12_COMPUTE2_RING_BASE 0x1e000
915#define GEN12_COMPUTE3_RING_BASE 0x26000
916#define BLT_RING_BASE 0x22000
917#define XEHPC_BCS1_RING_BASE 0x3e0000
918#define XEHPC_BCS2_RING_BASE 0x3e2000
919#define XEHPC_BCS3_RING_BASE 0x3e4000
920#define XEHPC_BCS4_RING_BASE 0x3e6000
921#define XEHPC_BCS5_RING_BASE 0x3e8000
922#define XEHPC_BCS6_RING_BASE 0x3ea000
923#define XEHPC_BCS7_RING_BASE 0x3ec000
924#define XEHPC_BCS8_RING_BASE 0x3ee000
925#define DG1_GSC_HECI1_BASE 0x00258000
926#define DG1_GSC_HECI2_BASE 0x00259000
927#define DG2_GSC_HECI1_BASE 0x00373000
928#define DG2_GSC_HECI2_BASE 0x00374000
929#define MTL_GSC_HECI1_BASE 0x00116000
930#define MTL_GSC_HECI2_BASE 0x00117000
931
932#define HECI_H_CSR(base) _MMIO((base) + 0x4)
933#define HECI_H_CSR_IE REG_BIT(0)
934#define HECI_H_CSR_IS REG_BIT(1)
935#define HECI_H_CSR_IG REG_BIT(2)
936#define HECI_H_CSR_RDY REG_BIT(3)
937#define HECI_H_CSR_RST REG_BIT(4)
938
939#define HECI_H_GS1(base) _MMIO((base) + 0xc4c)
940#define HECI_H_GS1_ER_PREP REG_BIT(0)
941
942/*
943 * The FWSTS register values are FW defined and can be different between
944 * HECI1 and HECI2
945 */
946#define HECI_FWSTS1 0xc40
947#define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0)
948#define HECI1_FWSTS1_CURRENT_STATE_RESET 0
949#define HECI1_FWSTS1_PROXY_STATE_NORMAL 5
950#define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9)
951#define HECI_FWSTS2 0xc48
952#define HECI_FWSTS3 0xc60
953#define HECI_FWSTS4 0xc64
954#define HECI_FWSTS5 0xc68
955#define HECI1_FWSTS5_HUC_AUTH_DONE (1 << 19)
956#define HECI_FWSTS6 0xc6c
957
958/* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */
959#define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \
960 HECI_FWSTS1, \
961 HECI_FWSTS2, \
962 HECI_FWSTS3, \
963 HECI_FWSTS4, \
964 HECI_FWSTS5, \
965 HECI_FWSTS6))
966
967#define HSW_GTT_CACHE_EN _MMIO(0x4024)
968#define GTT_CACHE_EN_ALL 0xF0007FFF
969#define GEN7_WR_WATERMARK _MMIO(0x4028)
970#define GEN7_GFX_PRIO_CTRL _MMIO(0x402C)
971#define ARB_MODE _MMIO(0x4030)
972#define ARB_MODE_SWIZZLE_SNB (1 << 4)
973#define ARB_MODE_SWIZZLE_IVB (1 << 5)
974#define GEN7_GFX_PEND_TLB0 _MMIO(0x4034)
975#define GEN7_GFX_PEND_TLB1 _MMIO(0x4038)
976/* L3, CVS, ZTLB, RCC, CASC LRA min, max values */
977#define GEN7_LRA_LIMITS(i) _MMIO(0x403C + (i) * 4)
978#define GEN7_LRA_LIMITS_REG_NUM 13
979#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
980#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
981
982#define GEN7_ERR_INT _MMIO(0x44040)
983#define ERR_INT_POISON (1 << 31)
984#define ERR_INT_MMIO_UNCLAIMED (1 << 13)
985#define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
986#define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
987#define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
988#define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
989#define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
990#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
991#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
992#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
993
994#define FPGA_DBG _MMIO(0x42300)
995#define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
996
997#define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
998#define CLAIM_ER_CLR REG_BIT(31)
999#define CLAIM_ER_OVERFLOW REG_BIT(16)
1000#define CLAIM_ER_CTR_MASK REG_GENMASK(15, 0)
1001
1002#define DERRMR _MMIO(0x44050)
1003/* Note that HBLANK events are reserved on bdw+ */
1004#define DERRMR_PIPEA_SCANLINE (1 << 0)
1005#define DERRMR_PIPEA_PRI_FLIP_DONE (1 << 1)
1006#define DERRMR_PIPEA_SPR_FLIP_DONE (1 << 2)
1007#define DERRMR_PIPEA_VBLANK (1 << 3)
1008#define DERRMR_PIPEA_HBLANK (1 << 5)
1009#define DERRMR_PIPEB_SCANLINE (1 << 8)
1010#define DERRMR_PIPEB_PRI_FLIP_DONE (1 << 9)
1011#define DERRMR_PIPEB_SPR_FLIP_DONE (1 << 10)
1012#define DERRMR_PIPEB_VBLANK (1 << 11)
1013#define DERRMR_PIPEB_HBLANK (1 << 13)
1014/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
1015#define DERRMR_PIPEC_SCANLINE (1 << 14)
1016#define DERRMR_PIPEC_PRI_FLIP_DONE (1 << 15)
1017#define DERRMR_PIPEC_SPR_FLIP_DONE (1 << 20)
1018#define DERRMR_PIPEC_VBLANK (1 << 21)
1019#define DERRMR_PIPEC_HBLANK (1 << 22)
1020
1021#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
1022#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
1023#define SCPD0 _MMIO(0x209c) /* 915+ only */
1024#define SCPD_FBC_IGNORE_3D (1 << 6)
1025#define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5)
1026#define GEN2_IER _MMIO(0x20a0)
1027#define GEN2_IIR _MMIO(0x20a4)
1028#define GEN2_IMR _MMIO(0x20a8)
1029#define GEN2_ISR _MMIO(0x20ac)
1030#define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
1031#define GINT_DIS (1 << 22)
1032#define GCFG_DIS (1 << 8)
1033#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
1034#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
1035#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
1036#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
1037#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
1038#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
1039#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
1040#define VLV_PCBR_ADDR_SHIFT 12
1041
1042#define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
1043#define EIR _MMIO(0x20b0)
1044#define EMR _MMIO(0x20b4)
1045#define ESR _MMIO(0x20b8)
1046#define GM45_ERROR_PAGE_TABLE (1 << 5)
1047#define GM45_ERROR_MEM_PRIV (1 << 4)
1048#define I915_ERROR_PAGE_TABLE (1 << 4)
1049#define GM45_ERROR_CP_PRIV (1 << 3)
1050#define I915_ERROR_MEMORY_REFRESH (1 << 1)
1051#define I915_ERROR_INSTRUCTION (1 << 0)
1052#define INSTPM _MMIO(0x20c0)
1053#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
1054#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
1055 will not assert AGPBUSY# and will only
1056 be delivered when out of C3. */
1057#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
1058#define INSTPM_TLB_INVALIDATE (1 << 9)
1059#define INSTPM_SYNC_FLUSH (1 << 5)
1060#define MEM_MODE _MMIO(0x20cc)
1061#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
1062#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
1063#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
1064#define FW_BLC _MMIO(0x20d8)
1065#define FW_BLC2 _MMIO(0x20dc)
1066#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
1067#define FW_BLC_SELF_EN_MASK (1 << 31)
1068#define FW_BLC_SELF_FIFO_MASK (1 << 16) /* 945 only */
1069#define FW_BLC_SELF_EN (1 << 15) /* 945 only */
1070#define MM_BURST_LENGTH 0x00700000
1071#define MM_FIFO_WATERMARK 0x0001F000
1072#define LM_BURST_LENGTH 0x00000700
1073#define LM_FIFO_WATERMARK 0x0000001F
1074#define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */
1075
1076#define _MBUS_ABOX0_CTL 0x45038
1077#define _MBUS_ABOX1_CTL 0x45048
1078#define _MBUS_ABOX2_CTL 0x4504C
1079#define MBUS_ABOX_CTL(x) \
1080 _MMIO(_PICK_EVEN_2RANGES(x, 2, \
1081 _MBUS_ABOX0_CTL, _MBUS_ABOX1_CTL, \
1082 _MBUS_ABOX2_CTL, _MBUS_ABOX2_CTL))
1083
1084#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20)
1085#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20)
1086#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16)
1087#define MBUS_ABOX_B_CREDIT(x) ((x) << 16)
1088#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8)
1089#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8)
1090#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0)
1091#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0)
1092
1093/* Make render/texture TLB fetches lower priorty than associated data
1094 * fetches. This is not turned on by default
1095 */
1096#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
1097
1098/* Isoch request wait on GTT enable (Display A/B/C streams).
1099 * Make isoch requests stall on the TLB update. May cause
1100 * display underruns (test mode only)
1101 */
1102#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
1103
1104/* Block grant count for isoch requests when block count is
1105 * set to a finite value.
1106 */
1107#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
1108#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
1109#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
1110#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
1111#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
1112
1113/* Enable render writes to complete in C2/C3/C4 power states.
1114 * If this isn't enabled, render writes are prevented in low
1115 * power states. That seems bad to me.
1116 */
1117#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
1118
1119/* This acknowledges an async flip immediately instead
1120 * of waiting for 2TLB fetches.
1121 */
1122#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
1123
1124/* Enables non-sequential data reads through arbiter
1125 */
1126#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
1127
1128/* Disable FSB snooping of cacheable write cycles from binner/render
1129 * command stream
1130 */
1131#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
1132
1133/* Arbiter time slice for non-isoch streams */
1134#define MI_ARB_TIME_SLICE_MASK (7 << 5)
1135#define MI_ARB_TIME_SLICE_1 (0 << 5)
1136#define MI_ARB_TIME_SLICE_2 (1 << 5)
1137#define MI_ARB_TIME_SLICE_4 (2 << 5)
1138#define MI_ARB_TIME_SLICE_6 (3 << 5)
1139#define MI_ARB_TIME_SLICE_8 (4 << 5)
1140#define MI_ARB_TIME_SLICE_10 (5 << 5)
1141#define MI_ARB_TIME_SLICE_14 (6 << 5)
1142#define MI_ARB_TIME_SLICE_16 (7 << 5)
1143
1144/* Low priority grace period page size */
1145#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
1146#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
1147
1148/* Disable display A/B trickle feed */
1149#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
1150
1151/* Set display plane priority */
1152#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
1153#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
1154
1155#define MI_STATE _MMIO(0x20e4) /* gen2 only */
1156#define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */
1157#define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */
1158
1159/* On modern GEN architectures interrupt control consists of two sets
1160 * of registers. The first set pertains to the ring generating the
1161 * interrupt. The second control is for the functional block generating the
1162 * interrupt. These are PM, GT, DE, etc.
1163 *
1164 * Luckily *knocks on wood* all the ring interrupt bits match up with the
1165 * GT interrupt bits, so we don't need to duplicate the defines.
1166 *
1167 * These defines should cover us well from SNB->HSW with minor exceptions
1168 * it can also work on ILK.
1169 */
1170#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
1171#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
1172#define GT_BLT_USER_INTERRUPT (1 << 22)
1173#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
1174#define GT_BSD_USER_INTERRUPT (1 << 12)
1175#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
1176#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */
1177#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
1178#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
1179#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
1180#define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3)
1181#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
1182#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
1183#define GT_RENDER_USER_INTERRUPT (1 << 0)
1184
1185#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
1186#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
1187
1188#define GT_PARITY_ERROR(dev_priv) \
1189 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
1190 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
1191
1192/* These are all the "old" interrupts */
1193#define ILK_BSD_USER_INTERRUPT (1 << 5)
1194
1195#define I915_PM_INTERRUPT (1 << 31)
1196#define I915_ISP_INTERRUPT (1 << 22)
1197#define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
1198#define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
1199#define I915_MIPIC_INTERRUPT (1 << 19)
1200#define I915_MIPIA_INTERRUPT (1 << 18)
1201#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
1202#define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
1203#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
1204#define I915_MASTER_ERROR_INTERRUPT (1 << 15)
1205#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
1206#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
1207#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
1208#define I915_HWB_OOM_INTERRUPT (1 << 13)
1209#define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
1210#define I915_SYNC_STATUS_INTERRUPT (1 << 12)
1211#define I915_MISC_INTERRUPT (1 << 11)
1212#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
1213#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
1214#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
1215#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
1216#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
1217#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
1218#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
1219#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
1220#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
1221#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
1222#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
1223#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
1224#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
1225#define I915_DEBUG_INTERRUPT (1 << 2)
1226#define I915_WINVALID_INTERRUPT (1 << 1)
1227#define I915_USER_INTERRUPT (1 << 1)
1228#define I915_ASLE_INTERRUPT (1 << 0)
1229#define I915_BSD_USER_INTERRUPT (1 << 25)
1230
1231#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
1232#define I915_HDMI_LPE_AUDIO_SIZE 0x1000
1233
1234/* DisplayPort Audio w/ LPE */
1235#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
1236#define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0)
1237
1238#define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
1239#define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
1240#define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
1241#define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
1242 _VLV_AUD_PORT_EN_B_DBG, \
1243 _VLV_AUD_PORT_EN_C_DBG, \
1244 _VLV_AUD_PORT_EN_D_DBG)
1245#define VLV_AMP_MUTE (1 << 1)
1246
1247#define GEN6_BSD_RNCID _MMIO(0x12198)
1248
1249#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
1250#define GEN7_FF_SCHED_MASK 0x0077070
1251#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
1252#define GEN12_FF_TESSELATION_DOP_GATE_DISABLE BIT(19)
1253#define GEN7_FF_TS_SCHED_HS1 (0x5 << 16)
1254#define GEN7_FF_TS_SCHED_HS0 (0x3 << 16)
1255#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1 << 16)
1256#define GEN7_FF_TS_SCHED_HW (0x0 << 16) /* Default */
1257#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
1258#define GEN7_FF_VS_SCHED_HS1 (0x5 << 12)
1259#define GEN7_FF_VS_SCHED_HS0 (0x3 << 12)
1260#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1 << 12) /* Default */
1261#define GEN7_FF_VS_SCHED_HW (0x0 << 12)
1262#define GEN7_FF_DS_SCHED_HS1 (0x5 << 4)
1263#define GEN7_FF_DS_SCHED_HS0 (0x3 << 4)
1264#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */
1265#define GEN7_FF_DS_SCHED_HW (0x0 << 4)
1266
1267/*
1268 * Framebuffer compression (915+ only)
1269 */
1270
1271#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
1272#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
1273#define FBC_CONTROL _MMIO(0x3208)
1274#define FBC_CTL_EN REG_BIT(31)
1275#define FBC_CTL_PERIODIC REG_BIT(30)
1276#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16)
1277#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x))
1278#define FBC_CTL_STOP_ON_MOD REG_BIT(15)
1279#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */
1280#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */
1281#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5)
1282#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x))
1283#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
1284#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x))
1285#define FBC_COMMAND _MMIO(0x320c)
1286#define FBC_CMD_COMPRESS REG_BIT(0)
1287#define FBC_STATUS _MMIO(0x3210)
1288#define FBC_STAT_COMPRESSING REG_BIT(31)
1289#define FBC_STAT_COMPRESSED REG_BIT(30)
1290#define FBC_STAT_MODIFIED REG_BIT(29)
1291#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
1292#define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */
1293#define FBC_CTL_FENCE_DBL REG_BIT(4)
1294#define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2)
1295#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
1296#define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1)
1297#define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2)
1298#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3)
1299#define FBC_CTL_CPU_FENCE_EN REG_BIT(1)
1300#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
1301#define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane))
1302#define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */
1303#define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */
1304#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1)
1305#define FBC_MOD_NUM_VALID REG_BIT(0)
1306#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */
1307#define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */
1308#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)
1309#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1)
1310#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2)
1311#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3)
1312
1313#define FBC_LL_SIZE (1536)
1314
1315/* Framebuffer compression for GM45+ */
1316#define DPFC_CB_BASE _MMIO(0x3200)
1317#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
1318#define DPFC_CONTROL _MMIO(0x3208)
1319#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
1320#define DPFC_CTL_EN REG_BIT(31)
1321#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
1322#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane))
1323#define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
1324#define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */
1325#define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane))
1326#define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */
1327#define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
1328#define DPFC_CTL_PLANE_BINDING_MASK REG_GENMASK(12, 11) /* lnl+ */
1329#define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id))
1330#define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */
1331#define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */
1332#define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */
1333#define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6)
1334#define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
1335#define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1)
1336#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2)
1337#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
1338#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence))
1339#define DPFC_RECOMP_CTL _MMIO(0x320c)
1340#define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
1341#define DPFC_RECOMP_STALL_EN REG_BIT(27)
1342#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16)
1343#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
1344#define DPFC_STATUS _MMIO(0x3210)
1345#define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
1346#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16)
1347#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
1348#define DPFC_STATUS2 _MMIO(0x3214)
1349#define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
1350#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
1351#define DPFC_FENCE_YOFF _MMIO(0x3218)
1352#define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
1353#define DPFC_CHICKEN _MMIO(0x3224)
1354#define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
1355#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
1356#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */
1357#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */
1358#define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */
1359#define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */
1360
1361#define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
1362#define FBC_STRIDE_OVERRIDE REG_BIT(15)
1363#define FBC_STRIDE_MASK REG_GENMASK(14, 0)
1364#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x))
1365
1366#define ILK_FBC_RT_BASE _MMIO(0x2128)
1367#define ILK_FBC_RT_VALID REG_BIT(0)
1368#define SNB_FBC_FRONT_BUFFER REG_BIT(1)
1369
1370#define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000)
1371#define ILK_FBCQ_DIS REG_BIT(22)
1372#define ILK_PABSTRETCH_DIS REG_BIT(21)
1373#define ILK_SABSTRETCH_DIS REG_BIT(20)
1374#define IVB_PRI_STRETCH_MAX_MASK REG_GENMASK(21, 20)
1375#define IVB_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
1376#define IVB_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)
1377#define IVB_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)
1378#define IVB_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)
1379#define IVB_SPR_STRETCH_MAX_MASK REG_GENMASK(19, 18)
1380#define IVB_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
1381#define IVB_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)
1382#define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)
1383#define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)
1384
1385
1386/*
1387 * Framebuffer compression for Sandybridge
1388 *
1389 * The following two registers are of type GTTMMADR
1390 */
1391#define SNB_DPFC_CTL_SA _MMIO(0x100100)
1392#define SNB_DPFC_FENCE_EN REG_BIT(29)
1393#define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0)
1394#define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence))
1395#define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
1396
1397/* Framebuffer compression for Ivybridge */
1398#define IVB_FBC_RT_BASE _MMIO(0x7020)
1399#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
1400
1401#define IPS_CTL _MMIO(0x43408)
1402#define IPS_ENABLE REG_BIT(31)
1403#define IPS_FALSE_COLOR REG_BIT(4)
1404
1405#define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)
1406#define FBC_REND_NUKE REG_BIT(2)
1407#define FBC_REND_CACHE_CLEAN REG_BIT(1)
1408
1409/*
1410 * Clock control & power management
1411 */
1412#define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
1413#define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
1414#define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
1415#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
1416
1417#define VGA0 _MMIO(0x6000)
1418#define VGA1 _MMIO(0x6004)
1419#define VGA_PD _MMIO(0x6010)
1420#define VGA0_PD_P2_DIV_4 (1 << 7)
1421#define VGA0_PD_P1_DIV_2 (1 << 5)
1422#define VGA0_PD_P1_SHIFT 0
1423#define VGA0_PD_P1_MASK (0x1f << 0)
1424#define VGA1_PD_P2_DIV_4 (1 << 15)
1425#define VGA1_PD_P1_DIV_2 (1 << 13)
1426#define VGA1_PD_P1_SHIFT 8
1427#define VGA1_PD_P1_MASK (0x1f << 8)
1428#define DPLL_VCO_ENABLE (1 << 31)
1429#define DPLL_SDVO_HIGH_SPEED (1 << 30)
1430#define DPLL_DVO_2X_MODE (1 << 30)
1431#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
1432#define DPLL_SYNCLOCK_ENABLE (1 << 29)
1433#define DPLL_REF_CLK_ENABLE_VLV (1 << 29)
1434#define DPLL_VGA_MODE_DIS (1 << 28)
1435#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
1436#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
1437#define DPLL_MODE_MASK (3 << 26)
1438#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1439#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1440#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
1441#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
1442#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
1443#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
1444#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
1445#define DPLL_LOCK_VLV (1 << 15)
1446#define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
1447#define DPLL_INTEGRATED_REF_CLK_VLV (1 << 13)
1448#define DPLL_SSC_REF_CLK_CHV (1 << 13)
1449#define DPLL_PORTC_READY_MASK (0xf << 4)
1450#define DPLL_PORTB_READY_MASK (0xf)
1451
1452#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
1453
1454/* Additional CHV pll/phy registers */
1455#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
1456#define DPLL_PORTD_READY_MASK (0xf)
1457#define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
1458#define PHY_CH_POWER_DOWN_OVRD_EN(phy, ch) (1 << (2 * (phy) + (ch) + 27))
1459#define PHY_LDO_DELAY_0NS 0x0
1460#define PHY_LDO_DELAY_200NS 0x1
1461#define PHY_LDO_DELAY_600NS 0x2
1462#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2 * (phy) + 23))
1463#define PHY_CH_POWER_DOWN_OVRD(mask, phy, ch) ((mask) << (8 * (phy) + 4 * (ch) + 11))
1464#define PHY_CH_SU_PSR 0x1
1465#define PHY_CH_DEEP_PSR 0x7
1466#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6 * (phy) + 3 * (ch) + 2))
1467#define PHY_COM_LANE_RESET_DEASSERT(phy) (1 << (phy))
1468#define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
1469#define PHY_POWERGOOD(phy) (((phy) == DPIO_PHY0) ? (1 << 31) : (1 << 30))
1470#define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
1471#define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline))))
1472
1473/*
1474 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1475 * this field (only one bit may be set).
1476 */
1477#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1478#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
1479#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
1480/* i830, required in DVO non-gang */
1481#define PLL_P2_DIVIDE_BY_4 (1 << 23)
1482#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
1483#define PLL_REF_INPUT_DREFCLK (0 << 13)
1484#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
1485#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
1486#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1487#define PLL_REF_INPUT_MASK (3 << 13)
1488#define PLL_LOAD_PULSE_PHASE_SHIFT 9
1489/* Ironlake */
1490# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
1491# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
1492# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
1493# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
1494# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
1495
1496/*
1497 * Parallel to Serial Load Pulse phase selection.
1498 * Selects the phase for the 10X DPLL clock for the PCIe
1499 * digital display port. The range is 4 to 13; 10 or more
1500 * is just a flip delay. The default is 6
1501 */
1502#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1503#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1504/*
1505 * SDVO multiplier for 945G/GM. Not used on 965.
1506 */
1507#define SDVO_MULTIPLIER_MASK 0x000000ff
1508#define SDVO_MULTIPLIER_SHIFT_HIRES 4
1509#define SDVO_MULTIPLIER_SHIFT_VGA 0
1510
1511#define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
1512#define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
1513#define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
1514#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)
1515
1516/*
1517 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1518 *
1519 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1520 */
1521#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1522#define DPLL_MD_UDI_DIVIDER_SHIFT 24
1523/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1524#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1525#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1526/*
1527 * SDVO/UDI pixel multiplier.
1528 *
1529 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1530 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1531 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1532 * dummy bytes in the datastream at an increased clock rate, with both sides of
1533 * the link knowing how many bytes are fill.
1534 *
1535 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1536 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1537 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1538 * through an SDVO command.
1539 *
1540 * This register field has values of multiplication factor minus 1, with
1541 * a maximum multiplier of 5 for SDVO.
1542 */
1543#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1544#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1545/*
1546 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1547 * This best be set to the default value (3) or the CRT won't work. No,
1548 * I don't entirely understand what this does...
1549 */
1550#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1551#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1552
1553#define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
1554
1555#define _FPA0 0x6040
1556#define _FPA1 0x6044
1557#define _FPB0 0x6048
1558#define _FPB1 0x604c
1559#define FP0(pipe) _MMIO_PIPE(pipe, _FPA0, _FPB0)
1560#define FP1(pipe) _MMIO_PIPE(pipe, _FPA1, _FPB1)
1561#define FP_N_DIV_MASK 0x003f0000
1562#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
1563#define FP_N_DIV_SHIFT 16
1564#define FP_M1_DIV_MASK 0x00003f00
1565#define FP_M1_DIV_SHIFT 8
1566#define FP_M2_DIV_MASK 0x0000003f
1567#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
1568#define FP_M2_DIV_SHIFT 0
1569#define DPLL_TEST _MMIO(0x606c)
1570#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1571#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1572#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1573#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1574#define DPLLB_TEST_N_BYPASS (1 << 19)
1575#define DPLLB_TEST_M_BYPASS (1 << 18)
1576#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1577#define DPLLA_TEST_N_BYPASS (1 << 3)
1578#define DPLLA_TEST_M_BYPASS (1 << 2)
1579#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1580#define D_STATE _MMIO(0x6104)
1581#define DSTATE_GFX_RESET_I830 (1 << 6)
1582#define DSTATE_PLL_D3_OFF (1 << 3)
1583#define DSTATE_GFX_CLOCK_GATING (1 << 1)
1584#define DSTATE_DOT_CLOCK_GATING (1 << 0)
1585#define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
1586# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1587# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1588# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1589# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
1590# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
1591# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
1592# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
1593# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
1594# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1595# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1596# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1597# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1598# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1599# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1600# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1601# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1602# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1603# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1604# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1605# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1606# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1607# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1608# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1609# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1610# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
1611# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1612# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1613# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1614# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
1615/*
1616 * This bit must be set on the 830 to prevent hangs when turning off the
1617 * overlay scaler.
1618 */
1619# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1620# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1621# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1622# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
1623# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
1624
1625#define RENCLK_GATE_D1 _MMIO(0x6204)
1626# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
1627# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
1628# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1629# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1630# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1631# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1632# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1633# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1634# define MAG_CLOCK_GATE_DISABLE (1 << 5)
1635/* This bit must be unset on 855,865 */
1636# define MECI_CLOCK_GATE_DISABLE (1 << 4)
1637# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1638# define MEC_CLOCK_GATE_DISABLE (1 << 2)
1639# define MECO_CLOCK_GATE_DISABLE (1 << 1)
1640/* This bit must be set on 855,865. */
1641# define SV_CLOCK_GATE_DISABLE (1 << 0)
1642# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1643# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1644# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1645# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1646# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1647# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1648# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1649# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1650# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1651# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1652# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1653# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1654# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1655# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1656# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1657# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1658# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1659
1660# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1661/* This bit must always be set on 965G/965GM */
1662# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1663# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1664# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1665# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1666# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1667# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1668/* This bit must always be set on 965G */
1669# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1670# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1671# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1672# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1673# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1674# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1675# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1676# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1677# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1678# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1679# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1680# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1681# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1682# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1683# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1684# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1685# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1686# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1687# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1688
1689#define RENCLK_GATE_D2 _MMIO(0x6208)
1690#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1691#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1692#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
1693
1694#define VDECCLK_GATE_D _MMIO(0x620C) /* g4x only */
1695#define VCP_UNIT_CLOCK_GATE_DISABLE (1 << 4)
1696
1697#define RAMCLK_GATE_D _MMIO(0x6210) /* CRL only */
1698#define DEUC _MMIO(0x6214) /* CRL only */
1699
1700#define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
1701#define FW_CSPWRDWNEN (1 << 15)
1702
1703#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
1704
1705#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
1706#define CDCLK_FREQ_SHIFT 4
1707#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
1708#define CZCLK_FREQ_MASK 0xf
1709
1710#define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
1711#define PFI_CREDIT_63 (9 << 28) /* chv only */
1712#define PFI_CREDIT_31 (8 << 28) /* chv only */
1713#define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
1714#define PFI_CREDIT_RESEND (1 << 27)
1715#define VGA_FAST_MODE_DISABLE (1 << 14)
1716
1717#define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
1718
1719/*
1720 * Palette regs
1721 */
1722#define _PALETTE_A 0xa000
1723#define _PALETTE_B 0xa800
1724#define _CHV_PALETTE_C 0xc000
1725/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */
1726#define PALETTE_RED_MASK REG_GENMASK(23, 16)
1727#define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
1728#define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
1729/* pre-i965 10bit interpolated mode ldw */
1730#define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16)
1731#define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8)
1732#define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0)
1733/* pre-i965 10bit interpolated mode udw */
1734#define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22)
1735#define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18)
1736#define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16)
1737#define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14)
1738#define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10)
1739#define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8)
1740#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6)
1741#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2)
1742#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
1743#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
1744 _PICK_EVEN_2RANGES(pipe, 2, \
1745 _PALETTE_A, _PALETTE_B, \
1746 _CHV_PALETTE_C, _CHV_PALETTE_C) + \
1747 (i) * 4)
1748
1749#define PEG_BAND_GAP_DATA _MMIO(0x14d68)
1750
1751#define BXT_RP_STATE_CAP _MMIO(0x138170)
1752#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
1753#define XEHPSDV_RP_STATE_CAP _MMIO(0x250014)
1754#define PVC_RP_STATE_CAP _MMIO(0x281014)
1755
1756#define MTL_RP_STATE_CAP _MMIO(0x138000)
1757#define MTL_MEDIAP_STATE_CAP _MMIO(0x138020)
1758#define MTL_RP0_CAP_MASK REG_GENMASK(8, 0)
1759#define MTL_RPN_CAP_MASK REG_GENMASK(24, 16)
1760
1761#define MTL_GT_RPE_FREQUENCY _MMIO(0x13800c)
1762#define MTL_MPE_FREQUENCY _MMIO(0x13802c)
1763#define MTL_RPE_MASK REG_GENMASK(8, 0)
1764
1765#define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
1766#define GT0_PERF_LIMIT_REASONS_MASK 0xde3
1767#define PROCHOT_MASK REG_BIT(0)
1768#define THERMAL_LIMIT_MASK REG_BIT(1)
1769#define RATL_MASK REG_BIT(5)
1770#define VR_THERMALERT_MASK REG_BIT(6)
1771#define VR_TDC_MASK REG_BIT(7)
1772#define POWER_LIMIT_4_MASK REG_BIT(8)
1773#define POWER_LIMIT_1_MASK REG_BIT(10)
1774#define POWER_LIMIT_2_MASK REG_BIT(11)
1775#define GT0_PERF_LIMIT_REASONS_LOG_MASK REG_GENMASK(31, 16)
1776#define MTL_MEDIA_PERF_LIMIT_REASONS _MMIO(0x138030)
1777
1778#define CHV_CLK_CTL1 _MMIO(0x101100)
1779#define VLV_CLK_CTL2 _MMIO(0x101104)
1780#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
1781
1782/*
1783 * Overlay regs
1784 */
1785
1786#define OVADD _MMIO(0x30000)
1787#define DOVSTA _MMIO(0x30008)
1788#define OC_BUF (0x3 << 20)
1789#define OGAMC5 _MMIO(0x30010)
1790#define OGAMC4 _MMIO(0x30014)
1791#define OGAMC3 _MMIO(0x30018)
1792#define OGAMC2 _MMIO(0x3001c)
1793#define OGAMC1 _MMIO(0x30020)
1794#define OGAMC0 _MMIO(0x30024)
1795
1796/*
1797 * GEN9 clock gating regs
1798 */
1799#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
1800#define DARBF_GATING_DIS REG_BIT(27)
1801#define MTL_PIPEDMC_GATING_DIS_A REG_BIT(15)
1802#define MTL_PIPEDMC_GATING_DIS_B REG_BIT(14)
1803#define PWM2_GATING_DIS REG_BIT(14)
1804#define PWM1_GATING_DIS REG_BIT(13)
1805
1806#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
1807#define TGL_VRH_GATING_DIS REG_BIT(31)
1808#define DPT_GATING_DIS REG_BIT(22)
1809
1810#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
1811#define BXT_GMBUS_GATING_DIS (1 << 14)
1812
1813#define GEN9_CLKGATE_DIS_5 _MMIO(0x46540)
1814#define DPCE_GATING_DIS REG_BIT(17)
1815
1816#define _CLKGATE_DIS_PSL_A 0x46520
1817#define _CLKGATE_DIS_PSL_B 0x46524
1818#define _CLKGATE_DIS_PSL_C 0x46528
1819#define DUPS1_GATING_DIS (1 << 15)
1820#define DUPS2_GATING_DIS (1 << 19)
1821#define DUPS3_GATING_DIS (1 << 23)
1822#define CURSOR_GATING_DIS REG_BIT(28)
1823#define DPF_GATING_DIS (1 << 10)
1824#define DPF_RAM_GATING_DIS (1 << 9)
1825#define DPFR_GATING_DIS (1 << 8)
1826
1827#define CLKGATE_DIS_PSL(pipe) \
1828 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_A, _CLKGATE_DIS_PSL_B)
1829
1830#define _CLKGATE_DIS_PSL_EXT_A 0x4654C
1831#define _CLKGATE_DIS_PSL_EXT_B 0x46550
1832#define PIPEDMC_GATING_DIS REG_BIT(12)
1833
1834#define CLKGATE_DIS_PSL_EXT(pipe) \
1835 _MMIO_PIPE(pipe, _CLKGATE_DIS_PSL_EXT_A, _CLKGATE_DIS_PSL_EXT_B)
1836
1837/* DDI Buffer Control */
1838#define _DDI_CLK_VALFREQ_A 0x64030
1839#define _DDI_CLK_VALFREQ_B 0x64130
1840#define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B)
1841
1842/*
1843 * Display engine regs
1844 */
1845
1846/* Pipe A CRC regs */
1847#define _PIPE_CRC_CTL_A 0x60050
1848#define PIPE_CRC_ENABLE REG_BIT(31)
1849/* skl+ source selection */
1850#define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28)
1851#define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0)
1852#define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2)
1853#define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4)
1854#define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6)
1855#define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7)
1856#define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5)
1857#define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3)
1858#define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1)
1859/* ivb+ source selection */
1860#define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29)
1861#define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0)
1862#define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1)
1863#define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2)
1864/* ilk+ source selection */
1865#define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28)
1866#define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0)
1867#define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1)
1868#define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2)
1869/* embedded DP port on the north display block */
1870#define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4)
1871#define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5)
1872/* vlv source selection */
1873#define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27)
1874#define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0)
1875#define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1)
1876#define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2)
1877/* with DP port the pipe source is invalid */
1878#define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3)
1879#define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6)
1880#define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7)
1881/* gen3+ source selection */
1882#define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28)
1883#define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0)
1884#define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1)
1885#define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2)
1886/* with DP/TV port the pipe source is invalid */
1887#define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3)
1888#define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4)
1889#define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5)
1890#define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6)
1891#define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7)
1892/* gen2 doesn't have source selection bits */
1893#define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30)
1894
1895#define _PIPE_CRC_RES_1_A_IVB 0x60064
1896#define _PIPE_CRC_RES_2_A_IVB 0x60068
1897#define _PIPE_CRC_RES_3_A_IVB 0x6006c
1898#define _PIPE_CRC_RES_4_A_IVB 0x60070
1899#define _PIPE_CRC_RES_5_A_IVB 0x60074
1900
1901#define _PIPE_CRC_RES_RED_A 0x60060
1902#define _PIPE_CRC_RES_GREEN_A 0x60064
1903#define _PIPE_CRC_RES_BLUE_A 0x60068
1904#define _PIPE_CRC_RES_RES1_A_I915 0x6006c
1905#define _PIPE_CRC_RES_RES2_A_G4X 0x60080
1906
1907/* Pipe B CRC regs */
1908#define _PIPE_CRC_RES_1_B_IVB 0x61064
1909#define _PIPE_CRC_RES_2_B_IVB 0x61068
1910#define _PIPE_CRC_RES_3_B_IVB 0x6106c
1911#define _PIPE_CRC_RES_4_B_IVB 0x61070
1912#define _PIPE_CRC_RES_5_B_IVB 0x61074
1913
1914#define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A)
1915#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB)
1916#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB)
1917#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB)
1918#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB)
1919#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB)
1920
1921#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A)
1922#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A)
1923#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A)
1924#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
1925#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
1926
1927/* Pipe/transcoder A timing regs */
1928#define _TRANS_HTOTAL_A 0x60000
1929#define HTOTAL_MASK REG_GENMASK(31, 16)
1930#define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal))
1931#define HACTIVE_MASK REG_GENMASK(15, 0)
1932#define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay))
1933#define _TRANS_HBLANK_A 0x60004
1934#define HBLANK_END_MASK REG_GENMASK(31, 16)
1935#define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end))
1936#define HBLANK_START_MASK REG_GENMASK(15, 0)
1937#define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start))
1938#define _TRANS_HSYNC_A 0x60008
1939#define HSYNC_END_MASK REG_GENMASK(31, 16)
1940#define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end))
1941#define HSYNC_START_MASK REG_GENMASK(15, 0)
1942#define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start))
1943#define _TRANS_VTOTAL_A 0x6000c
1944#define VTOTAL_MASK REG_GENMASK(31, 16)
1945#define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal))
1946#define VACTIVE_MASK REG_GENMASK(15, 0)
1947#define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay))
1948#define _TRANS_VBLANK_A 0x60010
1949#define VBLANK_END_MASK REG_GENMASK(31, 16)
1950#define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end))
1951#define VBLANK_START_MASK REG_GENMASK(15, 0)
1952#define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start))
1953#define _TRANS_VSYNC_A 0x60014
1954#define VSYNC_END_MASK REG_GENMASK(31, 16)
1955#define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end))
1956#define VSYNC_START_MASK REG_GENMASK(15, 0)
1957#define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start))
1958#define _TRANS_EXITLINE_A 0x60018
1959#define _PIPEASRC 0x6001c
1960#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
1961#define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
1962#define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
1963#define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
1964#define _BCLRPAT_A 0x60020
1965#define _TRANS_VSYNCSHIFT_A 0x60028
1966#define _TRANS_MULT_A 0x6002c
1967
1968/* Pipe/transcoder B timing regs */
1969#define _TRANS_HTOTAL_B 0x61000
1970#define _TRANS_HBLANK_B 0x61004
1971#define _TRANS_HSYNC_B 0x61008
1972#define _TRANS_VTOTAL_B 0x6100c
1973#define _TRANS_VBLANK_B 0x61010
1974#define _TRANS_VSYNC_B 0x61014
1975#define _PIPEBSRC 0x6101c
1976#define _BCLRPAT_B 0x61020
1977#define _TRANS_VSYNCSHIFT_B 0x61028
1978#define _TRANS_MULT_B 0x6102c
1979
1980/* DSI 0 timing regs */
1981#define _TRANS_HTOTAL_DSI0 0x6b000
1982#define _TRANS_HSYNC_DSI0 0x6b008
1983#define _TRANS_VTOTAL_DSI0 0x6b00c
1984#define _TRANS_VSYNC_DSI0 0x6b014
1985#define _TRANS_VSYNCSHIFT_DSI0 0x6b028
1986
1987/* DSI 1 timing regs */
1988#define _TRANS_HTOTAL_DSI1 0x6b800
1989#define _TRANS_HSYNC_DSI1 0x6b808
1990#define _TRANS_VTOTAL_DSI1 0x6b80c
1991#define _TRANS_VSYNC_DSI1 0x6b814
1992#define _TRANS_VSYNCSHIFT_DSI1 0x6b828
1993
1994#define TRANS_HTOTAL(trans) _MMIO_TRANS2((trans), _TRANS_HTOTAL_A)
1995#define TRANS_HBLANK(trans) _MMIO_TRANS2((trans), _TRANS_HBLANK_A)
1996#define TRANS_HSYNC(trans) _MMIO_TRANS2((trans), _TRANS_HSYNC_A)
1997#define TRANS_VTOTAL(trans) _MMIO_TRANS2((trans), _TRANS_VTOTAL_A)
1998#define TRANS_VBLANK(trans) _MMIO_TRANS2((trans), _TRANS_VBLANK_A)
1999#define TRANS_VSYNC(trans) _MMIO_TRANS2((trans), _TRANS_VSYNC_A)
2000#define BCLRPAT(trans) _MMIO_TRANS2((trans), _BCLRPAT_A)
2001#define TRANS_VSYNCSHIFT(trans) _MMIO_TRANS2((trans), _TRANS_VSYNCSHIFT_A)
2002#define PIPESRC(pipe) _MMIO_TRANS2((pipe), _PIPEASRC)
2003#define TRANS_MULT(trans) _MMIO_TRANS2((trans), _TRANS_MULT_A)
2004
2005/* VRR registers */
2006#define _TRANS_VRR_CTL_A 0x60420
2007#define _TRANS_VRR_CTL_B 0x61420
2008#define _TRANS_VRR_CTL_C 0x62420
2009#define _TRANS_VRR_CTL_D 0x63420
2010#define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A)
2011#define VRR_CTL_VRR_ENABLE REG_BIT(31)
2012#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
2013#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
2014#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
2015#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
2016#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
2017#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
2018#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
2019
2020#define _TRANS_VRR_VMAX_A 0x60424
2021#define _TRANS_VRR_VMAX_B 0x61424
2022#define _TRANS_VRR_VMAX_C 0x62424
2023#define _TRANS_VRR_VMAX_D 0x63424
2024#define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A)
2025#define VRR_VMAX_MASK REG_GENMASK(19, 0)
2026
2027#define _TRANS_VRR_VMIN_A 0x60434
2028#define _TRANS_VRR_VMIN_B 0x61434
2029#define _TRANS_VRR_VMIN_C 0x62434
2030#define _TRANS_VRR_VMIN_D 0x63434
2031#define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A)
2032#define VRR_VMIN_MASK REG_GENMASK(15, 0)
2033
2034#define _TRANS_VRR_VMAXSHIFT_A 0x60428
2035#define _TRANS_VRR_VMAXSHIFT_B 0x61428
2036#define _TRANS_VRR_VMAXSHIFT_C 0x62428
2037#define _TRANS_VRR_VMAXSHIFT_D 0x63428
2038#define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \
2039 _TRANS_VRR_VMAXSHIFT_A)
2040#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
2041#define VRR_VMAXSHIFT_DEC REG_BIT(16)
2042#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
2043
2044#define _TRANS_VRR_STATUS_A 0x6042C
2045#define _TRANS_VRR_STATUS_B 0x6142C
2046#define _TRANS_VRR_STATUS_C 0x6242C
2047#define _TRANS_VRR_STATUS_D 0x6342C
2048#define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A)
2049#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
2050#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
2051#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
2052#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
2053#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
2054#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
2055#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
2056#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
2057#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
2058#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
2059#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
2060#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
2061#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
2062#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
2063
2064#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
2065#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
2066#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
2067#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
2068#define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \
2069 _TRANS_VRR_VTOTAL_PREV_A)
2070#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
2071#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
2072#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
2073#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
2074
2075#define _TRANS_VRR_FLIPLINE_A 0x60438
2076#define _TRANS_VRR_FLIPLINE_B 0x61438
2077#define _TRANS_VRR_FLIPLINE_C 0x62438
2078#define _TRANS_VRR_FLIPLINE_D 0x63438
2079#define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \
2080 _TRANS_VRR_FLIPLINE_A)
2081#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
2082
2083#define _TRANS_VRR_STATUS2_A 0x6043C
2084#define _TRANS_VRR_STATUS2_B 0x6143C
2085#define _TRANS_VRR_STATUS2_C 0x6243C
2086#define _TRANS_VRR_STATUS2_D 0x6343C
2087#define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A)
2088#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
2089
2090#define _TRANS_PUSH_A 0x60A70
2091#define _TRANS_PUSH_B 0x61A70
2092#define _TRANS_PUSH_C 0x62A70
2093#define _TRANS_PUSH_D 0x63A70
2094#define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A)
2095#define TRANS_PUSH_EN REG_BIT(31)
2096#define TRANS_PUSH_SEND REG_BIT(30)
2097
2098/* VGA port control */
2099#define ADPA _MMIO(0x61100)
2100#define PCH_ADPA _MMIO(0xe1100)
2101#define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
2102
2103#define ADPA_DAC_ENABLE (1 << 31)
2104#define ADPA_DAC_DISABLE 0
2105#define ADPA_PIPE_SEL_SHIFT 30
2106#define ADPA_PIPE_SEL_MASK (1 << 30)
2107#define ADPA_PIPE_SEL(pipe) ((pipe) << 30)
2108#define ADPA_PIPE_SEL_SHIFT_CPT 29
2109#define ADPA_PIPE_SEL_MASK_CPT (3 << 29)
2110#define ADPA_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2111#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2112#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0 << 24)
2113#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3 << 24)
2114#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3 << 24)
2115#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2 << 24)
2116#define ADPA_CRT_HOTPLUG_ENABLE (1 << 23)
2117#define ADPA_CRT_HOTPLUG_PERIOD_64 (0 << 22)
2118#define ADPA_CRT_HOTPLUG_PERIOD_128 (1 << 22)
2119#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0 << 21)
2120#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1 << 21)
2121#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0 << 20)
2122#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1 << 20)
2123#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0 << 18)
2124#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1 << 18)
2125#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2 << 18)
2126#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3 << 18)
2127#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0 << 17)
2128#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1 << 17)
2129#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1 << 16)
2130#define ADPA_USE_VGA_HVPOLARITY (1 << 15)
2131#define ADPA_SETS_HVPOLARITY 0
2132#define ADPA_VSYNC_CNTL_DISABLE (1 << 10)
2133#define ADPA_VSYNC_CNTL_ENABLE 0
2134#define ADPA_HSYNC_CNTL_DISABLE (1 << 11)
2135#define ADPA_HSYNC_CNTL_ENABLE 0
2136#define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
2137#define ADPA_VSYNC_ACTIVE_LOW 0
2138#define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
2139#define ADPA_HSYNC_ACTIVE_LOW 0
2140#define ADPA_DPMS_MASK (~(3 << 10))
2141#define ADPA_DPMS_ON (0 << 10)
2142#define ADPA_DPMS_SUSPEND (1 << 10)
2143#define ADPA_DPMS_STANDBY (2 << 10)
2144#define ADPA_DPMS_OFF (3 << 10)
2145
2146
2147/* Hotplug control (945+ only) */
2148#define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
2149#define PORTB_HOTPLUG_INT_EN (1 << 29)
2150#define PORTC_HOTPLUG_INT_EN (1 << 28)
2151#define PORTD_HOTPLUG_INT_EN (1 << 27)
2152#define SDVOB_HOTPLUG_INT_EN (1 << 26)
2153#define SDVOC_HOTPLUG_INT_EN (1 << 25)
2154#define TV_HOTPLUG_INT_EN (1 << 18)
2155#define CRT_HOTPLUG_INT_EN (1 << 9)
2156#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
2157 PORTC_HOTPLUG_INT_EN | \
2158 PORTD_HOTPLUG_INT_EN | \
2159 SDVOC_HOTPLUG_INT_EN | \
2160 SDVOB_HOTPLUG_INT_EN | \
2161 CRT_HOTPLUG_INT_EN)
2162#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
2163#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
2164/* must use period 64 on GM45 according to docs */
2165#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
2166#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
2167#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
2168#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
2169#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
2170#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
2171#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
2172#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
2173#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
2174#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
2175#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
2176#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
2177
2178#define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
2179/* HDMI/DP bits are g4x+ */
2180#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
2181#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
2182#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
2183#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
2184#define PORTD_HOTPLUG_INT_LONG_PULSE (2 << 21)
2185#define PORTD_HOTPLUG_INT_SHORT_PULSE (1 << 21)
2186#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
2187#define PORTC_HOTPLUG_INT_LONG_PULSE (2 << 19)
2188#define PORTC_HOTPLUG_INT_SHORT_PULSE (1 << 19)
2189#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
2190#define PORTB_HOTPLUG_INT_LONG_PULSE (2 << 17)
2191#define PORTB_HOTPLUG_INT_SHORT_PLUSE (1 << 17)
2192/* CRT/TV common between gen3+ */
2193#define CRT_HOTPLUG_INT_STATUS (1 << 11)
2194#define TV_HOTPLUG_INT_STATUS (1 << 10)
2195#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
2196#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
2197#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
2198#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
2199#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
2200#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
2201#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
2202#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
2203
2204/* SDVO is different across gen3/4 */
2205#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
2206#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
2207/*
2208 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
2209 * since reality corrobates that they're the same as on gen3. But keep these
2210 * bits here (and the comment!) to help any other lost wanderers back onto the
2211 * right tracks.
2212 */
2213#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
2214#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
2215#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
2216#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
2217#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
2218 SDVOB_HOTPLUG_INT_STATUS_G4X | \
2219 SDVOC_HOTPLUG_INT_STATUS_G4X | \
2220 PORTB_HOTPLUG_INT_STATUS | \
2221 PORTC_HOTPLUG_INT_STATUS | \
2222 PORTD_HOTPLUG_INT_STATUS)
2223
2224#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
2225 SDVOB_HOTPLUG_INT_STATUS_I915 | \
2226 SDVOC_HOTPLUG_INT_STATUS_I915 | \
2227 PORTB_HOTPLUG_INT_STATUS | \
2228 PORTC_HOTPLUG_INT_STATUS | \
2229 PORTD_HOTPLUG_INT_STATUS)
2230
2231/* SDVO and HDMI port control.
2232 * The same register may be used for SDVO or HDMI */
2233#define _GEN3_SDVOB 0x61140
2234#define _GEN3_SDVOC 0x61160
2235#define GEN3_SDVOB _MMIO(_GEN3_SDVOB)
2236#define GEN3_SDVOC _MMIO(_GEN3_SDVOC)
2237#define GEN4_HDMIB GEN3_SDVOB
2238#define GEN4_HDMIC GEN3_SDVOC
2239#define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
2240#define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
2241#define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
2242#define PCH_SDVOB _MMIO(0xe1140)
2243#define PCH_HDMIB PCH_SDVOB
2244#define PCH_HDMIC _MMIO(0xe1150)
2245#define PCH_HDMID _MMIO(0xe1160)
2246
2247#define PORT_DFT_I9XX _MMIO(0x61150)
2248#define DC_BALANCE_RESET (1 << 25)
2249#define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
2250#define DC_BALANCE_RESET_VLV (1 << 31)
2251#define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0))
2252#define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */
2253#define PIPE_B_SCRAMBLE_RESET REG_BIT(1)
2254#define PIPE_A_SCRAMBLE_RESET REG_BIT(0)
2255
2256/* Gen 3 SDVO bits: */
2257#define SDVO_ENABLE (1 << 31)
2258#define SDVO_PIPE_SEL_SHIFT 30
2259#define SDVO_PIPE_SEL_MASK (1 << 30)
2260#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
2261#define SDVO_STALL_SELECT (1 << 29)
2262#define SDVO_INTERRUPT_ENABLE (1 << 26)
2263/*
2264 * 915G/GM SDVO pixel multiplier.
2265 * Programmed value is multiplier - 1, up to 5x.
2266 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
2267 */
2268#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
2269#define SDVO_PORT_MULTIPLY_SHIFT 23
2270#define SDVO_PHASE_SELECT_MASK (15 << 19)
2271#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
2272#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
2273#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
2274#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
2275#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
2276#define SDVO_DETECTED (1 << 2)
2277/* Bits to be preserved when writing */
2278#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
2279 SDVO_INTERRUPT_ENABLE)
2280#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
2281
2282/* Gen 4 SDVO/HDMI bits: */
2283#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
2284#define SDVO_COLOR_FORMAT_MASK (7 << 26)
2285#define SDVO_ENCODING_SDVO (0 << 10)
2286#define SDVO_ENCODING_HDMI (2 << 10)
2287#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
2288#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
2289#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
2290#define HDMI_AUDIO_ENABLE (1 << 6) /* HDMI only */
2291/* VSYNC/HSYNC bits new with 965, default is to be set */
2292#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
2293#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
2294
2295/* Gen 5 (IBX) SDVO/HDMI bits: */
2296#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
2297#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
2298
2299/* Gen 6 (CPT) SDVO/HDMI bits: */
2300#define SDVO_PIPE_SEL_SHIFT_CPT 29
2301#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
2302#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2303
2304/* CHV SDVO/HDMI bits: */
2305#define SDVO_PIPE_SEL_SHIFT_CHV 24
2306#define SDVO_PIPE_SEL_MASK_CHV (3 << 24)
2307#define SDVO_PIPE_SEL_CHV(pipe) ((pipe) << 24)
2308
2309/* Video Data Island Packet control */
2310#define VIDEO_DIP_DATA _MMIO(0x61178)
2311/* Read the description of VIDEO_DIP_DATA (before Haswell) or VIDEO_DIP_ECC
2312 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
2313 * of the infoframe structure specified by CEA-861. */
2314#define VIDEO_DIP_DATA_SIZE 32
2315#define VIDEO_DIP_GMP_DATA_SIZE 36
2316#define VIDEO_DIP_VSC_DATA_SIZE 36
2317#define VIDEO_DIP_PPS_DATA_SIZE 132
2318#define VIDEO_DIP_CTL _MMIO(0x61170)
2319/* Pre HSW: */
2320#define VIDEO_DIP_ENABLE (1 << 31)
2321#define VIDEO_DIP_PORT(port) ((port) << 29)
2322#define VIDEO_DIP_PORT_MASK (3 << 29)
2323#define VIDEO_DIP_ENABLE_GCP (1 << 25) /* ilk+ */
2324#define VIDEO_DIP_ENABLE_AVI (1 << 21)
2325#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
2326#define VIDEO_DIP_ENABLE_GAMUT (4 << 21) /* ilk+ */
2327#define VIDEO_DIP_ENABLE_SPD (8 << 21)
2328#define VIDEO_DIP_SELECT_AVI (0 << 19)
2329#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
2330#define VIDEO_DIP_SELECT_GAMUT (2 << 19)
2331#define VIDEO_DIP_SELECT_SPD (3 << 19)
2332#define VIDEO_DIP_SELECT_MASK (3 << 19)
2333#define VIDEO_DIP_FREQ_ONCE (0 << 16)
2334#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
2335#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
2336#define VIDEO_DIP_FREQ_MASK (3 << 16)
2337/* HSW and later: */
2338#define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28)
2339#define PSR_VSC_BIT_7_SET (1 << 27)
2340#define VSC_SELECT_MASK (0x3 << 25)
2341#define VSC_SELECT_SHIFT 25
2342#define VSC_DIP_HW_HEA_DATA (0 << 25)
2343#define VSC_DIP_HW_HEA_SW_DATA (1 << 25)
2344#define VSC_DIP_HW_DATA_SW_HEA (2 << 25)
2345#define VSC_DIP_SW_HEA_DATA (3 << 25)
2346#define VDIP_ENABLE_PPS (1 << 24)
2347#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
2348#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
2349#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
2350#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
2351#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
2352#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
2353
2354/* Panel fitting */
2355#define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
2356#define PFIT_ENABLE REG_BIT(31)
2357#define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */
2358#define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe))
2359#define PFIT_SCALING_MASK REG_GENMASK(28, 26) /* 965+ */
2360#define PFIT_SCALING_AUTO REG_FIELD_PREP(PFIT_SCALING_MASK, 0)
2361#define PFIT_SCALING_PROGRAMMED REG_FIELD_PREP(PFIT_SCALING_MASK, 1)
2362#define PFIT_SCALING_PILLAR REG_FIELD_PREP(PFIT_SCALING_MASK, 2)
2363#define PFIT_SCALING_LETTER REG_FIELD_PREP(PFIT_SCALING_MASK, 3)
2364#define PFIT_FILTER_MASK REG_GENMASK(25, 24) /* 965+ */
2365#define PFIT_FILTER_FUZZY REG_FIELD_PREP(PFIT_FILTER_MASK, 0)
2366#define PFIT_FILTER_CRISP REG_FIELD_PREP(PFIT_FILTER_MASK, 1)
2367#define PFIT_FILTER_MEDIAN REG_FIELD_PREP(PFIT_FILTER_MASK, 2)
2368#define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */
2369#define PFIT_VERT_INTERP_BILINEAR REG_FIELD_PREP(PFIT_VERT_INTERP_MASK, 1)
2370#define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */
2371#define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */
2372#define PFIT_HORIZ_INTERP_BILINEAR REG_FIELD_PREP(PFIT_HORIZ_INTERP_MASK, 1)
2373#define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */
2374#define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */
2375
2376#define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
2377#define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */
2378#define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x))
2379#define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */
2380#define PFIT_HORIZ_SCALE(x) REG_FIELD_PREP(PFIT_HORIZ_SCALE_MASK, (x))
2381#define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */
2382#define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */
2383
2384#define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
2385
2386#define PCH_GTC_CTL _MMIO(0xe7000)
2387#define PCH_GTC_ENABLE (1 << 31)
2388
2389/* Display Port */
2390#define DP_A _MMIO(0x64000) /* eDP */
2391#define DP_B _MMIO(0x64100)
2392#define DP_C _MMIO(0x64200)
2393#define DP_D _MMIO(0x64300)
2394
2395#define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
2396#define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
2397#define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
2398
2399#define DP_PORT_EN (1 << 31)
2400#define DP_PIPE_SEL_SHIFT 30
2401#define DP_PIPE_SEL_MASK (1 << 30)
2402#define DP_PIPE_SEL(pipe) ((pipe) << 30)
2403#define DP_PIPE_SEL_SHIFT_IVB 29
2404#define DP_PIPE_SEL_MASK_IVB (3 << 29)
2405#define DP_PIPE_SEL_IVB(pipe) ((pipe) << 29)
2406#define DP_PIPE_SEL_SHIFT_CHV 16
2407#define DP_PIPE_SEL_MASK_CHV (3 << 16)
2408#define DP_PIPE_SEL_CHV(pipe) ((pipe) << 16)
2409
2410/* Link training mode - select a suitable mode for each stage */
2411#define DP_LINK_TRAIN_PAT_1 (0 << 28)
2412#define DP_LINK_TRAIN_PAT_2 (1 << 28)
2413#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
2414#define DP_LINK_TRAIN_OFF (3 << 28)
2415#define DP_LINK_TRAIN_MASK (3 << 28)
2416#define DP_LINK_TRAIN_SHIFT 28
2417
2418/* CPT Link training mode */
2419#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
2420#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
2421#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
2422#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
2423#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
2424#define DP_LINK_TRAIN_SHIFT_CPT 8
2425
2426/* Signal voltages. These are mostly controlled by the other end */
2427#define DP_VOLTAGE_0_4 (0 << 25)
2428#define DP_VOLTAGE_0_6 (1 << 25)
2429#define DP_VOLTAGE_0_8 (2 << 25)
2430#define DP_VOLTAGE_1_2 (3 << 25)
2431#define DP_VOLTAGE_MASK (7 << 25)
2432#define DP_VOLTAGE_SHIFT 25
2433
2434/* Signal pre-emphasis levels, like voltages, the other end tells us what
2435 * they want
2436 */
2437#define DP_PRE_EMPHASIS_0 (0 << 22)
2438#define DP_PRE_EMPHASIS_3_5 (1 << 22)
2439#define DP_PRE_EMPHASIS_6 (2 << 22)
2440#define DP_PRE_EMPHASIS_9_5 (3 << 22)
2441#define DP_PRE_EMPHASIS_MASK (7 << 22)
2442#define DP_PRE_EMPHASIS_SHIFT 22
2443
2444/* How many wires to use. I guess 3 was too hard */
2445#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
2446#define DP_PORT_WIDTH_MASK (7 << 19)
2447#define DP_PORT_WIDTH_SHIFT 19
2448
2449/* Mystic DPCD version 1.1 special mode */
2450#define DP_ENHANCED_FRAMING (1 << 18)
2451
2452/* eDP */
2453#define DP_PLL_FREQ_270MHZ (0 << 16)
2454#define DP_PLL_FREQ_162MHZ (1 << 16)
2455#define DP_PLL_FREQ_MASK (3 << 16)
2456
2457/* locked once port is enabled */
2458#define DP_PORT_REVERSAL (1 << 15)
2459
2460/* eDP */
2461#define DP_PLL_ENABLE (1 << 14)
2462
2463/* sends the clock on lane 15 of the PEG for debug */
2464#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
2465
2466#define DP_SCRAMBLING_DISABLE (1 << 12)
2467#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
2468
2469/* limit RGB values to avoid confusing TVs */
2470#define DP_COLOR_RANGE_16_235 (1 << 8)
2471
2472/* Turn on the audio link */
2473#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
2474
2475/* vs and hs sync polarity */
2476#define DP_SYNC_VS_HIGH (1 << 4)
2477#define DP_SYNC_HS_HIGH (1 << 3)
2478
2479/* A fantasy */
2480#define DP_DETECTED (1 << 2)
2481
2482/*
2483 * Computing GMCH M and N values for the Display Port link
2484 *
2485 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2486 *
2487 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2488 *
2489 * The GMCH value is used internally
2490 *
2491 * bytes_per_pixel is the number of bytes coming out of the plane,
2492 * which is after the LUTs, so we want the bytes for our color format.
2493 * For our current usage, this is always 3, one byte for R, G and B.
2494 */
2495#define _PIPEA_DATA_M_G4X 0x70050
2496#define _PIPEB_DATA_M_G4X 0x71050
2497
2498/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2499#define TU_SIZE_MASK REG_GENMASK(30, 25)
2500#define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
2501
2502#define DATA_LINK_M_N_MASK REG_GENMASK(23, 0)
2503#define DATA_LINK_N_MAX (0x800000)
2504
2505#define _PIPEA_DATA_N_G4X 0x70054
2506#define _PIPEB_DATA_N_G4X 0x71054
2507
2508/*
2509 * Computing Link M and N values for the Display Port link
2510 *
2511 * Link M / N = pixel_clock / ls_clk
2512 *
2513 * (the DP spec calls pixel_clock the 'strm_clk')
2514 *
2515 * The Link value is transmitted in the Main Stream
2516 * Attributes and VB-ID.
2517 */
2518
2519#define _PIPEA_LINK_M_G4X 0x70060
2520#define _PIPEB_LINK_M_G4X 0x71060
2521#define _PIPEA_LINK_N_G4X 0x70064
2522#define _PIPEB_LINK_N_G4X 0x71064
2523
2524#define PIPE_DATA_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
2525#define PIPE_DATA_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
2526#define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
2527#define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
2528
2529/* Display & cursor control */
2530
2531/* Pipe A */
2532#define _PIPEADSL 0x70000
2533#define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
2534#define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
2535#define _TRANSACONF 0x70008
2536#define TRANSCONF_ENABLE REG_BIT(31)
2537#define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
2538#define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */
2539#define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
2540#define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
2541#define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
2542#define TRANSCONF_PIPE_LOCKED REG_BIT(25)
2543#define TRANSCONF_FORCE_BORDER REG_BIT(25)
2544#define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
2545#define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
2546#define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0)
2547#define TRANSCONF_GAMMA_MODE_10BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1)
2548#define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
2549#define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
2550#define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
2551#define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */
2552#define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0)
2553#define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */
2554#define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */
2555#define TRANSCONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6)
2556#define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */
2557/*
2558 * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
2559 * DBL=power saving pixel doubling, PF-ID* requires panel fitter
2560 */
2561#define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */
2562#define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */
2563#define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0)
2564#define TRANSCONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1)
2565#define TRANSCONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3)
2566#define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
2567#define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
2568#define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
2569#define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */
2570#define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x))
2571#define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16)
2572#define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */
2573#define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
2574#define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13)
2575#define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
2576#define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
2577#define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
2578#define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
2579#define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
2580#define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
2581#define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0)
2582#define TRANSCONF_BPC_10 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1)
2583#define TRANSCONF_BPC_6 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2)
2584#define TRANSCONF_BPC_12 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3)
2585#define TRANSCONF_DITHER_EN REG_BIT(4)
2586#define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
2587#define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0)
2588#define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1)
2589#define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2)
2590#define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3)
2591#define _PIPEASTAT 0x70024
2592#define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
2593#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
2594#define PIPE_CRC_ERROR_ENABLE (1UL << 29)
2595#define PIPE_CRC_DONE_ENABLE (1UL << 28)
2596#define PERF_COUNTER2_INTERRUPT_EN (1UL << 27)
2597#define PIPE_GMBUS_EVENT_ENABLE (1UL << 27)
2598#define PLANE_FLIP_DONE_INT_EN_VLV (1UL << 26)
2599#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL << 26)
2600#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL << 25)
2601#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL << 24)
2602#define PIPE_DPST_EVENT_ENABLE (1UL << 23)
2603#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL << 22)
2604#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL << 22)
2605#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL << 21)
2606#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL << 20)
2607#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL << 19)
2608#define PERF_COUNTER_INTERRUPT_EN (1UL << 19)
2609#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
2610#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18) /* 965 or later */
2611#define PIPE_FRAMESTART_INTERRUPT_ENABLE (1UL << 17)
2612#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
2613#define PIPEA_HBLANK_INT_EN_VLV (1UL << 16)
2614#define PIPE_OVERLAY_UPDATED_ENABLE (1UL << 16)
2615#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL << 15)
2616#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL << 14)
2617#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL << 13)
2618#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL << 12)
2619#define PERF_COUNTER2_INTERRUPT_STATUS (1UL << 11)
2620#define PIPE_GMBUS_INTERRUPT_STATUS (1UL << 11)
2621#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL << 10)
2622#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
2623#define PIPE_VSYNC_INTERRUPT_STATUS (1UL << 9)
2624#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL << 8)
2625#define PIPE_DPST_EVENT_STATUS (1UL << 7)
2626#define PIPE_A_PSR_STATUS_VLV (1UL << 6)
2627#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL << 6)
2628#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL << 5)
2629#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL << 4)
2630#define PIPE_B_PSR_STATUS_VLV (1UL << 3)
2631#define PERF_COUNTER_INTERRUPT_STATUS (1UL << 3)
2632#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
2633#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2) /* 965 or later */
2634#define PIPE_FRAMESTART_INTERRUPT_STATUS (1UL << 1)
2635#define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
2636#define PIPE_HBLANK_INT_STATUS (1UL << 0)
2637#define PIPE_OVERLAY_UPDATED_STATUS (1UL << 0)
2638
2639#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
2640#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
2641
2642#define TRANSCONF(trans) _MMIO_PIPE2((trans), _TRANSACONF)
2643#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
2644#define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
2645#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
2646#define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT)
2647
2648#define _PIPEAGCMAX 0x70010
2649#define _PIPEBGCMAX 0x71010
2650#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */
2651
2652#define _PIPE_ARB_CTL_A 0x70028 /* icl+ */
2653#define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A)
2654#define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
2655
2656#define _PIPE_MISC_A 0x70030
2657#define _PIPE_MISC_B 0x71030
2658#define PIPE_MISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
2659#define PIPE_MISC_YUV420_MODE_FULL_BLEND REG_BIT(26) /* glk+ */
2660#define PIPE_MISC_HDR_MODE_PRECISION REG_BIT(23) /* icl+ */
2661#define PIPE_MISC_PSR_MASK_PRIMARY_FLIP REG_BIT(23) /* bdw */
2662#define PIPE_MISC_PSR_MASK_SPRITE_ENABLE REG_BIT(22) /* bdw */
2663#define PIPE_MISC_PSR_MASK_PIPE_REG_WRITE REG_BIT(21) /* skl+ */
2664#define PIPE_MISC_PSR_MASK_CURSOR_MOVE REG_BIT(21) /* bdw */
2665#define PIPE_MISC_PSR_MASK_VBLANK_VSYNC_INT REG_BIT(20)
2666#define PIPE_MISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
2667#define PIPE_MISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
2668/*
2669 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
2670 * valid values of: 6, 8, 10 BPC.
2671 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
2672 * 6, 8, 10, 12 BPC.
2673 */
2674#define PIPE_MISC_BPC_MASK REG_GENMASK(7, 5)
2675#define PIPE_MISC_BPC_8 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0)
2676#define PIPE_MISC_BPC_10 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 1)
2677#define PIPE_MISC_BPC_6 REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 2)
2678#define PIPE_MISC_BPC_12_ADLP REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 4) /* adlp+ */
2679#define PIPE_MISC_DITHER_ENABLE REG_BIT(4)
2680#define PIPE_MISC_DITHER_TYPE_MASK REG_GENMASK(3, 2)
2681#define PIPE_MISC_DITHER_TYPE_SP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0)
2682#define PIPE_MISC_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 1)
2683#define PIPE_MISC_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 2)
2684#define PIPE_MISC_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 3)
2685#define PIPE_MISC(pipe) _MMIO_PIPE(pipe, _PIPE_MISC_A, _PIPE_MISC_B)
2686
2687#define _PIPE_MISC2_A 0x7002C
2688#define _PIPE_MISC2_B 0x7102C
2689#define PIPE_MISC2_BUBBLE_COUNTER_MASK REG_GENMASK(31, 24)
2690#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)
2691#define PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)
2692#define PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK REG_GENMASK(2, 0) /* tgl+ */
2693#define PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id) REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
2694#define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B)
2695
2696#define _ICL_PIPE_A_STATUS 0x70058
2697#define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS)
2698#define PIPE_STATUS_UNDERRUN REG_BIT(31)
2699#define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28)
2700#define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27)
2701#define PIPE_STATUS_PORT_UNDERRUN_XELPD REG_BIT(26)
2702
2703#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
2704#define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
2705#define PIPEB_HLINE_INT_EN REG_BIT(28)
2706#define PIPEB_VBLANK_INT_EN REG_BIT(27)
2707#define SPRITED_FLIP_DONE_INT_EN REG_BIT(26)
2708#define SPRITEC_FLIP_DONE_INT_EN REG_BIT(25)
2709#define PLANEB_FLIP_DONE_INT_EN REG_BIT(24)
2710#define PIPE_PSR_INT_EN REG_BIT(22)
2711#define PIPEA_LINE_COMPARE_INT_EN REG_BIT(21)
2712#define PIPEA_HLINE_INT_EN REG_BIT(20)
2713#define PIPEA_VBLANK_INT_EN REG_BIT(19)
2714#define SPRITEB_FLIP_DONE_INT_EN REG_BIT(18)
2715#define SPRITEA_FLIP_DONE_INT_EN REG_BIT(17)
2716#define PLANEA_FLIPDONE_INT_EN REG_BIT(16)
2717#define PIPEC_LINE_COMPARE_INT_EN REG_BIT(13)
2718#define PIPEC_HLINE_INT_EN REG_BIT(12)
2719#define PIPEC_VBLANK_INT_EN REG_BIT(11)
2720#define SPRITEF_FLIPDONE_INT_EN REG_BIT(10)
2721#define SPRITEE_FLIPDONE_INT_EN REG_BIT(9)
2722#define PLANEC_FLIPDONE_INT_EN REG_BIT(8)
2723
2724#define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
2725#define DPINVGTT_EN_MASK_CHV REG_GENMASK(27, 16)
2726#define DPINVGTT_EN_MASK_VLV REG_GENMASK(23, 16)
2727#define SPRITEF_INVALID_GTT_INT_EN REG_BIT(27)
2728#define SPRITEE_INVALID_GTT_INT_EN REG_BIT(26)
2729#define PLANEC_INVALID_GTT_INT_EN REG_BIT(25)
2730#define CURSORC_INVALID_GTT_INT_EN REG_BIT(24)
2731#define CURSORB_INVALID_GTT_INT_EN REG_BIT(23)
2732#define CURSORA_INVALID_GTT_INT_EN REG_BIT(22)
2733#define SPRITED_INVALID_GTT_INT_EN REG_BIT(21)
2734#define SPRITEC_INVALID_GTT_INT_EN REG_BIT(20)
2735#define PLANEB_INVALID_GTT_INT_EN REG_BIT(19)
2736#define SPRITEB_INVALID_GTT_INT_EN REG_BIT(18)
2737#define SPRITEA_INVALID_GTT_INT_EN REG_BIT(17)
2738#define PLANEA_INVALID_GTT_INT_EN REG_BIT(16)
2739#define DPINVGTT_STATUS_MASK_CHV REG_GENMASK(11, 0)
2740#define DPINVGTT_STATUS_MASK_VLV REG_GENMASK(7, 0)
2741#define SPRITEF_INVALID_GTT_STATUS REG_BIT(11)
2742#define SPRITEE_INVALID_GTT_STATUS REG_BIT(10)
2743#define PLANEC_INVALID_GTT_STATUS REG_BIT(9)
2744#define CURSORC_INVALID_GTT_STATUS REG_BIT(8)
2745#define CURSORB_INVALID_GTT_STATUS REG_BIT(7)
2746#define CURSORA_INVALID_GTT_STATUS REG_BIT(6)
2747#define SPRITED_INVALID_GTT_STATUS REG_BIT(5)
2748#define SPRITEC_INVALID_GTT_STATUS REG_BIT(4)
2749#define PLANEB_INVALID_GTT_STATUS REG_BIT(3)
2750#define SPRITEB_INVALID_GTT_STATUS REG_BIT(2)
2751#define SPRITEA_INVALID_GTT_STATUS REG_BIT(1)
2752#define PLANEA_INVALID_GTT_STATUS REG_BIT(0)
2753
2754#define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
2755#define DSPARB_CSTART_MASK (0x7f << 7)
2756#define DSPARB_CSTART_SHIFT 7
2757#define DSPARB_BSTART_MASK (0x7f)
2758#define DSPARB_BSTART_SHIFT 0
2759#define DSPARB_BEND_SHIFT 9 /* on 855 */
2760#define DSPARB_AEND_SHIFT 0
2761#define DSPARB_SPRITEA_SHIFT_VLV 0
2762#define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
2763#define DSPARB_SPRITEB_SHIFT_VLV 8
2764#define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
2765#define DSPARB_SPRITEC_SHIFT_VLV 16
2766#define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
2767#define DSPARB_SPRITED_SHIFT_VLV 24
2768#define DSPARB_SPRITED_MASK_VLV (0xff << 24)
2769#define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
2770#define DSPARB_SPRITEA_HI_SHIFT_VLV 0
2771#define DSPARB_SPRITEA_HI_MASK_VLV (0x1 << 0)
2772#define DSPARB_SPRITEB_HI_SHIFT_VLV 4
2773#define DSPARB_SPRITEB_HI_MASK_VLV (0x1 << 4)
2774#define DSPARB_SPRITEC_HI_SHIFT_VLV 8
2775#define DSPARB_SPRITEC_HI_MASK_VLV (0x1 << 8)
2776#define DSPARB_SPRITED_HI_SHIFT_VLV 12
2777#define DSPARB_SPRITED_HI_MASK_VLV (0x1 << 12)
2778#define DSPARB_SPRITEE_HI_SHIFT_VLV 16
2779#define DSPARB_SPRITEE_HI_MASK_VLV (0x1 << 16)
2780#define DSPARB_SPRITEF_HI_SHIFT_VLV 20
2781#define DSPARB_SPRITEF_HI_MASK_VLV (0x1 << 20)
2782#define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
2783#define DSPARB_SPRITEE_SHIFT_VLV 0
2784#define DSPARB_SPRITEE_MASK_VLV (0xff << 0)
2785#define DSPARB_SPRITEF_SHIFT_VLV 8
2786#define DSPARB_SPRITEF_MASK_VLV (0xff << 8)
2787
2788/* pnv/gen4/g4x/vlv/chv */
2789#define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
2790#define DSPFW_SR_SHIFT 23
2791#define DSPFW_SR_MASK (0x1ff << 23)
2792#define DSPFW_CURSORB_SHIFT 16
2793#define DSPFW_CURSORB_MASK (0x3f << 16)
2794#define DSPFW_PLANEB_SHIFT 8
2795#define DSPFW_PLANEB_MASK (0x7f << 8)
2796#define DSPFW_PLANEB_MASK_VLV (0xff << 8) /* vlv/chv */
2797#define DSPFW_PLANEA_SHIFT 0
2798#define DSPFW_PLANEA_MASK (0x7f << 0)
2799#define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */
2800#define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
2801#define DSPFW_FBC_SR_EN (1 << 31) /* g4x */
2802#define DSPFW_FBC_SR_SHIFT 28
2803#define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */
2804#define DSPFW_FBC_HPLL_SR_SHIFT 24
2805#define DSPFW_FBC_HPLL_SR_MASK (0xf << 24) /* g4x */
2806#define DSPFW_SPRITEB_SHIFT (16)
2807#define DSPFW_SPRITEB_MASK (0x7f << 16) /* g4x */
2808#define DSPFW_SPRITEB_MASK_VLV (0xff << 16) /* vlv/chv */
2809#define DSPFW_CURSORA_SHIFT 8
2810#define DSPFW_CURSORA_MASK (0x3f << 8)
2811#define DSPFW_PLANEC_OLD_SHIFT 0
2812#define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
2813#define DSPFW_SPRITEA_SHIFT 0
2814#define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */
2815#define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */
2816#define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
2817#define DSPFW_HPLL_SR_EN (1 << 31)
2818#define PINEVIEW_SELF_REFRESH_EN (1 << 30)
2819#define DSPFW_CURSOR_SR_SHIFT 24
2820#define DSPFW_CURSOR_SR_MASK (0x3f << 24)
2821#define DSPFW_HPLL_CURSOR_SHIFT 16
2822#define DSPFW_HPLL_CURSOR_MASK (0x3f << 16)
2823#define DSPFW_HPLL_SR_SHIFT 0
2824#define DSPFW_HPLL_SR_MASK (0x1ff << 0)
2825
2826/* vlv/chv */
2827#define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
2828#define DSPFW_SPRITEB_WM1_SHIFT 16
2829#define DSPFW_SPRITEB_WM1_MASK (0xff << 16)
2830#define DSPFW_CURSORA_WM1_SHIFT 8
2831#define DSPFW_CURSORA_WM1_MASK (0x3f << 8)
2832#define DSPFW_SPRITEA_WM1_SHIFT 0
2833#define DSPFW_SPRITEA_WM1_MASK (0xff << 0)
2834#define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
2835#define DSPFW_PLANEB_WM1_SHIFT 24
2836#define DSPFW_PLANEB_WM1_MASK (0xff << 24)
2837#define DSPFW_PLANEA_WM1_SHIFT 16
2838#define DSPFW_PLANEA_WM1_MASK (0xff << 16)
2839#define DSPFW_CURSORB_WM1_SHIFT 8
2840#define DSPFW_CURSORB_WM1_MASK (0x3f << 8)
2841#define DSPFW_CURSOR_SR_WM1_SHIFT 0
2842#define DSPFW_CURSOR_SR_WM1_MASK (0x3f << 0)
2843#define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
2844#define DSPFW_SR_WM1_SHIFT 0
2845#define DSPFW_SR_WM1_MASK (0x1ff << 0)
2846#define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
2847#define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
2848#define DSPFW_SPRITED_WM1_SHIFT 24
2849#define DSPFW_SPRITED_WM1_MASK (0xff << 24)
2850#define DSPFW_SPRITED_SHIFT 16
2851#define DSPFW_SPRITED_MASK_VLV (0xff << 16)
2852#define DSPFW_SPRITEC_WM1_SHIFT 8
2853#define DSPFW_SPRITEC_WM1_MASK (0xff << 8)
2854#define DSPFW_SPRITEC_SHIFT 0
2855#define DSPFW_SPRITEC_MASK_VLV (0xff << 0)
2856#define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
2857#define DSPFW_SPRITEF_WM1_SHIFT 24
2858#define DSPFW_SPRITEF_WM1_MASK (0xff << 24)
2859#define DSPFW_SPRITEF_SHIFT 16
2860#define DSPFW_SPRITEF_MASK_VLV (0xff << 16)
2861#define DSPFW_SPRITEE_WM1_SHIFT 8
2862#define DSPFW_SPRITEE_WM1_MASK (0xff << 8)
2863#define DSPFW_SPRITEE_SHIFT 0
2864#define DSPFW_SPRITEE_MASK_VLV (0xff << 0)
2865#define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
2866#define DSPFW_PLANEC_WM1_SHIFT 24
2867#define DSPFW_PLANEC_WM1_MASK (0xff << 24)
2868#define DSPFW_PLANEC_SHIFT 16
2869#define DSPFW_PLANEC_MASK_VLV (0xff << 16)
2870#define DSPFW_CURSORC_WM1_SHIFT 8
2871#define DSPFW_CURSORC_WM1_MASK (0x3f << 16)
2872#define DSPFW_CURSORC_SHIFT 0
2873#define DSPFW_CURSORC_MASK (0x3f << 0)
2874
2875/* vlv/chv high order bits */
2876#define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
2877#define DSPFW_SR_HI_SHIFT 24
2878#define DSPFW_SR_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
2879#define DSPFW_SPRITEF_HI_SHIFT 23
2880#define DSPFW_SPRITEF_HI_MASK (1 << 23)
2881#define DSPFW_SPRITEE_HI_SHIFT 22
2882#define DSPFW_SPRITEE_HI_MASK (1 << 22)
2883#define DSPFW_PLANEC_HI_SHIFT 21
2884#define DSPFW_PLANEC_HI_MASK (1 << 21)
2885#define DSPFW_SPRITED_HI_SHIFT 20
2886#define DSPFW_SPRITED_HI_MASK (1 << 20)
2887#define DSPFW_SPRITEC_HI_SHIFT 16
2888#define DSPFW_SPRITEC_HI_MASK (1 << 16)
2889#define DSPFW_PLANEB_HI_SHIFT 12
2890#define DSPFW_PLANEB_HI_MASK (1 << 12)
2891#define DSPFW_SPRITEB_HI_SHIFT 8
2892#define DSPFW_SPRITEB_HI_MASK (1 << 8)
2893#define DSPFW_SPRITEA_HI_SHIFT 4
2894#define DSPFW_SPRITEA_HI_MASK (1 << 4)
2895#define DSPFW_PLANEA_HI_SHIFT 0
2896#define DSPFW_PLANEA_HI_MASK (1 << 0)
2897#define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
2898#define DSPFW_SR_WM1_HI_SHIFT 24
2899#define DSPFW_SR_WM1_HI_MASK (3 << 24) /* 2 bits for chv, 1 for vlv */
2900#define DSPFW_SPRITEF_WM1_HI_SHIFT 23
2901#define DSPFW_SPRITEF_WM1_HI_MASK (1 << 23)
2902#define DSPFW_SPRITEE_WM1_HI_SHIFT 22
2903#define DSPFW_SPRITEE_WM1_HI_MASK (1 << 22)
2904#define DSPFW_PLANEC_WM1_HI_SHIFT 21
2905#define DSPFW_PLANEC_WM1_HI_MASK (1 << 21)
2906#define DSPFW_SPRITED_WM1_HI_SHIFT 20
2907#define DSPFW_SPRITED_WM1_HI_MASK (1 << 20)
2908#define DSPFW_SPRITEC_WM1_HI_SHIFT 16
2909#define DSPFW_SPRITEC_WM1_HI_MASK (1 << 16)
2910#define DSPFW_PLANEB_WM1_HI_SHIFT 12
2911#define DSPFW_PLANEB_WM1_HI_MASK (1 << 12)
2912#define DSPFW_SPRITEB_WM1_HI_SHIFT 8
2913#define DSPFW_SPRITEB_WM1_HI_MASK (1 << 8)
2914#define DSPFW_SPRITEA_WM1_HI_SHIFT 4
2915#define DSPFW_SPRITEA_WM1_HI_MASK (1 << 4)
2916#define DSPFW_PLANEA_WM1_HI_SHIFT 0
2917#define DSPFW_PLANEA_WM1_HI_MASK (1 << 0)
2918
2919/* drain latency register values*/
2920#define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
2921#define DDL_CURSOR_SHIFT 24
2922#define DDL_SPRITE_SHIFT(sprite) (8 + 8 * (sprite))
2923#define DDL_PLANE_SHIFT 0
2924#define DDL_PRECISION_HIGH (1 << 7)
2925#define DDL_PRECISION_LOW (0 << 7)
2926#define DRAIN_LATENCY_MASK 0x7f
2927
2928#define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
2929#define CBR_PND_DEADLINE_DISABLE (1 << 31)
2930#define CBR_PWM_CLOCK_MUX_SELECT (1 << 30)
2931
2932#define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
2933#define CBR_DPLLBMD_PIPE(pipe) (1 << (7 + (pipe) * 11)) /* pipes B and C */
2934
2935/* FIFO watermark sizes etc */
2936#define G4X_FIFO_LINE_SIZE 64
2937#define I915_FIFO_LINE_SIZE 64
2938#define I830_FIFO_LINE_SIZE 32
2939
2940#define VALLEYVIEW_FIFO_SIZE 255
2941#define G4X_FIFO_SIZE 127
2942#define I965_FIFO_SIZE 512
2943#define I945_FIFO_SIZE 127
2944#define I915_FIFO_SIZE 95
2945#define I855GM_FIFO_SIZE 127 /* In cachelines */
2946#define I830_FIFO_SIZE 95
2947
2948#define VALLEYVIEW_MAX_WM 0xff
2949#define G4X_MAX_WM 0x3f
2950#define I915_MAX_WM 0x3f
2951
2952#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
2953#define PINEVIEW_FIFO_LINE_SIZE 64
2954#define PINEVIEW_MAX_WM 0x1ff
2955#define PINEVIEW_DFT_WM 0x3f
2956#define PINEVIEW_DFT_HPLLOFF_WM 0
2957#define PINEVIEW_GUARD_WM 10
2958#define PINEVIEW_CURSOR_FIFO 64
2959#define PINEVIEW_CURSOR_MAX_WM 0x3f
2960#define PINEVIEW_CURSOR_DFT_WM 0
2961#define PINEVIEW_CURSOR_GUARD_WM 5
2962
2963#define VALLEYVIEW_CURSOR_MAX_WM 64
2964#define I965_CURSOR_FIFO 64
2965#define I965_CURSOR_MAX_WM 32
2966#define I965_CURSOR_DFT_WM 8
2967
2968/* define the Watermark register on Ironlake */
2969#define _WM0_PIPEA_ILK 0x45100
2970#define _WM0_PIPEB_ILK 0x45104
2971#define _WM0_PIPEC_IVB 0x45200
2972#define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \
2973 _WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
2974#define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16)
2975#define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8)
2976#define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0)
2977#define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x))
2978#define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x))
2979#define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x))
2980#define WM1_LP_ILK _MMIO(0x45108)
2981#define WM2_LP_ILK _MMIO(0x4510c)
2982#define WM3_LP_ILK _MMIO(0x45110)
2983#define WM_LP_ENABLE REG_BIT(31)
2984#define WM_LP_LATENCY_MASK REG_GENMASK(30, 24)
2985#define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19)
2986#define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20)
2987#define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8)
2988#define WM_LP_CURSOR_MASK REG_GENMASK(7, 0)
2989#define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x))
2990#define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x))
2991#define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x))
2992#define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x))
2993#define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x))
2994#define WM1S_LP_ILK _MMIO(0x45120)
2995#define WM2S_LP_IVB _MMIO(0x45124)
2996#define WM3S_LP_IVB _MMIO(0x45128)
2997#define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */
2998#define WM_LP_SPRITE_MASK REG_GENMASK(10, 0)
2999#define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x))
3000
3001/*
3002 * The two pipe frame counter registers are not synchronized, so
3003 * reading a stable value is somewhat tricky. The following code
3004 * should work:
3005 *
3006 * do {
3007 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3008 * PIPE_FRAME_HIGH_SHIFT;
3009 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
3010 * PIPE_FRAME_LOW_SHIFT);
3011 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3012 * PIPE_FRAME_HIGH_SHIFT);
3013 * } while (high1 != high2);
3014 * frame = (high1 << 8) | low1;
3015 */
3016#define _PIPEAFRAMEHIGH 0x70040
3017#define PIPE_FRAME_HIGH_MASK 0x0000ffff
3018#define PIPE_FRAME_HIGH_SHIFT 0
3019#define _PIPEAFRAMEPIXEL 0x70044
3020#define PIPE_FRAME_LOW_MASK 0xff000000
3021#define PIPE_FRAME_LOW_SHIFT 24
3022#define PIPE_PIXEL_MASK 0x00ffffff
3023#define PIPE_PIXEL_SHIFT 0
3024/* GM45+ just has to be different */
3025#define _PIPEA_FRMCOUNT_G4X 0x70040
3026#define _PIPEA_FLIPCOUNT_G4X 0x70044
3027#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X)
3028#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X)
3029
3030/* Cursor A & B regs */
3031#define _CURACNTR 0x70080
3032/* Old style CUR*CNTR flags (desktop 8xx) */
3033#define CURSOR_ENABLE REG_BIT(31)
3034#define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
3035#define CURSOR_STRIDE_MASK REG_GENMASK(29, 28)
3036#define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */
3037#define CURSOR_FORMAT_MASK REG_GENMASK(26, 24)
3038#define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)
3039#define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1)
3040#define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2)
3041#define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4)
3042#define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5)
3043/* New style CUR*CNTR flags */
3044#define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
3045#define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */
3046#define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28)
3047#define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe))
3048#define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26)
3049#define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
3050#define MCURSOR_ROTATE_180 REG_BIT(15)
3051#define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
3052#define MCURSOR_MODE_MASK 0x27
3053#define MCURSOR_MODE_DISABLE 0x00
3054#define MCURSOR_MODE_128_32B_AX 0x02
3055#define MCURSOR_MODE_256_32B_AX 0x03
3056#define MCURSOR_MODE_64_32B_AX 0x07
3057#define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX)
3058#define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX)
3059#define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX)
3060#define _CURABASE 0x70084
3061#define _CURAPOS 0x70088
3062#define _CURAPOS_ERLY_TPT 0x7008c
3063#define CURSOR_POS_Y_SIGN REG_BIT(31)
3064#define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
3065#define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
3066#define CURSOR_POS_X_SIGN REG_BIT(15)
3067#define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
3068#define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
3069#define _CURASIZE 0x700a0 /* 845/865 */
3070#define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
3071#define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
3072#define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
3073#define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
3074#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
3075#define CUR_FBC_EN REG_BIT(31)
3076#define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
3077#define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
3078#define _CUR_CHICKEN_A 0x700a4 /* mtl+ */
3079#define _CURASURFLIVE 0x700ac /* g4x+ */
3080#define _CURBCNTR 0x700c0
3081#define _CURBBASE 0x700c4
3082#define _CURBPOS 0x700c8
3083
3084#define _CURBCNTR_IVB 0x71080
3085#define _CURBBASE_IVB 0x71084
3086#define _CURBPOS_IVB 0x71088
3087
3088#define CURCNTR(pipe) _MMIO_CURSOR2(pipe, _CURACNTR)
3089#define CURBASE(pipe) _MMIO_CURSOR2(pipe, _CURABASE)
3090#define CURPOS(pipe) _MMIO_CURSOR2(pipe, _CURAPOS)
3091#define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(pipe, _CURAPOS_ERLY_TPT)
3092#define CURSIZE(pipe) _MMIO_CURSOR2(pipe, _CURASIZE)
3093#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(pipe, _CUR_FBC_CTL_A)
3094#define CUR_CHICKEN(pipe) _MMIO_CURSOR2(pipe, _CUR_CHICKEN_A)
3095#define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE)
3096
3097/* Display A control */
3098#define _DSPAADDR_VLV 0x7017C /* vlv/chv */
3099#define _DSPACNTR 0x70180
3100#define DISP_ENABLE REG_BIT(31)
3101#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
3102#define DISP_FORMAT_MASK REG_GENMASK(29, 26)
3103#define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2)
3104#define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3)
3105#define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4)
3106#define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5)
3107#define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6)
3108#define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7)
3109#define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8)
3110#define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9)
3111#define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10)
3112#define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11)
3113#define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12)
3114#define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14)
3115#define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15)
3116#define DISP_STEREO_ENABLE REG_BIT(25)
3117#define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
3118#define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24)
3119#define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe))
3120#define DISP_SRC_KEY_ENABLE REG_BIT(22)
3121#define DISP_LINE_DOUBLE REG_BIT(20)
3122#define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
3123#define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
3124#define DISP_ROTATE_180 REG_BIT(15)
3125#define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
3126#define DISP_TILED REG_BIT(10)
3127#define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
3128#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
3129#define _DSPAADDR 0x70184
3130#define _DSPASTRIDE 0x70188
3131#define _DSPAPOS 0x7018C /* reserved */
3132#define DISP_POS_Y_MASK REG_GENMASK(31, 16)
3133#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
3134#define DISP_POS_X_MASK REG_GENMASK(15, 0)
3135#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
3136#define _DSPASIZE 0x70190
3137#define DISP_HEIGHT_MASK REG_GENMASK(31, 16)
3138#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
3139#define DISP_WIDTH_MASK REG_GENMASK(15, 0)
3140#define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
3141#define _DSPASURF 0x7019C /* 965+ only */
3142#define DISP_ADDR_MASK REG_GENMASK(31, 12)
3143#define _DSPATILEOFF 0x701A4 /* 965+ only */
3144#define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
3145#define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
3146#define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
3147#define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
3148#define _DSPAOFFSET 0x701A4 /* HSW */
3149#define _DSPASURFLIVE 0x701AC
3150#define _DSPAGAMC 0x701E0
3151
3152#define DSPADDR_VLV(plane) _MMIO_PIPE2(plane, _DSPAADDR_VLV)
3153#define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)
3154#define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR)
3155#define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE)
3156#define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS)
3157#define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE)
3158#define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF)
3159#define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF)
3160#define DSPLINOFF(plane) DSPADDR(plane)
3161#define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
3162#define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
3163#define DSPGAMC(plane, i) _MMIO_PIPE2(plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
3164
3165/* CHV pipe B blender and primary plane */
3166#define _CHV_BLEND_A 0x60a00
3167#define CHV_BLEND_MASK REG_GENMASK(31, 30)
3168#define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
3169#define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1)
3170#define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2)
3171#define _CHV_CANVAS_A 0x60a04
3172#define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
3173#define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
3174#define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
3175#define _PRIMPOS_A 0x60a08
3176#define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
3177#define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
3178#define PRIM_POS_X_MASK REG_GENMASK(15, 0)
3179#define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
3180#define _PRIMSIZE_A 0x60a0c
3181#define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
3182#define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
3183#define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
3184#define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
3185#define _PRIMCNSTALPHA_A 0x60a10
3186#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
3187#define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
3188#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
3189
3190#define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
3191#define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
3192#define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A)
3193#define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A)
3194#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A)
3195
3196/* Display/Sprite base address macros */
3197#define DISP_BASEADDR_MASK (0xfffff000)
3198#define I915_LO_DISPBASE(val) ((val) & ~DISP_BASEADDR_MASK)
3199#define I915_HI_DISPBASE(val) ((val) & DISP_BASEADDR_MASK)
3200
3201/*
3202 * VBIOS flags
3203 * gen2:
3204 * [00:06] alm,mgm
3205 * [10:16] all
3206 * [30:32] alm,mgm
3207 * gen3+:
3208 * [00:0f] all
3209 * [10:1f] all
3210 * [30:32] all
3211 */
3212#define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
3213#define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
3214#define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
3215#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
3216
3217/* Pipe B */
3218#define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
3219#define _TRANSBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
3220#define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
3221#define _PIPEBFRAMEHIGH 0x71040
3222#define _PIPEBFRAMEPIXEL 0x71044
3223#define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
3224#define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
3225
3226
3227/* Display B control */
3228#define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
3229#define DISP_ALPHA_TRANS_ENABLE REG_BIT(15)
3230#define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0)
3231#define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
3232#define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
3233#define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
3234#define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
3235#define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
3236#define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
3237#define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
3238#define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
3239
3240/* ICL DSI 0 and 1 */
3241#define _PIPEDSI0CONF 0x7b008
3242#define _PIPEDSI1CONF 0x7b808
3243
3244/* Sprite A control */
3245#define _DVSACNTR 0x72180
3246#define DVS_ENABLE REG_BIT(31)
3247#define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
3248#define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
3249#define DVS_FORMAT_MASK REG_GENMASK(26, 25)
3250#define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
3251#define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1)
3252#define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2)
3253#define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3)
3254#define DVS_PIPE_CSC_ENABLE REG_BIT(24)
3255#define DVS_SOURCE_KEY REG_BIT(22)
3256#define DVS_RGB_ORDER_XBGR REG_BIT(20)
3257#define DVS_YUV_FORMAT_BT709 REG_BIT(18)
3258#define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16)
3259#define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
3260#define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1)
3261#define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2)
3262#define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3)
3263#define DVS_ROTATE_180 REG_BIT(15)
3264#define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
3265#define DVS_TILED REG_BIT(10)
3266#define DVS_DEST_KEY REG_BIT(2)
3267#define _DVSALINOFF 0x72184
3268#define _DVSASTRIDE 0x72188
3269#define _DVSAPOS 0x7218c
3270#define DVS_POS_Y_MASK REG_GENMASK(31, 16)
3271#define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
3272#define DVS_POS_X_MASK REG_GENMASK(15, 0)
3273#define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
3274#define _DVSASIZE 0x72190
3275#define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
3276#define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
3277#define DVS_WIDTH_MASK REG_GENMASK(15, 0)
3278#define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
3279#define _DVSAKEYVAL 0x72194
3280#define _DVSAKEYMSK 0x72198
3281#define _DVSASURF 0x7219c
3282#define DVS_ADDR_MASK REG_GENMASK(31, 12)
3283#define _DVSAKEYMAXVAL 0x721a0
3284#define _DVSATILEOFF 0x721a4
3285#define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
3286#define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
3287#define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
3288#define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
3289#define _DVSASURFLIVE 0x721ac
3290#define _DVSAGAMC_G4X 0x721e0 /* g4x */
3291#define _DVSASCALE 0x72204
3292#define DVS_SCALE_ENABLE REG_BIT(31)
3293#define DVS_FILTER_MASK REG_GENMASK(30, 29)
3294#define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0)
3295#define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1)
3296#define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2)
3297#define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
3298#define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27)
3299#define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16)
3300#define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
3301#define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
3302#define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
3303#define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
3304#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
3305
3306#define _DVSBCNTR 0x73180
3307#define _DVSBLINOFF 0x73184
3308#define _DVSBSTRIDE 0x73188
3309#define _DVSBPOS 0x7318c
3310#define _DVSBSIZE 0x73190
3311#define _DVSBKEYVAL 0x73194
3312#define _DVSBKEYMSK 0x73198
3313#define _DVSBSURF 0x7319c
3314#define _DVSBKEYMAXVAL 0x731a0
3315#define _DVSBTILEOFF 0x731a4
3316#define _DVSBSURFLIVE 0x731ac
3317#define _DVSBGAMC_G4X 0x731e0 /* g4x */
3318#define _DVSBSCALE 0x73204
3319#define _DVSBGAMC_ILK 0x73300 /* ilk/snb */
3320#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
3321
3322#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
3323#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
3324#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
3325#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
3326#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
3327#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
3328#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
3329#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
3330#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
3331#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
3332#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
3333#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
3334#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
3335#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
3336#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
3337
3338#define _SPRA_CTL 0x70280
3339#define SPRITE_ENABLE REG_BIT(31)
3340#define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
3341#define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
3342#define SPRITE_FORMAT_MASK REG_GENMASK(27, 25)
3343#define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
3344#define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1)
3345#define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2)
3346#define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3)
3347#define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4)
3348#define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */
3349#define SPRITE_PIPE_CSC_ENABLE REG_BIT(24)
3350#define SPRITE_SOURCE_KEY REG_BIT(22)
3351#define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */
3352#define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19)
3353#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */
3354#define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16)
3355#define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
3356#define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1)
3357#define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2)
3358#define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3)
3359#define SPRITE_ROTATE_180 REG_BIT(15)
3360#define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14)
3361#define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
3362#define SPRITE_TILED REG_BIT(10)
3363#define SPRITE_DEST_KEY REG_BIT(2)
3364#define _SPRA_LINOFF 0x70284
3365#define _SPRA_STRIDE 0x70288
3366#define _SPRA_POS 0x7028c
3367#define SPRITE_POS_Y_MASK REG_GENMASK(31, 16)
3368#define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
3369#define SPRITE_POS_X_MASK REG_GENMASK(15, 0)
3370#define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
3371#define _SPRA_SIZE 0x70290
3372#define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16)
3373#define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
3374#define SPRITE_WIDTH_MASK REG_GENMASK(15, 0)
3375#define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
3376#define _SPRA_KEYVAL 0x70294
3377#define _SPRA_KEYMSK 0x70298
3378#define _SPRA_SURF 0x7029c
3379#define SPRITE_ADDR_MASK REG_GENMASK(31, 12)
3380#define _SPRA_KEYMAX 0x702a0
3381#define _SPRA_TILEOFF 0x702a4
3382#define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
3383#define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
3384#define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
3385#define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
3386#define _SPRA_OFFSET 0x702a4
3387#define _SPRA_SURFLIVE 0x702ac
3388#define _SPRA_SCALE 0x70304
3389#define SPRITE_SCALE_ENABLE REG_BIT(31)
3390#define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
3391#define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
3392#define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1)
3393#define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2)
3394#define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */
3395#define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27)
3396#define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16)
3397#define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
3398#define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
3399#define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
3400#define _SPRA_GAMC 0x70400
3401#define _SPRA_GAMC16 0x70440
3402#define _SPRA_GAMC17 0x7044c
3403
3404#define _SPRB_CTL 0x71280
3405#define _SPRB_LINOFF 0x71284
3406#define _SPRB_STRIDE 0x71288
3407#define _SPRB_POS 0x7128c
3408#define _SPRB_SIZE 0x71290
3409#define _SPRB_KEYVAL 0x71294
3410#define _SPRB_KEYMSK 0x71298
3411#define _SPRB_SURF 0x7129c
3412#define _SPRB_KEYMAX 0x712a0
3413#define _SPRB_TILEOFF 0x712a4
3414#define _SPRB_OFFSET 0x712a4
3415#define _SPRB_SURFLIVE 0x712ac
3416#define _SPRB_SCALE 0x71304
3417#define _SPRB_GAMC 0x71400
3418#define _SPRB_GAMC16 0x71440
3419#define _SPRB_GAMC17 0x7144c
3420
3421#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
3422#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
3423#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
3424#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
3425#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
3426#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
3427#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
3428#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
3429#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
3430#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
3431#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
3432#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
3433#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
3434#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
3435#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
3436#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
3437
3438#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
3439#define SP_ENABLE REG_BIT(31)
3440#define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
3441#define SP_FORMAT_MASK REG_GENMASK(29, 26)
3442#define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0)
3443#define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)
3444#define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5)
3445#define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6)
3446#define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7)
3447#define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8)
3448#define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9)
3449#define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */
3450#define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */
3451#define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14)
3452#define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15)
3453#define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */
3454#define SP_SOURCE_KEY REG_BIT(22)
3455#define SP_YUV_FORMAT_BT709 REG_BIT(18)
3456#define SP_YUV_ORDER_MASK REG_GENMASK(17, 16)
3457#define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
3458#define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1)
3459#define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2)
3460#define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3)
3461#define SP_ROTATE_180 REG_BIT(15)
3462#define SP_TILED REG_BIT(10)
3463#define SP_MIRROR REG_BIT(8) /* CHV pipe B */
3464#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
3465#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
3466#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
3467#define SP_POS_Y_MASK REG_GENMASK(31, 16)
3468#define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))
3469#define SP_POS_X_MASK REG_GENMASK(15, 0)
3470#define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))
3471#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
3472#define SP_HEIGHT_MASK REG_GENMASK(31, 16)
3473#define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
3474#define SP_WIDTH_MASK REG_GENMASK(15, 0)
3475#define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))
3476#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
3477#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
3478#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
3479#define SP_ADDR_MASK REG_GENMASK(31, 12)
3480#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
3481#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
3482#define SP_OFFSET_Y_MASK REG_GENMASK(31, 16)
3483#define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
3484#define SP_OFFSET_X_MASK REG_GENMASK(15, 0)
3485#define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
3486#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
3487#define SP_CONST_ALPHA_ENABLE REG_BIT(31)
3488#define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
3489#define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
3490#define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac)
3491#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
3492#define SP_CONTRAST_MASK REG_GENMASK(26, 18)
3493#define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
3494#define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0)
3495#define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
3496#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
3497#define SP_SH_SIN_MASK REG_GENMASK(26, 16)
3498#define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
3499#define SP_SH_COS_MASK REG_GENMASK(9, 0)
3500#define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
3501#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
3502
3503#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
3504#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
3505#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
3506#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
3507#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
3508#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
3509#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
3510#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
3511#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
3512#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
3513#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
3514#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)
3515#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
3516#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
3517#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
3518
3519#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
3520 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
3521#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
3522 _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
3523
3524#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
3525#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
3526#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
3527#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
3528#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
3529#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
3530#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
3531#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
3532#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
3533#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
3534#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
3535#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
3536#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
3537#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
3538#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
3539
3540/*
3541 * CHV pipe B sprite CSC
3542 *
3543 * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff|
3544 * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff|
3545 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|
3546 */
3547#define _MMIO_CHV_SPCSC(plane_id, reg) \
3548 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
3549
3550#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900)
3551#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904)
3552#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908)
3553#define SPCSC_OOFF_MASK REG_GENMASK(26, 16)
3554#define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
3555#define SPCSC_IOFF_MASK REG_GENMASK(10, 0)
3556#define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
3557
3558#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c)
3559#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910)
3560#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914)
3561#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918)
3562#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c)
3563#define SPCSC_C1_MASK REG_GENMASK(30, 16)
3564#define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
3565#define SPCSC_C0_MASK REG_GENMASK(14, 0)
3566#define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
3567
3568#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920)
3569#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924)
3570#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928)
3571#define SPCSC_IMAX_MASK REG_GENMASK(26, 16)
3572#define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
3573#define SPCSC_IMIN_MASK REG_GENMASK(10, 0)
3574#define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
3575
3576#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c)
3577#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930)
3578#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934)
3579#define SPCSC_OMAX_MASK REG_GENMASK(25, 16)
3580#define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */
3581#define SPCSC_OMIN_MASK REG_GENMASK(9, 0)
3582#define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */
3583
3584/* Skylake plane registers */
3585
3586#define _PLANE_CTL_1_A 0x70180
3587#define _PLANE_CTL_2_A 0x70280
3588#define _PLANE_CTL_3_A 0x70380
3589#define PLANE_CTL_ENABLE REG_BIT(31)
3590#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */
3591#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */
3592#define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
3593#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
3594/*
3595 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
3596 * expanded to include bit 23 as well. However, the shift-24 based values
3597 * correctly map to the same formats in ICL, as long as bit 23 is set to 0
3598 */
3599#define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
3600#define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */
3601#define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
3602#define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1)
3603#define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2)
3604#define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3)
3605#define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4)
3606#define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5)
3607#define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6)
3608#define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7)
3609#define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8)
3610#define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12)
3611#define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14)
3612#define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1)
3613#define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3)
3614#define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5)
3615#define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
3616#define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
3617#define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
3618#define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
3619#define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21)
3620#define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)
3621#define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2)
3622#define PLANE_CTL_ORDER_RGBX REG_BIT(20)
3623#define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
3624#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
3625#define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16)
3626#define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)
3627#define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1)
3628#define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2)
3629#define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3)
3630#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
3631#define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
3632#define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
3633#define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
3634#define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10)
3635#define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)
3636#define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)
3637#define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)
3638#define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
3639#define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
3640#define PLANE_CTL_ASYNC_FLIP REG_BIT(9)
3641#define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8)
3642#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */
3643#define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
3644#define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)
3645#define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2)
3646#define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3)
3647#define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0)
3648#define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)
3649#define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1)
3650#define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2)
3651#define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3)
3652#define _PLANE_STRIDE_1_A 0x70188
3653#define _PLANE_STRIDE_2_A 0x70288
3654#define _PLANE_STRIDE_3_A 0x70388
3655#define PLANE_STRIDE__MASK REG_GENMASK(11, 0)
3656#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride))
3657#define _PLANE_POS_1_A 0x7018c
3658#define _PLANE_POS_2_A 0x7028c
3659#define _PLANE_POS_3_A 0x7038c
3660#define PLANE_POS_Y_MASK REG_GENMASK(31, 16)
3661#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y))
3662#define PLANE_POS_X_MASK REG_GENMASK(15, 0)
3663#define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x))
3664#define _PLANE_SIZE_1_A 0x70190
3665#define _PLANE_SIZE_2_A 0x70290
3666#define _PLANE_SIZE_3_A 0x70390
3667#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16)
3668#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h))
3669#define PLANE_WIDTH_MASK REG_GENMASK(15, 0)
3670#define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w))
3671#define _PLANE_SURF_1_A 0x7019c
3672#define _PLANE_SURF_2_A 0x7029c
3673#define _PLANE_SURF_3_A 0x7039c
3674#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12)
3675#define PLANE_SURF_DECRYPT REG_BIT(2)
3676#define _PLANE_OFFSET_1_A 0x701a4
3677#define _PLANE_OFFSET_2_A 0x702a4
3678#define _PLANE_OFFSET_3_A 0x703a4
3679#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16)
3680#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y))
3681#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0)
3682#define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x))
3683#define _PLANE_KEYVAL_1_A 0x70194
3684#define _PLANE_KEYVAL_2_A 0x70294
3685#define _PLANE_KEYMSK_1_A 0x70198
3686#define _PLANE_KEYMSK_2_A 0x70298
3687#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31)
3688#define _PLANE_KEYMAX_1_A 0x701a0
3689#define _PLANE_KEYMAX_2_A 0x702a0
3690#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24)
3691#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a))
3692#define _PLANE_SURFLIVE_1_A 0x701ac
3693#define _PLANE_SURFLIVE_2_A 0x702ac
3694#define _PLANE_CC_VAL_1_A 0x701b4
3695#define _PLANE_CC_VAL_2_A 0x702b4
3696#define _PLANE_AUX_DIST_1_A 0x701c0
3697#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12)
3698#define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0)
3699#define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride))
3700#define _PLANE_AUX_DIST_2_A 0x702c0
3701#define _PLANE_AUX_OFFSET_1_A 0x701c4
3702#define _PLANE_AUX_OFFSET_2_A 0x702c4
3703#define _PLANE_CUS_CTL_1_A 0x701c8
3704#define _PLANE_CUS_CTL_2_A 0x702c8
3705#define PLANE_CUS_ENABLE REG_BIT(31)
3706#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30)
3707#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
3708#define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
3709#define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
3710#define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1)
3711#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19)
3712#define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16)
3713#define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
3714#define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1)
3715#define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2)
3716#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15)
3717#define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12)
3718#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
3719#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1)
3720#define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2)
3721#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */
3722#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */
3723#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */
3724#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
3725#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
3726#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
3727#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */
3728#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */
3729#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17)
3730#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
3731#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1)
3732#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2)
3733#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3)
3734#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4)
3735#define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13)
3736#define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4)
3737#define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
3738#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2)
3739#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3)
3740#define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */
3741#define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */
3742#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */
3743#define _PLANE_BUF_CFG_1_A 0x7027c
3744#define _PLANE_BUF_CFG_2_A 0x7037c
3745/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
3746#define PLANE_BUF_END_MASK REG_GENMASK(27, 16)
3747#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
3748#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
3749#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
3750#define _PLANE_NV12_BUF_CFG_1_A 0x70278
3751#define _PLANE_NV12_BUF_CFG_2_A 0x70378
3752
3753#define _PLANE_CC_VAL_1_B 0x711b4
3754#define _PLANE_CC_VAL_2_B 0x712b4
3755#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4)
3756#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4)
3757#define PLANE_CC_VAL(pipe, plane, dw) \
3758 _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw)))
3759
3760/* Input CSC Register Definitions */
3761#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0
3762#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0
3763
3764#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0
3765#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0
3766
3767#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
3768 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
3769 _PLANE_INPUT_CSC_RY_GY_1_B)
3770#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
3771 _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
3772 _PLANE_INPUT_CSC_RY_GY_2_B)
3773
3774#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \
3775 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \
3776 _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
3777
3778#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8
3779#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8
3780
3781#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8
3782#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8
3783
3784#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \
3785 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
3786 _PLANE_INPUT_CSC_PREOFF_HI_1_B)
3787#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \
3788 _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
3789 _PLANE_INPUT_CSC_PREOFF_HI_2_B)
3790#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \
3791 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
3792 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
3793
3794#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204
3795#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304
3796
3797#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204
3798#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304
3799
3800#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \
3801 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
3802 _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
3803#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \
3804 _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
3805 _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
3806#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \
3807 _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
3808 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
3809
3810#define _PLANE_CTL_1_B 0x71180
3811#define _PLANE_CTL_2_B 0x71280
3812#define _PLANE_CTL_3_B 0x71380
3813#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B)
3814#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B)
3815#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B)
3816#define PLANE_CTL(pipe, plane) \
3817 _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe))
3818
3819#define _PLANE_STRIDE_1_B 0x71188
3820#define _PLANE_STRIDE_2_B 0x71288
3821#define _PLANE_STRIDE_3_B 0x71388
3822#define _PLANE_STRIDE_1(pipe) \
3823 _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B)
3824#define _PLANE_STRIDE_2(pipe) \
3825 _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B)
3826#define _PLANE_STRIDE_3(pipe) \
3827 _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
3828#define PLANE_STRIDE(pipe, plane) \
3829 _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
3830
3831#define _PLANE_POS_1_B 0x7118c
3832#define _PLANE_POS_2_B 0x7128c
3833#define _PLANE_POS_3_B 0x7138c
3834#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B)
3835#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B)
3836#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B)
3837#define PLANE_POS(pipe, plane) \
3838 _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe))
3839
3840#define _PLANE_SIZE_1_B 0x71190
3841#define _PLANE_SIZE_2_B 0x71290
3842#define _PLANE_SIZE_3_B 0x71390
3843#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B)
3844#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B)
3845#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B)
3846#define PLANE_SIZE(pipe, plane) \
3847 _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe))
3848
3849#define _PLANE_SURF_1_B 0x7119c
3850#define _PLANE_SURF_2_B 0x7129c
3851#define _PLANE_SURF_3_B 0x7139c
3852#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B)
3853#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B)
3854#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B)
3855#define PLANE_SURF(pipe, plane) \
3856 _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe))
3857
3858#define _PLANE_OFFSET_1_B 0x711a4
3859#define _PLANE_OFFSET_2_B 0x712a4
3860#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B)
3861#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B)
3862#define PLANE_OFFSET(pipe, plane) \
3863 _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe))
3864
3865#define _PLANE_KEYVAL_1_B 0x71194
3866#define _PLANE_KEYVAL_2_B 0x71294
3867#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B)
3868#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B)
3869#define PLANE_KEYVAL(pipe, plane) \
3870 _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe))
3871
3872#define _PLANE_KEYMSK_1_B 0x71198
3873#define _PLANE_KEYMSK_2_B 0x71298
3874#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B)
3875#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B)
3876#define PLANE_KEYMSK(pipe, plane) \
3877 _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe))
3878
3879#define _PLANE_KEYMAX_1_B 0x711a0
3880#define _PLANE_KEYMAX_2_B 0x712a0
3881#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B)
3882#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B)
3883#define PLANE_KEYMAX(pipe, plane) \
3884 _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe))
3885
3886#define _PLANE_SURFLIVE_1_B 0x711ac
3887#define _PLANE_SURFLIVE_2_B 0x712ac
3888#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B)
3889#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B)
3890#define PLANE_SURFLIVE(pipe, plane) \
3891 _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe))
3892
3893#define _PLANE_CHICKEN_1_B 0x7126c
3894#define _PLANE_CHICKEN_2_B 0x7136c
3895#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B)
3896#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B)
3897#define PLANE_CHICKEN(pipe, plane) \
3898 _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe))
3899
3900#define _PLANE_AUX_DIST_1_B 0x711c0
3901#define _PLANE_AUX_DIST_2_B 0x712c0
3902#define _PLANE_AUX_DIST_1(pipe) \
3903 _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B)
3904#define _PLANE_AUX_DIST_2(pipe) \
3905 _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B)
3906#define PLANE_AUX_DIST(pipe, plane) \
3907 _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe))
3908
3909#define _PLANE_AUX_OFFSET_1_B 0x711c4
3910#define _PLANE_AUX_OFFSET_2_B 0x712c4
3911#define _PLANE_AUX_OFFSET_1(pipe) \
3912 _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B)
3913#define _PLANE_AUX_OFFSET_2(pipe) \
3914 _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B)
3915#define PLANE_AUX_OFFSET(pipe, plane) \
3916 _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe))
3917
3918#define _PLANE_CUS_CTL_1_B 0x711c8
3919#define _PLANE_CUS_CTL_2_B 0x712c8
3920#define _PLANE_CUS_CTL_1(pipe) \
3921 _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B)
3922#define _PLANE_CUS_CTL_2(pipe) \
3923 _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B)
3924#define PLANE_CUS_CTL(pipe, plane) \
3925 _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe))
3926
3927#define _PLANE_COLOR_CTL_1_B 0x711CC
3928#define _PLANE_COLOR_CTL_2_B 0x712CC
3929#define _PLANE_COLOR_CTL_3_B 0x713CC
3930#define _PLANE_COLOR_CTL_1(pipe) \
3931 _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B)
3932#define _PLANE_COLOR_CTL_2(pipe) \
3933 _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B)
3934#define PLANE_COLOR_CTL(pipe, plane) \
3935 _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe))
3936
3937/* VBIOS regs */
3938#define VGACNTRL _MMIO(0x71400)
3939# define VGA_DISP_DISABLE (1 << 31)
3940# define VGA_2X_MODE (1 << 30)
3941# define VGA_PIPE_B_SELECT (1 << 29)
3942
3943#define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
3944
3945/* Ironlake */
3946
3947#define CPU_VGACNTRL _MMIO(0x41000)
3948
3949#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
3950#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
3951#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
3952#define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
3953#define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
3954#define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
3955#define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
3956#define DIGITAL_PORTA_HOTPLUG_STATUS_MASK (3 << 0)
3957#define DIGITAL_PORTA_HOTPLUG_NO_DETECT (0 << 0)
3958#define DIGITAL_PORTA_HOTPLUG_SHORT_DETECT (1 << 0)
3959#define DIGITAL_PORTA_HOTPLUG_LONG_DETECT (2 << 0)
3960
3961/* refresh rate hardware control */
3962#define RR_HW_CTL _MMIO(0x45300)
3963#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
3964#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
3965
3966#define PCH_3DCGDIS0 _MMIO(0x46020)
3967# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
3968# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
3969
3970#define PCH_3DCGDIS1 _MMIO(0x46024)
3971# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
3972
3973#define _PIPEA_DATA_M1 0x60030
3974#define _PIPEA_DATA_N1 0x60034
3975#define _PIPEA_DATA_M2 0x60038
3976#define _PIPEA_DATA_N2 0x6003c
3977#define _PIPEA_LINK_M1 0x60040
3978#define _PIPEA_LINK_N1 0x60044
3979#define _PIPEA_LINK_M2 0x60048
3980#define _PIPEA_LINK_N2 0x6004c
3981
3982/* PIPEB timing regs are same start from 0x61000 */
3983
3984#define _PIPEB_DATA_M1 0x61030
3985#define _PIPEB_DATA_N1 0x61034
3986#define _PIPEB_DATA_M2 0x61038
3987#define _PIPEB_DATA_N2 0x6103c
3988#define _PIPEB_LINK_M1 0x61040
3989#define _PIPEB_LINK_N1 0x61044
3990#define _PIPEB_LINK_M2 0x61048
3991#define _PIPEB_LINK_N2 0x6104c
3992
3993#define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1)
3994#define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1)
3995#define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2)
3996#define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2)
3997#define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1)
3998#define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1)
3999#define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2)
4000#define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2)
4001
4002/* CPU panel fitter */
4003/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
4004#define _PFA_CTL_1 0x68080
4005#define _PFB_CTL_1 0x68880
4006#define PF_ENABLE REG_BIT(31)
4007#define PF_PIPE_SEL_MASK_IVB REG_GENMASK(30, 29) /* ivb/hsw */
4008#define PF_PIPE_SEL_IVB(pipe) REG_FIELD_PREP(PF_PIPE_SEL_MASK_IVB, (pipe))
4009#define PF_FILTER_MASK REG_GENMASK(24, 23)
4010#define PF_FILTER_PROGRAMMED REG_FIELD_PREP(PF_FILTER_MASK, 0)
4011#define PF_FILTER_MED_3x3 REG_FIELD_PREP(PF_FILTER_MASK, 1)
4012#define PF_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 2)
4013#define PF_FILTER_EDGE_SOFTEN REG_FIELD_PREP(PF_FILTER_EDGE_MASK, 3)
4014#define _PFA_WIN_SZ 0x68074
4015#define _PFB_WIN_SZ 0x68874
4016#define PF_WIN_XSIZE_MASK REG_GENMASK(31, 16)
4017#define PF_WIN_XSIZE(w) REG_FIELD_PREP(PF_WIN_XSIZE_MASK, (w))
4018#define PF_WIN_YSIZE_MASK REG_GENMASK(15, 0)
4019#define PF_WIN_YSIZE(h) REG_FIELD_PREP(PF_WIN_YSIZE_MASK, (h))
4020#define _PFA_WIN_POS 0x68070
4021#define _PFB_WIN_POS 0x68870
4022#define PF_WIN_XPOS_MASK REG_GENMASK(31, 16)
4023#define PF_WIN_XPOS(x) REG_FIELD_PREP(PF_WIN_XPOS_MASK, (x))
4024#define PF_WIN_YPOS_MASK REG_GENMASK(15, 0)
4025#define PF_WIN_YPOS(y) REG_FIELD_PREP(PF_WIN_YPOS_MASK, (y))
4026#define _PFA_VSCALE 0x68084
4027#define _PFB_VSCALE 0x68884
4028#define _PFA_HSCALE 0x68090
4029#define _PFB_HSCALE 0x68890
4030
4031#define PF_CTL(pipe) _MMIO_PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
4032#define PF_WIN_SZ(pipe) _MMIO_PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
4033#define PF_WIN_POS(pipe) _MMIO_PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
4034#define PF_VSCALE(pipe) _MMIO_PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
4035#define PF_HSCALE(pipe) _MMIO_PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
4036
4037/*
4038 * Skylake scalers
4039 */
4040#define _PS_1A_CTRL 0x68180
4041#define _PS_2A_CTRL 0x68280
4042#define _PS_1B_CTRL 0x68980
4043#define _PS_2B_CTRL 0x68A80
4044#define _PS_1C_CTRL 0x69180
4045#define PS_SCALER_EN REG_BIT(31)
4046#define PS_SCALER_TYPE_MASK REG_BIT(30) /* icl+ */
4047#define PS_SCALER_TYPE_NON_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
4048#define PS_SCALER_TYPE_LINEAR REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 1)
4049#define SKL_PS_SCALER_MODE_MASK REG_GENMASK(29, 28) /* skl/bxt */
4050#define SKL_PS_SCALER_MODE_DYN REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
4051#define SKL_PS_SCALER_MODE_HQ REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 1)
4052#define SKL_PS_SCALER_MODE_NV12 REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 2)
4053#define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
4054#define PS_SCALER_MODE_NORMAL REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
4055#define PS_SCALER_MODE_PLANAR REG_FIELD_PREP(PS_SCALER_MODE_MASK, 1)
4056#define PS_ADAPTIVE_FILTERING_EN REG_BIT(28) /* icl+ */
4057#define PS_BINDING_MASK REG_GENMASK(27, 25)
4058#define PS_BINDING_PIPE REG_FIELD_PREP(PS_BINDING_MASK, 0)
4059#define PS_BINDING_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_MASK, (plane_id) + 1)
4060#define PS_FILTER_MASK REG_GENMASK(24, 23)
4061#define PS_FILTER_MEDIUM REG_FIELD_PREP(PS_FILTER_MASK, 0)
4062#define PS_FILTER_PROGRAMMED REG_FIELD_PREP(PS_FILTER_MASK, 1)
4063#define PS_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_FILTER_MASK, 2)
4064#define PS_FILTER_BILINEAR REG_FIELD_PREP(PS_FILTER_MASK, 3)
4065#define PS_ADAPTIVE_FILTER_MASK REG_BIT(22) /* icl+ */
4066#define PS_ADAPTIVE_FILTER_MEDIUM REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
4067#define PS_ADAPTIVE_FILTER_EDGE_ENHANCE REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 1)
4068#define PS_PIPE_SCALER_LOC_MASK REG_BIT(21) /* icl+ */
4069#define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-linear */
4070#define PS_PIPE_SCALER_LOC_AFTER_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 1) /* linear */
4071#define PS_VERT3TAP REG_BIT(21) /* skl/bxt */
4072#define PS_VERT_INT_INVERT_FIELD REG_BIT(20)
4073#define PS_PROG_SCALE_FACTOR REG_BIT(19) /* tgl+ */
4074#define PS_PWRUP_PROGRESS REG_BIT(17)
4075#define PS_V_FILTER_BYPASS REG_BIT(8)
4076#define PS_VADAPT_EN REG_BIT(7) /* skl/bxt */
4077#define PS_VADAPT_MODE_MASK REG_GENMASK(6, 5) /* skl/bxt */
4078#define PS_VADAPT_MODE_LEAST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0)
4079#define PS_VADAPT_MODE_MOD_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 1)
4080#define PS_VADAPT_MODE_MOST_ADAPT REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 3)
4081#define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */
4082#define PS_BINDING_Y_PLANE(plane_id) REG_FIELD_PREP(PS_BINDING_Y_MASK, (plane_id) + 1)
4083#define PS_Y_VERT_FILTER_SELECT_MASK REG_BIT(4) /* glk+ */
4084#define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set))
4085#define PS_Y_HORZ_FILTER_SELECT_MASK REG_BIT(3) /* glk+ */
4086#define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set))
4087#define PS_UV_VERT_FILTER_SELECT_MASK REG_BIT(2) /* glk+ */
4088#define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set))
4089#define PS_UV_HORZ_FILTER_SELECT_MASK REG_BIT(1) /* glk+ */
4090#define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set))
4091
4092#define _PS_PWR_GATE_1A 0x68160
4093#define _PS_PWR_GATE_2A 0x68260
4094#define _PS_PWR_GATE_1B 0x68960
4095#define _PS_PWR_GATE_2B 0x68A60
4096#define _PS_PWR_GATE_1C 0x69160
4097#define PS_PWR_GATE_DIS_OVERRIDE REG_BIT(31)
4098#define PS_PWR_GATE_SETTLING_TIME_MASK REG_GENMASK(4, 3)
4099#define PS_PWR_GATE_SETTLING_TIME_32 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0)
4100#define PS_PWR_GATE_SETTLING_TIME_64 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 1)
4101#define PS_PWR_GATE_SETTLING_TIME_96 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 2)
4102#define PS_PWR_GATE_SETTLING_TIME_128 REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 3)
4103#define PS_PWR_GATE_SLPEN_MASK REG_GENMASK(1, 0)
4104#define PS_PWR_GATE_SLPEN_8 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0)
4105#define PS_PWR_GATE_SLPEN_16 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 1)
4106#define PS_PWR_GATE_SLPEN_24 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 2)
4107#define PS_PWR_GATE_SLPEN_32 REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 3)
4108
4109#define _PS_WIN_POS_1A 0x68170
4110#define _PS_WIN_POS_2A 0x68270
4111#define _PS_WIN_POS_1B 0x68970
4112#define _PS_WIN_POS_2B 0x68A70
4113#define _PS_WIN_POS_1C 0x69170
4114#define PS_WIN_XPOS_MASK REG_GENMASK(31, 16)
4115#define PS_WIN_XPOS(x) REG_FIELD_PREP(PS_WIN_XPOS_MASK, (x))
4116#define PS_WIN_YPOS_MASK REG_GENMASK(15, 0)
4117#define PS_WIN_YPOS(y) REG_FIELD_PREP(PS_WIN_YPOS_MASK, (y))
4118
4119#define _PS_WIN_SZ_1A 0x68174
4120#define _PS_WIN_SZ_2A 0x68274
4121#define _PS_WIN_SZ_1B 0x68974
4122#define _PS_WIN_SZ_2B 0x68A74
4123#define _PS_WIN_SZ_1C 0x69174
4124#define PS_WIN_XSIZE_MASK REG_GENMASK(31, 16)
4125#define PS_WIN_XSIZE(w) REG_FIELD_PREP(PS_WIN_XSIZE_MASK, (w))
4126#define PS_WIN_YSIZE_MASK REG_GENMASK(15, 0)
4127#define PS_WIN_YSIZE(h) REG_FIELD_PREP(PS_WIN_YSIZE_MASK, (h))
4128
4129#define _PS_VSCALE_1A 0x68184
4130#define _PS_VSCALE_2A 0x68284
4131#define _PS_VSCALE_1B 0x68984
4132#define _PS_VSCALE_2B 0x68A84
4133#define _PS_VSCALE_1C 0x69184
4134
4135#define _PS_HSCALE_1A 0x68190
4136#define _PS_HSCALE_2A 0x68290
4137#define _PS_HSCALE_1B 0x68990
4138#define _PS_HSCALE_2B 0x68A90
4139#define _PS_HSCALE_1C 0x69190
4140
4141#define _PS_VPHASE_1A 0x68188
4142#define _PS_VPHASE_2A 0x68288
4143#define _PS_VPHASE_1B 0x68988
4144#define _PS_VPHASE_2B 0x68A88
4145#define _PS_VPHASE_1C 0x69188
4146#define PS_Y_PHASE_MASK REG_GENMASK(31, 16)
4147#define PS_Y_PHASE(x) REG_FIELD_PREP(PS_Y_PHASE_MASK, (x))
4148#define PS_UV_RGB_PHASE_MASK REG_GENMASK(15, 0)
4149#define PS_UV_RGB_PHASE(x) REG_FIELD_PREP(PS_UV_RGB_PHASE_MASK, (x))
4150#define PS_PHASE_MASK (0x7fff << 1) /* u2.13 */
4151#define PS_PHASE_TRIP (1 << 0)
4152
4153#define _PS_HPHASE_1A 0x68194
4154#define _PS_HPHASE_2A 0x68294
4155#define _PS_HPHASE_1B 0x68994
4156#define _PS_HPHASE_2B 0x68A94
4157#define _PS_HPHASE_1C 0x69194
4158
4159#define _PS_ECC_STAT_1A 0x681D0
4160#define _PS_ECC_STAT_2A 0x682D0
4161#define _PS_ECC_STAT_1B 0x689D0
4162#define _PS_ECC_STAT_2B 0x68AD0
4163#define _PS_ECC_STAT_1C 0x691D0
4164
4165#define _PS_COEF_SET0_INDEX_1A 0x68198
4166#define _PS_COEF_SET0_INDEX_2A 0x68298
4167#define _PS_COEF_SET0_INDEX_1B 0x68998
4168#define _PS_COEF_SET0_INDEX_2B 0x68A98
4169#define PS_COEF_INDEX_AUTO_INC REG_BIT(10)
4170
4171#define _PS_COEF_SET0_DATA_1A 0x6819C
4172#define _PS_COEF_SET0_DATA_2A 0x6829C
4173#define _PS_COEF_SET0_DATA_1B 0x6899C
4174#define _PS_COEF_SET0_DATA_2B 0x68A9C
4175
4176#define _ID(id, a, b) _PICK_EVEN(id, a, b)
4177#define SKL_PS_CTRL(pipe, id) _MMIO_PIPE(pipe, \
4178 _ID(id, _PS_1A_CTRL, _PS_2A_CTRL), \
4179 _ID(id, _PS_1B_CTRL, _PS_2B_CTRL))
4180#define SKL_PS_PWR_GATE(pipe, id) _MMIO_PIPE(pipe, \
4181 _ID(id, _PS_PWR_GATE_1A, _PS_PWR_GATE_2A), \
4182 _ID(id, _PS_PWR_GATE_1B, _PS_PWR_GATE_2B))
4183#define SKL_PS_WIN_POS(pipe, id) _MMIO_PIPE(pipe, \
4184 _ID(id, _PS_WIN_POS_1A, _PS_WIN_POS_2A), \
4185 _ID(id, _PS_WIN_POS_1B, _PS_WIN_POS_2B))
4186#define SKL_PS_WIN_SZ(pipe, id) _MMIO_PIPE(pipe, \
4187 _ID(id, _PS_WIN_SZ_1A, _PS_WIN_SZ_2A), \
4188 _ID(id, _PS_WIN_SZ_1B, _PS_WIN_SZ_2B))
4189#define SKL_PS_VSCALE(pipe, id) _MMIO_PIPE(pipe, \
4190 _ID(id, _PS_VSCALE_1A, _PS_VSCALE_2A), \
4191 _ID(id, _PS_VSCALE_1B, _PS_VSCALE_2B))
4192#define SKL_PS_HSCALE(pipe, id) _MMIO_PIPE(pipe, \
4193 _ID(id, _PS_HSCALE_1A, _PS_HSCALE_2A), \
4194 _ID(id, _PS_HSCALE_1B, _PS_HSCALE_2B))
4195#define SKL_PS_VPHASE(pipe, id) _MMIO_PIPE(pipe, \
4196 _ID(id, _PS_VPHASE_1A, _PS_VPHASE_2A), \
4197 _ID(id, _PS_VPHASE_1B, _PS_VPHASE_2B))
4198#define SKL_PS_HPHASE(pipe, id) _MMIO_PIPE(pipe, \
4199 _ID(id, _PS_HPHASE_1A, _PS_HPHASE_2A), \
4200 _ID(id, _PS_HPHASE_1B, _PS_HPHASE_2B))
4201#define SKL_PS_ECC_STAT(pipe, id) _MMIO_PIPE(pipe, \
4202 _ID(id, _PS_ECC_STAT_1A, _PS_ECC_STAT_2A), \
4203 _ID(id, _PS_ECC_STAT_1B, _PS_ECC_STAT_2B))
4204#define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
4205 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
4206 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
4207
4208#define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
4209 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
4210 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
4211
4212/* Display Internal Timeout Register */
4213#define RM_TIMEOUT _MMIO(0x42060)
4214#define MMIO_TIMEOUT_US(us) ((us) << 0)
4215
4216/* interrupts */
4217#define DE_MASTER_IRQ_CONTROL (1 << 31)
4218#define DE_SPRITEB_FLIP_DONE (1 << 29)
4219#define DE_SPRITEA_FLIP_DONE (1 << 28)
4220#define DE_PLANEB_FLIP_DONE (1 << 27)
4221#define DE_PLANEA_FLIP_DONE (1 << 26)
4222#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
4223#define DE_PCU_EVENT (1 << 25)
4224#define DE_GTT_FAULT (1 << 24)
4225#define DE_POISON (1 << 23)
4226#define DE_PERFORM_COUNTER (1 << 22)
4227#define DE_PCH_EVENT (1 << 21)
4228#define DE_AUX_CHANNEL_A (1 << 20)
4229#define DE_DP_A_HOTPLUG (1 << 19)
4230#define DE_GSE (1 << 18)
4231#define DE_PIPEB_VBLANK (1 << 15)
4232#define DE_PIPEB_EVEN_FIELD (1 << 14)
4233#define DE_PIPEB_ODD_FIELD (1 << 13)
4234#define DE_PIPEB_LINE_COMPARE (1 << 12)
4235#define DE_PIPEB_VSYNC (1 << 11)
4236#define DE_PIPEB_CRC_DONE (1 << 10)
4237#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
4238#define DE_PIPEA_VBLANK (1 << 7)
4239#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
4240#define DE_PIPEA_EVEN_FIELD (1 << 6)
4241#define DE_PIPEA_ODD_FIELD (1 << 5)
4242#define DE_PIPEA_LINE_COMPARE (1 << 4)
4243#define DE_PIPEA_VSYNC (1 << 3)
4244#define DE_PIPEA_CRC_DONE (1 << 2)
4245#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
4246#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
4247#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
4248
4249/* More Ivybridge lolz */
4250#define DE_ERR_INT_IVB (1 << 30)
4251#define DE_GSE_IVB (1 << 29)
4252#define DE_PCH_EVENT_IVB (1 << 28)
4253#define DE_DP_A_HOTPLUG_IVB (1 << 27)
4254#define DE_AUX_CHANNEL_A_IVB (1 << 26)
4255#define DE_EDP_PSR_INT_HSW (1 << 19)
4256#define DE_SPRITEC_FLIP_DONE_IVB (1 << 14)
4257#define DE_PLANEC_FLIP_DONE_IVB (1 << 13)
4258#define DE_PIPEC_VBLANK_IVB (1 << 10)
4259#define DE_SPRITEB_FLIP_DONE_IVB (1 << 9)
4260#define DE_PLANEB_FLIP_DONE_IVB (1 << 8)
4261#define DE_PIPEB_VBLANK_IVB (1 << 5)
4262#define DE_SPRITEA_FLIP_DONE_IVB (1 << 4)
4263#define DE_PLANEA_FLIP_DONE_IVB (1 << 3)
4264#define DE_PLANE_FLIP_DONE_IVB(plane) (1 << (3 + 5 * (plane)))
4265#define DE_PIPEA_VBLANK_IVB (1 << 0)
4266#define DE_PIPE_VBLANK_IVB(pipe) (1 << ((pipe) * 5))
4267
4268#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
4269#define MASTER_INTERRUPT_ENABLE (1 << 31)
4270
4271#define DEISR _MMIO(0x44000)
4272#define DEIMR _MMIO(0x44004)
4273#define DEIIR _MMIO(0x44008)
4274#define DEIER _MMIO(0x4400c)
4275
4276#define GTISR _MMIO(0x44010)
4277#define GTIMR _MMIO(0x44014)
4278#define GTIIR _MMIO(0x44018)
4279#define GTIER _MMIO(0x4401c)
4280
4281#define GEN8_MASTER_IRQ _MMIO(0x44200)
4282#define GEN8_MASTER_IRQ_CONTROL (1 << 31)
4283#define GEN8_PCU_IRQ (1 << 30)
4284#define GEN8_DE_PCH_IRQ (1 << 23)
4285#define GEN8_DE_MISC_IRQ (1 << 22)
4286#define GEN8_DE_PORT_IRQ (1 << 20)
4287#define GEN8_DE_PIPE_C_IRQ (1 << 18)
4288#define GEN8_DE_PIPE_B_IRQ (1 << 17)
4289#define GEN8_DE_PIPE_A_IRQ (1 << 16)
4290#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
4291#define GEN8_GT_VECS_IRQ (1 << 6)
4292#define GEN8_GT_GUC_IRQ (1 << 5)
4293#define GEN8_GT_PM_IRQ (1 << 4)
4294#define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
4295#define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
4296#define GEN8_GT_BCS_IRQ (1 << 1)
4297#define GEN8_GT_RCS_IRQ (1 << 0)
4298
4299#define XELPD_DISPLAY_ERR_FATAL_MASK _MMIO(0x4421c)
4300
4301#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
4302#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
4303#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
4304#define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
4305
4306#define GEN8_RCS_IRQ_SHIFT 0
4307#define GEN8_BCS_IRQ_SHIFT 16
4308#define GEN8_VCS0_IRQ_SHIFT 0 /* NB: VCS1 in bspec! */
4309#define GEN8_VCS1_IRQ_SHIFT 16 /* NB: VCS2 in bpsec! */
4310#define GEN8_VECS_IRQ_SHIFT 0
4311#define GEN8_WD_IRQ_SHIFT 16
4312
4313#define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
4314#define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
4315#define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
4316#define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
4317#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
4318#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
4319#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
4320#define XELPD_PIPE_SOFT_UNDERRUN (1 << 22)
4321#define XELPD_PIPE_HARD_UNDERRUN (1 << 21)
4322#define GEN12_PIPE_VBLANK_UNMOD (1 << 19)
4323#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
4324#define GEN8_PIPE_SPRITE_FAULT (1 << 9)
4325#define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
4326#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
4327#define GEN8_PIPE_PRIMARY_FLIP_DONE (1 << 4)
4328#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
4329#define GEN8_PIPE_VSYNC (1 << 1)
4330#define GEN8_PIPE_VBLANK (1 << 0)
4331#define GEN9_PIPE_CURSOR_FAULT (1 << 11)
4332#define GEN11_PIPE_PLANE7_FAULT (1 << 22)
4333#define GEN11_PIPE_PLANE6_FAULT (1 << 21)
4334#define GEN11_PIPE_PLANE5_FAULT (1 << 20)
4335#define GEN9_PIPE_PLANE4_FAULT (1 << 10)
4336#define GEN9_PIPE_PLANE3_FAULT (1 << 9)
4337#define GEN9_PIPE_PLANE2_FAULT (1 << 8)
4338#define GEN9_PIPE_PLANE1_FAULT (1 << 7)
4339#define GEN9_PIPE_PLANE4_FLIP_DONE (1 << 6)
4340#define GEN9_PIPE_PLANE3_FLIP_DONE (1 << 5)
4341#define GEN9_PIPE_PLANE2_FLIP_DONE (1 << 4)
4342#define GEN9_PIPE_PLANE1_FLIP_DONE (1 << 3)
4343#define GEN9_PIPE_PLANE_FLIP_DONE(p) (1 << (3 + (p)))
4344#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
4345 (GEN8_PIPE_CURSOR_FAULT | \
4346 GEN8_PIPE_SPRITE_FAULT | \
4347 GEN8_PIPE_PRIMARY_FAULT)
4348#define GEN9_DE_PIPE_IRQ_FAULT_ERRORS \
4349 (GEN9_PIPE_CURSOR_FAULT | \
4350 GEN9_PIPE_PLANE4_FAULT | \
4351 GEN9_PIPE_PLANE3_FAULT | \
4352 GEN9_PIPE_PLANE2_FAULT | \
4353 GEN9_PIPE_PLANE1_FAULT)
4354#define GEN11_DE_PIPE_IRQ_FAULT_ERRORS \
4355 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
4356 GEN11_PIPE_PLANE7_FAULT | \
4357 GEN11_PIPE_PLANE6_FAULT | \
4358 GEN11_PIPE_PLANE5_FAULT)
4359#define RKL_DE_PIPE_IRQ_FAULT_ERRORS \
4360 (GEN9_DE_PIPE_IRQ_FAULT_ERRORS | \
4361 GEN11_PIPE_PLANE5_FAULT)
4362
4363#define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
4364#define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
4365
4366#define GEN8_DE_PORT_ISR _MMIO(0x44440)
4367#define GEN8_DE_PORT_IMR _MMIO(0x44444)
4368#define GEN8_DE_PORT_IIR _MMIO(0x44448)
4369#define GEN8_DE_PORT_IER _MMIO(0x4444c)
4370#define DSI1_NON_TE (1 << 31)
4371#define DSI0_NON_TE (1 << 30)
4372#define ICL_AUX_CHANNEL_E (1 << 29)
4373#define ICL_AUX_CHANNEL_F (1 << 28)
4374#define GEN9_AUX_CHANNEL_D (1 << 27)
4375#define GEN9_AUX_CHANNEL_C (1 << 26)
4376#define GEN9_AUX_CHANNEL_B (1 << 25)
4377#define DSI1_TE (1 << 24)
4378#define DSI0_TE (1 << 23)
4379#define GEN8_DE_PORT_HOTPLUG(hpd_pin) REG_BIT(3 + _HPD_PIN_DDI(hpd_pin))
4380#define BXT_DE_PORT_HOTPLUG_MASK (GEN8_DE_PORT_HOTPLUG(HPD_PORT_A) | \
4381 GEN8_DE_PORT_HOTPLUG(HPD_PORT_B) | \
4382 GEN8_DE_PORT_HOTPLUG(HPD_PORT_C))
4383#define BDW_DE_PORT_HOTPLUG_MASK GEN8_DE_PORT_HOTPLUG(HPD_PORT_A)
4384#define BXT_DE_PORT_GMBUS (1 << 1)
4385#define GEN8_AUX_CHANNEL_A (1 << 0)
4386#define TGL_DE_PORT_AUX_USBC6 REG_BIT(13)
4387#define XELPD_DE_PORT_AUX_DDIE REG_BIT(13)
4388#define TGL_DE_PORT_AUX_USBC5 REG_BIT(12)
4389#define XELPD_DE_PORT_AUX_DDID REG_BIT(12)
4390#define TGL_DE_PORT_AUX_USBC4 REG_BIT(11)
4391#define TGL_DE_PORT_AUX_USBC3 REG_BIT(10)
4392#define TGL_DE_PORT_AUX_USBC2 REG_BIT(9)
4393#define TGL_DE_PORT_AUX_USBC1 REG_BIT(8)
4394#define TGL_DE_PORT_AUX_DDIC REG_BIT(2)
4395#define TGL_DE_PORT_AUX_DDIB REG_BIT(1)
4396#define TGL_DE_PORT_AUX_DDIA REG_BIT(0)
4397
4398#define GEN8_DE_MISC_ISR _MMIO(0x44460)
4399#define GEN8_DE_MISC_IMR _MMIO(0x44464)
4400#define GEN8_DE_MISC_IIR _MMIO(0x44468)
4401#define GEN8_DE_MISC_IER _MMIO(0x4446c)
4402#define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
4403#define GEN8_DE_MISC_GSE REG_BIT(27)
4404#define GEN8_DE_EDP_PSR REG_BIT(19)
4405#define XELPDP_PMDEMAND_RSP REG_BIT(3)
4406
4407#define GEN8_PCU_ISR _MMIO(0x444e0)
4408#define GEN8_PCU_IMR _MMIO(0x444e4)
4409#define GEN8_PCU_IIR _MMIO(0x444e8)
4410#define GEN8_PCU_IER _MMIO(0x444ec)
4411
4412#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
4413#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
4414#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
4415#define GEN11_GU_MISC_IER _MMIO(0x444fc)
4416#define GEN11_GU_MISC_GSE (1 << 27)
4417
4418#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
4419#define GEN11_MASTER_IRQ (1 << 31)
4420#define GEN11_PCU_IRQ (1 << 30)
4421#define GEN11_GU_MISC_IRQ (1 << 29)
4422#define GEN11_DISPLAY_IRQ (1 << 16)
4423#define GEN11_GT_DW_IRQ(x) (1 << (x))
4424#define GEN11_GT_DW1_IRQ (1 << 1)
4425#define GEN11_GT_DW0_IRQ (1 << 0)
4426
4427#define DG1_MSTR_TILE_INTR _MMIO(0x190008)
4428#define DG1_MSTR_IRQ REG_BIT(31)
4429#define DG1_MSTR_TILE(t) REG_BIT(t)
4430
4431#define GEN11_DISPLAY_INT_CTL _MMIO(0x44200)
4432#define GEN11_DISPLAY_IRQ_ENABLE (1 << 31)
4433#define GEN11_AUDIO_CODEC_IRQ (1 << 24)
4434#define GEN11_DE_PCH_IRQ (1 << 23)
4435#define GEN11_DE_MISC_IRQ (1 << 22)
4436#define GEN11_DE_HPD_IRQ (1 << 21)
4437#define GEN11_DE_PORT_IRQ (1 << 20)
4438#define GEN11_DE_PIPE_C (1 << 18)
4439#define GEN11_DE_PIPE_B (1 << 17)
4440#define GEN11_DE_PIPE_A (1 << 16)
4441
4442#define GEN11_DE_HPD_ISR _MMIO(0x44470)
4443#define GEN11_DE_HPD_IMR _MMIO(0x44474)
4444#define GEN11_DE_HPD_IIR _MMIO(0x44478)
4445#define GEN11_DE_HPD_IER _MMIO(0x4447c)
4446#define GEN11_TC_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
4447#define GEN11_DE_TC_HOTPLUG_MASK (GEN11_TC_HOTPLUG(HPD_PORT_TC6) | \
4448 GEN11_TC_HOTPLUG(HPD_PORT_TC5) | \
4449 GEN11_TC_HOTPLUG(HPD_PORT_TC4) | \
4450 GEN11_TC_HOTPLUG(HPD_PORT_TC3) | \
4451 GEN11_TC_HOTPLUG(HPD_PORT_TC2) | \
4452 GEN11_TC_HOTPLUG(HPD_PORT_TC1))
4453#define GEN11_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
4454#define GEN11_DE_TBT_HOTPLUG_MASK (GEN11_TBT_HOTPLUG(HPD_PORT_TC6) | \
4455 GEN11_TBT_HOTPLUG(HPD_PORT_TC5) | \
4456 GEN11_TBT_HOTPLUG(HPD_PORT_TC4) | \
4457 GEN11_TBT_HOTPLUG(HPD_PORT_TC3) | \
4458 GEN11_TBT_HOTPLUG(HPD_PORT_TC2) | \
4459 GEN11_TBT_HOTPLUG(HPD_PORT_TC1))
4460
4461#define GEN11_TBT_HOTPLUG_CTL _MMIO(0x44030)
4462#define GEN11_TC_HOTPLUG_CTL _MMIO(0x44038)
4463#define GEN11_HOTPLUG_CTL_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
4464#define GEN11_HOTPLUG_CTL_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
4465#define GEN11_HOTPLUG_CTL_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
4466#define GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin) (0 << (_HPD_PIN_TC(hpd_pin) * 4))
4467
4468#define PICAINTERRUPT_ISR _MMIO(0x16FE50)
4469#define PICAINTERRUPT_IMR _MMIO(0x16FE54)
4470#define PICAINTERRUPT_IIR _MMIO(0x16FE58)
4471#define PICAINTERRUPT_IER _MMIO(0x16FE5C)
4472#define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
4473#define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16)
4474#define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
4475#define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8)
4476#define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin))
4477#define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6)
4478#define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
4479#define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
4480
4481#define XELPDP_PORT_HOTPLUG_CTL(hpd_pin) _MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200))
4482#define XELPDP_TBT_HOTPLUG_ENABLE REG_BIT(6)
4483#define XELPDP_TBT_HPD_LONG_DETECT REG_BIT(5)
4484#define XELPDP_TBT_HPD_SHORT_DETECT REG_BIT(4)
4485#define XELPDP_DP_ALT_HOTPLUG_ENABLE REG_BIT(2)
4486#define XELPDP_DP_ALT_HPD_LONG_DETECT REG_BIT(1)
4487#define XELPDP_DP_ALT_HPD_SHORT_DETECT REG_BIT(0)
4488
4489#define XELPDP_INITIATE_PMDEMAND_REQUEST(dword) _MMIO(0x45230 + 4 * (dword))
4490#define XELPDP_PMDEMAND_QCLK_GV_BW_MASK REG_GENMASK(31, 16)
4491#define XELPDP_PMDEMAND_VOLTAGE_INDEX_MASK REG_GENMASK(14, 12)
4492#define XELPDP_PMDEMAND_QCLK_GV_INDEX_MASK REG_GENMASK(11, 8)
4493#define XELPDP_PMDEMAND_PIPES_MASK REG_GENMASK(7, 6)
4494#define XELPDP_PMDEMAND_DBUFS_MASK REG_GENMASK(5, 4)
4495#define XELPDP_PMDEMAND_PHYS_MASK REG_GENMASK(2, 0)
4496
4497#define XELPDP_PMDEMAND_REQ_ENABLE REG_BIT(31)
4498#define XELPDP_PMDEMAND_CDCLK_FREQ_MASK REG_GENMASK(30, 20)
4499#define XELPDP_PMDEMAND_DDICLK_FREQ_MASK REG_GENMASK(18, 8)
4500#define XELPDP_PMDEMAND_SCALERS_MASK REG_GENMASK(6, 4)
4501#define XELPDP_PMDEMAND_PLLS_MASK REG_GENMASK(2, 0)
4502
4503#define GEN12_DCPR_STATUS_1 _MMIO(0x46440)
4504#define XELPDP_PMDEMAND_INFLIGHT_STATUS REG_BIT(26)
4505
4506#define ILK_DISPLAY_CHICKEN2 _MMIO(0x42004)
4507/* Required on all Ironlake and Sandybridge according to the B-Spec. */
4508#define ILK_ELPIN_409_SELECT REG_BIT(25)
4509#define ILK_DPARB_GATE REG_BIT(22)
4510#define ILK_VSDPFD_FULL REG_BIT(21)
4511
4512#define FUSE_STRAP _MMIO(0x42014)
4513#define ILK_INTERNAL_GRAPHICS_DISABLE REG_BIT(31)
4514#define ILK_INTERNAL_DISPLAY_DISABLE REG_BIT(30)
4515#define ILK_DISPLAY_DEBUG_DISABLE REG_BIT(29)
4516#define IVB_PIPE_C_DISABLE REG_BIT(28)
4517#define ILK_HDCP_DISABLE REG_BIT(25)
4518#define ILK_eDP_A_DISABLE REG_BIT(24)
4519#define HSW_CDCLK_LIMIT REG_BIT(24)
4520#define ILK_DESKTOP REG_BIT(23)
4521#define HSW_CPU_SSC_ENABLE REG_BIT(21)
4522
4523#define FUSE_STRAP3 _MMIO(0x42020)
4524#define HSW_REF_CLK_SELECT REG_BIT(1)
4525
4526#define ILK_DSPCLK_GATE_D _MMIO(0x42020)
4527#define ILK_VRHUNIT_CLOCK_GATE_DISABLE REG_BIT(28)
4528#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE REG_BIT(9)
4529#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE REG_BIT(8)
4530#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE REG_BIT(7)
4531#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE REG_BIT(5)
4532
4533#define IVB_CHICKEN3 _MMIO(0x4200c)
4534#define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5)
4535#define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2)
4536
4537#define CHICKEN_PAR1_1 _MMIO(0x42080)
4538#define IGNORE_KVMR_PIPE_A REG_BIT(23)
4539#define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
4540#define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16)
4541#define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15)
4542#define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */
4543#define FORCE_ARB_IDLE_PLANES REG_BIT(14)
4544#define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3)
4545#define IGNORE_PSR2_HW_TRACKING REG_BIT(1)
4546
4547#define CHICKEN_PAR2_1 _MMIO(0x42090)
4548#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
4549
4550#define CHICKEN_MISC_2 _MMIO(0x42084)
4551#define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */
4552#define KBL_ARB_FILL_SPARE_14 REG_BIT(14)
4553#define KBL_ARB_FILL_SPARE_13 REG_BIT(13)
4554#define GLK_CL2_PWR_DOWN REG_BIT(12)
4555#define GLK_CL1_PWR_DOWN REG_BIT(11)
4556#define GLK_CL0_PWR_DOWN REG_BIT(10)
4557
4558#define CHICKEN_MISC_4 _MMIO(0x4208c)
4559#define CHICKEN_FBC_STRIDE_OVERRIDE REG_BIT(13)
4560#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
4561#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
4562
4563#define _CHICKEN_PIPESL_1_A 0x420b0
4564#define _CHICKEN_PIPESL_1_B 0x420b4
4565#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
4566#define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27)
4567#define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
4568#define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
4569#define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
4570#define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
4571#define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25)
4572#define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
4573#define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
4574#define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
4575#define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
4576#define HSW_FBCQ_DIS REG_BIT(22)
4577#define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
4578#define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */
4579#define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0)
4580#define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
4581#define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
4582#define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
4583#define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
4584#define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */
4585
4586#define _CHICKEN_TRANS_A 0x420c0
4587#define _CHICKEN_TRANS_B 0x420c4
4588#define _CHICKEN_TRANS_C 0x420c8
4589#define _CHICKEN_TRANS_EDP 0x420cc
4590#define _CHICKEN_TRANS_D 0x420d8
4591#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \
4592 [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \
4593 [TRANSCODER_A] = _CHICKEN_TRANS_A, \
4594 [TRANSCODER_B] = _CHICKEN_TRANS_B, \
4595 [TRANSCODER_C] = _CHICKEN_TRANS_C, \
4596 [TRANSCODER_D] = _CHICKEN_TRANS_D))
4597#define _MTL_CHICKEN_TRANS_A 0x604e0
4598#define _MTL_CHICKEN_TRANS_B 0x614e0
4599#define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \
4600 _MTL_CHICKEN_TRANS_A, \
4601 _MTL_CHICKEN_TRANS_B)
4602#define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */
4603#define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */
4604#define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
4605#define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
4606#define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */
4607#define FECSTALL_DIS_DPTSTREAM_DPTTG REG_BIT(23)
4608#define DDI_TRAINING_OVERRIDE_ENABLE REG_BIT(19)
4609#define ADLP_1_BASED_X_GRANULARITY REG_BIT(18)
4610#define DDI_TRAINING_OVERRIDE_VALUE REG_BIT(18)
4611#define DDIE_TRAINING_OVERRIDE_ENABLE REG_BIT(17) /* CHICKEN_TRANS_A only */
4612#define DDIE_TRAINING_OVERRIDE_VALUE REG_BIT(16) /* CHICKEN_TRANS_A only */
4613#define PSR2_ADD_VERTICAL_LINE_COUNT REG_BIT(15)
4614#define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12)
4615
4616#define DISP_ARB_CTL _MMIO(0x45000)
4617#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
4618#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
4619#define DISP_FBC_WM_DIS REG_BIT(15)
4620
4621#define DISP_ARB_CTL2 _MMIO(0x45004)
4622#define DISP_DATA_PARTITION_5_6 REG_BIT(6)
4623#define DISP_IPC_ENABLE REG_BIT(3)
4624
4625#define GEN7_MSG_CTL _MMIO(0x45010)
4626#define WAIT_FOR_PCH_RESET_ACK (1 << 1)
4627#define WAIT_FOR_PCH_FLR_ACK (1 << 0)
4628
4629#define _BW_BUDDY0_CTL 0x45130
4630#define _BW_BUDDY1_CTL 0x45140
4631#define BW_BUDDY_CTL(x) _MMIO(_PICK_EVEN(x, \
4632 _BW_BUDDY0_CTL, \
4633 _BW_BUDDY1_CTL))
4634#define BW_BUDDY_DISABLE REG_BIT(31)
4635#define BW_BUDDY_TLB_REQ_TIMER_MASK REG_GENMASK(21, 16)
4636#define BW_BUDDY_TLB_REQ_TIMER(x) REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, x)
4637
4638#define _BW_BUDDY0_PAGE_MASK 0x45134
4639#define _BW_BUDDY1_PAGE_MASK 0x45144
4640#define BW_BUDDY_PAGE_MASK(x) _MMIO(_PICK_EVEN(x, \
4641 _BW_BUDDY0_PAGE_MASK, \
4642 _BW_BUDDY1_PAGE_MASK))
4643
4644#define HSW_NDE_RSTWRN_OPT _MMIO(0x46408)
4645#define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6)
4646#define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4)
4647
4648#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
4649#define LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
4650#define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
4651#define LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25)
4652#define LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24)
4653#define LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23)
4654#define ICL_DELAY_PMRSP REG_BIT(22)
4655#define DISABLE_FLR_SRC REG_BIT(15)
4656#define MASK_WAKEMEM REG_BIT(13)
4657#define DDI_CLOCK_REG_ACCESS REG_BIT(7)
4658
4659#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
4660#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
4661#define DCPR_MASK_LPMODE REG_BIT(26)
4662#define DCPR_SEND_RESP_IMM REG_BIT(25)
4663#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
4664
4665#define XELPD_CHICKEN_DCPR_3 _MMIO(0x46438)
4666#define DMD_RSP_TIMEOUT_DISABLE REG_BIT(19)
4667
4668#define SKL_DFSM _MMIO(0x51000)
4669#define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
4670#define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
4671#define SKL_DFSM_CDCLK_LIMIT_MASK (3 << 23)
4672#define SKL_DFSM_CDCLK_LIMIT_675 (0 << 23)
4673#define SKL_DFSM_CDCLK_LIMIT_540 (1 << 23)
4674#define SKL_DFSM_CDCLK_LIMIT_450 (2 << 23)
4675#define SKL_DFSM_CDCLK_LIMIT_337_5 (3 << 23)
4676#define ICL_DFSM_DMC_DISABLE (1 << 23)
4677#define SKL_DFSM_PIPE_A_DISABLE (1 << 30)
4678#define SKL_DFSM_PIPE_B_DISABLE (1 << 21)
4679#define SKL_DFSM_PIPE_C_DISABLE (1 << 28)
4680#define TGL_DFSM_PIPE_D_DISABLE (1 << 22)
4681#define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
4682
4683#define XE2LPD_DE_CAP _MMIO(0x41100)
4684#define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30)
4685#define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28)
4686#define XE2LPD_DE_CAP_DSC_REMOVED 1
4687#define XE2LPD_DE_CAP_SCALER_MASK REG_GENMASK(27, 26)
4688#define XE2LPD_DE_CAP_SCALER_SINGLE 1
4689
4690#define SKL_DSSM _MMIO(0x51004)
4691#define ICL_DSSM_CDCLK_PLL_REFCLK_MASK (7 << 29)
4692#define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz (0 << 29)
4693#define ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz (1 << 29)
4694#define ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz (2 << 29)
4695
4696#define GMD_ID_DISPLAY _MMIO(0x510a0)
4697#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
4698#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
4699#define GMD_ID_STEP REG_GENMASK(5, 0)
4700
4701/*GEN11 chicken */
4702#define _PIPEA_CHICKEN 0x70038
4703#define _PIPEB_CHICKEN 0x71038
4704#define _PIPEC_CHICKEN 0x72038
4705#define PIPE_CHICKEN(pipe) _MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
4706 _PIPEB_CHICKEN)
4707#define UNDERRUN_RECOVERY_DISABLE_ADLP REG_BIT(30)
4708#define UNDERRUN_RECOVERY_ENABLE_DG2 REG_BIT(30)
4709#define PIXEL_ROUNDING_TRUNC_FB_PASSTHRU REG_BIT(15)
4710#define DG2_RENDER_CCSTAG_4_3_EN REG_BIT(12)
4711#define PER_PIXEL_ALPHA_BYPASS_EN REG_BIT(7)
4712
4713/* PCH */
4714
4715#define PCH_DISPLAY_BASE 0xc0000u
4716
4717/* south display engine interrupt: IBX */
4718#define SDE_AUDIO_POWER_D (1 << 27)
4719#define SDE_AUDIO_POWER_C (1 << 26)
4720#define SDE_AUDIO_POWER_B (1 << 25)
4721#define SDE_AUDIO_POWER_SHIFT (25)
4722#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
4723#define SDE_GMBUS (1 << 24)
4724#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
4725#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
4726#define SDE_AUDIO_HDCP_MASK (3 << 22)
4727#define SDE_AUDIO_TRANSB (1 << 21)
4728#define SDE_AUDIO_TRANSA (1 << 20)
4729#define SDE_AUDIO_TRANS_MASK (3 << 20)
4730#define SDE_POISON (1 << 19)
4731/* 18 reserved */
4732#define SDE_FDI_RXB (1 << 17)
4733#define SDE_FDI_RXA (1 << 16)
4734#define SDE_FDI_MASK (3 << 16)
4735#define SDE_AUXD (1 << 15)
4736#define SDE_AUXC (1 << 14)
4737#define SDE_AUXB (1 << 13)
4738#define SDE_AUX_MASK (7 << 13)
4739/* 12 reserved */
4740#define SDE_CRT_HOTPLUG (1 << 11)
4741#define SDE_PORTD_HOTPLUG (1 << 10)
4742#define SDE_PORTC_HOTPLUG (1 << 9)
4743#define SDE_PORTB_HOTPLUG (1 << 8)
4744#define SDE_SDVOB_HOTPLUG (1 << 6)
4745#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
4746 SDE_SDVOB_HOTPLUG | \
4747 SDE_PORTB_HOTPLUG | \
4748 SDE_PORTC_HOTPLUG | \
4749 SDE_PORTD_HOTPLUG)
4750#define SDE_TRANSB_CRC_DONE (1 << 5)
4751#define SDE_TRANSB_CRC_ERR (1 << 4)
4752#define SDE_TRANSB_FIFO_UNDER (1 << 3)
4753#define SDE_TRANSA_CRC_DONE (1 << 2)
4754#define SDE_TRANSA_CRC_ERR (1 << 1)
4755#define SDE_TRANSA_FIFO_UNDER (1 << 0)
4756#define SDE_TRANS_MASK (0x3f)
4757
4758/* south display engine interrupt: CPT - CNP */
4759#define SDE_AUDIO_POWER_D_CPT (1 << 31)
4760#define SDE_AUDIO_POWER_C_CPT (1 << 30)
4761#define SDE_AUDIO_POWER_B_CPT (1 << 29)
4762#define SDE_AUDIO_POWER_SHIFT_CPT 29
4763#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
4764#define SDE_AUXD_CPT (1 << 27)
4765#define SDE_AUXC_CPT (1 << 26)
4766#define SDE_AUXB_CPT (1 << 25)
4767#define SDE_AUX_MASK_CPT (7 << 25)
4768#define SDE_PORTE_HOTPLUG_SPT (1 << 25)
4769#define SDE_PORTA_HOTPLUG_SPT (1 << 24)
4770#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
4771#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
4772#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
4773#define SDE_CRT_HOTPLUG_CPT (1 << 19)
4774#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
4775#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
4776 SDE_SDVOB_HOTPLUG_CPT | \
4777 SDE_PORTD_HOTPLUG_CPT | \
4778 SDE_PORTC_HOTPLUG_CPT | \
4779 SDE_PORTB_HOTPLUG_CPT)
4780#define SDE_HOTPLUG_MASK_SPT (SDE_PORTE_HOTPLUG_SPT | \
4781 SDE_PORTD_HOTPLUG_CPT | \
4782 SDE_PORTC_HOTPLUG_CPT | \
4783 SDE_PORTB_HOTPLUG_CPT | \
4784 SDE_PORTA_HOTPLUG_SPT)
4785#define SDE_GMBUS_CPT (1 << 17)
4786#define SDE_ERROR_CPT (1 << 16)
4787#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
4788#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
4789#define SDE_FDI_RXC_CPT (1 << 8)
4790#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
4791#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
4792#define SDE_FDI_RXB_CPT (1 << 4)
4793#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
4794#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
4795#define SDE_FDI_RXA_CPT (1 << 0)
4796#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
4797 SDE_AUDIO_CP_REQ_B_CPT | \
4798 SDE_AUDIO_CP_REQ_A_CPT)
4799#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
4800 SDE_AUDIO_CP_CHG_B_CPT | \
4801 SDE_AUDIO_CP_CHG_A_CPT)
4802#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
4803 SDE_FDI_RXB_CPT | \
4804 SDE_FDI_RXA_CPT)
4805
4806/* south display engine interrupt: ICP/TGP/MTP */
4807#define SDE_PICAINTERRUPT REG_BIT(31)
4808#define SDE_GMBUS_ICP (1 << 23)
4809#define SDE_TC_HOTPLUG_ICP(hpd_pin) REG_BIT(24 + _HPD_PIN_TC(hpd_pin))
4810#define SDE_TC_HOTPLUG_DG2(hpd_pin) REG_BIT(25 + _HPD_PIN_TC(hpd_pin)) /* sigh */
4811#define SDE_DDI_HOTPLUG_ICP(hpd_pin) REG_BIT(16 + _HPD_PIN_DDI(hpd_pin))
4812#define SDE_DDI_HOTPLUG_MASK_ICP (SDE_DDI_HOTPLUG_ICP(HPD_PORT_D) | \
4813 SDE_DDI_HOTPLUG_ICP(HPD_PORT_C) | \
4814 SDE_DDI_HOTPLUG_ICP(HPD_PORT_B) | \
4815 SDE_DDI_HOTPLUG_ICP(HPD_PORT_A))
4816#define SDE_TC_HOTPLUG_MASK_ICP (SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6) | \
4817 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5) | \
4818 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4) | \
4819 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3) | \
4820 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
4821 SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
4822
4823#define SDEISR _MMIO(0xc4000)
4824#define SDEIMR _MMIO(0xc4004)
4825#define SDEIIR _MMIO(0xc4008)
4826#define SDEIER _MMIO(0xc400c)
4827
4828#define SERR_INT _MMIO(0xc4040)
4829#define SERR_INT_POISON (1 << 31)
4830#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
4831
4832/* digital port hotplug */
4833#define PCH_PORT_HOTPLUG _MMIO(0xc4030) /* SHOTPLUG_CTL */
4834#define PORTA_HOTPLUG_ENABLE (1 << 28) /* LPT:LP+ & BXT */
4835#define BXT_DDIA_HPD_INVERT (1 << 27)
4836#define PORTA_HOTPLUG_STATUS_MASK (3 << 24) /* SPT+ & BXT */
4837#define PORTA_HOTPLUG_NO_DETECT (0 << 24) /* SPT+ & BXT */
4838#define PORTA_HOTPLUG_SHORT_DETECT (1 << 24) /* SPT+ & BXT */
4839#define PORTA_HOTPLUG_LONG_DETECT (2 << 24) /* SPT+ & BXT */
4840#define PORTD_HOTPLUG_ENABLE (1 << 20)
4841#define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
4842#define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
4843#define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
4844#define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
4845#define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
4846#define PORTD_HOTPLUG_STATUS_MASK (3 << 16)
4847#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
4848#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
4849#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
4850#define PORTC_HOTPLUG_ENABLE (1 << 12)
4851#define BXT_DDIC_HPD_INVERT (1 << 11)
4852#define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
4853#define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
4854#define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
4855#define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
4856#define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
4857#define PORTC_HOTPLUG_STATUS_MASK (3 << 8)
4858#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
4859#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
4860#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
4861#define PORTB_HOTPLUG_ENABLE (1 << 4)
4862#define BXT_DDIB_HPD_INVERT (1 << 3)
4863#define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
4864#define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
4865#define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
4866#define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
4867#define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
4868#define PORTB_HOTPLUG_STATUS_MASK (3 << 0)
4869#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
4870#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
4871#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
4872#define BXT_DDI_HPD_INVERT_MASK (BXT_DDIA_HPD_INVERT | \
4873 BXT_DDIB_HPD_INVERT | \
4874 BXT_DDIC_HPD_INVERT)
4875
4876#define PCH_PORT_HOTPLUG2 _MMIO(0xc403C) /* SHOTPLUG_CTL2 SPT+ */
4877#define PORTE_HOTPLUG_ENABLE (1 << 4)
4878#define PORTE_HOTPLUG_STATUS_MASK (3 << 0)
4879#define PORTE_HOTPLUG_NO_DETECT (0 << 0)
4880#define PORTE_HOTPLUG_SHORT_DETECT (1 << 0)
4881#define PORTE_HOTPLUG_LONG_DETECT (2 << 0)
4882
4883/* This register is a reuse of PCH_PORT_HOTPLUG register. The
4884 * functionality covered in PCH_PORT_HOTPLUG is split into
4885 * SHOTPLUG_CTL_DDI and SHOTPLUG_CTL_TC.
4886 */
4887
4888#define SHOTPLUG_CTL_DDI _MMIO(0xc4030)
4889#define SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin) (0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
4890#define SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin) (0x4 << (_HPD_PIN_DDI(hpd_pin) * 4))
4891#define SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
4892#define SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin) (0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
4893#define SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin) (0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
4894#define SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin) (0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
4895#define SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin) (0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
4896
4897#define SHOTPLUG_CTL_TC _MMIO(0xc4034)
4898#define ICP_TC_HPD_ENABLE(hpd_pin) (8 << (_HPD_PIN_TC(hpd_pin) * 4))
4899#define ICP_TC_HPD_LONG_DETECT(hpd_pin) (2 << (_HPD_PIN_TC(hpd_pin) * 4))
4900#define ICP_TC_HPD_SHORT_DETECT(hpd_pin) (1 << (_HPD_PIN_TC(hpd_pin) * 4))
4901
4902#define SHPD_FILTER_CNT _MMIO(0xc4038)
4903#define SHPD_FILTER_CNT_500_ADJ 0x001D9
4904#define SHPD_FILTER_CNT_250 0x000F8
4905
4906#define _PCH_DPLL_A 0xc6014
4907#define _PCH_DPLL_B 0xc6018
4908#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
4909
4910#define _PCH_FPA0 0xc6040
4911#define FP_CB_TUNE (0x3 << 22)
4912#define _PCH_FPA1 0xc6044
4913#define _PCH_FPB0 0xc6048
4914#define _PCH_FPB1 0xc604c
4915#define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
4916#define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
4917
4918#define PCH_DPLL_TEST _MMIO(0xc606c)
4919
4920#define PCH_DREF_CONTROL _MMIO(0xC6200)
4921#define DREF_CONTROL_MASK 0x7fc3
4922#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
4923#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
4924#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
4925#define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
4926#define DREF_SSC_SOURCE_DISABLE (0 << 11)
4927#define DREF_SSC_SOURCE_ENABLE (2 << 11)
4928#define DREF_SSC_SOURCE_MASK (3 << 11)
4929#define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
4930#define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
4931#define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
4932#define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
4933#define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
4934#define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
4935#define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
4936#define DREF_SSC4_DOWNSPREAD (0 << 6)
4937#define DREF_SSC4_CENTERSPREAD (1 << 6)
4938#define DREF_SSC1_DISABLE (0 << 1)
4939#define DREF_SSC1_ENABLE (1 << 1)
4940#define DREF_SSC4_DISABLE (0)
4941#define DREF_SSC4_ENABLE (1)
4942
4943#define PCH_RAWCLK_FREQ _MMIO(0xc6204)
4944#define FDL_TP1_TIMER_SHIFT 12
4945#define FDL_TP1_TIMER_MASK (3 << 12)
4946#define FDL_TP2_TIMER_SHIFT 10
4947#define FDL_TP2_TIMER_MASK (3 << 10)
4948#define RAWCLK_FREQ_MASK 0x3ff
4949#define CNP_RAWCLK_DIV_MASK (0x3ff << 16)
4950#define CNP_RAWCLK_DIV(div) ((div) << 16)
4951#define CNP_RAWCLK_FRAC_MASK (0xf << 26)
4952#define CNP_RAWCLK_DEN(den) ((den) << 26)
4953#define ICP_RAWCLK_NUM(num) ((num) << 11)
4954
4955#define PCH_DPLL_TMR_CFG _MMIO(0xc6208)
4956
4957#define PCH_SSC4_PARMS _MMIO(0xc6210)
4958#define PCH_SSC4_AUX_PARMS _MMIO(0xc6214)
4959
4960#define PCH_DPLL_SEL _MMIO(0xc7000)
4961#define TRANS_DPLLB_SEL(pipe) (1 << ((pipe) * 4))
4962#define TRANS_DPLLA_SEL(pipe) 0
4963#define TRANS_DPLL_ENABLE(pipe) (1 << ((pipe) * 4 + 3))
4964
4965/* transcoder */
4966
4967#define _PCH_TRANS_HTOTAL_A 0xe0000
4968#define TRANS_HTOTAL_SHIFT 16
4969#define TRANS_HACTIVE_SHIFT 0
4970#define _PCH_TRANS_HBLANK_A 0xe0004
4971#define TRANS_HBLANK_END_SHIFT 16
4972#define TRANS_HBLANK_START_SHIFT 0
4973#define _PCH_TRANS_HSYNC_A 0xe0008
4974#define TRANS_HSYNC_END_SHIFT 16
4975#define TRANS_HSYNC_START_SHIFT 0
4976#define _PCH_TRANS_VTOTAL_A 0xe000c
4977#define TRANS_VTOTAL_SHIFT 16
4978#define TRANS_VACTIVE_SHIFT 0
4979#define _PCH_TRANS_VBLANK_A 0xe0010
4980#define TRANS_VBLANK_END_SHIFT 16
4981#define TRANS_VBLANK_START_SHIFT 0
4982#define _PCH_TRANS_VSYNC_A 0xe0014
4983#define TRANS_VSYNC_END_SHIFT 16
4984#define TRANS_VSYNC_START_SHIFT 0
4985#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
4986
4987#define _PCH_TRANSA_DATA_M1 0xe0030
4988#define _PCH_TRANSA_DATA_N1 0xe0034
4989#define _PCH_TRANSA_DATA_M2 0xe0038
4990#define _PCH_TRANSA_DATA_N2 0xe003c
4991#define _PCH_TRANSA_LINK_M1 0xe0040
4992#define _PCH_TRANSA_LINK_N1 0xe0044
4993#define _PCH_TRANSA_LINK_M2 0xe0048
4994#define _PCH_TRANSA_LINK_N2 0xe004c
4995
4996/* Per-transcoder DIP controls (PCH) */
4997#define _VIDEO_DIP_CTL_A 0xe0200
4998#define _VIDEO_DIP_DATA_A 0xe0208
4999#define _VIDEO_DIP_GCP_A 0xe0210
5000#define GCP_COLOR_INDICATION (1 << 2)
5001#define GCP_DEFAULT_PHASE_ENABLE (1 << 1)
5002#define GCP_AV_MUTE (1 << 0)
5003
5004#define _VIDEO_DIP_CTL_B 0xe1200
5005#define _VIDEO_DIP_DATA_B 0xe1208
5006#define _VIDEO_DIP_GCP_B 0xe1210
5007
5008#define TVIDEO_DIP_CTL(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
5009#define TVIDEO_DIP_DATA(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
5010#define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
5011
5012/* Per-transcoder DIP controls (VLV) */
5013#define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
5014#define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
5015#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
5016
5017#define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
5018#define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
5019#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
5020
5021#define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
5022#define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
5023#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
5024
5025#define VLV_TVIDEO_DIP_CTL(pipe) \
5026 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \
5027 _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C)
5028#define VLV_TVIDEO_DIP_DATA(pipe) \
5029 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \
5030 _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C)
5031#define VLV_TVIDEO_DIP_GCP(pipe) \
5032 _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \
5033 _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C)
5034
5035/* Haswell DIP controls */
5036
5037#define _HSW_VIDEO_DIP_CTL_A 0x60200
5038#define _HSW_VIDEO_DIP_AVI_DATA_A 0x60220
5039#define _HSW_VIDEO_DIP_VS_DATA_A 0x60260
5040#define _HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
5041#define _HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
5042#define _HSW_VIDEO_DIP_VSC_DATA_A 0x60320
5043#define _GLK_VIDEO_DIP_DRM_DATA_A 0x60440
5044#define _HSW_VIDEO_DIP_AVI_ECC_A 0x60240
5045#define _HSW_VIDEO_DIP_VS_ECC_A 0x60280
5046#define _HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
5047#define _HSW_VIDEO_DIP_GMP_ECC_A 0x60300
5048#define _HSW_VIDEO_DIP_VSC_ECC_A 0x60344
5049#define _HSW_VIDEO_DIP_GCP_A 0x60210
5050
5051#define _HSW_VIDEO_DIP_CTL_B 0x61200
5052#define _HSW_VIDEO_DIP_AVI_DATA_B 0x61220
5053#define _HSW_VIDEO_DIP_VS_DATA_B 0x61260
5054#define _HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
5055#define _HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
5056#define _HSW_VIDEO_DIP_VSC_DATA_B 0x61320
5057#define _GLK_VIDEO_DIP_DRM_DATA_B 0x61440
5058#define _HSW_VIDEO_DIP_BVI_ECC_B 0x61240
5059#define _HSW_VIDEO_DIP_VS_ECC_B 0x61280
5060#define _HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
5061#define _HSW_VIDEO_DIP_GMP_ECC_B 0x61300
5062#define _HSW_VIDEO_DIP_VSC_ECC_B 0x61344
5063#define _HSW_VIDEO_DIP_GCP_B 0x61210
5064
5065/* Icelake PPS_DATA and _ECC DIP Registers.
5066 * These are available for transcoders B,C and eDP.
5067 * Adding the _A so as to reuse the _MMIO_TRANS2
5068 * definition, with which it offsets to the right location.
5069 */
5070
5071#define _ICL_VIDEO_DIP_PPS_DATA_A 0x60350
5072#define _ICL_VIDEO_DIP_PPS_DATA_B 0x61350
5073#define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4
5074#define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4
5075
5076#define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A)
5077#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
5078#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4)
5079#define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4)
5080#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
5081#define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4)
5082#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
5083#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
5084#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
5085#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
5086
5087#define _HSW_STEREO_3D_CTL_A 0x70020
5088#define S3D_ENABLE (1 << 31)
5089#define _HSW_STEREO_3D_CTL_B 0x71020
5090
5091#define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A)
5092
5093#define _PCH_TRANS_HTOTAL_B 0xe1000
5094#define _PCH_TRANS_HBLANK_B 0xe1004
5095#define _PCH_TRANS_HSYNC_B 0xe1008
5096#define _PCH_TRANS_VTOTAL_B 0xe100c
5097#define _PCH_TRANS_VBLANK_B 0xe1010
5098#define _PCH_TRANS_VSYNC_B 0xe1014
5099#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
5100
5101#define PCH_TRANS_HTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
5102#define PCH_TRANS_HBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
5103#define PCH_TRANS_HSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
5104#define PCH_TRANS_VTOTAL(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
5105#define PCH_TRANS_VBLANK(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
5106#define PCH_TRANS_VSYNC(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
5107#define PCH_TRANS_VSYNCSHIFT(pipe) _MMIO_PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, _PCH_TRANS_VSYNCSHIFT_B)
5108
5109#define _PCH_TRANSB_DATA_M1 0xe1030
5110#define _PCH_TRANSB_DATA_N1 0xe1034
5111#define _PCH_TRANSB_DATA_M2 0xe1038
5112#define _PCH_TRANSB_DATA_N2 0xe103c
5113#define _PCH_TRANSB_LINK_M1 0xe1040
5114#define _PCH_TRANSB_LINK_N1 0xe1044
5115#define _PCH_TRANSB_LINK_M2 0xe1048
5116#define _PCH_TRANSB_LINK_N2 0xe104c
5117
5118#define PCH_TRANS_DATA_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
5119#define PCH_TRANS_DATA_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
5120#define PCH_TRANS_DATA_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
5121#define PCH_TRANS_DATA_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
5122#define PCH_TRANS_LINK_M1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
5123#define PCH_TRANS_LINK_N1(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
5124#define PCH_TRANS_LINK_M2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
5125#define PCH_TRANS_LINK_N2(pipe) _MMIO_PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
5126
5127#define _PCH_TRANSACONF 0xf0008
5128#define _PCH_TRANSBCONF 0xf1008
5129#define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
5130#define LPT_TRANSCONF PCH_TRANSCONF(PIPE_A) /* lpt has only one transcoder */
5131#define TRANS_ENABLE REG_BIT(31)
5132#define TRANS_STATE_ENABLE REG_BIT(30)
5133#define TRANS_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* ibx */
5134#define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
5135#define TRANS_INTERLACE_MASK REG_GENMASK(23, 21)
5136#define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
5137#define TRANS_INTERLACE_LEGACY_VSYNC_IBX REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
5138#define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
5139#define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
5140#define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
5141#define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1)
5142#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
5143#define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
5144
5145#define _TRANSA_CHICKEN1 0xf0060
5146#define _TRANSB_CHICKEN1 0xf1060
5147#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
5148#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
5149#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
5150
5151#define _TRANSA_CHICKEN2 0xf0064
5152#define _TRANSB_CHICKEN2 0xf1064
5153#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
5154#define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31)
5155#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29)
5156#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
5157#define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
5158#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26)
5159#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25)
5160
5161#define SOUTH_CHICKEN1 _MMIO(0xc2000)
5162#define FDIA_PHASE_SYNC_SHIFT_OVR 19
5163#define FDIA_PHASE_SYNC_SHIFT_EN 18
5164#define INVERT_DDIE_HPD REG_BIT(28)
5165#define INVERT_DDID_HPD_MTP REG_BIT(27)
5166#define INVERT_TC4_HPD REG_BIT(26)
5167#define INVERT_TC3_HPD REG_BIT(25)
5168#define INVERT_TC2_HPD REG_BIT(24)
5169#define INVERT_TC1_HPD REG_BIT(23)
5170#define INVERT_DDID_HPD (1 << 18)
5171#define INVERT_DDIC_HPD (1 << 17)
5172#define INVERT_DDIB_HPD (1 << 16)
5173#define INVERT_DDIA_HPD (1 << 15)
5174#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
5175#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
5176#define FDI_BC_BIFURCATION_SELECT (1 << 12)
5177#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
5178#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
5179#define SBCLK_RUN_REFCLK_DIS (1 << 7)
5180#define ICP_SECOND_PPS_IO_SELECT REG_BIT(2)
5181#define SPT_PWM_GRANULARITY (1 << 0)
5182#define SOUTH_CHICKEN2 _MMIO(0xc2004)
5183#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
5184#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
5185#define LPT_PWM_GRANULARITY (1 << 5)
5186#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
5187
5188#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
5189#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
5190#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
5191#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
5192#define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
5193#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
5194#define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
5195#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
5196
5197#define _PCH_DP_B 0xe4100
5198#define PCH_DP_B _MMIO(_PCH_DP_B)
5199#define _PCH_DPB_AUX_CH_CTL 0xe4110
5200#define _PCH_DPB_AUX_CH_DATA1 0xe4114
5201#define _PCH_DPB_AUX_CH_DATA2 0xe4118
5202#define _PCH_DPB_AUX_CH_DATA3 0xe411c
5203#define _PCH_DPB_AUX_CH_DATA4 0xe4120
5204#define _PCH_DPB_AUX_CH_DATA5 0xe4124
5205
5206#define _PCH_DP_C 0xe4200
5207#define PCH_DP_C _MMIO(_PCH_DP_C)
5208#define _PCH_DPC_AUX_CH_CTL 0xe4210
5209#define _PCH_DPC_AUX_CH_DATA1 0xe4214
5210#define _PCH_DPC_AUX_CH_DATA2 0xe4218
5211#define _PCH_DPC_AUX_CH_DATA3 0xe421c
5212#define _PCH_DPC_AUX_CH_DATA4 0xe4220
5213#define _PCH_DPC_AUX_CH_DATA5 0xe4224
5214
5215#define _PCH_DP_D 0xe4300
5216#define PCH_DP_D _MMIO(_PCH_DP_D)
5217#define _PCH_DPD_AUX_CH_CTL 0xe4310
5218#define _PCH_DPD_AUX_CH_DATA1 0xe4314
5219#define _PCH_DPD_AUX_CH_DATA2 0xe4318
5220#define _PCH_DPD_AUX_CH_DATA3 0xe431c
5221#define _PCH_DPD_AUX_CH_DATA4 0xe4320
5222#define _PCH_DPD_AUX_CH_DATA5 0xe4324
5223
5224#define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
5225#define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
5226
5227/* CPT */
5228#define _TRANS_DP_CTL_A 0xe0300
5229#define _TRANS_DP_CTL_B 0xe1300
5230#define _TRANS_DP_CTL_C 0xe2300
5231#define TRANS_DP_CTL(pipe) _MMIO_PIPE(pipe, _TRANS_DP_CTL_A, _TRANS_DP_CTL_B)
5232#define TRANS_DP_OUTPUT_ENABLE REG_BIT(31)
5233#define TRANS_DP_PORT_SEL_MASK REG_GENMASK(30, 29)
5234#define TRANS_DP_PORT_SEL_NONE REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, 3)
5235#define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
5236#define TRANS_DP_AUDIO_ONLY REG_BIT(26)
5237#define TRANS_DP_ENH_FRAMING REG_BIT(18)
5238#define TRANS_DP_BPC_MASK REG_GENMASK(10, 9)
5239#define TRANS_DP_BPC_8 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
5240#define TRANS_DP_BPC_10 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 1)
5241#define TRANS_DP_BPC_6 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 2)
5242#define TRANS_DP_BPC_12 REG_FIELD_PREP(TRANS_DP_BPC_MASK, 3)
5243#define TRANS_DP_VSYNC_ACTIVE_HIGH REG_BIT(4)
5244#define TRANS_DP_HSYNC_ACTIVE_HIGH REG_BIT(3)
5245
5246#define _TRANS_DP2_CTL_A 0x600a0
5247#define _TRANS_DP2_CTL_B 0x610a0
5248#define _TRANS_DP2_CTL_C 0x620a0
5249#define _TRANS_DP2_CTL_D 0x630a0
5250#define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
5251#define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31)
5252#define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30)
5253#define TRANS_DP2_DEBUG_ENABLE REG_BIT(23)
5254
5255#define _TRANS_DP2_VFREQHIGH_A 0x600a4
5256#define _TRANS_DP2_VFREQHIGH_B 0x610a4
5257#define _TRANS_DP2_VFREQHIGH_C 0x620a4
5258#define _TRANS_DP2_VFREQHIGH_D 0x630a4
5259#define TRANS_DP2_VFREQHIGH(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQHIGH_A, _TRANS_DP2_VFREQHIGH_B)
5260#define TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK REG_GENMASK(31, 8)
5261#define TRANS_DP2_VFREQ_PIXEL_CLOCK(clk_hz) REG_FIELD_PREP(TRANS_DP2_VFREQ_PIXEL_CLOCK_MASK, (clk_hz))
5262
5263#define _TRANS_DP2_VFREQLOW_A 0x600a8
5264#define _TRANS_DP2_VFREQLOW_B 0x610a8
5265#define _TRANS_DP2_VFREQLOW_C 0x620a8
5266#define _TRANS_DP2_VFREQLOW_D 0x630a8
5267#define TRANS_DP2_VFREQLOW(trans) _MMIO_TRANS(trans, _TRANS_DP2_VFREQLOW_A, _TRANS_DP2_VFREQLOW_B)
5268
5269/* SNB eDP training params */
5270/* SNB A-stepping */
5271#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22)
5272#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22)
5273#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01 << 22)
5274#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0 << 22)
5275/* SNB B-stepping */
5276#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0 << 22)
5277#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1 << 22)
5278#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a << 22)
5279#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39 << 22)
5280#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38 << 22)
5281#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f << 22)
5282
5283/* IVB */
5284#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 << 22)
5285#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a << 22)
5286#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f << 22)
5287#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 << 22)
5288#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 << 22)
5289#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 << 22)
5290#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e << 22)
5291
5292/* legacy values */
5293#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 << 22)
5294#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 << 22)
5295#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 << 22)
5296#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 << 22)
5297#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 << 22)
5298
5299#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f << 22)
5300
5301#define VLV_PMWGICZ _MMIO(0x1300a4)
5302
5303#define HSW_EDRAM_CAP _MMIO(0x120010)
5304#define EDRAM_ENABLED 0x1
5305#define EDRAM_NUM_BANKS(cap) (((cap) >> 1) & 0xf)
5306#define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
5307#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
5308
5309#define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
5310#define PIXEL_OVERLAP_CNT_MASK (3 << 30)
5311#define PIXEL_OVERLAP_CNT_SHIFT 30
5312
5313#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
5314#define GEN6_PCODE_READY (1 << 31)
5315#define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
5316#define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
5317#define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
5318#define GEN6_PCODE_ERROR_MASK 0xFF
5319#define GEN6_PCODE_SUCCESS 0x0
5320#define GEN6_PCODE_ILLEGAL_CMD 0x1
5321#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
5322#define GEN6_PCODE_TIMEOUT 0x3
5323#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
5324#define GEN7_PCODE_TIMEOUT 0x2
5325#define GEN7_PCODE_ILLEGAL_DATA 0x3
5326#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
5327#define GEN11_PCODE_LOCKED 0x6
5328#define GEN11_PCODE_REJECTED 0x11
5329#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
5330#define GEN6_PCODE_WRITE_RC6VIDS 0x4
5331#define GEN6_PCODE_READ_RC6VIDS 0x5
5332#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
5333#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
5334#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
5335#define GEN9_PCODE_READ_MEM_LATENCY 0x6
5336#define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24)
5337#define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16)
5338#define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8)
5339#define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
5340#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
5341#define SKL_PCODE_CDCLK_CONTROL 0x7
5342#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
5343#define SKL_CDCLK_READY_FOR_CHANGE 0x1
5344#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
5345#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
5346#define GEN6_READ_OC_PARAMS 0xc
5347#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
5348#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
5349#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
5350#define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
5351#define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D
5352#define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0)
5353#define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK
5354#define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27)
5355#define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31)
5356#define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16)
5357#define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28)
5358#define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
5359#define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
5360#define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
5361#define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
5362 ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
5363 (DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
5364 (DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
5365#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
5366#define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
5367#define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
5368#define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
5369#define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
5370#define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
5371#define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
5372#define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
5373#define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
5374#define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
5375#define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
5376#define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
5377#define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
5378#define GEN6_PCODE_READ_D_COMP 0x10
5379#define GEN6_PCODE_WRITE_D_COMP 0x11
5380#define ICL_PCODE_EXIT_TCCOLD 0x12
5381#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
5382#define DISPLAY_IPS_CONTROL 0x19
5383#define TGL_PCODE_TCCOLD 0x26
5384#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
5385#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
5386#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
5387 /* See also IPS_CTL */
5388#define IPS_PCODE_CONTROL (1 << 30)
5389#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
5390#define GEN9_PCODE_SAGV_CONTROL 0x21
5391#define GEN9_SAGV_DISABLE 0x0
5392#define GEN9_SAGV_IS_DISABLED 0x1
5393#define GEN9_SAGV_ENABLE 0x3
5394#define DG1_PCODE_STATUS 0x7E
5395#define DG1_UNCORE_GET_INIT_STATUS 0x0
5396#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
5397#define PCODE_POWER_SETUP 0x7C
5398#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
5399#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
5400#define POWER_SETUP_I1_WATTS REG_BIT(31)
5401#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
5402#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
5403#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
5404#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */
5405/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
5406#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
5407#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
5408/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
5409/* XEHP_PCODE_FREQUENCY_CONFIG param2 */
5410#define PCODE_MBOX_DOMAIN_NONE 0x0
5411#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
5412#define GEN6_PCODE_DATA _MMIO(0x138128)
5413#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
5414#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
5415#define GEN6_PCODE_DATA1 _MMIO(0x13812C)
5416
5417#define MTL_PCODE_STOLEN_ACCESS _MMIO(0x138914)
5418#define STOLEN_ACCESS_ALLOWED 0x1
5419
5420/* IVYBRIDGE DPF */
5421#define GEN7_L3CDERRST1(slice) _MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
5422#define GEN7_L3CDERRST1_ROW_MASK (0x7ff << 14)
5423#define GEN7_PARITY_ERROR_VALID (1 << 13)
5424#define GEN7_L3CDERRST1_BANK_MASK (3 << 11)
5425#define GEN7_L3CDERRST1_SUBBANK_MASK (7 << 8)
5426#define GEN7_PARITY_ERROR_ROW(reg) \
5427 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
5428#define GEN7_PARITY_ERROR_BANK(reg) \
5429 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
5430#define GEN7_PARITY_ERROR_SUBBANK(reg) \
5431 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
5432#define GEN7_L3CDERRST1_ENABLE (1 << 7)
5433
5434/* These are the 4 32-bit write offset registers for each stream
5435 * output buffer. It determines the offset from the
5436 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
5437 */
5438#define GEN7_SO_WRITE_OFFSET(n) _MMIO(0x5280 + (n) * 4)
5439
5440/*
5441 * HSW - ICL power wells
5442 *
5443 * Platforms have up to 3 power well control register sets, each set
5444 * controlling up to 16 power wells via a request/status HW flag tuple:
5445 * - main (HSW_PWR_WELL_CTL[1-4])
5446 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
5447 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
5448 * Each control register set consists of up to 4 registers used by different
5449 * sources that can request a power well to be enabled:
5450 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
5451 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
5452 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
5453 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
5454 */
5455#define HSW_PWR_WELL_CTL1 _MMIO(0x45400)
5456#define HSW_PWR_WELL_CTL2 _MMIO(0x45404)
5457#define HSW_PWR_WELL_CTL3 _MMIO(0x45408)
5458#define HSW_PWR_WELL_CTL4 _MMIO(0x4540C)
5459#define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2))
5460#define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2))
5461
5462/* HSW/BDW power well */
5463#define HSW_PW_CTL_IDX_GLOBAL 15
5464
5465/* SKL/BXT/GLK power wells */
5466#define SKL_PW_CTL_IDX_PW_2 15
5467#define SKL_PW_CTL_IDX_PW_1 14
5468#define GLK_PW_CTL_IDX_AUX_C 10
5469#define GLK_PW_CTL_IDX_AUX_B 9
5470#define GLK_PW_CTL_IDX_AUX_A 8
5471#define SKL_PW_CTL_IDX_DDI_D 4
5472#define SKL_PW_CTL_IDX_DDI_C 3
5473#define SKL_PW_CTL_IDX_DDI_B 2
5474#define SKL_PW_CTL_IDX_DDI_A_E 1
5475#define GLK_PW_CTL_IDX_DDI_A 1
5476#define SKL_PW_CTL_IDX_MISC_IO 0
5477
5478/* ICL/TGL - power wells */
5479#define TGL_PW_CTL_IDX_PW_5 4
5480#define ICL_PW_CTL_IDX_PW_4 3
5481#define ICL_PW_CTL_IDX_PW_3 2
5482#define ICL_PW_CTL_IDX_PW_2 1
5483#define ICL_PW_CTL_IDX_PW_1 0
5484
5485/* XE_LPD - power wells */
5486#define XELPD_PW_CTL_IDX_PW_D 8
5487#define XELPD_PW_CTL_IDX_PW_C 7
5488#define XELPD_PW_CTL_IDX_PW_B 6
5489#define XELPD_PW_CTL_IDX_PW_A 5
5490
5491#define ICL_PWR_WELL_CTL_AUX1 _MMIO(0x45440)
5492#define ICL_PWR_WELL_CTL_AUX2 _MMIO(0x45444)
5493#define ICL_PWR_WELL_CTL_AUX4 _MMIO(0x4544C)
5494#define TGL_PW_CTL_IDX_AUX_TBT6 14
5495#define TGL_PW_CTL_IDX_AUX_TBT5 13
5496#define TGL_PW_CTL_IDX_AUX_TBT4 12
5497#define ICL_PW_CTL_IDX_AUX_TBT4 11
5498#define TGL_PW_CTL_IDX_AUX_TBT3 11
5499#define ICL_PW_CTL_IDX_AUX_TBT3 10
5500#define TGL_PW_CTL_IDX_AUX_TBT2 10
5501#define ICL_PW_CTL_IDX_AUX_TBT2 9
5502#define TGL_PW_CTL_IDX_AUX_TBT1 9
5503#define ICL_PW_CTL_IDX_AUX_TBT1 8
5504#define TGL_PW_CTL_IDX_AUX_TC6 8
5505#define XELPD_PW_CTL_IDX_AUX_E 8
5506#define TGL_PW_CTL_IDX_AUX_TC5 7
5507#define XELPD_PW_CTL_IDX_AUX_D 7
5508#define TGL_PW_CTL_IDX_AUX_TC4 6
5509#define ICL_PW_CTL_IDX_AUX_F 5
5510#define TGL_PW_CTL_IDX_AUX_TC3 5
5511#define ICL_PW_CTL_IDX_AUX_E 4
5512#define TGL_PW_CTL_IDX_AUX_TC2 4
5513#define ICL_PW_CTL_IDX_AUX_D 3
5514#define TGL_PW_CTL_IDX_AUX_TC1 3
5515#define ICL_PW_CTL_IDX_AUX_C 2
5516#define ICL_PW_CTL_IDX_AUX_B 1
5517#define ICL_PW_CTL_IDX_AUX_A 0
5518
5519#define ICL_PWR_WELL_CTL_DDI1 _MMIO(0x45450)
5520#define ICL_PWR_WELL_CTL_DDI2 _MMIO(0x45454)
5521#define ICL_PWR_WELL_CTL_DDI4 _MMIO(0x4545C)
5522#define XELPD_PW_CTL_IDX_DDI_E 8
5523#define TGL_PW_CTL_IDX_DDI_TC6 8
5524#define XELPD_PW_CTL_IDX_DDI_D 7
5525#define TGL_PW_CTL_IDX_DDI_TC5 7
5526#define TGL_PW_CTL_IDX_DDI_TC4 6
5527#define ICL_PW_CTL_IDX_DDI_F 5
5528#define TGL_PW_CTL_IDX_DDI_TC3 5
5529#define ICL_PW_CTL_IDX_DDI_E 4
5530#define TGL_PW_CTL_IDX_DDI_TC2 4
5531#define ICL_PW_CTL_IDX_DDI_D 3
5532#define TGL_PW_CTL_IDX_DDI_TC1 3
5533#define ICL_PW_CTL_IDX_DDI_C 2
5534#define ICL_PW_CTL_IDX_DDI_B 1
5535#define ICL_PW_CTL_IDX_DDI_A 0
5536
5537/* HSW - power well misc debug registers */
5538#define HSW_PWR_WELL_CTL5 _MMIO(0x45410)
5539#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1 << 31)
5540#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1 << 20)
5541#define HSW_PWR_WELL_FORCE_ON (1 << 19)
5542#define HSW_PWR_WELL_CTL6 _MMIO(0x45414)
5543
5544/* SKL Fuse Status */
5545enum skl_power_gate {
5546 SKL_PG0,
5547 SKL_PG1,
5548 SKL_PG2,
5549 ICL_PG3,
5550 ICL_PG4,
5551};
5552
5553#define SKL_FUSE_STATUS _MMIO(0x42000)
5554#define SKL_FUSE_DOWNLOAD_STATUS (1 << 31)
5555/*
5556 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
5557 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
5558 */
5559#define SKL_PW_CTL_IDX_TO_PG(pw_idx) \
5560 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
5561/*
5562 * PG0 is HW controlled, so doesn't have a corresponding power well control knob
5563 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
5564 */
5565#define ICL_PW_CTL_IDX_TO_PG(pw_idx) \
5566 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
5567#define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
5568
5569#define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
5570#define _ICL_AUX_ANAOVRD1_A 0x162398
5571#define _ICL_AUX_ANAOVRD1_B 0x6C398
5572#define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \
5573 _ICL_AUX_ANAOVRD1_A, \
5574 _ICL_AUX_ANAOVRD1_B))
5575#define ICL_AUX_ANAOVRD1_LDO_BYPASS (1 << 7)
5576#define ICL_AUX_ANAOVRD1_ENABLE (1 << 0)
5577
5578/* Per-pipe DDI Function Control */
5579#define _TRANS_DDI_FUNC_CTL_A 0x60400
5580#define _TRANS_DDI_FUNC_CTL_B 0x61400
5581#define _TRANS_DDI_FUNC_CTL_C 0x62400
5582#define _TRANS_DDI_FUNC_CTL_D 0x63400
5583#define _TRANS_DDI_FUNC_CTL_EDP 0x6F400
5584#define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400
5585#define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00
5586#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A)
5587
5588#define TRANS_DDI_FUNC_ENABLE (1 << 31)
5589/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
5590#define TRANS_DDI_PORT_SHIFT 28
5591#define TGL_TRANS_DDI_PORT_SHIFT 27
5592#define TRANS_DDI_PORT_MASK (7 << TRANS_DDI_PORT_SHIFT)
5593#define TGL_TRANS_DDI_PORT_MASK (0xf << TGL_TRANS_DDI_PORT_SHIFT)
5594#define TRANS_DDI_SELECT_PORT(x) ((x) << TRANS_DDI_PORT_SHIFT)
5595#define TGL_TRANS_DDI_SELECT_PORT(x) (((x) + 1) << TGL_TRANS_DDI_PORT_SHIFT)
5596#define TRANS_DDI_MODE_SELECT_MASK (7 << 24)
5597#define TRANS_DDI_MODE_SELECT_HDMI (0 << 24)
5598#define TRANS_DDI_MODE_SELECT_DVI (1 << 24)
5599#define TRANS_DDI_MODE_SELECT_DP_SST (2 << 24)
5600#define TRANS_DDI_MODE_SELECT_DP_MST (3 << 24)
5601#define TRANS_DDI_MODE_SELECT_FDI_OR_128B132B (4 << 24)
5602#define TRANS_DDI_BPC_MASK (7 << 20)
5603#define TRANS_DDI_BPC_8 (0 << 20)
5604#define TRANS_DDI_BPC_10 (1 << 20)
5605#define TRANS_DDI_BPC_6 (2 << 20)
5606#define TRANS_DDI_BPC_12 (3 << 20)
5607#define TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK REG_GENMASK(19, 18)
5608#define TRANS_DDI_PORT_SYNC_MASTER_SELECT(x) REG_FIELD_PREP(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, (x))
5609#define TRANS_DDI_PVSYNC (1 << 17)
5610#define TRANS_DDI_PHSYNC (1 << 16)
5611#define TRANS_DDI_PORT_SYNC_ENABLE REG_BIT(15)
5612#define TRANS_DDI_EDP_INPUT_MASK (7 << 12)
5613#define TRANS_DDI_EDP_INPUT_A_ON (0 << 12)
5614#define TRANS_DDI_EDP_INPUT_A_ONOFF (4 << 12)
5615#define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12)
5616#define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12)
5617#define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12)
5618#define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10)
5619#define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
5620 REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
5621#define TRANS_DDI_HDCP_SIGNALLING (1 << 9)
5622#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
5623#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
5624#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
5625#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
5626#define TRANS_DDI_BFI_ENABLE (1 << 4)
5627#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
5628#define TRANS_DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1)
5629#define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1)
5630#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
5631#define TRANS_DDI_HDMI_SCRAMBLING_MASK (TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE \
5632 | TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ \
5633 | TRANS_DDI_HDMI_SCRAMBLING)
5634
5635#define _TRANS_DDI_FUNC_CTL2_A 0x60404
5636#define _TRANS_DDI_FUNC_CTL2_B 0x61404
5637#define _TRANS_DDI_FUNC_CTL2_C 0x62404
5638#define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404
5639#define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404
5640#define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04
5641#define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A)
5642#define PORT_SYNC_MODE_ENABLE REG_BIT(4)
5643#define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0)
5644#define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x))
5645
5646#define TRANS_CMTG_CHICKEN _MMIO(0x6fa90)
5647#define DISABLE_DPT_CLK_GATING REG_BIT(1)
5648
5649/* DisplayPort Transport Control */
5650#define _DP_TP_CTL_A 0x64040
5651#define _DP_TP_CTL_B 0x64140
5652#define _TGL_DP_TP_CTL_A 0x60540
5653#define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
5654#define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
5655#define DP_TP_CTL_ENABLE (1 << 31)
5656#define DP_TP_CTL_FEC_ENABLE (1 << 30)
5657#define DP_TP_CTL_MODE_SST (0 << 27)
5658#define DP_TP_CTL_MODE_MST (1 << 27)
5659#define DP_TP_CTL_FORCE_ACT (1 << 25)
5660#define DP_TP_CTL_TRAIN_PAT4_SEL_MASK (3 << 19)
5661#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4A (0 << 19)
5662#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4B (1 << 19)
5663#define DP_TP_CTL_TRAIN_PAT4_SEL_TP4C (2 << 19)
5664#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1 << 18)
5665#define DP_TP_CTL_FDI_AUTOTRAIN (1 << 15)
5666#define DP_TP_CTL_LINK_TRAIN_MASK (7 << 8)
5667#define DP_TP_CTL_LINK_TRAIN_PAT1 (0 << 8)
5668#define DP_TP_CTL_LINK_TRAIN_PAT2 (1 << 8)
5669#define DP_TP_CTL_LINK_TRAIN_PAT3 (4 << 8)
5670#define DP_TP_CTL_LINK_TRAIN_PAT4 (5 << 8)
5671#define DP_TP_CTL_LINK_TRAIN_IDLE (2 << 8)
5672#define DP_TP_CTL_LINK_TRAIN_NORMAL (3 << 8)
5673#define DP_TP_CTL_SCRAMBLE_DISABLE (1 << 7)
5674
5675/* DisplayPort Transport Status */
5676#define _DP_TP_STATUS_A 0x64044
5677#define _DP_TP_STATUS_B 0x64144
5678#define _TGL_DP_TP_STATUS_A 0x60544
5679#define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
5680#define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
5681#define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28)
5682#define DP_TP_STATUS_IDLE_DONE (1 << 25)
5683#define DP_TP_STATUS_ACT_SENT (1 << 24)
5684#define DP_TP_STATUS_MODE_STATUS_MST (1 << 23)
5685#define DP_TP_STATUS_AUTOTRAIN_DONE (1 << 12)
5686#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
5687#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
5688#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
5689
5690/* DDI Buffer Control */
5691#define _DDI_BUF_CTL_A 0x64000
5692#define _DDI_BUF_CTL_B 0x64100
5693/* Known as DDI_CTL_DE in MTL+ */
5694#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
5695#define DDI_BUF_CTL_ENABLE (1 << 31)
5696#define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29)
5697#define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28)
5698#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
5699#define DDI_BUF_EMP_MASK (0xf << 24)
5700#define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20)
5701#define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18)
5702#define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0)
5703#define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1)
5704#define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2)
5705#define DDI_BUF_PORT_REVERSAL (1 << 16)
5706#define DDI_BUF_IS_IDLE (1 << 7)
5707#define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6)
5708#define DDI_A_4_LANES (1 << 4)
5709#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
5710#define DDI_PORT_WIDTH_MASK (7 << 1)
5711#define DDI_PORT_WIDTH_SHIFT 1
5712#define DDI_INIT_DISPLAY_DETECTED (1 << 0)
5713
5714/* DDI Buffer Translations */
5715#define _DDI_BUF_TRANS_A 0x64E00
5716#define _DDI_BUF_TRANS_B 0x64E60
5717#define DDI_BUF_TRANS_LO(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8)
5718#define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31)
5719#define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4)
5720
5721/* DDI DP Compliance Control */
5722#define _DDI_DP_COMP_CTL_A 0x605F0
5723#define _DDI_DP_COMP_CTL_B 0x615F0
5724#define DDI_DP_COMP_CTL(pipe) _MMIO_PIPE(pipe, _DDI_DP_COMP_CTL_A, _DDI_DP_COMP_CTL_B)
5725#define DDI_DP_COMP_CTL_ENABLE (1 << 31)
5726#define DDI_DP_COMP_CTL_D10_2 (0 << 28)
5727#define DDI_DP_COMP_CTL_SCRAMBLED_0 (1 << 28)
5728#define DDI_DP_COMP_CTL_PRBS7 (2 << 28)
5729#define DDI_DP_COMP_CTL_CUSTOM80 (3 << 28)
5730#define DDI_DP_COMP_CTL_HBR2 (4 << 28)
5731#define DDI_DP_COMP_CTL_SCRAMBLED_1 (5 << 28)
5732#define DDI_DP_COMP_CTL_HBR2_RESET (0xFC << 0)
5733
5734/* DDI DP Compliance Pattern */
5735#define _DDI_DP_COMP_PAT_A 0x605F4
5736#define _DDI_DP_COMP_PAT_B 0x615F4
5737#define DDI_DP_COMP_PAT(pipe, i) _MMIO(_PIPE(pipe, _DDI_DP_COMP_PAT_A, _DDI_DP_COMP_PAT_B) + (i) * 4)
5738
5739/* Sideband Interface (SBI) is programmed indirectly, via
5740 * SBI_ADDR, which contains the register offset; and SBI_DATA,
5741 * which contains the payload */
5742#define SBI_ADDR _MMIO(0xC6000)
5743#define SBI_DATA _MMIO(0xC6004)
5744#define SBI_CTL_STAT _MMIO(0xC6008)
5745#define SBI_CTL_DEST_ICLK (0x0 << 16)
5746#define SBI_CTL_DEST_MPHY (0x1 << 16)
5747#define SBI_CTL_OP_IORD (0x2 << 8)
5748#define SBI_CTL_OP_IOWR (0x3 << 8)
5749#define SBI_CTL_OP_CRRD (0x6 << 8)
5750#define SBI_CTL_OP_CRWR (0x7 << 8)
5751#define SBI_RESPONSE_FAIL (0x1 << 1)
5752#define SBI_RESPONSE_SUCCESS (0x0 << 1)
5753#define SBI_BUSY (0x1 << 0)
5754#define SBI_READY (0x0 << 0)
5755
5756/* SBI offsets */
5757#define SBI_SSCDIVINTPHASE 0x0200
5758#define SBI_SSCDIVINTPHASE6 0x0600
5759#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1
5760#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f << 1)
5761#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x) << 1)
5762#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8
5763#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f << 8)
5764#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x) << 8)
5765#define SBI_SSCDIVINTPHASE_DIR(x) ((x) << 15)
5766#define SBI_SSCDIVINTPHASE_PROPAGATE (1 << 0)
5767#define SBI_SSCDITHPHASE 0x0204
5768#define SBI_SSCCTL 0x020c
5769#define SBI_SSCCTL6 0x060C
5770#define SBI_SSCCTL_PATHALT (1 << 3)
5771#define SBI_SSCCTL_DISABLE (1 << 0)
5772#define SBI_SSCAUXDIV6 0x0610
5773#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4
5774#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1 << 4)
5775#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x) << 4)
5776#define SBI_DBUFF0 0x2a00
5777#define SBI_GEN0 0x1f00
5778#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1 << 0)
5779
5780/* LPT PIXCLK_GATE */
5781#define PIXCLK_GATE _MMIO(0xC6020)
5782#define PIXCLK_GATE_UNGATE (1 << 0)
5783#define PIXCLK_GATE_GATE (0 << 0)
5784
5785/* SPLL */
5786#define SPLL_CTL _MMIO(0x46020)
5787#define SPLL_PLL_ENABLE (1 << 31)
5788#define SPLL_REF_BCLK (0 << 28)
5789#define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
5790#define SPLL_REF_NON_SSC_HSW (2 << 28)
5791#define SPLL_REF_PCH_SSC_BDW (2 << 28)
5792#define SPLL_REF_LCPLL (3 << 28)
5793#define SPLL_REF_MASK (3 << 28)
5794#define SPLL_FREQ_810MHz (0 << 26)
5795#define SPLL_FREQ_1350MHz (1 << 26)
5796#define SPLL_FREQ_2700MHz (2 << 26)
5797#define SPLL_FREQ_MASK (3 << 26)
5798
5799/* WRPLL */
5800#define _WRPLL_CTL1 0x46040
5801#define _WRPLL_CTL2 0x46060
5802#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
5803#define WRPLL_PLL_ENABLE (1 << 31)
5804#define WRPLL_REF_BCLK (0 << 28)
5805#define WRPLL_REF_PCH_SSC (1 << 28)
5806#define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
5807#define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
5808#define WRPLL_REF_LCPLL (3 << 28)
5809#define WRPLL_REF_MASK (3 << 28)
5810/* WRPLL divider programming */
5811#define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
5812#define WRPLL_DIVIDER_REF_MASK (0xff)
5813#define WRPLL_DIVIDER_POST(x) ((x) << 8)
5814#define WRPLL_DIVIDER_POST_MASK (0x3f << 8)
5815#define WRPLL_DIVIDER_POST_SHIFT 8
5816#define WRPLL_DIVIDER_FEEDBACK(x) ((x) << 16)
5817#define WRPLL_DIVIDER_FB_SHIFT 16
5818#define WRPLL_DIVIDER_FB_MASK (0xff << 16)
5819
5820/* Port clock selection */
5821#define _PORT_CLK_SEL_A 0x46100
5822#define _PORT_CLK_SEL_B 0x46104
5823#define PORT_CLK_SEL(port) _MMIO_PORT(port, _PORT_CLK_SEL_A, _PORT_CLK_SEL_B)
5824#define PORT_CLK_SEL_MASK REG_GENMASK(31, 29)
5825#define PORT_CLK_SEL_LCPLL_2700 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0)
5826#define PORT_CLK_SEL_LCPLL_1350 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 1)
5827#define PORT_CLK_SEL_LCPLL_810 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 2)
5828#define PORT_CLK_SEL_SPLL REG_FIELD_PREP(PORT_CLK_SEL_MASK, 3)
5829#define PORT_CLK_SEL_WRPLL(pll) REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4 + (pll))
5830#define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4)
5831#define PORT_CLK_SEL_WRPLL2 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 5)
5832#define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7)
5833
5834/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
5835#define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
5836#define DDI_CLK_SEL_MASK REG_GENMASK(31, 28)
5837#define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)
5838#define DDI_CLK_SEL_MG REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
5839#define DDI_CLK_SEL_TBT_162 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC)
5840#define DDI_CLK_SEL_TBT_270 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD)
5841#define DDI_CLK_SEL_TBT_540 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE)
5842#define DDI_CLK_SEL_TBT_810 REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF)
5843
5844/* Transcoder clock selection */
5845#define _TRANS_CLK_SEL_A 0x46140
5846#define _TRANS_CLK_SEL_B 0x46144
5847#define TRANS_CLK_SEL(tran) _MMIO_TRANS(tran, _TRANS_CLK_SEL_A, _TRANS_CLK_SEL_B)
5848/* For each transcoder, we need to select the corresponding port clock */
5849#define TRANS_CLK_SEL_DISABLED (0x0 << 29)
5850#define TRANS_CLK_SEL_PORT(x) (((x) + 1) << 29)
5851#define TGL_TRANS_CLK_SEL_DISABLED (0x0 << 28)
5852#define TGL_TRANS_CLK_SEL_PORT(x) (((x) + 1) << 28)
5853
5854
5855#define CDCLK_FREQ _MMIO(0x46200)
5856
5857#define _TRANSA_MSA_MISC 0x60410
5858#define _TRANSB_MSA_MISC 0x61410
5859#define _TRANSC_MSA_MISC 0x62410
5860#define _TRANS_EDP_MSA_MISC 0x6f410
5861#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC)
5862/* See DP_MSA_MISC_* for the bit definitions */
5863
5864#define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C
5865#define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C
5866#define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C
5867#define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C
5868#define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY)
5869#define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0)
5870#define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x))
5871
5872/* LCPLL Control */
5873#define LCPLL_CTL _MMIO(0x130040)
5874#define LCPLL_PLL_DISABLE (1 << 31)
5875#define LCPLL_PLL_LOCK (1 << 30)
5876#define LCPLL_REF_NON_SSC (0 << 28)
5877#define LCPLL_REF_BCLK (2 << 28)
5878#define LCPLL_REF_PCH_SSC (3 << 28)
5879#define LCPLL_REF_MASK (3 << 28)
5880#define LCPLL_CLK_FREQ_MASK (3 << 26)
5881#define LCPLL_CLK_FREQ_450 (0 << 26)
5882#define LCPLL_CLK_FREQ_54O_BDW (1 << 26)
5883#define LCPLL_CLK_FREQ_337_5_BDW (2 << 26)
5884#define LCPLL_CLK_FREQ_675_BDW (3 << 26)
5885#define LCPLL_CD_CLOCK_DISABLE (1 << 25)
5886#define LCPLL_ROOT_CD_CLOCK_DISABLE (1 << 24)
5887#define LCPLL_CD2X_CLOCK_DISABLE (1 << 23)
5888#define LCPLL_POWER_DOWN_ALLOW (1 << 22)
5889#define LCPLL_CD_SOURCE_FCLK (1 << 21)
5890#define LCPLL_CD_SOURCE_FCLK_DONE (1 << 19)
5891
5892/*
5893 * SKL Clocks
5894 */
5895
5896/* CDCLK_CTL */
5897#define CDCLK_CTL _MMIO(0x46000)
5898#define CDCLK_FREQ_SEL_MASK REG_GENMASK(27, 26)
5899#define CDCLK_FREQ_450_432 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)
5900#define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
5901#define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
5902#define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
5903#define MDCLK_SOURCE_SEL_CDCLK_PLL REG_BIT(25)
5904#define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
5905#define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
5906#define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
5907#define BXT_CDCLK_CD2X_DIV_SEL_2 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2)
5908#define BXT_CDCLK_CD2X_DIV_SEL_4 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3)
5909#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe) << 20)
5910#define CDCLK_DIVMUX_CD_OVERRIDE (1 << 19)
5911#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
5912#define ICL_CDCLK_CD2X_PIPE(pipe) (_PICK(pipe, 0, 2, 6) << 19)
5913#define ICL_CDCLK_CD2X_PIPE_NONE (7 << 19)
5914#define TGL_CDCLK_CD2X_PIPE(pipe) BXT_CDCLK_CD2X_PIPE(pipe)
5915#define TGL_CDCLK_CD2X_PIPE_NONE ICL_CDCLK_CD2X_PIPE_NONE
5916#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1 << 16)
5917#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
5918
5919/* CDCLK_SQUASH_CTL */
5920#define CDCLK_SQUASH_CTL _MMIO(0x46008)
5921#define CDCLK_SQUASH_ENABLE REG_BIT(31)
5922#define CDCLK_SQUASH_WINDOW_SIZE_MASK REG_GENMASK(27, 24)
5923#define CDCLK_SQUASH_WINDOW_SIZE(x) REG_FIELD_PREP(CDCLK_SQUASH_WINDOW_SIZE_MASK, (x))
5924#define CDCLK_SQUASH_WAVEFORM_MASK REG_GENMASK(15, 0)
5925#define CDCLK_SQUASH_WAVEFORM(x) REG_FIELD_PREP(CDCLK_SQUASH_WAVEFORM_MASK, (x))
5926
5927/* LCPLL_CTL */
5928#define LCPLL1_CTL _MMIO(0x46010)
5929#define LCPLL2_CTL _MMIO(0x46014)
5930#define LCPLL_PLL_ENABLE (1 << 31)
5931
5932/* DPLL control1 */
5933#define DPLL_CTRL1 _MMIO(0x6C058)
5934#define DPLL_CTRL1_HDMI_MODE(id) (1 << ((id) * 6 + 5))
5935#define DPLL_CTRL1_SSC(id) (1 << ((id) * 6 + 4))
5936#define DPLL_CTRL1_LINK_RATE_MASK(id) (7 << ((id) * 6 + 1))
5937#define DPLL_CTRL1_LINK_RATE_SHIFT(id) ((id) * 6 + 1)
5938#define DPLL_CTRL1_LINK_RATE(linkrate, id) ((linkrate) << ((id) * 6 + 1))
5939#define DPLL_CTRL1_OVERRIDE(id) (1 << ((id) * 6))
5940#define DPLL_CTRL1_LINK_RATE_2700 0
5941#define DPLL_CTRL1_LINK_RATE_1350 1
5942#define DPLL_CTRL1_LINK_RATE_810 2
5943#define DPLL_CTRL1_LINK_RATE_1620 3
5944#define DPLL_CTRL1_LINK_RATE_1080 4
5945#define DPLL_CTRL1_LINK_RATE_2160 5
5946
5947/* DPLL control2 */
5948#define DPLL_CTRL2 _MMIO(0x6C05C)
5949#define DPLL_CTRL2_DDI_CLK_OFF(port) (1 << ((port) + 15))
5950#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3 << ((port) * 3 + 1))
5951#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port) * 3 + 1)
5952#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) ((clk) << ((port) * 3 + 1))
5953#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1 << ((port) * 3))
5954
5955/* DPLL Status */
5956#define DPLL_STATUS _MMIO(0x6C060)
5957#define DPLL_LOCK(id) (1 << ((id) * 8))
5958
5959/* DPLL cfg */
5960#define _DPLL1_CFGCR1 0x6C040
5961#define _DPLL2_CFGCR1 0x6C048
5962#define _DPLL3_CFGCR1 0x6C050
5963#define DPLL_CFGCR1_FREQ_ENABLE (1 << 31)
5964#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff << 9)
5965#define DPLL_CFGCR1_DCO_FRACTION(x) ((x) << 9)
5966#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
5967
5968#define _DPLL1_CFGCR2 0x6C044
5969#define _DPLL2_CFGCR2 0x6C04C
5970#define _DPLL3_CFGCR2 0x6C054
5971#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff << 8)
5972#define DPLL_CFGCR2_QDIV_RATIO(x) ((x) << 8)
5973#define DPLL_CFGCR2_QDIV_MODE(x) ((x) << 7)
5974#define DPLL_CFGCR2_KDIV_MASK (3 << 5)
5975#define DPLL_CFGCR2_KDIV(x) ((x) << 5)
5976#define DPLL_CFGCR2_KDIV_5 (0 << 5)
5977#define DPLL_CFGCR2_KDIV_2 (1 << 5)
5978#define DPLL_CFGCR2_KDIV_3 (2 << 5)
5979#define DPLL_CFGCR2_KDIV_1 (3 << 5)
5980#define DPLL_CFGCR2_PDIV_MASK (7 << 2)
5981#define DPLL_CFGCR2_PDIV(x) ((x) << 2)
5982#define DPLL_CFGCR2_PDIV_1 (0 << 2)
5983#define DPLL_CFGCR2_PDIV_2 (1 << 2)
5984#define DPLL_CFGCR2_PDIV_3 (2 << 2)
5985#define DPLL_CFGCR2_PDIV_7 (4 << 2)
5986#define DPLL_CFGCR2_PDIV_7_INVALID (5 << 2)
5987#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
5988
5989#define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
5990#define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
5991
5992/* ICL Clocks */
5993#define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
5994#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24, 4, 5))
5995#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
5996#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < TC_PORT_4 ? \
5997 (tc_port) + 12 : \
5998 (tc_port) - TC_PORT_4 + 21))
5999#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
6000#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
6001#define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
6002#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
6003#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
6004 (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
6005#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
6006 ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
6007
6008/*
6009 * DG1 Clocks
6010 * First registers controls the first A and B, while the second register
6011 * controls the phy C and D. The bits on these registers are the
6012 * same, but refer to different phys
6013 */
6014#define _DG1_DPCLKA_CFGCR0 0x164280
6015#define _DG1_DPCLKA1_CFGCR0 0x16C280
6016#define _DG1_DPCLKA_PHY_IDX(phy) ((phy) % 2)
6017#define _DG1_DPCLKA_PLL_IDX(pll) ((pll) % 2)
6018#define DG1_DPCLKA_CFGCR0(phy) _MMIO_PHY((phy) / 2, \
6019 _DG1_DPCLKA_CFGCR0, \
6020 _DG1_DPCLKA1_CFGCR0)
6021#define DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT(_DG1_DPCLKA_PHY_IDX(phy) + 10)
6022#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) (_DG1_DPCLKA_PHY_IDX(phy) * 2)
6023#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) (_DG1_DPCLKA_PLL_IDX(pll) << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
6024#define DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
6025
6026/* ADLS Clocks */
6027#define _ADLS_DPCLKA_CFGCR0 0x164280
6028#define _ADLS_DPCLKA_CFGCR1 0x1642BC
6029#define ADLS_DPCLKA_CFGCR(phy) _MMIO_PHY((phy) / 3, \
6030 _ADLS_DPCLKA_CFGCR0, \
6031 _ADLS_DPCLKA_CFGCR1)
6032#define ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy) (((phy) % 3) * 2)
6033/* ADLS DPCLKA_CFGCR0 DDI mask */
6034#define ADLS_DPCLKA_DDII_SEL_MASK REG_GENMASK(5, 4)
6035#define ADLS_DPCLKA_DDIB_SEL_MASK REG_GENMASK(3, 2)
6036#define ADLS_DPCLKA_DDIA_SEL_MASK REG_GENMASK(1, 0)
6037/* ADLS DPCLKA_CFGCR1 DDI mask */
6038#define ADLS_DPCLKA_DDIK_SEL_MASK REG_GENMASK(3, 2)
6039#define ADLS_DPCLKA_DDIJ_SEL_MASK REG_GENMASK(1, 0)
6040#define ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy) _PICK((phy), \
6041 ADLS_DPCLKA_DDIA_SEL_MASK, \
6042 ADLS_DPCLKA_DDIB_SEL_MASK, \
6043 ADLS_DPCLKA_DDII_SEL_MASK, \
6044 ADLS_DPCLKA_DDIJ_SEL_MASK, \
6045 ADLS_DPCLKA_DDIK_SEL_MASK)
6046
6047/* ICL PLL */
6048#define _DPLL0_ENABLE 0x46010
6049#define _DPLL1_ENABLE 0x46014
6050#define _ADLS_DPLL2_ENABLE 0x46018
6051#define _ADLS_DPLL3_ENABLE 0x46030
6052#define PLL_ENABLE REG_BIT(31)
6053#define PLL_LOCK REG_BIT(30)
6054#define PLL_POWER_ENABLE REG_BIT(27)
6055#define PLL_POWER_STATE REG_BIT(26)
6056#define ICL_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \
6057 _DPLL0_ENABLE, _DPLL1_ENABLE, \
6058 _ADLS_DPLL3_ENABLE, _ADLS_DPLL3_ENABLE))
6059
6060#define _DG2_PLL3_ENABLE 0x4601C
6061
6062#define DG2_PLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 3, \
6063 _DPLL0_ENABLE, _DPLL1_ENABLE, \
6064 _DG2_PLL3_ENABLE, _DG2_PLL3_ENABLE))
6065
6066#define TBT_PLL_ENABLE _MMIO(0x46020)
6067
6068#define _MG_PLL1_ENABLE 0x46030
6069#define _MG_PLL2_ENABLE 0x46034
6070#define _MG_PLL3_ENABLE 0x46038
6071#define _MG_PLL4_ENABLE 0x4603C
6072/* Bits are the same as _DPLL0_ENABLE */
6073#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
6074 _MG_PLL2_ENABLE)
6075
6076/* DG1 PLL */
6077#define DG1_DPLL_ENABLE(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
6078 _DPLL0_ENABLE, _DPLL1_ENABLE, \
6079 _MG_PLL1_ENABLE, _MG_PLL2_ENABLE))
6080
6081/* ADL-P Type C PLL */
6082#define PORTTC1_PLL_ENABLE 0x46038
6083#define PORTTC2_PLL_ENABLE 0x46040
6084
6085#define ADLP_PORTTC_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), \
6086 PORTTC1_PLL_ENABLE, \
6087 PORTTC2_PLL_ENABLE)
6088
6089#define _ICL_DPLL0_CFGCR0 0x164000
6090#define _ICL_DPLL1_CFGCR0 0x164080
6091#define ICL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR0, \
6092 _ICL_DPLL1_CFGCR0)
6093#define DPLL_CFGCR0_HDMI_MODE (1 << 30)
6094#define DPLL_CFGCR0_SSC_ENABLE (1 << 29)
6095#define DPLL_CFGCR0_SSC_ENABLE_ICL (1 << 25)
6096#define DPLL_CFGCR0_LINK_RATE_MASK (0xf << 25)
6097#define DPLL_CFGCR0_LINK_RATE_2700 (0 << 25)
6098#define DPLL_CFGCR0_LINK_RATE_1350 (1 << 25)
6099#define DPLL_CFGCR0_LINK_RATE_810 (2 << 25)
6100#define DPLL_CFGCR0_LINK_RATE_1620 (3 << 25)
6101#define DPLL_CFGCR0_LINK_RATE_1080 (4 << 25)
6102#define DPLL_CFGCR0_LINK_RATE_2160 (5 << 25)
6103#define DPLL_CFGCR0_LINK_RATE_3240 (6 << 25)
6104#define DPLL_CFGCR0_LINK_RATE_4050 (7 << 25)
6105#define DPLL_CFGCR0_DCO_FRACTION_MASK (0x7fff << 10)
6106#define DPLL_CFGCR0_DCO_FRACTION_SHIFT (10)
6107#define DPLL_CFGCR0_DCO_FRACTION(x) ((x) << 10)
6108#define DPLL_CFGCR0_DCO_INTEGER_MASK (0x3ff)
6109
6110#define _ICL_DPLL0_CFGCR1 0x164004
6111#define _ICL_DPLL1_CFGCR1 0x164084
6112#define ICL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
6113 _ICL_DPLL1_CFGCR1)
6114#define DPLL_CFGCR1_QDIV_RATIO_MASK (0xff << 10)
6115#define DPLL_CFGCR1_QDIV_RATIO_SHIFT (10)
6116#define DPLL_CFGCR1_QDIV_RATIO(x) ((x) << 10)
6117#define DPLL_CFGCR1_QDIV_MODE_SHIFT (9)
6118#define DPLL_CFGCR1_QDIV_MODE(x) ((x) << 9)
6119#define DPLL_CFGCR1_KDIV_MASK (7 << 6)
6120#define DPLL_CFGCR1_KDIV_SHIFT (6)
6121#define DPLL_CFGCR1_KDIV(x) ((x) << 6)
6122#define DPLL_CFGCR1_KDIV_1 (1 << 6)
6123#define DPLL_CFGCR1_KDIV_2 (2 << 6)
6124#define DPLL_CFGCR1_KDIV_3 (4 << 6)
6125#define DPLL_CFGCR1_PDIV_MASK (0xf << 2)
6126#define DPLL_CFGCR1_PDIV_SHIFT (2)
6127#define DPLL_CFGCR1_PDIV(x) ((x) << 2)
6128#define DPLL_CFGCR1_PDIV_2 (1 << 2)
6129#define DPLL_CFGCR1_PDIV_3 (2 << 2)
6130#define DPLL_CFGCR1_PDIV_5 (4 << 2)
6131#define DPLL_CFGCR1_PDIV_7 (8 << 2)
6132#define DPLL_CFGCR1_CENTRAL_FREQ (3 << 0)
6133#define DPLL_CFGCR1_CENTRAL_FREQ_8400 (3 << 0)
6134#define TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL (0 << 0)
6135
6136#define _TGL_DPLL0_CFGCR0 0x164284
6137#define _TGL_DPLL1_CFGCR0 0x16428C
6138#define _TGL_TBTPLL_CFGCR0 0x16429C
6139#define TGL_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
6140 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
6141 _TGL_TBTPLL_CFGCR0, _TGL_TBTPLL_CFGCR0))
6142#define RKL_DPLL_CFGCR0(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR0, \
6143 _TGL_DPLL1_CFGCR0)
6144
6145#define _TGL_DPLL0_DIV0 0x164B00
6146#define _TGL_DPLL1_DIV0 0x164C00
6147#define TGL_DPLL0_DIV0(pll) _MMIO_PLL(pll, _TGL_DPLL0_DIV0, _TGL_DPLL1_DIV0)
6148#define TGL_DPLL0_DIV0_AFC_STARTUP_MASK REG_GENMASK(27, 25)
6149#define TGL_DPLL0_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(TGL_DPLL0_DIV0_AFC_STARTUP_MASK, (val))
6150
6151#define _TGL_DPLL0_CFGCR1 0x164288
6152#define _TGL_DPLL1_CFGCR1 0x164290
6153#define _TGL_TBTPLL_CFGCR1 0x1642A0
6154#define TGL_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
6155 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
6156 _TGL_TBTPLL_CFGCR1, _TGL_TBTPLL_CFGCR1))
6157#define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
6158 _TGL_DPLL1_CFGCR1)
6159
6160#define _DG1_DPLL2_CFGCR0 0x16C284
6161#define _DG1_DPLL3_CFGCR0 0x16C28C
6162#define DG1_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
6163 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
6164 _DG1_DPLL2_CFGCR0, _DG1_DPLL3_CFGCR0))
6165
6166#define _DG1_DPLL2_CFGCR1 0x16C288
6167#define _DG1_DPLL3_CFGCR1 0x16C290
6168#define DG1_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
6169 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
6170 _DG1_DPLL2_CFGCR1, _DG1_DPLL3_CFGCR1))
6171
6172/* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
6173#define _ADLS_DPLL4_CFGCR0 0x164294
6174#define _ADLS_DPLL3_CFGCR0 0x1642C0
6175#define ADLS_DPLL_CFGCR0(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
6176 _TGL_DPLL0_CFGCR0, _TGL_DPLL1_CFGCR0, \
6177 _ADLS_DPLL4_CFGCR0, _ADLS_DPLL3_CFGCR0))
6178
6179#define _ADLS_DPLL4_CFGCR1 0x164298
6180#define _ADLS_DPLL3_CFGCR1 0x1642C4
6181#define ADLS_DPLL_CFGCR1(pll) _MMIO(_PICK_EVEN_2RANGES(pll, 2, \
6182 _TGL_DPLL0_CFGCR1, _TGL_DPLL1_CFGCR1, \
6183 _ADLS_DPLL4_CFGCR1, _ADLS_DPLL3_CFGCR1))
6184
6185/* BXT display engine PLL */
6186#define BXT_DE_PLL_CTL _MMIO(0x6d000)
6187#define BXT_DE_PLL_RATIO(x) (x) /* {60,65,100} * 19.2MHz */
6188#define BXT_DE_PLL_RATIO_MASK 0xff
6189
6190#define BXT_DE_PLL_ENABLE _MMIO(0x46070)
6191#define BXT_DE_PLL_PLL_ENABLE (1 << 31)
6192#define BXT_DE_PLL_LOCK (1 << 30)
6193#define BXT_DE_PLL_FREQ_REQ (1 << 23)
6194#define BXT_DE_PLL_FREQ_REQ_ACK (1 << 22)
6195#define ICL_CDCLK_PLL_RATIO(x) (x)
6196#define ICL_CDCLK_PLL_RATIO_MASK 0xff
6197
6198/* GEN9 DC */
6199#define DC_STATE_EN _MMIO(0x45504)
6200#define DC_STATE_DISABLE 0
6201#define DC_STATE_EN_DC3CO REG_BIT(30)
6202#define DC_STATE_DC3CO_STATUS REG_BIT(29)
6203#define HOLD_PHY_CLKREQ_PG1_LATCH REG_BIT(21)
6204#define HOLD_PHY_PG1_LATCH REG_BIT(20)
6205#define DC_STATE_EN_UPTO_DC5 (1 << 0)
6206#define DC_STATE_EN_DC9 (1 << 3)
6207#define DC_STATE_EN_UPTO_DC6 (2 << 0)
6208#define DC_STATE_EN_UPTO_DC5_DC6_MASK 0x3
6209
6210#define DC_STATE_DEBUG _MMIO(0x45520)
6211#define DC_STATE_DEBUG_MASK_CORES (1 << 0)
6212#define DC_STATE_DEBUG_MASK_MEMORY_UP (1 << 1)
6213
6214#define D_COMP_BDW _MMIO(0x138144)
6215
6216/* Pipe WM_LINETIME - watermark line time */
6217#define _WM_LINETIME_A 0x45270
6218#define _WM_LINETIME_B 0x45274
6219#define WM_LINETIME(pipe) _MMIO_PIPE(pipe, _WM_LINETIME_A, _WM_LINETIME_B)
6220#define HSW_LINETIME_MASK REG_GENMASK(8, 0)
6221#define HSW_LINETIME(x) REG_FIELD_PREP(HSW_LINETIME_MASK, (x))
6222#define HSW_IPS_LINETIME_MASK REG_GENMASK(24, 16)
6223#define HSW_IPS_LINETIME(x) REG_FIELD_PREP(HSW_IPS_LINETIME_MASK, (x))
6224
6225/* SFUSE_STRAP */
6226#define SFUSE_STRAP _MMIO(0xc2014)
6227#define SFUSE_STRAP_FUSE_LOCK (1 << 13)
6228#define SFUSE_STRAP_RAW_FREQUENCY (1 << 8)
6229#define SFUSE_STRAP_DISPLAY_DISABLED (1 << 7)
6230#define SFUSE_STRAP_CRT_DISABLED (1 << 6)
6231#define SFUSE_STRAP_DDIF_DETECTED (1 << 3)
6232#define SFUSE_STRAP_DDIB_DETECTED (1 << 2)
6233#define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
6234#define SFUSE_STRAP_DDID_DETECTED (1 << 0)
6235
6236#define WM_MISC _MMIO(0x45260)
6237#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
6238
6239#define WM_DBG _MMIO(0x45280)
6240#define WM_DBG_DISALLOW_MULTIPLE_LP (1 << 0)
6241#define WM_DBG_DISALLOW_MAXFIFO (1 << 1)
6242#define WM_DBG_DISALLOW_SPRITE (1 << 2)
6243
6244#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
6245
6246/* Plane CSC Registers */
6247#define _PLANE_CSC_RY_GY_1_A 0x70210
6248#define _PLANE_CSC_RY_GY_2_A 0x70310
6249
6250#define _PLANE_CSC_RY_GY_1_B 0x71210
6251#define _PLANE_CSC_RY_GY_2_B 0x71310
6252
6253#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \
6254 _PLANE_CSC_RY_GY_1_B)
6255#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, \
6256 _PLANE_CSC_RY_GY_2_B)
6257#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \
6258 _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \
6259 _PLANE_CSC_RY_GY_2(pipe) + (index) * 4)
6260
6261#define _PLANE_CSC_PREOFF_HI_1_A 0x70228
6262#define _PLANE_CSC_PREOFF_HI_2_A 0x70328
6263
6264#define _PLANE_CSC_PREOFF_HI_1_B 0x71228
6265#define _PLANE_CSC_PREOFF_HI_2_B 0x71328
6266
6267#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \
6268 _PLANE_CSC_PREOFF_HI_1_B)
6269#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \
6270 _PLANE_CSC_PREOFF_HI_2_B)
6271#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \
6272 (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \
6273 (index) * 4)
6274
6275#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234
6276#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334
6277
6278#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234
6279#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334
6280
6281#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \
6282 _PLANE_CSC_POSTOFF_HI_1_B)
6283#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \
6284 _PLANE_CSC_POSTOFF_HI_2_B)
6285#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \
6286 (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \
6287 (index) * 4)
6288
6289/* Gen4+ Timestamp and Pipe Frame time stamp registers */
6290#define GEN4_TIMESTAMP _MMIO(0x2358)
6291#define ILK_TIMESTAMP_HI _MMIO(0x70070)
6292#define IVB_TIMESTAMP_CTR _MMIO(0x44070)
6293
6294#define GEN9_TIMESTAMP_OVERRIDE _MMIO(0x44074)
6295#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0
6296#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff
6297#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12
6298#define GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12)
6299
6300/* g4x+, except vlv/chv! */
6301#define _PIPE_FRMTMSTMP_A 0x70048
6302#define _PIPE_FRMTMSTMP_B 0x71048
6303#define PIPE_FRMTMSTMP(pipe) \
6304 _MMIO_PIPE(pipe, _PIPE_FRMTMSTMP_A, _PIPE_FRMTMSTMP_B)
6305
6306/* g4x+, except vlv/chv! */
6307#define _PIPE_FLIPTMSTMP_A 0x7004C
6308#define _PIPE_FLIPTMSTMP_B 0x7104C
6309#define PIPE_FLIPTMSTMP(pipe) \
6310 _MMIO_PIPE(pipe, _PIPE_FLIPTMSTMP_A, _PIPE_FLIPTMSTMP_B)
6311
6312/* tgl+ */
6313#define _PIPE_FLIPDONETMSTMP_A 0x70054
6314#define _PIPE_FLIPDONETMSTMP_B 0x71054
6315#define PIPE_FLIPDONETIMSTMP(pipe) \
6316 _MMIO_PIPE(pipe, _PIPE_FLIPDONETMSTMP_A, _PIPE_FLIPDONETMSTMP_B)
6317
6318#define _VLV_PIPE_MSA_MISC_A 0x70048
6319#define VLV_PIPE_MSA_MISC(pipe) \
6320 _MMIO_PIPE2(pipe, _VLV_PIPE_MSA_MISC_A)
6321#define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31)
6322#define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */
6323
6324#define GGC _MMIO(0x108040)
6325#define GMS_MASK REG_GENMASK(15, 8)
6326#define GGMS_MASK REG_GENMASK(7, 6)
6327
6328#define GEN6_GSMBASE _MMIO(0x108100)
6329#define GEN6_DSMBASE _MMIO(0x1080C0)
6330#define GEN6_BDSM_MASK REG_GENMASK64(31, 20)
6331#define GEN11_BDSM_MASK REG_GENMASK64(63, 20)
6332
6333#define XEHP_CLOCK_GATE_DIS _MMIO(0x101014)
6334#define SGSI_SIDECLK_DIS REG_BIT(17)
6335#define SGGI_DIS REG_BIT(15)
6336#define SGR_DIS REG_BIT(13)
6337
6338#define _ICL_PHY_MISC_A 0x64C00
6339#define _ICL_PHY_MISC_B 0x64C04
6340#define _DG2_PHY_MISC_TC1 0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
6341#define ICL_PHY_MISC(port) _MMIO_PORT(port, _ICL_PHY_MISC_A, _ICL_PHY_MISC_B)
6342#define DG2_PHY_MISC(port) ((port) == PHY_E ? _MMIO(_DG2_PHY_MISC_TC1) : \
6343 ICL_PHY_MISC(port))
6344#define ICL_PHY_MISC_MUX_DDID (1 << 28)
6345#define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
6346#define DG2_PHY_DP_TX_ACK_MASK REG_GENMASK(23, 20)
6347
6348#define PORT_TX_DFLEXDPSP(fia) _MMIO_FIA((fia), 0x008A0)
6349#define MODULAR_FIA_MASK (1 << 4)
6350#define TC_LIVE_STATE_TBT(idx) (1 << ((idx) * 8 + 6))
6351#define TC_LIVE_STATE_TC(idx) (1 << ((idx) * 8 + 5))
6352#define DP_LANE_ASSIGNMENT_SHIFT(idx) ((idx) * 8)
6353#define DP_LANE_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 8))
6354#define DP_LANE_ASSIGNMENT(idx, x) ((x) << ((idx) * 8))
6355
6356#define PORT_TX_DFLEXDPPMS(fia) _MMIO_FIA((fia), 0x00890)
6357#define DP_PHY_MODE_STATUS_COMPLETED(idx) (1 << (idx))
6358
6359#define PORT_TX_DFLEXDPCSSS(fia) _MMIO_FIA((fia), 0x00894)
6360#define DP_PHY_MODE_STATUS_NOT_SAFE(idx) (1 << (idx))
6361
6362#define PORT_TX_DFLEXPA1(fia) _MMIO_FIA((fia), 0x00880)
6363#define DP_PIN_ASSIGNMENT_SHIFT(idx) ((idx) * 4)
6364#define DP_PIN_ASSIGNMENT_MASK(idx) (0xf << ((idx) * 4))
6365#define DP_PIN_ASSIGNMENT(idx, x) ((x) << ((idx) * 4))
6366
6367#define _TCSS_DDI_STATUS_1 0x161500
6368#define _TCSS_DDI_STATUS_2 0x161504
6369#define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
6370 _TCSS_DDI_STATUS_1, \
6371 _TCSS_DDI_STATUS_2))
6372#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25)
6373#define TCSS_DDI_STATUS_READY REG_BIT(2)
6374#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
6375#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
6376
6377#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
6378#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
6379#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
6380#define SPI_STATIC_REGIONS _MMIO(0x102090)
6381#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
6382#define OROM_OFFSET _MMIO(0x1020c0)
6383#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
6384
6385#define CLKREQ_POLICY _MMIO(0x101038)
6386#define CLKREQ_POLICY_MEM_UP_OVRD REG_BIT(1)
6387
6388#define CLKGATE_DIS_MISC _MMIO(0x46534)
6389#define CLKGATE_DIS_MISC_DMASC_GATING_DIS REG_BIT(21)
6390
6391#define _MTL_CLKGATE_DIS_TRANS_A 0x604E8
6392#define _MTL_CLKGATE_DIS_TRANS_B 0x614E8
6393#define MTL_CLKGATE_DIS_TRANS(trans) _MMIO_TRANS2(trans, _MTL_CLKGATE_DIS_TRANS_A)
6394#define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7)
6395
6396#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
6397#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
6398#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
6399#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
6400
6401#define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710
6402#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8)
6403#define MTL_TRCD_MASK REG_GENMASK(31, 24)
6404#define MTL_TRP_MASK REG_GENMASK(23, 16)
6405#define MTL_DCLK_MASK REG_GENMASK(15, 0)
6406
6407#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4)
6408#define MTL_TRAS_MASK REG_GENMASK(16, 8)
6409#define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
6410
6411#define MTL_MEDIA_GSI_BASE 0x380000
6412
6413#endif /* _I915_REG_H_ */