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   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (c) 2009, Intel Corporation.
   4 */
   5#ifndef __PSB_INTEL_REG_H__
   6#define __PSB_INTEL_REG_H__
   7
   8/*
   9 * GPIO regs
  10 */
  11#define GPIOA			0x5010
  12#define GPIOB			0x5014
  13#define GPIOC			0x5018
  14#define GPIOD			0x501c
  15#define GPIOE			0x5020
  16#define GPIOF			0x5024
  17#define GPIOG			0x5028
  18#define GPIOH			0x502c
  19# define GPIO_CLOCK_DIR_MASK		(1 << 0)
  20# define GPIO_CLOCK_DIR_IN		(0 << 1)
  21# define GPIO_CLOCK_DIR_OUT		(1 << 1)
  22# define GPIO_CLOCK_VAL_MASK		(1 << 2)
  23# define GPIO_CLOCK_VAL_OUT		(1 << 3)
  24# define GPIO_CLOCK_VAL_IN		(1 << 4)
  25# define GPIO_CLOCK_PULLUP_DISABLE	(1 << 5)
  26# define GPIO_DATA_DIR_MASK		(1 << 8)
  27# define GPIO_DATA_DIR_IN		(0 << 9)
  28# define GPIO_DATA_DIR_OUT		(1 << 9)
  29# define GPIO_DATA_VAL_MASK		(1 << 10)
  30# define GPIO_DATA_VAL_OUT		(1 << 11)
  31# define GPIO_DATA_VAL_IN		(1 << 12)
  32# define GPIO_DATA_PULLUP_DISABLE	(1 << 13)
  33
  34#define GMBUS0			0x5100 /* clock/port select */
  35#define   GMBUS_RATE_100KHZ	(0<<8)
  36#define   GMBUS_RATE_50KHZ	(1<<8)
  37#define   GMBUS_RATE_400KHZ	(2<<8) /* reserved on Pineview */
  38#define   GMBUS_RATE_1MHZ	(3<<8) /* reserved on Pineview */
  39#define   GMBUS_HOLD_EXT	(1<<7) /* 300ns hold time, rsvd on Pineview */
  40#define   GMBUS_PORT_DISABLED	0
  41#define   GMBUS_PORT_SSC	1
  42#define   GMBUS_PORT_VGADDC	2
  43#define   GMBUS_PORT_PANEL	3
  44#define   GMBUS_PORT_DPC	4 /* HDMIC */
  45#define   GMBUS_PORT_DPB	5 /* SDVO, HDMIB */
  46				  /* 6 reserved */
  47#define   GMBUS_PORT_DPD	7 /* HDMID */
  48#define   GMBUS_NUM_PORTS       8
  49#define GMBUS1			0x5104 /* command/status */
  50#define   GMBUS_SW_CLR_INT	(1<<31)
  51#define   GMBUS_SW_RDY		(1<<30)
  52#define   GMBUS_ENT		(1<<29) /* enable timeout */
  53#define   GMBUS_CYCLE_NONE	(0<<25)
  54#define   GMBUS_CYCLE_WAIT	(1<<25)
  55#define   GMBUS_CYCLE_INDEX	(2<<25)
  56#define   GMBUS_CYCLE_STOP	(4<<25)
  57#define   GMBUS_BYTE_COUNT_SHIFT 16
  58#define   GMBUS_SLAVE_INDEX_SHIFT 8
  59#define   GMBUS_SLAVE_ADDR_SHIFT 1
  60#define   GMBUS_SLAVE_READ	(1<<0)
  61#define   GMBUS_SLAVE_WRITE	(0<<0)
  62#define GMBUS2			0x5108 /* status */
  63#define   GMBUS_INUSE		(1<<15)
  64#define   GMBUS_HW_WAIT_PHASE	(1<<14)
  65#define   GMBUS_STALL_TIMEOUT	(1<<13)
  66#define   GMBUS_INT		(1<<12)
  67#define   GMBUS_HW_RDY		(1<<11)
  68#define   GMBUS_SATOER		(1<<10)
  69#define   GMBUS_ACTIVE		(1<<9)
  70#define GMBUS3			0x510c /* data buffer bytes 3-0 */
  71#define GMBUS4			0x5110 /* interrupt mask (Pineview+) */
  72#define   GMBUS_SLAVE_TIMEOUT_EN (1<<4)
  73#define   GMBUS_NAK_EN		(1<<3)
  74#define   GMBUS_IDLE_EN		(1<<2)
  75#define   GMBUS_HW_WAIT_EN	(1<<1)
  76#define   GMBUS_HW_RDY_EN	(1<<0)
  77#define GMBUS5			0x5120 /* byte index */
  78#define   GMBUS_2BYTE_INDEX_EN	(1<<31)
  79
  80#define BLC_PWM_CTL		0x61254
  81#define BLC_PWM_CTL2		0x61250
  82#define  PWM_ENABLE		(1 << 31)
  83#define  PWM_LEGACY_MODE	(1 << 30)
  84#define  PWM_PIPE_B		(1 << 29)
  85#define BLC_PWM_CTL_C		0x62254
  86#define BLC_PWM_CTL2_C		0x62250
  87#define BACKLIGHT_MODULATION_FREQ_SHIFT		(17)
  88/*
  89 * This is the most significant 15 bits of the number of backlight cycles in a
  90 * complete cycle of the modulated backlight control.
  91 *
  92 * The actual value is this field multiplied by two.
  93 */
  94#define BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
  95#define BLM_LEGACY_MODE			(1 << 16)
  96/*
  97 * This is the number of cycles out of the backlight modulation cycle for which
  98 * the backlight is on.
  99 *
 100 * This field must be no greater than the number of cycles in the complete
 101 * backlight modulation cycle.
 102 */
 103#define BACKLIGHT_DUTY_CYCLE_SHIFT	(0)
 104#define BACKLIGHT_DUTY_CYCLE_MASK	(0xffff)
 105
 106#define I915_GCFGC			0xf0
 107#define I915_LOW_FREQUENCY_ENABLE	(1 << 7)
 108#define I915_DISPLAY_CLOCK_190_200_MHZ	(0 << 4)
 109#define I915_DISPLAY_CLOCK_333_MHZ	(4 << 4)
 110#define I915_DISPLAY_CLOCK_MASK		(7 << 4)
 111
 112#define I855_HPLLCC			0xc0
 113#define I855_CLOCK_CONTROL_MASK		(3 << 0)
 114#define I855_CLOCK_133_200		(0 << 0)
 115#define I855_CLOCK_100_200		(1 << 0)
 116#define I855_CLOCK_100_133		(2 << 0)
 117#define I855_CLOCK_166_250		(3 << 0)
 118
 119/* I830 CRTC registers */
 120#define HTOTAL_A		0x60000
 121#define HBLANK_A		0x60004
 122#define HSYNC_A			0x60008
 123#define VTOTAL_A		0x6000c
 124#define VBLANK_A		0x60010
 125#define VSYNC_A			0x60014
 126#define PIPEASRC		0x6001c
 127#define BCLRPAT_A		0x60020
 128#define VSYNCSHIFT_A		0x60028
 129
 130#define HTOTAL_B		0x61000
 131#define HBLANK_B		0x61004
 132#define HSYNC_B			0x61008
 133#define VTOTAL_B		0x6100c
 134#define VBLANK_B		0x61010
 135#define VSYNC_B			0x61014
 136#define PIPEBSRC		0x6101c
 137#define BCLRPAT_B		0x61020
 138#define VSYNCSHIFT_B		0x61028
 139
 140#define HTOTAL_C		0x62000
 141#define HBLANK_C		0x62004
 142#define HSYNC_C			0x62008
 143#define VTOTAL_C		0x6200c
 144#define VBLANK_C		0x62010
 145#define VSYNC_C			0x62014
 146#define PIPECSRC		0x6201c
 147#define BCLRPAT_C		0x62020
 148#define VSYNCSHIFT_C		0x62028
 149
 150#define PP_STATUS		0x61200
 151# define PP_ON				(1 << 31)
 152/*
 153 * Indicates that all dependencies of the panel are on:
 154 *
 155 * - PLL enabled
 156 * - pipe enabled
 157 * - LVDS/DVOB/DVOC on
 158 */
 159#define PP_READY			(1 << 30)
 160#define PP_SEQUENCE_NONE		(0 << 28)
 161#define PP_SEQUENCE_ON			(1 << 28)
 162#define PP_SEQUENCE_OFF			(2 << 28)
 163#define PP_SEQUENCE_MASK		0x30000000
 164#define	PP_CYCLE_DELAY_ACTIVE		(1 << 27)
 165#define	PP_SEQUENCE_STATE_ON_IDLE	(1 << 3)
 166#define	PP_SEQUENCE_STATE_MASK		0x0000000f
 167
 168#define PP_CONTROL		0x61204
 169#define POWER_TARGET_ON			(1 << 0)
 170#define	PANEL_UNLOCK_REGS		(0xabcd << 16)
 171#define	PANEL_UNLOCK_MASK		(0xffff << 16)
 172#define	EDP_FORCE_VDD			(1 << 3)
 173#define	EDP_BLC_ENABLE			(1 << 2)
 174#define	PANEL_POWER_RESET		(1 << 1)
 175#define	PANEL_POWER_OFF			(0 << 0)
 176#define	PANEL_POWER_ON			(1 << 0)
 177
 178/* Poulsbo/Oaktrail */
 179#define LVDSPP_ON		0x61208
 180#define LVDSPP_OFF		0x6120c
 181#define PP_CYCLE		0x61210
 182
 183/* Cedartrail */
 184#define PP_ON_DELAYS		0x61208		/* Cedartrail */
 185#define PANEL_PORT_SELECT_MASK 		(3 << 30)
 186#define PANEL_PORT_SELECT_LVDS 		(0 << 30)
 187#define PANEL_PORT_SELECT_EDP		(1 << 30)
 188#define PANEL_POWER_UP_DELAY_MASK	(0x1fff0000)
 189#define PANEL_POWER_UP_DELAY_SHIFT	16
 190#define PANEL_LIGHT_ON_DELAY_MASK	(0x1fff)
 191#define PANEL_LIGHT_ON_DELAY_SHIFT	0
 192
 193#define PP_OFF_DELAYS		0x6120c		/* Cedartrail */
 194#define PANEL_POWER_DOWN_DELAY_MASK	(0x1fff0000)
 195#define PANEL_POWER_DOWN_DELAY_SHIFT	16
 196#define PANEL_LIGHT_OFF_DELAY_MASK	(0x1fff)
 197#define PANEL_LIGHT_OFF_DELAY_SHIFT	0
 198
 199#define PP_DIVISOR		0x61210		/* Cedartrail */
 200#define  PP_REFERENCE_DIVIDER_MASK	(0xffffff00)
 201#define  PP_REFERENCE_DIVIDER_SHIFT	8
 202#define  PANEL_POWER_CYCLE_DELAY_MASK	(0x1f)
 203#define  PANEL_POWER_CYCLE_DELAY_SHIFT	0
 204
 205#define PFIT_CONTROL		0x61230
 206#define PFIT_ENABLE			(1 << 31)
 207#define PFIT_PIPE_MASK			(3 << 29)
 208#define PFIT_PIPE_SHIFT			29
 209#define PFIT_SCALING_MODE_PILLARBOX	(1 << 27)
 210#define PFIT_SCALING_MODE_LETTERBOX	(3 << 26)
 211#define VERT_INTERP_DISABLE		(0 << 10)
 212#define VERT_INTERP_BILINEAR		(1 << 10)
 213#define VERT_INTERP_MASK		(3 << 10)
 214#define VERT_AUTO_SCALE			(1 << 9)
 215#define HORIZ_INTERP_DISABLE		(0 << 6)
 216#define HORIZ_INTERP_BILINEAR		(1 << 6)
 217#define HORIZ_INTERP_MASK		(3 << 6)
 218#define HORIZ_AUTO_SCALE		(1 << 5)
 219#define PANEL_8TO6_DITHER_ENABLE	(1 << 3)
 220
 221#define PFIT_PGM_RATIOS		0x61234
 222#define PFIT_VERT_SCALE_MASK			0xfff00000
 223#define PFIT_HORIZ_SCALE_MASK			0x0000fff0
 224
 225#define PFIT_AUTO_RATIOS	0x61238
 226
 227#define DPLL_A			0x06014
 228#define DPLL_B			0x06018
 229#define DPLL_VCO_ENABLE			(1 << 31)
 230#define DPLL_DVO_HIGH_SPEED		(1 << 30)
 231#define DPLL_SYNCLOCK_ENABLE		(1 << 29)
 232#define DPLL_VGA_MODE_DIS		(1 << 28)
 233#define DPLLB_MODE_DAC_SERIAL		(1 << 26)	/* i915 */
 234#define DPLLB_MODE_LVDS			(2 << 26)	/* i915 */
 235#define DPLL_MODE_MASK			(3 << 26)
 236#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10	(0 << 24)	/* i915 */
 237#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5	(1 << 24)	/* i915 */
 238#define DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24)	/* i915 */
 239#define DPLLB_LVDS_P2_CLOCK_DIV_7	(1 << 24)	/* i915 */
 240#define DPLL_P2_CLOCK_DIV_MASK		0x03000000	/* i915 */
 241#define DPLL_FPA0h1_P1_POST_DIV_MASK	0x00ff0000	/* i915 */
 242#define DPLL_LOCK			(1 << 15)	/* CDV */
 243
 244/*
 245 *  The i830 generation, in DAC/serial mode, defines p1 as two plus this
 246 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
 247 */
 248# define DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
 249/*
 250 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
 251 * this field (only one bit may be set).
 252 */
 253#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
 254#define DPLL_FPA01_P1_POST_DIV_SHIFT	16
 255#define PLL_P2_DIVIDE_BY_4		(1 << 23)	/* i830, required
 256							 * in DVO non-gang */
 257# define PLL_P1_DIVIDE_BY_TWO		(1 << 21)	/* i830 */
 258#define PLL_REF_INPUT_DREFCLK		(0 << 13)
 259#define PLL_REF_INPUT_TVCLKINA		(1 << 13)	/* i830 */
 260#define PLL_REF_INPUT_TVCLKINBC		(2 << 13)	/* SDVO
 261								 * TVCLKIN */
 262#define PLLB_REF_INPUT_SPREADSPECTRUMIN	(3 << 13)
 263#define PLL_REF_INPUT_MASK		(3 << 13)
 264#define PLL_LOAD_PULSE_PHASE_SHIFT	9
 265/*
 266 * Parallel to Serial Load Pulse phase selection.
 267 * Selects the phase for the 10X DPLL clock for the PCIe
 268 * digital display port. The range is 4 to 13; 10 or more
 269 * is just a flip delay. The default is 6
 270 */
 271#define PLL_LOAD_PULSE_PHASE_MASK	(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
 272#define DISPLAY_RATE_SELECT_FPA1	(1 << 8)
 273
 274/*
 275 * SDVO multiplier for 945G/GM. Not used on 965.
 276 *
 277 * DPLL_MD_UDI_MULTIPLIER_MASK
 278 */
 279#define SDVO_MULTIPLIER_MASK		0x000000ff
 280#define SDVO_MULTIPLIER_SHIFT_HIRES	4
 281#define SDVO_MULTIPLIER_SHIFT_VGA	0
 282
 283/*
 284 * PLL_MD
 285 */
 286/* Pipe A SDVO/UDI clock multiplier/divider register for G965. */
 287#define DPLL_A_MD		0x0601c
 288/* Pipe B SDVO/UDI clock multiplier/divider register for G965. */
 289#define DPLL_B_MD		0x06020
 290/*
 291 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
 292 *
 293 * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
 294 */
 295#define DPLL_MD_UDI_DIVIDER_MASK	0x3f000000
 296#define DPLL_MD_UDI_DIVIDER_SHIFT	24
 297/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
 298#define DPLL_MD_VGA_UDI_DIVIDER_MASK	0x003f0000
 299#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT	16
 300/*
 301 * SDVO/UDI pixel multiplier.
 302 *
 303 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
 304 * clock rate is 10 times the DPLL clock.  At low resolution/refresh rate
 305 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
 306 * dummy bytes in the datastream at an increased clock rate, with both sides of
 307 * the link knowing how many bytes are fill.
 308 *
 309 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
 310 * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
 311 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
 312 * through an SDVO command.
 313 *
 314 * This register field has values of multiplication factor minus 1, with
 315 * a maximum multiplier of 5 for SDVO.
 316 */
 317#define DPLL_MD_UDI_MULTIPLIER_MASK	0x00003f00
 318#define DPLL_MD_UDI_MULTIPLIER_SHIFT	8
 319/*
 320 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
 321 * This best be set to the default value (3) or the CRT won't work. No,
 322 * I don't entirely understand what this does...
 323 */
 324#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
 325#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
 326
 327#define DPLL_TEST		0x606c
 328#define DPLLB_TEST_SDVO_DIV_1		(0 << 22)
 329#define DPLLB_TEST_SDVO_DIV_2		(1 << 22)
 330#define DPLLB_TEST_SDVO_DIV_4		(2 << 22)
 331#define DPLLB_TEST_SDVO_DIV_MASK	(3 << 22)
 332#define DPLLB_TEST_N_BYPASS		(1 << 19)
 333#define DPLLB_TEST_M_BYPASS		(1 << 18)
 334#define DPLLB_INPUT_BUFFER_ENABLE	(1 << 16)
 335#define DPLLA_TEST_N_BYPASS		(1 << 3)
 336#define DPLLA_TEST_M_BYPASS		(1 << 2)
 337#define DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
 338
 339#define ADPA			0x61100
 340#define ADPA_DAC_ENABLE			(1 << 31)
 341#define ADPA_DAC_DISABLE		0
 342#define ADPA_PIPE_SELECT_MASK		(1 << 30)
 343#define ADPA_PIPE_A_SELECT		0
 344#define ADPA_PIPE_B_SELECT		(1 << 30)
 345#define ADPA_USE_VGA_HVPOLARITY		(1 << 15)
 346#define ADPA_SETS_HVPOLARITY		0
 347#define ADPA_VSYNC_CNTL_DISABLE		(1 << 11)
 348#define ADPA_VSYNC_CNTL_ENABLE		0
 349#define ADPA_HSYNC_CNTL_DISABLE		(1 << 10)
 350#define ADPA_HSYNC_CNTL_ENABLE		0
 351#define ADPA_VSYNC_ACTIVE_HIGH		(1 << 4)
 352#define ADPA_VSYNC_ACTIVE_LOW		0
 353#define ADPA_HSYNC_ACTIVE_HIGH		(1 << 3)
 354#define ADPA_HSYNC_ACTIVE_LOW		0
 355
 356#define FPA0			0x06040
 357#define FPA1			0x06044
 358#define FPB0			0x06048
 359#define FPB1			0x0604c
 360#define FP_N_DIV_MASK			0x003f0000
 361#define FP_N_DIV_SHIFT			16
 362#define FP_M1_DIV_MASK			0x00003f00
 363#define FP_M1_DIV_SHIFT			8
 364#define FP_M2_DIV_MASK			0x0000003f
 365#define FP_M2_DIV_SHIFT			0
 366
 367#define PORT_HOTPLUG_EN		0x61110
 368#define HDMIB_HOTPLUG_INT_EN		(1 << 29)
 369#define HDMIC_HOTPLUG_INT_EN		(1 << 28)
 370#define HDMID_HOTPLUG_INT_EN		(1 << 27)
 371#define SDVOB_HOTPLUG_INT_EN		(1 << 26)
 372#define SDVOC_HOTPLUG_INT_EN		(1 << 25)
 373#define TV_HOTPLUG_INT_EN		(1 << 18)
 374#define CRT_HOTPLUG_INT_EN		(1 << 9)
 375#define CRT_HOTPLUG_FORCE_DETECT	(1 << 3)
 376/* CDV.. */
 377#define CRT_HOTPLUG_ACTIVATION_PERIOD_64	(1 << 8)
 378#define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
 379#define CRT_HOTPLUG_DAC_ON_TIME_4M		(1 << 7)
 380#define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
 381#define CRT_HOTPLUG_VOLTAGE_COMPARE_50		(1 << 5)
 382#define CRT_HOTPLUG_VOLTAGE_COMPARE_60		(2 << 5)
 383#define CRT_HOTPLUG_VOLTAGE_COMPARE_70		(3 << 5)
 384#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK	(3 << 5)
 385#define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
 386#define CRT_HOTPLUG_DETECT_DELAY_2G		(1 << 4)
 387#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
 388#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
 389#define CRT_HOTPLUG_DETECT_MASK			0x000000F8
 390
 391#define PORT_HOTPLUG_STAT	0x61114
 392#define CRT_HOTPLUG_INT_STATUS		(1 << 11)
 393#define TV_HOTPLUG_INT_STATUS		(1 << 10)
 394#define CRT_HOTPLUG_MONITOR_MASK	(3 << 8)
 395#define CRT_HOTPLUG_MONITOR_COLOR	(3 << 8)
 396#define CRT_HOTPLUG_MONITOR_MONO	(2 << 8)
 397#define CRT_HOTPLUG_MONITOR_NONE	(0 << 8)
 398#define SDVOC_HOTPLUG_INT_STATUS	(1 << 7)
 399#define SDVOB_HOTPLUG_INT_STATUS	(1 << 6)
 400
 401#define SDVOB			0x61140
 402#define SDVOC			0x61160
 403#define SDVO_ENABLE			(1 << 31)
 404#define SDVO_PIPE_B_SELECT		(1 << 30)
 405#define SDVO_STALL_SELECT		(1 << 29)
 406#define SDVO_INTERRUPT_ENABLE		(1 << 26)
 407#define SDVO_COLOR_RANGE_16_235		(1 << 8)
 408#define SDVO_AUDIO_ENABLE		(1 << 6)
 409
 410/**
 411 * 915G/GM SDVO pixel multiplier.
 412 *
 413 * Programmed value is multiplier - 1, up to 5x.
 414 *
 415 * DPLL_MD_UDI_MULTIPLIER_MASK
 416 */
 417#define SDVO_PORT_MULTIPLY_MASK		(7 << 23)
 418#define SDVO_PORT_MULTIPLY_SHIFT	23
 419#define SDVO_PHASE_SELECT_MASK		(15 << 19)
 420#define SDVO_PHASE_SELECT_DEFAULT	(6 << 19)
 421#define SDVO_CLOCK_OUTPUT_INVERT	(1 << 18)
 422#define SDVOC_GANG_MODE			(1 << 16)
 423#define SDVO_BORDER_ENABLE		(1 << 7)
 424#define SDVOB_PCIE_CONCURRENCY		(1 << 3)
 425#define SDVO_DETECTED			(1 << 2)
 426/* Bits to be preserved when writing */
 427#define SDVOB_PRESERVE_MASK		((1 << 17) | (1 << 16) | (1 << 14))
 428#define SDVOC_PRESERVE_MASK		(1 << 17)
 429
 430/*
 431 * This register controls the LVDS output enable, pipe selection, and data
 432 * format selection.
 433 *
 434 * All of the clock/data pairs are force powered down by power sequencing.
 435 */
 436#define LVDS			0x61180
 437/*
 438 * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
 439 * the DPLL semantics change when the LVDS is assigned to that pipe.
 440 */
 441#define LVDS_PORT_EN			(1 << 31)
 442/* Selects pipe B for LVDS data.  Must be set on pre-965. */
 443#define LVDS_PIPEB_SELECT		(1 << 30)
 444
 445/* Turns on border drawing to allow centered display. */
 446#define LVDS_BORDER_EN			(1 << 15)
 447
 448/*
 449 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
 450 * pixel.
 451 */
 452#define LVDS_A0A2_CLKA_POWER_MASK	(3 << 8)
 453#define LVDS_A0A2_CLKA_POWER_DOWN	(0 << 8)
 454#define LVDS_A0A2_CLKA_POWER_UP		(3 << 8)
 455/*
 456 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
 457 * mode.  Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
 458 * on.
 459 */
 460#define LVDS_A3_POWER_MASK		(3 << 6)
 461#define LVDS_A3_POWER_DOWN		(0 << 6)
 462#define LVDS_A3_POWER_UP		(3 << 6)
 463/*
 464 * Controls the CLKB pair.  This should only be set when LVDS_B0B3_POWER_UP
 465 * is set.
 466 */
 467#define LVDS_CLKB_POWER_MASK		(3 << 4)
 468#define LVDS_CLKB_POWER_DOWN		(0 << 4)
 469#define LVDS_CLKB_POWER_UP		(3 << 4)
 470/*
 471 * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
 472 * setting for whether we are in dual-channel mode.  The B3 pair will
 473 * additionally only be powered up when LVDS_A3_POWER_UP is set.
 474 */
 475#define LVDS_B0B3_POWER_MASK		(3 << 2)
 476#define LVDS_B0B3_POWER_DOWN		(0 << 2)
 477#define LVDS_B0B3_POWER_UP		(3 << 2)
 478
 479#define PIPEACONF		0x70008
 480#define PIPEACONF_ENABLE		(1 << 31)
 481#define PIPEACONF_DISABLE		0
 482#define PIPEACONF_DOUBLE_WIDE		(1 << 30)
 483#define PIPECONF_ACTIVE			(1 << 30)
 484#define PIPECONF_DSIPLL_LOCK		(1 << 29)
 485#define PIPEACONF_SINGLE_WIDE		0
 486#define PIPEACONF_PIPE_UNLOCKED		0
 487#define PIPEACONF_DSR			(1 << 26)
 488#define PIPEACONF_PIPE_LOCKED		(1 << 25)
 489#define PIPEACONF_PALETTE		0
 490#define PIPECONF_FORCE_BORDER		(1 << 25)
 491#define PIPEACONF_GAMMA			(1 << 24)
 492#define PIPECONF_PROGRESSIVE		(0 << 21)
 493#define PIPECONF_INTERLACE_W_FIELD_INDICATION	(6 << 21)
 494#define PIPECONF_INTERLACE_FIELD_0_ONLY		(7 << 21)
 495#define PIPECONF_PLANE_OFF		(1 << 19)
 496#define PIPECONF_CURSOR_OFF		(1 << 18)
 497
 498#define PIPEBCONF		0x71008
 499#define PIPEBCONF_ENABLE		(1 << 31)
 500#define PIPEBCONF_DISABLE		0
 501#define PIPEBCONF_DOUBLE_WIDE		(1 << 30)
 502#define PIPEBCONF_DISABLE		0
 503#define PIPEBCONF_GAMMA			(1 << 24)
 504#define PIPEBCONF_PALETTE		0
 505
 506#define PIPECCONF		0x72008
 507
 508#define PIPEBGCMAXRED		0x71010
 509#define PIPEBGCMAXGREEN		0x71014
 510#define PIPEBGCMAXBLUE		0x71018
 511
 512#define PIPEASTAT		0x70024
 513#define PIPEBSTAT		0x71024
 514#define PIPECSTAT		0x72024
 515#define PIPE_VBLANK_INTERRUPT_STATUS		(1UL << 1)
 516#define PIPE_START_VBLANK_INTERRUPT_STATUS	(1UL << 2)
 517#define PIPE_VBLANK_CLEAR			(1 << 1)
 518#define PIPE_VBLANK_STATUS			(1 << 1)
 519#define PIPE_TE_STATUS				(1UL << 6)
 520#define PIPE_DPST_EVENT_STATUS			(1UL << 7)
 521#define PIPE_VSYNC_CLEAR			(1UL << 9)
 522#define PIPE_VSYNC_STATUS			(1UL << 9)
 523#define PIPE_HDMI_AUDIO_UNDERRUN_STATUS		(1UL << 10)
 524#define PIPE_HDMI_AUDIO_BUFFER_DONE_STATUS	(1UL << 11)
 525#define PIPE_VBLANK_INTERRUPT_ENABLE		(1UL << 17)
 526#define PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL << 18)
 527#define PIPE_TE_ENABLE				(1UL << 22)
 528#define PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL << 22)
 529#define PIPE_DPST_EVENT_ENABLE			(1UL << 23)
 530#define PIPE_VSYNC_ENABL			(1UL << 25)
 531#define PIPE_HDMI_AUDIO_UNDERRUN		(1UL << 26)
 532#define PIPE_HDMI_AUDIO_BUFFER_DONE		(1UL << 27)
 533#define PIPE_FIFO_UNDERRUN			(1UL << 31)
 534#define PIPE_HDMI_AUDIO_INT_MASK		(PIPE_HDMI_AUDIO_UNDERRUN | \
 535						PIPE_HDMI_AUDIO_BUFFER_DONE)
 536#define PIPE_EVENT_MASK ((1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)|(1 << 22)|(1 << 21)|(1 << 20)|(1 << 16))
 537#define PIPE_VBLANK_MASK ((1 << 25)|(1 << 24)|(1 << 18)|(1 << 17))
 538#define HISTOGRAM_INT_CONTROL		0x61268
 539#define HISTOGRAM_BIN_DATA		0X61264
 540#define HISTOGRAM_LOGIC_CONTROL		0x61260
 541#define PWM_CONTROL_LOGIC		0x61250
 542#define PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL << 10)
 543#define HISTOGRAM_INTERRUPT_ENABLE		(1UL << 31)
 544#define HISTOGRAM_LOGIC_ENABLE			(1UL << 31)
 545#define PWM_LOGIC_ENABLE			(1UL << 31)
 546#define PWM_PHASEIN_ENABLE			(1UL << 25)
 547#define PWM_PHASEIN_INT_ENABLE			(1UL << 24)
 548#define PWM_PHASEIN_VB_COUNT			0x00001f00
 549#define PWM_PHASEIN_INC				0x0000001f
 550#define HISTOGRAM_INT_CTRL_CLEAR		(1UL << 30)
 551#define DPST_YUV_LUMA_MODE			0
 552
 553#define PIPEAFRAMEHIGH		0x70040
 554#define PIPEAFRAMEPIXEL		0x70044
 555#define PIPEBFRAMEHIGH		0x71040
 556#define PIPEBFRAMEPIXEL		0x71044
 557#define PIPECFRAMEHIGH		0x72040
 558#define PIPECFRAMEPIXEL		0x72044
 559#define PIPE_FRAME_HIGH_MASK	0x0000ffff
 560#define PIPE_FRAME_HIGH_SHIFT	0
 561#define PIPE_FRAME_LOW_MASK	0xff000000
 562#define PIPE_FRAME_LOW_SHIFT	24
 563#define PIPE_PIXEL_MASK		0x00ffffff
 564#define PIPE_PIXEL_SHIFT	0
 565
 566#define FW_BLC_SELF		0x20e0
 567#define FW_BLC_SELF_EN          (1<<15)
 568
 569#define DSPARB			0x70030
 570#define DSPFW1			0x70034
 571#define DSP_FIFO_SR_WM_MASK		0xFF800000
 572#define DSP_FIFO_SR_WM_SHIFT		23
 573#define CURSOR_B_FIFO_WM_MASK		0x003F0000
 574#define CURSOR_B_FIFO_WM_SHIFT		16
 575#define DSPFW2			0x70038
 576#define CURSOR_A_FIFO_WM_MASK		0x3F00
 577#define CURSOR_A_FIFO_WM_SHIFT		8
 578#define DSP_PLANE_C_FIFO_WM_MASK	0x7F
 579#define DSP_PLANE_C_FIFO_WM_SHIFT	0
 580#define DSPFW3			0x7003c
 581#define DSPFW4			0x70050
 582#define DSPFW5			0x70054
 583#define DSP_PLANE_B_FIFO_WM1_SHIFT	24
 584#define DSP_PLANE_A_FIFO_WM1_SHIFT	16
 585#define CURSOR_B_FIFO_WM1_SHIFT		8
 586#define CURSOR_FIFO_SR_WM1_SHIFT	0
 587#define DSPFW6			0x70058
 588#define DSPCHICKENBIT		0x70400
 589#define DSPACNTR		0x70180
 590#define DSPBCNTR		0x71180
 591#define DSPCCNTR		0x72180
 592#define DISPLAY_PLANE_ENABLE			(1 << 31)
 593#define DISPLAY_PLANE_DISABLE			0
 594#define DISPPLANE_GAMMA_ENABLE			(1 << 30)
 595#define DISPPLANE_GAMMA_DISABLE			0
 596#define DISPPLANE_PIXFORMAT_MASK		(0xf << 26)
 597#define DISPPLANE_8BPP				(0x2 << 26)
 598#define DISPPLANE_15_16BPP			(0x4 << 26)
 599#define DISPPLANE_16BPP				(0x5 << 26)
 600#define DISPPLANE_32BPP_NO_ALPHA		(0x6 << 26)
 601#define DISPPLANE_32BPP				(0x7 << 26)
 602#define DISPPLANE_STEREO_ENABLE			(1 << 25)
 603#define DISPPLANE_STEREO_DISABLE		0
 604#define DISPPLANE_SEL_PIPE_MASK			(1 << 24)
 605#define DISPPLANE_SEL_PIPE_POS			24
 606#define DISPPLANE_SEL_PIPE_A			0
 607#define DISPPLANE_SEL_PIPE_B			(1 << 24)
 608#define DISPPLANE_SRC_KEY_ENABLE		(1 << 22)
 609#define DISPPLANE_SRC_KEY_DISABLE		0
 610#define DISPPLANE_LINE_DOUBLE			(1 << 20)
 611#define DISPPLANE_NO_LINE_DOUBLE		0
 612#define DISPPLANE_STEREO_POLARITY_FIRST		0
 613#define DISPPLANE_STEREO_POLARITY_SECOND	(1 << 18)
 614/* plane B only */
 615#define DISPPLANE_ALPHA_TRANS_ENABLE		(1 << 15)
 616#define DISPPLANE_ALPHA_TRANS_DISABLE		0
 617#define DISPPLANE_SPRITE_ABOVE_DISPLAYA		0
 618#define DISPPLANE_SPRITE_ABOVE_OVERLAY		(1)
 619#define DISPPLANE_BOTTOM			(4)
 620
 621#define DSPABASE		0x70184
 622#define DSPALINOFF		0x70184
 623#define DSPASTRIDE		0x70188
 624
 625#define DSPBBASE		0x71184
 626#define DSPBLINOFF		0X71184
 627#define DSPBADDR		DSPBBASE
 628#define DSPBSTRIDE		0x71188
 629
 630#define DSPCBASE		0x72184
 631#define DSPCLINOFF		0x72184
 632#define DSPCSTRIDE		0x72188
 633
 634#define DSPAKEYVAL		0x70194
 635#define DSPAKEYMASK		0x70198
 636
 637#define DSPAPOS			0x7018C	/* reserved */
 638#define DSPASIZE		0x70190
 639#define DSPBPOS			0x7118C
 640#define DSPBSIZE		0x71190
 641#define DSPCPOS			0x7218C
 642#define DSPCSIZE		0x72190
 643
 644#define DSPASURF		0x7019C
 645#define DSPATILEOFF		0x701A4
 646
 647#define DSPBSURF		0x7119C
 648#define DSPBTILEOFF		0x711A4
 649
 650#define DSPCSURF		0x7219C
 651#define DSPCTILEOFF		0x721A4
 652#define DSPCKEYMAXVAL		0x721A0
 653#define DSPCKEYMINVAL		0x72194
 654#define DSPCKEYMSK		0x72198
 655
 656#define VGACNTRL		0x71400
 657#define VGA_DISP_DISABLE		(1 << 31)
 658#define VGA_2X_MODE			(1 << 30)
 659#define VGA_PIPE_B_SELECT		(1 << 29)
 660
 661/*
 662 * Overlay registers
 663 */
 664#define OV_C_OFFSET		0x08000
 665#define OV_OVADD		0x30000
 666#define OV_DOVASTA		0x30008
 667# define OV_PIPE_SELECT			((1 << 6)|(1 << 7))
 668# define OV_PIPE_SELECT_POS		6
 669# define OV_PIPE_A			0
 670# define OV_PIPE_C			1
 671#define OV_OGAMC5		0x30010
 672#define OV_OGAMC4		0x30014
 673#define OV_OGAMC3		0x30018
 674#define OV_OGAMC2		0x3001C
 675#define OV_OGAMC1		0x30020
 676#define OV_OGAMC0		0x30024
 677#define OVC_OVADD		0x38000
 678#define OVC_DOVCSTA		0x38008
 679#define OVC_OGAMC5		0x38010
 680#define OVC_OGAMC4		0x38014
 681#define OVC_OGAMC3		0x38018
 682#define OVC_OGAMC2		0x3801C
 683#define OVC_OGAMC1		0x38020
 684#define OVC_OGAMC0		0x38024
 685
 686/*
 687 * Some BIOS scratch area registers.  The 845 (and 830?) store the amount
 688 * of video memory available to the BIOS in SWF1.
 689 */
 690#define SWF0			0x71410
 691#define SWF1			0x71414
 692#define SWF2			0x71418
 693#define SWF3			0x7141c
 694#define SWF4			0x71420
 695#define SWF5			0x71424
 696#define SWF6			0x71428
 697
 698/*
 699 * 855 scratch registers.
 700 */
 701#define SWF00			0x70410
 702#define SWF01			0x70414
 703#define SWF02			0x70418
 704#define SWF03			0x7041c
 705#define SWF04			0x70420
 706#define SWF05			0x70424
 707#define SWF06			0x70428
 708
 709#define SWF10			SWF0
 710#define SWF11			SWF1
 711#define SWF12			SWF2
 712#define SWF13			SWF3
 713#define SWF14			SWF4
 714#define SWF15			SWF5
 715#define SWF16			SWF6
 716
 717#define SWF30			0x72414
 718#define SWF31			0x72418
 719#define SWF32			0x7241c
 720
 721
 722/*
 723 * Palette registers
 724 */
 725#define PALETTE_A		0x0a000
 726#define PALETTE_B		0x0a800
 727#define PALETTE_C		0x0ac00
 728
 729/* Cursor A & B regs */
 730#define CURACNTR		0x70080
 731#define CURSOR_MODE_DISABLE		0x00
 732#define CURSOR_MODE_64_32B_AX		0x07
 733#define CURSOR_MODE_64_ARGB_AX		((1 << 5) | CURSOR_MODE_64_32B_AX)
 734#define MCURSOR_GAMMA_ENABLE		(1 << 26)
 735#define CURABASE		0x70084
 736#define CURAPOS			0x70088
 737#define CURSOR_POS_MASK			0x007FF
 738#define CURSOR_POS_SIGN			0x8000
 739#define CURSOR_X_SHIFT			0
 740#define CURSOR_Y_SHIFT			16
 741#define CURBCNTR		0x700c0
 742#define CURBBASE		0x700c4
 743#define CURBPOS			0x700c8
 744#define CURCCNTR		0x700e0
 745#define CURCBASE		0x700e4
 746#define CURCPOS			0x700e8
 747
 748/*
 749 * Interrupt Registers
 750 */
 751#define IER			0x020a0
 752#define IIR			0x020a4
 753#define IMR			0x020a8
 754#define ISR			0x020ac
 755
 756/*
 757 * MOORESTOWN delta registers
 758 */
 759#define MRST_DPLL_A		0x0f014
 760#define DPLLA_MODE_LVDS			(2 << 26)	/* mrst */
 761#define MRST_FPA0		0x0f040
 762#define MRST_FPA1		0x0f044
 763#define MRST_PERF_MODE		0x020f4
 764
 765/*
 766 * MEDFIELD HDMI registers
 767 */
 768#define HDMIPHYMISCCTL		0x61134
 769#define HDMI_PHY_POWER_DOWN		0x7f
 770#define HDMIB_CONTROL		0x61140
 771#define HDMIB_PORT_EN			(1 << 31)
 772#define HDMIB_PIPE_B_SELECT		(1 << 30)
 773#define HDMIB_NULL_PACKET		(1 << 9)
 774#define HDMIB_HDCP_PORT			(1 << 5)
 775
 776/* #define LVDS			0x61180 */
 777#define MRST_PANEL_8TO6_DITHER_ENABLE	(1 << 25)
 778#define MRST_PANEL_24_DOT_1_FORMAT	(1 << 24)
 779#define LVDS_A3_POWER_UP_0_OUTPUT	(1 << 6)
 780
 781#define MIPI			0x61190
 782#define MIPI_C			0x62190
 783#define MIPI_PORT_EN			(1 << 31)
 784/* Turns on border drawing to allow centered display. */
 785#define SEL_FLOPPED_HSTX		(1 << 23)
 786#define PASS_FROM_SPHY_TO_AFE		(1 << 16)
 787#define MIPI_BORDER_EN			(1 << 15)
 788#define MIPIA_3LANE_MIPIC_1LANE		0x1
 789#define MIPIA_2LANE_MIPIC_2LANE		0x2
 790#define TE_TRIGGER_DSI_PROTOCOL		(1 << 2)
 791#define TE_TRIGGER_GPIO_PIN		(1 << 3)
 792#define MIPI_TE_COUNT		0x61194
 793
 794/* #define PP_CONTROL	0x61204 */
 795#define POWER_DOWN_ON_RESET		(1 << 1)
 796
 797/* #define PFIT_CONTROL	0x61230 */
 798#define PFIT_PIPE_SELECT		(3 << 29)
 799#define PFIT_PIPE_SELECT_SHIFT		(29)
 800
 801/* #define BLC_PWM_CTL		0x61254 */
 802#define MRST_BACKLIGHT_MODULATION_FREQ_SHIFT	(16)
 803#define MRST_BACKLIGHT_MODULATION_FREQ_MASK	(0xffff << 16)
 804
 805/* #define PIPEACONF 0x70008 */
 806#define PIPEACONF_PIPE_STATE		(1 << 30)
 807/* #define DSPACNTR		0x70180 */
 808
 809#define MRST_DSPABASE		0x7019c
 810#define MRST_DSPBBASE		0x7119c
 811
 812/*
 813 * Moorestown registers.
 814 */
 815
 816/*
 817 *	MIPI IP registers
 818 */
 819#define MIPIC_REG_OFFSET		0x800
 820
 821#define DEVICE_READY_REG		0xb000
 822#define LP_OUTPUT_HOLD				(1 << 16)
 823#define EXIT_ULPS_DEV_READY			0x3
 824#define LP_OUTPUT_HOLD_RELEASE			0x810000
 825# define ENTERING_ULPS				(2 << 1)
 826# define EXITING_ULPS				(1 << 1)
 827# define ULPS_MASK				(3 << 1)
 828# define BUS_POSSESSION				(1 << 3)
 829#define INTR_STAT_REG			0xb004
 830#define RX_SOT_ERROR				(1 << 0)
 831#define RX_SOT_SYNC_ERROR			(1 << 1)
 832#define RX_ESCAPE_MODE_ENTRY_ERROR		(1 << 3)
 833#define RX_LP_TX_SYNC_ERROR			(1 << 4)
 834#define RX_HS_RECEIVE_TIMEOUT_ERROR		(1 << 5)
 835#define RX_FALSE_CONTROL_ERROR			(1 << 6)
 836#define RX_ECC_SINGLE_BIT_ERROR			(1 << 7)
 837#define RX_ECC_MULTI_BIT_ERROR			(1 << 8)
 838#define RX_CHECKSUM_ERROR			(1 << 9)
 839#define RX_DSI_DATA_TYPE_NOT_RECOGNIZED		(1 << 10)
 840#define RX_DSI_VC_ID_INVALID			(1 << 11)
 841#define TX_FALSE_CONTROL_ERROR			(1 << 12)
 842#define TX_ECC_SINGLE_BIT_ERROR			(1 << 13)
 843#define TX_ECC_MULTI_BIT_ERROR			(1 << 14)
 844#define TX_CHECKSUM_ERROR			(1 << 15)
 845#define TX_DSI_DATA_TYPE_NOT_RECOGNIZED		(1 << 16)
 846#define TX_DSI_VC_ID_INVALID			(1 << 17)
 847#define HIGH_CONTENTION				(1 << 18)
 848#define LOW_CONTENTION				(1 << 19)
 849#define DPI_FIFO_UNDER_RUN			(1 << 20)
 850#define HS_TX_TIMEOUT				(1 << 21)
 851#define LP_RX_TIMEOUT				(1 << 22)
 852#define TURN_AROUND_ACK_TIMEOUT			(1 << 23)
 853#define ACK_WITH_NO_ERROR			(1 << 24)
 854#define HS_GENERIC_WR_FIFO_FULL			(1 << 27)
 855#define LP_GENERIC_WR_FIFO_FULL			(1 << 28)
 856#define SPL_PKT_SENT				(1 << 30)
 857#define INTR_EN_REG			0xb008
 858#define DSI_FUNC_PRG_REG		0xb00c
 859#define DPI_CHANNEL_NUMBER_POS			0x03
 860#define DBI_CHANNEL_NUMBER_POS			0x05
 861#define FMT_DPI_POS				0x07
 862#define FMT_DBI_POS				0x0A
 863#define DBI_DATA_WIDTH_POS			0x0D
 864
 865/* DPI PIXEL FORMATS */
 866#define RGB_565_FMT				0x01	/* RGB 565 FORMAT */
 867#define RGB_666_FMT				0x02	/* RGB 666 FORMAT */
 868#define LRGB_666_FMT				0x03	/* RGB LOOSELY PACKED
 869							 * 666 FORMAT
 870							 */
 871#define RGB_888_FMT				0x04	/* RGB 888 FORMAT */
 872#define VIRTUAL_CHANNEL_NUMBER_0		0x00	/* Virtual channel 0 */
 873#define VIRTUAL_CHANNEL_NUMBER_1		0x01	/* Virtual channel 1 */
 874#define VIRTUAL_CHANNEL_NUMBER_2		0x02	/* Virtual channel 2 */
 875#define VIRTUAL_CHANNEL_NUMBER_3		0x03	/* Virtual channel 3 */
 876
 877#define DBI_NOT_SUPPORTED			0x00	/* command mode
 878							 * is not supported
 879							 */
 880#define DBI_DATA_WIDTH_16BIT			0x01	/* 16 bit data */
 881#define DBI_DATA_WIDTH_9BIT			0x02	/* 9 bit data */
 882#define DBI_DATA_WIDTH_8BIT			0x03	/* 8 bit data */
 883#define DBI_DATA_WIDTH_OPT1			0x04	/* option 1 */
 884#define DBI_DATA_WIDTH_OPT2			0x05	/* option 2 */
 885
 886#define HS_TX_TIMEOUT_REG		0xb010
 887#define LP_RX_TIMEOUT_REG		0xb014
 888#define TURN_AROUND_TIMEOUT_REG		0xb018
 889#define DEVICE_RESET_REG		0xb01C
 890#define DPI_RESOLUTION_REG		0xb020
 891#define RES_V_POS				0x10
 892#define HORIZ_SYNC_PAD_COUNT_REG	0xb028
 893#define HORIZ_BACK_PORCH_COUNT_REG	0xb02C
 894#define HORIZ_FRONT_PORCH_COUNT_REG	0xb030
 895#define HORIZ_ACTIVE_AREA_COUNT_REG	0xb034
 896#define VERT_SYNC_PAD_COUNT_REG		0xb038
 897#define VERT_BACK_PORCH_COUNT_REG	0xb03c
 898#define VERT_FRONT_PORCH_COUNT_REG	0xb040
 899#define HIGH_LOW_SWITCH_COUNT_REG	0xb044
 900#define DPI_CONTROL_REG			0xb048
 901#define DPI_SHUT_DOWN				(1 << 0)
 902#define DPI_TURN_ON				(1 << 1)
 903#define DPI_COLOR_MODE_ON			(1 << 2)
 904#define DPI_COLOR_MODE_OFF			(1 << 3)
 905#define DPI_BACK_LIGHT_ON			(1 << 4)
 906#define DPI_BACK_LIGHT_OFF			(1 << 5)
 907#define DPI_LP					(1 << 6)
 908#define DPI_DATA_REG			0xb04c
 909#define DPI_BACK_LIGHT_ON_DATA			0x07
 910#define DPI_BACK_LIGHT_OFF_DATA			0x17
 911#define INIT_COUNT_REG			0xb050
 912#define MAX_RET_PAK_REG			0xb054
 913#define VIDEO_FMT_REG			0xb058
 914#define COMPLETE_LAST_PCKT			(1 << 2)
 915#define EOT_DISABLE_REG			0xb05c
 916#define ENABLE_CLOCK_STOPPING			(1 << 1)
 917#define LP_BYTECLK_REG			0xb060
 918#define LP_GEN_DATA_REG			0xb064
 919#define HS_GEN_DATA_REG			0xb068
 920#define LP_GEN_CTRL_REG			0xb06C
 921#define HS_GEN_CTRL_REG			0xb070
 922#define DCS_CHANNEL_NUMBER_POS		0x6
 923#define MCS_COMMANDS_POS		0x8
 924#define WORD_COUNTS_POS			0x8
 925#define MCS_PARAMETER_POS			0x10
 926#define GEN_FIFO_STAT_REG		0xb074
 927#define HS_DATA_FIFO_FULL			(1 << 0)
 928#define HS_DATA_FIFO_HALF_EMPTY			(1 << 1)
 929#define HS_DATA_FIFO_EMPTY			(1 << 2)
 930#define LP_DATA_FIFO_FULL			(1 << 8)
 931#define LP_DATA_FIFO_HALF_EMPTY			(1 << 9)
 932#define LP_DATA_FIFO_EMPTY			(1 << 10)
 933#define HS_CTRL_FIFO_FULL			(1 << 16)
 934#define HS_CTRL_FIFO_HALF_EMPTY			(1 << 17)
 935#define HS_CTRL_FIFO_EMPTY			(1 << 18)
 936#define LP_CTRL_FIFO_FULL			(1 << 24)
 937#define LP_CTRL_FIFO_HALF_EMPTY			(1 << 25)
 938#define LP_CTRL_FIFO_EMPTY			(1 << 26)
 939#define DBI_FIFO_EMPTY				(1 << 27)
 940#define DPI_FIFO_EMPTY				(1 << 28)
 941#define HS_LS_DBI_ENABLE_REG		0xb078
 942#define TXCLKESC_REG			0xb07c
 943#define DPHY_PARAM_REG			0xb080
 944#define DBI_BW_CTRL_REG			0xb084
 945#define CLK_LANE_SWT_REG		0xb088
 946
 947/*
 948 * MIPI Adapter registers
 949 */
 950#define MIPI_CONTROL_REG		0xb104
 951#define MIPI_2X_CLOCK_BITS			((1 << 0) | (1 << 1))
 952#define MIPI_DATA_ADDRESS_REG		0xb108
 953#define MIPI_DATA_LENGTH_REG		0xb10C
 954#define MIPI_COMMAND_ADDRESS_REG	0xb110
 955#define MIPI_COMMAND_LENGTH_REG		0xb114
 956#define MIPI_READ_DATA_RETURN_REG0	0xb118
 957#define MIPI_READ_DATA_RETURN_REG1	0xb11C
 958#define MIPI_READ_DATA_RETURN_REG2	0xb120
 959#define MIPI_READ_DATA_RETURN_REG3	0xb124
 960#define MIPI_READ_DATA_RETURN_REG4	0xb128
 961#define MIPI_READ_DATA_RETURN_REG5	0xb12C
 962#define MIPI_READ_DATA_RETURN_REG6	0xb130
 963#define MIPI_READ_DATA_RETURN_REG7	0xb134
 964#define MIPI_READ_DATA_VALID_REG	0xb138
 965
 966/* DBI COMMANDS */
 967#define soft_reset			0x01
 968/*
 969 *	The display module performs a software reset.
 970 *	Registers are written with their SW Reset default values.
 971 */
 972#define get_power_mode			0x0a
 973/*
 974 *	The display module returns the current power mode
 975 */
 976#define get_address_mode		0x0b
 977/*
 978 *	The display module returns the current status.
 979 */
 980#define get_pixel_format		0x0c
 981/*
 982 *	This command gets the pixel format for the RGB image data
 983 *	used by the interface.
 984 */
 985#define get_display_mode		0x0d
 986/*
 987 *	The display module returns the Display Image Mode status.
 988 */
 989#define get_signal_mode			0x0e
 990/*
 991 *	The display module returns the Display Signal Mode.
 992 */
 993#define get_diagnostic_result		0x0f
 994/*
 995 *	The display module returns the self-diagnostic results following
 996 *	a Sleep Out command.
 997 */
 998#define enter_sleep_mode		0x10
 999/*
1000 *	This command causes the display module to enter the Sleep mode.
1001 *	In this mode, all unnecessary blocks inside the display module are
1002 *	disabled except interface communication. This is the lowest power
1003 *	mode the display module supports.
1004 */
1005#define exit_sleep_mode			0x11
1006/*
1007 *	This command causes the display module to exit Sleep mode.
1008 *	All blocks inside the display module are enabled.
1009 */
1010#define enter_partial_mode		0x12
1011/*
1012 *	This command causes the display module to enter the Partial Display
1013 *	Mode. The Partial Display Mode window is described by the
1014 *	set_partial_area command.
1015 */
1016#define enter_normal_mode		0x13
1017/*
1018 *	This command causes the display module to enter the Normal mode.
1019 *	Normal Mode is defined as Partial Display mode and Scroll mode are off
1020 */
1021#define exit_invert_mode		0x20
1022/*
1023 *	This command causes the display module to stop inverting the image
1024 *	data on the display device. The frame memory contents remain unchanged.
1025 *	No status bits are changed.
1026 */
1027#define enter_invert_mode		0x21
1028/*
1029 *	This command causes the display module to invert the image data only on
1030 *	the display device. The frame memory contents remain unchanged.
1031 *	No status bits are changed.
1032 */
1033#define set_gamma_curve			0x26
1034/*
1035 *	This command selects the desired gamma curve for the display device.
1036 *	Four fixed gamma curves are defined in section DCS spec.
1037 */
1038#define set_display_off			0x28
1039/* ************************************************************************* *\
1040This command causes the display module to stop displaying the image data
1041on the display device. The frame memory contents remain unchanged.
1042No status bits are changed.
1043\* ************************************************************************* */
1044#define set_display_on			0x29
1045/* ************************************************************************* *\
1046This command causes the display module to start displaying the image data
1047on the display device. The frame memory contents remain unchanged.
1048No status bits are changed.
1049\* ************************************************************************* */
1050#define set_column_address		0x2a
1051/*
1052 *	This command defines the column extent of the frame memory accessed by
1053 *	the hostprocessor with the read_memory_continue and
1054 *	write_memory_continue commands.
1055 *	No status bits are changed.
1056 */
1057#define set_page_addr			0x2b
1058/*
1059 *	This command defines the page extent of the frame memory accessed by
1060 *	the host processor with the write_memory_continue and
1061 *	read_memory_continue command.
1062 *	No status bits are changed.
1063 */
1064#define write_mem_start			0x2c
1065/*
1066 *	This command transfers image data from the host processor to the
1067 *	display modules frame memory starting at the pixel location specified
1068 *	by preceding set_column_address and set_page_address commands.
1069 */
1070#define set_partial_area		0x30
1071/*
1072 *	This command defines the Partial Display mode s display area.
1073 *	There are two parameters associated with this command, the first
1074 *	defines the Start Row (SR) and the second the End Row (ER). SR and ER
1075 *	refer to the Frame Memory Line Pointer.
1076 */
1077#define set_scroll_area			0x33
1078/*
1079 *	This command defines the display modules Vertical Scrolling Area.
1080 */
1081#define set_tear_off			0x34
1082/*
1083 *	This command turns off the display modules Tearing Effect output
1084 *	signal on the TE signal line.
1085 */
1086#define set_tear_on			0x35
1087/*
1088 *	This command turns on the display modules Tearing Effect output signal
1089 *	on the TE signal line.
1090 */
1091#define set_address_mode		0x36
1092/*
1093 *	This command sets the data order for transfers from the host processor
1094 *	to display modules frame memory,bits B[7:5] and B3, and from the
1095 *	display modules frame memory to the display device, bits B[2:0] and B4.
1096 */
1097#define set_scroll_start		0x37
1098/*
1099 *	This command sets the start of the vertical scrolling area in the frame
1100 *	memory. The vertical scrolling area is fully defined when this command
1101 *	is used with the set_scroll_area command The set_scroll_start command
1102 *	has one parameter, the Vertical Scroll Pointer. The VSP defines the
1103 *	line in the frame memory that is written to the display device as the
1104 *	first line of the vertical scroll area.
1105 */
1106#define exit_idle_mode			0x38
1107/*
1108 *	This command causes the display module to exit Idle mode.
1109 */
1110#define enter_idle_mode			0x39
1111/*
1112 *	This command causes the display module to enter Idle Mode.
1113 *	In Idle Mode, color expression is reduced. Colors are shown on the
1114 *	display device using the MSB of each of the R, G and B color
1115 *	components in the frame memory
1116 */
1117#define set_pixel_format		0x3a
1118/*
1119 *	This command sets the pixel format for the RGB image data used by the
1120 *	interface.
1121 *	Bits D[6:4]  DPI Pixel Format Definition
1122 *	Bits D[2:0]  DBI Pixel Format Definition
1123 *	Bits D7 and D3 are not used.
1124 */
1125#define DCS_PIXEL_FORMAT_3bpp		0x1
1126#define DCS_PIXEL_FORMAT_8bpp		0x2
1127#define DCS_PIXEL_FORMAT_12bpp		0x3
1128#define DCS_PIXEL_FORMAT_16bpp		0x5
1129#define DCS_PIXEL_FORMAT_18bpp		0x6
1130#define DCS_PIXEL_FORMAT_24bpp		0x7
1131
1132#define write_mem_cont			0x3c
1133
1134/*
1135 *	This command transfers image data from the host processor to the
1136 *	display module's frame memory continuing from the pixel location
1137 *	following the previous write_memory_continue or write_memory_start
1138 *	command.
1139 */
1140#define set_tear_scanline		0x44
1141/*
1142 *	This command turns on the display modules Tearing Effect output signal
1143 *	on the TE signal line when the display module reaches line N.
1144 */
1145#define get_scanline			0x45
1146/*
1147 *	The display module returns the current scanline, N, used to update the
1148 *	 display device. The total number of scanlines on a display device is
1149 *	defined as VSYNC + VBP + VACT + VFP.The first scanline is defined as
1150 *	the first line of V Sync and is denoted as Line 0.
1151 *	When in Sleep Mode, the value returned by get_scanline is undefined.
1152 */
1153
1154/* MCS or Generic COMMANDS */
1155/* MCS/generic data type */
1156#define GEN_SHORT_WRITE_0	0x03  /* generic short write, no parameters */
1157#define GEN_SHORT_WRITE_1	0x13  /* generic short write, 1 parameters */
1158#define GEN_SHORT_WRITE_2	0x23  /* generic short write, 2 parameters */
1159#define GEN_READ_0		0x04  /* generic read, no parameters */
1160#define GEN_READ_1		0x14  /* generic read, 1 parameters */
1161#define GEN_READ_2		0x24  /* generic read, 2 parameters */
1162#define GEN_LONG_WRITE		0x29  /* generic long write */
1163#define MCS_SHORT_WRITE_0	0x05  /* MCS short write, no parameters */
1164#define MCS_SHORT_WRITE_1	0x15  /* MCS short write, 1 parameters */
1165#define MCS_READ		0x06  /* MCS read, no parameters */
1166#define MCS_LONG_WRITE		0x39  /* MCS long write */
1167/* MCS/generic commands */
1168/* TPO MCS */
1169#define write_display_profile		0x50
1170#define write_display_brightness	0x51
1171#define write_ctrl_display		0x53
1172#define write_ctrl_cabc			0x55
1173  #define UI_IMAGE		0x01
1174  #define STILL_IMAGE		0x02
1175  #define MOVING_IMAGE		0x03
1176#define write_hysteresis		0x57
1177#define write_gamma_setting		0x58
1178#define write_cabc_min_bright		0x5e
1179#define write_kbbc_profile		0x60
1180/* TMD MCS */
1181#define tmd_write_display_brightness 0x8c
1182
1183/*
1184 *	This command is used to control ambient light, panel backlight
1185 *	brightness and gamma settings.
1186 */
1187#define BRIGHT_CNTL_BLOCK_ON	(1 << 5)
1188#define AMBIENT_LIGHT_SENSE_ON	(1 << 4)
1189#define DISPLAY_DIMMING_ON	(1 << 3)
1190#define BACKLIGHT_ON		(1 << 2)
1191#define DISPLAY_BRIGHTNESS_AUTO	(1 << 1)
1192#define GAMMA_AUTO		(1 << 0)
1193
1194/* DCS Interface Pixel Formats */
1195#define DCS_PIXEL_FORMAT_3BPP	0x1
1196#define DCS_PIXEL_FORMAT_8BPP	0x2
1197#define DCS_PIXEL_FORMAT_12BPP	0x3
1198#define DCS_PIXEL_FORMAT_16BPP	0x5
1199#define DCS_PIXEL_FORMAT_18BPP	0x6
1200#define DCS_PIXEL_FORMAT_24BPP	0x7
1201/* ONE PARAMETER READ DATA */
1202#define addr_mode_data		0xfc
1203#define diag_res_data		0x00
1204#define disp_mode_data		0x23
1205#define pxl_fmt_data		0x77
1206#define pwr_mode_data		0x74
1207#define sig_mode_data		0x00
1208/* TWO PARAMETERS READ DATA */
1209#define scanline_data1		0xff
1210#define scanline_data2		0xff
1211#define NON_BURST_MODE_SYNC_PULSE	0x01	/* Non Burst Mode
1212						 * with Sync Pulse
1213						 */
1214#define NON_BURST_MODE_SYNC_EVENTS	0x02	/* Non Burst Mode
1215						 * with Sync events
1216						 */
1217#define BURST_MODE			0x03	/* Burst Mode */
1218#define DBI_COMMAND_BUFFER_SIZE		0x240   /* 0x32 */    /* 0x120 */
1219						/* Allocate at least
1220						 * 0x100 Byte with 32
1221						 * byte alignment
1222						 */
1223#define DBI_DATA_BUFFER_SIZE		0x120	/* Allocate at least
1224						 * 0x100 Byte with 32
1225						 * byte alignment
1226						 */
1227#define DBI_CB_TIME_OUT			0xFFFF
1228
1229#define GEN_FB_TIME_OUT			2000
1230
1231#define SKU_83				0x01
1232#define SKU_100				0x02
1233#define SKU_100L			0x04
1234#define SKU_BYPASS			0x08
1235
1236/* Some handy macros for playing with bitfields. */
1237#define PSB_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low))
1238#define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK)
1239#define GET_FIELD(word, field) (((word)  & field ## _MASK) >> field ## _SHIFT)
1240
1241#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
1242
1243/* PCI config space */
1244
1245#define SB_PCKT         0x02100 /* cedarview */
1246# define SB_OPCODE_MASK                         PSB_MASK(31, 16)
1247# define SB_OPCODE_SHIFT                        16
1248# define SB_OPCODE_READ                         0
1249# define SB_OPCODE_WRITE                        1
1250# define SB_DEST_MASK                           PSB_MASK(15, 8)
1251# define SB_DEST_SHIFT                          8
1252# define SB_DEST_DPLL                           0x88
1253# define SB_BYTE_ENABLE_MASK                    PSB_MASK(7, 4)
1254# define SB_BYTE_ENABLE_SHIFT                   4
1255# define SB_BUSY                                (1 << 0)
1256
1257#define DSPCLK_GATE_D		0x6200
1258# define VRHUNIT_CLOCK_GATE_DISABLE		(1 << 28) /* Fixed value on CDV */
1259# define DPOUNIT_CLOCK_GATE_DISABLE		(1 << 11)
1260# define DPIOUNIT_CLOCK_GATE_DISABLE		(1 << 6)
1261# define DPUNIT_PIPEB_GATE_DISABLE		(1 << 30)
1262# define DPUNIT_PIPEA_GATE_DISABLE		(1 << 25)
1263# define DPCUNIT_CLOCK_GATE_DISABLE		(1 << 24)
1264# define DPLSUNIT_CLOCK_GATE_DISABLE		(1 << 13)
1265
1266#define RAMCLK_GATE_D		0x6210
1267
1268/* 32-bit value read/written from the DPIO reg. */
1269#define SB_DATA		0x02104 /* cedarview */
1270/* 32-bit address of the DPIO reg to be read/written. */
1271#define SB_ADDR		0x02108 /* cedarview */
1272#define DPIO_CFG	0x02110 /* cedarview */
1273# define DPIO_MODE_SELECT_1			(1 << 3)
1274# define DPIO_MODE_SELECT_0			(1 << 2)
1275# define DPIO_SFR_BYPASS			(1 << 1)
1276/* reset is active low */
1277# define DPIO_CMN_RESET_N			(1 << 0)
1278
1279/* Cedarview sideband registers */
1280#define _SB_M_A			0x8008
1281#define _SB_M_B			0x8028
1282#define SB_M(pipe) _PIPE(pipe, _SB_M_A, _SB_M_B)
1283# define SB_M_DIVIDER_MASK			(0xFF << 24)
1284# define SB_M_DIVIDER_SHIFT			24
1285
1286#define _SB_N_VCO_A		0x8014
1287#define _SB_N_VCO_B		0x8034
1288#define SB_N_VCO(pipe) _PIPE(pipe, _SB_N_VCO_A, _SB_N_VCO_B)
1289#define SB_N_VCO_SEL_MASK			PSB_MASK(31, 30)
1290#define SB_N_VCO_SEL_SHIFT			30
1291#define SB_N_DIVIDER_MASK			PSB_MASK(29, 26)
1292#define SB_N_DIVIDER_SHIFT			26
1293#define SB_N_CB_TUNE_MASK			PSB_MASK(25, 24)
1294#define SB_N_CB_TUNE_SHIFT			24
1295
1296/* the bit 14:13 is used to select between the different reference clock for Pipe A/B */
1297#define SB_REF_DPLLA		0x8010
1298#define SB_REF_DPLLB		0x8030
1299#define	REF_CLK_MASK		(0x3 << 13)
1300#define REF_CLK_CORE		(0 << 13)
1301#define REF_CLK_DPLL		(1 << 13)
1302#define REF_CLK_DPLLA		(2 << 13)
1303/* For the DPLL B, it will use the reference clk from DPLL A when using (2 << 13) */
1304
1305#define _SB_REF_A		0x8018
1306#define _SB_REF_B		0x8038
1307#define SB_REF_SFR(pipe)	_PIPE(pipe, _SB_REF_A, _SB_REF_B)
1308
1309#define _SB_P_A			0x801c
1310#define _SB_P_B			0x803c
1311#define SB_P(pipe) _PIPE(pipe, _SB_P_A, _SB_P_B)
1312#define SB_P2_DIVIDER_MASK			PSB_MASK(31, 30)
1313#define SB_P2_DIVIDER_SHIFT			30
1314#define SB_P2_10				0 /* HDMI, DP, DAC */
1315#define SB_P2_5				1 /* DAC */
1316#define SB_P2_14				2 /* LVDS single */
1317#define SB_P2_7				3 /* LVDS double */
1318#define SB_P1_DIVIDER_MASK			PSB_MASK(15, 12)
1319#define SB_P1_DIVIDER_SHIFT			12
1320
1321#define PSB_LANE0		0x120
1322#define PSB_LANE1		0x220
1323#define PSB_LANE2		0x2320
1324#define PSB_LANE3		0x2420
1325
1326#define LANE_PLL_MASK		(0x7 << 20)
1327#define LANE_PLL_ENABLE		(0x3 << 20)
1328#define LANE_PLL_PIPE(p)	(((p) == 0) ? (1 << 21) : (0 << 21))
1329
1330#define DP_B				0x64100
1331#define DP_C				0x64200
1332
1333#define   DP_PORT_EN			(1 << 31)
1334#define   DP_PIPEB_SELECT		(1 << 30)
1335#define   DP_PIPE_MASK			(1 << 30)
1336
1337/* Link training mode - select a suitable mode for each stage */
1338#define   DP_LINK_TRAIN_PAT_1		(0 << 28)
1339#define   DP_LINK_TRAIN_PAT_2		(1 << 28)
1340#define   DP_LINK_TRAIN_PAT_IDLE	(2 << 28)
1341#define   DP_LINK_TRAIN_OFF		(3 << 28)
1342#define   DP_LINK_TRAIN_MASK		(3 << 28)
1343#define   DP_LINK_TRAIN_SHIFT		28
1344
1345/* Signal voltages. These are mostly controlled by the other end */
1346#define   DP_VOLTAGE_0_4		(0 << 25)
1347#define   DP_VOLTAGE_0_6		(1 << 25)
1348#define   DP_VOLTAGE_0_8		(2 << 25)
1349#define   DP_VOLTAGE_1_2		(3 << 25)
1350#define   DP_VOLTAGE_MASK		(7 << 25)
1351#define   DP_VOLTAGE_SHIFT		25
1352
1353/* Signal pre-emphasis levels, like voltages, the other end tells us what
1354 * they want
1355 */
1356#define   DP_PRE_EMPHASIS_0		(0 << 22)
1357#define   DP_PRE_EMPHASIS_3_5		(1 << 22)
1358#define   DP_PRE_EMPHASIS_6		(2 << 22)
1359#define   DP_PRE_EMPHASIS_9_5		(3 << 22)
1360#define   DP_PRE_EMPHASIS_MASK		(7 << 22)
1361#define   DP_PRE_EMPHASIS_SHIFT		22
1362
1363/* How many wires to use. I guess 3 was too hard */
1364#define   DP_PORT_WIDTH_1		(0 << 19)
1365#define   DP_PORT_WIDTH_2		(1 << 19)
1366#define   DP_PORT_WIDTH_4		(3 << 19)
1367#define   DP_PORT_WIDTH_MASK		(7 << 19)
1368
1369/* Mystic DPCD version 1.1 special mode */
1370#define   DP_ENHANCED_FRAMING		(1 << 18)
1371
1372/** locked once port is enabled */
1373#define   DP_PORT_REVERSAL		(1 << 15)
1374
1375/** sends the clock on lane 15 of the PEG for debug */
1376#define   DP_CLOCK_OUTPUT_ENABLE	(1 << 13)
1377
1378#define   DP_SCRAMBLING_DISABLE		(1 << 12)
1379#define   DP_SCRAMBLING_DISABLE_IRONLAKE	(1 << 7)
1380
1381/** limit RGB values to avoid confusing TVs */
1382#define   DP_COLOR_RANGE_16_235		(1 << 8)
1383
1384/** Turn on the audio link */
1385#define   DP_AUDIO_OUTPUT_ENABLE	(1 << 6)
1386
1387/** vs and hs sync polarity */
1388#define   DP_SYNC_VS_HIGH		(1 << 4)
1389#define   DP_SYNC_HS_HIGH		(1 << 3)
1390
1391/** A fantasy */
1392#define   DP_DETECTED			(1 << 2)
1393
1394/** The aux channel provides a way to talk to the
1395 * signal sink for DDC etc. Max packet size supported
1396 * is 20 bytes in each direction, hence the 5 fixed
1397 * data registers
1398 */
1399#define DPB_AUX_CH_CTL			0x64110
1400#define DPB_AUX_CH_DATA1		0x64114
1401#define DPB_AUX_CH_DATA2		0x64118
1402#define DPB_AUX_CH_DATA3		0x6411c
1403#define DPB_AUX_CH_DATA4		0x64120
1404#define DPB_AUX_CH_DATA5		0x64124
1405
1406#define DPC_AUX_CH_CTL			0x64210
1407#define DPC_AUX_CH_DATA1		0x64214
1408#define DPC_AUX_CH_DATA2		0x64218
1409#define DPC_AUX_CH_DATA3		0x6421c
1410#define DPC_AUX_CH_DATA4		0x64220
1411#define DPC_AUX_CH_DATA5		0x64224
1412
1413#define   DP_AUX_CH_CTL_SEND_BUSY	    (1 << 31)
1414#define   DP_AUX_CH_CTL_DONE		    (1 << 30)
1415#define   DP_AUX_CH_CTL_INTERRUPT	    (1 << 29)
1416#define   DP_AUX_CH_CTL_TIME_OUT_ERROR	    (1 << 28)
1417#define   DP_AUX_CH_CTL_TIME_OUT_400us	    (0 << 26)
1418#define   DP_AUX_CH_CTL_TIME_OUT_600us	    (1 << 26)
1419#define   DP_AUX_CH_CTL_TIME_OUT_800us	    (2 << 26)
1420#define   DP_AUX_CH_CTL_TIME_OUT_1600us	    (3 << 26)
1421#define   DP_AUX_CH_CTL_TIME_OUT_MASK	    (3 << 26)
1422#define   DP_AUX_CH_CTL_RECEIVE_ERROR	    (1 << 25)
1423#define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
1424#define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
1425#define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
1426#define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
1427#define   DP_AUX_CH_CTL_AUX_AKSV_SELECT	    (1 << 15)
1428#define   DP_AUX_CH_CTL_MANCHESTER_TEST	    (1 << 14)
1429#define   DP_AUX_CH_CTL_SYNC_TEST	    (1 << 13)
1430#define   DP_AUX_CH_CTL_DEGLITCH_TEST	    (1 << 12)
1431#define   DP_AUX_CH_CTL_PRECHARGE_TEST	    (1 << 11)
1432#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
1433#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
1434
1435/*
1436 * Computing GMCH M and N values for the Display Port link
1437 *
1438 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
1439 *
1440 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
1441 *
1442 * The GMCH value is used internally
1443 *
1444 * bytes_per_pixel is the number of bytes coming out of the plane,
1445 * which is after the LUTs, so we want the bytes for our color format.
1446 * For our current usage, this is always 3, one byte for R, G and B.
1447 */
1448
1449#define _PIPEA_GMCH_DATA_M			0x70050
1450#define _PIPEB_GMCH_DATA_M			0x71050
1451
1452/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1453#define   PIPE_GMCH_DATA_M_TU_SIZE_MASK		(0x3f << 25)
1454#define   PIPE_GMCH_DATA_M_TU_SIZE_SHIFT	25
1455
1456#define   PIPE_GMCH_DATA_M_MASK			(0xffffff)
1457
1458#define _PIPEA_GMCH_DATA_N			0x70054
1459#define _PIPEB_GMCH_DATA_N			0x71054
1460#define   PIPE_GMCH_DATA_N_MASK			(0xffffff)
1461
1462/*
1463 * Computing Link M and N values for the Display Port link
1464 *
1465 * Link M / N = pixel_clock / ls_clk
1466 *
1467 * (the DP spec calls pixel_clock the 'strm_clk')
1468 *
1469 * The Link value is transmitted in the Main Stream
1470 * Attributes and VB-ID.
1471 */
1472
1473#define _PIPEA_DP_LINK_M				0x70060
1474#define _PIPEB_DP_LINK_M				0x71060
1475#define   PIPEA_DP_LINK_M_MASK			(0xffffff)
1476
1477#define _PIPEA_DP_LINK_N				0x70064
1478#define _PIPEB_DP_LINK_N				0x71064
1479#define   PIPEA_DP_LINK_N_MASK			(0xffffff)
1480
1481#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
1482#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
1483#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
1484#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
1485
1486#define   PIPE_BPC_MASK				(7 << 5)
1487#define   PIPE_8BPC				(0 << 5)
1488#define   PIPE_10BPC				(1 << 5)
1489#define   PIPE_6BPC				(2 << 5)
1490
1491#endif