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1/*
2 * Copyright © 2009 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#include <linux/backlight.h>
24#include <linux/delay.h>
25#include <linux/errno.h>
26#include <linux/i2c.h>
27#include <linux/init.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/sched.h>
31#include <linux/seq_file.h>
32#include <linux/string_helpers.h>
33#include <linux/dynamic_debug.h>
34
35#include <drm/display/drm_dp_helper.h>
36#include <drm/display/drm_dp_mst_helper.h>
37#include <drm/drm_edid.h>
38#include <drm/drm_print.h>
39#include <drm/drm_vblank.h>
40#include <drm/drm_panel.h>
41
42#include "drm_dp_helper_internal.h"
43
44DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
45 "DRM_UT_CORE",
46 "DRM_UT_DRIVER",
47 "DRM_UT_KMS",
48 "DRM_UT_PRIME",
49 "DRM_UT_ATOMIC",
50 "DRM_UT_VBL",
51 "DRM_UT_STATE",
52 "DRM_UT_LEASE",
53 "DRM_UT_DP",
54 "DRM_UT_DRMRES");
55
56struct dp_aux_backlight {
57 struct backlight_device *base;
58 struct drm_dp_aux *aux;
59 struct drm_edp_backlight_info info;
60 bool enabled;
61};
62
63/**
64 * DOC: dp helpers
65 *
66 * These functions contain some common logic and helpers at various abstraction
67 * levels to deal with Display Port sink devices and related things like DP aux
68 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
69 * blocks, ...
70 */
71
72/* Helpers for DP link training */
73static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
74{
75 return link_status[r - DP_LANE0_1_STATUS];
76}
77
78static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
79 int lane)
80{
81 int i = DP_LANE0_1_STATUS + (lane >> 1);
82 int s = (lane & 1) * 4;
83 u8 l = dp_link_status(link_status, i);
84
85 return (l >> s) & 0xf;
86}
87
88bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
89 int lane_count)
90{
91 u8 lane_align;
92 u8 lane_status;
93 int lane;
94
95 lane_align = dp_link_status(link_status,
96 DP_LANE_ALIGN_STATUS_UPDATED);
97 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
98 return false;
99 for (lane = 0; lane < lane_count; lane++) {
100 lane_status = dp_get_lane_status(link_status, lane);
101 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
102 return false;
103 }
104 return true;
105}
106EXPORT_SYMBOL(drm_dp_channel_eq_ok);
107
108bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
109 int lane_count)
110{
111 int lane;
112 u8 lane_status;
113
114 for (lane = 0; lane < lane_count; lane++) {
115 lane_status = dp_get_lane_status(link_status, lane);
116 if ((lane_status & DP_LANE_CR_DONE) == 0)
117 return false;
118 }
119 return true;
120}
121EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
122
123u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
124 int lane)
125{
126 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
127 int s = ((lane & 1) ?
128 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
129 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
130 u8 l = dp_link_status(link_status, i);
131
132 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
133}
134EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
135
136u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
137 int lane)
138{
139 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
140 int s = ((lane & 1) ?
141 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
142 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
143 u8 l = dp_link_status(link_status, i);
144
145 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
146}
147EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
148
149/* DP 2.0 128b/132b */
150u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
151 int lane)
152{
153 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
154 int s = ((lane & 1) ?
155 DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT :
156 DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT);
157 u8 l = dp_link_status(link_status, i);
158
159 return (l >> s) & 0xf;
160}
161EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset);
162
163/* DP 2.0 errata for 128b/132b */
164bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
165 int lane_count)
166{
167 u8 lane_align, lane_status;
168 int lane;
169
170 lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
171 if (!(lane_align & DP_INTERLANE_ALIGN_DONE))
172 return false;
173
174 for (lane = 0; lane < lane_count; lane++) {
175 lane_status = dp_get_lane_status(link_status, lane);
176 if (!(lane_status & DP_LANE_CHANNEL_EQ_DONE))
177 return false;
178 }
179 return true;
180}
181EXPORT_SYMBOL(drm_dp_128b132b_lane_channel_eq_done);
182
183/* DP 2.0 errata for 128b/132b */
184bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
185 int lane_count)
186{
187 u8 lane_status;
188 int lane;
189
190 for (lane = 0; lane < lane_count; lane++) {
191 lane_status = dp_get_lane_status(link_status, lane);
192 if (!(lane_status & DP_LANE_SYMBOL_LOCKED))
193 return false;
194 }
195 return true;
196}
197EXPORT_SYMBOL(drm_dp_128b132b_lane_symbol_locked);
198
199/* DP 2.0 errata for 128b/132b */
200bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])
201{
202 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
203
204 return status & DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE;
205}
206EXPORT_SYMBOL(drm_dp_128b132b_eq_interlane_align_done);
207
208/* DP 2.0 errata for 128b/132b */
209bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])
210{
211 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
212
213 return status & DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE;
214}
215EXPORT_SYMBOL(drm_dp_128b132b_cds_interlane_align_done);
216
217/* DP 2.0 errata for 128b/132b */
218bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE])
219{
220 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
221
222 return status & DP_128B132B_LT_FAILED;
223}
224EXPORT_SYMBOL(drm_dp_128b132b_link_training_failed);
225
226static int __8b10b_clock_recovery_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
227{
228 if (rd_interval > 4)
229 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n",
230 aux->name, rd_interval);
231
232 if (rd_interval == 0)
233 return 100;
234
235 return rd_interval * 4 * USEC_PER_MSEC;
236}
237
238static int __8b10b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
239{
240 if (rd_interval > 4)
241 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n",
242 aux->name, rd_interval);
243
244 if (rd_interval == 0)
245 return 400;
246
247 return rd_interval * 4 * USEC_PER_MSEC;
248}
249
250static int __128b132b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
251{
252 switch (rd_interval) {
253 default:
254 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n",
255 aux->name, rd_interval);
256 fallthrough;
257 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US:
258 return 400;
259 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS:
260 return 4000;
261 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS:
262 return 8000;
263 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS:
264 return 12000;
265 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS:
266 return 16000;
267 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS:
268 return 32000;
269 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS:
270 return 64000;
271 }
272}
273
274/*
275 * The link training delays are different for:
276 *
277 * - Clock recovery vs. channel equalization
278 * - DPRX vs. LTTPR
279 * - 128b/132b vs. 8b/10b
280 * - DPCD rev 1.3 vs. later
281 *
282 * Get the correct delay in us, reading DPCD if necessary.
283 */
284static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
285 enum drm_dp_phy dp_phy, bool uhbr, bool cr)
286{
287 int (*parse)(const struct drm_dp_aux *aux, u8 rd_interval);
288 unsigned int offset;
289 u8 rd_interval, mask;
290
291 if (dp_phy == DP_PHY_DPRX) {
292 if (uhbr) {
293 if (cr)
294 return 100;
295
296 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL;
297 mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
298 parse = __128b132b_channel_eq_delay_us;
299 } else {
300 if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
301 return 100;
302
303 offset = DP_TRAINING_AUX_RD_INTERVAL;
304 mask = DP_TRAINING_AUX_RD_MASK;
305 if (cr)
306 parse = __8b10b_clock_recovery_delay_us;
307 else
308 parse = __8b10b_channel_eq_delay_us;
309 }
310 } else {
311 if (uhbr) {
312 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy);
313 mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
314 parse = __128b132b_channel_eq_delay_us;
315 } else {
316 if (cr)
317 return 100;
318
319 offset = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy);
320 mask = DP_TRAINING_AUX_RD_MASK;
321 parse = __8b10b_channel_eq_delay_us;
322 }
323 }
324
325 if (offset < DP_RECEIVER_CAP_SIZE) {
326 rd_interval = dpcd[offset];
327 } else {
328 if (drm_dp_dpcd_readb(aux, offset, &rd_interval) != 1) {
329 drm_dbg_kms(aux->drm_dev, "%s: failed rd interval read\n",
330 aux->name);
331 /* arbitrary default delay */
332 return 400;
333 }
334 }
335
336 return parse(aux, rd_interval & mask);
337}
338
339int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
340 enum drm_dp_phy dp_phy, bool uhbr)
341{
342 return __read_delay(aux, dpcd, dp_phy, uhbr, true);
343}
344EXPORT_SYMBOL(drm_dp_read_clock_recovery_delay);
345
346int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
347 enum drm_dp_phy dp_phy, bool uhbr)
348{
349 return __read_delay(aux, dpcd, dp_phy, uhbr, false);
350}
351EXPORT_SYMBOL(drm_dp_read_channel_eq_delay);
352
353/* Per DP 2.0 Errata */
354int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux)
355{
356 int unit;
357 u8 val;
358
359 if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, &val) != 1) {
360 drm_err(aux->drm_dev, "%s: failed rd interval read\n",
361 aux->name);
362 /* default to max */
363 val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
364 }
365
366 unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2;
367 val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
368
369 return (val + 1) * unit * 1000;
370}
371EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval);
372
373void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
374 const u8 dpcd[DP_RECEIVER_CAP_SIZE])
375{
376 u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
377 DP_TRAINING_AUX_RD_MASK;
378 int delay_us;
379
380 if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
381 delay_us = 100;
382 else
383 delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval);
384
385 usleep_range(delay_us, delay_us * 2);
386}
387EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
388
389static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
390 u8 rd_interval)
391{
392 int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval);
393
394 usleep_range(delay_us, delay_us * 2);
395}
396
397void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
398 const u8 dpcd[DP_RECEIVER_CAP_SIZE])
399{
400 __drm_dp_link_train_channel_eq_delay(aux,
401 dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
402 DP_TRAINING_AUX_RD_MASK);
403}
404EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
405
406/**
407 * drm_dp_phy_name() - Get the name of the given DP PHY
408 * @dp_phy: The DP PHY identifier
409 *
410 * Given the @dp_phy, get a user friendly name of the DP PHY, either "DPRX" or
411 * "LTTPR <N>", or "<INVALID DP PHY>" on errors. The returned string is always
412 * non-NULL and valid.
413 *
414 * Returns: Name of the DP PHY.
415 */
416const char *drm_dp_phy_name(enum drm_dp_phy dp_phy)
417{
418 static const char * const phy_names[] = {
419 [DP_PHY_DPRX] = "DPRX",
420 [DP_PHY_LTTPR1] = "LTTPR 1",
421 [DP_PHY_LTTPR2] = "LTTPR 2",
422 [DP_PHY_LTTPR3] = "LTTPR 3",
423 [DP_PHY_LTTPR4] = "LTTPR 4",
424 [DP_PHY_LTTPR5] = "LTTPR 5",
425 [DP_PHY_LTTPR6] = "LTTPR 6",
426 [DP_PHY_LTTPR7] = "LTTPR 7",
427 [DP_PHY_LTTPR8] = "LTTPR 8",
428 };
429
430 if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names) ||
431 WARN_ON(!phy_names[dp_phy]))
432 return "<INVALID DP PHY>";
433
434 return phy_names[dp_phy];
435}
436EXPORT_SYMBOL(drm_dp_phy_name);
437
438void drm_dp_lttpr_link_train_clock_recovery_delay(void)
439{
440 usleep_range(100, 200);
441}
442EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay);
443
444static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r)
445{
446 return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1];
447}
448
449void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
450 const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE])
451{
452 u8 interval = dp_lttpr_phy_cap(phy_cap,
453 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) &
454 DP_TRAINING_AUX_RD_MASK;
455
456 __drm_dp_link_train_channel_eq_delay(aux, interval);
457}
458EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
459
460u8 drm_dp_link_rate_to_bw_code(int link_rate)
461{
462 switch (link_rate) {
463 case 1000000:
464 return DP_LINK_BW_10;
465 case 1350000:
466 return DP_LINK_BW_13_5;
467 case 2000000:
468 return DP_LINK_BW_20;
469 default:
470 /* Spec says link_bw = link_rate / 0.27Gbps */
471 return link_rate / 27000;
472 }
473}
474EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
475
476int drm_dp_bw_code_to_link_rate(u8 link_bw)
477{
478 switch (link_bw) {
479 case DP_LINK_BW_10:
480 return 1000000;
481 case DP_LINK_BW_13_5:
482 return 1350000;
483 case DP_LINK_BW_20:
484 return 2000000;
485 default:
486 /* Spec says link_rate = link_bw * 0.27Gbps */
487 return link_bw * 27000;
488 }
489}
490EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
491
492#define AUX_RETRY_INTERVAL 500 /* us */
493
494static inline void
495drm_dp_dump_access(const struct drm_dp_aux *aux,
496 u8 request, uint offset, void *buffer, int ret)
497{
498 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
499
500 if (ret > 0)
501 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
502 aux->name, offset, arrow, ret, min(ret, 20), buffer);
503 else
504 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n",
505 aux->name, offset, arrow, ret);
506}
507
508/**
509 * DOC: dp helpers
510 *
511 * The DisplayPort AUX channel is an abstraction to allow generic, driver-
512 * independent access to AUX functionality. Drivers can take advantage of
513 * this by filling in the fields of the drm_dp_aux structure.
514 *
515 * Transactions are described using a hardware-independent drm_dp_aux_msg
516 * structure, which is passed into a driver's .transfer() implementation.
517 * Both native and I2C-over-AUX transactions are supported.
518 */
519
520static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
521 unsigned int offset, void *buffer, size_t size)
522{
523 struct drm_dp_aux_msg msg;
524 unsigned int retry, native_reply;
525 int err = 0, ret = 0;
526
527 memset(&msg, 0, sizeof(msg));
528 msg.address = offset;
529 msg.request = request;
530 msg.buffer = buffer;
531 msg.size = size;
532
533 mutex_lock(&aux->hw_mutex);
534
535 /*
536 * If the device attached to the aux bus is powered down then there's
537 * no reason to attempt a transfer. Error out immediately.
538 */
539 if (aux->powered_down) {
540 ret = -EBUSY;
541 goto unlock;
542 }
543
544 /*
545 * The specification doesn't give any recommendation on how often to
546 * retry native transactions. We used to retry 7 times like for
547 * aux i2c transactions but real world devices this wasn't
548 * sufficient, bump to 32 which makes Dell 4k monitors happier.
549 */
550 for (retry = 0; retry < 32; retry++) {
551 if (ret != 0 && ret != -ETIMEDOUT) {
552 usleep_range(AUX_RETRY_INTERVAL,
553 AUX_RETRY_INTERVAL + 100);
554 }
555
556 ret = aux->transfer(aux, &msg);
557 if (ret >= 0) {
558 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
559 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
560 if (ret == size)
561 goto unlock;
562
563 ret = -EPROTO;
564 } else
565 ret = -EIO;
566 }
567
568 /*
569 * We want the error we return to be the error we received on
570 * the first transaction, since we may get a different error the
571 * next time we retry
572 */
573 if (!err)
574 err = ret;
575 }
576
577 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n",
578 aux->name, err);
579 ret = err;
580
581unlock:
582 mutex_unlock(&aux->hw_mutex);
583 return ret;
584}
585
586/**
587 * drm_dp_dpcd_probe() - probe a given DPCD address with a 1-byte read access
588 * @aux: DisplayPort AUX channel (SST)
589 * @offset: address of the register to probe
590 *
591 * Probe the provided DPCD address by reading 1 byte from it. The function can
592 * be used to trigger some side-effect the read access has, like waking up the
593 * sink, without the need for the read-out value.
594 *
595 * Returns 0 if the read access suceeded, or a negative error code on failure.
596 */
597int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset)
598{
599 u8 buffer;
600 int ret;
601
602 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, 1);
603 WARN_ON(ret == 0);
604
605 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, ret);
606
607 return ret < 0 ? ret : 0;
608}
609EXPORT_SYMBOL(drm_dp_dpcd_probe);
610
611/**
612 * drm_dp_dpcd_set_powered() - Set whether the DP device is powered
613 * @aux: DisplayPort AUX channel; for convenience it's OK to pass NULL here
614 * and the function will be a no-op.
615 * @powered: true if powered; false if not
616 *
617 * If the endpoint device on the DP AUX bus is known to be powered down
618 * then this function can be called to make future transfers fail immediately
619 * instead of needing to time out.
620 *
621 * If this function is never called then a device defaults to being powered.
622 */
623void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered)
624{
625 if (!aux)
626 return;
627
628 mutex_lock(&aux->hw_mutex);
629 aux->powered_down = !powered;
630 mutex_unlock(&aux->hw_mutex);
631}
632EXPORT_SYMBOL(drm_dp_dpcd_set_powered);
633
634/**
635 * drm_dp_dpcd_read() - read a series of bytes from the DPCD
636 * @aux: DisplayPort AUX channel (SST or MST)
637 * @offset: address of the (first) register to read
638 * @buffer: buffer to store the register values
639 * @size: number of bytes in @buffer
640 *
641 * Returns the number of bytes transferred on success, or a negative error
642 * code on failure. -EIO is returned if the request was NAKed by the sink or
643 * if the retry count was exceeded. If not all bytes were transferred, this
644 * function returns -EPROTO. Errors from the underlying AUX channel transfer
645 * function, with the exception of -EBUSY (which causes the transaction to
646 * be retried), are propagated to the caller.
647 */
648ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
649 void *buffer, size_t size)
650{
651 int ret;
652
653 /*
654 * HP ZR24w corrupts the first DPCD access after entering power save
655 * mode. Eg. on a read, the entire buffer will be filled with the same
656 * byte. Do a throw away read to avoid corrupting anything we care
657 * about. Afterwards things will work correctly until the monitor
658 * gets woken up and subsequently re-enters power save mode.
659 *
660 * The user pressing any button on the monitor is enough to wake it
661 * up, so there is no particularly good place to do the workaround.
662 * We just have to do it before any DPCD access and hope that the
663 * monitor doesn't power down exactly after the throw away read.
664 */
665 if (!aux->is_remote) {
666 ret = drm_dp_dpcd_probe(aux, DP_DPCD_REV);
667 if (ret < 0)
668 return ret;
669 }
670
671 if (aux->is_remote)
672 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size);
673 else
674 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset,
675 buffer, size);
676
677 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
678 return ret;
679}
680EXPORT_SYMBOL(drm_dp_dpcd_read);
681
682/**
683 * drm_dp_dpcd_write() - write a series of bytes to the DPCD
684 * @aux: DisplayPort AUX channel (SST or MST)
685 * @offset: address of the (first) register to write
686 * @buffer: buffer containing the values to write
687 * @size: number of bytes in @buffer
688 *
689 * Returns the number of bytes transferred on success, or a negative error
690 * code on failure. -EIO is returned if the request was NAKed by the sink or
691 * if the retry count was exceeded. If not all bytes were transferred, this
692 * function returns -EPROTO. Errors from the underlying AUX channel transfer
693 * function, with the exception of -EBUSY (which causes the transaction to
694 * be retried), are propagated to the caller.
695 */
696ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
697 void *buffer, size_t size)
698{
699 int ret;
700
701 if (aux->is_remote)
702 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size);
703 else
704 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset,
705 buffer, size);
706
707 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
708 return ret;
709}
710EXPORT_SYMBOL(drm_dp_dpcd_write);
711
712/**
713 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
714 * @aux: DisplayPort AUX channel
715 * @status: buffer to store the link status in (must be at least 6 bytes)
716 *
717 * Returns the number of bytes transferred on success or a negative error
718 * code on failure.
719 */
720int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
721 u8 status[DP_LINK_STATUS_SIZE])
722{
723 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
724 DP_LINK_STATUS_SIZE);
725}
726EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
727
728/**
729 * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY
730 * @aux: DisplayPort AUX channel
731 * @dp_phy: the DP PHY to get the link status for
732 * @link_status: buffer to return the status in
733 *
734 * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The
735 * layout of the returned @link_status matches the DPCD register layout of the
736 * DPRX PHY link status.
737 *
738 * Returns 0 if the information was read successfully or a negative error code
739 * on failure.
740 */
741int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
742 enum drm_dp_phy dp_phy,
743 u8 link_status[DP_LINK_STATUS_SIZE])
744{
745 int ret;
746
747 if (dp_phy == DP_PHY_DPRX) {
748 ret = drm_dp_dpcd_read(aux,
749 DP_LANE0_1_STATUS,
750 link_status,
751 DP_LINK_STATUS_SIZE);
752
753 if (ret < 0)
754 return ret;
755
756 WARN_ON(ret != DP_LINK_STATUS_SIZE);
757
758 return 0;
759 }
760
761 ret = drm_dp_dpcd_read(aux,
762 DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy),
763 link_status,
764 DP_LINK_STATUS_SIZE - 1);
765
766 if (ret < 0)
767 return ret;
768
769 WARN_ON(ret != DP_LINK_STATUS_SIZE - 1);
770
771 /* Convert the LTTPR to the sink PHY link status layout */
772 memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1],
773 &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS],
774 DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1);
775 link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0;
776
777 return 0;
778}
779EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status);
780
781static bool is_edid_digital_input_dp(const struct drm_edid *drm_edid)
782{
783 /* FIXME: get rid of drm_edid_raw() */
784 const struct edid *edid = drm_edid_raw(drm_edid);
785
786 return edid && edid->revision >= 4 &&
787 edid->input & DRM_EDID_INPUT_DIGITAL &&
788 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP;
789}
790
791/**
792 * drm_dp_downstream_is_type() - is the downstream facing port of certain type?
793 * @dpcd: DisplayPort configuration data
794 * @port_cap: port capabilities
795 * @type: port type to be checked. Can be:
796 * %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI,
797 * %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID,
798 * %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS.
799 *
800 * Caveat: Only works with DPCD 1.1+ port caps.
801 *
802 * Returns: whether the downstream facing port matches the type.
803 */
804bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
805 const u8 port_cap[4], u8 type)
806{
807 return drm_dp_is_branch(dpcd) &&
808 dpcd[DP_DPCD_REV] >= 0x11 &&
809 (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type;
810}
811EXPORT_SYMBOL(drm_dp_downstream_is_type);
812
813/**
814 * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?
815 * @dpcd: DisplayPort configuration data
816 * @port_cap: port capabilities
817 * @drm_edid: EDID
818 *
819 * Returns: whether the downstream facing port is TMDS (HDMI/DVI).
820 */
821bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
822 const u8 port_cap[4],
823 const struct drm_edid *drm_edid)
824{
825 if (dpcd[DP_DPCD_REV] < 0x11) {
826 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
827 case DP_DWN_STRM_PORT_TYPE_TMDS:
828 return true;
829 default:
830 return false;
831 }
832 }
833
834 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
835 case DP_DS_PORT_TYPE_DP_DUALMODE:
836 if (is_edid_digital_input_dp(drm_edid))
837 return false;
838 fallthrough;
839 case DP_DS_PORT_TYPE_DVI:
840 case DP_DS_PORT_TYPE_HDMI:
841 return true;
842 default:
843 return false;
844 }
845}
846EXPORT_SYMBOL(drm_dp_downstream_is_tmds);
847
848/**
849 * drm_dp_send_real_edid_checksum() - send back real edid checksum value
850 * @aux: DisplayPort AUX channel
851 * @real_edid_checksum: real edid checksum for the last block
852 *
853 * Returns:
854 * True on success
855 */
856bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
857 u8 real_edid_checksum)
858{
859 u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
860
861 if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
862 &auto_test_req, 1) < 1) {
863 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
864 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
865 return false;
866 }
867 auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
868
869 if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) {
870 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
871 aux->name, DP_TEST_REQUEST);
872 return false;
873 }
874 link_edid_read &= DP_TEST_LINK_EDID_READ;
875
876 if (!auto_test_req || !link_edid_read) {
877 drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n",
878 aux->name);
879 return false;
880 }
881
882 if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
883 &auto_test_req, 1) < 1) {
884 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
885 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
886 return false;
887 }
888
889 /* send back checksum for the last edid extension block data */
890 if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM,
891 &real_edid_checksum, 1) < 1) {
892 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
893 aux->name, DP_TEST_EDID_CHECKSUM);
894 return false;
895 }
896
897 test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
898 if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) {
899 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
900 aux->name, DP_TEST_RESPONSE);
901 return false;
902 }
903
904 return true;
905}
906EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
907
908static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
909{
910 u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK;
911
912 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4)
913 port_count = 4;
914
915 return port_count;
916}
917
918static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
919 u8 dpcd[DP_RECEIVER_CAP_SIZE])
920{
921 u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];
922 int ret;
923
924 /*
925 * Prior to DP1.3 the bit represented by
926 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
927 * If it is set DP_DPCD_REV at 0000h could be at a value less than
928 * the true capability of the panel. The only way to check is to
929 * then compare 0000h and 2200h.
930 */
931 if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
932 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
933 return 0;
934
935 ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext,
936 sizeof(dpcd_ext));
937 if (ret < 0)
938 return ret;
939 if (ret != sizeof(dpcd_ext))
940 return -EIO;
941
942 if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
943 drm_dbg_kms(aux->drm_dev,
944 "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n",
945 aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]);
946 return 0;
947 }
948
949 if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext)))
950 return 0;
951
952 drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
953
954 memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext));
955
956 return 0;
957}
958
959/**
960 * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if
961 * available
962 * @aux: DisplayPort AUX channel
963 * @dpcd: Buffer to store the resulting DPCD in
964 *
965 * Attempts to read the base DPCD caps for @aux. Additionally, this function
966 * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if
967 * present.
968 *
969 * Returns: %0 if the DPCD was read successfully, negative error code
970 * otherwise.
971 */
972int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
973 u8 dpcd[DP_RECEIVER_CAP_SIZE])
974{
975 int ret;
976
977 ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE);
978 if (ret < 0)
979 return ret;
980 if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0)
981 return -EIO;
982
983 ret = drm_dp_read_extended_dpcd_caps(aux, dpcd);
984 if (ret < 0)
985 return ret;
986
987 drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
988
989 return ret;
990}
991EXPORT_SYMBOL(drm_dp_read_dpcd_caps);
992
993/**
994 * drm_dp_read_downstream_info() - read DPCD downstream port info if available
995 * @aux: DisplayPort AUX channel
996 * @dpcd: A cached copy of the port's DPCD
997 * @downstream_ports: buffer to store the downstream port info in
998 *
999 * See also:
1000 * drm_dp_downstream_max_clock()
1001 * drm_dp_downstream_max_bpc()
1002 *
1003 * Returns: 0 if either the downstream port info was read successfully or
1004 * there was no downstream info to read, or a negative error code otherwise.
1005 */
1006int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
1007 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1008 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS])
1009{
1010 int ret;
1011 u8 len;
1012
1013 memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS);
1014
1015 /* No downstream info to read */
1016 if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10)
1017 return 0;
1018
1019 /* Some branches advertise having 0 downstream ports, despite also advertising they have a
1020 * downstream port present. The DP spec isn't clear on if this is allowed or not, but since
1021 * some branches do it we need to handle it regardless.
1022 */
1023 len = drm_dp_downstream_port_count(dpcd);
1024 if (!len)
1025 return 0;
1026
1027 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE)
1028 len *= 4;
1029
1030 ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len);
1031 if (ret < 0)
1032 return ret;
1033 if (ret != len)
1034 return -EIO;
1035
1036 drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports);
1037
1038 return 0;
1039}
1040EXPORT_SYMBOL(drm_dp_read_downstream_info);
1041
1042/**
1043 * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock
1044 * @dpcd: DisplayPort configuration data
1045 * @port_cap: port capabilities
1046 *
1047 * Returns: Downstream facing port max dot clock in kHz on success,
1048 * or 0 if max clock not defined
1049 */
1050int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1051 const u8 port_cap[4])
1052{
1053 if (!drm_dp_is_branch(dpcd))
1054 return 0;
1055
1056 if (dpcd[DP_DPCD_REV] < 0x11)
1057 return 0;
1058
1059 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1060 case DP_DS_PORT_TYPE_VGA:
1061 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1062 return 0;
1063 return port_cap[1] * 8000;
1064 default:
1065 return 0;
1066 }
1067}
1068EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);
1069
1070/**
1071 * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock
1072 * @dpcd: DisplayPort configuration data
1073 * @port_cap: port capabilities
1074 * @drm_edid: EDID
1075 *
1076 * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success,
1077 * or 0 if max TMDS clock not defined
1078 */
1079int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1080 const u8 port_cap[4],
1081 const struct drm_edid *drm_edid)
1082{
1083 if (!drm_dp_is_branch(dpcd))
1084 return 0;
1085
1086 if (dpcd[DP_DPCD_REV] < 0x11) {
1087 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1088 case DP_DWN_STRM_PORT_TYPE_TMDS:
1089 return 165000;
1090 default:
1091 return 0;
1092 }
1093 }
1094
1095 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1096 case DP_DS_PORT_TYPE_DP_DUALMODE:
1097 if (is_edid_digital_input_dp(drm_edid))
1098 return 0;
1099 /*
1100 * It's left up to the driver to check the
1101 * DP dual mode adapter's max TMDS clock.
1102 *
1103 * Unfortunately it looks like branch devices
1104 * may not fordward that the DP dual mode i2c
1105 * access so we just usually get i2c nak :(
1106 */
1107 fallthrough;
1108 case DP_DS_PORT_TYPE_HDMI:
1109 /*
1110 * We should perhaps assume 165 MHz when detailed cap
1111 * info is not available. But looks like many typical
1112 * branch devices fall into that category and so we'd
1113 * probably end up with users complaining that they can't
1114 * get high resolution modes with their favorite dongle.
1115 *
1116 * So let's limit to 300 MHz instead since DPCD 1.4
1117 * HDMI 2.0 DFPs are required to have the detailed cap
1118 * info. So it's more likely we're dealing with a HDMI 1.4
1119 * compatible* device here.
1120 */
1121 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1122 return 300000;
1123 return port_cap[1] * 2500;
1124 case DP_DS_PORT_TYPE_DVI:
1125 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1126 return 165000;
1127 /* FIXME what to do about DVI dual link? */
1128 return port_cap[1] * 2500;
1129 default:
1130 return 0;
1131 }
1132}
1133EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock);
1134
1135/**
1136 * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock
1137 * @dpcd: DisplayPort configuration data
1138 * @port_cap: port capabilities
1139 * @drm_edid: EDID
1140 *
1141 * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success,
1142 * or 0 if max TMDS clock not defined
1143 */
1144int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1145 const u8 port_cap[4],
1146 const struct drm_edid *drm_edid)
1147{
1148 if (!drm_dp_is_branch(dpcd))
1149 return 0;
1150
1151 if (dpcd[DP_DPCD_REV] < 0x11) {
1152 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1153 case DP_DWN_STRM_PORT_TYPE_TMDS:
1154 return 25000;
1155 default:
1156 return 0;
1157 }
1158 }
1159
1160 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1161 case DP_DS_PORT_TYPE_DP_DUALMODE:
1162 if (is_edid_digital_input_dp(drm_edid))
1163 return 0;
1164 fallthrough;
1165 case DP_DS_PORT_TYPE_DVI:
1166 case DP_DS_PORT_TYPE_HDMI:
1167 /*
1168 * Unclear whether the protocol converter could
1169 * utilize pixel replication. Assume it won't.
1170 */
1171 return 25000;
1172 default:
1173 return 0;
1174 }
1175}
1176EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock);
1177
1178/**
1179 * drm_dp_downstream_max_bpc() - extract downstream facing port max
1180 * bits per component
1181 * @dpcd: DisplayPort configuration data
1182 * @port_cap: downstream facing port capabilities
1183 * @drm_edid: EDID
1184 *
1185 * Returns: Max bpc on success or 0 if max bpc not defined
1186 */
1187int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1188 const u8 port_cap[4],
1189 const struct drm_edid *drm_edid)
1190{
1191 if (!drm_dp_is_branch(dpcd))
1192 return 0;
1193
1194 if (dpcd[DP_DPCD_REV] < 0x11) {
1195 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1196 case DP_DWN_STRM_PORT_TYPE_DP:
1197 return 0;
1198 default:
1199 return 8;
1200 }
1201 }
1202
1203 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1204 case DP_DS_PORT_TYPE_DP:
1205 return 0;
1206 case DP_DS_PORT_TYPE_DP_DUALMODE:
1207 if (is_edid_digital_input_dp(drm_edid))
1208 return 0;
1209 fallthrough;
1210 case DP_DS_PORT_TYPE_HDMI:
1211 case DP_DS_PORT_TYPE_DVI:
1212 case DP_DS_PORT_TYPE_VGA:
1213 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1214 return 8;
1215
1216 switch (port_cap[2] & DP_DS_MAX_BPC_MASK) {
1217 case DP_DS_8BPC:
1218 return 8;
1219 case DP_DS_10BPC:
1220 return 10;
1221 case DP_DS_12BPC:
1222 return 12;
1223 case DP_DS_16BPC:
1224 return 16;
1225 default:
1226 return 8;
1227 }
1228 break;
1229 default:
1230 return 8;
1231 }
1232}
1233EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
1234
1235/**
1236 * drm_dp_downstream_420_passthrough() - determine downstream facing port
1237 * YCbCr 4:2:0 pass-through capability
1238 * @dpcd: DisplayPort configuration data
1239 * @port_cap: downstream facing port capabilities
1240 *
1241 * Returns: whether the downstream facing port can pass through YCbCr 4:2:0
1242 */
1243bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1244 const u8 port_cap[4])
1245{
1246 if (!drm_dp_is_branch(dpcd))
1247 return false;
1248
1249 if (dpcd[DP_DPCD_REV] < 0x13)
1250 return false;
1251
1252 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1253 case DP_DS_PORT_TYPE_DP:
1254 return true;
1255 case DP_DS_PORT_TYPE_HDMI:
1256 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1257 return false;
1258
1259 return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;
1260 default:
1261 return false;
1262 }
1263}
1264EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);
1265
1266/**
1267 * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port
1268 * YCbCr 4:4:4->4:2:0 conversion capability
1269 * @dpcd: DisplayPort configuration data
1270 * @port_cap: downstream facing port capabilities
1271 *
1272 * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0
1273 */
1274bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1275 const u8 port_cap[4])
1276{
1277 if (!drm_dp_is_branch(dpcd))
1278 return false;
1279
1280 if (dpcd[DP_DPCD_REV] < 0x13)
1281 return false;
1282
1283 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1284 case DP_DS_PORT_TYPE_HDMI:
1285 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1286 return false;
1287
1288 return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;
1289 default:
1290 return false;
1291 }
1292}
1293EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
1294
1295/**
1296 * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port
1297 * RGB->YCbCr conversion capability
1298 * @dpcd: DisplayPort configuration data
1299 * @port_cap: downstream facing port capabilities
1300 * @color_spc: Colorspace for which conversion cap is sought
1301 *
1302 * Returns: whether the downstream facing port can convert RGB->YCbCr for a given
1303 * colorspace.
1304 */
1305bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1306 const u8 port_cap[4],
1307 u8 color_spc)
1308{
1309 if (!drm_dp_is_branch(dpcd))
1310 return false;
1311
1312 if (dpcd[DP_DPCD_REV] < 0x13)
1313 return false;
1314
1315 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1316 case DP_DS_PORT_TYPE_HDMI:
1317 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1318 return false;
1319
1320 return port_cap[3] & color_spc;
1321 default:
1322 return false;
1323 }
1324}
1325EXPORT_SYMBOL(drm_dp_downstream_rgb_to_ycbcr_conversion);
1326
1327/**
1328 * drm_dp_downstream_mode() - return a mode for downstream facing port
1329 * @dev: DRM device
1330 * @dpcd: DisplayPort configuration data
1331 * @port_cap: port capabilities
1332 *
1333 * Provides a suitable mode for downstream facing ports without EDID.
1334 *
1335 * Returns: A new drm_display_mode on success or NULL on failure
1336 */
1337struct drm_display_mode *
1338drm_dp_downstream_mode(struct drm_device *dev,
1339 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1340 const u8 port_cap[4])
1341
1342{
1343 u8 vic;
1344
1345 if (!drm_dp_is_branch(dpcd))
1346 return NULL;
1347
1348 if (dpcd[DP_DPCD_REV] < 0x11)
1349 return NULL;
1350
1351 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1352 case DP_DS_PORT_TYPE_NON_EDID:
1353 switch (port_cap[0] & DP_DS_NON_EDID_MASK) {
1354 case DP_DS_NON_EDID_720x480i_60:
1355 vic = 6;
1356 break;
1357 case DP_DS_NON_EDID_720x480i_50:
1358 vic = 21;
1359 break;
1360 case DP_DS_NON_EDID_1920x1080i_60:
1361 vic = 5;
1362 break;
1363 case DP_DS_NON_EDID_1920x1080i_50:
1364 vic = 20;
1365 break;
1366 case DP_DS_NON_EDID_1280x720_60:
1367 vic = 4;
1368 break;
1369 case DP_DS_NON_EDID_1280x720_50:
1370 vic = 19;
1371 break;
1372 default:
1373 return NULL;
1374 }
1375 return drm_display_mode_from_cea_vic(dev, vic);
1376 default:
1377 return NULL;
1378 }
1379}
1380EXPORT_SYMBOL(drm_dp_downstream_mode);
1381
1382/**
1383 * drm_dp_downstream_id() - identify branch device
1384 * @aux: DisplayPort AUX channel
1385 * @id: DisplayPort branch device id
1386 *
1387 * Returns branch device id on success or NULL on failure
1388 */
1389int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
1390{
1391 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
1392}
1393EXPORT_SYMBOL(drm_dp_downstream_id);
1394
1395/**
1396 * drm_dp_downstream_debug() - debug DP branch devices
1397 * @m: pointer for debugfs file
1398 * @dpcd: DisplayPort configuration data
1399 * @port_cap: port capabilities
1400 * @drm_edid: EDID
1401 * @aux: DisplayPort AUX channel
1402 *
1403 */
1404void drm_dp_downstream_debug(struct seq_file *m,
1405 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1406 const u8 port_cap[4],
1407 const struct drm_edid *drm_edid,
1408 struct drm_dp_aux *aux)
1409{
1410 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1411 DP_DETAILED_CAP_INFO_AVAILABLE;
1412 int clk;
1413 int bpc;
1414 char id[7];
1415 int len;
1416 uint8_t rev[2];
1417 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1418 bool branch_device = drm_dp_is_branch(dpcd);
1419
1420 seq_printf(m, "\tDP branch device present: %s\n",
1421 str_yes_no(branch_device));
1422
1423 if (!branch_device)
1424 return;
1425
1426 switch (type) {
1427 case DP_DS_PORT_TYPE_DP:
1428 seq_puts(m, "\t\tType: DisplayPort\n");
1429 break;
1430 case DP_DS_PORT_TYPE_VGA:
1431 seq_puts(m, "\t\tType: VGA\n");
1432 break;
1433 case DP_DS_PORT_TYPE_DVI:
1434 seq_puts(m, "\t\tType: DVI\n");
1435 break;
1436 case DP_DS_PORT_TYPE_HDMI:
1437 seq_puts(m, "\t\tType: HDMI\n");
1438 break;
1439 case DP_DS_PORT_TYPE_NON_EDID:
1440 seq_puts(m, "\t\tType: others without EDID support\n");
1441 break;
1442 case DP_DS_PORT_TYPE_DP_DUALMODE:
1443 seq_puts(m, "\t\tType: DP++\n");
1444 break;
1445 case DP_DS_PORT_TYPE_WIRELESS:
1446 seq_puts(m, "\t\tType: Wireless\n");
1447 break;
1448 default:
1449 seq_puts(m, "\t\tType: N/A\n");
1450 }
1451
1452 memset(id, 0, sizeof(id));
1453 drm_dp_downstream_id(aux, id);
1454 seq_printf(m, "\t\tID: %s\n", id);
1455
1456 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1);
1457 if (len > 0)
1458 seq_printf(m, "\t\tHW: %d.%d\n",
1459 (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
1460
1461 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2);
1462 if (len > 0)
1463 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
1464
1465 if (detailed_cap_info) {
1466 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);
1467 if (clk > 0)
1468 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
1469
1470 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, drm_edid);
1471 if (clk > 0)
1472 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
1473
1474 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, drm_edid);
1475 if (clk > 0)
1476 seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk);
1477
1478 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, drm_edid);
1479
1480 if (bpc > 0)
1481 seq_printf(m, "\t\tMax bpc: %d\n", bpc);
1482 }
1483}
1484EXPORT_SYMBOL(drm_dp_downstream_debug);
1485
1486/**
1487 * drm_dp_subconnector_type() - get DP branch device type
1488 * @dpcd: DisplayPort configuration data
1489 * @port_cap: port capabilities
1490 */
1491enum drm_mode_subconnector
1492drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1493 const u8 port_cap[4])
1494{
1495 int type;
1496 if (!drm_dp_is_branch(dpcd))
1497 return DRM_MODE_SUBCONNECTOR_Native;
1498 /* DP 1.0 approach */
1499 if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) {
1500 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1501 DP_DWN_STRM_PORT_TYPE_MASK;
1502
1503 switch (type) {
1504 case DP_DWN_STRM_PORT_TYPE_TMDS:
1505 /* Can be HDMI or DVI-D, DVI-D is a safer option */
1506 return DRM_MODE_SUBCONNECTOR_DVID;
1507 case DP_DWN_STRM_PORT_TYPE_ANALOG:
1508 /* Can be VGA or DVI-A, VGA is more popular */
1509 return DRM_MODE_SUBCONNECTOR_VGA;
1510 case DP_DWN_STRM_PORT_TYPE_DP:
1511 return DRM_MODE_SUBCONNECTOR_DisplayPort;
1512 case DP_DWN_STRM_PORT_TYPE_OTHER:
1513 default:
1514 return DRM_MODE_SUBCONNECTOR_Unknown;
1515 }
1516 }
1517 type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1518
1519 switch (type) {
1520 case DP_DS_PORT_TYPE_DP:
1521 case DP_DS_PORT_TYPE_DP_DUALMODE:
1522 return DRM_MODE_SUBCONNECTOR_DisplayPort;
1523 case DP_DS_PORT_TYPE_VGA:
1524 return DRM_MODE_SUBCONNECTOR_VGA;
1525 case DP_DS_PORT_TYPE_DVI:
1526 return DRM_MODE_SUBCONNECTOR_DVID;
1527 case DP_DS_PORT_TYPE_HDMI:
1528 return DRM_MODE_SUBCONNECTOR_HDMIA;
1529 case DP_DS_PORT_TYPE_WIRELESS:
1530 return DRM_MODE_SUBCONNECTOR_Wireless;
1531 case DP_DS_PORT_TYPE_NON_EDID:
1532 default:
1533 return DRM_MODE_SUBCONNECTOR_Unknown;
1534 }
1535}
1536EXPORT_SYMBOL(drm_dp_subconnector_type);
1537
1538/**
1539 * drm_dp_set_subconnector_property - set subconnector for DP connector
1540 * @connector: connector to set property on
1541 * @status: connector status
1542 * @dpcd: DisplayPort configuration data
1543 * @port_cap: port capabilities
1544 *
1545 * Called by a driver on every detect event.
1546 */
1547void drm_dp_set_subconnector_property(struct drm_connector *connector,
1548 enum drm_connector_status status,
1549 const u8 *dpcd,
1550 const u8 port_cap[4])
1551{
1552 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
1553
1554 if (status == connector_status_connected)
1555 subconnector = drm_dp_subconnector_type(dpcd, port_cap);
1556 drm_object_property_set_value(&connector->base,
1557 connector->dev->mode_config.dp_subconnector_property,
1558 subconnector);
1559}
1560EXPORT_SYMBOL(drm_dp_set_subconnector_property);
1561
1562/**
1563 * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink
1564 * count
1565 * @connector: The DRM connector to check
1566 * @dpcd: A cached copy of the connector's DPCD RX capabilities
1567 * @desc: A cached copy of the connector's DP descriptor
1568 *
1569 * See also: drm_dp_read_sink_count()
1570 *
1571 * Returns: %True if the (e)DP connector has a valid sink count that should
1572 * be probed, %false otherwise.
1573 */
1574bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
1575 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1576 const struct drm_dp_desc *desc)
1577{
1578 /* Some eDP panels don't set a valid value for the sink count */
1579 return connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
1580 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&
1581 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
1582 !drm_dp_has_quirk(desc, DP_DPCD_QUIRK_NO_SINK_COUNT);
1583}
1584EXPORT_SYMBOL(drm_dp_read_sink_count_cap);
1585
1586/**
1587 * drm_dp_read_sink_count() - Retrieve the sink count for a given sink
1588 * @aux: The DP AUX channel to use
1589 *
1590 * See also: drm_dp_read_sink_count_cap()
1591 *
1592 * Returns: The current sink count reported by @aux, or a negative error code
1593 * otherwise.
1594 */
1595int drm_dp_read_sink_count(struct drm_dp_aux *aux)
1596{
1597 u8 count;
1598 int ret;
1599
1600 ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT, &count);
1601 if (ret < 0)
1602 return ret;
1603 if (ret != 1)
1604 return -EIO;
1605
1606 return DP_GET_SINK_COUNT(count);
1607}
1608EXPORT_SYMBOL(drm_dp_read_sink_count);
1609
1610/*
1611 * I2C-over-AUX implementation
1612 */
1613
1614static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
1615{
1616 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1617 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
1618 I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1619 I2C_FUNC_10BIT_ADDR;
1620}
1621
1622static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
1623{
1624 /*
1625 * In case of i2c defer or short i2c ack reply to a write,
1626 * we need to switch to WRITE_STATUS_UPDATE to drain the
1627 * rest of the message
1628 */
1629 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
1630 msg->request &= DP_AUX_I2C_MOT;
1631 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
1632 }
1633}
1634
1635#define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
1636#define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
1637#define AUX_STOP_LEN 4
1638#define AUX_CMD_LEN 4
1639#define AUX_ADDRESS_LEN 20
1640#define AUX_REPLY_PAD_LEN 4
1641#define AUX_LENGTH_LEN 8
1642
1643/*
1644 * Calculate the duration of the AUX request/reply in usec. Gives the
1645 * "best" case estimate, ie. successful while as short as possible.
1646 */
1647static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
1648{
1649 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1650 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
1651
1652 if ((msg->request & DP_AUX_I2C_READ) == 0)
1653 len += msg->size * 8;
1654
1655 return len;
1656}
1657
1658static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
1659{
1660 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1661 AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
1662
1663 /*
1664 * For read we expect what was asked. For writes there will
1665 * be 0 or 1 data bytes. Assume 0 for the "best" case.
1666 */
1667 if (msg->request & DP_AUX_I2C_READ)
1668 len += msg->size * 8;
1669
1670 return len;
1671}
1672
1673#define I2C_START_LEN 1
1674#define I2C_STOP_LEN 1
1675#define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
1676#define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
1677
1678/*
1679 * Calculate the length of the i2c transfer in usec, assuming
1680 * the i2c bus speed is as specified. Gives the "worst"
1681 * case estimate, ie. successful while as long as possible.
1682 * Doesn't account the "MOT" bit, and instead assumes each
1683 * message includes a START, ADDRESS and STOP. Neither does it
1684 * account for additional random variables such as clock stretching.
1685 */
1686static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
1687 int i2c_speed_khz)
1688{
1689 /* AUX bitrate is 1MHz, i2c bitrate as specified */
1690 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
1691 msg->size * I2C_DATA_LEN +
1692 I2C_STOP_LEN) * 1000, i2c_speed_khz);
1693}
1694
1695/*
1696 * Determine how many retries should be attempted to successfully transfer
1697 * the specified message, based on the estimated durations of the
1698 * i2c and AUX transfers.
1699 */
1700static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
1701 int i2c_speed_khz)
1702{
1703 int aux_time_us = drm_dp_aux_req_duration(msg) +
1704 drm_dp_aux_reply_duration(msg);
1705 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
1706
1707 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
1708}
1709
1710/*
1711 * FIXME currently assumes 10 kHz as some real world devices seem
1712 * to require it. We should query/set the speed via DPCD if supported.
1713 */
1714static int dp_aux_i2c_speed_khz __read_mostly = 10;
1715module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
1716MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
1717 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
1718
1719/*
1720 * Transfer a single I2C-over-AUX message and handle various error conditions,
1721 * retrying the transaction as appropriate. It is assumed that the
1722 * &drm_dp_aux.transfer function does not modify anything in the msg other than the
1723 * reply field.
1724 *
1725 * Returns bytes transferred on success, or a negative error code on failure.
1726 */
1727static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1728{
1729 unsigned int retry, defer_i2c;
1730 int ret;
1731 /*
1732 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
1733 * is required to retry at least seven times upon receiving AUX_DEFER
1734 * before giving up the AUX transaction.
1735 *
1736 * We also try to account for the i2c bus speed.
1737 */
1738 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
1739
1740 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
1741 ret = aux->transfer(aux, msg);
1742 if (ret < 0) {
1743 if (ret == -EBUSY)
1744 continue;
1745
1746 /*
1747 * While timeouts can be errors, they're usually normal
1748 * behavior (for instance, when a driver tries to
1749 * communicate with a non-existent DisplayPort device).
1750 * Avoid spamming the kernel log with timeout errors.
1751 */
1752 if (ret == -ETIMEDOUT)
1753 drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n",
1754 aux->name);
1755 else
1756 drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n",
1757 aux->name, ret);
1758 return ret;
1759 }
1760
1761
1762 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
1763 case DP_AUX_NATIVE_REPLY_ACK:
1764 /*
1765 * For I2C-over-AUX transactions this isn't enough, we
1766 * need to check for the I2C ACK reply.
1767 */
1768 break;
1769
1770 case DP_AUX_NATIVE_REPLY_NACK:
1771 drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n",
1772 aux->name, ret, msg->size);
1773 return -EREMOTEIO;
1774
1775 case DP_AUX_NATIVE_REPLY_DEFER:
1776 drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name);
1777 /*
1778 * We could check for I2C bit rate capabilities and if
1779 * available adjust this interval. We could also be
1780 * more careful with DP-to-legacy adapters where a
1781 * long legacy cable may force very low I2C bit rates.
1782 *
1783 * For now just defer for long enough to hopefully be
1784 * safe for all use-cases.
1785 */
1786 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
1787 continue;
1788
1789 default:
1790 drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n",
1791 aux->name, msg->reply);
1792 return -EREMOTEIO;
1793 }
1794
1795 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
1796 case DP_AUX_I2C_REPLY_ACK:
1797 /*
1798 * Both native ACK and I2C ACK replies received. We
1799 * can assume the transfer was successful.
1800 */
1801 if (ret != msg->size)
1802 drm_dp_i2c_msg_write_status_update(msg);
1803 return ret;
1804
1805 case DP_AUX_I2C_REPLY_NACK:
1806 drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n",
1807 aux->name, ret, msg->size);
1808 aux->i2c_nack_count++;
1809 return -EREMOTEIO;
1810
1811 case DP_AUX_I2C_REPLY_DEFER:
1812 drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name);
1813 /* DP Compliance Test 4.2.2.5 Requirement:
1814 * Must have at least 7 retries for I2C defers on the
1815 * transaction to pass this test
1816 */
1817 aux->i2c_defer_count++;
1818 if (defer_i2c < 7)
1819 defer_i2c++;
1820 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
1821 drm_dp_i2c_msg_write_status_update(msg);
1822
1823 continue;
1824
1825 default:
1826 drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n",
1827 aux->name, msg->reply);
1828 return -EREMOTEIO;
1829 }
1830 }
1831
1832 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name);
1833 return -EREMOTEIO;
1834}
1835
1836static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
1837 const struct i2c_msg *i2c_msg)
1838{
1839 msg->request = (i2c_msg->flags & I2C_M_RD) ?
1840 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
1841 if (!(i2c_msg->flags & I2C_M_STOP))
1842 msg->request |= DP_AUX_I2C_MOT;
1843}
1844
1845/*
1846 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
1847 *
1848 * Returns an error code on failure, or a recommended transfer size on success.
1849 */
1850static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
1851{
1852 int err, ret = orig_msg->size;
1853 struct drm_dp_aux_msg msg = *orig_msg;
1854
1855 while (msg.size > 0) {
1856 err = drm_dp_i2c_do_msg(aux, &msg);
1857 if (err <= 0)
1858 return err == 0 ? -EPROTO : err;
1859
1860 if (err < msg.size && err < ret) {
1861 drm_dbg_kms(aux->drm_dev,
1862 "%s: Partial I2C reply: requested %zu bytes got %d bytes\n",
1863 aux->name, msg.size, err);
1864 ret = err;
1865 }
1866
1867 msg.size -= err;
1868 msg.buffer += err;
1869 }
1870
1871 return ret;
1872}
1873
1874/*
1875 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
1876 * packets to be as large as possible. If not, the I2C transactions never
1877 * succeed. Hence the default is maximum.
1878 */
1879static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
1880module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
1881MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
1882 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
1883
1884static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
1885 int num)
1886{
1887 struct drm_dp_aux *aux = adapter->algo_data;
1888 unsigned int i, j;
1889 unsigned transfer_size;
1890 struct drm_dp_aux_msg msg;
1891 int err = 0;
1892
1893 if (aux->powered_down)
1894 return -EBUSY;
1895
1896 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
1897
1898 memset(&msg, 0, sizeof(msg));
1899
1900 for (i = 0; i < num; i++) {
1901 msg.address = msgs[i].addr;
1902 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1903 /* Send a bare address packet to start the transaction.
1904 * Zero sized messages specify an address only (bare
1905 * address) transaction.
1906 */
1907 msg.buffer = NULL;
1908 msg.size = 0;
1909 err = drm_dp_i2c_do_msg(aux, &msg);
1910
1911 /*
1912 * Reset msg.request in case in case it got
1913 * changed into a WRITE_STATUS_UPDATE.
1914 */
1915 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1916
1917 if (err < 0)
1918 break;
1919 /* We want each transaction to be as large as possible, but
1920 * we'll go to smaller sizes if the hardware gives us a
1921 * short reply.
1922 */
1923 transfer_size = dp_aux_i2c_transfer_size;
1924 for (j = 0; j < msgs[i].len; j += msg.size) {
1925 msg.buffer = msgs[i].buf + j;
1926 msg.size = min(transfer_size, msgs[i].len - j);
1927
1928 err = drm_dp_i2c_drain_msg(aux, &msg);
1929
1930 /*
1931 * Reset msg.request in case in case it got
1932 * changed into a WRITE_STATUS_UPDATE.
1933 */
1934 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1935
1936 if (err < 0)
1937 break;
1938 transfer_size = err;
1939 }
1940 if (err < 0)
1941 break;
1942 }
1943 if (err >= 0)
1944 err = num;
1945 /* Send a bare address packet to close out the transaction.
1946 * Zero sized messages specify an address only (bare
1947 * address) transaction.
1948 */
1949 msg.request &= ~DP_AUX_I2C_MOT;
1950 msg.buffer = NULL;
1951 msg.size = 0;
1952 (void)drm_dp_i2c_do_msg(aux, &msg);
1953
1954 return err;
1955}
1956
1957static const struct i2c_algorithm drm_dp_i2c_algo = {
1958 .functionality = drm_dp_i2c_functionality,
1959 .master_xfer = drm_dp_i2c_xfer,
1960};
1961
1962static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
1963{
1964 return container_of(i2c, struct drm_dp_aux, ddc);
1965}
1966
1967static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
1968{
1969 mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
1970}
1971
1972static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
1973{
1974 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
1975}
1976
1977static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
1978{
1979 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex);
1980}
1981
1982static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
1983 .lock_bus = lock_bus,
1984 .trylock_bus = trylock_bus,
1985 .unlock_bus = unlock_bus,
1986};
1987
1988static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
1989{
1990 u8 buf, count;
1991 int ret;
1992
1993 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1994 if (ret < 0)
1995 return ret;
1996
1997 WARN_ON(!(buf & DP_TEST_SINK_START));
1998
1999 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
2000 if (ret < 0)
2001 return ret;
2002
2003 count = buf & DP_TEST_COUNT_MASK;
2004 if (count == aux->crc_count)
2005 return -EAGAIN; /* No CRC yet */
2006
2007 aux->crc_count = count;
2008
2009 /*
2010 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
2011 * per component (RGB or CrYCb).
2012 */
2013 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6);
2014 if (ret < 0)
2015 return ret;
2016
2017 return 0;
2018}
2019
2020static void drm_dp_aux_crc_work(struct work_struct *work)
2021{
2022 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
2023 crc_work);
2024 struct drm_crtc *crtc;
2025 u8 crc_bytes[6];
2026 uint32_t crcs[3];
2027 int ret;
2028
2029 if (WARN_ON(!aux->crtc))
2030 return;
2031
2032 crtc = aux->crtc;
2033 while (crtc->crc.opened) {
2034 drm_crtc_wait_one_vblank(crtc);
2035 if (!crtc->crc.opened)
2036 break;
2037
2038 ret = drm_dp_aux_get_crc(aux, crc_bytes);
2039 if (ret == -EAGAIN) {
2040 usleep_range(1000, 2000);
2041 ret = drm_dp_aux_get_crc(aux, crc_bytes);
2042 }
2043
2044 if (ret == -EAGAIN) {
2045 drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n",
2046 aux->name, ret);
2047 continue;
2048 } else if (ret) {
2049 drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret);
2050 continue;
2051 }
2052
2053 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
2054 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
2055 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
2056 drm_crtc_add_crc_entry(crtc, false, 0, crcs);
2057 }
2058}
2059
2060/**
2061 * drm_dp_remote_aux_init() - minimally initialise a remote aux channel
2062 * @aux: DisplayPort AUX channel
2063 *
2064 * Used for remote aux channel in general. Merely initialize the crc work
2065 * struct.
2066 */
2067void drm_dp_remote_aux_init(struct drm_dp_aux *aux)
2068{
2069 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
2070}
2071EXPORT_SYMBOL(drm_dp_remote_aux_init);
2072
2073/**
2074 * drm_dp_aux_init() - minimally initialise an aux channel
2075 * @aux: DisplayPort AUX channel
2076 *
2077 * If you need to use the drm_dp_aux's i2c adapter prior to registering it with
2078 * the outside world, call drm_dp_aux_init() first. For drivers which are
2079 * grandparents to their AUX adapters (e.g. the AUX adapter is parented by a
2080 * &drm_connector), you must still call drm_dp_aux_register() once the connector
2081 * has been registered to allow userspace access to the auxiliary DP channel.
2082 * Likewise, for such drivers you should also assign &drm_dp_aux.drm_dev as
2083 * early as possible so that the &drm_device that corresponds to the AUX adapter
2084 * may be mentioned in debugging output from the DRM DP helpers.
2085 *
2086 * For devices which use a separate platform device for their AUX adapters, this
2087 * may be called as early as required by the driver.
2088 *
2089 */
2090void drm_dp_aux_init(struct drm_dp_aux *aux)
2091{
2092 mutex_init(&aux->hw_mutex);
2093 mutex_init(&aux->cec.lock);
2094 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
2095
2096 aux->ddc.algo = &drm_dp_i2c_algo;
2097 aux->ddc.algo_data = aux;
2098 aux->ddc.retries = 3;
2099
2100 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
2101}
2102EXPORT_SYMBOL(drm_dp_aux_init);
2103
2104/**
2105 * drm_dp_aux_register() - initialise and register aux channel
2106 * @aux: DisplayPort AUX channel
2107 *
2108 * Automatically calls drm_dp_aux_init() if this hasn't been done yet. This
2109 * should only be called once the parent of @aux, &drm_dp_aux.dev, is
2110 * initialized. For devices which are grandparents of their AUX channels,
2111 * &drm_dp_aux.dev will typically be the &drm_connector &device which
2112 * corresponds to @aux. For these devices, it's advised to call
2113 * drm_dp_aux_register() in &drm_connector_funcs.late_register, and likewise to
2114 * call drm_dp_aux_unregister() in &drm_connector_funcs.early_unregister.
2115 * Functions which don't follow this will likely Oops when
2116 * %CONFIG_DRM_DP_AUX_CHARDEV is enabled.
2117 *
2118 * For devices where the AUX channel is a device that exists independently of
2119 * the &drm_device that uses it, such as SoCs and bridge devices, it is
2120 * recommended to call drm_dp_aux_register() after a &drm_device has been
2121 * assigned to &drm_dp_aux.drm_dev, and likewise to call
2122 * drm_dp_aux_unregister() once the &drm_device should no longer be associated
2123 * with the AUX channel (e.g. on bridge detach).
2124 *
2125 * Drivers which need to use the aux channel before either of the two points
2126 * mentioned above need to call drm_dp_aux_init() in order to use the AUX
2127 * channel before registration.
2128 *
2129 * Returns 0 on success or a negative error code on failure.
2130 */
2131int drm_dp_aux_register(struct drm_dp_aux *aux)
2132{
2133 int ret;
2134
2135 WARN_ON_ONCE(!aux->drm_dev);
2136
2137 if (!aux->ddc.algo)
2138 drm_dp_aux_init(aux);
2139
2140 aux->ddc.owner = THIS_MODULE;
2141 aux->ddc.dev.parent = aux->dev;
2142
2143 strscpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
2144 sizeof(aux->ddc.name));
2145
2146 ret = drm_dp_aux_register_devnode(aux);
2147 if (ret)
2148 return ret;
2149
2150 ret = i2c_add_adapter(&aux->ddc);
2151 if (ret) {
2152 drm_dp_aux_unregister_devnode(aux);
2153 return ret;
2154 }
2155
2156 return 0;
2157}
2158EXPORT_SYMBOL(drm_dp_aux_register);
2159
2160/**
2161 * drm_dp_aux_unregister() - unregister an AUX adapter
2162 * @aux: DisplayPort AUX channel
2163 */
2164void drm_dp_aux_unregister(struct drm_dp_aux *aux)
2165{
2166 drm_dp_aux_unregister_devnode(aux);
2167 i2c_del_adapter(&aux->ddc);
2168}
2169EXPORT_SYMBOL(drm_dp_aux_unregister);
2170
2171#define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
2172
2173/**
2174 * drm_dp_psr_setup_time() - PSR setup in time usec
2175 * @psr_cap: PSR capabilities from DPCD
2176 *
2177 * Returns:
2178 * PSR setup time for the panel in microseconds, negative
2179 * error code on failure.
2180 */
2181int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
2182{
2183 static const u16 psr_setup_time_us[] = {
2184 PSR_SETUP_TIME(330),
2185 PSR_SETUP_TIME(275),
2186 PSR_SETUP_TIME(220),
2187 PSR_SETUP_TIME(165),
2188 PSR_SETUP_TIME(110),
2189 PSR_SETUP_TIME(55),
2190 PSR_SETUP_TIME(0),
2191 };
2192 int i;
2193
2194 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
2195 if (i >= ARRAY_SIZE(psr_setup_time_us))
2196 return -EINVAL;
2197
2198 return psr_setup_time_us[i];
2199}
2200EXPORT_SYMBOL(drm_dp_psr_setup_time);
2201
2202#undef PSR_SETUP_TIME
2203
2204/**
2205 * drm_dp_start_crc() - start capture of frame CRCs
2206 * @aux: DisplayPort AUX channel
2207 * @crtc: CRTC displaying the frames whose CRCs are to be captured
2208 *
2209 * Returns 0 on success or a negative error code on failure.
2210 */
2211int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
2212{
2213 u8 buf;
2214 int ret;
2215
2216 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
2217 if (ret < 0)
2218 return ret;
2219
2220 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);
2221 if (ret < 0)
2222 return ret;
2223
2224 aux->crc_count = 0;
2225 aux->crtc = crtc;
2226 schedule_work(&aux->crc_work);
2227
2228 return 0;
2229}
2230EXPORT_SYMBOL(drm_dp_start_crc);
2231
2232/**
2233 * drm_dp_stop_crc() - stop capture of frame CRCs
2234 * @aux: DisplayPort AUX channel
2235 *
2236 * Returns 0 on success or a negative error code on failure.
2237 */
2238int drm_dp_stop_crc(struct drm_dp_aux *aux)
2239{
2240 u8 buf;
2241 int ret;
2242
2243 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
2244 if (ret < 0)
2245 return ret;
2246
2247 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START);
2248 if (ret < 0)
2249 return ret;
2250
2251 flush_work(&aux->crc_work);
2252 aux->crtc = NULL;
2253
2254 return 0;
2255}
2256EXPORT_SYMBOL(drm_dp_stop_crc);
2257
2258struct dpcd_quirk {
2259 u8 oui[3];
2260 u8 device_id[6];
2261 bool is_branch;
2262 u32 quirks;
2263};
2264
2265#define OUI(first, second, third) { (first), (second), (third) }
2266#define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
2267 { (first), (second), (third), (fourth), (fifth), (sixth) }
2268
2269#define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0)
2270
2271static const struct dpcd_quirk dpcd_quirk_list[] = {
2272 /* Analogix 7737 needs reduced M and N at HBR2 link rates */
2273 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
2274 /* LG LP140WF6-SPM1 eDP panel */
2275 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
2276 /* Apple panels need some additional handling to support PSR */
2277 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
2278 /* CH7511 seems to leave SINK_COUNT zeroed */
2279 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
2280 /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
2281 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
2282 /* Synaptics DP1.4 MST hubs require DSC for some modes on which it applies HBLANK expansion. */
2283 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
2284 /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
2285 { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
2286};
2287
2288#undef OUI
2289
2290/*
2291 * Get a bit mask of DPCD quirks for the sink/branch device identified by
2292 * ident. The quirk data is shared but it's up to the drivers to act on the
2293 * data.
2294 *
2295 * For now, only the OUI (first three bytes) is used, but this may be extended
2296 * to device identification string and hardware/firmware revisions later.
2297 */
2298static u32
2299drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
2300{
2301 const struct dpcd_quirk *quirk;
2302 u32 quirks = 0;
2303 int i;
2304 u8 any_device[] = DEVICE_ID_ANY;
2305
2306 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
2307 quirk = &dpcd_quirk_list[i];
2308
2309 if (quirk->is_branch != is_branch)
2310 continue;
2311
2312 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
2313 continue;
2314
2315 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 &&
2316 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0)
2317 continue;
2318
2319 quirks |= quirk->quirks;
2320 }
2321
2322 return quirks;
2323}
2324
2325#undef DEVICE_ID_ANY
2326#undef DEVICE_ID
2327
2328/**
2329 * drm_dp_read_desc - read sink/branch descriptor from DPCD
2330 * @aux: DisplayPort AUX channel
2331 * @desc: Device descriptor to fill from DPCD
2332 * @is_branch: true for branch devices, false for sink devices
2333 *
2334 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
2335 * identification.
2336 *
2337 * Returns 0 on success or a negative error code on failure.
2338 */
2339int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
2340 bool is_branch)
2341{
2342 struct drm_dp_dpcd_ident *ident = &desc->ident;
2343 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
2344 int ret, dev_id_len;
2345
2346 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
2347 if (ret < 0)
2348 return ret;
2349
2350 desc->quirks = drm_dp_get_quirks(ident, is_branch);
2351
2352 dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
2353
2354 drm_dbg_kms(aux->drm_dev,
2355 "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
2356 aux->name, is_branch ? "branch" : "sink",
2357 (int)sizeof(ident->oui), ident->oui, dev_id_len,
2358 ident->device_id, ident->hw_rev >> 4, ident->hw_rev & 0xf,
2359 ident->sw_major_rev, ident->sw_minor_rev, desc->quirks);
2360
2361 return 0;
2362}
2363EXPORT_SYMBOL(drm_dp_read_desc);
2364
2365/**
2366 * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
2367 * @dsc_dpcd: DSC capabilities from DPCD
2368 *
2369 * Returns the bpp precision supported by the DP sink.
2370 */
2371u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
2372{
2373 u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
2374
2375 switch (bpp_increment_dpcd) {
2376 case DP_DSC_BITS_PER_PIXEL_1_16:
2377 return 16;
2378 case DP_DSC_BITS_PER_PIXEL_1_8:
2379 return 8;
2380 case DP_DSC_BITS_PER_PIXEL_1_4:
2381 return 4;
2382 case DP_DSC_BITS_PER_PIXEL_1_2:
2383 return 2;
2384 case DP_DSC_BITS_PER_PIXEL_1_1:
2385 return 1;
2386 }
2387
2388 return 0;
2389}
2390EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
2391
2392/**
2393 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
2394 * supported by the DSC sink.
2395 * @dsc_dpcd: DSC capabilities from DPCD
2396 * @is_edp: true if its eDP, false for DP
2397 *
2398 * Read the slice capabilities DPCD register from DSC sink to get
2399 * the maximum slice count supported. This is used to populate
2400 * the DSC parameters in the &struct drm_dsc_config by the driver.
2401 * Driver creates an infoframe using these parameters to populate
2402 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2403 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2404 *
2405 * Returns:
2406 * Maximum slice count supported by DSC sink or 0 its invalid
2407 */
2408u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2409 bool is_edp)
2410{
2411 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
2412
2413 if (is_edp) {
2414 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
2415 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2416 return 4;
2417 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2418 return 2;
2419 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2420 return 1;
2421 } else {
2422 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
2423 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
2424
2425 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
2426 return 24;
2427 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
2428 return 20;
2429 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
2430 return 16;
2431 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
2432 return 12;
2433 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
2434 return 10;
2435 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
2436 return 8;
2437 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
2438 return 6;
2439 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2440 return 4;
2441 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2442 return 2;
2443 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2444 return 1;
2445 }
2446
2447 return 0;
2448}
2449EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
2450
2451/**
2452 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
2453 * @dsc_dpcd: DSC capabilities from DPCD
2454 *
2455 * Read the DSC DPCD register to parse the line buffer depth in bits which is
2456 * number of bits of precision within the decoder line buffer supported by
2457 * the DSC sink. This is used to populate the DSC parameters in the
2458 * &struct drm_dsc_config by the driver.
2459 * Driver creates an infoframe using these parameters to populate
2460 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2461 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2462 *
2463 * Returns:
2464 * Line buffer depth supported by DSC panel or 0 its invalid
2465 */
2466u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
2467{
2468 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
2469
2470 switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
2471 case DP_DSC_LINE_BUF_BIT_DEPTH_9:
2472 return 9;
2473 case DP_DSC_LINE_BUF_BIT_DEPTH_10:
2474 return 10;
2475 case DP_DSC_LINE_BUF_BIT_DEPTH_11:
2476 return 11;
2477 case DP_DSC_LINE_BUF_BIT_DEPTH_12:
2478 return 12;
2479 case DP_DSC_LINE_BUF_BIT_DEPTH_13:
2480 return 13;
2481 case DP_DSC_LINE_BUF_BIT_DEPTH_14:
2482 return 14;
2483 case DP_DSC_LINE_BUF_BIT_DEPTH_15:
2484 return 15;
2485 case DP_DSC_LINE_BUF_BIT_DEPTH_16:
2486 return 16;
2487 case DP_DSC_LINE_BUF_BIT_DEPTH_8:
2488 return 8;
2489 }
2490
2491 return 0;
2492}
2493EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
2494
2495/**
2496 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
2497 * values supported by the DSC sink.
2498 * @dsc_dpcd: DSC capabilities from DPCD
2499 * @dsc_bpc: An array to be filled by this helper with supported
2500 * input bpcs.
2501 *
2502 * Read the DSC DPCD from the sink device to parse the supported bits per
2503 * component values. This is used to populate the DSC parameters
2504 * in the &struct drm_dsc_config by the driver.
2505 * Driver creates an infoframe using these parameters to populate
2506 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2507 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2508 *
2509 * Returns:
2510 * Number of input BPC values parsed from the DPCD
2511 */
2512int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2513 u8 dsc_bpc[3])
2514{
2515 int num_bpc = 0;
2516 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
2517
2518 if (!drm_dp_sink_supports_dsc(dsc_dpcd))
2519 return 0;
2520
2521 if (color_depth & DP_DSC_12_BPC)
2522 dsc_bpc[num_bpc++] = 12;
2523 if (color_depth & DP_DSC_10_BPC)
2524 dsc_bpc[num_bpc++] = 10;
2525
2526 /* A DP DSC Sink device shall support 8 bpc. */
2527 dsc_bpc[num_bpc++] = 8;
2528
2529 return num_bpc;
2530}
2531EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
2532
2533static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,
2534 const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
2535 u8 *buf, int buf_size)
2536{
2537 /*
2538 * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns
2539 * corrupted values when reading from the 0xF0000- range with a block
2540 * size bigger than 1.
2541 */
2542 int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
2543 int offset;
2544 int ret;
2545
2546 for (offset = 0; offset < buf_size; offset += block_size) {
2547 ret = drm_dp_dpcd_read(aux,
2548 address + offset,
2549 &buf[offset], block_size);
2550 if (ret < 0)
2551 return ret;
2552
2553 WARN_ON(ret != block_size);
2554 }
2555
2556 return 0;
2557}
2558
2559/**
2560 * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
2561 * @aux: DisplayPort AUX channel
2562 * @dpcd: DisplayPort configuration data
2563 * @caps: buffer to return the capability info in
2564 *
2565 * Read capabilities common to all LTTPRs.
2566 *
2567 * Returns 0 on success or a negative error code on failure.
2568 */
2569int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
2570 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2571 u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2572{
2573 return drm_dp_read_lttpr_regs(aux, dpcd,
2574 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
2575 caps, DP_LTTPR_COMMON_CAP_SIZE);
2576}
2577EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
2578
2579/**
2580 * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
2581 * @aux: DisplayPort AUX channel
2582 * @dpcd: DisplayPort configuration data
2583 * @dp_phy: LTTPR PHY to read the capabilities for
2584 * @caps: buffer to return the capability info in
2585 *
2586 * Read the capabilities for the given LTTPR PHY.
2587 *
2588 * Returns 0 on success or a negative error code on failure.
2589 */
2590int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
2591 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2592 enum drm_dp_phy dp_phy,
2593 u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2594{
2595 return drm_dp_read_lttpr_regs(aux, dpcd,
2596 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
2597 caps, DP_LTTPR_PHY_CAP_SIZE);
2598}
2599EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
2600
2601static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r)
2602{
2603 return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
2604}
2605
2606/**
2607 * drm_dp_lttpr_count - get the number of detected LTTPRs
2608 * @caps: LTTPR common capabilities
2609 *
2610 * Get the number of detected LTTPRs from the LTTPR common capabilities info.
2611 *
2612 * Returns:
2613 * -ERANGE if more than supported number (8) of LTTPRs are detected
2614 * -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value
2615 * otherwise the number of detected LTTPRs
2616 */
2617int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2618{
2619 u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT);
2620
2621 switch (hweight8(count)) {
2622 case 0:
2623 return 0;
2624 case 1:
2625 return 8 - ilog2(count);
2626 case 8:
2627 return -ERANGE;
2628 default:
2629 return -EINVAL;
2630 }
2631}
2632EXPORT_SYMBOL(drm_dp_lttpr_count);
2633
2634/**
2635 * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs
2636 * @caps: LTTPR common capabilities
2637 *
2638 * Returns the maximum link rate supported by all detected LTTPRs.
2639 */
2640int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2641{
2642 u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER);
2643
2644 return drm_dp_bw_code_to_link_rate(rate);
2645}
2646EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate);
2647
2648/**
2649 * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs
2650 * @caps: LTTPR common capabilities
2651 *
2652 * Returns the maximum lane count supported by all detected LTTPRs.
2653 */
2654int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2655{
2656 u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER);
2657
2658 return max_lanes & DP_MAX_LANE_COUNT_MASK;
2659}
2660EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count);
2661
2662/**
2663 * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support
2664 * @caps: LTTPR PHY capabilities
2665 *
2666 * Returns true if the @caps for an LTTPR TX PHY indicate support for
2667 * voltage swing level 3.
2668 */
2669bool
2670drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2671{
2672 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
2673
2674 return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED;
2675}
2676EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported);
2677
2678/**
2679 * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support
2680 * @caps: LTTPR PHY capabilities
2681 *
2682 * Returns true if the @caps for an LTTPR TX PHY indicate support for
2683 * pre-emphasis level 3.
2684 */
2685bool
2686drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2687{
2688 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
2689
2690 return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED;
2691}
2692EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported);
2693
2694/**
2695 * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
2696 * @aux: DisplayPort AUX channel
2697 * @data: DP phy compliance test parameters.
2698 *
2699 * Returns 0 on success or a negative error code on failure.
2700 */
2701int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
2702 struct drm_dp_phy_test_params *data)
2703{
2704 int err;
2705 u8 rate, lanes;
2706
2707 err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
2708 if (err < 0)
2709 return err;
2710 data->link_rate = drm_dp_bw_code_to_link_rate(rate);
2711
2712 err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
2713 if (err < 0)
2714 return err;
2715 data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
2716
2717 if (lanes & DP_ENHANCED_FRAME_CAP)
2718 data->enhanced_frame_cap = true;
2719
2720 err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
2721 if (err < 0)
2722 return err;
2723
2724 switch (data->phy_pattern) {
2725 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
2726 err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2727 &data->custom80, sizeof(data->custom80));
2728 if (err < 0)
2729 return err;
2730
2731 break;
2732 case DP_PHY_TEST_PATTERN_CP2520:
2733 err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
2734 &data->hbr2_reset,
2735 sizeof(data->hbr2_reset));
2736 if (err < 0)
2737 return err;
2738 }
2739
2740 return 0;
2741}
2742EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
2743
2744/**
2745 * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
2746 * @aux: DisplayPort AUX channel
2747 * @data: DP phy compliance test parameters.
2748 * @dp_rev: DP revision to use for compliance testing
2749 *
2750 * Returns 0 on success or a negative error code on failure.
2751 */
2752int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
2753 struct drm_dp_phy_test_params *data, u8 dp_rev)
2754{
2755 int err, i;
2756 u8 test_pattern;
2757
2758 test_pattern = data->phy_pattern;
2759 if (dp_rev < 0x12) {
2760 test_pattern = (test_pattern << 2) &
2761 DP_LINK_QUAL_PATTERN_11_MASK;
2762 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
2763 test_pattern);
2764 if (err < 0)
2765 return err;
2766 } else {
2767 for (i = 0; i < data->num_lanes; i++) {
2768 err = drm_dp_dpcd_writeb(aux,
2769 DP_LINK_QUAL_LANE0_SET + i,
2770 test_pattern);
2771 if (err < 0)
2772 return err;
2773 }
2774 }
2775
2776 return 0;
2777}
2778EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
2779
2780static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
2781{
2782 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
2783 return "Invalid";
2784
2785 switch (pixelformat) {
2786 case DP_PIXELFORMAT_RGB:
2787 return "RGB";
2788 case DP_PIXELFORMAT_YUV444:
2789 return "YUV444";
2790 case DP_PIXELFORMAT_YUV422:
2791 return "YUV422";
2792 case DP_PIXELFORMAT_YUV420:
2793 return "YUV420";
2794 case DP_PIXELFORMAT_Y_ONLY:
2795 return "Y_ONLY";
2796 case DP_PIXELFORMAT_RAW:
2797 return "RAW";
2798 default:
2799 return "Reserved";
2800 }
2801}
2802
2803static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
2804 enum dp_colorimetry colorimetry)
2805{
2806 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
2807 return "Invalid";
2808
2809 switch (colorimetry) {
2810 case DP_COLORIMETRY_DEFAULT:
2811 switch (pixelformat) {
2812 case DP_PIXELFORMAT_RGB:
2813 return "sRGB";
2814 case DP_PIXELFORMAT_YUV444:
2815 case DP_PIXELFORMAT_YUV422:
2816 case DP_PIXELFORMAT_YUV420:
2817 return "BT.601";
2818 case DP_PIXELFORMAT_Y_ONLY:
2819 return "DICOM PS3.14";
2820 case DP_PIXELFORMAT_RAW:
2821 return "Custom Color Profile";
2822 default:
2823 return "Reserved";
2824 }
2825 case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
2826 switch (pixelformat) {
2827 case DP_PIXELFORMAT_RGB:
2828 return "Wide Fixed";
2829 case DP_PIXELFORMAT_YUV444:
2830 case DP_PIXELFORMAT_YUV422:
2831 case DP_PIXELFORMAT_YUV420:
2832 return "BT.709";
2833 default:
2834 return "Reserved";
2835 }
2836 case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
2837 switch (pixelformat) {
2838 case DP_PIXELFORMAT_RGB:
2839 return "Wide Float";
2840 case DP_PIXELFORMAT_YUV444:
2841 case DP_PIXELFORMAT_YUV422:
2842 case DP_PIXELFORMAT_YUV420:
2843 return "xvYCC 601";
2844 default:
2845 return "Reserved";
2846 }
2847 case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
2848 switch (pixelformat) {
2849 case DP_PIXELFORMAT_RGB:
2850 return "OpRGB";
2851 case DP_PIXELFORMAT_YUV444:
2852 case DP_PIXELFORMAT_YUV422:
2853 case DP_PIXELFORMAT_YUV420:
2854 return "xvYCC 709";
2855 default:
2856 return "Reserved";
2857 }
2858 case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
2859 switch (pixelformat) {
2860 case DP_PIXELFORMAT_RGB:
2861 return "DCI-P3";
2862 case DP_PIXELFORMAT_YUV444:
2863 case DP_PIXELFORMAT_YUV422:
2864 case DP_PIXELFORMAT_YUV420:
2865 return "sYCC 601";
2866 default:
2867 return "Reserved";
2868 }
2869 case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
2870 switch (pixelformat) {
2871 case DP_PIXELFORMAT_RGB:
2872 return "Custom Profile";
2873 case DP_PIXELFORMAT_YUV444:
2874 case DP_PIXELFORMAT_YUV422:
2875 case DP_PIXELFORMAT_YUV420:
2876 return "OpYCC 601";
2877 default:
2878 return "Reserved";
2879 }
2880 case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
2881 switch (pixelformat) {
2882 case DP_PIXELFORMAT_RGB:
2883 return "BT.2020 RGB";
2884 case DP_PIXELFORMAT_YUV444:
2885 case DP_PIXELFORMAT_YUV422:
2886 case DP_PIXELFORMAT_YUV420:
2887 return "BT.2020 CYCC";
2888 default:
2889 return "Reserved";
2890 }
2891 case DP_COLORIMETRY_BT2020_YCC:
2892 switch (pixelformat) {
2893 case DP_PIXELFORMAT_YUV444:
2894 case DP_PIXELFORMAT_YUV422:
2895 case DP_PIXELFORMAT_YUV420:
2896 return "BT.2020 YCC";
2897 default:
2898 return "Reserved";
2899 }
2900 default:
2901 return "Invalid";
2902 }
2903}
2904
2905static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
2906{
2907 switch (dynamic_range) {
2908 case DP_DYNAMIC_RANGE_VESA:
2909 return "VESA range";
2910 case DP_DYNAMIC_RANGE_CTA:
2911 return "CTA range";
2912 default:
2913 return "Invalid";
2914 }
2915}
2916
2917static const char *dp_content_type_get_name(enum dp_content_type content_type)
2918{
2919 switch (content_type) {
2920 case DP_CONTENT_TYPE_NOT_DEFINED:
2921 return "Not defined";
2922 case DP_CONTENT_TYPE_GRAPHICS:
2923 return "Graphics";
2924 case DP_CONTENT_TYPE_PHOTO:
2925 return "Photo";
2926 case DP_CONTENT_TYPE_VIDEO:
2927 return "Video";
2928 case DP_CONTENT_TYPE_GAME:
2929 return "Game";
2930 default:
2931 return "Reserved";
2932 }
2933}
2934
2935void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc)
2936{
2937 drm_printf(p, "DP SDP: VSC, revision %u, length %u\n",
2938 vsc->revision, vsc->length);
2939 drm_printf(p, " pixelformat: %s\n",
2940 dp_pixelformat_get_name(vsc->pixelformat));
2941 drm_printf(p, " colorimetry: %s\n",
2942 dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry));
2943 drm_printf(p, " bpc: %u\n", vsc->bpc);
2944 drm_printf(p, " dynamic range: %s\n",
2945 dp_dynamic_range_get_name(vsc->dynamic_range));
2946 drm_printf(p, " content type: %s\n",
2947 dp_content_type_get_name(vsc->content_type));
2948}
2949EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
2950
2951/**
2952 * drm_dp_vsc_sdp_supported() - check if vsc sdp is supported
2953 * @aux: DisplayPort AUX channel
2954 * @dpcd: DisplayPort configuration data
2955 *
2956 * Returns true if vsc sdp is supported, else returns false
2957 */
2958bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
2959{
2960 u8 rx_feature;
2961
2962 if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13)
2963 return false;
2964
2965 if (drm_dp_dpcd_readb(aux, DP_DPRX_FEATURE_ENUMERATION_LIST, &rx_feature) != 1) {
2966 drm_dbg_dp(aux->drm_dev, "failed to read DP_DPRX_FEATURE_ENUMERATION_LIST\n");
2967 return false;
2968 }
2969
2970 return (rx_feature & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED);
2971}
2972EXPORT_SYMBOL(drm_dp_vsc_sdp_supported);
2973
2974/**
2975 * drm_dp_vsc_sdp_pack() - pack a given vsc sdp into generic dp_sdp
2976 * @vsc: vsc sdp initialized according to its purpose as defined in
2977 * table 2-118 - table 2-120 in DP 1.4a specification
2978 * @sdp: valid handle to the generic dp_sdp which will be packed
2979 *
2980 * Returns length of sdp on success and error code on failure
2981 */
2982ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
2983 struct dp_sdp *sdp)
2984{
2985 size_t length = sizeof(struct dp_sdp);
2986
2987 memset(sdp, 0, sizeof(struct dp_sdp));
2988
2989 /*
2990 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
2991 * VSC SDP Header Bytes
2992 */
2993 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
2994 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
2995 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
2996 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
2997
2998 if (vsc->revision == 0x6) {
2999 sdp->db[0] = 1;
3000 sdp->db[3] = 1;
3001 }
3002
3003 /*
3004 * Revision 0x5 and revision 0x7 supports Pixel Encoding/Colorimetry
3005 * Format as per DP 1.4a spec and DP 2.0 respectively.
3006 */
3007 if (!(vsc->revision == 0x5 || vsc->revision == 0x7))
3008 goto out;
3009
3010 /* VSC SDP Payload for DB16 through DB18 */
3011 /* Pixel Encoding and Colorimetry Formats */
3012 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3013 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3014
3015 switch (vsc->bpc) {
3016 case 6:
3017 /* 6bpc: 0x0 */
3018 break;
3019 case 8:
3020 sdp->db[17] = 0x1; /* DB17[3:0] */
3021 break;
3022 case 10:
3023 sdp->db[17] = 0x2;
3024 break;
3025 case 12:
3026 sdp->db[17] = 0x3;
3027 break;
3028 case 16:
3029 sdp->db[17] = 0x4;
3030 break;
3031 default:
3032 WARN(1, "Missing case %d\n", vsc->bpc);
3033 return -EINVAL;
3034 }
3035
3036 /* Dynamic Range and Component Bit Depth */
3037 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3038 sdp->db[17] |= 0x80; /* DB17[7] */
3039
3040 /* Content Type */
3041 sdp->db[18] = vsc->content_type & 0x7;
3042
3043out:
3044 return length;
3045}
3046EXPORT_SYMBOL(drm_dp_vsc_sdp_pack);
3047
3048/**
3049 * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
3050 * @dpcd: DisplayPort configuration data
3051 * @port_cap: port capabilities
3052 *
3053 * Returns maximum frl bandwidth supported by PCON in GBPS,
3054 * returns 0 if not supported.
3055 */
3056int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
3057 const u8 port_cap[4])
3058{
3059 int bw;
3060 u8 buf;
3061
3062 buf = port_cap[2];
3063 bw = buf & DP_PCON_MAX_FRL_BW;
3064
3065 switch (bw) {
3066 case DP_PCON_MAX_9GBPS:
3067 return 9;
3068 case DP_PCON_MAX_18GBPS:
3069 return 18;
3070 case DP_PCON_MAX_24GBPS:
3071 return 24;
3072 case DP_PCON_MAX_32GBPS:
3073 return 32;
3074 case DP_PCON_MAX_40GBPS:
3075 return 40;
3076 case DP_PCON_MAX_48GBPS:
3077 return 48;
3078 case DP_PCON_MAX_0GBPS:
3079 default:
3080 return 0;
3081 }
3082
3083 return 0;
3084}
3085EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw);
3086
3087/**
3088 * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL.
3089 * @aux: DisplayPort AUX channel
3090 * @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY.
3091 *
3092 * Returns 0 if success, else returns negative error code.
3093 */
3094int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd)
3095{
3096 int ret;
3097 u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE |
3098 DP_PCON_ENABLE_LINK_FRL_MODE;
3099
3100 if (enable_frl_ready_hpd)
3101 buf |= DP_PCON_ENABLE_HPD_READY;
3102
3103 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3104
3105 return ret;
3106}
3107EXPORT_SYMBOL(drm_dp_pcon_frl_prepare);
3108
3109/**
3110 * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL
3111 * @aux: DisplayPort AUX channel
3112 *
3113 * Returns true if success, else returns false.
3114 */
3115bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux)
3116{
3117 int ret;
3118 u8 buf;
3119
3120 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
3121 if (ret < 0)
3122 return false;
3123
3124 if (buf & DP_PCON_FRL_READY)
3125 return true;
3126
3127 return false;
3128}
3129EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
3130
3131/**
3132 * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
3133 * @aux: DisplayPort AUX channel
3134 * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
3135 * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
3136 * In Concurrent Mode, the FRL link bring up can be done along with
3137 * DP Link training. In Sequential mode, the FRL link bring up is done prior to
3138 * the DP Link training.
3139 *
3140 * Returns 0 if success, else returns negative error code.
3141 */
3142
3143int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
3144 u8 frl_mode)
3145{
3146 int ret;
3147 u8 buf;
3148
3149 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
3150 if (ret < 0)
3151 return ret;
3152
3153 if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK)
3154 buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
3155 else
3156 buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
3157
3158 switch (max_frl_gbps) {
3159 case 9:
3160 buf |= DP_PCON_ENABLE_MAX_BW_9GBPS;
3161 break;
3162 case 18:
3163 buf |= DP_PCON_ENABLE_MAX_BW_18GBPS;
3164 break;
3165 case 24:
3166 buf |= DP_PCON_ENABLE_MAX_BW_24GBPS;
3167 break;
3168 case 32:
3169 buf |= DP_PCON_ENABLE_MAX_BW_32GBPS;
3170 break;
3171 case 40:
3172 buf |= DP_PCON_ENABLE_MAX_BW_40GBPS;
3173 break;
3174 case 48:
3175 buf |= DP_PCON_ENABLE_MAX_BW_48GBPS;
3176 break;
3177 case 0:
3178 buf |= DP_PCON_ENABLE_MAX_BW_0GBPS;
3179 break;
3180 default:
3181 return -EINVAL;
3182 }
3183
3184 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3185 if (ret < 0)
3186 return ret;
3187
3188 return 0;
3189}
3190EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
3191
3192/**
3193 * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
3194 * @aux: DisplayPort AUX channel
3195 * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
3196 * @frl_type : FRL training type, can be Extended, or Normal.
3197 * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask
3198 * starting from min, and stops when link training is successful. In Extended
3199 * FRL training, all frl bw selected in the mask are trained by the PCON.
3200 *
3201 * Returns 0 if success, else returns negative error code.
3202 */
3203int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
3204 u8 frl_type)
3205{
3206 int ret;
3207 u8 buf = max_frl_mask;
3208
3209 if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED)
3210 buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
3211 else
3212 buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
3213
3214 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
3215 if (ret < 0)
3216 return ret;
3217
3218 return 0;
3219}
3220EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2);
3221
3222/**
3223 * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration.
3224 * @aux: DisplayPort AUX channel
3225 *
3226 * Returns 0 if success, else returns negative error code.
3227 */
3228int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux)
3229{
3230 int ret;
3231
3232 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0);
3233 if (ret < 0)
3234 return ret;
3235
3236 return 0;
3237}
3238EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config);
3239
3240/**
3241 * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL
3242 * @aux: DisplayPort AUX channel
3243 *
3244 * Returns 0 if success, else returns negative error code.
3245 */
3246int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux)
3247{
3248 int ret;
3249 u8 buf = 0;
3250
3251 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
3252 if (ret < 0)
3253 return ret;
3254 if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) {
3255 drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n",
3256 aux->name);
3257 return -EINVAL;
3258 }
3259 buf |= DP_PCON_ENABLE_HDMI_LINK;
3260 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3261 if (ret < 0)
3262 return ret;
3263
3264 return 0;
3265}
3266EXPORT_SYMBOL(drm_dp_pcon_frl_enable);
3267
3268/**
3269 * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active.
3270 * @aux: DisplayPort AUX channel
3271 *
3272 * Returns true if link is active else returns false.
3273 */
3274bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux)
3275{
3276 u8 buf;
3277 int ret;
3278
3279 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
3280 if (ret < 0)
3281 return false;
3282
3283 return buf & DP_PCON_HDMI_TX_LINK_ACTIVE;
3284}
3285EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active);
3286
3287/**
3288 * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE
3289 * @aux: DisplayPort AUX channel
3290 * @frl_trained_mask: pointer to store bitmask of the trained bw configuration.
3291 * Valid only if the MODE returned is FRL. For Normal Link training mode
3292 * only 1 of the bits will be set, but in case of Extended mode, more than
3293 * one bits can be set.
3294 *
3295 * Returns the link mode : TMDS or FRL on success, else returns negative error
3296 * code.
3297 */
3298int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask)
3299{
3300 u8 buf;
3301 int mode;
3302 int ret;
3303
3304 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS, &buf);
3305 if (ret < 0)
3306 return ret;
3307
3308 mode = buf & DP_PCON_HDMI_LINK_MODE;
3309
3310 if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode)
3311 *frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW) >> 1;
3312
3313 return mode;
3314}
3315EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode);
3316
3317/**
3318 * drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane
3319 * during link failure between PCON and HDMI sink
3320 * @aux: DisplayPort AUX channel
3321 * @connector: DRM connector
3322 * code.
3323 **/
3324
3325void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
3326 struct drm_connector *connector)
3327{
3328 u8 buf, error_count;
3329 int i, num_error;
3330 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3331
3332 for (i = 0; i < hdmi->max_lanes; i++) {
3333 if (drm_dp_dpcd_readb(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, &buf) < 0)
3334 return;
3335
3336 error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK;
3337 switch (error_count) {
3338 case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS:
3339 num_error = 100;
3340 break;
3341 case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS:
3342 num_error = 10;
3343 break;
3344 case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS:
3345 num_error = 3;
3346 break;
3347 default:
3348 num_error = 0;
3349 }
3350
3351 drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d",
3352 aux->name, num_error, i);
3353 }
3354}
3355EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
3356
3357/*
3358 * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2
3359 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3360 *
3361 * Returns true is PCON encoder is DSC 1.2 else returns false.
3362 */
3363bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3364{
3365 u8 buf;
3366 u8 major_v, minor_v;
3367
3368 buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER];
3369 major_v = (buf & DP_PCON_DSC_MAJOR_MASK) >> DP_PCON_DSC_MAJOR_SHIFT;
3370 minor_v = (buf & DP_PCON_DSC_MINOR_MASK) >> DP_PCON_DSC_MINOR_SHIFT;
3371
3372 if (major_v == 1 && minor_v == 2)
3373 return true;
3374
3375 return false;
3376}
3377EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2);
3378
3379/*
3380 * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder
3381 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3382 *
3383 * Returns maximum no. of slices supported by the PCON DSC Encoder.
3384 */
3385int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3386{
3387 u8 slice_cap1, slice_cap2;
3388
3389 slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER];
3390 slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER];
3391
3392 if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC)
3393 return 24;
3394 if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC)
3395 return 20;
3396 if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC)
3397 return 16;
3398 if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC)
3399 return 12;
3400 if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC)
3401 return 10;
3402 if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC)
3403 return 8;
3404 if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC)
3405 return 6;
3406 if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC)
3407 return 4;
3408 if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC)
3409 return 2;
3410 if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC)
3411 return 1;
3412
3413 return 0;
3414}
3415EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices);
3416
3417/*
3418 * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder
3419 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3420 *
3421 * Returns maximum width of the slices in pixel width i.e. no. of pixels x 320.
3422 */
3423int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3424{
3425 u8 buf;
3426
3427 buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER];
3428
3429 return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER;
3430}
3431EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width);
3432
3433/*
3434 * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder
3435 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3436 *
3437 * Returns the bpp precision supported by the PCON encoder.
3438 */
3439int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3440{
3441 u8 buf;
3442
3443 buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER];
3444
3445 switch (buf & DP_PCON_DSC_BPP_INCR_MASK) {
3446 case DP_PCON_DSC_ONE_16TH_BPP:
3447 return 16;
3448 case DP_PCON_DSC_ONE_8TH_BPP:
3449 return 8;
3450 case DP_PCON_DSC_ONE_4TH_BPP:
3451 return 4;
3452 case DP_PCON_DSC_ONE_HALF_BPP:
3453 return 2;
3454 case DP_PCON_DSC_ONE_BPP:
3455 return 1;
3456 }
3457
3458 return 0;
3459}
3460EXPORT_SYMBOL(drm_dp_pcon_dsc_bpp_incr);
3461
3462static
3463int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config)
3464{
3465 u8 buf;
3466 int ret;
3467
3468 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);
3469 if (ret < 0)
3470 return ret;
3471
3472 buf |= DP_PCON_ENABLE_DSC_ENCODER;
3473
3474 if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) {
3475 buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK;
3476 buf |= pps_buf_config << 2;
3477 }
3478
3479 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
3480 if (ret < 0)
3481 return ret;
3482
3483 return 0;
3484}
3485
3486/**
3487 * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters
3488 * for DSC1.2 between PCON & HDMI2.1 sink
3489 * @aux: DisplayPort AUX channel
3490 *
3491 * Returns 0 on success, else returns negative error code.
3492 */
3493int drm_dp_pcon_pps_default(struct drm_dp_aux *aux)
3494{
3495 int ret;
3496
3497 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED);
3498 if (ret < 0)
3499 return ret;
3500
3501 return 0;
3502}
3503EXPORT_SYMBOL(drm_dp_pcon_pps_default);
3504
3505/**
3506 * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for
3507 * HDMI sink
3508 * @aux: DisplayPort AUX channel
3509 * @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON.
3510 *
3511 * Returns 0 on success, else returns negative error code.
3512 */
3513int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128])
3514{
3515 int ret;
3516
3517 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, &pps_buf, 128);
3518 if (ret < 0)
3519 return ret;
3520
3521 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
3522 if (ret < 0)
3523 return ret;
3524
3525 return 0;
3526}
3527EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf);
3528
3529/*
3530 * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder
3531 * override registers
3532 * @aux: DisplayPort AUX channel
3533 * @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height,
3534 * bits_per_pixel.
3535 *
3536 * Returns 0 on success, else returns negative error code.
3537 */
3538int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6])
3539{
3540 int ret;
3541
3542 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2);
3543 if (ret < 0)
3544 return ret;
3545 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[2], 2);
3546 if (ret < 0)
3547 return ret;
3548 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP, &pps_param[4], 2);
3549 if (ret < 0)
3550 return ret;
3551
3552 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
3553 if (ret < 0)
3554 return ret;
3555
3556 return 0;
3557}
3558EXPORT_SYMBOL(drm_dp_pcon_pps_override_param);
3559
3560/*
3561 * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr
3562 * @aux: displayPort AUX channel
3563 * @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable.
3564 *
3565 * Returns 0 on success, else returns negative error code.
3566 */
3567int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
3568{
3569 int ret;
3570 u8 buf;
3571
3572 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);
3573 if (ret < 0)
3574 return ret;
3575
3576 if (color_spc & DP_CONVERSION_RGB_YCBCR_MASK)
3577 buf |= (color_spc & DP_CONVERSION_RGB_YCBCR_MASK);
3578 else
3579 buf &= ~DP_CONVERSION_RGB_YCBCR_MASK;
3580
3581 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
3582 if (ret < 0)
3583 return ret;
3584
3585 return 0;
3586}
3587EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
3588
3589/**
3590 * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
3591 * @aux: The DP AUX channel to use
3592 * @bl: Backlight capability info from drm_edp_backlight_init()
3593 * @level: The brightness level to set
3594 *
3595 * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must
3596 * already have been enabled by the driver by calling drm_edp_backlight_enable().
3597 *
3598 * Returns: %0 on success, negative error code on failure
3599 */
3600int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3601 u16 level)
3602{
3603 int ret;
3604 u8 buf[2] = { 0 };
3605
3606 /* The panel uses the PWM for controlling brightness levels */
3607 if (!bl->aux_set)
3608 return 0;
3609
3610 if (bl->lsb_reg_used) {
3611 buf[0] = (level & 0xff00) >> 8;
3612 buf[1] = (level & 0x00ff);
3613 } else {
3614 buf[0] = level;
3615 }
3616
3617 ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf));
3618 if (ret != sizeof(buf)) {
3619 drm_err(aux->drm_dev,
3620 "%s: Failed to write aux backlight level: %d\n",
3621 aux->name, ret);
3622 return ret < 0 ? ret : -EIO;
3623 }
3624
3625 return 0;
3626}
3627EXPORT_SYMBOL(drm_edp_backlight_set_level);
3628
3629static int
3630drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3631 bool enable)
3632{
3633 int ret;
3634 u8 buf;
3635
3636 /* This panel uses the EDP_BL_PWR GPIO for enablement */
3637 if (!bl->aux_enable)
3638 return 0;
3639
3640 ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf);
3641 if (ret != 1) {
3642 drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n",
3643 aux->name, ret);
3644 return ret < 0 ? ret : -EIO;
3645 }
3646 if (enable)
3647 buf |= DP_EDP_BACKLIGHT_ENABLE;
3648 else
3649 buf &= ~DP_EDP_BACKLIGHT_ENABLE;
3650
3651 ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf);
3652 if (ret != 1) {
3653 drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n",
3654 aux->name, ret);
3655 return ret < 0 ? ret : -EIO;
3656 }
3657
3658 return 0;
3659}
3660
3661/**
3662 * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
3663 * @aux: The DP AUX channel to use
3664 * @bl: Backlight capability info from drm_edp_backlight_init()
3665 * @level: The initial backlight level to set via AUX, if there is one
3666 *
3667 * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally
3668 * restoring any important backlight state such as the given backlight level, the brightness byte
3669 * count, backlight frequency, etc.
3670 *
3671 * Note that certain panels do not support being enabled or disabled via DPCD, but instead require
3672 * that the driver handle enabling/disabling the panel through implementation-specific means using
3673 * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false,
3674 * this function becomes a no-op, and the driver is expected to handle powering the panel on using
3675 * the EDP_BL_PWR GPIO.
3676 *
3677 * Returns: %0 on success, negative error code on failure.
3678 */
3679int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3680 const u16 level)
3681{
3682 int ret;
3683 u8 dpcd_buf;
3684
3685 if (bl->aux_set)
3686 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
3687 else
3688 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_PWM;
3689
3690 if (bl->pwmgen_bit_count) {
3691 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count);
3692 if (ret != 1)
3693 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
3694 aux->name, ret);
3695 }
3696
3697 if (bl->pwm_freq_pre_divider) {
3698 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider);
3699 if (ret != 1)
3700 drm_dbg_kms(aux->drm_dev,
3701 "%s: Failed to write aux backlight frequency: %d\n",
3702 aux->name, ret);
3703 else
3704 dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
3705 }
3706
3707 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, dpcd_buf);
3708 if (ret != 1) {
3709 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n",
3710 aux->name, ret);
3711 return ret < 0 ? ret : -EIO;
3712 }
3713
3714 ret = drm_edp_backlight_set_level(aux, bl, level);
3715 if (ret < 0)
3716 return ret;
3717 ret = drm_edp_backlight_set_enable(aux, bl, true);
3718 if (ret < 0)
3719 return ret;
3720
3721 return 0;
3722}
3723EXPORT_SYMBOL(drm_edp_backlight_enable);
3724
3725/**
3726 * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
3727 * @aux: The DP AUX channel to use
3728 * @bl: Backlight capability info from drm_edp_backlight_init()
3729 *
3730 * This function handles disabling DPCD backlight controls on a panel over AUX.
3731 *
3732 * Note that certain panels do not support being enabled or disabled via DPCD, but instead require
3733 * that the driver handle enabling/disabling the panel through implementation-specific means using
3734 * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false,
3735 * this function becomes a no-op, and the driver is expected to handle powering the panel off using
3736 * the EDP_BL_PWR GPIO.
3737 *
3738 * Returns: %0 on success or no-op, negative error code on failure.
3739 */
3740int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl)
3741{
3742 int ret;
3743
3744 ret = drm_edp_backlight_set_enable(aux, bl, false);
3745 if (ret < 0)
3746 return ret;
3747
3748 return 0;
3749}
3750EXPORT_SYMBOL(drm_edp_backlight_disable);
3751
3752static inline int
3753drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
3754 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
3755{
3756 int fxp, fxp_min, fxp_max, fxp_actual, f = 1;
3757 int ret;
3758 u8 pn, pn_min, pn_max;
3759
3760 if (!bl->aux_set)
3761 return 0;
3762
3763 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
3764 if (ret != 1) {
3765 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",
3766 aux->name, ret);
3767 return -ENODEV;
3768 }
3769
3770 pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
3771 bl->max = (1 << pn) - 1;
3772 if (!driver_pwm_freq_hz)
3773 return 0;
3774
3775 /*
3776 * Set PWM Frequency divider to match desired frequency provided by the driver.
3777 * The PWM Frequency is calculated as 27Mhz / (F x P).
3778 * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
3779 * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
3780 * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
3781 * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
3782 */
3783
3784 /* Find desired value of (F x P)
3785 * Note that, if F x P is out of supported range, the maximum value or minimum value will
3786 * applied automatically. So no need to check that.
3787 */
3788 fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz);
3789
3790 /* Use highest possible value of Pn for more granularity of brightness adjustment while
3791 * satisfying the conditions below.
3792 * - Pn is in the range of Pn_min and Pn_max
3793 * - F is in the range of 1 and 255
3794 * - FxP is within 25% of desired value.
3795 * Note: 25% is arbitrary value and may need some tweak.
3796 */
3797 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
3798 if (ret != 1) {
3799 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n",
3800 aux->name, ret);
3801 return 0;
3802 }
3803 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
3804 if (ret != 1) {
3805 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n",
3806 aux->name, ret);
3807 return 0;
3808 }
3809 pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
3810 pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
3811
3812 /* Ensure frequency is within 25% of desired value */
3813 fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
3814 fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
3815 if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
3816 drm_dbg_kms(aux->drm_dev,
3817 "%s: Driver defined backlight frequency (%d) out of range\n",
3818 aux->name, driver_pwm_freq_hz);
3819 return 0;
3820 }
3821
3822 for (pn = pn_max; pn >= pn_min; pn--) {
3823 f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
3824 fxp_actual = f << pn;
3825 if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
3826 break;
3827 }
3828
3829 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
3830 if (ret != 1) {
3831 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
3832 aux->name, ret);
3833 return 0;
3834 }
3835 bl->pwmgen_bit_count = pn;
3836 bl->max = (1 << pn) - 1;
3837
3838 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) {
3839 bl->pwm_freq_pre_divider = f;
3840 drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n",
3841 aux->name, driver_pwm_freq_hz);
3842 }
3843
3844 return 0;
3845}
3846
3847static inline int
3848drm_edp_backlight_probe_state(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
3849 u8 *current_mode)
3850{
3851 int ret;
3852 u8 buf[2];
3853 u8 mode_reg;
3854
3855 ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
3856 if (ret != 1) {
3857 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n",
3858 aux->name, ret);
3859 return ret < 0 ? ret : -EIO;
3860 }
3861
3862 *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK);
3863 if (!bl->aux_set)
3864 return 0;
3865
3866 if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
3867 int size = 1 + bl->lsb_reg_used;
3868
3869 ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size);
3870 if (ret != size) {
3871 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n",
3872 aux->name, ret);
3873 return ret < 0 ? ret : -EIO;
3874 }
3875
3876 if (bl->lsb_reg_used)
3877 return (buf[0] << 8) | buf[1];
3878 else
3879 return buf[0];
3880 }
3881
3882 /*
3883 * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and
3884 * the driver should assume max brightness
3885 */
3886 return bl->max;
3887}
3888
3889/**
3890 * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
3891 * interface.
3892 * @aux: The DP aux device to use for probing
3893 * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight
3894 * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz
3895 * @edp_dpcd: A cached copy of the eDP DPCD
3896 * @current_level: Where to store the probed brightness level, if any
3897 * @current_mode: Where to store the currently set backlight control mode
3898 *
3899 * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities,
3900 * along with also probing the current and maximum supported brightness levels.
3901 *
3902 * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
3903 * default frequency from the panel is used.
3904 *
3905 * Returns: %0 on success, negative error code on failure.
3906 */
3907int
3908drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
3909 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
3910 u16 *current_level, u8 *current_mode)
3911{
3912 int ret;
3913
3914 if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
3915 bl->aux_enable = true;
3916 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)
3917 bl->aux_set = true;
3918 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
3919 bl->lsb_reg_used = true;
3920
3921 /* Sanity check caps */
3922 if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) {
3923 drm_dbg_kms(aux->drm_dev,
3924 "%s: Panel supports neither AUX or PWM brightness control? Aborting\n",
3925 aux->name);
3926 return -EINVAL;
3927 }
3928
3929 ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
3930 if (ret < 0)
3931 return ret;
3932
3933 ret = drm_edp_backlight_probe_state(aux, bl, current_mode);
3934 if (ret < 0)
3935 return ret;
3936 *current_level = ret;
3937
3938 drm_dbg_kms(aux->drm_dev,
3939 "%s: Found backlight: aux_set=%d aux_enable=%d mode=%d\n",
3940 aux->name, bl->aux_set, bl->aux_enable, *current_mode);
3941 if (bl->aux_set) {
3942 drm_dbg_kms(aux->drm_dev,
3943 "%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n",
3944 aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider,
3945 bl->lsb_reg_used);
3946 }
3947
3948 return 0;
3949}
3950EXPORT_SYMBOL(drm_edp_backlight_init);
3951
3952#if IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
3953 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))
3954
3955static int dp_aux_backlight_update_status(struct backlight_device *bd)
3956{
3957 struct dp_aux_backlight *bl = bl_get_data(bd);
3958 u16 brightness = backlight_get_brightness(bd);
3959 int ret = 0;
3960
3961 if (!backlight_is_blank(bd)) {
3962 if (!bl->enabled) {
3963 drm_edp_backlight_enable(bl->aux, &bl->info, brightness);
3964 bl->enabled = true;
3965 return 0;
3966 }
3967 ret = drm_edp_backlight_set_level(bl->aux, &bl->info, brightness);
3968 } else {
3969 if (bl->enabled) {
3970 drm_edp_backlight_disable(bl->aux, &bl->info);
3971 bl->enabled = false;
3972 }
3973 }
3974
3975 return ret;
3976}
3977
3978static const struct backlight_ops dp_aux_bl_ops = {
3979 .update_status = dp_aux_backlight_update_status,
3980};
3981
3982/**
3983 * drm_panel_dp_aux_backlight - create and use DP AUX backlight
3984 * @panel: DRM panel
3985 * @aux: The DP AUX channel to use
3986 *
3987 * Use this function to create and handle backlight if your panel
3988 * supports backlight control over DP AUX channel using DPCD
3989 * registers as per VESA's standard backlight control interface.
3990 *
3991 * When the panel is enabled backlight will be enabled after a
3992 * successful call to &drm_panel_funcs.enable()
3993 *
3994 * When the panel is disabled backlight will be disabled before the
3995 * call to &drm_panel_funcs.disable().
3996 *
3997 * A typical implementation for a panel driver supporting backlight
3998 * control over DP AUX will call this function at probe time.
3999 * Backlight will then be handled transparently without requiring
4000 * any intervention from the driver.
4001 *
4002 * drm_panel_dp_aux_backlight() must be called after the call to drm_panel_init().
4003 *
4004 * Return: 0 on success or a negative error code on failure.
4005 */
4006int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
4007{
4008 struct dp_aux_backlight *bl;
4009 struct backlight_properties props = { 0 };
4010 u16 current_level;
4011 u8 current_mode;
4012 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
4013 int ret;
4014
4015 if (!panel || !panel->dev || !aux)
4016 return -EINVAL;
4017
4018 ret = drm_dp_dpcd_read(aux, DP_EDP_DPCD_REV, edp_dpcd,
4019 EDP_DISPLAY_CTL_CAP_SIZE);
4020 if (ret < 0)
4021 return ret;
4022
4023 if (!drm_edp_backlight_supported(edp_dpcd)) {
4024 DRM_DEV_INFO(panel->dev, "DP AUX backlight is not supported\n");
4025 return 0;
4026 }
4027
4028 bl = devm_kzalloc(panel->dev, sizeof(*bl), GFP_KERNEL);
4029 if (!bl)
4030 return -ENOMEM;
4031
4032 bl->aux = aux;
4033
4034 ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd,
4035 ¤t_level, ¤t_mode);
4036 if (ret < 0)
4037 return ret;
4038
4039 props.type = BACKLIGHT_RAW;
4040 props.brightness = current_level;
4041 props.max_brightness = bl->info.max;
4042
4043 bl->base = devm_backlight_device_register(panel->dev, "dp_aux_backlight",
4044 panel->dev, bl,
4045 &dp_aux_bl_ops, &props);
4046 if (IS_ERR(bl->base))
4047 return PTR_ERR(bl->base);
4048
4049 backlight_disable(bl->base);
4050
4051 panel->backlight = bl->base;
4052
4053 return 0;
4054}
4055EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
4056
4057#endif
4058
4059/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
4060static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
4061 int symbol_size, bool is_mst)
4062{
4063 int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
4064 int align = is_mst ? 4 / lane_count : 1;
4065
4066 return ALIGN(cycles, align);
4067}
4068
4069static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
4070 int bpp_x16, int symbol_size, bool is_mst)
4071{
4072 int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
4073 int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
4074 bpp_x16, symbol_size, is_mst);
4075 int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
4076
4077 return slice_count * (slice_data_cycles + slice_eoc_cycles);
4078}
4079
4080/**
4081 * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
4082 * @lane_count: DP link lane count
4083 * @hactive: pixel count of the active period in one scanline of the stream
4084 * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
4085 * @bpp_x16: bits per pixel in .4 binary fixed point
4086 * @flags: DRM_DP_OVERHEAD_x flags
4087 *
4088 * Calculate the BW allocation overhead of a DP link stream, depending
4089 * on the link's
4090 * - @lane_count
4091 * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
4092 * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
4093 * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
4094 * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
4095 * as well as the stream's
4096 * - @hactive timing
4097 * - @bpp_x16 color depth
4098 * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
4099 * Note that this overhead doesn't account for the 8b/10b, 128b/132b
4100 * channel coding efficiency, for that see
4101 * @drm_dp_link_bw_channel_coding_efficiency().
4102 *
4103 * Returns the overhead as 100% + overhead% in 1ppm units.
4104 */
4105int drm_dp_bw_overhead(int lane_count, int hactive,
4106 int dsc_slice_count,
4107 int bpp_x16, unsigned long flags)
4108{
4109 int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
4110 bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
4111 u32 overhead = 1000000;
4112 int symbol_cycles;
4113
4114 if (lane_count == 0 || hactive == 0 || bpp_x16 == 0) {
4115 DRM_DEBUG_KMS("Invalid BW overhead params: lane_count %d, hactive %d, bpp_x16 %d.%04d\n",
4116 lane_count, hactive,
4117 bpp_x16 >> 4, (bpp_x16 & 0xf) * 625);
4118 return 0;
4119 }
4120
4121 /*
4122 * DP Standard v2.1 2.6.4.1
4123 * SSC downspread and ref clock variation margin:
4124 * 5300ppm + 300ppm ~ 0.6%
4125 */
4126 if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
4127 overhead += 6000;
4128
4129 /*
4130 * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
4131 * FEC symbol insertions for 8b/10b channel coding:
4132 * After each 250 data symbols on 2-4 lanes:
4133 * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block)
4134 * After each 2 x 250 data symbols on 1 lane:
4135 * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
4136 * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
4137 * 256 * 256 bytes + 1 FEC_PM
4138 * or
4139 * 128 * 512 bytes + 1 FEC_PM
4140 * (256 * 6 + 1) / (256 * 250) = 2.4015625 %
4141 */
4142 if (flags & DRM_DP_BW_OVERHEAD_FEC)
4143 overhead += 24016;
4144
4145 /*
4146 * DP Standard v2.1 2.7.9, 5.9.7
4147 * The FEC overhead for UHBR is accounted for in its 96.71% channel
4148 * coding efficiency.
4149 */
4150 WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
4151 (flags & DRM_DP_BW_OVERHEAD_FEC));
4152
4153 if (flags & DRM_DP_BW_OVERHEAD_DSC)
4154 symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
4155 dsc_slice_count,
4156 bpp_x16, symbol_size,
4157 is_mst);
4158 else
4159 symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
4160 bpp_x16, symbol_size,
4161 is_mst);
4162
4163 return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
4164 overhead * 16),
4165 hactive * bpp_x16);
4166}
4167EXPORT_SYMBOL(drm_dp_bw_overhead);
4168
4169/**
4170 * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
4171 * @is_uhbr: Whether the link has a 128b/132b channel coding
4172 *
4173 * Return the channel coding efficiency of the given DP link type, which is
4174 * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
4175 * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
4176 * and for 128b/132b any link or PHY level control symbol insertion overhead
4177 * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
4178 * corresponding FEC overhead is BW allocation specific, included in the value
4179 * returned by drm_dp_bw_overhead().
4180 *
4181 * Returns the efficiency in the 100%/coding-overhead% ratio in
4182 * 1ppm units.
4183 */
4184int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
4185{
4186 if (is_uhbr)
4187 return 967100;
4188 else
4189 /*
4190 * Note that on 8b/10b MST the efficiency is only
4191 * 78.75% due to the 1 out of 64 MTPH packet overhead,
4192 * not accounted for here.
4193 */
4194 return 800000;
4195}
4196EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
4197
4198/**
4199 * drm_dp_max_dprx_data_rate - Get the max data bandwidth of a DPRX sink
4200 * @max_link_rate: max DPRX link rate in 10kbps units
4201 * @max_lanes: max DPRX lane count
4202 *
4203 * Given a link rate and lanes, get the data bandwidth.
4204 *
4205 * Data bandwidth is the actual payload rate, which depends on the data
4206 * bandwidth efficiency and the link rate.
4207 *
4208 * Note that protocol layers above the DPRX link level considered here can
4209 * further limit the maximum data rate. Such layers are the MST topology (with
4210 * limits on the link between the source and first branch device as well as on
4211 * the whole MST path until the DPRX link) and (Thunderbolt) DP tunnels -
4212 * which in turn can encapsulate an MST link with its own limit - with each
4213 * SST or MST encapsulated tunnel sharing the BW of a tunnel group.
4214 *
4215 * Returns the maximum data rate in kBps units.
4216 */
4217int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes)
4218{
4219 int ch_coding_efficiency =
4220 drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(max_link_rate));
4221
4222 return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate * 10 * max_lanes,
4223 ch_coding_efficiency),
4224 1000000 * 8);
4225}
4226EXPORT_SYMBOL(drm_dp_max_dprx_data_rate);