1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Tegra 124 cpufreq driver
  4 */
  5
  6#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
  7
  8#include <linux/clk.h>
  9#include <linux/cpufreq.h>
 10#include <linux/err.h>
 11#include <linux/init.h>
 12#include <linux/kernel.h>
 13#include <linux/module.h>
 14#include <linux/of.h>
 15#include <linux/platform_device.h>
 16#include <linux/pm_opp.h>
 17#include <linux/types.h>
 18
 19struct tegra124_cpufreq_priv {
 20	struct clk *cpu_clk;
 21	struct clk *pllp_clk;
 22	struct clk *pllx_clk;
 23	struct clk *dfll_clk;
 24	struct platform_device *cpufreq_dt_pdev;
 25};
 26
 27static int tegra124_cpu_switch_to_dfll(struct tegra124_cpufreq_priv *priv)
 28{
 29	struct clk *orig_parent;
 30	int ret;
 31
 32	ret = clk_set_rate(priv->dfll_clk, clk_get_rate(priv->cpu_clk));
 33	if (ret)
 34		return ret;
 35
 36	orig_parent = clk_get_parent(priv->cpu_clk);
 37	clk_set_parent(priv->cpu_clk, priv->pllp_clk);
 38
 39	ret = clk_prepare_enable(priv->dfll_clk);
 40	if (ret)
 41		goto out;
 42
 43	clk_set_parent(priv->cpu_clk, priv->dfll_clk);
 44
 45	return 0;
 46
 47out:
 48	clk_set_parent(priv->cpu_clk, orig_parent);
 49
 50	return ret;
 51}
 52
 53static int tegra124_cpufreq_probe(struct platform_device *pdev)
 54{
 55	struct tegra124_cpufreq_priv *priv;
 56	struct device_node *np;
 57	struct device *cpu_dev;
 58	struct platform_device_info cpufreq_dt_devinfo = {};
 59	int ret;
 60
 61	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 62	if (!priv)
 63		return -ENOMEM;
 64
 65	cpu_dev = get_cpu_device(0);
 66	if (!cpu_dev)
 67		return -ENODEV;
 68
 69	np = of_cpu_device_node_get(0);
 70	if (!np)
 71		return -ENODEV;
 72
 73	priv->cpu_clk = of_clk_get_by_name(np, "cpu_g");
 74	if (IS_ERR(priv->cpu_clk)) {
 75		ret = PTR_ERR(priv->cpu_clk);
 76		goto out_put_np;
 77	}
 78
 79	priv->dfll_clk = of_clk_get_by_name(np, "dfll");
 80	if (IS_ERR(priv->dfll_clk)) {
 81		ret = PTR_ERR(priv->dfll_clk);
 82		goto out_put_cpu_clk;
 83	}
 84
 85	priv->pllx_clk = of_clk_get_by_name(np, "pll_x");
 86	if (IS_ERR(priv->pllx_clk)) {
 87		ret = PTR_ERR(priv->pllx_clk);
 88		goto out_put_dfll_clk;
 89	}
 90
 91	priv->pllp_clk = of_clk_get_by_name(np, "pll_p");
 92	if (IS_ERR(priv->pllp_clk)) {
 93		ret = PTR_ERR(priv->pllp_clk);
 94		goto out_put_pllx_clk;
 95	}
 96
 97	ret = tegra124_cpu_switch_to_dfll(priv);
 98	if (ret)
 99		goto out_put_pllp_clk;
100
101	cpufreq_dt_devinfo.name = "cpufreq-dt";
102	cpufreq_dt_devinfo.parent = &pdev->dev;
103
104	priv->cpufreq_dt_pdev =
105		platform_device_register_full(&cpufreq_dt_devinfo);
106	if (IS_ERR(priv->cpufreq_dt_pdev)) {
107		ret = PTR_ERR(priv->cpufreq_dt_pdev);
108		goto out_put_pllp_clk;
109	}
110
111	platform_set_drvdata(pdev, priv);
112
113	of_node_put(np);
114
115	return 0;
116
117out_put_pllp_clk:
118	clk_put(priv->pllp_clk);
119out_put_pllx_clk:
120	clk_put(priv->pllx_clk);
121out_put_dfll_clk:
122	clk_put(priv->dfll_clk);
123out_put_cpu_clk:
124	clk_put(priv->cpu_clk);
125out_put_np:
126	of_node_put(np);
127
128	return ret;
129}
130
131static int __maybe_unused tegra124_cpufreq_suspend(struct device *dev)
132{
133	struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
134	int err;
135
136	/*
137	 * PLLP rate 408Mhz is below the CPU Fmax at Vmin and is safe to
138	 * use during suspend and resume. So, switch the CPU clock source
139	 * to PLLP and disable DFLL.
140	 */
141	err = clk_set_parent(priv->cpu_clk, priv->pllp_clk);
142	if (err < 0) {
143		dev_err(dev, "failed to reparent to PLLP: %d\n", err);
144		return err;
145	}
146
147	clk_disable_unprepare(priv->dfll_clk);
148
149	return 0;
150}
151
152static int __maybe_unused tegra124_cpufreq_resume(struct device *dev)
153{
154	struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
155	int err;
156
157	/*
158	 * Warmboot code powers up the CPU with PLLP clock source.
159	 * Enable DFLL clock and switch CPU clock source back to DFLL.
160	 */
161	err = clk_prepare_enable(priv->dfll_clk);
162	if (err < 0) {
163		dev_err(dev, "failed to enable DFLL clock for CPU: %d\n", err);
164		goto disable_cpufreq;
165	}
166
167	err = clk_set_parent(priv->cpu_clk, priv->dfll_clk);
168	if (err < 0) {
169		dev_err(dev, "failed to reparent to DFLL clock: %d\n", err);
170		goto disable_dfll;
171	}
172
173	return 0;
174
175disable_dfll:
176	clk_disable_unprepare(priv->dfll_clk);
177disable_cpufreq:
178	disable_cpufreq();
179
180	return err;
181}
182
183static const struct dev_pm_ops tegra124_cpufreq_pm_ops = {
184	SET_SYSTEM_SLEEP_PM_OPS(tegra124_cpufreq_suspend,
185				tegra124_cpufreq_resume)
186};
187
188static struct platform_driver tegra124_cpufreq_platdrv = {
189	.driver.name	= "cpufreq-tegra124",
190	.driver.pm	= &tegra124_cpufreq_pm_ops,
191	.probe		= tegra124_cpufreq_probe,
192};
193
194static int __init tegra_cpufreq_init(void)
195{
196	int ret;
197	struct platform_device *pdev;
198
199	if (!(of_machine_is_compatible("nvidia,tegra124") ||
200		of_machine_is_compatible("nvidia,tegra210")))
201		return -ENODEV;
202
203	/*
204	 * Platform driver+device required for handling EPROBE_DEFER with
205	 * the regulator and the DFLL clock
206	 */
207	ret = platform_driver_register(&tegra124_cpufreq_platdrv);
208	if (ret)
209		return ret;
210
211	pdev = platform_device_register_simple("cpufreq-tegra124", -1, NULL, 0);
212	if (IS_ERR(pdev)) {
213		platform_driver_unregister(&tegra124_cpufreq_platdrv);
214		return PTR_ERR(pdev);
215	}
216
217	return 0;
218}
219module_init(tegra_cpufreq_init);
220
221MODULE_AUTHOR("Tuomas Tynkkynen <ttynkkynen@nvidia.com>");
222MODULE_DESCRIPTION("cpufreq driver for NVIDIA Tegra124");