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1/*
2 * Copyright 2010-2011 Picochip Ltd., Jamie Iles
3 * http://www.picochip.com
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 *
10 * This file implements a driver for the Synopsys DesignWare watchdog device
11 * in the many ARM subsystems. The watchdog has 16 different timeout periods
12 * and these are a function of the input clock frequency.
13 *
14 * The DesignWare watchdog cannot be stopped once it has been started so we
15 * use a software timer to implement a ping that will keep the watchdog alive.
16 * If we receive an expected close for the watchdog then we keep the timer
17 * running, otherwise the timer is stopped and the watchdog will expire.
18 */
19#define pr_fmt(fmt) "dw_wdt: " fmt
20
21#include <linux/bitops.h>
22#include <linux/clk.h>
23#include <linux/device.h>
24#include <linux/err.h>
25#include <linux/fs.h>
26#include <linux/io.h>
27#include <linux/kernel.h>
28#include <linux/miscdevice.h>
29#include <linux/module.h>
30#include <linux/moduleparam.h>
31#include <linux/pm.h>
32#include <linux/platform_device.h>
33#include <linux/spinlock.h>
34#include <linux/timer.h>
35#include <linux/uaccess.h>
36#include <linux/watchdog.h>
37
38#define WDOG_CONTROL_REG_OFFSET 0x00
39#define WDOG_CONTROL_REG_WDT_EN_MASK 0x01
40#define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04
41#define WDOG_CURRENT_COUNT_REG_OFFSET 0x08
42#define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c
43#define WDOG_COUNTER_RESTART_KICK_VALUE 0x76
44
45/* The maximum TOP (timeout period) value that can be set in the watchdog. */
46#define DW_WDT_MAX_TOP 15
47
48static int nowayout = WATCHDOG_NOWAYOUT;
49module_param(nowayout, int, 0);
50MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
51 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
52
53#define WDT_TIMEOUT (HZ / 2)
54
55static struct {
56 spinlock_t lock;
57 void __iomem *regs;
58 struct clk *clk;
59 unsigned long in_use;
60 unsigned long next_heartbeat;
61 struct timer_list timer;
62 int expect_close;
63} dw_wdt;
64
65static inline int dw_wdt_is_enabled(void)
66{
67 return readl(dw_wdt.regs + WDOG_CONTROL_REG_OFFSET) &
68 WDOG_CONTROL_REG_WDT_EN_MASK;
69}
70
71static inline int dw_wdt_top_in_seconds(unsigned top)
72{
73 /*
74 * There are 16 possible timeout values in 0..15 where the number of
75 * cycles is 2 ^ (16 + i) and the watchdog counts down.
76 */
77 return (1 << (16 + top)) / clk_get_rate(dw_wdt.clk);
78}
79
80static int dw_wdt_get_top(void)
81{
82 int top = readl(dw_wdt.regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;
83
84 return dw_wdt_top_in_seconds(top);
85}
86
87static inline void dw_wdt_set_next_heartbeat(void)
88{
89 dw_wdt.next_heartbeat = jiffies + dw_wdt_get_top() * HZ;
90}
91
92static int dw_wdt_set_top(unsigned top_s)
93{
94 int i, top_val = DW_WDT_MAX_TOP;
95
96 /*
97 * Iterate over the timeout values until we find the closest match. We
98 * always look for >=.
99 */
100 for (i = 0; i <= DW_WDT_MAX_TOP; ++i)
101 if (dw_wdt_top_in_seconds(i) >= top_s) {
102 top_val = i;
103 break;
104 }
105
106 /* Set the new value in the watchdog. */
107 writel(top_val, dw_wdt.regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
108
109 dw_wdt_set_next_heartbeat();
110
111 return dw_wdt_top_in_seconds(top_val);
112}
113
114static void dw_wdt_keepalive(void)
115{
116 writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt.regs +
117 WDOG_COUNTER_RESTART_REG_OFFSET);
118}
119
120static void dw_wdt_ping(unsigned long data)
121{
122 if (time_before(jiffies, dw_wdt.next_heartbeat) ||
123 (!nowayout && !dw_wdt.in_use)) {
124 dw_wdt_keepalive();
125 mod_timer(&dw_wdt.timer, jiffies + WDT_TIMEOUT);
126 } else
127 pr_crit("keepalive missed, machine will reset\n");
128}
129
130static int dw_wdt_open(struct inode *inode, struct file *filp)
131{
132 if (test_and_set_bit(0, &dw_wdt.in_use))
133 return -EBUSY;
134
135 /* Make sure we don't get unloaded. */
136 __module_get(THIS_MODULE);
137
138 spin_lock(&dw_wdt.lock);
139 if (!dw_wdt_is_enabled()) {
140 /*
141 * The watchdog is not currently enabled. Set the timeout to
142 * the maximum and then start it.
143 */
144 dw_wdt_set_top(DW_WDT_MAX_TOP);
145 writel(WDOG_CONTROL_REG_WDT_EN_MASK,
146 dw_wdt.regs + WDOG_CONTROL_REG_OFFSET);
147 }
148
149 dw_wdt_set_next_heartbeat();
150
151 spin_unlock(&dw_wdt.lock);
152
153 return nonseekable_open(inode, filp);
154}
155
156ssize_t dw_wdt_write(struct file *filp, const char __user *buf, size_t len,
157 loff_t *offset)
158{
159 if (!len)
160 return 0;
161
162 if (!nowayout) {
163 size_t i;
164
165 dw_wdt.expect_close = 0;
166
167 for (i = 0; i < len; ++i) {
168 char c;
169
170 if (get_user(c, buf + i))
171 return -EFAULT;
172
173 if (c == 'V') {
174 dw_wdt.expect_close = 1;
175 break;
176 }
177 }
178 }
179
180 dw_wdt_set_next_heartbeat();
181 mod_timer(&dw_wdt.timer, jiffies + WDT_TIMEOUT);
182
183 return len;
184}
185
186static u32 dw_wdt_time_left(void)
187{
188 return readl(dw_wdt.regs + WDOG_CURRENT_COUNT_REG_OFFSET) /
189 clk_get_rate(dw_wdt.clk);
190}
191
192static const struct watchdog_info dw_wdt_ident = {
193 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
194 WDIOF_MAGICCLOSE,
195 .identity = "Synopsys DesignWare Watchdog",
196};
197
198static long dw_wdt_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
199{
200 unsigned long val;
201 int timeout;
202
203 switch (cmd) {
204 case WDIOC_GETSUPPORT:
205 return copy_to_user((struct watchdog_info *)arg, &dw_wdt_ident,
206 sizeof(dw_wdt_ident)) ? -EFAULT : 0;
207
208 case WDIOC_GETSTATUS:
209 case WDIOC_GETBOOTSTATUS:
210 return put_user(0, (int *)arg);
211
212 case WDIOC_KEEPALIVE:
213 dw_wdt_set_next_heartbeat();
214 return 0;
215
216 case WDIOC_SETTIMEOUT:
217 if (get_user(val, (int __user *)arg))
218 return -EFAULT;
219 timeout = dw_wdt_set_top(val);
220 return put_user(timeout , (int __user *)arg);
221
222 case WDIOC_GETTIMEOUT:
223 return put_user(dw_wdt_get_top(), (int __user *)arg);
224
225 case WDIOC_GETTIMELEFT:
226 /* Get the time left until expiry. */
227 if (get_user(val, (int __user *)arg))
228 return -EFAULT;
229 return put_user(dw_wdt_time_left(), (int __user *)arg);
230
231 default:
232 return -ENOTTY;
233 }
234}
235
236static int dw_wdt_release(struct inode *inode, struct file *filp)
237{
238 clear_bit(0, &dw_wdt.in_use);
239
240 if (!dw_wdt.expect_close) {
241 del_timer(&dw_wdt.timer);
242
243 if (!nowayout)
244 pr_crit("unexpected close, system will reboot soon\n");
245 else
246 pr_crit("watchdog cannot be disabled, system will reboot soon\n");
247 }
248
249 dw_wdt.expect_close = 0;
250
251 return 0;
252}
253
254#ifdef CONFIG_PM
255static int dw_wdt_suspend(struct device *dev)
256{
257 clk_disable(dw_wdt.clk);
258
259 return 0;
260}
261
262static int dw_wdt_resume(struct device *dev)
263{
264 int err = clk_enable(dw_wdt.clk);
265
266 if (err)
267 return err;
268
269 dw_wdt_keepalive();
270
271 return 0;
272}
273
274static const struct dev_pm_ops dw_wdt_pm_ops = {
275 .suspend = dw_wdt_suspend,
276 .resume = dw_wdt_resume,
277};
278#endif /* CONFIG_PM */
279
280static const struct file_operations wdt_fops = {
281 .owner = THIS_MODULE,
282 .llseek = no_llseek,
283 .open = dw_wdt_open,
284 .write = dw_wdt_write,
285 .unlocked_ioctl = dw_wdt_ioctl,
286 .release = dw_wdt_release
287};
288
289static struct miscdevice dw_wdt_miscdev = {
290 .fops = &wdt_fops,
291 .name = "watchdog",
292 .minor = WATCHDOG_MINOR,
293};
294
295static int __devinit dw_wdt_drv_probe(struct platform_device *pdev)
296{
297 int ret;
298 struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
299
300 if (!mem)
301 return -EINVAL;
302
303 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
304 "dw_wdt"))
305 return -ENOMEM;
306
307 dw_wdt.regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
308 if (!dw_wdt.regs)
309 return -ENOMEM;
310
311 dw_wdt.clk = clk_get(&pdev->dev, NULL);
312 if (IS_ERR(dw_wdt.clk))
313 return PTR_ERR(dw_wdt.clk);
314
315 ret = clk_enable(dw_wdt.clk);
316 if (ret)
317 goto out_put_clk;
318
319 spin_lock_init(&dw_wdt.lock);
320
321 ret = misc_register(&dw_wdt_miscdev);
322 if (ret)
323 goto out_disable_clk;
324
325 dw_wdt_set_next_heartbeat();
326 setup_timer(&dw_wdt.timer, dw_wdt_ping, 0);
327 mod_timer(&dw_wdt.timer, jiffies + WDT_TIMEOUT);
328
329 return 0;
330
331out_disable_clk:
332 clk_disable(dw_wdt.clk);
333out_put_clk:
334 clk_put(dw_wdt.clk);
335
336 return ret;
337}
338
339static int __devexit dw_wdt_drv_remove(struct platform_device *pdev)
340{
341 misc_deregister(&dw_wdt_miscdev);
342
343 clk_disable(dw_wdt.clk);
344 clk_put(dw_wdt.clk);
345
346 return 0;
347}
348
349static struct platform_driver dw_wdt_driver = {
350 .probe = dw_wdt_drv_probe,
351 .remove = __devexit_p(dw_wdt_drv_remove),
352 .driver = {
353 .name = "dw_wdt",
354 .owner = THIS_MODULE,
355#ifdef CONFIG_PM
356 .pm = &dw_wdt_pm_ops,
357#endif /* CONFIG_PM */
358 },
359};
360
361static int __init dw_wdt_watchdog_init(void)
362{
363 return platform_driver_register(&dw_wdt_driver);
364}
365module_init(dw_wdt_watchdog_init);
366
367static void __exit dw_wdt_watchdog_exit(void)
368{
369 platform_driver_unregister(&dw_wdt_driver);
370}
371module_exit(dw_wdt_watchdog_exit);
372
373MODULE_AUTHOR("Jamie Iles");
374MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver");
375MODULE_LICENSE("GPL");
376MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2010-2011 Picochip Ltd., Jamie Iles
4 * https://www.picochip.com
5 *
6 * This file implements a driver for the Synopsys DesignWare watchdog device
7 * in the many subsystems. The watchdog has 16 different timeout periods
8 * and these are a function of the input clock frequency.
9 *
10 * The DesignWare watchdog cannot be stopped once it has been started so we
11 * do not implement a stop function. The watchdog core will continue to send
12 * heartbeat requests after the watchdog device has been closed.
13 */
14
15#include <linux/bitops.h>
16#include <linux/clk.h>
17#include <linux/debugfs.h>
18#include <linux/delay.h>
19#include <linux/err.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/kernel.h>
23#include <linux/limits.h>
24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/of.h>
27#include <linux/platform_device.h>
28#include <linux/pm.h>
29#include <linux/reset.h>
30#include <linux/watchdog.h>
31
32#define WDOG_CONTROL_REG_OFFSET 0x00
33#define WDOG_CONTROL_REG_WDT_EN_MASK 0x01
34#define WDOG_CONTROL_REG_RESP_MODE_MASK 0x02
35#define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04
36#define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4
37#define WDOG_CURRENT_COUNT_REG_OFFSET 0x08
38#define WDOG_COUNTER_RESTART_REG_OFFSET 0x0c
39#define WDOG_COUNTER_RESTART_KICK_VALUE 0x76
40#define WDOG_INTERRUPT_STATUS_REG_OFFSET 0x10
41#define WDOG_INTERRUPT_CLEAR_REG_OFFSET 0x14
42#define WDOG_COMP_PARAMS_5_REG_OFFSET 0xe4
43#define WDOG_COMP_PARAMS_4_REG_OFFSET 0xe8
44#define WDOG_COMP_PARAMS_3_REG_OFFSET 0xec
45#define WDOG_COMP_PARAMS_2_REG_OFFSET 0xf0
46#define WDOG_COMP_PARAMS_1_REG_OFFSET 0xf4
47#define WDOG_COMP_PARAMS_1_USE_FIX_TOP BIT(6)
48#define WDOG_COMP_VERSION_REG_OFFSET 0xf8
49#define WDOG_COMP_TYPE_REG_OFFSET 0xfc
50
51/* There are sixteen TOPs (timeout periods) that can be set in the watchdog. */
52#define DW_WDT_NUM_TOPS 16
53#define DW_WDT_FIX_TOP(_idx) (1U << (16 + _idx))
54
55#define DW_WDT_DEFAULT_SECONDS 30
56
57static const u32 dw_wdt_fix_tops[DW_WDT_NUM_TOPS] = {
58 DW_WDT_FIX_TOP(0), DW_WDT_FIX_TOP(1), DW_WDT_FIX_TOP(2),
59 DW_WDT_FIX_TOP(3), DW_WDT_FIX_TOP(4), DW_WDT_FIX_TOP(5),
60 DW_WDT_FIX_TOP(6), DW_WDT_FIX_TOP(7), DW_WDT_FIX_TOP(8),
61 DW_WDT_FIX_TOP(9), DW_WDT_FIX_TOP(10), DW_WDT_FIX_TOP(11),
62 DW_WDT_FIX_TOP(12), DW_WDT_FIX_TOP(13), DW_WDT_FIX_TOP(14),
63 DW_WDT_FIX_TOP(15)
64};
65
66static bool nowayout = WATCHDOG_NOWAYOUT;
67module_param(nowayout, bool, 0);
68MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
69 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
70
71enum dw_wdt_rmod {
72 DW_WDT_RMOD_RESET = 1,
73 DW_WDT_RMOD_IRQ = 2
74};
75
76struct dw_wdt_timeout {
77 u32 top_val;
78 unsigned int sec;
79 unsigned int msec;
80};
81
82struct dw_wdt {
83 void __iomem *regs;
84 struct clk *clk;
85 struct clk *pclk;
86 unsigned long rate;
87 enum dw_wdt_rmod rmod;
88 struct dw_wdt_timeout timeouts[DW_WDT_NUM_TOPS];
89 struct watchdog_device wdd;
90 struct reset_control *rst;
91 /* Save/restore */
92 u32 control;
93 u32 timeout;
94
95#ifdef CONFIG_DEBUG_FS
96 struct dentry *dbgfs_dir;
97#endif
98};
99
100#define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd)
101
102static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt)
103{
104 return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) &
105 WDOG_CONTROL_REG_WDT_EN_MASK;
106}
107
108static void dw_wdt_update_mode(struct dw_wdt *dw_wdt, enum dw_wdt_rmod rmod)
109{
110 u32 val;
111
112 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
113 if (rmod == DW_WDT_RMOD_IRQ)
114 val |= WDOG_CONTROL_REG_RESP_MODE_MASK;
115 else
116 val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
117 writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
118
119 dw_wdt->rmod = rmod;
120}
121
122static unsigned int dw_wdt_find_best_top(struct dw_wdt *dw_wdt,
123 unsigned int timeout, u32 *top_val)
124{
125 int idx;
126
127 /*
128 * Find a TOP with timeout greater or equal to the requested number.
129 * Note we'll select a TOP with maximum timeout if the requested
130 * timeout couldn't be reached.
131 */
132 for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) {
133 if (dw_wdt->timeouts[idx].sec >= timeout)
134 break;
135 }
136
137 if (idx == DW_WDT_NUM_TOPS)
138 --idx;
139
140 *top_val = dw_wdt->timeouts[idx].top_val;
141
142 return dw_wdt->timeouts[idx].sec;
143}
144
145static unsigned int dw_wdt_get_min_timeout(struct dw_wdt *dw_wdt)
146{
147 int idx;
148
149 /*
150 * We'll find a timeout greater or equal to one second anyway because
151 * the driver probe would have failed if there was none.
152 */
153 for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) {
154 if (dw_wdt->timeouts[idx].sec)
155 break;
156 }
157
158 return dw_wdt->timeouts[idx].sec;
159}
160
161static unsigned int dw_wdt_get_max_timeout_ms(struct dw_wdt *dw_wdt)
162{
163 struct dw_wdt_timeout *timeout = &dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1];
164 u64 msec;
165
166 msec = (u64)timeout->sec * MSEC_PER_SEC + timeout->msec;
167
168 return msec < UINT_MAX ? msec : UINT_MAX;
169}
170
171static unsigned int dw_wdt_get_timeout(struct dw_wdt *dw_wdt)
172{
173 int top_val = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;
174 int idx;
175
176 for (idx = 0; idx < DW_WDT_NUM_TOPS; ++idx) {
177 if (dw_wdt->timeouts[idx].top_val == top_val)
178 break;
179 }
180
181 /*
182 * In IRQ mode due to the two stages counter, the actual timeout is
183 * twice greater than the TOP setting.
184 */
185 return dw_wdt->timeouts[idx].sec * dw_wdt->rmod;
186}
187
188static int dw_wdt_ping(struct watchdog_device *wdd)
189{
190 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
191
192 writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs +
193 WDOG_COUNTER_RESTART_REG_OFFSET);
194
195 return 0;
196}
197
198static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s)
199{
200 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
201 unsigned int timeout;
202 u32 top_val;
203
204 /*
205 * Note IRQ mode being enabled means having a non-zero pre-timeout
206 * setup. In this case we try to find a TOP as close to the half of the
207 * requested timeout as possible since DW Watchdog IRQ mode is designed
208 * in two stages way - first timeout rises the pre-timeout interrupt,
209 * second timeout performs the system reset. So basically the effective
210 * watchdog-caused reset happens after two watchdog TOPs elapsed.
211 */
212 timeout = dw_wdt_find_best_top(dw_wdt, DIV_ROUND_UP(top_s, dw_wdt->rmod),
213 &top_val);
214 if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)
215 wdd->pretimeout = timeout;
216 else
217 wdd->pretimeout = 0;
218
219 /*
220 * Set the new value in the watchdog. Some versions of dw_wdt
221 * have TOPINIT in the TIMEOUT_RANGE register (as per
222 * CP_WDT_DUAL_TOP in WDT_COMP_PARAMS_1). On those we
223 * effectively get a pat of the watchdog right here.
224 */
225 writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT,
226 dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
227
228 /* Kick new TOP value into the watchdog counter if activated. */
229 if (watchdog_active(wdd))
230 dw_wdt_ping(wdd);
231
232 /*
233 * In case users set bigger timeout value than HW can support,
234 * kernel(watchdog_dev.c) helps to feed watchdog before
235 * wdd->max_hw_heartbeat_ms
236 */
237 if (top_s * 1000 <= wdd->max_hw_heartbeat_ms)
238 wdd->timeout = timeout * dw_wdt->rmod;
239 else
240 wdd->timeout = top_s;
241
242 return 0;
243}
244
245static int dw_wdt_set_pretimeout(struct watchdog_device *wdd, unsigned int req)
246{
247 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
248
249 /*
250 * We ignore actual value of the timeout passed from user-space
251 * using it as a flag whether the pretimeout functionality is intended
252 * to be activated.
253 */
254 dw_wdt_update_mode(dw_wdt, req ? DW_WDT_RMOD_IRQ : DW_WDT_RMOD_RESET);
255 dw_wdt_set_timeout(wdd, wdd->timeout);
256
257 return 0;
258}
259
260static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt)
261{
262 u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
263
264 /* Disable/enable interrupt mode depending on the RMOD flag. */
265 if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)
266 val |= WDOG_CONTROL_REG_RESP_MODE_MASK;
267 else
268 val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
269 /* Enable watchdog. */
270 val |= WDOG_CONTROL_REG_WDT_EN_MASK;
271 writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
272}
273
274static int dw_wdt_start(struct watchdog_device *wdd)
275{
276 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
277
278 dw_wdt_set_timeout(wdd, wdd->timeout);
279 dw_wdt_ping(&dw_wdt->wdd);
280 dw_wdt_arm_system_reset(dw_wdt);
281
282 return 0;
283}
284
285static int dw_wdt_stop(struct watchdog_device *wdd)
286{
287 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
288
289 if (!dw_wdt->rst) {
290 set_bit(WDOG_HW_RUNNING, &wdd->status);
291 return 0;
292 }
293
294 reset_control_assert(dw_wdt->rst);
295 reset_control_deassert(dw_wdt->rst);
296
297 return 0;
298}
299
300static int dw_wdt_restart(struct watchdog_device *wdd,
301 unsigned long action, void *data)
302{
303 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
304
305 writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
306 dw_wdt_update_mode(dw_wdt, DW_WDT_RMOD_RESET);
307 if (dw_wdt_is_enabled(dw_wdt))
308 writel(WDOG_COUNTER_RESTART_KICK_VALUE,
309 dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);
310 else
311 dw_wdt_arm_system_reset(dw_wdt);
312
313 /* wait for reset to assert... */
314 mdelay(500);
315
316 return 0;
317}
318
319static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd)
320{
321 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
322 unsigned int sec;
323 u32 val;
324
325 val = readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET);
326 sec = val / dw_wdt->rate;
327
328 if (dw_wdt->rmod == DW_WDT_RMOD_IRQ) {
329 val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);
330 if (!val)
331 sec += wdd->pretimeout;
332 }
333
334 return sec;
335}
336
337static const struct watchdog_info dw_wdt_ident = {
338 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
339 WDIOF_MAGICCLOSE,
340 .identity = "Synopsys DesignWare Watchdog",
341};
342
343static const struct watchdog_info dw_wdt_pt_ident = {
344 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
345 WDIOF_PRETIMEOUT | WDIOF_MAGICCLOSE,
346 .identity = "Synopsys DesignWare Watchdog",
347};
348
349static const struct watchdog_ops dw_wdt_ops = {
350 .owner = THIS_MODULE,
351 .start = dw_wdt_start,
352 .stop = dw_wdt_stop,
353 .ping = dw_wdt_ping,
354 .set_timeout = dw_wdt_set_timeout,
355 .set_pretimeout = dw_wdt_set_pretimeout,
356 .get_timeleft = dw_wdt_get_timeleft,
357 .restart = dw_wdt_restart,
358};
359
360static irqreturn_t dw_wdt_irq(int irq, void *devid)
361{
362 struct dw_wdt *dw_wdt = devid;
363 u32 val;
364
365 /*
366 * We don't clear the IRQ status. It's supposed to be done by the
367 * following ping operations.
368 */
369 val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);
370 if (!val)
371 return IRQ_NONE;
372
373 watchdog_notify_pretimeout(&dw_wdt->wdd);
374
375 return IRQ_HANDLED;
376}
377
378static int dw_wdt_suspend(struct device *dev)
379{
380 struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
381
382 dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
383 dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
384
385 clk_disable_unprepare(dw_wdt->pclk);
386 clk_disable_unprepare(dw_wdt->clk);
387
388 return 0;
389}
390
391static int dw_wdt_resume(struct device *dev)
392{
393 struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
394 int err = clk_prepare_enable(dw_wdt->clk);
395
396 if (err)
397 return err;
398
399 err = clk_prepare_enable(dw_wdt->pclk);
400 if (err) {
401 clk_disable_unprepare(dw_wdt->clk);
402 return err;
403 }
404
405 writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
406 writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
407
408 dw_wdt_ping(&dw_wdt->wdd);
409
410 return 0;
411}
412
413static DEFINE_SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume);
414
415/*
416 * In case if DW WDT IP core is synthesized with fixed TOP feature disabled the
417 * TOPs array can be arbitrary ordered with nearly any sixteen uint numbers
418 * depending on the system engineer imagination. The next method handles the
419 * passed TOPs array to pre-calculate the effective timeouts and to sort the
420 * TOP items out in the ascending order with respect to the timeouts.
421 */
422
423static void dw_wdt_handle_tops(struct dw_wdt *dw_wdt, const u32 *tops)
424{
425 struct dw_wdt_timeout tout, *dst;
426 int val, tidx;
427 u64 msec;
428
429 /*
430 * We walk over the passed TOPs array and calculate corresponding
431 * timeouts in seconds and milliseconds. The milliseconds granularity
432 * is needed to distinguish the TOPs with very close timeouts and to
433 * set the watchdog max heartbeat setting further.
434 */
435 for (val = 0; val < DW_WDT_NUM_TOPS; ++val) {
436 tout.top_val = val;
437 tout.sec = tops[val] / dw_wdt->rate;
438 msec = (u64)tops[val] * MSEC_PER_SEC;
439 do_div(msec, dw_wdt->rate);
440 tout.msec = msec - ((u64)tout.sec * MSEC_PER_SEC);
441
442 /*
443 * Find a suitable place for the current TOP in the timeouts
444 * array so that the list is remained in the ascending order.
445 */
446 for (tidx = 0; tidx < val; ++tidx) {
447 dst = &dw_wdt->timeouts[tidx];
448 if (tout.sec > dst->sec || (tout.sec == dst->sec &&
449 tout.msec >= dst->msec))
450 continue;
451 else
452 swap(*dst, tout);
453 }
454
455 dw_wdt->timeouts[val] = tout;
456 }
457}
458
459static int dw_wdt_init_timeouts(struct dw_wdt *dw_wdt, struct device *dev)
460{
461 u32 data, of_tops[DW_WDT_NUM_TOPS];
462 const u32 *tops;
463 int ret;
464
465 /*
466 * Retrieve custom or fixed counter values depending on the
467 * WDT_USE_FIX_TOP flag found in the component specific parameters
468 * #1 register.
469 */
470 data = readl(dw_wdt->regs + WDOG_COMP_PARAMS_1_REG_OFFSET);
471 if (data & WDOG_COMP_PARAMS_1_USE_FIX_TOP) {
472 tops = dw_wdt_fix_tops;
473 } else {
474 ret = of_property_read_variable_u32_array(dev_of_node(dev),
475 "snps,watchdog-tops", of_tops, DW_WDT_NUM_TOPS,
476 DW_WDT_NUM_TOPS);
477 if (ret < 0) {
478 dev_warn(dev, "No valid TOPs array specified\n");
479 tops = dw_wdt_fix_tops;
480 } else {
481 tops = of_tops;
482 }
483 }
484
485 /* Convert the specified TOPs into an array of watchdog timeouts. */
486 dw_wdt_handle_tops(dw_wdt, tops);
487 if (!dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1].sec) {
488 dev_err(dev, "No any valid TOP detected\n");
489 return -EINVAL;
490 }
491
492 return 0;
493}
494
495#ifdef CONFIG_DEBUG_FS
496
497#define DW_WDT_DBGFS_REG(_name, _off) \
498{ \
499 .name = _name, \
500 .offset = _off \
501}
502
503static const struct debugfs_reg32 dw_wdt_dbgfs_regs[] = {
504 DW_WDT_DBGFS_REG("cr", WDOG_CONTROL_REG_OFFSET),
505 DW_WDT_DBGFS_REG("torr", WDOG_TIMEOUT_RANGE_REG_OFFSET),
506 DW_WDT_DBGFS_REG("ccvr", WDOG_CURRENT_COUNT_REG_OFFSET),
507 DW_WDT_DBGFS_REG("crr", WDOG_COUNTER_RESTART_REG_OFFSET),
508 DW_WDT_DBGFS_REG("stat", WDOG_INTERRUPT_STATUS_REG_OFFSET),
509 DW_WDT_DBGFS_REG("param5", WDOG_COMP_PARAMS_5_REG_OFFSET),
510 DW_WDT_DBGFS_REG("param4", WDOG_COMP_PARAMS_4_REG_OFFSET),
511 DW_WDT_DBGFS_REG("param3", WDOG_COMP_PARAMS_3_REG_OFFSET),
512 DW_WDT_DBGFS_REG("param2", WDOG_COMP_PARAMS_2_REG_OFFSET),
513 DW_WDT_DBGFS_REG("param1", WDOG_COMP_PARAMS_1_REG_OFFSET),
514 DW_WDT_DBGFS_REG("version", WDOG_COMP_VERSION_REG_OFFSET),
515 DW_WDT_DBGFS_REG("type", WDOG_COMP_TYPE_REG_OFFSET)
516};
517
518static void dw_wdt_dbgfs_init(struct dw_wdt *dw_wdt)
519{
520 struct device *dev = dw_wdt->wdd.parent;
521 struct debugfs_regset32 *regset;
522
523 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
524 if (!regset)
525 return;
526
527 regset->regs = dw_wdt_dbgfs_regs;
528 regset->nregs = ARRAY_SIZE(dw_wdt_dbgfs_regs);
529 regset->base = dw_wdt->regs;
530
531 dw_wdt->dbgfs_dir = debugfs_create_dir(dev_name(dev), NULL);
532
533 debugfs_create_regset32("registers", 0444, dw_wdt->dbgfs_dir, regset);
534}
535
536static void dw_wdt_dbgfs_clear(struct dw_wdt *dw_wdt)
537{
538 debugfs_remove_recursive(dw_wdt->dbgfs_dir);
539}
540
541#else /* !CONFIG_DEBUG_FS */
542
543static void dw_wdt_dbgfs_init(struct dw_wdt *dw_wdt) {}
544static void dw_wdt_dbgfs_clear(struct dw_wdt *dw_wdt) {}
545
546#endif /* !CONFIG_DEBUG_FS */
547
548static int dw_wdt_drv_probe(struct platform_device *pdev)
549{
550 struct device *dev = &pdev->dev;
551 struct watchdog_device *wdd;
552 struct dw_wdt *dw_wdt;
553 int ret;
554
555 dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL);
556 if (!dw_wdt)
557 return -ENOMEM;
558
559 dw_wdt->regs = devm_platform_ioremap_resource(pdev, 0);
560 if (IS_ERR(dw_wdt->regs))
561 return PTR_ERR(dw_wdt->regs);
562
563 /*
564 * Try to request the watchdog dedicated timer clock source. It must
565 * be supplied if asynchronous mode is enabled. Otherwise fallback
566 * to the common timer/bus clocks configuration, in which the very
567 * first found clock supply both timer and APB signals.
568 */
569 dw_wdt->clk = devm_clk_get_enabled(dev, "tclk");
570 if (IS_ERR(dw_wdt->clk)) {
571 dw_wdt->clk = devm_clk_get_enabled(dev, NULL);
572 if (IS_ERR(dw_wdt->clk))
573 return PTR_ERR(dw_wdt->clk);
574 }
575
576 dw_wdt->rate = clk_get_rate(dw_wdt->clk);
577 if (dw_wdt->rate == 0)
578 return -EINVAL;
579
580 /*
581 * Request APB clock if device is configured with async clocks mode.
582 * In this case both tclk and pclk clocks are supposed to be specified.
583 * Alas we can't know for sure whether async mode was really activated,
584 * so the pclk phandle reference is left optional. If it couldn't be
585 * found we consider the device configured in synchronous clocks mode.
586 */
587 dw_wdt->pclk = devm_clk_get_optional_enabled(dev, "pclk");
588 if (IS_ERR(dw_wdt->pclk))
589 return PTR_ERR(dw_wdt->pclk);
590
591 dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
592 if (IS_ERR(dw_wdt->rst))
593 return PTR_ERR(dw_wdt->rst);
594
595 /* Enable normal reset without pre-timeout by default. */
596 dw_wdt_update_mode(dw_wdt, DW_WDT_RMOD_RESET);
597
598 /*
599 * Pre-timeout IRQ is optional, since some hardware may lack support
600 * of it. Note we must request rising-edge IRQ, since the lane is left
601 * pending either until the next watchdog kick event or up to the
602 * system reset.
603 */
604 ret = platform_get_irq_optional(pdev, 0);
605 if (ret > 0) {
606 ret = devm_request_irq(dev, ret, dw_wdt_irq,
607 IRQF_SHARED | IRQF_TRIGGER_RISING,
608 pdev->name, dw_wdt);
609 if (ret)
610 return ret;
611
612 dw_wdt->wdd.info = &dw_wdt_pt_ident;
613 } else {
614 if (ret == -EPROBE_DEFER)
615 return ret;
616
617 dw_wdt->wdd.info = &dw_wdt_ident;
618 }
619
620 reset_control_deassert(dw_wdt->rst);
621
622 ret = dw_wdt_init_timeouts(dw_wdt, dev);
623 if (ret)
624 goto out_assert_rst;
625
626 wdd = &dw_wdt->wdd;
627 wdd->ops = &dw_wdt_ops;
628 wdd->min_timeout = dw_wdt_get_min_timeout(dw_wdt);
629 wdd->max_hw_heartbeat_ms = dw_wdt_get_max_timeout_ms(dw_wdt);
630 wdd->parent = dev;
631
632 watchdog_set_drvdata(wdd, dw_wdt);
633 watchdog_set_nowayout(wdd, nowayout);
634 watchdog_init_timeout(wdd, 0, dev);
635
636 /*
637 * If the watchdog is already running, use its already configured
638 * timeout. Otherwise use the default or the value provided through
639 * devicetree.
640 */
641 if (dw_wdt_is_enabled(dw_wdt)) {
642 wdd->timeout = dw_wdt_get_timeout(dw_wdt);
643 set_bit(WDOG_HW_RUNNING, &wdd->status);
644 } else {
645 wdd->timeout = DW_WDT_DEFAULT_SECONDS;
646 watchdog_init_timeout(wdd, 0, dev);
647 }
648
649 platform_set_drvdata(pdev, dw_wdt);
650
651 watchdog_set_restart_priority(wdd, 128);
652 watchdog_stop_on_reboot(wdd);
653
654 ret = watchdog_register_device(wdd);
655 if (ret)
656 goto out_assert_rst;
657
658 dw_wdt_dbgfs_init(dw_wdt);
659
660 return 0;
661
662out_assert_rst:
663 reset_control_assert(dw_wdt->rst);
664 return ret;
665}
666
667static void dw_wdt_drv_remove(struct platform_device *pdev)
668{
669 struct dw_wdt *dw_wdt = platform_get_drvdata(pdev);
670
671 dw_wdt_dbgfs_clear(dw_wdt);
672
673 watchdog_unregister_device(&dw_wdt->wdd);
674 reset_control_assert(dw_wdt->rst);
675}
676
677#ifdef CONFIG_OF
678static const struct of_device_id dw_wdt_of_match[] = {
679 { .compatible = "snps,dw-wdt", },
680 { /* sentinel */ }
681};
682MODULE_DEVICE_TABLE(of, dw_wdt_of_match);
683#endif
684
685static struct platform_driver dw_wdt_driver = {
686 .probe = dw_wdt_drv_probe,
687 .remove_new = dw_wdt_drv_remove,
688 .driver = {
689 .name = "dw_wdt",
690 .of_match_table = of_match_ptr(dw_wdt_of_match),
691 .pm = pm_sleep_ptr(&dw_wdt_pm_ops),
692 },
693};
694
695module_platform_driver(dw_wdt_driver);
696
697MODULE_AUTHOR("Jamie Iles");
698MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver");
699MODULE_LICENSE("GPL");