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1/*
2 * drivers/net/phy/broadcom.c
3 *
4 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
5 * transceivers.
6 *
7 * Copyright (c) 2006 Maciej W. Rozycki
8 *
9 * Inspired by code written by Amy Fong.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16
17#include <linux/module.h>
18#include <linux/phy.h>
19#include <linux/brcmphy.h>
20
21
22#define BRCM_PHY_MODEL(phydev) \
23 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
24
25#define BRCM_PHY_REV(phydev) \
26 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
27
28
29#define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */
30#define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */
31#define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */
32
33#define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */
34#define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */
35
36#define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
37#define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
38#define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
39#define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
40
41#define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */
42#define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */
43#define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */
44#define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */
45#define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */
46#define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */
47#define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */
48#define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */
49#define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */
50#define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */
51#define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */
52#define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */
53#define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */
54#define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */
55#define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */
56#define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */
57#define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */
58#define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */
59
60#define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */
61#define MII_BCM54XX_SHD_WRITE 0x8000
62#define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
63#define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
64
65/*
66 * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18)
67 */
68#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
69#define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400
70#define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
71
72#define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
73#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
74#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
75#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
76
77#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
78
79
80/*
81 * Broadcom LED source encodings. These are used in BCM5461, BCM5481,
82 * BCM5482, and possibly some others.
83 */
84#define BCM_LED_SRC_LINKSPD1 0x0
85#define BCM_LED_SRC_LINKSPD2 0x1
86#define BCM_LED_SRC_XMITLED 0x2
87#define BCM_LED_SRC_ACTIVITYLED 0x3
88#define BCM_LED_SRC_FDXLED 0x4
89#define BCM_LED_SRC_SLAVE 0x5
90#define BCM_LED_SRC_INTR 0x6
91#define BCM_LED_SRC_QUALITY 0x7
92#define BCM_LED_SRC_RCVLED 0x8
93#define BCM_LED_SRC_MULTICOLOR1 0xa
94#define BCM_LED_SRC_OPENSHORT 0xb
95#define BCM_LED_SRC_OFF 0xe /* Tied high */
96#define BCM_LED_SRC_ON 0xf /* Tied low */
97
98
99/*
100 * BCM5482: Shadow registers
101 * Shadow values go into bits [14:10] of register 0x1c to select a shadow
102 * register to access.
103 */
104/* 00101: Spare Control Register 3 */
105#define BCM54XX_SHD_SCR3 0x05
106#define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001
107#define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002
108#define BCM54XX_SHD_SCR3_TRDDAPD 0x0004
109
110/* 01010: Auto Power-Down */
111#define BCM54XX_SHD_APD 0x0a
112#define BCM54XX_SHD_APD_EN 0x0020
113
114#define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */
115 /* LED3 / ~LINKSPD[2] selector */
116#define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4)
117 /* LED1 / ~LINKSPD[1] selector */
118#define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0)
119#define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */
120#define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */
121#define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */
122#define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */
123#define BCM5482_SHD_MODE 0x1f /* 11111: Mode Control Register */
124#define BCM5482_SHD_MODE_1000BX 0x0001 /* Enable 1000BASE-X registers */
125
126
127/*
128 * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17)
129 */
130#define MII_BCM54XX_EXP_AADJ1CH0 0x001f
131#define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200
132#define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100
133#define MII_BCM54XX_EXP_AADJ1CH3 0x601f
134#define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002
135#define MII_BCM54XX_EXP_EXP08 0x0F08
136#define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001
137#define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200
138#define MII_BCM54XX_EXP_EXP75 0x0f75
139#define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c
140#define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001
141#define MII_BCM54XX_EXP_EXP96 0x0f96
142#define MII_BCM54XX_EXP_EXP96_MYST 0x0010
143#define MII_BCM54XX_EXP_EXP97 0x0f97
144#define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c
145
146/*
147 * BCM5482: Secondary SerDes registers
148 */
149#define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */
150#define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */
151#define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */
152#define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
153#define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
154
155
156/*****************************************************************************/
157/* Fast Ethernet Transceiver definitions. */
158/*****************************************************************************/
159
160#define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */
161#define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */
162#define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */
163#define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */
164#define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */
165#define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */
166
167#define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */
168#define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */
169
170
171/*** Shadow register definitions ***/
172
173#define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */
174#define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */
175
176#define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */
177#define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003
178#define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001
179
180#define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */
181#define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */
182
183
184MODULE_DESCRIPTION("Broadcom PHY driver");
185MODULE_AUTHOR("Maciej W. Rozycki");
186MODULE_LICENSE("GPL");
187
188/*
189 * Indirect register access functions for the 1000BASE-T/100BASE-TX/10BASE-T
190 * 0x1c shadow registers.
191 */
192static int bcm54xx_shadow_read(struct phy_device *phydev, u16 shadow)
193{
194 phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
195 return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
196}
197
198static int bcm54xx_shadow_write(struct phy_device *phydev, u16 shadow, u16 val)
199{
200 return phy_write(phydev, MII_BCM54XX_SHD,
201 MII_BCM54XX_SHD_WRITE |
202 MII_BCM54XX_SHD_VAL(shadow) |
203 MII_BCM54XX_SHD_DATA(val));
204}
205
206/* Indirect register access functions for the Expansion Registers */
207static int bcm54xx_exp_read(struct phy_device *phydev, u16 regnum)
208{
209 int val;
210
211 val = phy_write(phydev, MII_BCM54XX_EXP_SEL, regnum);
212 if (val < 0)
213 return val;
214
215 val = phy_read(phydev, MII_BCM54XX_EXP_DATA);
216
217 /* Restore default value. It's O.K. if this write fails. */
218 phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
219
220 return val;
221}
222
223static int bcm54xx_exp_write(struct phy_device *phydev, u16 regnum, u16 val)
224{
225 int ret;
226
227 ret = phy_write(phydev, MII_BCM54XX_EXP_SEL, regnum);
228 if (ret < 0)
229 return ret;
230
231 ret = phy_write(phydev, MII_BCM54XX_EXP_DATA, val);
232
233 /* Restore default value. It's O.K. if this write fails. */
234 phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
235
236 return ret;
237}
238
239static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
240{
241 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
242}
243
244/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
245static int bcm50610_a0_workaround(struct phy_device *phydev)
246{
247 int err;
248
249 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_AADJ1CH0,
250 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
251 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
252 if (err < 0)
253 return err;
254
255 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_AADJ1CH3,
256 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
257 if (err < 0)
258 return err;
259
260 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP75,
261 MII_BCM54XX_EXP_EXP75_VDACCTRL);
262 if (err < 0)
263 return err;
264
265 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP96,
266 MII_BCM54XX_EXP_EXP96_MYST);
267 if (err < 0)
268 return err;
269
270 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP97,
271 MII_BCM54XX_EXP_EXP97_MYST);
272
273 return err;
274}
275
276static int bcm54xx_phydsp_config(struct phy_device *phydev)
277{
278 int err, err2;
279
280 /* Enable the SMDSP clock */
281 err = bcm54xx_auxctl_write(phydev,
282 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
283 MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
284 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
285 if (err < 0)
286 return err;
287
288 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
289 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
290 /* Clear bit 9 to fix a phy interop issue. */
291 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP08,
292 MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
293 if (err < 0)
294 goto error;
295
296 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
297 err = bcm50610_a0_workaround(phydev);
298 if (err < 0)
299 goto error;
300 }
301 }
302
303 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
304 int val;
305
306 val = bcm54xx_exp_read(phydev, MII_BCM54XX_EXP_EXP75);
307 if (val < 0)
308 goto error;
309
310 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
311 err = bcm54xx_exp_write(phydev, MII_BCM54XX_EXP_EXP75, val);
312 }
313
314error:
315 /* Disable the SMDSP clock */
316 err2 = bcm54xx_auxctl_write(phydev,
317 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
318 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
319
320 /* Return the first error reported. */
321 return err ? err : err2;
322}
323
324static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
325{
326 u32 orig;
327 int val;
328 bool clk125en = true;
329
330 /* Abort if we are using an untested phy. */
331 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
332 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
333 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M)
334 return;
335
336 val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_SCR3);
337 if (val < 0)
338 return;
339
340 orig = val;
341
342 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
343 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
344 BRCM_PHY_REV(phydev) >= 0x3) {
345 /*
346 * Here, bit 0 _disables_ CLK125 when set.
347 * This bit is set by default.
348 */
349 clk125en = false;
350 } else {
351 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
352 /* Here, bit 0 _enables_ CLK125 when set */
353 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
354 clk125en = false;
355 }
356 }
357
358 if (clk125en == false ||
359 (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
360 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
361 else
362 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
363
364 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY)
365 val |= BCM54XX_SHD_SCR3_TRDDAPD;
366
367 if (orig != val)
368 bcm54xx_shadow_write(phydev, BCM54XX_SHD_SCR3, val);
369
370 val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_APD);
371 if (val < 0)
372 return;
373
374 orig = val;
375
376 if (clk125en == false ||
377 (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
378 val |= BCM54XX_SHD_APD_EN;
379 else
380 val &= ~BCM54XX_SHD_APD_EN;
381
382 if (orig != val)
383 bcm54xx_shadow_write(phydev, BCM54XX_SHD_APD, val);
384}
385
386static int bcm54xx_config_init(struct phy_device *phydev)
387{
388 int reg, err;
389
390 reg = phy_read(phydev, MII_BCM54XX_ECR);
391 if (reg < 0)
392 return reg;
393
394 /* Mask interrupts globally. */
395 reg |= MII_BCM54XX_ECR_IM;
396 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
397 if (err < 0)
398 return err;
399
400 /* Unmask events we are interested in. */
401 reg = ~(MII_BCM54XX_INT_DUPLEX |
402 MII_BCM54XX_INT_SPEED |
403 MII_BCM54XX_INT_LINK);
404 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
405 if (err < 0)
406 return err;
407
408 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
409 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
410 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
411 bcm54xx_shadow_write(phydev, BCM54XX_SHD_RGMII_MODE, 0);
412
413 if ((phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) ||
414 (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) ||
415 (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
416 bcm54xx_adjust_rxrefclk(phydev);
417
418 bcm54xx_phydsp_config(phydev);
419
420 return 0;
421}
422
423static int bcm5482_config_init(struct phy_device *phydev)
424{
425 int err, reg;
426
427 err = bcm54xx_config_init(phydev);
428
429 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
430 /*
431 * Enable secondary SerDes and its use as an LED source
432 */
433 reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_SSD);
434 bcm54xx_shadow_write(phydev, BCM5482_SHD_SSD,
435 reg |
436 BCM5482_SHD_SSD_LEDM |
437 BCM5482_SHD_SSD_EN);
438
439 /*
440 * Enable SGMII slave mode and auto-detection
441 */
442 reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD;
443 err = bcm54xx_exp_read(phydev, reg);
444 if (err < 0)
445 return err;
446 err = bcm54xx_exp_write(phydev, reg, err |
447 BCM5482_SSD_SGMII_SLAVE_EN |
448 BCM5482_SSD_SGMII_SLAVE_AD);
449 if (err < 0)
450 return err;
451
452 /*
453 * Disable secondary SerDes powerdown
454 */
455 reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD;
456 err = bcm54xx_exp_read(phydev, reg);
457 if (err < 0)
458 return err;
459 err = bcm54xx_exp_write(phydev, reg,
460 err & ~BCM5482_SSD_1000BX_CTL_PWRDOWN);
461 if (err < 0)
462 return err;
463
464 /*
465 * Select 1000BASE-X register set (primary SerDes)
466 */
467 reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_MODE);
468 bcm54xx_shadow_write(phydev, BCM5482_SHD_MODE,
469 reg | BCM5482_SHD_MODE_1000BX);
470
471 /*
472 * LED1=ACTIVITYLED, LED3=LINKSPD[2]
473 * (Use LED1 as secondary SerDes ACTIVITY LED)
474 */
475 bcm54xx_shadow_write(phydev, BCM5482_SHD_LEDS1,
476 BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
477 BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
478
479 /*
480 * Auto-negotiation doesn't seem to work quite right
481 * in this mode, so we disable it and force it to the
482 * right speed/duplex setting. Only 'link status'
483 * is important.
484 */
485 phydev->autoneg = AUTONEG_DISABLE;
486 phydev->speed = SPEED_1000;
487 phydev->duplex = DUPLEX_FULL;
488 }
489
490 return err;
491}
492
493static int bcm5482_read_status(struct phy_device *phydev)
494{
495 int err;
496
497 err = genphy_read_status(phydev);
498
499 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
500 /*
501 * Only link status matters for 1000Base-X mode, so force
502 * 1000 Mbit/s full-duplex status
503 */
504 if (phydev->link) {
505 phydev->speed = SPEED_1000;
506 phydev->duplex = DUPLEX_FULL;
507 }
508 }
509
510 return err;
511}
512
513static int bcm54xx_ack_interrupt(struct phy_device *phydev)
514{
515 int reg;
516
517 /* Clear pending interrupts. */
518 reg = phy_read(phydev, MII_BCM54XX_ISR);
519 if (reg < 0)
520 return reg;
521
522 return 0;
523}
524
525static int bcm54xx_config_intr(struct phy_device *phydev)
526{
527 int reg, err;
528
529 reg = phy_read(phydev, MII_BCM54XX_ECR);
530 if (reg < 0)
531 return reg;
532
533 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
534 reg &= ~MII_BCM54XX_ECR_IM;
535 else
536 reg |= MII_BCM54XX_ECR_IM;
537
538 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
539 return err;
540}
541
542static int bcm5481_config_aneg(struct phy_device *phydev)
543{
544 int ret;
545
546 /* Aneg firsly. */
547 ret = genphy_config_aneg(phydev);
548
549 /* Then we can set up the delay. */
550 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
551 u16 reg;
552
553 /*
554 * There is no BCM5481 specification available, so down
555 * here is everything we know about "register 0x18". This
556 * at least helps BCM5481 to successfuly receive packets
557 * on MPC8360E-RDK board. Peter Barada <peterb@logicpd.com>
558 * says: "This sets delay between the RXD and RXC signals
559 * instead of using trace lengths to achieve timing".
560 */
561
562 /* Set RDX clk delay. */
563 reg = 0x7 | (0x7 << 12);
564 phy_write(phydev, 0x18, reg);
565
566 reg = phy_read(phydev, 0x18);
567 /* Set RDX-RXC skew. */
568 reg |= (1 << 8);
569 /* Write bits 14:0. */
570 reg |= (1 << 15);
571 phy_write(phydev, 0x18, reg);
572 }
573
574 return ret;
575}
576
577static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
578{
579 int val;
580
581 val = phy_read(phydev, reg);
582 if (val < 0)
583 return val;
584
585 return phy_write(phydev, reg, val | set);
586}
587
588static int brcm_fet_config_init(struct phy_device *phydev)
589{
590 int reg, err, err2, brcmtest;
591
592 /* Reset the PHY to bring it to a known state. */
593 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
594 if (err < 0)
595 return err;
596
597 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
598 if (reg < 0)
599 return reg;
600
601 /* Unmask events we are interested in and mask interrupts globally. */
602 reg = MII_BRCM_FET_IR_DUPLEX_EN |
603 MII_BRCM_FET_IR_SPEED_EN |
604 MII_BRCM_FET_IR_LINK_EN |
605 MII_BRCM_FET_IR_ENABLE |
606 MII_BRCM_FET_IR_MASK;
607
608 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
609 if (err < 0)
610 return err;
611
612 /* Enable shadow register access */
613 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
614 if (brcmtest < 0)
615 return brcmtest;
616
617 reg = brcmtest | MII_BRCM_FET_BT_SRE;
618
619 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
620 if (err < 0)
621 return err;
622
623 /* Set the LED mode */
624 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
625 if (reg < 0) {
626 err = reg;
627 goto done;
628 }
629
630 reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
631 reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
632
633 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
634 if (err < 0)
635 goto done;
636
637 /* Enable auto MDIX */
638 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
639 MII_BRCM_FET_SHDW_MC_FAME);
640 if (err < 0)
641 goto done;
642
643 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
644 /* Enable auto power down */
645 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
646 MII_BRCM_FET_SHDW_AS2_APDE);
647 }
648
649done:
650 /* Disable shadow register access */
651 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
652 if (!err)
653 err = err2;
654
655 return err;
656}
657
658static int brcm_fet_ack_interrupt(struct phy_device *phydev)
659{
660 int reg;
661
662 /* Clear pending interrupts. */
663 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
664 if (reg < 0)
665 return reg;
666
667 return 0;
668}
669
670static int brcm_fet_config_intr(struct phy_device *phydev)
671{
672 int reg, err;
673
674 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
675 if (reg < 0)
676 return reg;
677
678 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
679 reg &= ~MII_BRCM_FET_IR_MASK;
680 else
681 reg |= MII_BRCM_FET_IR_MASK;
682
683 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
684 return err;
685}
686
687static struct phy_driver bcm5411_driver = {
688 .phy_id = PHY_ID_BCM5411,
689 .phy_id_mask = 0xfffffff0,
690 .name = "Broadcom BCM5411",
691 .features = PHY_GBIT_FEATURES |
692 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
693 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
694 .config_init = bcm54xx_config_init,
695 .config_aneg = genphy_config_aneg,
696 .read_status = genphy_read_status,
697 .ack_interrupt = bcm54xx_ack_interrupt,
698 .config_intr = bcm54xx_config_intr,
699 .driver = { .owner = THIS_MODULE },
700};
701
702static struct phy_driver bcm5421_driver = {
703 .phy_id = PHY_ID_BCM5421,
704 .phy_id_mask = 0xfffffff0,
705 .name = "Broadcom BCM5421",
706 .features = PHY_GBIT_FEATURES |
707 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
708 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
709 .config_init = bcm54xx_config_init,
710 .config_aneg = genphy_config_aneg,
711 .read_status = genphy_read_status,
712 .ack_interrupt = bcm54xx_ack_interrupt,
713 .config_intr = bcm54xx_config_intr,
714 .driver = { .owner = THIS_MODULE },
715};
716
717static struct phy_driver bcm5461_driver = {
718 .phy_id = PHY_ID_BCM5461,
719 .phy_id_mask = 0xfffffff0,
720 .name = "Broadcom BCM5461",
721 .features = PHY_GBIT_FEATURES |
722 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
723 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
724 .config_init = bcm54xx_config_init,
725 .config_aneg = genphy_config_aneg,
726 .read_status = genphy_read_status,
727 .ack_interrupt = bcm54xx_ack_interrupt,
728 .config_intr = bcm54xx_config_intr,
729 .driver = { .owner = THIS_MODULE },
730};
731
732static struct phy_driver bcm5464_driver = {
733 .phy_id = PHY_ID_BCM5464,
734 .phy_id_mask = 0xfffffff0,
735 .name = "Broadcom BCM5464",
736 .features = PHY_GBIT_FEATURES |
737 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
738 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
739 .config_init = bcm54xx_config_init,
740 .config_aneg = genphy_config_aneg,
741 .read_status = genphy_read_status,
742 .ack_interrupt = bcm54xx_ack_interrupt,
743 .config_intr = bcm54xx_config_intr,
744 .driver = { .owner = THIS_MODULE },
745};
746
747static struct phy_driver bcm5481_driver = {
748 .phy_id = PHY_ID_BCM5481,
749 .phy_id_mask = 0xfffffff0,
750 .name = "Broadcom BCM5481",
751 .features = PHY_GBIT_FEATURES |
752 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
753 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
754 .config_init = bcm54xx_config_init,
755 .config_aneg = bcm5481_config_aneg,
756 .read_status = genphy_read_status,
757 .ack_interrupt = bcm54xx_ack_interrupt,
758 .config_intr = bcm54xx_config_intr,
759 .driver = { .owner = THIS_MODULE },
760};
761
762static struct phy_driver bcm5482_driver = {
763 .phy_id = PHY_ID_BCM5482,
764 .phy_id_mask = 0xfffffff0,
765 .name = "Broadcom BCM5482",
766 .features = PHY_GBIT_FEATURES |
767 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
768 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
769 .config_init = bcm5482_config_init,
770 .config_aneg = genphy_config_aneg,
771 .read_status = bcm5482_read_status,
772 .ack_interrupt = bcm54xx_ack_interrupt,
773 .config_intr = bcm54xx_config_intr,
774 .driver = { .owner = THIS_MODULE },
775};
776
777static struct phy_driver bcm50610_driver = {
778 .phy_id = PHY_ID_BCM50610,
779 .phy_id_mask = 0xfffffff0,
780 .name = "Broadcom BCM50610",
781 .features = PHY_GBIT_FEATURES |
782 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
783 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
784 .config_init = bcm54xx_config_init,
785 .config_aneg = genphy_config_aneg,
786 .read_status = genphy_read_status,
787 .ack_interrupt = bcm54xx_ack_interrupt,
788 .config_intr = bcm54xx_config_intr,
789 .driver = { .owner = THIS_MODULE },
790};
791
792static struct phy_driver bcm50610m_driver = {
793 .phy_id = PHY_ID_BCM50610M,
794 .phy_id_mask = 0xfffffff0,
795 .name = "Broadcom BCM50610M",
796 .features = PHY_GBIT_FEATURES |
797 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
798 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
799 .config_init = bcm54xx_config_init,
800 .config_aneg = genphy_config_aneg,
801 .read_status = genphy_read_status,
802 .ack_interrupt = bcm54xx_ack_interrupt,
803 .config_intr = bcm54xx_config_intr,
804 .driver = { .owner = THIS_MODULE },
805};
806
807static struct phy_driver bcm57780_driver = {
808 .phy_id = PHY_ID_BCM57780,
809 .phy_id_mask = 0xfffffff0,
810 .name = "Broadcom BCM57780",
811 .features = PHY_GBIT_FEATURES |
812 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
813 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
814 .config_init = bcm54xx_config_init,
815 .config_aneg = genphy_config_aneg,
816 .read_status = genphy_read_status,
817 .ack_interrupt = bcm54xx_ack_interrupt,
818 .config_intr = bcm54xx_config_intr,
819 .driver = { .owner = THIS_MODULE },
820};
821
822static struct phy_driver bcmac131_driver = {
823 .phy_id = PHY_ID_BCMAC131,
824 .phy_id_mask = 0xfffffff0,
825 .name = "Broadcom BCMAC131",
826 .features = PHY_BASIC_FEATURES |
827 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
828 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
829 .config_init = brcm_fet_config_init,
830 .config_aneg = genphy_config_aneg,
831 .read_status = genphy_read_status,
832 .ack_interrupt = brcm_fet_ack_interrupt,
833 .config_intr = brcm_fet_config_intr,
834 .driver = { .owner = THIS_MODULE },
835};
836
837static struct phy_driver bcm5241_driver = {
838 .phy_id = PHY_ID_BCM5241,
839 .phy_id_mask = 0xfffffff0,
840 .name = "Broadcom BCM5241",
841 .features = PHY_BASIC_FEATURES |
842 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
843 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
844 .config_init = brcm_fet_config_init,
845 .config_aneg = genphy_config_aneg,
846 .read_status = genphy_read_status,
847 .ack_interrupt = brcm_fet_ack_interrupt,
848 .config_intr = brcm_fet_config_intr,
849 .driver = { .owner = THIS_MODULE },
850};
851
852static int __init broadcom_init(void)
853{
854 int ret;
855
856 ret = phy_driver_register(&bcm5411_driver);
857 if (ret)
858 goto out_5411;
859 ret = phy_driver_register(&bcm5421_driver);
860 if (ret)
861 goto out_5421;
862 ret = phy_driver_register(&bcm5461_driver);
863 if (ret)
864 goto out_5461;
865 ret = phy_driver_register(&bcm5464_driver);
866 if (ret)
867 goto out_5464;
868 ret = phy_driver_register(&bcm5481_driver);
869 if (ret)
870 goto out_5481;
871 ret = phy_driver_register(&bcm5482_driver);
872 if (ret)
873 goto out_5482;
874 ret = phy_driver_register(&bcm50610_driver);
875 if (ret)
876 goto out_50610;
877 ret = phy_driver_register(&bcm50610m_driver);
878 if (ret)
879 goto out_50610m;
880 ret = phy_driver_register(&bcm57780_driver);
881 if (ret)
882 goto out_57780;
883 ret = phy_driver_register(&bcmac131_driver);
884 if (ret)
885 goto out_ac131;
886 ret = phy_driver_register(&bcm5241_driver);
887 if (ret)
888 goto out_5241;
889 return ret;
890
891out_5241:
892 phy_driver_unregister(&bcmac131_driver);
893out_ac131:
894 phy_driver_unregister(&bcm57780_driver);
895out_57780:
896 phy_driver_unregister(&bcm50610m_driver);
897out_50610m:
898 phy_driver_unregister(&bcm50610_driver);
899out_50610:
900 phy_driver_unregister(&bcm5482_driver);
901out_5482:
902 phy_driver_unregister(&bcm5481_driver);
903out_5481:
904 phy_driver_unregister(&bcm5464_driver);
905out_5464:
906 phy_driver_unregister(&bcm5461_driver);
907out_5461:
908 phy_driver_unregister(&bcm5421_driver);
909out_5421:
910 phy_driver_unregister(&bcm5411_driver);
911out_5411:
912 return ret;
913}
914
915static void __exit broadcom_exit(void)
916{
917 phy_driver_unregister(&bcm5241_driver);
918 phy_driver_unregister(&bcmac131_driver);
919 phy_driver_unregister(&bcm57780_driver);
920 phy_driver_unregister(&bcm50610m_driver);
921 phy_driver_unregister(&bcm50610_driver);
922 phy_driver_unregister(&bcm5482_driver);
923 phy_driver_unregister(&bcm5481_driver);
924 phy_driver_unregister(&bcm5464_driver);
925 phy_driver_unregister(&bcm5461_driver);
926 phy_driver_unregister(&bcm5421_driver);
927 phy_driver_unregister(&bcm5411_driver);
928}
929
930module_init(broadcom_init);
931module_exit(broadcom_exit);
932
933static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
934 { PHY_ID_BCM5411, 0xfffffff0 },
935 { PHY_ID_BCM5421, 0xfffffff0 },
936 { PHY_ID_BCM5461, 0xfffffff0 },
937 { PHY_ID_BCM5464, 0xfffffff0 },
938 { PHY_ID_BCM5482, 0xfffffff0 },
939 { PHY_ID_BCM5482, 0xfffffff0 },
940 { PHY_ID_BCM50610, 0xfffffff0 },
941 { PHY_ID_BCM50610M, 0xfffffff0 },
942 { PHY_ID_BCM57780, 0xfffffff0 },
943 { PHY_ID_BCMAC131, 0xfffffff0 },
944 { PHY_ID_BCM5241, 0xfffffff0 },
945 { }
946};
947
948MODULE_DEVICE_TABLE(mdio, broadcom_tbl);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/broadcom.c
4 *
5 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
6 * transceivers.
7 *
8 * Copyright (c) 2006 Maciej W. Rozycki
9 *
10 * Inspired by code written by Amy Fong.
11 */
12
13#include "bcm-phy-lib.h"
14#include <linux/delay.h>
15#include <linux/module.h>
16#include <linux/phy.h>
17#include <linux/pm_wakeup.h>
18#include <linux/brcmphy.h>
19#include <linux/of.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22#include <linux/gpio/consumer.h>
23
24#define BRCM_PHY_MODEL(phydev) \
25 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
26
27#define BRCM_PHY_REV(phydev) \
28 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
29
30MODULE_DESCRIPTION("Broadcom PHY driver");
31MODULE_AUTHOR("Maciej W. Rozycki");
32MODULE_LICENSE("GPL");
33
34struct bcm54xx_phy_priv {
35 u64 *stats;
36 struct bcm_ptp_private *ptp;
37 int wake_irq;
38 bool wake_irq_enabled;
39};
40
41static bool bcm54xx_phy_can_wakeup(struct phy_device *phydev)
42{
43 struct bcm54xx_phy_priv *priv = phydev->priv;
44
45 return phy_interrupt_is_valid(phydev) || priv->wake_irq >= 0;
46}
47
48static int bcm54xx_config_clock_delay(struct phy_device *phydev)
49{
50 int rc, val;
51
52 /* handling PHY's internal RX clock delay */
53 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
54 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
55 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
56 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
57 /* Disable RGMII RXC-RXD skew */
58 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
59 }
60 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
61 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
62 /* Enable RGMII RXC-RXD skew */
63 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
64 }
65 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
66 val);
67 if (rc < 0)
68 return rc;
69
70 /* handling PHY's internal TX clock delay */
71 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
72 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
73 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
74 /* Disable internal TX clock delay */
75 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
76 }
77 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
78 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
79 /* Enable internal TX clock delay */
80 val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN;
81 }
82 rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
83 if (rc < 0)
84 return rc;
85
86 return 0;
87}
88
89static int bcm54210e_config_init(struct phy_device *phydev)
90{
91 int val;
92
93 bcm54xx_config_clock_delay(phydev);
94
95 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) {
96 val = phy_read(phydev, MII_CTRL1000);
97 val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
98 phy_write(phydev, MII_CTRL1000, val);
99 }
100
101 return 0;
102}
103
104static int bcm54612e_config_init(struct phy_device *phydev)
105{
106 int reg;
107
108 bcm54xx_config_clock_delay(phydev);
109
110 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
111 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
112 int err;
113
114 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
115 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
116 BCM54612E_LED4_CLK125OUT_EN | reg);
117
118 if (err < 0)
119 return err;
120 }
121
122 return 0;
123}
124
125static int bcm54616s_config_init(struct phy_device *phydev)
126{
127 int rc, val;
128
129 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
130 phydev->interface != PHY_INTERFACE_MODE_1000BASEX)
131 return 0;
132
133 /* Ensure proper interface mode is selected. */
134 /* Disable RGMII mode */
135 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
136 if (val < 0)
137 return val;
138 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN;
139 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
140 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
141 val);
142 if (rc < 0)
143 return rc;
144
145 /* Select 1000BASE-X register set (primary SerDes) */
146 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
147 if (val < 0)
148 return val;
149 val |= BCM54XX_SHD_MODE_1000BX;
150 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
151 if (rc < 0)
152 return rc;
153
154 /* Power down SerDes interface */
155 rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
156 if (rc < 0)
157 return rc;
158
159 /* Select proper interface mode */
160 val &= ~BCM54XX_SHD_INTF_SEL_MASK;
161 val |= phydev->interface == PHY_INTERFACE_MODE_SGMII ?
162 BCM54XX_SHD_INTF_SEL_SGMII :
163 BCM54XX_SHD_INTF_SEL_GBIC;
164 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
165 if (rc < 0)
166 return rc;
167
168 /* Power up SerDes interface */
169 rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
170 if (rc < 0)
171 return rc;
172
173 /* Select copper register set */
174 val &= ~BCM54XX_SHD_MODE_1000BX;
175 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
176 if (rc < 0)
177 return rc;
178
179 /* Power up copper interface */
180 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
181}
182
183/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
184static int bcm50610_a0_workaround(struct phy_device *phydev)
185{
186 int err;
187
188 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
189 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
190 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
191 if (err < 0)
192 return err;
193
194 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
195 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
196 if (err < 0)
197 return err;
198
199 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
200 MII_BCM54XX_EXP_EXP75_VDACCTRL);
201 if (err < 0)
202 return err;
203
204 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
205 MII_BCM54XX_EXP_EXP96_MYST);
206 if (err < 0)
207 return err;
208
209 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
210 MII_BCM54XX_EXP_EXP97_MYST);
211
212 return err;
213}
214
215static int bcm54xx_phydsp_config(struct phy_device *phydev)
216{
217 int err, err2;
218
219 /* Enable the SMDSP clock */
220 err = bcm54xx_auxctl_write(phydev,
221 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
222 MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
223 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
224 if (err < 0)
225 return err;
226
227 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
228 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
229 /* Clear bit 9 to fix a phy interop issue. */
230 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
231 MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
232 if (err < 0)
233 goto error;
234
235 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
236 err = bcm50610_a0_workaround(phydev);
237 if (err < 0)
238 goto error;
239 }
240 }
241
242 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
243 int val;
244
245 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
246 if (val < 0)
247 goto error;
248
249 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
250 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
251 }
252
253error:
254 /* Disable the SMDSP clock */
255 err2 = bcm54xx_auxctl_write(phydev,
256 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
257 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
258
259 /* Return the first error reported. */
260 return err ? err : err2;
261}
262
263static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
264{
265 u32 orig;
266 int val;
267 bool clk125en = true;
268
269 /* Abort if we are using an untested phy. */
270 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
271 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
272 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M &&
273 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54210E &&
274 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54810 &&
275 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811)
276 return;
277
278 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
279 if (val < 0)
280 return;
281
282 orig = val;
283
284 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
285 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
286 BRCM_PHY_REV(phydev) >= 0x3) {
287 /*
288 * Here, bit 0 _disables_ CLK125 when set.
289 * This bit is set by default.
290 */
291 clk125en = false;
292 } else {
293 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
294 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811) {
295 /* Here, bit 0 _enables_ CLK125 when set */
296 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
297 }
298 clk125en = false;
299 }
300 }
301
302 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
303 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
304 else
305 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
306
307 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) {
308 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E ||
309 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 ||
310 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54811)
311 val |= BCM54XX_SHD_SCR3_RXCTXC_DIS;
312 else
313 val |= BCM54XX_SHD_SCR3_TRDDAPD;
314 }
315
316 if (orig != val)
317 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
318
319 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
320 if (val < 0)
321 return;
322
323 orig = val;
324
325 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
326 val |= BCM54XX_SHD_APD_EN;
327 else
328 val &= ~BCM54XX_SHD_APD_EN;
329
330 if (orig != val)
331 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
332}
333
334static void bcm54xx_ptp_stop(struct phy_device *phydev)
335{
336 struct bcm54xx_phy_priv *priv = phydev->priv;
337
338 if (priv->ptp)
339 bcm_ptp_stop(priv->ptp);
340}
341
342static void bcm54xx_ptp_config_init(struct phy_device *phydev)
343{
344 struct bcm54xx_phy_priv *priv = phydev->priv;
345
346 if (priv->ptp)
347 bcm_ptp_config_init(phydev);
348}
349
350static int bcm54xx_config_init(struct phy_device *phydev)
351{
352 int reg, err, val;
353
354 reg = phy_read(phydev, MII_BCM54XX_ECR);
355 if (reg < 0)
356 return reg;
357
358 /* Mask interrupts globally. */
359 reg |= MII_BCM54XX_ECR_IM;
360 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
361 if (err < 0)
362 return err;
363
364 /* Unmask events we are interested in. */
365 reg = ~(MII_BCM54XX_INT_DUPLEX |
366 MII_BCM54XX_INT_SPEED |
367 MII_BCM54XX_INT_LINK);
368 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
369 if (err < 0)
370 return err;
371
372 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
373 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
374 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
375 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
376
377 bcm54xx_adjust_rxrefclk(phydev);
378
379 switch (BRCM_PHY_MODEL(phydev)) {
380 case PHY_ID_BCM50610:
381 case PHY_ID_BCM50610M:
382 err = bcm54xx_config_clock_delay(phydev);
383 break;
384 case PHY_ID_BCM54210E:
385 err = bcm54210e_config_init(phydev);
386 break;
387 case PHY_ID_BCM54612E:
388 err = bcm54612e_config_init(phydev);
389 break;
390 case PHY_ID_BCM54616S:
391 err = bcm54616s_config_init(phydev);
392 break;
393 case PHY_ID_BCM54810:
394 /* For BCM54810, we need to disable BroadR-Reach function */
395 val = bcm_phy_read_exp(phydev,
396 BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
397 val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
398 err = bcm_phy_write_exp(phydev,
399 BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
400 val);
401 break;
402 }
403 if (err)
404 return err;
405
406 bcm54xx_phydsp_config(phydev);
407
408 /* For non-SFP setups, encode link speed into LED1 and LED3 pair
409 * (green/amber).
410 * Also flash these two LEDs on activity. This means configuring
411 * them for MULTICOLOR and encoding link/activity into them.
412 * Don't do this for devices on an SFP module, since some of these
413 * use the LED outputs to control the SFP LOS signal, and changing
414 * these settings will cause LOS to malfunction.
415 */
416 if (!phy_on_sfp(phydev)) {
417 val = BCM54XX_SHD_LEDS1_LED1(BCM_LED_SRC_MULTICOLOR1) |
418 BCM54XX_SHD_LEDS1_LED3(BCM_LED_SRC_MULTICOLOR1);
419 bcm_phy_write_shadow(phydev, BCM54XX_SHD_LEDS1, val);
420
421 val = BCM_LED_MULTICOLOR_IN_PHASE |
422 BCM54XX_SHD_LEDS1_LED1(BCM_LED_MULTICOLOR_LINK_ACT) |
423 BCM54XX_SHD_LEDS1_LED3(BCM_LED_MULTICOLOR_LINK_ACT);
424 bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val);
425 }
426
427 bcm54xx_ptp_config_init(phydev);
428
429 /* Acknowledge any left over interrupt and charge the device for
430 * wake-up.
431 */
432 err = bcm_phy_read_exp(phydev, BCM54XX_WOL_INT_STATUS);
433 if (err < 0)
434 return err;
435
436 if (err)
437 pm_wakeup_event(&phydev->mdio.dev, 0);
438
439 return 0;
440}
441
442static int bcm54xx_iddq_set(struct phy_device *phydev, bool enable)
443{
444 int ret = 0;
445
446 if (!(phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND))
447 return ret;
448
449 ret = bcm_phy_read_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL);
450 if (ret < 0)
451 goto out;
452
453 if (enable)
454 ret |= BCM54XX_TOP_MISC_IDDQ_SR | BCM54XX_TOP_MISC_IDDQ_LP;
455 else
456 ret &= ~(BCM54XX_TOP_MISC_IDDQ_SR | BCM54XX_TOP_MISC_IDDQ_LP);
457
458 ret = bcm_phy_write_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL, ret);
459out:
460 return ret;
461}
462
463static int bcm54xx_set_wakeup_irq(struct phy_device *phydev, bool state)
464{
465 struct bcm54xx_phy_priv *priv = phydev->priv;
466 int ret = 0;
467
468 if (!bcm54xx_phy_can_wakeup(phydev))
469 return ret;
470
471 if (priv->wake_irq_enabled != state) {
472 if (state)
473 ret = enable_irq_wake(priv->wake_irq);
474 else
475 ret = disable_irq_wake(priv->wake_irq);
476 priv->wake_irq_enabled = state;
477 }
478
479 return ret;
480}
481
482static int bcm54xx_suspend(struct phy_device *phydev)
483{
484 int ret = 0;
485
486 bcm54xx_ptp_stop(phydev);
487
488 /* Acknowledge any Wake-on-LAN interrupt prior to suspend */
489 ret = bcm_phy_read_exp(phydev, BCM54XX_WOL_INT_STATUS);
490 if (ret < 0)
491 return ret;
492
493 if (phydev->wol_enabled)
494 return bcm54xx_set_wakeup_irq(phydev, true);
495
496 /* We cannot use a read/modify/write here otherwise the PHY gets into
497 * a bad state where its LEDs keep flashing, thus defeating the purpose
498 * of low power mode.
499 */
500 ret = phy_write(phydev, MII_BMCR, BMCR_PDOWN);
501 if (ret < 0)
502 return ret;
503
504 return bcm54xx_iddq_set(phydev, true);
505}
506
507static int bcm54xx_resume(struct phy_device *phydev)
508{
509 int ret = 0;
510
511 if (phydev->wol_enabled) {
512 ret = bcm54xx_set_wakeup_irq(phydev, false);
513 if (ret)
514 return ret;
515 }
516
517 ret = bcm54xx_iddq_set(phydev, false);
518 if (ret < 0)
519 return ret;
520
521 /* Writes to register other than BMCR would be ignored
522 * unless we clear the PDOWN bit first
523 */
524 ret = genphy_resume(phydev);
525 if (ret < 0)
526 return ret;
527
528 /* Upon exiting power down, the PHY remains in an internal reset state
529 * for 40us
530 */
531 fsleep(40);
532
533 /* Issue a soft reset after clearing the power down bit
534 * and before doing any other configuration.
535 */
536 if (phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND) {
537 ret = genphy_soft_reset(phydev);
538 if (ret < 0)
539 return ret;
540 }
541
542 return bcm54xx_config_init(phydev);
543}
544
545static int bcm54810_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
546{
547 return -EOPNOTSUPP;
548}
549
550static int bcm54810_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
551 u16 val)
552{
553 return -EOPNOTSUPP;
554}
555
556static int bcm54811_config_init(struct phy_device *phydev)
557{
558 int err, reg;
559
560 /* Disable BroadR-Reach function. */
561 reg = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
562 reg &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
563 err = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
564 reg);
565 if (err < 0)
566 return err;
567
568 err = bcm54xx_config_init(phydev);
569
570 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
571 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
572 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
573 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
574 BCM54612E_LED4_CLK125OUT_EN | reg);
575 if (err < 0)
576 return err;
577 }
578
579 return err;
580}
581
582static int bcm5481_config_aneg(struct phy_device *phydev)
583{
584 struct device_node *np = phydev->mdio.dev.of_node;
585 int ret;
586
587 /* Aneg firstly. */
588 ret = genphy_config_aneg(phydev);
589
590 /* Then we can set up the delay. */
591 bcm54xx_config_clock_delay(phydev);
592
593 if (of_property_read_bool(np, "enet-phy-lane-swap")) {
594 /* Lane Swap - Undocumented register...magic! */
595 ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
596 0x11B);
597 if (ret < 0)
598 return ret;
599 }
600
601 return ret;
602}
603
604struct bcm54616s_phy_priv {
605 bool mode_1000bx_en;
606};
607
608static int bcm54616s_probe(struct phy_device *phydev)
609{
610 struct bcm54616s_phy_priv *priv;
611 int val;
612
613 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
614 if (!priv)
615 return -ENOMEM;
616
617 phydev->priv = priv;
618
619 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
620 if (val < 0)
621 return val;
622
623 /* The PHY is strapped in RGMII-fiber mode when INTERF_SEL[1:0]
624 * is 01b, and the link between PHY and its link partner can be
625 * either 1000Base-X or 100Base-FX.
626 * RGMII-1000Base-X is properly supported, but RGMII-100Base-FX
627 * support is still missing as of now.
628 */
629 if ((val & BCM54XX_SHD_INTF_SEL_MASK) == BCM54XX_SHD_INTF_SEL_RGMII) {
630 val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL);
631 if (val < 0)
632 return val;
633
634 /* Bit 0 of the SerDes 100-FX Control register, when set
635 * to 1, sets the MII/RGMII -> 100BASE-FX configuration.
636 * When this bit is set to 0, it sets the GMII/RGMII ->
637 * 1000BASE-X configuration.
638 */
639 if (!(val & BCM54616S_100FX_MODE))
640 priv->mode_1000bx_en = true;
641
642 phydev->port = PORT_FIBRE;
643 }
644
645 return 0;
646}
647
648static int bcm54616s_config_aneg(struct phy_device *phydev)
649{
650 struct bcm54616s_phy_priv *priv = phydev->priv;
651 int ret;
652
653 /* Aneg firstly. */
654 if (priv->mode_1000bx_en)
655 ret = genphy_c37_config_aneg(phydev);
656 else
657 ret = genphy_config_aneg(phydev);
658
659 /* Then we can set up the delay. */
660 bcm54xx_config_clock_delay(phydev);
661
662 return ret;
663}
664
665static int bcm54616s_read_status(struct phy_device *phydev)
666{
667 struct bcm54616s_phy_priv *priv = phydev->priv;
668 bool changed;
669 int err;
670
671 if (priv->mode_1000bx_en)
672 err = genphy_c37_read_status(phydev, &changed);
673 else
674 err = genphy_read_status(phydev);
675
676 return err;
677}
678
679static int brcm_fet_config_init(struct phy_device *phydev)
680{
681 int reg, err, err2, brcmtest;
682
683 /* Reset the PHY to bring it to a known state. */
684 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
685 if (err < 0)
686 return err;
687
688 /* The datasheet indicates the PHY needs up to 1us to complete a reset,
689 * build some slack here.
690 */
691 usleep_range(1000, 2000);
692
693 /* The PHY requires 65 MDC clock cycles to complete a write operation
694 * and turnaround the line properly.
695 *
696 * We ignore -EIO here as the MDIO controller (e.g.: mdio-bcm-unimac)
697 * may flag the lack of turn-around as a read failure. This is
698 * particularly true with this combination since the MDIO controller
699 * only used 64 MDC cycles. This is not a critical failure in this
700 * specific case and it has no functional impact otherwise, so we let
701 * that one go through. If there is a genuine bus error, the next read
702 * of MII_BRCM_FET_INTREG will error out.
703 */
704 err = phy_read(phydev, MII_BMCR);
705 if (err < 0 && err != -EIO)
706 return err;
707
708 /* Read to clear status bits */
709 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
710 if (reg < 0)
711 return reg;
712
713 /* Unmask events we are interested in and mask interrupts globally. */
714 if (phydev->phy_id == PHY_ID_BCM5221)
715 reg = MII_BRCM_FET_IR_ENABLE |
716 MII_BRCM_FET_IR_MASK;
717 else
718 reg = MII_BRCM_FET_IR_DUPLEX_EN |
719 MII_BRCM_FET_IR_SPEED_EN |
720 MII_BRCM_FET_IR_LINK_EN |
721 MII_BRCM_FET_IR_ENABLE |
722 MII_BRCM_FET_IR_MASK;
723
724 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
725 if (err < 0)
726 return err;
727
728 /* Enable shadow register access */
729 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
730 if (brcmtest < 0)
731 return brcmtest;
732
733 reg = brcmtest | MII_BRCM_FET_BT_SRE;
734
735 phy_lock_mdio_bus(phydev);
736
737 err = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
738 if (err < 0) {
739 phy_unlock_mdio_bus(phydev);
740 return err;
741 }
742
743 if (phydev->phy_id != PHY_ID_BCM5221) {
744 /* Set the LED mode */
745 reg = __phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
746 if (reg < 0) {
747 err = reg;
748 goto done;
749 }
750
751 err = __phy_modify(phydev, MII_BRCM_FET_SHDW_AUXMODE4,
752 MII_BRCM_FET_SHDW_AM4_LED_MASK,
753 MII_BRCM_FET_SHDW_AM4_LED_MODE1);
754 if (err < 0)
755 goto done;
756
757 /* Enable auto MDIX */
758 err = __phy_set_bits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
759 MII_BRCM_FET_SHDW_MC_FAME);
760 if (err < 0)
761 goto done;
762 }
763
764 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
765 /* Enable auto power down */
766 err = __phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
767 MII_BRCM_FET_SHDW_AS2_APDE);
768 }
769
770done:
771 /* Disable shadow register access */
772 err2 = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
773 if (!err)
774 err = err2;
775
776 phy_unlock_mdio_bus(phydev);
777
778 return err;
779}
780
781static int brcm_fet_ack_interrupt(struct phy_device *phydev)
782{
783 int reg;
784
785 /* Clear pending interrupts. */
786 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
787 if (reg < 0)
788 return reg;
789
790 return 0;
791}
792
793static int brcm_fet_config_intr(struct phy_device *phydev)
794{
795 int reg, err;
796
797 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
798 if (reg < 0)
799 return reg;
800
801 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
802 err = brcm_fet_ack_interrupt(phydev);
803 if (err)
804 return err;
805
806 reg &= ~MII_BRCM_FET_IR_MASK;
807 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
808 } else {
809 reg |= MII_BRCM_FET_IR_MASK;
810 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
811 if (err)
812 return err;
813
814 err = brcm_fet_ack_interrupt(phydev);
815 }
816
817 return err;
818}
819
820static irqreturn_t brcm_fet_handle_interrupt(struct phy_device *phydev)
821{
822 int irq_status;
823
824 irq_status = phy_read(phydev, MII_BRCM_FET_INTREG);
825 if (irq_status < 0) {
826 phy_error(phydev);
827 return IRQ_NONE;
828 }
829
830 if (irq_status == 0)
831 return IRQ_NONE;
832
833 phy_trigger_machine(phydev);
834
835 return IRQ_HANDLED;
836}
837
838static int brcm_fet_suspend(struct phy_device *phydev)
839{
840 int reg, err, err2, brcmtest;
841
842 /* We cannot use a read/modify/write here otherwise the PHY continues
843 * to drive LEDs which defeats the purpose of low power mode.
844 */
845 err = phy_write(phydev, MII_BMCR, BMCR_PDOWN);
846 if (err < 0)
847 return err;
848
849 /* Enable shadow register access */
850 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
851 if (brcmtest < 0)
852 return brcmtest;
853
854 reg = brcmtest | MII_BRCM_FET_BT_SRE;
855
856 phy_lock_mdio_bus(phydev);
857
858 err = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
859 if (err < 0) {
860 phy_unlock_mdio_bus(phydev);
861 return err;
862 }
863
864 if (phydev->phy_id == PHY_ID_BCM5221)
865 /* Force Low Power Mode with clock enabled */
866 reg = BCM5221_SHDW_AM4_EN_CLK_LPM | BCM5221_SHDW_AM4_FORCE_LPM;
867 else
868 /* Set standby mode */
869 reg = MII_BRCM_FET_SHDW_AM4_STANDBY;
870
871 err = __phy_set_bits(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
872
873 /* Disable shadow register access */
874 err2 = __phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
875 if (!err)
876 err = err2;
877
878 phy_unlock_mdio_bus(phydev);
879
880 return err;
881}
882
883static int bcm5221_config_aneg(struct phy_device *phydev)
884{
885 int ret, val;
886
887 ret = genphy_config_aneg(phydev);
888 if (ret)
889 return ret;
890
891 switch (phydev->mdix_ctrl) {
892 case ETH_TP_MDI:
893 val = BCM5221_AEGSR_MDIX_DIS;
894 break;
895 case ETH_TP_MDI_X:
896 val = BCM5221_AEGSR_MDIX_DIS | BCM5221_AEGSR_MDIX_MAN_SWAP;
897 break;
898 case ETH_TP_MDI_AUTO:
899 val = 0;
900 break;
901 default:
902 return 0;
903 }
904
905 return phy_modify(phydev, BCM5221_AEGSR, BCM5221_AEGSR_MDIX_MAN_SWAP |
906 BCM5221_AEGSR_MDIX_DIS,
907 val);
908}
909
910static int bcm5221_read_status(struct phy_device *phydev)
911{
912 int ret;
913
914 /* Read MDIX status */
915 ret = phy_read(phydev, BCM5221_AEGSR);
916 if (ret < 0)
917 return ret;
918
919 if (ret & BCM5221_AEGSR_MDIX_DIS) {
920 if (ret & BCM5221_AEGSR_MDIX_MAN_SWAP)
921 phydev->mdix_ctrl = ETH_TP_MDI_X;
922 else
923 phydev->mdix_ctrl = ETH_TP_MDI;
924 } else {
925 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
926 }
927
928 if (ret & BCM5221_AEGSR_MDIX_STATUS)
929 phydev->mdix = ETH_TP_MDI_X;
930 else
931 phydev->mdix = ETH_TP_MDI;
932
933 return genphy_read_status(phydev);
934}
935
936static void bcm54xx_phy_get_wol(struct phy_device *phydev,
937 struct ethtool_wolinfo *wol)
938{
939 /* We cannot wake-up if we do not have a dedicated PHY interrupt line
940 * or an out of band GPIO descriptor for wake-up. Zeroing
941 * wol->supported allows the caller (MAC driver) to play through and
942 * offer its own Wake-on-LAN scheme if available.
943 */
944 if (!bcm54xx_phy_can_wakeup(phydev)) {
945 wol->supported = 0;
946 return;
947 }
948
949 bcm_phy_get_wol(phydev, wol);
950}
951
952static int bcm54xx_phy_set_wol(struct phy_device *phydev,
953 struct ethtool_wolinfo *wol)
954{
955 int ret;
956
957 /* We cannot wake-up if we do not have a dedicated PHY interrupt line
958 * or an out of band GPIO descriptor for wake-up. Returning -EOPNOTSUPP
959 * allows the caller (MAC driver) to play through and offer its own
960 * Wake-on-LAN scheme if available.
961 */
962 if (!bcm54xx_phy_can_wakeup(phydev))
963 return -EOPNOTSUPP;
964
965 ret = bcm_phy_set_wol(phydev, wol);
966 if (ret < 0)
967 return ret;
968
969 return 0;
970}
971
972static int bcm54xx_phy_probe(struct phy_device *phydev)
973{
974 struct bcm54xx_phy_priv *priv;
975 struct gpio_desc *wakeup_gpio;
976 int ret = 0;
977
978 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
979 if (!priv)
980 return -ENOMEM;
981
982 priv->wake_irq = -ENXIO;
983
984 phydev->priv = priv;
985
986 priv->stats = devm_kcalloc(&phydev->mdio.dev,
987 bcm_phy_get_sset_count(phydev), sizeof(u64),
988 GFP_KERNEL);
989 if (!priv->stats)
990 return -ENOMEM;
991
992 priv->ptp = bcm_ptp_probe(phydev);
993 if (IS_ERR(priv->ptp))
994 return PTR_ERR(priv->ptp);
995
996 /* We cannot utilize the _optional variant here since we want to know
997 * whether the GPIO descriptor exists or not to advertise Wake-on-LAN
998 * support or not.
999 */
1000 wakeup_gpio = devm_gpiod_get(&phydev->mdio.dev, "wakeup", GPIOD_IN);
1001 if (PTR_ERR(wakeup_gpio) == -EPROBE_DEFER)
1002 return PTR_ERR(wakeup_gpio);
1003
1004 if (!IS_ERR(wakeup_gpio)) {
1005 priv->wake_irq = gpiod_to_irq(wakeup_gpio);
1006
1007 /* Dummy interrupt handler which is not enabled but is provided
1008 * in order for the interrupt descriptor to be fully set-up.
1009 */
1010 ret = devm_request_irq(&phydev->mdio.dev, priv->wake_irq,
1011 bcm_phy_wol_isr,
1012 IRQF_TRIGGER_LOW | IRQF_NO_AUTOEN,
1013 dev_name(&phydev->mdio.dev), phydev);
1014 if (ret)
1015 return ret;
1016 }
1017
1018 /* If we do not have a main interrupt or a side-band wake-up interrupt,
1019 * then the device cannot be marked as wake-up capable.
1020 */
1021 if (!bcm54xx_phy_can_wakeup(phydev))
1022 return 0;
1023
1024 return device_init_wakeup(&phydev->mdio.dev, true);
1025}
1026
1027static void bcm54xx_get_stats(struct phy_device *phydev,
1028 struct ethtool_stats *stats, u64 *data)
1029{
1030 struct bcm54xx_phy_priv *priv = phydev->priv;
1031
1032 bcm_phy_get_stats(phydev, priv->stats, stats, data);
1033}
1034
1035static void bcm54xx_link_change_notify(struct phy_device *phydev)
1036{
1037 u16 mask = MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE |
1038 MII_BCM54XX_EXP_EXP08_FORCE_DAC_WAKE;
1039 int ret;
1040
1041 if (phydev->state != PHY_RUNNING)
1042 return;
1043
1044 /* Don't change the DAC wake settings if auto power down
1045 * is not requested.
1046 */
1047 if (!(phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
1048 return;
1049
1050 ret = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP08);
1051 if (ret < 0)
1052 return;
1053
1054 /* Enable/disable 10BaseT auto and forced early DAC wake depending
1055 * on the negotiated speed, those settings should only be done
1056 * for 10Mbits/sec.
1057 */
1058 if (phydev->speed == SPEED_10)
1059 ret |= mask;
1060 else
1061 ret &= ~mask;
1062 bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08, ret);
1063}
1064
1065static struct phy_driver broadcom_drivers[] = {
1066{
1067 .phy_id = PHY_ID_BCM5411,
1068 .phy_id_mask = 0xfffffff0,
1069 .name = "Broadcom BCM5411",
1070 /* PHY_GBIT_FEATURES */
1071 .get_sset_count = bcm_phy_get_sset_count,
1072 .get_strings = bcm_phy_get_strings,
1073 .get_stats = bcm54xx_get_stats,
1074 .probe = bcm54xx_phy_probe,
1075 .config_init = bcm54xx_config_init,
1076 .config_intr = bcm_phy_config_intr,
1077 .handle_interrupt = bcm_phy_handle_interrupt,
1078 .link_change_notify = bcm54xx_link_change_notify,
1079}, {
1080 .phy_id = PHY_ID_BCM5421,
1081 .phy_id_mask = 0xfffffff0,
1082 .name = "Broadcom BCM5421",
1083 /* PHY_GBIT_FEATURES */
1084 .get_sset_count = bcm_phy_get_sset_count,
1085 .get_strings = bcm_phy_get_strings,
1086 .get_stats = bcm54xx_get_stats,
1087 .probe = bcm54xx_phy_probe,
1088 .config_init = bcm54xx_config_init,
1089 .config_intr = bcm_phy_config_intr,
1090 .handle_interrupt = bcm_phy_handle_interrupt,
1091 .link_change_notify = bcm54xx_link_change_notify,
1092}, {
1093 .phy_id = PHY_ID_BCM54210E,
1094 .phy_id_mask = 0xfffffff0,
1095 .name = "Broadcom BCM54210E",
1096 /* PHY_GBIT_FEATURES */
1097 .flags = PHY_ALWAYS_CALL_SUSPEND,
1098 .get_sset_count = bcm_phy_get_sset_count,
1099 .get_strings = bcm_phy_get_strings,
1100 .get_stats = bcm54xx_get_stats,
1101 .probe = bcm54xx_phy_probe,
1102 .config_init = bcm54xx_config_init,
1103 .config_intr = bcm_phy_config_intr,
1104 .handle_interrupt = bcm_phy_handle_interrupt,
1105 .link_change_notify = bcm54xx_link_change_notify,
1106 .suspend = bcm54xx_suspend,
1107 .resume = bcm54xx_resume,
1108 .get_wol = bcm54xx_phy_get_wol,
1109 .set_wol = bcm54xx_phy_set_wol,
1110 .led_brightness_set = bcm_phy_led_brightness_set,
1111}, {
1112 .phy_id = PHY_ID_BCM5461,
1113 .phy_id_mask = 0xfffffff0,
1114 .name = "Broadcom BCM5461",
1115 /* PHY_GBIT_FEATURES */
1116 .get_sset_count = bcm_phy_get_sset_count,
1117 .get_strings = bcm_phy_get_strings,
1118 .get_stats = bcm54xx_get_stats,
1119 .probe = bcm54xx_phy_probe,
1120 .config_init = bcm54xx_config_init,
1121 .config_intr = bcm_phy_config_intr,
1122 .handle_interrupt = bcm_phy_handle_interrupt,
1123 .link_change_notify = bcm54xx_link_change_notify,
1124 .led_brightness_set = bcm_phy_led_brightness_set,
1125}, {
1126 .phy_id = PHY_ID_BCM54612E,
1127 .phy_id_mask = 0xfffffff0,
1128 .name = "Broadcom BCM54612E",
1129 /* PHY_GBIT_FEATURES */
1130 .get_sset_count = bcm_phy_get_sset_count,
1131 .get_strings = bcm_phy_get_strings,
1132 .get_stats = bcm54xx_get_stats,
1133 .probe = bcm54xx_phy_probe,
1134 .config_init = bcm54xx_config_init,
1135 .config_intr = bcm_phy_config_intr,
1136 .handle_interrupt = bcm_phy_handle_interrupt,
1137 .link_change_notify = bcm54xx_link_change_notify,
1138 .led_brightness_set = bcm_phy_led_brightness_set,
1139 .suspend = bcm54xx_suspend,
1140 .resume = bcm54xx_resume,
1141}, {
1142 .phy_id = PHY_ID_BCM54616S,
1143 .phy_id_mask = 0xfffffff0,
1144 .name = "Broadcom BCM54616S",
1145 /* PHY_GBIT_FEATURES */
1146 .soft_reset = genphy_soft_reset,
1147 .config_init = bcm54xx_config_init,
1148 .config_aneg = bcm54616s_config_aneg,
1149 .config_intr = bcm_phy_config_intr,
1150 .handle_interrupt = bcm_phy_handle_interrupt,
1151 .read_status = bcm54616s_read_status,
1152 .probe = bcm54616s_probe,
1153 .link_change_notify = bcm54xx_link_change_notify,
1154 .led_brightness_set = bcm_phy_led_brightness_set,
1155}, {
1156 .phy_id = PHY_ID_BCM5464,
1157 .phy_id_mask = 0xfffffff0,
1158 .name = "Broadcom BCM5464",
1159 /* PHY_GBIT_FEATURES */
1160 .get_sset_count = bcm_phy_get_sset_count,
1161 .get_strings = bcm_phy_get_strings,
1162 .get_stats = bcm54xx_get_stats,
1163 .probe = bcm54xx_phy_probe,
1164 .config_init = bcm54xx_config_init,
1165 .config_intr = bcm_phy_config_intr,
1166 .handle_interrupt = bcm_phy_handle_interrupt,
1167 .suspend = genphy_suspend,
1168 .resume = genphy_resume,
1169 .link_change_notify = bcm54xx_link_change_notify,
1170 .led_brightness_set = bcm_phy_led_brightness_set,
1171}, {
1172 .phy_id = PHY_ID_BCM5481,
1173 .phy_id_mask = 0xfffffff0,
1174 .name = "Broadcom BCM5481",
1175 /* PHY_GBIT_FEATURES */
1176 .get_sset_count = bcm_phy_get_sset_count,
1177 .get_strings = bcm_phy_get_strings,
1178 .get_stats = bcm54xx_get_stats,
1179 .probe = bcm54xx_phy_probe,
1180 .config_init = bcm54xx_config_init,
1181 .config_aneg = bcm5481_config_aneg,
1182 .config_intr = bcm_phy_config_intr,
1183 .handle_interrupt = bcm_phy_handle_interrupt,
1184 .link_change_notify = bcm54xx_link_change_notify,
1185 .led_brightness_set = bcm_phy_led_brightness_set,
1186}, {
1187 .phy_id = PHY_ID_BCM54810,
1188 .phy_id_mask = 0xfffffff0,
1189 .name = "Broadcom BCM54810",
1190 /* PHY_GBIT_FEATURES */
1191 .get_sset_count = bcm_phy_get_sset_count,
1192 .get_strings = bcm_phy_get_strings,
1193 .get_stats = bcm54xx_get_stats,
1194 .probe = bcm54xx_phy_probe,
1195 .read_mmd = bcm54810_read_mmd,
1196 .write_mmd = bcm54810_write_mmd,
1197 .config_init = bcm54xx_config_init,
1198 .config_aneg = bcm5481_config_aneg,
1199 .config_intr = bcm_phy_config_intr,
1200 .handle_interrupt = bcm_phy_handle_interrupt,
1201 .suspend = bcm54xx_suspend,
1202 .resume = bcm54xx_resume,
1203 .link_change_notify = bcm54xx_link_change_notify,
1204 .led_brightness_set = bcm_phy_led_brightness_set,
1205}, {
1206 .phy_id = PHY_ID_BCM54811,
1207 .phy_id_mask = 0xfffffff0,
1208 .name = "Broadcom BCM54811",
1209 /* PHY_GBIT_FEATURES */
1210 .get_sset_count = bcm_phy_get_sset_count,
1211 .get_strings = bcm_phy_get_strings,
1212 .get_stats = bcm54xx_get_stats,
1213 .probe = bcm54xx_phy_probe,
1214 .config_init = bcm54811_config_init,
1215 .config_aneg = bcm5481_config_aneg,
1216 .config_intr = bcm_phy_config_intr,
1217 .handle_interrupt = bcm_phy_handle_interrupt,
1218 .suspend = bcm54xx_suspend,
1219 .resume = bcm54xx_resume,
1220 .link_change_notify = bcm54xx_link_change_notify,
1221 .led_brightness_set = bcm_phy_led_brightness_set,
1222}, {
1223 .phy_id = PHY_ID_BCM5482,
1224 .phy_id_mask = 0xfffffff0,
1225 .name = "Broadcom BCM5482",
1226 /* PHY_GBIT_FEATURES */
1227 .get_sset_count = bcm_phy_get_sset_count,
1228 .get_strings = bcm_phy_get_strings,
1229 .get_stats = bcm54xx_get_stats,
1230 .probe = bcm54xx_phy_probe,
1231 .config_init = bcm54xx_config_init,
1232 .config_intr = bcm_phy_config_intr,
1233 .handle_interrupt = bcm_phy_handle_interrupt,
1234 .link_change_notify = bcm54xx_link_change_notify,
1235 .led_brightness_set = bcm_phy_led_brightness_set,
1236}, {
1237 .phy_id = PHY_ID_BCM50610,
1238 .phy_id_mask = 0xfffffff0,
1239 .name = "Broadcom BCM50610",
1240 /* PHY_GBIT_FEATURES */
1241 .get_sset_count = bcm_phy_get_sset_count,
1242 .get_strings = bcm_phy_get_strings,
1243 .get_stats = bcm54xx_get_stats,
1244 .probe = bcm54xx_phy_probe,
1245 .config_init = bcm54xx_config_init,
1246 .config_intr = bcm_phy_config_intr,
1247 .handle_interrupt = bcm_phy_handle_interrupt,
1248 .link_change_notify = bcm54xx_link_change_notify,
1249 .suspend = bcm54xx_suspend,
1250 .resume = bcm54xx_resume,
1251 .led_brightness_set = bcm_phy_led_brightness_set,
1252}, {
1253 .phy_id = PHY_ID_BCM50610M,
1254 .phy_id_mask = 0xfffffff0,
1255 .name = "Broadcom BCM50610M",
1256 /* PHY_GBIT_FEATURES */
1257 .get_sset_count = bcm_phy_get_sset_count,
1258 .get_strings = bcm_phy_get_strings,
1259 .get_stats = bcm54xx_get_stats,
1260 .probe = bcm54xx_phy_probe,
1261 .config_init = bcm54xx_config_init,
1262 .config_intr = bcm_phy_config_intr,
1263 .handle_interrupt = bcm_phy_handle_interrupt,
1264 .link_change_notify = bcm54xx_link_change_notify,
1265 .suspend = bcm54xx_suspend,
1266 .resume = bcm54xx_resume,
1267 .led_brightness_set = bcm_phy_led_brightness_set,
1268}, {
1269 .phy_id = PHY_ID_BCM57780,
1270 .phy_id_mask = 0xfffffff0,
1271 .name = "Broadcom BCM57780",
1272 /* PHY_GBIT_FEATURES */
1273 .get_sset_count = bcm_phy_get_sset_count,
1274 .get_strings = bcm_phy_get_strings,
1275 .get_stats = bcm54xx_get_stats,
1276 .probe = bcm54xx_phy_probe,
1277 .config_init = bcm54xx_config_init,
1278 .config_intr = bcm_phy_config_intr,
1279 .handle_interrupt = bcm_phy_handle_interrupt,
1280 .link_change_notify = bcm54xx_link_change_notify,
1281 .led_brightness_set = bcm_phy_led_brightness_set,
1282}, {
1283 .phy_id = PHY_ID_BCMAC131,
1284 .phy_id_mask = 0xfffffff0,
1285 .name = "Broadcom BCMAC131",
1286 /* PHY_BASIC_FEATURES */
1287 .config_init = brcm_fet_config_init,
1288 .config_intr = brcm_fet_config_intr,
1289 .handle_interrupt = brcm_fet_handle_interrupt,
1290 .suspend = brcm_fet_suspend,
1291 .resume = brcm_fet_config_init,
1292}, {
1293 .phy_id = PHY_ID_BCM5241,
1294 .phy_id_mask = 0xfffffff0,
1295 .name = "Broadcom BCM5241",
1296 /* PHY_BASIC_FEATURES */
1297 .config_init = brcm_fet_config_init,
1298 .config_intr = brcm_fet_config_intr,
1299 .handle_interrupt = brcm_fet_handle_interrupt,
1300 .suspend = brcm_fet_suspend,
1301 .resume = brcm_fet_config_init,
1302}, {
1303 .phy_id = PHY_ID_BCM5221,
1304 .phy_id_mask = 0xfffffff0,
1305 .name = "Broadcom BCM5221",
1306 /* PHY_BASIC_FEATURES */
1307 .config_init = brcm_fet_config_init,
1308 .config_intr = brcm_fet_config_intr,
1309 .handle_interrupt = brcm_fet_handle_interrupt,
1310 .suspend = brcm_fet_suspend,
1311 .resume = brcm_fet_config_init,
1312 .config_aneg = bcm5221_config_aneg,
1313 .read_status = bcm5221_read_status,
1314}, {
1315 .phy_id = PHY_ID_BCM5395,
1316 .phy_id_mask = 0xfffffff0,
1317 .name = "Broadcom BCM5395",
1318 .flags = PHY_IS_INTERNAL,
1319 /* PHY_GBIT_FEATURES */
1320 .get_sset_count = bcm_phy_get_sset_count,
1321 .get_strings = bcm_phy_get_strings,
1322 .get_stats = bcm54xx_get_stats,
1323 .probe = bcm54xx_phy_probe,
1324 .link_change_notify = bcm54xx_link_change_notify,
1325 .led_brightness_set = bcm_phy_led_brightness_set,
1326}, {
1327 .phy_id = PHY_ID_BCM53125,
1328 .phy_id_mask = 0xfffffff0,
1329 .name = "Broadcom BCM53125",
1330 .flags = PHY_IS_INTERNAL,
1331 /* PHY_GBIT_FEATURES */
1332 .get_sset_count = bcm_phy_get_sset_count,
1333 .get_strings = bcm_phy_get_strings,
1334 .get_stats = bcm54xx_get_stats,
1335 .probe = bcm54xx_phy_probe,
1336 .config_init = bcm54xx_config_init,
1337 .config_intr = bcm_phy_config_intr,
1338 .handle_interrupt = bcm_phy_handle_interrupt,
1339 .link_change_notify = bcm54xx_link_change_notify,
1340 .led_brightness_set = bcm_phy_led_brightness_set,
1341}, {
1342 .phy_id = PHY_ID_BCM53128,
1343 .phy_id_mask = 0xfffffff0,
1344 .name = "Broadcom BCM53128",
1345 .flags = PHY_IS_INTERNAL,
1346 /* PHY_GBIT_FEATURES */
1347 .get_sset_count = bcm_phy_get_sset_count,
1348 .get_strings = bcm_phy_get_strings,
1349 .get_stats = bcm54xx_get_stats,
1350 .probe = bcm54xx_phy_probe,
1351 .config_init = bcm54xx_config_init,
1352 .config_intr = bcm_phy_config_intr,
1353 .handle_interrupt = bcm_phy_handle_interrupt,
1354 .link_change_notify = bcm54xx_link_change_notify,
1355 .led_brightness_set = bcm_phy_led_brightness_set,
1356}, {
1357 .phy_id = PHY_ID_BCM89610,
1358 .phy_id_mask = 0xfffffff0,
1359 .name = "Broadcom BCM89610",
1360 /* PHY_GBIT_FEATURES */
1361 .get_sset_count = bcm_phy_get_sset_count,
1362 .get_strings = bcm_phy_get_strings,
1363 .get_stats = bcm54xx_get_stats,
1364 .probe = bcm54xx_phy_probe,
1365 .config_init = bcm54xx_config_init,
1366 .config_intr = bcm_phy_config_intr,
1367 .handle_interrupt = bcm_phy_handle_interrupt,
1368 .link_change_notify = bcm54xx_link_change_notify,
1369} };
1370
1371module_phy_driver(broadcom_drivers);
1372
1373static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
1374 { PHY_ID_BCM5411, 0xfffffff0 },
1375 { PHY_ID_BCM5421, 0xfffffff0 },
1376 { PHY_ID_BCM54210E, 0xfffffff0 },
1377 { PHY_ID_BCM5461, 0xfffffff0 },
1378 { PHY_ID_BCM54612E, 0xfffffff0 },
1379 { PHY_ID_BCM54616S, 0xfffffff0 },
1380 { PHY_ID_BCM5464, 0xfffffff0 },
1381 { PHY_ID_BCM5481, 0xfffffff0 },
1382 { PHY_ID_BCM54810, 0xfffffff0 },
1383 { PHY_ID_BCM54811, 0xfffffff0 },
1384 { PHY_ID_BCM5482, 0xfffffff0 },
1385 { PHY_ID_BCM50610, 0xfffffff0 },
1386 { PHY_ID_BCM50610M, 0xfffffff0 },
1387 { PHY_ID_BCM57780, 0xfffffff0 },
1388 { PHY_ID_BCMAC131, 0xfffffff0 },
1389 { PHY_ID_BCM5221, 0xfffffff0 },
1390 { PHY_ID_BCM5241, 0xfffffff0 },
1391 { PHY_ID_BCM5395, 0xfffffff0 },
1392 { PHY_ID_BCM53125, 0xfffffff0 },
1393 { PHY_ID_BCM53128, 0xfffffff0 },
1394 { PHY_ID_BCM89610, 0xfffffff0 },
1395 { }
1396};
1397
1398MODULE_DEVICE_TABLE(mdio, broadcom_tbl);