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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Fast Ethernet Controller (ENET) PTP driver for MX6x.
4 *
5 * Copyright (C) 2012 Freescale Semiconductor, Inc.
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/string.h>
13#include <linux/ptrace.h>
14#include <linux/errno.h>
15#include <linux/ioport.h>
16#include <linux/slab.h>
17#include <linux/interrupt.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/netdevice.h>
21#include <linux/etherdevice.h>
22#include <linux/skbuff.h>
23#include <linux/spinlock.h>
24#include <linux/workqueue.h>
25#include <linux/bitops.h>
26#include <linux/io.h>
27#include <linux/irq.h>
28#include <linux/clk.h>
29#include <linux/platform_device.h>
30#include <linux/phy.h>
31#include <linux/fec.h>
32#include <linux/of.h>
33#include <linux/of_gpio.h>
34#include <linux/of_net.h>
35
36#include "fec.h"
37
38/* FEC 1588 register bits */
39#define FEC_T_CTRL_SLAVE 0x00002000
40#define FEC_T_CTRL_CAPTURE 0x00000800
41#define FEC_T_CTRL_RESTART 0x00000200
42#define FEC_T_CTRL_PERIOD_RST 0x00000030
43#define FEC_T_CTRL_PERIOD_EN 0x00000010
44#define FEC_T_CTRL_ENABLE 0x00000001
45
46#define FEC_T_INC_MASK 0x0000007f
47#define FEC_T_INC_OFFSET 0
48#define FEC_T_INC_CORR_MASK 0x00007f00
49#define FEC_T_INC_CORR_OFFSET 8
50
51#define FEC_T_CTRL_PINPER 0x00000080
52#define FEC_T_TF0_MASK 0x00000001
53#define FEC_T_TF0_OFFSET 0
54#define FEC_T_TF1_MASK 0x00000002
55#define FEC_T_TF1_OFFSET 1
56#define FEC_T_TF2_MASK 0x00000004
57#define FEC_T_TF2_OFFSET 2
58#define FEC_T_TF3_MASK 0x00000008
59#define FEC_T_TF3_OFFSET 3
60#define FEC_T_TDRE_MASK 0x00000001
61#define FEC_T_TDRE_OFFSET 0
62#define FEC_T_TMODE_MASK 0x0000003C
63#define FEC_T_TMODE_OFFSET 2
64#define FEC_T_TIE_MASK 0x00000040
65#define FEC_T_TIE_OFFSET 6
66#define FEC_T_TF_MASK 0x00000080
67#define FEC_T_TF_OFFSET 7
68
69#define FEC_ATIME_CTRL 0x400
70#define FEC_ATIME 0x404
71#define FEC_ATIME_EVT_OFFSET 0x408
72#define FEC_ATIME_EVT_PERIOD 0x40c
73#define FEC_ATIME_CORR 0x410
74#define FEC_ATIME_INC 0x414
75#define FEC_TS_TIMESTAMP 0x418
76
77#define FEC_TGSR 0x604
78#define FEC_TCSR(n) (0x608 + n * 0x08)
79#define FEC_TCCR(n) (0x60C + n * 0x08)
80#define MAX_TIMER_CHANNEL 3
81#define FEC_TMODE_TOGGLE 0x05
82#define FEC_HIGH_PULSE 0x0F
83
84#define FEC_CC_MULT (1 << 31)
85#define FEC_COUNTER_PERIOD (1 << 31)
86#define PPS_OUPUT_RELOAD_PERIOD NSEC_PER_SEC
87#define FEC_CHANNLE_0 0
88#define DEFAULT_PPS_CHANNEL FEC_CHANNLE_0
89
90#define FEC_PTP_MAX_NSEC_PERIOD 4000000000ULL
91#define FEC_PTP_MAX_NSEC_COUNTER 0x80000000ULL
92
93/**
94 * fec_ptp_enable_pps
95 * @fep: the fec_enet_private structure handle
96 * @enable: enable the channel pps output
97 *
98 * This function enble the PPS ouput on the timer channel.
99 */
100static int fec_ptp_enable_pps(struct fec_enet_private *fep, uint enable)
101{
102 unsigned long flags;
103 u32 val, tempval;
104 struct timespec64 ts;
105 u64 ns;
106
107 spin_lock_irqsave(&fep->tmreg_lock, flags);
108
109 if (fep->pps_enable == enable) {
110 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
111 return 0;
112 }
113
114 if (enable) {
115 /* clear capture or output compare interrupt status if have.
116 */
117 writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel));
118
119 /* It is recommended to double check the TMODE field in the
120 * TCSR register to be cleared before the first compare counter
121 * is written into TCCR register. Just add a double check.
122 */
123 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
124 do {
125 val &= ~(FEC_T_TMODE_MASK);
126 writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
127 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
128 } while (val & FEC_T_TMODE_MASK);
129
130 /* Dummy read counter to update the counter */
131 timecounter_read(&fep->tc);
132 /* We want to find the first compare event in the next
133 * second point. So we need to know what the ptp time
134 * is now and how many nanoseconds is ahead to get next second.
135 * The remaining nanosecond ahead before the next second would be
136 * NSEC_PER_SEC - ts.tv_nsec. Add the remaining nanoseconds
137 * to current timer would be next second.
138 */
139 tempval = fep->cc.read(&fep->cc);
140 /* Convert the ptp local counter to 1588 timestamp */
141 ns = timecounter_cyc2time(&fep->tc, tempval);
142 ts = ns_to_timespec64(ns);
143
144 /* The tempval is less than 3 seconds, and so val is less than
145 * 4 seconds. No overflow for 32bit calculation.
146 */
147 val = NSEC_PER_SEC - (u32)ts.tv_nsec + tempval;
148
149 /* Need to consider the situation that the current time is
150 * very close to the second point, which means NSEC_PER_SEC
151 * - ts.tv_nsec is close to be zero(For example 20ns); Since the timer
152 * is still running when we calculate the first compare event, it is
153 * possible that the remaining nanoseonds run out before the compare
154 * counter is calculated and written into TCCR register. To avoid
155 * this possibility, we will set the compare event to be the next
156 * of next second. The current setting is 31-bit timer and wrap
157 * around over 2 seconds. So it is okay to set the next of next
158 * seond for the timer.
159 */
160 val += NSEC_PER_SEC;
161
162 /* We add (2 * NSEC_PER_SEC - (u32)ts.tv_nsec) to current
163 * ptp counter, which maybe cause 32-bit wrap. Since the
164 * (NSEC_PER_SEC - (u32)ts.tv_nsec) is less than 2 second.
165 * We can ensure the wrap will not cause issue. If the offset
166 * is bigger than fep->cc.mask would be a error.
167 */
168 val &= fep->cc.mask;
169 writel(val, fep->hwp + FEC_TCCR(fep->pps_channel));
170
171 /* Calculate the second the compare event timestamp */
172 fep->next_counter = (val + fep->reload_period) & fep->cc.mask;
173
174 /* * Enable compare event when overflow */
175 val = readl(fep->hwp + FEC_ATIME_CTRL);
176 val |= FEC_T_CTRL_PINPER;
177 writel(val, fep->hwp + FEC_ATIME_CTRL);
178
179 /* Compare channel setting. */
180 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
181 val |= (1 << FEC_T_TF_OFFSET | 1 << FEC_T_TIE_OFFSET);
182 val &= ~(1 << FEC_T_TDRE_OFFSET);
183 val &= ~(FEC_T_TMODE_MASK);
184 val |= (FEC_HIGH_PULSE << FEC_T_TMODE_OFFSET);
185 writel(val, fep->hwp + FEC_TCSR(fep->pps_channel));
186
187 /* Write the second compare event timestamp and calculate
188 * the third timestamp. Refer the TCCR register detail in the spec.
189 */
190 writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel));
191 fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask;
192 } else {
193 writel(0, fep->hwp + FEC_TCSR(fep->pps_channel));
194 }
195
196 fep->pps_enable = enable;
197 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
198
199 return 0;
200}
201
202static int fec_ptp_pps_perout(struct fec_enet_private *fep)
203{
204 u32 compare_val, ptp_hc, temp_val;
205 u64 curr_time;
206 unsigned long flags;
207
208 spin_lock_irqsave(&fep->tmreg_lock, flags);
209
210 /* Update time counter */
211 timecounter_read(&fep->tc);
212
213 /* Get the current ptp hardware time counter */
214 temp_val = readl(fep->hwp + FEC_ATIME_CTRL);
215 temp_val |= FEC_T_CTRL_CAPTURE;
216 writel(temp_val, fep->hwp + FEC_ATIME_CTRL);
217 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE)
218 udelay(1);
219
220 ptp_hc = readl(fep->hwp + FEC_ATIME);
221
222 /* Convert the ptp local counter to 1588 timestamp */
223 curr_time = timecounter_cyc2time(&fep->tc, ptp_hc);
224
225 /* If the pps start time less than current time add 100ms, just return.
226 * Because the software might not able to set the comparison time into
227 * the FEC_TCCR register in time and missed the start time.
228 */
229 if (fep->perout_stime < curr_time + 100 * NSEC_PER_MSEC) {
230 dev_err(&fep->pdev->dev, "Current time is too close to the start time!\n");
231 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
232 return -1;
233 }
234
235 compare_val = fep->perout_stime - curr_time + ptp_hc;
236 compare_val &= fep->cc.mask;
237
238 writel(compare_val, fep->hwp + FEC_TCCR(fep->pps_channel));
239 fep->next_counter = (compare_val + fep->reload_period) & fep->cc.mask;
240
241 /* Enable compare event when overflow */
242 temp_val = readl(fep->hwp + FEC_ATIME_CTRL);
243 temp_val |= FEC_T_CTRL_PINPER;
244 writel(temp_val, fep->hwp + FEC_ATIME_CTRL);
245
246 /* Compare channel setting. */
247 temp_val = readl(fep->hwp + FEC_TCSR(fep->pps_channel));
248 temp_val |= (1 << FEC_T_TF_OFFSET | 1 << FEC_T_TIE_OFFSET);
249 temp_val &= ~(1 << FEC_T_TDRE_OFFSET);
250 temp_val &= ~(FEC_T_TMODE_MASK);
251 temp_val |= (FEC_TMODE_TOGGLE << FEC_T_TMODE_OFFSET);
252 writel(temp_val, fep->hwp + FEC_TCSR(fep->pps_channel));
253
254 /* Write the second compare event timestamp and calculate
255 * the third timestamp. Refer the TCCR register detail in the spec.
256 */
257 writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel));
258 fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask;
259 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
260
261 return 0;
262}
263
264static enum hrtimer_restart fec_ptp_pps_perout_handler(struct hrtimer *timer)
265{
266 struct fec_enet_private *fep = container_of(timer,
267 struct fec_enet_private, perout_timer);
268
269 fec_ptp_pps_perout(fep);
270
271 return HRTIMER_NORESTART;
272}
273
274/**
275 * fec_ptp_read - read raw cycle counter (to be used by time counter)
276 * @cc: the cyclecounter structure
277 *
278 * this function reads the cyclecounter registers and is called by the
279 * cyclecounter structure used to construct a ns counter from the
280 * arbitrary fixed point registers
281 */
282static u64 fec_ptp_read(const struct cyclecounter *cc)
283{
284 struct fec_enet_private *fep =
285 container_of(cc, struct fec_enet_private, cc);
286 u32 tempval;
287
288 tempval = readl(fep->hwp + FEC_ATIME_CTRL);
289 tempval |= FEC_T_CTRL_CAPTURE;
290 writel(tempval, fep->hwp + FEC_ATIME_CTRL);
291
292 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE)
293 udelay(1);
294
295 return readl(fep->hwp + FEC_ATIME);
296}
297
298/**
299 * fec_ptp_start_cyclecounter - create the cycle counter from hw
300 * @ndev: network device
301 *
302 * this function initializes the timecounter and cyclecounter
303 * structures for use in generated a ns counter from the arbitrary
304 * fixed point cycles registers in the hardware.
305 */
306void fec_ptp_start_cyclecounter(struct net_device *ndev)
307{
308 struct fec_enet_private *fep = netdev_priv(ndev);
309 unsigned long flags;
310 int inc;
311
312 inc = 1000000000 / fep->cycle_speed;
313
314 /* grab the ptp lock */
315 spin_lock_irqsave(&fep->tmreg_lock, flags);
316
317 /* 1ns counter */
318 writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC);
319
320 /* use 31-bit timer counter */
321 writel(FEC_COUNTER_PERIOD, fep->hwp + FEC_ATIME_EVT_PERIOD);
322
323 writel(FEC_T_CTRL_ENABLE | FEC_T_CTRL_PERIOD_RST,
324 fep->hwp + FEC_ATIME_CTRL);
325
326 memset(&fep->cc, 0, sizeof(fep->cc));
327 fep->cc.read = fec_ptp_read;
328 fep->cc.mask = CLOCKSOURCE_MASK(31);
329 fep->cc.shift = 31;
330 fep->cc.mult = FEC_CC_MULT;
331
332 /* reset the ns time counter */
333 timecounter_init(&fep->tc, &fep->cc, 0);
334
335 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
336}
337
338/**
339 * fec_ptp_adjfine - adjust ptp cycle frequency
340 * @ptp: the ptp clock structure
341 * @scaled_ppm: scaled parts per million adjustment from base
342 *
343 * Adjust the frequency of the ptp cycle counter by the
344 * indicated amount from the base frequency.
345 *
346 * Scaled parts per million is ppm with a 16-bit binary fractional field.
347 *
348 * Because ENET hardware frequency adjust is complex,
349 * using software method to do that.
350 */
351static int fec_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
352{
353 s32 ppb = scaled_ppm_to_ppb(scaled_ppm);
354 unsigned long flags;
355 int neg_adj = 0;
356 u32 i, tmp;
357 u32 corr_inc, corr_period;
358 u32 corr_ns;
359 u64 lhs, rhs;
360
361 struct fec_enet_private *fep =
362 container_of(ptp, struct fec_enet_private, ptp_caps);
363
364 if (ppb == 0)
365 return 0;
366
367 if (ppb < 0) {
368 ppb = -ppb;
369 neg_adj = 1;
370 }
371
372 /* In theory, corr_inc/corr_period = ppb/NSEC_PER_SEC;
373 * Try to find the corr_inc between 1 to fep->ptp_inc to
374 * meet adjustment requirement.
375 */
376 lhs = NSEC_PER_SEC;
377 rhs = (u64)ppb * (u64)fep->ptp_inc;
378 for (i = 1; i <= fep->ptp_inc; i++) {
379 if (lhs >= rhs) {
380 corr_inc = i;
381 corr_period = div_u64(lhs, rhs);
382 break;
383 }
384 lhs += NSEC_PER_SEC;
385 }
386 /* Not found? Set it to high value - double speed
387 * correct in every clock step.
388 */
389 if (i > fep->ptp_inc) {
390 corr_inc = fep->ptp_inc;
391 corr_period = 1;
392 }
393
394 if (neg_adj)
395 corr_ns = fep->ptp_inc - corr_inc;
396 else
397 corr_ns = fep->ptp_inc + corr_inc;
398
399 spin_lock_irqsave(&fep->tmreg_lock, flags);
400
401 tmp = readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK;
402 tmp |= corr_ns << FEC_T_INC_CORR_OFFSET;
403 writel(tmp, fep->hwp + FEC_ATIME_INC);
404 corr_period = corr_period > 1 ? corr_period - 1 : corr_period;
405 writel(corr_period, fep->hwp + FEC_ATIME_CORR);
406 /* dummy read to update the timer. */
407 timecounter_read(&fep->tc);
408
409 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
410
411 return 0;
412}
413
414/**
415 * fec_ptp_adjtime
416 * @ptp: the ptp clock structure
417 * @delta: offset to adjust the cycle counter by
418 *
419 * adjust the timer by resetting the timecounter structure.
420 */
421static int fec_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
422{
423 struct fec_enet_private *fep =
424 container_of(ptp, struct fec_enet_private, ptp_caps);
425 unsigned long flags;
426
427 spin_lock_irqsave(&fep->tmreg_lock, flags);
428 timecounter_adjtime(&fep->tc, delta);
429 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
430
431 return 0;
432}
433
434/**
435 * fec_ptp_gettime
436 * @ptp: the ptp clock structure
437 * @ts: timespec structure to hold the current time value
438 *
439 * read the timecounter and return the correct value on ns,
440 * after converting it into a struct timespec.
441 */
442static int fec_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
443{
444 struct fec_enet_private *fep =
445 container_of(ptp, struct fec_enet_private, ptp_caps);
446 u64 ns;
447 unsigned long flags;
448
449 mutex_lock(&fep->ptp_clk_mutex);
450 /* Check the ptp clock */
451 if (!fep->ptp_clk_on) {
452 mutex_unlock(&fep->ptp_clk_mutex);
453 return -EINVAL;
454 }
455 spin_lock_irqsave(&fep->tmreg_lock, flags);
456 ns = timecounter_read(&fep->tc);
457 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
458 mutex_unlock(&fep->ptp_clk_mutex);
459
460 *ts = ns_to_timespec64(ns);
461
462 return 0;
463}
464
465/**
466 * fec_ptp_settime
467 * @ptp: the ptp clock structure
468 * @ts: the timespec containing the new time for the cycle counter
469 *
470 * reset the timecounter to use a new base value instead of the kernel
471 * wall timer value.
472 */
473static int fec_ptp_settime(struct ptp_clock_info *ptp,
474 const struct timespec64 *ts)
475{
476 struct fec_enet_private *fep =
477 container_of(ptp, struct fec_enet_private, ptp_caps);
478
479 u64 ns;
480 unsigned long flags;
481 u32 counter;
482
483 mutex_lock(&fep->ptp_clk_mutex);
484 /* Check the ptp clock */
485 if (!fep->ptp_clk_on) {
486 mutex_unlock(&fep->ptp_clk_mutex);
487 return -EINVAL;
488 }
489
490 ns = timespec64_to_ns(ts);
491 /* Get the timer value based on timestamp.
492 * Update the counter with the masked value.
493 */
494 counter = ns & fep->cc.mask;
495
496 spin_lock_irqsave(&fep->tmreg_lock, flags);
497 writel(counter, fep->hwp + FEC_ATIME);
498 timecounter_init(&fep->tc, &fep->cc, ns);
499 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
500 mutex_unlock(&fep->ptp_clk_mutex);
501 return 0;
502}
503
504static int fec_ptp_pps_disable(struct fec_enet_private *fep, uint channel)
505{
506 unsigned long flags;
507
508 spin_lock_irqsave(&fep->tmreg_lock, flags);
509 writel(0, fep->hwp + FEC_TCSR(channel));
510 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
511
512 return 0;
513}
514
515/**
516 * fec_ptp_enable
517 * @ptp: the ptp clock structure
518 * @rq: the requested feature to change
519 * @on: whether to enable or disable the feature
520 *
521 */
522static int fec_ptp_enable(struct ptp_clock_info *ptp,
523 struct ptp_clock_request *rq, int on)
524{
525 struct fec_enet_private *fep =
526 container_of(ptp, struct fec_enet_private, ptp_caps);
527 ktime_t timeout;
528 struct timespec64 start_time, period;
529 u64 curr_time, delta, period_ns;
530 unsigned long flags;
531 int ret = 0;
532
533 if (rq->type == PTP_CLK_REQ_PPS) {
534 fep->pps_channel = DEFAULT_PPS_CHANNEL;
535 fep->reload_period = PPS_OUPUT_RELOAD_PERIOD;
536
537 ret = fec_ptp_enable_pps(fep, on);
538
539 return ret;
540 } else if (rq->type == PTP_CLK_REQ_PEROUT) {
541 /* Reject requests with unsupported flags */
542 if (rq->perout.flags)
543 return -EOPNOTSUPP;
544
545 if (rq->perout.index != DEFAULT_PPS_CHANNEL)
546 return -EOPNOTSUPP;
547
548 fep->pps_channel = DEFAULT_PPS_CHANNEL;
549 period.tv_sec = rq->perout.period.sec;
550 period.tv_nsec = rq->perout.period.nsec;
551 period_ns = timespec64_to_ns(&period);
552
553 /* FEC PTP timer only has 31 bits, so if the period exceed
554 * 4s is not supported.
555 */
556 if (period_ns > FEC_PTP_MAX_NSEC_PERIOD) {
557 dev_err(&fep->pdev->dev, "The period must equal to or less than 4s!\n");
558 return -EOPNOTSUPP;
559 }
560
561 fep->reload_period = div_u64(period_ns, 2);
562 if (on && fep->reload_period) {
563 /* Convert 1588 timestamp to ns*/
564 start_time.tv_sec = rq->perout.start.sec;
565 start_time.tv_nsec = rq->perout.start.nsec;
566 fep->perout_stime = timespec64_to_ns(&start_time);
567
568 mutex_lock(&fep->ptp_clk_mutex);
569 if (!fep->ptp_clk_on) {
570 dev_err(&fep->pdev->dev, "Error: PTP clock is closed!\n");
571 mutex_unlock(&fep->ptp_clk_mutex);
572 return -EOPNOTSUPP;
573 }
574 spin_lock_irqsave(&fep->tmreg_lock, flags);
575 /* Read current timestamp */
576 curr_time = timecounter_read(&fep->tc);
577 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
578 mutex_unlock(&fep->ptp_clk_mutex);
579
580 /* Calculate time difference */
581 delta = fep->perout_stime - curr_time;
582
583 if (fep->perout_stime <= curr_time) {
584 dev_err(&fep->pdev->dev, "Start time must larger than current time!\n");
585 return -EINVAL;
586 }
587
588 /* Because the timer counter of FEC only has 31-bits, correspondingly,
589 * the time comparison register FEC_TCCR also only low 31 bits can be
590 * set. If the start time of pps signal exceeds current time more than
591 * 0x80000000 ns, a software timer is used and the timer expires about
592 * 1 second before the start time to be able to set FEC_TCCR.
593 */
594 if (delta > FEC_PTP_MAX_NSEC_COUNTER) {
595 timeout = ns_to_ktime(delta - NSEC_PER_SEC);
596 hrtimer_start(&fep->perout_timer, timeout, HRTIMER_MODE_REL);
597 } else {
598 return fec_ptp_pps_perout(fep);
599 }
600 } else {
601 fec_ptp_pps_disable(fep, fep->pps_channel);
602 }
603
604 return 0;
605 } else {
606 return -EOPNOTSUPP;
607 }
608}
609
610int fec_ptp_set(struct net_device *ndev, struct kernel_hwtstamp_config *config,
611 struct netlink_ext_ack *extack)
612{
613 struct fec_enet_private *fep = netdev_priv(ndev);
614
615 switch (config->tx_type) {
616 case HWTSTAMP_TX_OFF:
617 fep->hwts_tx_en = 0;
618 break;
619 case HWTSTAMP_TX_ON:
620 fep->hwts_tx_en = 1;
621 break;
622 default:
623 return -ERANGE;
624 }
625
626 switch (config->rx_filter) {
627 case HWTSTAMP_FILTER_NONE:
628 fep->hwts_rx_en = 0;
629 break;
630
631 default:
632 fep->hwts_rx_en = 1;
633 config->rx_filter = HWTSTAMP_FILTER_ALL;
634 break;
635 }
636
637 return 0;
638}
639
640void fec_ptp_get(struct net_device *ndev, struct kernel_hwtstamp_config *config)
641{
642 struct fec_enet_private *fep = netdev_priv(ndev);
643
644 config->flags = 0;
645 config->tx_type = fep->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
646 config->rx_filter = (fep->hwts_rx_en ?
647 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
648}
649
650/*
651 * fec_time_keep - call timecounter_read every second to avoid timer overrun
652 * because ENET just support 32bit counter, will timeout in 4s
653 */
654static void fec_time_keep(struct work_struct *work)
655{
656 struct delayed_work *dwork = to_delayed_work(work);
657 struct fec_enet_private *fep = container_of(dwork, struct fec_enet_private, time_keep);
658 unsigned long flags;
659
660 mutex_lock(&fep->ptp_clk_mutex);
661 if (fep->ptp_clk_on) {
662 spin_lock_irqsave(&fep->tmreg_lock, flags);
663 timecounter_read(&fep->tc);
664 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
665 }
666 mutex_unlock(&fep->ptp_clk_mutex);
667
668 schedule_delayed_work(&fep->time_keep, HZ);
669}
670
671/* This function checks the pps event and reloads the timer compare counter. */
672static irqreturn_t fec_pps_interrupt(int irq, void *dev_id)
673{
674 struct net_device *ndev = dev_id;
675 struct fec_enet_private *fep = netdev_priv(ndev);
676 u32 val;
677 u8 channel = fep->pps_channel;
678 struct ptp_clock_event event;
679
680 val = readl(fep->hwp + FEC_TCSR(channel));
681 if (val & FEC_T_TF_MASK) {
682 /* Write the next next compare(not the next according the spec)
683 * value to the register
684 */
685 writel(fep->next_counter, fep->hwp + FEC_TCCR(channel));
686 do {
687 writel(val, fep->hwp + FEC_TCSR(channel));
688 } while (readl(fep->hwp + FEC_TCSR(channel)) & FEC_T_TF_MASK);
689
690 /* Update the counter; */
691 fep->next_counter = (fep->next_counter + fep->reload_period) &
692 fep->cc.mask;
693
694 event.type = PTP_CLOCK_PPS;
695 ptp_clock_event(fep->ptp_clock, &event);
696 return IRQ_HANDLED;
697 }
698
699 return IRQ_NONE;
700}
701
702/**
703 * fec_ptp_init
704 * @pdev: The FEC network adapter
705 * @irq_idx: the interrupt index
706 *
707 * This function performs the required steps for enabling ptp
708 * support. If ptp support has already been loaded it simply calls the
709 * cyclecounter init routine and exits.
710 */
711
712void fec_ptp_init(struct platform_device *pdev, int irq_idx)
713{
714 struct net_device *ndev = platform_get_drvdata(pdev);
715 struct fec_enet_private *fep = netdev_priv(ndev);
716 int irq;
717 int ret;
718
719 fep->ptp_caps.owner = THIS_MODULE;
720 strscpy(fep->ptp_caps.name, "fec ptp", sizeof(fep->ptp_caps.name));
721
722 fep->ptp_caps.max_adj = 250000000;
723 fep->ptp_caps.n_alarm = 0;
724 fep->ptp_caps.n_ext_ts = 0;
725 fep->ptp_caps.n_per_out = 1;
726 fep->ptp_caps.n_pins = 0;
727 fep->ptp_caps.pps = 1;
728 fep->ptp_caps.adjfine = fec_ptp_adjfine;
729 fep->ptp_caps.adjtime = fec_ptp_adjtime;
730 fep->ptp_caps.gettime64 = fec_ptp_gettime;
731 fep->ptp_caps.settime64 = fec_ptp_settime;
732 fep->ptp_caps.enable = fec_ptp_enable;
733
734 fep->cycle_speed = clk_get_rate(fep->clk_ptp);
735 if (!fep->cycle_speed) {
736 fep->cycle_speed = NSEC_PER_SEC;
737 dev_err(&fep->pdev->dev, "clk_ptp clock rate is zero\n");
738 }
739 fep->ptp_inc = NSEC_PER_SEC / fep->cycle_speed;
740
741 spin_lock_init(&fep->tmreg_lock);
742
743 fec_ptp_start_cyclecounter(ndev);
744
745 INIT_DELAYED_WORK(&fep->time_keep, fec_time_keep);
746
747 hrtimer_init(&fep->perout_timer, CLOCK_REALTIME, HRTIMER_MODE_REL);
748 fep->perout_timer.function = fec_ptp_pps_perout_handler;
749
750 irq = platform_get_irq_byname_optional(pdev, "pps");
751 if (irq < 0)
752 irq = platform_get_irq_optional(pdev, irq_idx);
753 /* Failure to get an irq is not fatal,
754 * only the PTP_CLOCK_PPS clock events should stop
755 */
756 if (irq >= 0) {
757 ret = devm_request_irq(&pdev->dev, irq, fec_pps_interrupt,
758 0, pdev->name, ndev);
759 if (ret < 0)
760 dev_warn(&pdev->dev, "request for pps irq failed(%d)\n",
761 ret);
762 }
763
764 fep->ptp_clock = ptp_clock_register(&fep->ptp_caps, &pdev->dev);
765 if (IS_ERR(fep->ptp_clock)) {
766 fep->ptp_clock = NULL;
767 dev_err(&pdev->dev, "ptp_clock_register failed\n");
768 }
769
770 schedule_delayed_work(&fep->time_keep, HZ);
771}
772
773void fec_ptp_stop(struct platform_device *pdev)
774{
775 struct net_device *ndev = platform_get_drvdata(pdev);
776 struct fec_enet_private *fep = netdev_priv(ndev);
777
778 cancel_delayed_work_sync(&fep->time_keep);
779 hrtimer_cancel(&fep->perout_timer);
780 if (fep->ptp_clock)
781 ptp_clock_unregister(fep->ptp_clock);
782}