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1/*
2 * linux/drivers/message/fusion/mptbase.c
3 * This is the Fusion MPT base driver which supports multiple
4 * (SCSI + LAN) specialized protocol drivers.
5 * For use with LSI PCI chip/adapter(s)
6 * running LSI Fusion MPT (Message Passing Technology) firmware.
7 *
8 * Copyright (c) 1999-2008 LSI Corporation
9 * (mailto:DL-MPTFusionLinux@lsi.com)
10 *
11 */
12/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
13/*
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; version 2 of the License.
17
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 NO WARRANTY
24 THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
25 CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
26 LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
27 MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
28 solely responsible for determining the appropriateness of using and
29 distributing the Program and assumes all risks associated with its
30 exercise of rights under this Agreement, including but not limited to
31 the risks and costs of program errors, damage to or loss of data,
32 programs or equipment, and unavailability or interruption of operations.
33
34 DISCLAIMER OF LIABILITY
35 NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
36 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
38 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
39 TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
40 USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
41 HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
42
43 You should have received a copy of the GNU General Public License
44 along with this program; if not, write to the Free Software
45 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
46*/
47/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
48
49#include <linux/kernel.h>
50#include <linux/module.h>
51#include <linux/errno.h>
52#include <linux/init.h>
53#include <linux/seq_file.h>
54#include <linux/slab.h>
55#include <linux/types.h>
56#include <linux/pci.h>
57#include <linux/kdev_t.h>
58#include <linux/blkdev.h>
59#include <linux/delay.h>
60#include <linux/interrupt.h> /* needed for in_interrupt() proto */
61#include <linux/dma-mapping.h>
62#include <asm/io.h>
63#ifdef CONFIG_MTRR
64#include <asm/mtrr.h>
65#endif
66
67#include "mptbase.h"
68#include "lsi/mpi_log_fc.h"
69
70/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
71#define my_NAME "Fusion MPT base driver"
72#define my_VERSION MPT_LINUX_VERSION_COMMON
73#define MYNAM "mptbase"
74
75MODULE_AUTHOR(MODULEAUTHOR);
76MODULE_DESCRIPTION(my_NAME);
77MODULE_LICENSE("GPL");
78MODULE_VERSION(my_VERSION);
79
80/*
81 * cmd line parameters
82 */
83
84static int mpt_msi_enable_spi;
85module_param(mpt_msi_enable_spi, int, 0);
86MODULE_PARM_DESC(mpt_msi_enable_spi,
87 " Enable MSI Support for SPI controllers (default=0)");
88
89static int mpt_msi_enable_fc;
90module_param(mpt_msi_enable_fc, int, 0);
91MODULE_PARM_DESC(mpt_msi_enable_fc,
92 " Enable MSI Support for FC controllers (default=0)");
93
94static int mpt_msi_enable_sas;
95module_param(mpt_msi_enable_sas, int, 0);
96MODULE_PARM_DESC(mpt_msi_enable_sas,
97 " Enable MSI Support for SAS controllers (default=0)");
98
99static int mpt_channel_mapping;
100module_param(mpt_channel_mapping, int, 0);
101MODULE_PARM_DESC(mpt_channel_mapping, " Mapping id's to channels (default=0)");
102
103static int mpt_debug_level;
104static int mpt_set_debug_level(const char *val, struct kernel_param *kp);
105module_param_call(mpt_debug_level, mpt_set_debug_level, param_get_int,
106 &mpt_debug_level, 0600);
107MODULE_PARM_DESC(mpt_debug_level,
108 " debug level - refer to mptdebug.h - (default=0)");
109
110int mpt_fwfault_debug;
111EXPORT_SYMBOL(mpt_fwfault_debug);
112module_param(mpt_fwfault_debug, int, 0600);
113MODULE_PARM_DESC(mpt_fwfault_debug,
114 "Enable detection of Firmware fault and halt Firmware on fault - (default=0)");
115
116static char MptCallbacksName[MPT_MAX_PROTOCOL_DRIVERS][50];
117
118#ifdef MFCNT
119static int mfcounter = 0;
120#define PRINT_MF_COUNT 20000
121#endif
122
123/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
124/*
125 * Public data...
126 */
127
128#define WHOINIT_UNKNOWN 0xAA
129
130/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
131/*
132 * Private data...
133 */
134 /* Adapter link list */
135LIST_HEAD(ioc_list);
136 /* Callback lookup table */
137static MPT_CALLBACK MptCallbacks[MPT_MAX_PROTOCOL_DRIVERS];
138 /* Protocol driver class lookup table */
139static int MptDriverClass[MPT_MAX_PROTOCOL_DRIVERS];
140 /* Event handler lookup table */
141static MPT_EVHANDLER MptEvHandlers[MPT_MAX_PROTOCOL_DRIVERS];
142 /* Reset handler lookup table */
143static MPT_RESETHANDLER MptResetHandlers[MPT_MAX_PROTOCOL_DRIVERS];
144static struct mpt_pci_driver *MptDeviceDriverHandlers[MPT_MAX_PROTOCOL_DRIVERS];
145
146#ifdef CONFIG_PROC_FS
147static struct proc_dir_entry *mpt_proc_root_dir;
148#endif
149
150/*
151 * Driver Callback Index's
152 */
153static u8 mpt_base_index = MPT_MAX_PROTOCOL_DRIVERS;
154static u8 last_drv_idx;
155
156/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
157/*
158 * Forward protos...
159 */
160static irqreturn_t mpt_interrupt(int irq, void *bus_id);
161static int mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req,
162 MPT_FRAME_HDR *reply);
163static int mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes,
164 u32 *req, int replyBytes, u16 *u16reply, int maxwait,
165 int sleepFlag);
166static int mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag);
167static void mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev);
168static void mpt_adapter_disable(MPT_ADAPTER *ioc);
169static void mpt_adapter_dispose(MPT_ADAPTER *ioc);
170
171static void MptDisplayIocCapabilities(MPT_ADAPTER *ioc);
172static int MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag);
173static int GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason);
174static int GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag);
175static int SendIocInit(MPT_ADAPTER *ioc, int sleepFlag);
176static int SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag);
177static int mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag);
178static int mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag);
179static int mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag);
180static int KickStart(MPT_ADAPTER *ioc, int ignore, int sleepFlag);
181static int SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag);
182static int PrimeIocFifos(MPT_ADAPTER *ioc);
183static int WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
184static int WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
185static int WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
186static int GetLanConfigPages(MPT_ADAPTER *ioc);
187static int GetIoUnitPage2(MPT_ADAPTER *ioc);
188int mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode);
189static int mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum);
190static int mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum);
191static void mpt_read_ioc_pg_1(MPT_ADAPTER *ioc);
192static void mpt_read_ioc_pg_4(MPT_ADAPTER *ioc);
193static void mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc);
194static int SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch,
195 int sleepFlag);
196static int SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp);
197static int mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag);
198static int mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init);
199
200#ifdef CONFIG_PROC_FS
201static const struct file_operations mpt_summary_proc_fops;
202static const struct file_operations mpt_version_proc_fops;
203static const struct file_operations mpt_iocinfo_proc_fops;
204#endif
205static void mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc);
206
207static int ProcessEventNotification(MPT_ADAPTER *ioc,
208 EventNotificationReply_t *evReply, int *evHandlers);
209static void mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf);
210static void mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info);
211static void mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info);
212static void mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info , u8 cb_idx);
213static int mpt_read_ioc_pg_3(MPT_ADAPTER *ioc);
214static void mpt_inactive_raid_list_free(MPT_ADAPTER *ioc);
215
216/* module entry point */
217static int __init fusion_init (void);
218static void __exit fusion_exit (void);
219
220#define CHIPREG_READ32(addr) readl_relaxed(addr)
221#define CHIPREG_READ32_dmasync(addr) readl(addr)
222#define CHIPREG_WRITE32(addr,val) writel(val, addr)
223#define CHIPREG_PIO_WRITE32(addr,val) outl(val, (unsigned long)addr)
224#define CHIPREG_PIO_READ32(addr) inl((unsigned long)addr)
225
226static void
227pci_disable_io_access(struct pci_dev *pdev)
228{
229 u16 command_reg;
230
231 pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
232 command_reg &= ~1;
233 pci_write_config_word(pdev, PCI_COMMAND, command_reg);
234}
235
236static void
237pci_enable_io_access(struct pci_dev *pdev)
238{
239 u16 command_reg;
240
241 pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
242 command_reg |= 1;
243 pci_write_config_word(pdev, PCI_COMMAND, command_reg);
244}
245
246static int mpt_set_debug_level(const char *val, struct kernel_param *kp)
247{
248 int ret = param_set_int(val, kp);
249 MPT_ADAPTER *ioc;
250
251 if (ret)
252 return ret;
253
254 list_for_each_entry(ioc, &ioc_list, list)
255 ioc->debug_level = mpt_debug_level;
256 return 0;
257}
258
259/**
260 * mpt_get_cb_idx - obtain cb_idx for registered driver
261 * @dclass: class driver enum
262 *
263 * Returns cb_idx, or zero means it wasn't found
264 **/
265static u8
266mpt_get_cb_idx(MPT_DRIVER_CLASS dclass)
267{
268 u8 cb_idx;
269
270 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--)
271 if (MptDriverClass[cb_idx] == dclass)
272 return cb_idx;
273 return 0;
274}
275
276/**
277 * mpt_is_discovery_complete - determine if discovery has completed
278 * @ioc: per adatper instance
279 *
280 * Returns 1 when discovery completed, else zero.
281 */
282static int
283mpt_is_discovery_complete(MPT_ADAPTER *ioc)
284{
285 ConfigExtendedPageHeader_t hdr;
286 CONFIGPARMS cfg;
287 SasIOUnitPage0_t *buffer;
288 dma_addr_t dma_handle;
289 int rc = 0;
290
291 memset(&hdr, 0, sizeof(ConfigExtendedPageHeader_t));
292 memset(&cfg, 0, sizeof(CONFIGPARMS));
293 hdr.PageVersion = MPI_SASIOUNITPAGE0_PAGEVERSION;
294 hdr.PageType = MPI_CONFIG_PAGETYPE_EXTENDED;
295 hdr.ExtPageType = MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT;
296 cfg.cfghdr.ehdr = &hdr;
297 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
298
299 if ((mpt_config(ioc, &cfg)))
300 goto out;
301 if (!hdr.ExtPageLength)
302 goto out;
303
304 buffer = pci_alloc_consistent(ioc->pcidev, hdr.ExtPageLength * 4,
305 &dma_handle);
306 if (!buffer)
307 goto out;
308
309 cfg.physAddr = dma_handle;
310 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
311
312 if ((mpt_config(ioc, &cfg)))
313 goto out_free_consistent;
314
315 if (!(buffer->PhyData[0].PortFlags &
316 MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS))
317 rc = 1;
318
319 out_free_consistent:
320 pci_free_consistent(ioc->pcidev, hdr.ExtPageLength * 4,
321 buffer, dma_handle);
322 out:
323 return rc;
324}
325
326/**
327 * mpt_fault_reset_work - work performed on workq after ioc fault
328 * @work: input argument, used to derive ioc
329 *
330**/
331static void
332mpt_fault_reset_work(struct work_struct *work)
333{
334 MPT_ADAPTER *ioc =
335 container_of(work, MPT_ADAPTER, fault_reset_work.work);
336 u32 ioc_raw_state;
337 int rc;
338 unsigned long flags;
339
340 if (ioc->ioc_reset_in_progress || !ioc->active)
341 goto out;
342
343 ioc_raw_state = mpt_GetIocState(ioc, 0);
344 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
345 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state (%04xh)!!!\n",
346 ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK);
347 printk(MYIOC_s_WARN_FMT "Issuing HardReset from %s!!\n",
348 ioc->name, __func__);
349 rc = mpt_HardResetHandler(ioc, CAN_SLEEP);
350 printk(MYIOC_s_WARN_FMT "%s: HardReset: %s\n", ioc->name,
351 __func__, (rc == 0) ? "success" : "failed");
352 ioc_raw_state = mpt_GetIocState(ioc, 0);
353 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT)
354 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state after "
355 "reset (%04xh)\n", ioc->name, ioc_raw_state &
356 MPI_DOORBELL_DATA_MASK);
357 } else if (ioc->bus_type == SAS && ioc->sas_discovery_quiesce_io) {
358 if ((mpt_is_discovery_complete(ioc))) {
359 devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "clearing "
360 "discovery_quiesce_io flag\n", ioc->name));
361 ioc->sas_discovery_quiesce_io = 0;
362 }
363 }
364
365 out:
366 /*
367 * Take turns polling alternate controller
368 */
369 if (ioc->alt_ioc)
370 ioc = ioc->alt_ioc;
371
372 /* rearm the timer */
373 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
374 if (ioc->reset_work_q)
375 queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work,
376 msecs_to_jiffies(MPT_POLLING_INTERVAL));
377 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
378}
379
380
381/*
382 * Process turbo (context) reply...
383 */
384static void
385mpt_turbo_reply(MPT_ADAPTER *ioc, u32 pa)
386{
387 MPT_FRAME_HDR *mf = NULL;
388 MPT_FRAME_HDR *mr = NULL;
389 u16 req_idx = 0;
390 u8 cb_idx;
391
392 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got TURBO reply req_idx=%08x\n",
393 ioc->name, pa));
394
395 switch (pa >> MPI_CONTEXT_REPLY_TYPE_SHIFT) {
396 case MPI_CONTEXT_REPLY_TYPE_SCSI_INIT:
397 req_idx = pa & 0x0000FFFF;
398 cb_idx = (pa & 0x00FF0000) >> 16;
399 mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
400 break;
401 case MPI_CONTEXT_REPLY_TYPE_LAN:
402 cb_idx = mpt_get_cb_idx(MPTLAN_DRIVER);
403 /*
404 * Blind set of mf to NULL here was fatal
405 * after lan_reply says "freeme"
406 * Fix sort of combined with an optimization here;
407 * added explicit check for case where lan_reply
408 * was just returning 1 and doing nothing else.
409 * For this case skip the callback, but set up
410 * proper mf value first here:-)
411 */
412 if ((pa & 0x58000000) == 0x58000000) {
413 req_idx = pa & 0x0000FFFF;
414 mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
415 mpt_free_msg_frame(ioc, mf);
416 mb();
417 return;
418 break;
419 }
420 mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa);
421 break;
422 case MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET:
423 cb_idx = mpt_get_cb_idx(MPTSTM_DRIVER);
424 mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa);
425 break;
426 default:
427 cb_idx = 0;
428 BUG();
429 }
430
431 /* Check for (valid) IO callback! */
432 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS ||
433 MptCallbacks[cb_idx] == NULL) {
434 printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n",
435 __func__, ioc->name, cb_idx);
436 goto out;
437 }
438
439 if (MptCallbacks[cb_idx](ioc, mf, mr))
440 mpt_free_msg_frame(ioc, mf);
441 out:
442 mb();
443}
444
445static void
446mpt_reply(MPT_ADAPTER *ioc, u32 pa)
447{
448 MPT_FRAME_HDR *mf;
449 MPT_FRAME_HDR *mr;
450 u16 req_idx;
451 u8 cb_idx;
452 int freeme;
453
454 u32 reply_dma_low;
455 u16 ioc_stat;
456
457 /* non-TURBO reply! Hmmm, something may be up...
458 * Newest turbo reply mechanism; get address
459 * via left shift 1 (get rid of MPI_ADDRESS_REPLY_A_BIT)!
460 */
461
462 /* Map DMA address of reply header to cpu address.
463 * pa is 32 bits - but the dma address may be 32 or 64 bits
464 * get offset based only only the low addresses
465 */
466
467 reply_dma_low = (pa <<= 1);
468 mr = (MPT_FRAME_HDR *)((u8 *)ioc->reply_frames +
469 (reply_dma_low - ioc->reply_frames_low_dma));
470
471 req_idx = le16_to_cpu(mr->u.frame.hwhdr.msgctxu.fld.req_idx);
472 cb_idx = mr->u.frame.hwhdr.msgctxu.fld.cb_idx;
473 mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
474
475 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got non-TURBO reply=%p req_idx=%x cb_idx=%x Function=%x\n",
476 ioc->name, mr, req_idx, cb_idx, mr->u.hdr.Function));
477 DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mr);
478
479 /* Check/log IOC log info
480 */
481 ioc_stat = le16_to_cpu(mr->u.reply.IOCStatus);
482 if (ioc_stat & MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
483 u32 log_info = le32_to_cpu(mr->u.reply.IOCLogInfo);
484 if (ioc->bus_type == FC)
485 mpt_fc_log_info(ioc, log_info);
486 else if (ioc->bus_type == SPI)
487 mpt_spi_log_info(ioc, log_info);
488 else if (ioc->bus_type == SAS)
489 mpt_sas_log_info(ioc, log_info, cb_idx);
490 }
491
492 if (ioc_stat & MPI_IOCSTATUS_MASK)
493 mpt_iocstatus_info(ioc, (u32)ioc_stat, mf);
494
495 /* Check for (valid) IO callback! */
496 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS ||
497 MptCallbacks[cb_idx] == NULL) {
498 printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n",
499 __func__, ioc->name, cb_idx);
500 freeme = 0;
501 goto out;
502 }
503
504 freeme = MptCallbacks[cb_idx](ioc, mf, mr);
505
506 out:
507 /* Flush (non-TURBO) reply with a WRITE! */
508 CHIPREG_WRITE32(&ioc->chip->ReplyFifo, pa);
509
510 if (freeme)
511 mpt_free_msg_frame(ioc, mf);
512 mb();
513}
514
515/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
516/**
517 * mpt_interrupt - MPT adapter (IOC) specific interrupt handler.
518 * @irq: irq number (not used)
519 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
520 *
521 * This routine is registered via the request_irq() kernel API call,
522 * and handles all interrupts generated from a specific MPT adapter
523 * (also referred to as a IO Controller or IOC).
524 * This routine must clear the interrupt from the adapter and does
525 * so by reading the reply FIFO. Multiple replies may be processed
526 * per single call to this routine.
527 *
528 * This routine handles register-level access of the adapter but
529 * dispatches (calls) a protocol-specific callback routine to handle
530 * the protocol-specific details of the MPT request completion.
531 */
532static irqreturn_t
533mpt_interrupt(int irq, void *bus_id)
534{
535 MPT_ADAPTER *ioc = bus_id;
536 u32 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
537
538 if (pa == 0xFFFFFFFF)
539 return IRQ_NONE;
540
541 /*
542 * Drain the reply FIFO!
543 */
544 do {
545 if (pa & MPI_ADDRESS_REPLY_A_BIT)
546 mpt_reply(ioc, pa);
547 else
548 mpt_turbo_reply(ioc, pa);
549 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
550 } while (pa != 0xFFFFFFFF);
551
552 return IRQ_HANDLED;
553}
554
555/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
556/**
557 * mptbase_reply - MPT base driver's callback routine
558 * @ioc: Pointer to MPT_ADAPTER structure
559 * @req: Pointer to original MPT request frame
560 * @reply: Pointer to MPT reply frame (NULL if TurboReply)
561 *
562 * MPT base driver's callback routine; all base driver
563 * "internal" request/reply processing is routed here.
564 * Currently used for EventNotification and EventAck handling.
565 *
566 * Returns 1 indicating original alloc'd request frame ptr
567 * should be freed, or 0 if it shouldn't.
568 */
569static int
570mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, MPT_FRAME_HDR *reply)
571{
572 EventNotificationReply_t *pEventReply;
573 u8 event;
574 int evHandlers;
575 int freereq = 1;
576
577 switch (reply->u.hdr.Function) {
578 case MPI_FUNCTION_EVENT_NOTIFICATION:
579 pEventReply = (EventNotificationReply_t *)reply;
580 evHandlers = 0;
581 ProcessEventNotification(ioc, pEventReply, &evHandlers);
582 event = le32_to_cpu(pEventReply->Event) & 0xFF;
583 if (pEventReply->MsgFlags & MPI_MSGFLAGS_CONTINUATION_REPLY)
584 freereq = 0;
585 if (event != MPI_EVENT_EVENT_CHANGE)
586 break;
587 case MPI_FUNCTION_CONFIG:
588 case MPI_FUNCTION_SAS_IO_UNIT_CONTROL:
589 ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_COMMAND_GOOD;
590 if (reply) {
591 ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_RF_VALID;
592 memcpy(ioc->mptbase_cmds.reply, reply,
593 min(MPT_DEFAULT_FRAME_SIZE,
594 4 * reply->u.reply.MsgLength));
595 }
596 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) {
597 ioc->mptbase_cmds.status &= ~MPT_MGMT_STATUS_PENDING;
598 complete(&ioc->mptbase_cmds.done);
599 } else
600 freereq = 0;
601 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_FREE_MF)
602 freereq = 1;
603 break;
604 case MPI_FUNCTION_EVENT_ACK:
605 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
606 "EventAck reply received\n", ioc->name));
607 break;
608 default:
609 printk(MYIOC_s_ERR_FMT
610 "Unexpected msg function (=%02Xh) reply received!\n",
611 ioc->name, reply->u.hdr.Function);
612 break;
613 }
614
615 /*
616 * Conditionally tell caller to free the original
617 * EventNotification/EventAck/unexpected request frame!
618 */
619 return freereq;
620}
621
622/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
623/**
624 * mpt_register - Register protocol-specific main callback handler.
625 * @cbfunc: callback function pointer
626 * @dclass: Protocol driver's class (%MPT_DRIVER_CLASS enum value)
627 * @func_name: call function's name
628 *
629 * This routine is called by a protocol-specific driver (SCSI host,
630 * LAN, SCSI target) to register its reply callback routine. Each
631 * protocol-specific driver must do this before it will be able to
632 * use any IOC resources, such as obtaining request frames.
633 *
634 * NOTES: The SCSI protocol driver currently calls this routine thrice
635 * in order to register separate callbacks; one for "normal" SCSI IO;
636 * one for MptScsiTaskMgmt requests; one for Scan/DV requests.
637 *
638 * Returns u8 valued "handle" in the range (and S.O.D. order)
639 * {N,...,7,6,5,...,1} if successful.
640 * A return value of MPT_MAX_PROTOCOL_DRIVERS (including zero!) should be
641 * considered an error by the caller.
642 */
643u8
644mpt_register(MPT_CALLBACK cbfunc, MPT_DRIVER_CLASS dclass, char *func_name)
645{
646 u8 cb_idx;
647 last_drv_idx = MPT_MAX_PROTOCOL_DRIVERS;
648
649 /*
650 * Search for empty callback slot in this order: {N,...,7,6,5,...,1}
651 * (slot/handle 0 is reserved!)
652 */
653 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
654 if (MptCallbacks[cb_idx] == NULL) {
655 MptCallbacks[cb_idx] = cbfunc;
656 MptDriverClass[cb_idx] = dclass;
657 MptEvHandlers[cb_idx] = NULL;
658 last_drv_idx = cb_idx;
659 memcpy(MptCallbacksName[cb_idx], func_name,
660 strlen(func_name) > 50 ? 50 : strlen(func_name));
661 break;
662 }
663 }
664
665 return last_drv_idx;
666}
667
668/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
669/**
670 * mpt_deregister - Deregister a protocol drivers resources.
671 * @cb_idx: previously registered callback handle
672 *
673 * Each protocol-specific driver should call this routine when its
674 * module is unloaded.
675 */
676void
677mpt_deregister(u8 cb_idx)
678{
679 if (cb_idx && (cb_idx < MPT_MAX_PROTOCOL_DRIVERS)) {
680 MptCallbacks[cb_idx] = NULL;
681 MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER;
682 MptEvHandlers[cb_idx] = NULL;
683
684 last_drv_idx++;
685 }
686}
687
688/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
689/**
690 * mpt_event_register - Register protocol-specific event callback handler.
691 * @cb_idx: previously registered (via mpt_register) callback handle
692 * @ev_cbfunc: callback function
693 *
694 * This routine can be called by one or more protocol-specific drivers
695 * if/when they choose to be notified of MPT events.
696 *
697 * Returns 0 for success.
698 */
699int
700mpt_event_register(u8 cb_idx, MPT_EVHANDLER ev_cbfunc)
701{
702 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
703 return -1;
704
705 MptEvHandlers[cb_idx] = ev_cbfunc;
706 return 0;
707}
708
709/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
710/**
711 * mpt_event_deregister - Deregister protocol-specific event callback handler
712 * @cb_idx: previously registered callback handle
713 *
714 * Each protocol-specific driver should call this routine
715 * when it does not (or can no longer) handle events,
716 * or when its module is unloaded.
717 */
718void
719mpt_event_deregister(u8 cb_idx)
720{
721 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
722 return;
723
724 MptEvHandlers[cb_idx] = NULL;
725}
726
727/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
728/**
729 * mpt_reset_register - Register protocol-specific IOC reset handler.
730 * @cb_idx: previously registered (via mpt_register) callback handle
731 * @reset_func: reset function
732 *
733 * This routine can be called by one or more protocol-specific drivers
734 * if/when they choose to be notified of IOC resets.
735 *
736 * Returns 0 for success.
737 */
738int
739mpt_reset_register(u8 cb_idx, MPT_RESETHANDLER reset_func)
740{
741 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
742 return -1;
743
744 MptResetHandlers[cb_idx] = reset_func;
745 return 0;
746}
747
748/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
749/**
750 * mpt_reset_deregister - Deregister protocol-specific IOC reset handler.
751 * @cb_idx: previously registered callback handle
752 *
753 * Each protocol-specific driver should call this routine
754 * when it does not (or can no longer) handle IOC reset handling,
755 * or when its module is unloaded.
756 */
757void
758mpt_reset_deregister(u8 cb_idx)
759{
760 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
761 return;
762
763 MptResetHandlers[cb_idx] = NULL;
764}
765
766/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
767/**
768 * mpt_device_driver_register - Register device driver hooks
769 * @dd_cbfunc: driver callbacks struct
770 * @cb_idx: MPT protocol driver index
771 */
772int
773mpt_device_driver_register(struct mpt_pci_driver * dd_cbfunc, u8 cb_idx)
774{
775 MPT_ADAPTER *ioc;
776 const struct pci_device_id *id;
777
778 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
779 return -EINVAL;
780
781 MptDeviceDriverHandlers[cb_idx] = dd_cbfunc;
782
783 /* call per pci device probe entry point */
784 list_for_each_entry(ioc, &ioc_list, list) {
785 id = ioc->pcidev->driver ?
786 ioc->pcidev->driver->id_table : NULL;
787 if (dd_cbfunc->probe)
788 dd_cbfunc->probe(ioc->pcidev, id);
789 }
790
791 return 0;
792}
793
794/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
795/**
796 * mpt_device_driver_deregister - DeRegister device driver hooks
797 * @cb_idx: MPT protocol driver index
798 */
799void
800mpt_device_driver_deregister(u8 cb_idx)
801{
802 struct mpt_pci_driver *dd_cbfunc;
803 MPT_ADAPTER *ioc;
804
805 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
806 return;
807
808 dd_cbfunc = MptDeviceDriverHandlers[cb_idx];
809
810 list_for_each_entry(ioc, &ioc_list, list) {
811 if (dd_cbfunc->remove)
812 dd_cbfunc->remove(ioc->pcidev);
813 }
814
815 MptDeviceDriverHandlers[cb_idx] = NULL;
816}
817
818
819/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
820/**
821 * mpt_get_msg_frame - Obtain an MPT request frame from the pool
822 * @cb_idx: Handle of registered MPT protocol driver
823 * @ioc: Pointer to MPT adapter structure
824 *
825 * Obtain an MPT request frame from the pool (of 1024) that are
826 * allocated per MPT adapter.
827 *
828 * Returns pointer to a MPT request frame or %NULL if none are available
829 * or IOC is not active.
830 */
831MPT_FRAME_HDR*
832mpt_get_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc)
833{
834 MPT_FRAME_HDR *mf;
835 unsigned long flags;
836 u16 req_idx; /* Request index */
837
838 /* validate handle and ioc identifier */
839
840#ifdef MFCNT
841 if (!ioc->active)
842 printk(MYIOC_s_WARN_FMT "IOC Not Active! mpt_get_msg_frame "
843 "returning NULL!\n", ioc->name);
844#endif
845
846 /* If interrupts are not attached, do not return a request frame */
847 if (!ioc->active)
848 return NULL;
849
850 spin_lock_irqsave(&ioc->FreeQlock, flags);
851 if (!list_empty(&ioc->FreeQ)) {
852 int req_offset;
853
854 mf = list_entry(ioc->FreeQ.next, MPT_FRAME_HDR,
855 u.frame.linkage.list);
856 list_del(&mf->u.frame.linkage.list);
857 mf->u.frame.linkage.arg1 = 0;
858 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */
859 req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
860 /* u16! */
861 req_idx = req_offset / ioc->req_sz;
862 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
863 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
864 /* Default, will be changed if necessary in SG generation */
865 ioc->RequestNB[req_idx] = ioc->NB_for_64_byte_frame;
866#ifdef MFCNT
867 ioc->mfcnt++;
868#endif
869 }
870 else
871 mf = NULL;
872 spin_unlock_irqrestore(&ioc->FreeQlock, flags);
873
874#ifdef MFCNT
875 if (mf == NULL)
876 printk(MYIOC_s_WARN_FMT "IOC Active. No free Msg Frames! "
877 "Count 0x%x Max 0x%x\n", ioc->name, ioc->mfcnt,
878 ioc->req_depth);
879 mfcounter++;
880 if (mfcounter == PRINT_MF_COUNT)
881 printk(MYIOC_s_INFO_FMT "MF Count 0x%x Max 0x%x \n", ioc->name,
882 ioc->mfcnt, ioc->req_depth);
883#endif
884
885 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_get_msg_frame(%d,%d), got mf=%p\n",
886 ioc->name, cb_idx, ioc->id, mf));
887 return mf;
888}
889
890/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
891/**
892 * mpt_put_msg_frame - Send a protocol-specific MPT request frame to an IOC
893 * @cb_idx: Handle of registered MPT protocol driver
894 * @ioc: Pointer to MPT adapter structure
895 * @mf: Pointer to MPT request frame
896 *
897 * This routine posts an MPT request frame to the request post FIFO of a
898 * specific MPT adapter.
899 */
900void
901mpt_put_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
902{
903 u32 mf_dma_addr;
904 int req_offset;
905 u16 req_idx; /* Request index */
906
907 /* ensure values are reset properly! */
908 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */
909 req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
910 /* u16! */
911 req_idx = req_offset / ioc->req_sz;
912 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
913 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
914
915 DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf);
916
917 mf_dma_addr = (ioc->req_frames_low_dma + req_offset) | ioc->RequestNB[req_idx];
918 dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d "
919 "RequestNB=%x\n", ioc->name, mf_dma_addr, req_idx,
920 ioc->RequestNB[req_idx]));
921 CHIPREG_WRITE32(&ioc->chip->RequestFifo, mf_dma_addr);
922}
923
924/**
925 * mpt_put_msg_frame_hi_pri - Send a hi-pri protocol-specific MPT request frame
926 * @cb_idx: Handle of registered MPT protocol driver
927 * @ioc: Pointer to MPT adapter structure
928 * @mf: Pointer to MPT request frame
929 *
930 * Send a protocol-specific MPT request frame to an IOC using
931 * hi-priority request queue.
932 *
933 * This routine posts an MPT request frame to the request post FIFO of a
934 * specific MPT adapter.
935 **/
936void
937mpt_put_msg_frame_hi_pri(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
938{
939 u32 mf_dma_addr;
940 int req_offset;
941 u16 req_idx; /* Request index */
942
943 /* ensure values are reset properly! */
944 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
945 req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
946 req_idx = req_offset / ioc->req_sz;
947 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
948 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
949
950 DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf);
951
952 mf_dma_addr = (ioc->req_frames_low_dma + req_offset);
953 dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d\n",
954 ioc->name, mf_dma_addr, req_idx));
955 CHIPREG_WRITE32(&ioc->chip->RequestHiPriFifo, mf_dma_addr);
956}
957
958/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
959/**
960 * mpt_free_msg_frame - Place MPT request frame back on FreeQ.
961 * @ioc: Pointer to MPT adapter structure
962 * @mf: Pointer to MPT request frame
963 *
964 * This routine places a MPT request frame back on the MPT adapter's
965 * FreeQ.
966 */
967void
968mpt_free_msg_frame(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
969{
970 unsigned long flags;
971
972 /* Put Request back on FreeQ! */
973 spin_lock_irqsave(&ioc->FreeQlock, flags);
974 if (cpu_to_le32(mf->u.frame.linkage.arg1) == 0xdeadbeaf)
975 goto out;
976 /* signature to know if this mf is freed */
977 mf->u.frame.linkage.arg1 = cpu_to_le32(0xdeadbeaf);
978 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeQ);
979#ifdef MFCNT
980 ioc->mfcnt--;
981#endif
982 out:
983 spin_unlock_irqrestore(&ioc->FreeQlock, flags);
984}
985
986/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
987/**
988 * mpt_add_sge - Place a simple 32 bit SGE at address pAddr.
989 * @pAddr: virtual address for SGE
990 * @flagslength: SGE flags and data transfer length
991 * @dma_addr: Physical address
992 *
993 * This routine places a MPT request frame back on the MPT adapter's
994 * FreeQ.
995 */
996static void
997mpt_add_sge(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
998{
999 SGESimple32_t *pSge = (SGESimple32_t *) pAddr;
1000 pSge->FlagsLength = cpu_to_le32(flagslength);
1001 pSge->Address = cpu_to_le32(dma_addr);
1002}
1003
1004/**
1005 * mpt_add_sge_64bit - Place a simple 64 bit SGE at address pAddr.
1006 * @pAddr: virtual address for SGE
1007 * @flagslength: SGE flags and data transfer length
1008 * @dma_addr: Physical address
1009 *
1010 * This routine places a MPT request frame back on the MPT adapter's
1011 * FreeQ.
1012 **/
1013static void
1014mpt_add_sge_64bit(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
1015{
1016 SGESimple64_t *pSge = (SGESimple64_t *) pAddr;
1017 pSge->Address.Low = cpu_to_le32
1018 (lower_32_bits(dma_addr));
1019 pSge->Address.High = cpu_to_le32
1020 (upper_32_bits(dma_addr));
1021 pSge->FlagsLength = cpu_to_le32
1022 ((flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING));
1023}
1024
1025/**
1026 * mpt_add_sge_64bit_1078 - Place a simple 64 bit SGE at address pAddr (1078 workaround).
1027 * @pAddr: virtual address for SGE
1028 * @flagslength: SGE flags and data transfer length
1029 * @dma_addr: Physical address
1030 *
1031 * This routine places a MPT request frame back on the MPT adapter's
1032 * FreeQ.
1033 **/
1034static void
1035mpt_add_sge_64bit_1078(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
1036{
1037 SGESimple64_t *pSge = (SGESimple64_t *) pAddr;
1038 u32 tmp;
1039
1040 pSge->Address.Low = cpu_to_le32
1041 (lower_32_bits(dma_addr));
1042 tmp = (u32)(upper_32_bits(dma_addr));
1043
1044 /*
1045 * 1078 errata workaround for the 36GB limitation
1046 */
1047 if ((((u64)dma_addr + MPI_SGE_LENGTH(flagslength)) >> 32) == 9) {
1048 flagslength |=
1049 MPI_SGE_SET_FLAGS(MPI_SGE_FLAGS_LOCAL_ADDRESS);
1050 tmp |= (1<<31);
1051 if (mpt_debug_level & MPT_DEBUG_36GB_MEM)
1052 printk(KERN_DEBUG "1078 P0M2 addressing for "
1053 "addr = 0x%llx len = %d\n",
1054 (unsigned long long)dma_addr,
1055 MPI_SGE_LENGTH(flagslength));
1056 }
1057
1058 pSge->Address.High = cpu_to_le32(tmp);
1059 pSge->FlagsLength = cpu_to_le32(
1060 (flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING));
1061}
1062
1063/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1064/**
1065 * mpt_add_chain - Place a 32 bit chain SGE at address pAddr.
1066 * @pAddr: virtual address for SGE
1067 * @next: nextChainOffset value (u32's)
1068 * @length: length of next SGL segment
1069 * @dma_addr: Physical address
1070 *
1071 */
1072static void
1073mpt_add_chain(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr)
1074{
1075 SGEChain32_t *pChain = (SGEChain32_t *) pAddr;
1076 pChain->Length = cpu_to_le16(length);
1077 pChain->Flags = MPI_SGE_FLAGS_CHAIN_ELEMENT;
1078 pChain->NextChainOffset = next;
1079 pChain->Address = cpu_to_le32(dma_addr);
1080}
1081
1082/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1083/**
1084 * mpt_add_chain_64bit - Place a 64 bit chain SGE at address pAddr.
1085 * @pAddr: virtual address for SGE
1086 * @next: nextChainOffset value (u32's)
1087 * @length: length of next SGL segment
1088 * @dma_addr: Physical address
1089 *
1090 */
1091static void
1092mpt_add_chain_64bit(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr)
1093{
1094 SGEChain64_t *pChain = (SGEChain64_t *) pAddr;
1095 u32 tmp = dma_addr & 0xFFFFFFFF;
1096
1097 pChain->Length = cpu_to_le16(length);
1098 pChain->Flags = (MPI_SGE_FLAGS_CHAIN_ELEMENT |
1099 MPI_SGE_FLAGS_64_BIT_ADDRESSING);
1100
1101 pChain->NextChainOffset = next;
1102
1103 pChain->Address.Low = cpu_to_le32(tmp);
1104 tmp = (u32)(upper_32_bits(dma_addr));
1105 pChain->Address.High = cpu_to_le32(tmp);
1106}
1107
1108/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1109/**
1110 * mpt_send_handshake_request - Send MPT request via doorbell handshake method.
1111 * @cb_idx: Handle of registered MPT protocol driver
1112 * @ioc: Pointer to MPT adapter structure
1113 * @reqBytes: Size of the request in bytes
1114 * @req: Pointer to MPT request frame
1115 * @sleepFlag: Use schedule if CAN_SLEEP else use udelay.
1116 *
1117 * This routine is used exclusively to send MptScsiTaskMgmt
1118 * requests since they are required to be sent via doorbell handshake.
1119 *
1120 * NOTE: It is the callers responsibility to byte-swap fields in the
1121 * request which are greater than 1 byte in size.
1122 *
1123 * Returns 0 for success, non-zero for failure.
1124 */
1125int
1126mpt_send_handshake_request(u8 cb_idx, MPT_ADAPTER *ioc, int reqBytes, u32 *req, int sleepFlag)
1127{
1128 int r = 0;
1129 u8 *req_as_bytes;
1130 int ii;
1131
1132 /* State is known to be good upon entering
1133 * this function so issue the bus reset
1134 * request.
1135 */
1136
1137 /*
1138 * Emulate what mpt_put_msg_frame() does /wrt to sanity
1139 * setting cb_idx/req_idx. But ONLY if this request
1140 * is in proper (pre-alloc'd) request buffer range...
1141 */
1142 ii = MFPTR_2_MPT_INDEX(ioc,(MPT_FRAME_HDR*)req);
1143 if (reqBytes >= 12 && ii >= 0 && ii < ioc->req_depth) {
1144 MPT_FRAME_HDR *mf = (MPT_FRAME_HDR*)req;
1145 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(ii);
1146 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
1147 }
1148
1149 /* Make sure there are no doorbells */
1150 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1151
1152 CHIPREG_WRITE32(&ioc->chip->Doorbell,
1153 ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) |
1154 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT)));
1155
1156 /* Wait for IOC doorbell int */
1157 if ((ii = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) {
1158 return ii;
1159 }
1160
1161 /* Read doorbell and check for active bit */
1162 if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
1163 return -5;
1164
1165 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_send_handshake_request start, WaitCnt=%d\n",
1166 ioc->name, ii));
1167
1168 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1169
1170 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
1171 return -2;
1172 }
1173
1174 /* Send request via doorbell handshake */
1175 req_as_bytes = (u8 *) req;
1176 for (ii = 0; ii < reqBytes/4; ii++) {
1177 u32 word;
1178
1179 word = ((req_as_bytes[(ii*4) + 0] << 0) |
1180 (req_as_bytes[(ii*4) + 1] << 8) |
1181 (req_as_bytes[(ii*4) + 2] << 16) |
1182 (req_as_bytes[(ii*4) + 3] << 24));
1183 CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
1184 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
1185 r = -3;
1186 break;
1187 }
1188 }
1189
1190 if (r >= 0 && WaitForDoorbellInt(ioc, 10, sleepFlag) >= 0)
1191 r = 0;
1192 else
1193 r = -4;
1194
1195 /* Make sure there are no doorbells */
1196 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1197
1198 return r;
1199}
1200
1201/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1202/**
1203 * mpt_host_page_access_control - control the IOC's Host Page Buffer access
1204 * @ioc: Pointer to MPT adapter structure
1205 * @access_control_value: define bits below
1206 * @sleepFlag: Specifies whether the process can sleep
1207 *
1208 * Provides mechanism for the host driver to control the IOC's
1209 * Host Page Buffer access.
1210 *
1211 * Access Control Value - bits[15:12]
1212 * 0h Reserved
1213 * 1h Enable Access { MPI_DB_HPBAC_ENABLE_ACCESS }
1214 * 2h Disable Access { MPI_DB_HPBAC_DISABLE_ACCESS }
1215 * 3h Free Buffer { MPI_DB_HPBAC_FREE_BUFFER }
1216 *
1217 * Returns 0 for success, non-zero for failure.
1218 */
1219
1220static int
1221mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag)
1222{
1223 int r = 0;
1224
1225 /* return if in use */
1226 if (CHIPREG_READ32(&ioc->chip->Doorbell)
1227 & MPI_DOORBELL_ACTIVE)
1228 return -1;
1229
1230 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1231
1232 CHIPREG_WRITE32(&ioc->chip->Doorbell,
1233 ((MPI_FUNCTION_HOST_PAGEBUF_ACCESS_CONTROL
1234 <<MPI_DOORBELL_FUNCTION_SHIFT) |
1235 (access_control_value<<12)));
1236
1237 /* Wait for IOC to clear Doorbell Status bit */
1238 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
1239 return -2;
1240 }else
1241 return 0;
1242}
1243
1244/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1245/**
1246 * mpt_host_page_alloc - allocate system memory for the fw
1247 * @ioc: Pointer to pointer to IOC adapter
1248 * @ioc_init: Pointer to ioc init config page
1249 *
1250 * If we already allocated memory in past, then resend the same pointer.
1251 * Returns 0 for success, non-zero for failure.
1252 */
1253static int
1254mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init)
1255{
1256 char *psge;
1257 int flags_length;
1258 u32 host_page_buffer_sz=0;
1259
1260 if(!ioc->HostPageBuffer) {
1261
1262 host_page_buffer_sz =
1263 le32_to_cpu(ioc->facts.HostPageBufferSGE.FlagsLength) & 0xFFFFFF;
1264
1265 if(!host_page_buffer_sz)
1266 return 0; /* fw doesn't need any host buffers */
1267
1268 /* spin till we get enough memory */
1269 while(host_page_buffer_sz > 0) {
1270
1271 if((ioc->HostPageBuffer = pci_alloc_consistent(
1272 ioc->pcidev,
1273 host_page_buffer_sz,
1274 &ioc->HostPageBuffer_dma)) != NULL) {
1275
1276 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
1277 "host_page_buffer @ %p, dma @ %x, sz=%d bytes\n",
1278 ioc->name, ioc->HostPageBuffer,
1279 (u32)ioc->HostPageBuffer_dma,
1280 host_page_buffer_sz));
1281 ioc->alloc_total += host_page_buffer_sz;
1282 ioc->HostPageBuffer_sz = host_page_buffer_sz;
1283 break;
1284 }
1285
1286 host_page_buffer_sz -= (4*1024);
1287 }
1288 }
1289
1290 if(!ioc->HostPageBuffer) {
1291 printk(MYIOC_s_ERR_FMT
1292 "Failed to alloc memory for host_page_buffer!\n",
1293 ioc->name);
1294 return -999;
1295 }
1296
1297 psge = (char *)&ioc_init->HostPageBufferSGE;
1298 flags_length = MPI_SGE_FLAGS_SIMPLE_ELEMENT |
1299 MPI_SGE_FLAGS_SYSTEM_ADDRESS |
1300 MPI_SGE_FLAGS_HOST_TO_IOC |
1301 MPI_SGE_FLAGS_END_OF_BUFFER;
1302 flags_length = flags_length << MPI_SGE_FLAGS_SHIFT;
1303 flags_length |= ioc->HostPageBuffer_sz;
1304 ioc->add_sge(psge, flags_length, ioc->HostPageBuffer_dma);
1305 ioc->facts.HostPageBufferSGE = ioc_init->HostPageBufferSGE;
1306
1307return 0;
1308}
1309
1310/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1311/**
1312 * mpt_verify_adapter - Given IOC identifier, set pointer to its adapter structure.
1313 * @iocid: IOC unique identifier (integer)
1314 * @iocpp: Pointer to pointer to IOC adapter
1315 *
1316 * Given a unique IOC identifier, set pointer to the associated MPT
1317 * adapter structure.
1318 *
1319 * Returns iocid and sets iocpp if iocid is found.
1320 * Returns -1 if iocid is not found.
1321 */
1322int
1323mpt_verify_adapter(int iocid, MPT_ADAPTER **iocpp)
1324{
1325 MPT_ADAPTER *ioc;
1326
1327 list_for_each_entry(ioc,&ioc_list,list) {
1328 if (ioc->id == iocid) {
1329 *iocpp =ioc;
1330 return iocid;
1331 }
1332 }
1333
1334 *iocpp = NULL;
1335 return -1;
1336}
1337
1338/**
1339 * mpt_get_product_name - returns product string
1340 * @vendor: pci vendor id
1341 * @device: pci device id
1342 * @revision: pci revision id
1343 * @prod_name: string returned
1344 *
1345 * Returns product string displayed when driver loads,
1346 * in /proc/mpt/summary and /sysfs/class/scsi_host/host<X>/version_product
1347 *
1348 **/
1349static void
1350mpt_get_product_name(u16 vendor, u16 device, u8 revision, char *prod_name)
1351{
1352 char *product_str = NULL;
1353
1354 if (vendor == PCI_VENDOR_ID_BROCADE) {
1355 switch (device)
1356 {
1357 case MPI_MANUFACTPAGE_DEVICEID_FC949E:
1358 switch (revision)
1359 {
1360 case 0x00:
1361 product_str = "BRE040 A0";
1362 break;
1363 case 0x01:
1364 product_str = "BRE040 A1";
1365 break;
1366 default:
1367 product_str = "BRE040";
1368 break;
1369 }
1370 break;
1371 }
1372 goto out;
1373 }
1374
1375 switch (device)
1376 {
1377 case MPI_MANUFACTPAGE_DEVICEID_FC909:
1378 product_str = "LSIFC909 B1";
1379 break;
1380 case MPI_MANUFACTPAGE_DEVICEID_FC919:
1381 product_str = "LSIFC919 B0";
1382 break;
1383 case MPI_MANUFACTPAGE_DEVICEID_FC929:
1384 product_str = "LSIFC929 B0";
1385 break;
1386 case MPI_MANUFACTPAGE_DEVICEID_FC919X:
1387 if (revision < 0x80)
1388 product_str = "LSIFC919X A0";
1389 else
1390 product_str = "LSIFC919XL A1";
1391 break;
1392 case MPI_MANUFACTPAGE_DEVICEID_FC929X:
1393 if (revision < 0x80)
1394 product_str = "LSIFC929X A0";
1395 else
1396 product_str = "LSIFC929XL A1";
1397 break;
1398 case MPI_MANUFACTPAGE_DEVICEID_FC939X:
1399 product_str = "LSIFC939X A1";
1400 break;
1401 case MPI_MANUFACTPAGE_DEVICEID_FC949X:
1402 product_str = "LSIFC949X A1";
1403 break;
1404 case MPI_MANUFACTPAGE_DEVICEID_FC949E:
1405 switch (revision)
1406 {
1407 case 0x00:
1408 product_str = "LSIFC949E A0";
1409 break;
1410 case 0x01:
1411 product_str = "LSIFC949E A1";
1412 break;
1413 default:
1414 product_str = "LSIFC949E";
1415 break;
1416 }
1417 break;
1418 case MPI_MANUFACTPAGE_DEVID_53C1030:
1419 switch (revision)
1420 {
1421 case 0x00:
1422 product_str = "LSI53C1030 A0";
1423 break;
1424 case 0x01:
1425 product_str = "LSI53C1030 B0";
1426 break;
1427 case 0x03:
1428 product_str = "LSI53C1030 B1";
1429 break;
1430 case 0x07:
1431 product_str = "LSI53C1030 B2";
1432 break;
1433 case 0x08:
1434 product_str = "LSI53C1030 C0";
1435 break;
1436 case 0x80:
1437 product_str = "LSI53C1030T A0";
1438 break;
1439 case 0x83:
1440 product_str = "LSI53C1030T A2";
1441 break;
1442 case 0x87:
1443 product_str = "LSI53C1030T A3";
1444 break;
1445 case 0xc1:
1446 product_str = "LSI53C1020A A1";
1447 break;
1448 default:
1449 product_str = "LSI53C1030";
1450 break;
1451 }
1452 break;
1453 case MPI_MANUFACTPAGE_DEVID_1030_53C1035:
1454 switch (revision)
1455 {
1456 case 0x03:
1457 product_str = "LSI53C1035 A2";
1458 break;
1459 case 0x04:
1460 product_str = "LSI53C1035 B0";
1461 break;
1462 default:
1463 product_str = "LSI53C1035";
1464 break;
1465 }
1466 break;
1467 case MPI_MANUFACTPAGE_DEVID_SAS1064:
1468 switch (revision)
1469 {
1470 case 0x00:
1471 product_str = "LSISAS1064 A1";
1472 break;
1473 case 0x01:
1474 product_str = "LSISAS1064 A2";
1475 break;
1476 case 0x02:
1477 product_str = "LSISAS1064 A3";
1478 break;
1479 case 0x03:
1480 product_str = "LSISAS1064 A4";
1481 break;
1482 default:
1483 product_str = "LSISAS1064";
1484 break;
1485 }
1486 break;
1487 case MPI_MANUFACTPAGE_DEVID_SAS1064E:
1488 switch (revision)
1489 {
1490 case 0x00:
1491 product_str = "LSISAS1064E A0";
1492 break;
1493 case 0x01:
1494 product_str = "LSISAS1064E B0";
1495 break;
1496 case 0x02:
1497 product_str = "LSISAS1064E B1";
1498 break;
1499 case 0x04:
1500 product_str = "LSISAS1064E B2";
1501 break;
1502 case 0x08:
1503 product_str = "LSISAS1064E B3";
1504 break;
1505 default:
1506 product_str = "LSISAS1064E";
1507 break;
1508 }
1509 break;
1510 case MPI_MANUFACTPAGE_DEVID_SAS1068:
1511 switch (revision)
1512 {
1513 case 0x00:
1514 product_str = "LSISAS1068 A0";
1515 break;
1516 case 0x01:
1517 product_str = "LSISAS1068 B0";
1518 break;
1519 case 0x02:
1520 product_str = "LSISAS1068 B1";
1521 break;
1522 default:
1523 product_str = "LSISAS1068";
1524 break;
1525 }
1526 break;
1527 case MPI_MANUFACTPAGE_DEVID_SAS1068E:
1528 switch (revision)
1529 {
1530 case 0x00:
1531 product_str = "LSISAS1068E A0";
1532 break;
1533 case 0x01:
1534 product_str = "LSISAS1068E B0";
1535 break;
1536 case 0x02:
1537 product_str = "LSISAS1068E B1";
1538 break;
1539 case 0x04:
1540 product_str = "LSISAS1068E B2";
1541 break;
1542 case 0x08:
1543 product_str = "LSISAS1068E B3";
1544 break;
1545 default:
1546 product_str = "LSISAS1068E";
1547 break;
1548 }
1549 break;
1550 case MPI_MANUFACTPAGE_DEVID_SAS1078:
1551 switch (revision)
1552 {
1553 case 0x00:
1554 product_str = "LSISAS1078 A0";
1555 break;
1556 case 0x01:
1557 product_str = "LSISAS1078 B0";
1558 break;
1559 case 0x02:
1560 product_str = "LSISAS1078 C0";
1561 break;
1562 case 0x03:
1563 product_str = "LSISAS1078 C1";
1564 break;
1565 case 0x04:
1566 product_str = "LSISAS1078 C2";
1567 break;
1568 default:
1569 product_str = "LSISAS1078";
1570 break;
1571 }
1572 break;
1573 }
1574
1575 out:
1576 if (product_str)
1577 sprintf(prod_name, "%s", product_str);
1578}
1579
1580/**
1581 * mpt_mapresources - map in memory mapped io
1582 * @ioc: Pointer to pointer to IOC adapter
1583 *
1584 **/
1585static int
1586mpt_mapresources(MPT_ADAPTER *ioc)
1587{
1588 u8 __iomem *mem;
1589 int ii;
1590 resource_size_t mem_phys;
1591 unsigned long port;
1592 u32 msize;
1593 u32 psize;
1594 u8 revision;
1595 int r = -ENODEV;
1596 struct pci_dev *pdev;
1597
1598 pdev = ioc->pcidev;
1599 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
1600 if (pci_enable_device_mem(pdev)) {
1601 printk(MYIOC_s_ERR_FMT "pci_enable_device_mem() "
1602 "failed\n", ioc->name);
1603 return r;
1604 }
1605 if (pci_request_selected_regions(pdev, ioc->bars, "mpt")) {
1606 printk(MYIOC_s_ERR_FMT "pci_request_selected_regions() with "
1607 "MEM failed\n", ioc->name);
1608 return r;
1609 }
1610
1611 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision);
1612
1613 if (sizeof(dma_addr_t) > 4) {
1614 const uint64_t required_mask = dma_get_required_mask
1615 (&pdev->dev);
1616 if (required_mask > DMA_BIT_MASK(32)
1617 && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
1618 && !pci_set_consistent_dma_mask(pdev,
1619 DMA_BIT_MASK(64))) {
1620 ioc->dma_mask = DMA_BIT_MASK(64);
1621 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
1622 ": 64 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
1623 ioc->name));
1624 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1625 && !pci_set_consistent_dma_mask(pdev,
1626 DMA_BIT_MASK(32))) {
1627 ioc->dma_mask = DMA_BIT_MASK(32);
1628 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
1629 ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
1630 ioc->name));
1631 } else {
1632 printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n",
1633 ioc->name, pci_name(pdev));
1634 pci_release_selected_regions(pdev, ioc->bars);
1635 return r;
1636 }
1637 } else {
1638 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))
1639 && !pci_set_consistent_dma_mask(pdev,
1640 DMA_BIT_MASK(32))) {
1641 ioc->dma_mask = DMA_BIT_MASK(32);
1642 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
1643 ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
1644 ioc->name));
1645 } else {
1646 printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n",
1647 ioc->name, pci_name(pdev));
1648 pci_release_selected_regions(pdev, ioc->bars);
1649 return r;
1650 }
1651 }
1652
1653 mem_phys = msize = 0;
1654 port = psize = 0;
1655 for (ii = 0; ii < DEVICE_COUNT_RESOURCE; ii++) {
1656 if (pci_resource_flags(pdev, ii) & PCI_BASE_ADDRESS_SPACE_IO) {
1657 if (psize)
1658 continue;
1659 /* Get I/O space! */
1660 port = pci_resource_start(pdev, ii);
1661 psize = pci_resource_len(pdev, ii);
1662 } else {
1663 if (msize)
1664 continue;
1665 /* Get memmap */
1666 mem_phys = pci_resource_start(pdev, ii);
1667 msize = pci_resource_len(pdev, ii);
1668 }
1669 }
1670 ioc->mem_size = msize;
1671
1672 mem = NULL;
1673 /* Get logical ptr for PciMem0 space */
1674 /*mem = ioremap(mem_phys, msize);*/
1675 mem = ioremap(mem_phys, msize);
1676 if (mem == NULL) {
1677 printk(MYIOC_s_ERR_FMT ": ERROR - Unable to map adapter"
1678 " memory!\n", ioc->name);
1679 pci_release_selected_regions(pdev, ioc->bars);
1680 return -EINVAL;
1681 }
1682 ioc->memmap = mem;
1683 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "mem = %p, mem_phys = %llx\n",
1684 ioc->name, mem, (unsigned long long)mem_phys));
1685
1686 ioc->mem_phys = mem_phys;
1687 ioc->chip = (SYSIF_REGS __iomem *)mem;
1688
1689 /* Save Port IO values in case we need to do downloadboot */
1690 ioc->pio_mem_phys = port;
1691 ioc->pio_chip = (SYSIF_REGS __iomem *)port;
1692
1693 return 0;
1694}
1695
1696/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1697/**
1698 * mpt_attach - Install a PCI intelligent MPT adapter.
1699 * @pdev: Pointer to pci_dev structure
1700 * @id: PCI device ID information
1701 *
1702 * This routine performs all the steps necessary to bring the IOC of
1703 * a MPT adapter to a OPERATIONAL state. This includes registering
1704 * memory regions, registering the interrupt, and allocating request
1705 * and reply memory pools.
1706 *
1707 * This routine also pre-fetches the LAN MAC address of a Fibre Channel
1708 * MPT adapter.
1709 *
1710 * Returns 0 for success, non-zero for failure.
1711 *
1712 * TODO: Add support for polled controllers
1713 */
1714int
1715mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1716{
1717 MPT_ADAPTER *ioc;
1718 u8 cb_idx;
1719 int r = -ENODEV;
1720 u8 revision;
1721 u8 pcixcmd;
1722 static int mpt_ids = 0;
1723#ifdef CONFIG_PROC_FS
1724 struct proc_dir_entry *dent;
1725#endif
1726
1727 ioc = kzalloc(sizeof(MPT_ADAPTER), GFP_ATOMIC);
1728 if (ioc == NULL) {
1729 printk(KERN_ERR MYNAM ": ERROR - Insufficient memory to add adapter!\n");
1730 return -ENOMEM;
1731 }
1732
1733 ioc->id = mpt_ids++;
1734 sprintf(ioc->name, "ioc%d", ioc->id);
1735 dinitprintk(ioc, printk(KERN_WARNING MYNAM ": mpt_adapter_install\n"));
1736
1737 /*
1738 * set initial debug level
1739 * (refer to mptdebug.h)
1740 *
1741 */
1742 ioc->debug_level = mpt_debug_level;
1743 if (mpt_debug_level)
1744 printk(KERN_INFO "mpt_debug_level=%xh\n", mpt_debug_level);
1745
1746 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": mpt_adapter_install\n", ioc->name));
1747
1748 ioc->pcidev = pdev;
1749 if (mpt_mapresources(ioc)) {
1750 kfree(ioc);
1751 return r;
1752 }
1753
1754 /*
1755 * Setting up proper handlers for scatter gather handling
1756 */
1757 if (ioc->dma_mask == DMA_BIT_MASK(64)) {
1758 if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078)
1759 ioc->add_sge = &mpt_add_sge_64bit_1078;
1760 else
1761 ioc->add_sge = &mpt_add_sge_64bit;
1762 ioc->add_chain = &mpt_add_chain_64bit;
1763 ioc->sg_addr_size = 8;
1764 } else {
1765 ioc->add_sge = &mpt_add_sge;
1766 ioc->add_chain = &mpt_add_chain;
1767 ioc->sg_addr_size = 4;
1768 }
1769 ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size;
1770
1771 ioc->alloc_total = sizeof(MPT_ADAPTER);
1772 ioc->req_sz = MPT_DEFAULT_FRAME_SIZE; /* avoid div by zero! */
1773 ioc->reply_sz = MPT_REPLY_FRAME_SIZE;
1774
1775
1776 spin_lock_init(&ioc->taskmgmt_lock);
1777 mutex_init(&ioc->internal_cmds.mutex);
1778 init_completion(&ioc->internal_cmds.done);
1779 mutex_init(&ioc->mptbase_cmds.mutex);
1780 init_completion(&ioc->mptbase_cmds.done);
1781 mutex_init(&ioc->taskmgmt_cmds.mutex);
1782 init_completion(&ioc->taskmgmt_cmds.done);
1783
1784 /* Initialize the event logging.
1785 */
1786 ioc->eventTypes = 0; /* None */
1787 ioc->eventContext = 0;
1788 ioc->eventLogSize = 0;
1789 ioc->events = NULL;
1790
1791#ifdef MFCNT
1792 ioc->mfcnt = 0;
1793#endif
1794
1795 ioc->sh = NULL;
1796 ioc->cached_fw = NULL;
1797
1798 /* Initialize SCSI Config Data structure
1799 */
1800 memset(&ioc->spi_data, 0, sizeof(SpiCfgData));
1801
1802 /* Initialize the fc rport list head.
1803 */
1804 INIT_LIST_HEAD(&ioc->fc_rports);
1805
1806 /* Find lookup slot. */
1807 INIT_LIST_HEAD(&ioc->list);
1808
1809
1810 /* Initialize workqueue */
1811 INIT_DELAYED_WORK(&ioc->fault_reset_work, mpt_fault_reset_work);
1812
1813 snprintf(ioc->reset_work_q_name, MPT_KOBJ_NAME_LEN,
1814 "mpt_poll_%d", ioc->id);
1815 ioc->reset_work_q =
1816 create_singlethread_workqueue(ioc->reset_work_q_name);
1817 if (!ioc->reset_work_q) {
1818 printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n",
1819 ioc->name);
1820 pci_release_selected_regions(pdev, ioc->bars);
1821 kfree(ioc);
1822 return -ENOMEM;
1823 }
1824
1825 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "facts @ %p, pfacts[0] @ %p\n",
1826 ioc->name, &ioc->facts, &ioc->pfacts[0]));
1827
1828 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision);
1829 mpt_get_product_name(pdev->vendor, pdev->device, revision, ioc->prod_name);
1830
1831 switch (pdev->device)
1832 {
1833 case MPI_MANUFACTPAGE_DEVICEID_FC939X:
1834 case MPI_MANUFACTPAGE_DEVICEID_FC949X:
1835 ioc->errata_flag_1064 = 1;
1836 case MPI_MANUFACTPAGE_DEVICEID_FC909:
1837 case MPI_MANUFACTPAGE_DEVICEID_FC929:
1838 case MPI_MANUFACTPAGE_DEVICEID_FC919:
1839 case MPI_MANUFACTPAGE_DEVICEID_FC949E:
1840 ioc->bus_type = FC;
1841 break;
1842
1843 case MPI_MANUFACTPAGE_DEVICEID_FC929X:
1844 if (revision < XL_929) {
1845 /* 929X Chip Fix. Set Split transactions level
1846 * for PCIX. Set MOST bits to zero.
1847 */
1848 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1849 pcixcmd &= 0x8F;
1850 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1851 } else {
1852 /* 929XL Chip Fix. Set MMRBC to 0x08.
1853 */
1854 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1855 pcixcmd |= 0x08;
1856 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1857 }
1858 ioc->bus_type = FC;
1859 break;
1860
1861 case MPI_MANUFACTPAGE_DEVICEID_FC919X:
1862 /* 919X Chip Fix. Set Split transactions level
1863 * for PCIX. Set MOST bits to zero.
1864 */
1865 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1866 pcixcmd &= 0x8F;
1867 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1868 ioc->bus_type = FC;
1869 break;
1870
1871 case MPI_MANUFACTPAGE_DEVID_53C1030:
1872 /* 1030 Chip Fix. Disable Split transactions
1873 * for PCIX. Set MOST bits to zero if Rev < C0( = 8).
1874 */
1875 if (revision < C0_1030) {
1876 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1877 pcixcmd &= 0x8F;
1878 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1879 }
1880
1881 case MPI_MANUFACTPAGE_DEVID_1030_53C1035:
1882 ioc->bus_type = SPI;
1883 break;
1884
1885 case MPI_MANUFACTPAGE_DEVID_SAS1064:
1886 case MPI_MANUFACTPAGE_DEVID_SAS1068:
1887 ioc->errata_flag_1064 = 1;
1888 ioc->bus_type = SAS;
1889 break;
1890
1891 case MPI_MANUFACTPAGE_DEVID_SAS1064E:
1892 case MPI_MANUFACTPAGE_DEVID_SAS1068E:
1893 case MPI_MANUFACTPAGE_DEVID_SAS1078:
1894 ioc->bus_type = SAS;
1895 break;
1896 }
1897
1898
1899 switch (ioc->bus_type) {
1900
1901 case SAS:
1902 ioc->msi_enable = mpt_msi_enable_sas;
1903 break;
1904
1905 case SPI:
1906 ioc->msi_enable = mpt_msi_enable_spi;
1907 break;
1908
1909 case FC:
1910 ioc->msi_enable = mpt_msi_enable_fc;
1911 break;
1912
1913 default:
1914 ioc->msi_enable = 0;
1915 break;
1916 }
1917
1918 ioc->fw_events_off = 1;
1919
1920 if (ioc->errata_flag_1064)
1921 pci_disable_io_access(pdev);
1922
1923 spin_lock_init(&ioc->FreeQlock);
1924
1925 /* Disable all! */
1926 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
1927 ioc->active = 0;
1928 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1929
1930 /* Set IOC ptr in the pcidev's driver data. */
1931 pci_set_drvdata(ioc->pcidev, ioc);
1932
1933 /* Set lookup ptr. */
1934 list_add_tail(&ioc->list, &ioc_list);
1935
1936 /* Check for "bound ports" (929, 929X, 1030, 1035) to reduce redundant resets.
1937 */
1938 mpt_detect_bound_ports(ioc, pdev);
1939
1940 INIT_LIST_HEAD(&ioc->fw_event_list);
1941 spin_lock_init(&ioc->fw_event_lock);
1942 snprintf(ioc->fw_event_q_name, MPT_KOBJ_NAME_LEN, "mpt/%d", ioc->id);
1943 ioc->fw_event_q = create_singlethread_workqueue(ioc->fw_event_q_name);
1944
1945 if ((r = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP,
1946 CAN_SLEEP)) != 0){
1947 printk(MYIOC_s_ERR_FMT "didn't initialize properly! (%d)\n",
1948 ioc->name, r);
1949
1950 list_del(&ioc->list);
1951 if (ioc->alt_ioc)
1952 ioc->alt_ioc->alt_ioc = NULL;
1953 iounmap(ioc->memmap);
1954 if (r != -5)
1955 pci_release_selected_regions(pdev, ioc->bars);
1956
1957 destroy_workqueue(ioc->reset_work_q);
1958 ioc->reset_work_q = NULL;
1959
1960 kfree(ioc);
1961 pci_set_drvdata(pdev, NULL);
1962 return r;
1963 }
1964
1965 /* call per device driver probe entry point */
1966 for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
1967 if(MptDeviceDriverHandlers[cb_idx] &&
1968 MptDeviceDriverHandlers[cb_idx]->probe) {
1969 MptDeviceDriverHandlers[cb_idx]->probe(pdev,id);
1970 }
1971 }
1972
1973#ifdef CONFIG_PROC_FS
1974 /*
1975 * Create "/proc/mpt/iocN" subdirectory entry for each MPT adapter.
1976 */
1977 dent = proc_mkdir(ioc->name, mpt_proc_root_dir);
1978 if (dent) {
1979 proc_create_data("info", S_IRUGO, dent, &mpt_iocinfo_proc_fops, ioc);
1980 proc_create_data("summary", S_IRUGO, dent, &mpt_summary_proc_fops, ioc);
1981 }
1982#endif
1983
1984 if (!ioc->alt_ioc)
1985 queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work,
1986 msecs_to_jiffies(MPT_POLLING_INTERVAL));
1987
1988 return 0;
1989}
1990
1991/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1992/**
1993 * mpt_detach - Remove a PCI intelligent MPT adapter.
1994 * @pdev: Pointer to pci_dev structure
1995 */
1996
1997void
1998mpt_detach(struct pci_dev *pdev)
1999{
2000 MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
2001 char pname[32];
2002 u8 cb_idx;
2003 unsigned long flags;
2004 struct workqueue_struct *wq;
2005
2006 /*
2007 * Stop polling ioc for fault condition
2008 */
2009 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
2010 wq = ioc->reset_work_q;
2011 ioc->reset_work_q = NULL;
2012 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
2013 cancel_delayed_work(&ioc->fault_reset_work);
2014 destroy_workqueue(wq);
2015
2016 spin_lock_irqsave(&ioc->fw_event_lock, flags);
2017 wq = ioc->fw_event_q;
2018 ioc->fw_event_q = NULL;
2019 spin_unlock_irqrestore(&ioc->fw_event_lock, flags);
2020 destroy_workqueue(wq);
2021
2022 sprintf(pname, MPT_PROCFS_MPTBASEDIR "/%s/summary", ioc->name);
2023 remove_proc_entry(pname, NULL);
2024 sprintf(pname, MPT_PROCFS_MPTBASEDIR "/%s/info", ioc->name);
2025 remove_proc_entry(pname, NULL);
2026 sprintf(pname, MPT_PROCFS_MPTBASEDIR "/%s", ioc->name);
2027 remove_proc_entry(pname, NULL);
2028
2029 /* call per device driver remove entry point */
2030 for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
2031 if(MptDeviceDriverHandlers[cb_idx] &&
2032 MptDeviceDriverHandlers[cb_idx]->remove) {
2033 MptDeviceDriverHandlers[cb_idx]->remove(pdev);
2034 }
2035 }
2036
2037 /* Disable interrupts! */
2038 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2039
2040 ioc->active = 0;
2041 synchronize_irq(pdev->irq);
2042
2043 /* Clear any lingering interrupt */
2044 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
2045
2046 CHIPREG_READ32(&ioc->chip->IntStatus);
2047
2048 mpt_adapter_dispose(ioc);
2049
2050}
2051
2052/**************************************************************************
2053 * Power Management
2054 */
2055#ifdef CONFIG_PM
2056/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2057/**
2058 * mpt_suspend - Fusion MPT base driver suspend routine.
2059 * @pdev: Pointer to pci_dev structure
2060 * @state: new state to enter
2061 */
2062int
2063mpt_suspend(struct pci_dev *pdev, pm_message_t state)
2064{
2065 u32 device_state;
2066 MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
2067
2068 device_state = pci_choose_state(pdev, state);
2069 printk(MYIOC_s_INFO_FMT "pci-suspend: pdev=0x%p, slot=%s, Entering "
2070 "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev),
2071 device_state);
2072
2073 /* put ioc into READY_STATE */
2074 if(SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, CAN_SLEEP)) {
2075 printk(MYIOC_s_ERR_FMT
2076 "pci-suspend: IOC msg unit reset failed!\n", ioc->name);
2077 }
2078
2079 /* disable interrupts */
2080 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2081 ioc->active = 0;
2082
2083 /* Clear any lingering interrupt */
2084 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
2085
2086 free_irq(ioc->pci_irq, ioc);
2087 if (ioc->msi_enable)
2088 pci_disable_msi(ioc->pcidev);
2089 ioc->pci_irq = -1;
2090 pci_save_state(pdev);
2091 pci_disable_device(pdev);
2092 pci_release_selected_regions(pdev, ioc->bars);
2093 pci_set_power_state(pdev, device_state);
2094 return 0;
2095}
2096
2097/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2098/**
2099 * mpt_resume - Fusion MPT base driver resume routine.
2100 * @pdev: Pointer to pci_dev structure
2101 */
2102int
2103mpt_resume(struct pci_dev *pdev)
2104{
2105 MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
2106 u32 device_state = pdev->current_state;
2107 int recovery_state;
2108 int err;
2109
2110 printk(MYIOC_s_INFO_FMT "pci-resume: pdev=0x%p, slot=%s, Previous "
2111 "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev),
2112 device_state);
2113
2114 pci_set_power_state(pdev, PCI_D0);
2115 pci_enable_wake(pdev, PCI_D0, 0);
2116 pci_restore_state(pdev);
2117 ioc->pcidev = pdev;
2118 err = mpt_mapresources(ioc);
2119 if (err)
2120 return err;
2121
2122 if (ioc->dma_mask == DMA_BIT_MASK(64)) {
2123 if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078)
2124 ioc->add_sge = &mpt_add_sge_64bit_1078;
2125 else
2126 ioc->add_sge = &mpt_add_sge_64bit;
2127 ioc->add_chain = &mpt_add_chain_64bit;
2128 ioc->sg_addr_size = 8;
2129 } else {
2130
2131 ioc->add_sge = &mpt_add_sge;
2132 ioc->add_chain = &mpt_add_chain;
2133 ioc->sg_addr_size = 4;
2134 }
2135 ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size;
2136
2137 printk(MYIOC_s_INFO_FMT "pci-resume: ioc-state=0x%x,doorbell=0x%x\n",
2138 ioc->name, (mpt_GetIocState(ioc, 1) >> MPI_IOC_STATE_SHIFT),
2139 CHIPREG_READ32(&ioc->chip->Doorbell));
2140
2141 /*
2142 * Errata workaround for SAS pci express:
2143 * Upon returning to the D0 state, the contents of the doorbell will be
2144 * stale data, and this will incorrectly signal to the host driver that
2145 * the firmware is ready to process mpt commands. The workaround is
2146 * to issue a diagnostic reset.
2147 */
2148 if (ioc->bus_type == SAS && (pdev->device ==
2149 MPI_MANUFACTPAGE_DEVID_SAS1068E || pdev->device ==
2150 MPI_MANUFACTPAGE_DEVID_SAS1064E)) {
2151 if (KickStart(ioc, 1, CAN_SLEEP) < 0) {
2152 printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover\n",
2153 ioc->name);
2154 goto out;
2155 }
2156 }
2157
2158 /* bring ioc to operational state */
2159 printk(MYIOC_s_INFO_FMT "Sending mpt_do_ioc_recovery\n", ioc->name);
2160 recovery_state = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP,
2161 CAN_SLEEP);
2162 if (recovery_state != 0)
2163 printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover, "
2164 "error:[%x]\n", ioc->name, recovery_state);
2165 else
2166 printk(MYIOC_s_INFO_FMT
2167 "pci-resume: success\n", ioc->name);
2168 out:
2169 return 0;
2170
2171}
2172#endif
2173
2174static int
2175mpt_signal_reset(u8 index, MPT_ADAPTER *ioc, int reset_phase)
2176{
2177 if ((MptDriverClass[index] == MPTSPI_DRIVER &&
2178 ioc->bus_type != SPI) ||
2179 (MptDriverClass[index] == MPTFC_DRIVER &&
2180 ioc->bus_type != FC) ||
2181 (MptDriverClass[index] == MPTSAS_DRIVER &&
2182 ioc->bus_type != SAS))
2183 /* make sure we only call the relevant reset handler
2184 * for the bus */
2185 return 0;
2186 return (MptResetHandlers[index])(ioc, reset_phase);
2187}
2188
2189/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2190/**
2191 * mpt_do_ioc_recovery - Initialize or recover MPT adapter.
2192 * @ioc: Pointer to MPT adapter structure
2193 * @reason: Event word / reason
2194 * @sleepFlag: Use schedule if CAN_SLEEP else use udelay.
2195 *
2196 * This routine performs all the steps necessary to bring the IOC
2197 * to a OPERATIONAL state.
2198 *
2199 * This routine also pre-fetches the LAN MAC address of a Fibre Channel
2200 * MPT adapter.
2201 *
2202 * Returns:
2203 * 0 for success
2204 * -1 if failed to get board READY
2205 * -2 if READY but IOCFacts Failed
2206 * -3 if READY but PrimeIOCFifos Failed
2207 * -4 if READY but IOCInit Failed
2208 * -5 if failed to enable_device and/or request_selected_regions
2209 * -6 if failed to upload firmware
2210 */
2211static int
2212mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag)
2213{
2214 int hard_reset_done = 0;
2215 int alt_ioc_ready = 0;
2216 int hard;
2217 int rc=0;
2218 int ii;
2219 int ret = 0;
2220 int reset_alt_ioc_active = 0;
2221 int irq_allocated = 0;
2222 u8 *a;
2223
2224 printk(MYIOC_s_INFO_FMT "Initiating %s\n", ioc->name,
2225 reason == MPT_HOSTEVENT_IOC_BRINGUP ? "bringup" : "recovery");
2226
2227 /* Disable reply interrupts (also blocks FreeQ) */
2228 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2229 ioc->active = 0;
2230
2231 if (ioc->alt_ioc) {
2232 if (ioc->alt_ioc->active ||
2233 reason == MPT_HOSTEVENT_IOC_RECOVER) {
2234 reset_alt_ioc_active = 1;
2235 /* Disable alt-IOC's reply interrupts
2236 * (and FreeQ) for a bit
2237 **/
2238 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask,
2239 0xFFFFFFFF);
2240 ioc->alt_ioc->active = 0;
2241 }
2242 }
2243
2244 hard = 1;
2245 if (reason == MPT_HOSTEVENT_IOC_BRINGUP)
2246 hard = 0;
2247
2248 if ((hard_reset_done = MakeIocReady(ioc, hard, sleepFlag)) < 0) {
2249 if (hard_reset_done == -4) {
2250 printk(MYIOC_s_WARN_FMT "Owned by PEER..skipping!\n",
2251 ioc->name);
2252
2253 if (reset_alt_ioc_active && ioc->alt_ioc) {
2254 /* (re)Enable alt-IOC! (reply interrupt, FreeQ) */
2255 dprintk(ioc, printk(MYIOC_s_INFO_FMT
2256 "alt_ioc reply irq re-enabled\n", ioc->alt_ioc->name));
2257 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, MPI_HIM_DIM);
2258 ioc->alt_ioc->active = 1;
2259 }
2260
2261 } else {
2262 printk(MYIOC_s_WARN_FMT
2263 "NOT READY WARNING!\n", ioc->name);
2264 }
2265 ret = -1;
2266 goto out;
2267 }
2268
2269 /* hard_reset_done = 0 if a soft reset was performed
2270 * and 1 if a hard reset was performed.
2271 */
2272 if (hard_reset_done && reset_alt_ioc_active && ioc->alt_ioc) {
2273 if ((rc = MakeIocReady(ioc->alt_ioc, 0, sleepFlag)) == 0)
2274 alt_ioc_ready = 1;
2275 else
2276 printk(MYIOC_s_WARN_FMT
2277 ": alt-ioc Not ready WARNING!\n",
2278 ioc->alt_ioc->name);
2279 }
2280
2281 for (ii=0; ii<5; ii++) {
2282 /* Get IOC facts! Allow 5 retries */
2283 if ((rc = GetIocFacts(ioc, sleepFlag, reason)) == 0)
2284 break;
2285 }
2286
2287
2288 if (ii == 5) {
2289 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2290 "Retry IocFacts failed rc=%x\n", ioc->name, rc));
2291 ret = -2;
2292 } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
2293 MptDisplayIocCapabilities(ioc);
2294 }
2295
2296 if (alt_ioc_ready) {
2297 if ((rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason)) != 0) {
2298 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2299 "Initial Alt IocFacts failed rc=%x\n",
2300 ioc->name, rc));
2301 /* Retry - alt IOC was initialized once
2302 */
2303 rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason);
2304 }
2305 if (rc) {
2306 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2307 "Retry Alt IocFacts failed rc=%x\n", ioc->name, rc));
2308 alt_ioc_ready = 0;
2309 reset_alt_ioc_active = 0;
2310 } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
2311 MptDisplayIocCapabilities(ioc->alt_ioc);
2312 }
2313 }
2314
2315 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP) &&
2316 (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)) {
2317 pci_release_selected_regions(ioc->pcidev, ioc->bars);
2318 ioc->bars = pci_select_bars(ioc->pcidev, IORESOURCE_MEM |
2319 IORESOURCE_IO);
2320 if (pci_enable_device(ioc->pcidev))
2321 return -5;
2322 if (pci_request_selected_regions(ioc->pcidev, ioc->bars,
2323 "mpt"))
2324 return -5;
2325 }
2326
2327 /*
2328 * Device is reset now. It must have de-asserted the interrupt line
2329 * (if it was asserted) and it should be safe to register for the
2330 * interrupt now.
2331 */
2332 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) {
2333 ioc->pci_irq = -1;
2334 if (ioc->pcidev->irq) {
2335 if (ioc->msi_enable && !pci_enable_msi(ioc->pcidev))
2336 printk(MYIOC_s_INFO_FMT "PCI-MSI enabled\n",
2337 ioc->name);
2338 else
2339 ioc->msi_enable = 0;
2340 rc = request_irq(ioc->pcidev->irq, mpt_interrupt,
2341 IRQF_SHARED, ioc->name, ioc);
2342 if (rc < 0) {
2343 printk(MYIOC_s_ERR_FMT "Unable to allocate "
2344 "interrupt %d!\n",
2345 ioc->name, ioc->pcidev->irq);
2346 if (ioc->msi_enable)
2347 pci_disable_msi(ioc->pcidev);
2348 ret = -EBUSY;
2349 goto out;
2350 }
2351 irq_allocated = 1;
2352 ioc->pci_irq = ioc->pcidev->irq;
2353 pci_set_master(ioc->pcidev); /* ?? */
2354 pci_set_drvdata(ioc->pcidev, ioc);
2355 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2356 "installed at interrupt %d\n", ioc->name,
2357 ioc->pcidev->irq));
2358 }
2359 }
2360
2361 /* Prime reply & request queues!
2362 * (mucho alloc's) Must be done prior to
2363 * init as upper addresses are needed for init.
2364 * If fails, continue with alt-ioc processing
2365 */
2366 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "PrimeIocFifos\n",
2367 ioc->name));
2368 if ((ret == 0) && ((rc = PrimeIocFifos(ioc)) != 0))
2369 ret = -3;
2370
2371 /* May need to check/upload firmware & data here!
2372 * If fails, continue with alt-ioc processing
2373 */
2374 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "SendIocInit\n",
2375 ioc->name));
2376 if ((ret == 0) && ((rc = SendIocInit(ioc, sleepFlag)) != 0))
2377 ret = -4;
2378// NEW!
2379 if (alt_ioc_ready && ((rc = PrimeIocFifos(ioc->alt_ioc)) != 0)) {
2380 printk(MYIOC_s_WARN_FMT
2381 ": alt-ioc (%d) FIFO mgmt alloc WARNING!\n",
2382 ioc->alt_ioc->name, rc);
2383 alt_ioc_ready = 0;
2384 reset_alt_ioc_active = 0;
2385 }
2386
2387 if (alt_ioc_ready) {
2388 if ((rc = SendIocInit(ioc->alt_ioc, sleepFlag)) != 0) {
2389 alt_ioc_ready = 0;
2390 reset_alt_ioc_active = 0;
2391 printk(MYIOC_s_WARN_FMT
2392 ": alt-ioc: (%d) init failure WARNING!\n",
2393 ioc->alt_ioc->name, rc);
2394 }
2395 }
2396
2397 if (reason == MPT_HOSTEVENT_IOC_BRINGUP){
2398 if (ioc->upload_fw) {
2399 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2400 "firmware upload required!\n", ioc->name));
2401
2402 /* Controller is not operational, cannot do upload
2403 */
2404 if (ret == 0) {
2405 rc = mpt_do_upload(ioc, sleepFlag);
2406 if (rc == 0) {
2407 if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) {
2408 /*
2409 * Maintain only one pointer to FW memory
2410 * so there will not be two attempt to
2411 * downloadboot onboard dual function
2412 * chips (mpt_adapter_disable,
2413 * mpt_diag_reset)
2414 */
2415 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2416 "mpt_upload: alt_%s has cached_fw=%p \n",
2417 ioc->name, ioc->alt_ioc->name, ioc->alt_ioc->cached_fw));
2418 ioc->cached_fw = NULL;
2419 }
2420 } else {
2421 printk(MYIOC_s_WARN_FMT
2422 "firmware upload failure!\n", ioc->name);
2423 ret = -6;
2424 }
2425 }
2426 }
2427 }
2428
2429 /* Enable MPT base driver management of EventNotification
2430 * and EventAck handling.
2431 */
2432 if ((ret == 0) && (!ioc->facts.EventState)) {
2433 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2434 "SendEventNotification\n",
2435 ioc->name));
2436 ret = SendEventNotification(ioc, 1, sleepFlag); /* 1=Enable */
2437 }
2438
2439 if (ioc->alt_ioc && alt_ioc_ready && !ioc->alt_ioc->facts.EventState)
2440 rc = SendEventNotification(ioc->alt_ioc, 1, sleepFlag);
2441
2442 if (ret == 0) {
2443 /* Enable! (reply interrupt) */
2444 CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM);
2445 ioc->active = 1;
2446 }
2447 if (rc == 0) { /* alt ioc */
2448 if (reset_alt_ioc_active && ioc->alt_ioc) {
2449 /* (re)Enable alt-IOC! (reply interrupt) */
2450 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "alt-ioc"
2451 "reply irq re-enabled\n",
2452 ioc->alt_ioc->name));
2453 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask,
2454 MPI_HIM_DIM);
2455 ioc->alt_ioc->active = 1;
2456 }
2457 }
2458
2459
2460 /* Add additional "reason" check before call to GetLanConfigPages
2461 * (combined with GetIoUnitPage2 call). This prevents a somewhat
2462 * recursive scenario; GetLanConfigPages times out, timer expired
2463 * routine calls HardResetHandler, which calls into here again,
2464 * and we try GetLanConfigPages again...
2465 */
2466 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) {
2467
2468 /*
2469 * Initialize link list for inactive raid volumes.
2470 */
2471 mutex_init(&ioc->raid_data.inactive_list_mutex);
2472 INIT_LIST_HEAD(&ioc->raid_data.inactive_list);
2473
2474 switch (ioc->bus_type) {
2475
2476 case SAS:
2477 /* clear persistency table */
2478 if(ioc->facts.IOCExceptions &
2479 MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL) {
2480 ret = mptbase_sas_persist_operation(ioc,
2481 MPI_SAS_OP_CLEAR_NOT_PRESENT);
2482 if(ret != 0)
2483 goto out;
2484 }
2485
2486 /* Find IM volumes
2487 */
2488 mpt_findImVolumes(ioc);
2489
2490 /* Check, and possibly reset, the coalescing value
2491 */
2492 mpt_read_ioc_pg_1(ioc);
2493
2494 break;
2495
2496 case FC:
2497 if ((ioc->pfacts[0].ProtocolFlags &
2498 MPI_PORTFACTS_PROTOCOL_LAN) &&
2499 (ioc->lan_cnfg_page0.Header.PageLength == 0)) {
2500 /*
2501 * Pre-fetch the ports LAN MAC address!
2502 * (LANPage1_t stuff)
2503 */
2504 (void) GetLanConfigPages(ioc);
2505 a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
2506 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2507 "LanAddr = %02X:%02X:%02X"
2508 ":%02X:%02X:%02X\n",
2509 ioc->name, a[5], a[4],
2510 a[3], a[2], a[1], a[0]));
2511 }
2512 break;
2513
2514 case SPI:
2515 /* Get NVRAM and adapter maximums from SPP 0 and 2
2516 */
2517 mpt_GetScsiPortSettings(ioc, 0);
2518
2519 /* Get version and length of SDP 1
2520 */
2521 mpt_readScsiDevicePageHeaders(ioc, 0);
2522
2523 /* Find IM volumes
2524 */
2525 if (ioc->facts.MsgVersion >= MPI_VERSION_01_02)
2526 mpt_findImVolumes(ioc);
2527
2528 /* Check, and possibly reset, the coalescing value
2529 */
2530 mpt_read_ioc_pg_1(ioc);
2531
2532 mpt_read_ioc_pg_4(ioc);
2533
2534 break;
2535 }
2536
2537 GetIoUnitPage2(ioc);
2538 mpt_get_manufacturing_pg_0(ioc);
2539 }
2540
2541 out:
2542 if ((ret != 0) && irq_allocated) {
2543 free_irq(ioc->pci_irq, ioc);
2544 if (ioc->msi_enable)
2545 pci_disable_msi(ioc->pcidev);
2546 }
2547 return ret;
2548}
2549
2550/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2551/**
2552 * mpt_detect_bound_ports - Search for matching PCI bus/dev_function
2553 * @ioc: Pointer to MPT adapter structure
2554 * @pdev: Pointer to (struct pci_dev) structure
2555 *
2556 * Search for PCI bus/dev_function which matches
2557 * PCI bus/dev_function (+/-1) for newly discovered 929,
2558 * 929X, 1030 or 1035.
2559 *
2560 * If match on PCI dev_function +/-1 is found, bind the two MPT adapters
2561 * using alt_ioc pointer fields in their %MPT_ADAPTER structures.
2562 */
2563static void
2564mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev)
2565{
2566 struct pci_dev *peer=NULL;
2567 unsigned int slot = PCI_SLOT(pdev->devfn);
2568 unsigned int func = PCI_FUNC(pdev->devfn);
2569 MPT_ADAPTER *ioc_srch;
2570
2571 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "PCI device %s devfn=%x/%x,"
2572 " searching for devfn match on %x or %x\n",
2573 ioc->name, pci_name(pdev), pdev->bus->number,
2574 pdev->devfn, func-1, func+1));
2575
2576 peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func-1));
2577 if (!peer) {
2578 peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func+1));
2579 if (!peer)
2580 return;
2581 }
2582
2583 list_for_each_entry(ioc_srch, &ioc_list, list) {
2584 struct pci_dev *_pcidev = ioc_srch->pcidev;
2585 if (_pcidev == peer) {
2586 /* Paranoia checks */
2587 if (ioc->alt_ioc != NULL) {
2588 printk(MYIOC_s_WARN_FMT
2589 "Oops, already bound (%s <==> %s)!\n",
2590 ioc->name, ioc->name, ioc->alt_ioc->name);
2591 break;
2592 } else if (ioc_srch->alt_ioc != NULL) {
2593 printk(MYIOC_s_WARN_FMT
2594 "Oops, already bound (%s <==> %s)!\n",
2595 ioc_srch->name, ioc_srch->name,
2596 ioc_srch->alt_ioc->name);
2597 break;
2598 }
2599 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2600 "FOUND! binding %s <==> %s\n",
2601 ioc->name, ioc->name, ioc_srch->name));
2602 ioc_srch->alt_ioc = ioc;
2603 ioc->alt_ioc = ioc_srch;
2604 }
2605 }
2606 pci_dev_put(peer);
2607}
2608
2609/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2610/**
2611 * mpt_adapter_disable - Disable misbehaving MPT adapter.
2612 * @ioc: Pointer to MPT adapter structure
2613 */
2614static void
2615mpt_adapter_disable(MPT_ADAPTER *ioc)
2616{
2617 int sz;
2618 int ret;
2619
2620 if (ioc->cached_fw != NULL) {
2621 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2622 "%s: Pushing FW onto adapter\n", __func__, ioc->name));
2623 if ((ret = mpt_downloadboot(ioc, (MpiFwHeader_t *)
2624 ioc->cached_fw, CAN_SLEEP)) < 0) {
2625 printk(MYIOC_s_WARN_FMT
2626 ": firmware downloadboot failure (%d)!\n",
2627 ioc->name, ret);
2628 }
2629 }
2630
2631 /*
2632 * Put the controller into ready state (if its not already)
2633 */
2634 if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY) {
2635 if (!SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET,
2636 CAN_SLEEP)) {
2637 if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY)
2638 printk(MYIOC_s_ERR_FMT "%s: IOC msg unit "
2639 "reset failed to put ioc in ready state!\n",
2640 ioc->name, __func__);
2641 } else
2642 printk(MYIOC_s_ERR_FMT "%s: IOC msg unit reset "
2643 "failed!\n", ioc->name, __func__);
2644 }
2645
2646
2647 /* Disable adapter interrupts! */
2648 synchronize_irq(ioc->pcidev->irq);
2649 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2650 ioc->active = 0;
2651
2652 /* Clear any lingering interrupt */
2653 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
2654 CHIPREG_READ32(&ioc->chip->IntStatus);
2655
2656 if (ioc->alloc != NULL) {
2657 sz = ioc->alloc_sz;
2658 dexitprintk(ioc, printk(MYIOC_s_INFO_FMT "free @ %p, sz=%d bytes\n",
2659 ioc->name, ioc->alloc, ioc->alloc_sz));
2660 pci_free_consistent(ioc->pcidev, sz,
2661 ioc->alloc, ioc->alloc_dma);
2662 ioc->reply_frames = NULL;
2663 ioc->req_frames = NULL;
2664 ioc->alloc = NULL;
2665 ioc->alloc_total -= sz;
2666 }
2667
2668 if (ioc->sense_buf_pool != NULL) {
2669 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
2670 pci_free_consistent(ioc->pcidev, sz,
2671 ioc->sense_buf_pool, ioc->sense_buf_pool_dma);
2672 ioc->sense_buf_pool = NULL;
2673 ioc->alloc_total -= sz;
2674 }
2675
2676 if (ioc->events != NULL){
2677 sz = MPTCTL_EVENT_LOG_SIZE * sizeof(MPT_IOCTL_EVENTS);
2678 kfree(ioc->events);
2679 ioc->events = NULL;
2680 ioc->alloc_total -= sz;
2681 }
2682
2683 mpt_free_fw_memory(ioc);
2684
2685 kfree(ioc->spi_data.nvram);
2686 mpt_inactive_raid_list_free(ioc);
2687 kfree(ioc->raid_data.pIocPg2);
2688 kfree(ioc->raid_data.pIocPg3);
2689 ioc->spi_data.nvram = NULL;
2690 ioc->raid_data.pIocPg3 = NULL;
2691
2692 if (ioc->spi_data.pIocPg4 != NULL) {
2693 sz = ioc->spi_data.IocPg4Sz;
2694 pci_free_consistent(ioc->pcidev, sz,
2695 ioc->spi_data.pIocPg4,
2696 ioc->spi_data.IocPg4_dma);
2697 ioc->spi_data.pIocPg4 = NULL;
2698 ioc->alloc_total -= sz;
2699 }
2700
2701 if (ioc->ReqToChain != NULL) {
2702 kfree(ioc->ReqToChain);
2703 kfree(ioc->RequestNB);
2704 ioc->ReqToChain = NULL;
2705 }
2706
2707 kfree(ioc->ChainToChain);
2708 ioc->ChainToChain = NULL;
2709
2710 if (ioc->HostPageBuffer != NULL) {
2711 if((ret = mpt_host_page_access_control(ioc,
2712 MPI_DB_HPBAC_FREE_BUFFER, NO_SLEEP)) != 0) {
2713 printk(MYIOC_s_ERR_FMT
2714 ": %s: host page buffers free failed (%d)!\n",
2715 ioc->name, __func__, ret);
2716 }
2717 dexitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2718 "HostPageBuffer free @ %p, sz=%d bytes\n",
2719 ioc->name, ioc->HostPageBuffer,
2720 ioc->HostPageBuffer_sz));
2721 pci_free_consistent(ioc->pcidev, ioc->HostPageBuffer_sz,
2722 ioc->HostPageBuffer, ioc->HostPageBuffer_dma);
2723 ioc->HostPageBuffer = NULL;
2724 ioc->HostPageBuffer_sz = 0;
2725 ioc->alloc_total -= ioc->HostPageBuffer_sz;
2726 }
2727
2728 pci_set_drvdata(ioc->pcidev, NULL);
2729}
2730/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2731/**
2732 * mpt_adapter_dispose - Free all resources associated with an MPT adapter
2733 * @ioc: Pointer to MPT adapter structure
2734 *
2735 * This routine unregisters h/w resources and frees all alloc'd memory
2736 * associated with a MPT adapter structure.
2737 */
2738static void
2739mpt_adapter_dispose(MPT_ADAPTER *ioc)
2740{
2741 int sz_first, sz_last;
2742
2743 if (ioc == NULL)
2744 return;
2745
2746 sz_first = ioc->alloc_total;
2747
2748 mpt_adapter_disable(ioc);
2749
2750 if (ioc->pci_irq != -1) {
2751 free_irq(ioc->pci_irq, ioc);
2752 if (ioc->msi_enable)
2753 pci_disable_msi(ioc->pcidev);
2754 ioc->pci_irq = -1;
2755 }
2756
2757 if (ioc->memmap != NULL) {
2758 iounmap(ioc->memmap);
2759 ioc->memmap = NULL;
2760 }
2761
2762 pci_disable_device(ioc->pcidev);
2763 pci_release_selected_regions(ioc->pcidev, ioc->bars);
2764
2765#if defined(CONFIG_MTRR) && 0
2766 if (ioc->mtrr_reg > 0) {
2767 mtrr_del(ioc->mtrr_reg, 0, 0);
2768 dprintk(ioc, printk(MYIOC_s_INFO_FMT "MTRR region de-registered\n", ioc->name));
2769 }
2770#endif
2771
2772 /* Zap the adapter lookup ptr! */
2773 list_del(&ioc->list);
2774
2775 sz_last = ioc->alloc_total;
2776 dprintk(ioc, printk(MYIOC_s_INFO_FMT "free'd %d of %d bytes\n",
2777 ioc->name, sz_first-sz_last+(int)sizeof(*ioc), sz_first));
2778
2779 if (ioc->alt_ioc)
2780 ioc->alt_ioc->alt_ioc = NULL;
2781
2782 kfree(ioc);
2783}
2784
2785/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2786/**
2787 * MptDisplayIocCapabilities - Disply IOC's capabilities.
2788 * @ioc: Pointer to MPT adapter structure
2789 */
2790static void
2791MptDisplayIocCapabilities(MPT_ADAPTER *ioc)
2792{
2793 int i = 0;
2794
2795 printk(KERN_INFO "%s: ", ioc->name);
2796 if (ioc->prod_name)
2797 printk("%s: ", ioc->prod_name);
2798 printk("Capabilities={");
2799
2800 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR) {
2801 printk("Initiator");
2802 i++;
2803 }
2804
2805 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) {
2806 printk("%sTarget", i ? "," : "");
2807 i++;
2808 }
2809
2810 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) {
2811 printk("%sLAN", i ? "," : "");
2812 i++;
2813 }
2814
2815#if 0
2816 /*
2817 * This would probably evoke more questions than it's worth
2818 */
2819 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) {
2820 printk("%sLogBusAddr", i ? "," : "");
2821 i++;
2822 }
2823#endif
2824
2825 printk("}\n");
2826}
2827
2828/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2829/**
2830 * MakeIocReady - Get IOC to a READY state, using KickStart if needed.
2831 * @ioc: Pointer to MPT_ADAPTER structure
2832 * @force: Force hard KickStart of IOC
2833 * @sleepFlag: Specifies whether the process can sleep
2834 *
2835 * Returns:
2836 * 1 - DIAG reset and READY
2837 * 0 - READY initially OR soft reset and READY
2838 * -1 - Any failure on KickStart
2839 * -2 - Msg Unit Reset Failed
2840 * -3 - IO Unit Reset Failed
2841 * -4 - IOC owned by a PEER
2842 */
2843static int
2844MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag)
2845{
2846 u32 ioc_state;
2847 int statefault = 0;
2848 int cntdn;
2849 int hard_reset_done = 0;
2850 int r;
2851 int ii;
2852 int whoinit;
2853
2854 /* Get current [raw] IOC state */
2855 ioc_state = mpt_GetIocState(ioc, 0);
2856 dhsprintk(ioc, printk(MYIOC_s_INFO_FMT "MakeIocReady [raw] state=%08x\n", ioc->name, ioc_state));
2857
2858 /*
2859 * Check to see if IOC got left/stuck in doorbell handshake
2860 * grip of death. If so, hard reset the IOC.
2861 */
2862 if (ioc_state & MPI_DOORBELL_ACTIVE) {
2863 statefault = 1;
2864 printk(MYIOC_s_WARN_FMT "Unexpected doorbell active!\n",
2865 ioc->name);
2866 }
2867
2868 /* Is it already READY? */
2869 if (!statefault &&
2870 ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_READY)) {
2871 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2872 "IOC is in READY state\n", ioc->name));
2873 return 0;
2874 }
2875
2876 /*
2877 * Check to see if IOC is in FAULT state.
2878 */
2879 if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
2880 statefault = 2;
2881 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state!!!\n",
2882 ioc->name);
2883 printk(MYIOC_s_WARN_FMT " FAULT code = %04xh\n",
2884 ioc->name, ioc_state & MPI_DOORBELL_DATA_MASK);
2885 }
2886
2887 /*
2888 * Hmmm... Did it get left operational?
2889 */
2890 if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_OPERATIONAL) {
2891 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOC operational unexpected\n",
2892 ioc->name));
2893
2894 /* Check WhoInit.
2895 * If PCI Peer, exit.
2896 * Else, if no fault conditions are present, issue a MessageUnitReset
2897 * Else, fall through to KickStart case
2898 */
2899 whoinit = (ioc_state & MPI_DOORBELL_WHO_INIT_MASK) >> MPI_DOORBELL_WHO_INIT_SHIFT;
2900 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2901 "whoinit 0x%x statefault %d force %d\n",
2902 ioc->name, whoinit, statefault, force));
2903 if (whoinit == MPI_WHOINIT_PCI_PEER)
2904 return -4;
2905 else {
2906 if ((statefault == 0 ) && (force == 0)) {
2907 if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) == 0)
2908 return 0;
2909 }
2910 statefault = 3;
2911 }
2912 }
2913
2914 hard_reset_done = KickStart(ioc, statefault||force, sleepFlag);
2915 if (hard_reset_done < 0)
2916 return -1;
2917
2918 /*
2919 * Loop here waiting for IOC to come READY.
2920 */
2921 ii = 0;
2922 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 5; /* 5 seconds */
2923
2924 while ((ioc_state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) {
2925 if (ioc_state == MPI_IOC_STATE_OPERATIONAL) {
2926 /*
2927 * BIOS or previous driver load left IOC in OP state.
2928 * Reset messaging FIFOs.
2929 */
2930 if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) != 0) {
2931 printk(MYIOC_s_ERR_FMT "IOC msg unit reset failed!\n", ioc->name);
2932 return -2;
2933 }
2934 } else if (ioc_state == MPI_IOC_STATE_RESET) {
2935 /*
2936 * Something is wrong. Try to get IOC back
2937 * to a known state.
2938 */
2939 if ((r = SendIocReset(ioc, MPI_FUNCTION_IO_UNIT_RESET, sleepFlag)) != 0) {
2940 printk(MYIOC_s_ERR_FMT "IO unit reset failed!\n", ioc->name);
2941 return -3;
2942 }
2943 }
2944
2945 ii++; cntdn--;
2946 if (!cntdn) {
2947 printk(MYIOC_s_ERR_FMT
2948 "Wait IOC_READY state (0x%x) timeout(%d)!\n",
2949 ioc->name, ioc_state, (int)((ii+5)/HZ));
2950 return -ETIME;
2951 }
2952
2953 if (sleepFlag == CAN_SLEEP) {
2954 msleep(1);
2955 } else {
2956 mdelay (1); /* 1 msec delay */
2957 }
2958
2959 }
2960
2961 if (statefault < 3) {
2962 printk(MYIOC_s_INFO_FMT "Recovered from %s\n", ioc->name,
2963 statefault == 1 ? "stuck handshake" : "IOC FAULT");
2964 }
2965
2966 return hard_reset_done;
2967}
2968
2969/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2970/**
2971 * mpt_GetIocState - Get the current state of a MPT adapter.
2972 * @ioc: Pointer to MPT_ADAPTER structure
2973 * @cooked: Request raw or cooked IOC state
2974 *
2975 * Returns all IOC Doorbell register bits if cooked==0, else just the
2976 * Doorbell bits in MPI_IOC_STATE_MASK.
2977 */
2978u32
2979mpt_GetIocState(MPT_ADAPTER *ioc, int cooked)
2980{
2981 u32 s, sc;
2982
2983 /* Get! */
2984 s = CHIPREG_READ32(&ioc->chip->Doorbell);
2985 sc = s & MPI_IOC_STATE_MASK;
2986
2987 /* Save! */
2988 ioc->last_state = sc;
2989
2990 return cooked ? sc : s;
2991}
2992
2993/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2994/**
2995 * GetIocFacts - Send IOCFacts request to MPT adapter.
2996 * @ioc: Pointer to MPT_ADAPTER structure
2997 * @sleepFlag: Specifies whether the process can sleep
2998 * @reason: If recovery, only update facts.
2999 *
3000 * Returns 0 for success, non-zero for failure.
3001 */
3002static int
3003GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason)
3004{
3005 IOCFacts_t get_facts;
3006 IOCFactsReply_t *facts;
3007 int r;
3008 int req_sz;
3009 int reply_sz;
3010 int sz;
3011 u32 status, vv;
3012 u8 shiftFactor=1;
3013
3014 /* IOC *must* NOT be in RESET state! */
3015 if (ioc->last_state == MPI_IOC_STATE_RESET) {
3016 printk(KERN_ERR MYNAM
3017 ": ERROR - Can't get IOCFacts, %s NOT READY! (%08x)\n",
3018 ioc->name, ioc->last_state);
3019 return -44;
3020 }
3021
3022 facts = &ioc->facts;
3023
3024 /* Destination (reply area)... */
3025 reply_sz = sizeof(*facts);
3026 memset(facts, 0, reply_sz);
3027
3028 /* Request area (get_facts on the stack right now!) */
3029 req_sz = sizeof(get_facts);
3030 memset(&get_facts, 0, req_sz);
3031
3032 get_facts.Function = MPI_FUNCTION_IOC_FACTS;
3033 /* Assert: All other get_facts fields are zero! */
3034
3035 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3036 "Sending get IocFacts request req_sz=%d reply_sz=%d\n",
3037 ioc->name, req_sz, reply_sz));
3038
3039 /* No non-zero fields in the get_facts request are greater than
3040 * 1 byte in size, so we can just fire it off as is.
3041 */
3042 r = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_facts,
3043 reply_sz, (u16*)facts, 5 /*seconds*/, sleepFlag);
3044 if (r != 0)
3045 return r;
3046
3047 /*
3048 * Now byte swap (GRRR) the necessary fields before any further
3049 * inspection of reply contents.
3050 *
3051 * But need to do some sanity checks on MsgLength (byte) field
3052 * to make sure we don't zero IOC's req_sz!
3053 */
3054 /* Did we get a valid reply? */
3055 if (facts->MsgLength > offsetof(IOCFactsReply_t, RequestFrameSize)/sizeof(u32)) {
3056 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
3057 /*
3058 * If not been here, done that, save off first WhoInit value
3059 */
3060 if (ioc->FirstWhoInit == WHOINIT_UNKNOWN)
3061 ioc->FirstWhoInit = facts->WhoInit;
3062 }
3063
3064 facts->MsgVersion = le16_to_cpu(facts->MsgVersion);
3065 facts->MsgContext = le32_to_cpu(facts->MsgContext);
3066 facts->IOCExceptions = le16_to_cpu(facts->IOCExceptions);
3067 facts->IOCStatus = le16_to_cpu(facts->IOCStatus);
3068 facts->IOCLogInfo = le32_to_cpu(facts->IOCLogInfo);
3069 status = le16_to_cpu(facts->IOCStatus) & MPI_IOCSTATUS_MASK;
3070 /* CHECKME! IOCStatus, IOCLogInfo */
3071
3072 facts->ReplyQueueDepth = le16_to_cpu(facts->ReplyQueueDepth);
3073 facts->RequestFrameSize = le16_to_cpu(facts->RequestFrameSize);
3074
3075 /*
3076 * FC f/w version changed between 1.1 and 1.2
3077 * Old: u16{Major(4),Minor(4),SubMinor(8)}
3078 * New: u32{Major(8),Minor(8),Unit(8),Dev(8)}
3079 */
3080 if (facts->MsgVersion < MPI_VERSION_01_02) {
3081 /*
3082 * Handle old FC f/w style, convert to new...
3083 */
3084 u16 oldv = le16_to_cpu(facts->Reserved_0101_FWVersion);
3085 facts->FWVersion.Word =
3086 ((oldv<<12) & 0xFF000000) |
3087 ((oldv<<8) & 0x000FFF00);
3088 } else
3089 facts->FWVersion.Word = le32_to_cpu(facts->FWVersion.Word);
3090
3091 facts->ProductID = le16_to_cpu(facts->ProductID);
3092
3093 if ((ioc->facts.ProductID & MPI_FW_HEADER_PID_PROD_MASK)
3094 > MPI_FW_HEADER_PID_PROD_TARGET_SCSI)
3095 ioc->ir_firmware = 1;
3096
3097 facts->CurrentHostMfaHighAddr =
3098 le32_to_cpu(facts->CurrentHostMfaHighAddr);
3099 facts->GlobalCredits = le16_to_cpu(facts->GlobalCredits);
3100 facts->CurrentSenseBufferHighAddr =
3101 le32_to_cpu(facts->CurrentSenseBufferHighAddr);
3102 facts->CurReplyFrameSize =
3103 le16_to_cpu(facts->CurReplyFrameSize);
3104 facts->IOCCapabilities = le32_to_cpu(facts->IOCCapabilities);
3105
3106 /*
3107 * Handle NEW (!) IOCFactsReply fields in MPI-1.01.xx
3108 * Older MPI-1.00.xx struct had 13 dwords, and enlarged
3109 * to 14 in MPI-1.01.0x.
3110 */
3111 if (facts->MsgLength >= (offsetof(IOCFactsReply_t,FWImageSize) + 7)/4 &&
3112 facts->MsgVersion > MPI_VERSION_01_00) {
3113 facts->FWImageSize = le32_to_cpu(facts->FWImageSize);
3114 }
3115
3116 sz = facts->FWImageSize;
3117 if ( sz & 0x01 )
3118 sz += 1;
3119 if ( sz & 0x02 )
3120 sz += 2;
3121 facts->FWImageSize = sz;
3122
3123 if (!facts->RequestFrameSize) {
3124 /* Something is wrong! */
3125 printk(MYIOC_s_ERR_FMT "IOC reported invalid 0 request size!\n",
3126 ioc->name);
3127 return -55;
3128 }
3129
3130 r = sz = facts->BlockSize;
3131 vv = ((63 / (sz * 4)) + 1) & 0x03;
3132 ioc->NB_for_64_byte_frame = vv;
3133 while ( sz )
3134 {
3135 shiftFactor++;
3136 sz = sz >> 1;
3137 }
3138 ioc->NBShiftFactor = shiftFactor;
3139 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3140 "NB_for_64_byte_frame=%x NBShiftFactor=%x BlockSize=%x\n",
3141 ioc->name, vv, shiftFactor, r));
3142
3143 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
3144 /*
3145 * Set values for this IOC's request & reply frame sizes,
3146 * and request & reply queue depths...
3147 */
3148 ioc->req_sz = min(MPT_DEFAULT_FRAME_SIZE, facts->RequestFrameSize * 4);
3149 ioc->req_depth = min_t(int, MPT_MAX_REQ_DEPTH, facts->GlobalCredits);
3150 ioc->reply_sz = MPT_REPLY_FRAME_SIZE;
3151 ioc->reply_depth = min_t(int, MPT_DEFAULT_REPLY_DEPTH, facts->ReplyQueueDepth);
3152
3153 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "reply_sz=%3d, reply_depth=%4d\n",
3154 ioc->name, ioc->reply_sz, ioc->reply_depth));
3155 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "req_sz =%3d, req_depth =%4d\n",
3156 ioc->name, ioc->req_sz, ioc->req_depth));
3157
3158 /* Get port facts! */
3159 if ( (r = GetPortFacts(ioc, 0, sleepFlag)) != 0 )
3160 return r;
3161 }
3162 } else {
3163 printk(MYIOC_s_ERR_FMT
3164 "Invalid IOC facts reply, msgLength=%d offsetof=%zd!\n",
3165 ioc->name, facts->MsgLength, (offsetof(IOCFactsReply_t,
3166 RequestFrameSize)/sizeof(u32)));
3167 return -66;
3168 }
3169
3170 return 0;
3171}
3172
3173/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3174/**
3175 * GetPortFacts - Send PortFacts request to MPT adapter.
3176 * @ioc: Pointer to MPT_ADAPTER structure
3177 * @portnum: Port number
3178 * @sleepFlag: Specifies whether the process can sleep
3179 *
3180 * Returns 0 for success, non-zero for failure.
3181 */
3182static int
3183GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag)
3184{
3185 PortFacts_t get_pfacts;
3186 PortFactsReply_t *pfacts;
3187 int ii;
3188 int req_sz;
3189 int reply_sz;
3190 int max_id;
3191
3192 /* IOC *must* NOT be in RESET state! */
3193 if (ioc->last_state == MPI_IOC_STATE_RESET) {
3194 printk(MYIOC_s_ERR_FMT "Can't get PortFacts NOT READY! (%08x)\n",
3195 ioc->name, ioc->last_state );
3196 return -4;
3197 }
3198
3199 pfacts = &ioc->pfacts[portnum];
3200
3201 /* Destination (reply area)... */
3202 reply_sz = sizeof(*pfacts);
3203 memset(pfacts, 0, reply_sz);
3204
3205 /* Request area (get_pfacts on the stack right now!) */
3206 req_sz = sizeof(get_pfacts);
3207 memset(&get_pfacts, 0, req_sz);
3208
3209 get_pfacts.Function = MPI_FUNCTION_PORT_FACTS;
3210 get_pfacts.PortNumber = portnum;
3211 /* Assert: All other get_pfacts fields are zero! */
3212
3213 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending get PortFacts(%d) request\n",
3214 ioc->name, portnum));
3215
3216 /* No non-zero fields in the get_pfacts request are greater than
3217 * 1 byte in size, so we can just fire it off as is.
3218 */
3219 ii = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_pfacts,
3220 reply_sz, (u16*)pfacts, 5 /*seconds*/, sleepFlag);
3221 if (ii != 0)
3222 return ii;
3223
3224 /* Did we get a valid reply? */
3225
3226 /* Now byte swap the necessary fields in the response. */
3227 pfacts->MsgContext = le32_to_cpu(pfacts->MsgContext);
3228 pfacts->IOCStatus = le16_to_cpu(pfacts->IOCStatus);
3229 pfacts->IOCLogInfo = le32_to_cpu(pfacts->IOCLogInfo);
3230 pfacts->MaxDevices = le16_to_cpu(pfacts->MaxDevices);
3231 pfacts->PortSCSIID = le16_to_cpu(pfacts->PortSCSIID);
3232 pfacts->ProtocolFlags = le16_to_cpu(pfacts->ProtocolFlags);
3233 pfacts->MaxPostedCmdBuffers = le16_to_cpu(pfacts->MaxPostedCmdBuffers);
3234 pfacts->MaxPersistentIDs = le16_to_cpu(pfacts->MaxPersistentIDs);
3235 pfacts->MaxLanBuckets = le16_to_cpu(pfacts->MaxLanBuckets);
3236
3237 max_id = (ioc->bus_type == SAS) ? pfacts->PortSCSIID :
3238 pfacts->MaxDevices;
3239 ioc->devices_per_bus = (max_id > 255) ? 256 : max_id;
3240 ioc->number_of_buses = (ioc->devices_per_bus < 256) ? 1 : max_id/256;
3241
3242 /*
3243 * Place all the devices on channels
3244 *
3245 * (for debuging)
3246 */
3247 if (mpt_channel_mapping) {
3248 ioc->devices_per_bus = 1;
3249 ioc->number_of_buses = (max_id > 255) ? 255 : max_id;
3250 }
3251
3252 return 0;
3253}
3254
3255/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3256/**
3257 * SendIocInit - Send IOCInit request to MPT adapter.
3258 * @ioc: Pointer to MPT_ADAPTER structure
3259 * @sleepFlag: Specifies whether the process can sleep
3260 *
3261 * Send IOCInit followed by PortEnable to bring IOC to OPERATIONAL state.
3262 *
3263 * Returns 0 for success, non-zero for failure.
3264 */
3265static int
3266SendIocInit(MPT_ADAPTER *ioc, int sleepFlag)
3267{
3268 IOCInit_t ioc_init;
3269 MPIDefaultReply_t init_reply;
3270 u32 state;
3271 int r;
3272 int count;
3273 int cntdn;
3274
3275 memset(&ioc_init, 0, sizeof(ioc_init));
3276 memset(&init_reply, 0, sizeof(init_reply));
3277
3278 ioc_init.WhoInit = MPI_WHOINIT_HOST_DRIVER;
3279 ioc_init.Function = MPI_FUNCTION_IOC_INIT;
3280
3281 /* If we are in a recovery mode and we uploaded the FW image,
3282 * then this pointer is not NULL. Skip the upload a second time.
3283 * Set this flag if cached_fw set for either IOC.
3284 */
3285 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)
3286 ioc->upload_fw = 1;
3287 else
3288 ioc->upload_fw = 0;
3289 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "upload_fw %d facts.Flags=%x\n",
3290 ioc->name, ioc->upload_fw, ioc->facts.Flags));
3291
3292 ioc_init.MaxDevices = (U8)ioc->devices_per_bus;
3293 ioc_init.MaxBuses = (U8)ioc->number_of_buses;
3294
3295 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "facts.MsgVersion=%x\n",
3296 ioc->name, ioc->facts.MsgVersion));
3297 if (ioc->facts.MsgVersion >= MPI_VERSION_01_05) {
3298 // set MsgVersion and HeaderVersion host driver was built with
3299 ioc_init.MsgVersion = cpu_to_le16(MPI_VERSION);
3300 ioc_init.HeaderVersion = cpu_to_le16(MPI_HEADER_VERSION);
3301
3302 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT) {
3303 ioc_init.HostPageBufferSGE = ioc->facts.HostPageBufferSGE;
3304 } else if(mpt_host_page_alloc(ioc, &ioc_init))
3305 return -99;
3306 }
3307 ioc_init.ReplyFrameSize = cpu_to_le16(ioc->reply_sz); /* in BYTES */
3308
3309 if (ioc->sg_addr_size == sizeof(u64)) {
3310 /* Save the upper 32-bits of the request
3311 * (reply) and sense buffers.
3312 */
3313 ioc_init.HostMfaHighAddr = cpu_to_le32((u32)((u64)ioc->alloc_dma >> 32));
3314 ioc_init.SenseBufferHighAddr = cpu_to_le32((u32)((u64)ioc->sense_buf_pool_dma >> 32));
3315 } else {
3316 /* Force 32-bit addressing */
3317 ioc_init.HostMfaHighAddr = cpu_to_le32(0);
3318 ioc_init.SenseBufferHighAddr = cpu_to_le32(0);
3319 }
3320
3321 ioc->facts.CurrentHostMfaHighAddr = ioc_init.HostMfaHighAddr;
3322 ioc->facts.CurrentSenseBufferHighAddr = ioc_init.SenseBufferHighAddr;
3323 ioc->facts.MaxDevices = ioc_init.MaxDevices;
3324 ioc->facts.MaxBuses = ioc_init.MaxBuses;
3325
3326 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOCInit (req @ %p)\n",
3327 ioc->name, &ioc_init));
3328
3329 r = mpt_handshake_req_reply_wait(ioc, sizeof(IOCInit_t), (u32*)&ioc_init,
3330 sizeof(MPIDefaultReply_t), (u16*)&init_reply, 10 /*seconds*/, sleepFlag);
3331 if (r != 0) {
3332 printk(MYIOC_s_ERR_FMT "Sending IOCInit failed(%d)!\n",ioc->name, r);
3333 return r;
3334 }
3335
3336 /* No need to byte swap the multibyte fields in the reply
3337 * since we don't even look at its contents.
3338 */
3339
3340 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending PortEnable (req @ %p)\n",
3341 ioc->name, &ioc_init));
3342
3343 if ((r = SendPortEnable(ioc, 0, sleepFlag)) != 0) {
3344 printk(MYIOC_s_ERR_FMT "Sending PortEnable failed(%d)!\n",ioc->name, r);
3345 return r;
3346 }
3347
3348 /* YIKES! SUPER IMPORTANT!!!
3349 * Poll IocState until _OPERATIONAL while IOC is doing
3350 * LoopInit and TargetDiscovery!
3351 */
3352 count = 0;
3353 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 60; /* 60 seconds */
3354 state = mpt_GetIocState(ioc, 1);
3355 while (state != MPI_IOC_STATE_OPERATIONAL && --cntdn) {
3356 if (sleepFlag == CAN_SLEEP) {
3357 msleep(1);
3358 } else {
3359 mdelay(1);
3360 }
3361
3362 if (!cntdn) {
3363 printk(MYIOC_s_ERR_FMT "Wait IOC_OP state timeout(%d)!\n",
3364 ioc->name, (int)((count+5)/HZ));
3365 return -9;
3366 }
3367
3368 state = mpt_GetIocState(ioc, 1);
3369 count++;
3370 }
3371 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wait IOC_OPERATIONAL state (cnt=%d)\n",
3372 ioc->name, count));
3373
3374 ioc->aen_event_read_flag=0;
3375 return r;
3376}
3377
3378/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3379/**
3380 * SendPortEnable - Send PortEnable request to MPT adapter port.
3381 * @ioc: Pointer to MPT_ADAPTER structure
3382 * @portnum: Port number to enable
3383 * @sleepFlag: Specifies whether the process can sleep
3384 *
3385 * Send PortEnable to bring IOC to OPERATIONAL state.
3386 *
3387 * Returns 0 for success, non-zero for failure.
3388 */
3389static int
3390SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag)
3391{
3392 PortEnable_t port_enable;
3393 MPIDefaultReply_t reply_buf;
3394 int rc;
3395 int req_sz;
3396 int reply_sz;
3397
3398 /* Destination... */
3399 reply_sz = sizeof(MPIDefaultReply_t);
3400 memset(&reply_buf, 0, reply_sz);
3401
3402 req_sz = sizeof(PortEnable_t);
3403 memset(&port_enable, 0, req_sz);
3404
3405 port_enable.Function = MPI_FUNCTION_PORT_ENABLE;
3406 port_enable.PortNumber = portnum;
3407/* port_enable.ChainOffset = 0; */
3408/* port_enable.MsgFlags = 0; */
3409/* port_enable.MsgContext = 0; */
3410
3411 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending Port(%d)Enable (req @ %p)\n",
3412 ioc->name, portnum, &port_enable));
3413
3414 /* RAID FW may take a long time to enable
3415 */
3416 if (ioc->ir_firmware || ioc->bus_type == SAS) {
3417 rc = mpt_handshake_req_reply_wait(ioc, req_sz,
3418 (u32*)&port_enable, reply_sz, (u16*)&reply_buf,
3419 300 /*seconds*/, sleepFlag);
3420 } else {
3421 rc = mpt_handshake_req_reply_wait(ioc, req_sz,
3422 (u32*)&port_enable, reply_sz, (u16*)&reply_buf,
3423 30 /*seconds*/, sleepFlag);
3424 }
3425 return rc;
3426}
3427
3428/**
3429 * mpt_alloc_fw_memory - allocate firmware memory
3430 * @ioc: Pointer to MPT_ADAPTER structure
3431 * @size: total FW bytes
3432 *
3433 * If memory has already been allocated, the same (cached) value
3434 * is returned.
3435 *
3436 * Return 0 if successful, or non-zero for failure
3437 **/
3438int
3439mpt_alloc_fw_memory(MPT_ADAPTER *ioc, int size)
3440{
3441 int rc;
3442
3443 if (ioc->cached_fw) {
3444 rc = 0; /* use already allocated memory */
3445 goto out;
3446 }
3447 else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) {
3448 ioc->cached_fw = ioc->alt_ioc->cached_fw; /* use alt_ioc's memory */
3449 ioc->cached_fw_dma = ioc->alt_ioc->cached_fw_dma;
3450 rc = 0;
3451 goto out;
3452 }
3453 ioc->cached_fw = pci_alloc_consistent(ioc->pcidev, size, &ioc->cached_fw_dma);
3454 if (!ioc->cached_fw) {
3455 printk(MYIOC_s_ERR_FMT "Unable to allocate memory for the cached firmware image!\n",
3456 ioc->name);
3457 rc = -1;
3458 } else {
3459 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Image @ %p[%p], sz=%d[%x] bytes\n",
3460 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, size, size));
3461 ioc->alloc_total += size;
3462 rc = 0;
3463 }
3464 out:
3465 return rc;
3466}
3467
3468/**
3469 * mpt_free_fw_memory - free firmware memory
3470 * @ioc: Pointer to MPT_ADAPTER structure
3471 *
3472 * If alt_img is NULL, delete from ioc structure.
3473 * Else, delete a secondary image in same format.
3474 **/
3475void
3476mpt_free_fw_memory(MPT_ADAPTER *ioc)
3477{
3478 int sz;
3479
3480 if (!ioc->cached_fw)
3481 return;
3482
3483 sz = ioc->facts.FWImageSize;
3484 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "free_fw_memory: FW Image @ %p[%p], sz=%d[%x] bytes\n",
3485 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz));
3486 pci_free_consistent(ioc->pcidev, sz, ioc->cached_fw, ioc->cached_fw_dma);
3487 ioc->alloc_total -= sz;
3488 ioc->cached_fw = NULL;
3489}
3490
3491/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3492/**
3493 * mpt_do_upload - Construct and Send FWUpload request to MPT adapter port.
3494 * @ioc: Pointer to MPT_ADAPTER structure
3495 * @sleepFlag: Specifies whether the process can sleep
3496 *
3497 * Returns 0 for success, >0 for handshake failure
3498 * <0 for fw upload failure.
3499 *
3500 * Remark: If bound IOC and a successful FWUpload was performed
3501 * on the bound IOC, the second image is discarded
3502 * and memory is free'd. Both channels must upload to prevent
3503 * IOC from running in degraded mode.
3504 */
3505static int
3506mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag)
3507{
3508 u8 reply[sizeof(FWUploadReply_t)];
3509 FWUpload_t *prequest;
3510 FWUploadReply_t *preply;
3511 FWUploadTCSGE_t *ptcsge;
3512 u32 flagsLength;
3513 int ii, sz, reply_sz;
3514 int cmdStatus;
3515 int request_size;
3516 /* If the image size is 0, we are done.
3517 */
3518 if ((sz = ioc->facts.FWImageSize) == 0)
3519 return 0;
3520
3521 if (mpt_alloc_fw_memory(ioc, ioc->facts.FWImageSize) != 0)
3522 return -ENOMEM;
3523
3524 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": FW Image @ %p[%p], sz=%d[%x] bytes\n",
3525 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz));
3526
3527 prequest = (sleepFlag == NO_SLEEP) ? kzalloc(ioc->req_sz, GFP_ATOMIC) :
3528 kzalloc(ioc->req_sz, GFP_KERNEL);
3529 if (!prequest) {
3530 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed "
3531 "while allocating memory \n", ioc->name));
3532 mpt_free_fw_memory(ioc);
3533 return -ENOMEM;
3534 }
3535
3536 preply = (FWUploadReply_t *)&reply;
3537
3538 reply_sz = sizeof(reply);
3539 memset(preply, 0, reply_sz);
3540
3541 prequest->ImageType = MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM;
3542 prequest->Function = MPI_FUNCTION_FW_UPLOAD;
3543
3544 ptcsge = (FWUploadTCSGE_t *) &prequest->SGL;
3545 ptcsge->DetailsLength = 12;
3546 ptcsge->Flags = MPI_SGE_FLAGS_TRANSACTION_ELEMENT;
3547 ptcsge->ImageSize = cpu_to_le32(sz);
3548 ptcsge++;
3549
3550 flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ | sz;
3551 ioc->add_sge((char *)ptcsge, flagsLength, ioc->cached_fw_dma);
3552 request_size = offsetof(FWUpload_t, SGL) + sizeof(FWUploadTCSGE_t) +
3553 ioc->SGE_size;
3554 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending FW Upload "
3555 " (req @ %p) fw_size=%d mf_request_size=%d\n", ioc->name, prequest,
3556 ioc->facts.FWImageSize, request_size));
3557 DBG_DUMP_FW_REQUEST_FRAME(ioc, (u32 *)prequest);
3558
3559 ii = mpt_handshake_req_reply_wait(ioc, request_size, (u32 *)prequest,
3560 reply_sz, (u16 *)preply, 65 /*seconds*/, sleepFlag);
3561
3562 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Upload completed "
3563 "rc=%x \n", ioc->name, ii));
3564
3565 cmdStatus = -EFAULT;
3566 if (ii == 0) {
3567 /* Handshake transfer was complete and successful.
3568 * Check the Reply Frame.
3569 */
3570 int status;
3571 status = le16_to_cpu(preply->IOCStatus) &
3572 MPI_IOCSTATUS_MASK;
3573 if (status == MPI_IOCSTATUS_SUCCESS &&
3574 ioc->facts.FWImageSize ==
3575 le32_to_cpu(preply->ActualImageSize))
3576 cmdStatus = 0;
3577 }
3578 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT ": do_upload cmdStatus=%d \n",
3579 ioc->name, cmdStatus));
3580
3581
3582 if (cmdStatus) {
3583 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed, "
3584 "freeing image \n", ioc->name));
3585 mpt_free_fw_memory(ioc);
3586 }
3587 kfree(prequest);
3588
3589 return cmdStatus;
3590}
3591
3592/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3593/**
3594 * mpt_downloadboot - DownloadBoot code
3595 * @ioc: Pointer to MPT_ADAPTER structure
3596 * @pFwHeader: Pointer to firmware header info
3597 * @sleepFlag: Specifies whether the process can sleep
3598 *
3599 * FwDownloadBoot requires Programmed IO access.
3600 *
3601 * Returns 0 for success
3602 * -1 FW Image size is 0
3603 * -2 No valid cached_fw Pointer
3604 * <0 for fw upload failure.
3605 */
3606static int
3607mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag)
3608{
3609 MpiExtImageHeader_t *pExtImage;
3610 u32 fwSize;
3611 u32 diag0val;
3612 int count;
3613 u32 *ptrFw;
3614 u32 diagRwData;
3615 u32 nextImage;
3616 u32 load_addr;
3617 u32 ioc_state=0;
3618
3619 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot: fw size 0x%x (%d), FW Ptr %p\n",
3620 ioc->name, pFwHeader->ImageSize, pFwHeader->ImageSize, pFwHeader));
3621
3622 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
3623 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
3624 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
3625 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
3626 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
3627 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
3628
3629 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM));
3630
3631 /* wait 1 msec */
3632 if (sleepFlag == CAN_SLEEP) {
3633 msleep(1);
3634 } else {
3635 mdelay (1);
3636 }
3637
3638 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3639 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
3640
3641 for (count = 0; count < 30; count ++) {
3642 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3643 if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {
3644 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RESET_ADAPTER cleared, count=%d\n",
3645 ioc->name, count));
3646 break;
3647 }
3648 /* wait .1 sec */
3649 if (sleepFlag == CAN_SLEEP) {
3650 msleep (100);
3651 } else {
3652 mdelay (100);
3653 }
3654 }
3655
3656 if ( count == 30 ) {
3657 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot failed! "
3658 "Unable to get MPI_DIAG_DRWE mode, diag0val=%x\n",
3659 ioc->name, diag0val));
3660 return -3;
3661 }
3662
3663 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
3664 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
3665 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
3666 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
3667 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
3668 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
3669
3670 /* Set the DiagRwEn and Disable ARM bits */
3671 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_RW_ENABLE | MPI_DIAG_DISABLE_ARM));
3672
3673 fwSize = (pFwHeader->ImageSize + 3)/4;
3674 ptrFw = (u32 *) pFwHeader;
3675
3676 /* Write the LoadStartAddress to the DiagRw Address Register
3677 * using Programmed IO
3678 */
3679 if (ioc->errata_flag_1064)
3680 pci_enable_io_access(ioc->pcidev);
3681
3682 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress);
3683 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "LoadStart addr written 0x%x \n",
3684 ioc->name, pFwHeader->LoadStartAddress));
3685
3686 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write FW Image: 0x%x bytes @ %p\n",
3687 ioc->name, fwSize*4, ptrFw));
3688 while (fwSize--) {
3689 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
3690 }
3691
3692 nextImage = pFwHeader->NextImageHeaderOffset;
3693 while (nextImage) {
3694 pExtImage = (MpiExtImageHeader_t *) ((char *)pFwHeader + nextImage);
3695
3696 load_addr = pExtImage->LoadStartAddress;
3697
3698 fwSize = (pExtImage->ImageSize + 3) >> 2;
3699 ptrFw = (u32 *)pExtImage;
3700
3701 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write Ext Image: 0x%x (%d) bytes @ %p load_addr=%x\n",
3702 ioc->name, fwSize*4, fwSize*4, ptrFw, load_addr));
3703 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, load_addr);
3704
3705 while (fwSize--) {
3706 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
3707 }
3708 nextImage = pExtImage->NextImageHeaderOffset;
3709 }
3710
3711 /* Write the IopResetVectorRegAddr */
3712 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Addr=%x! \n", ioc->name, pFwHeader->IopResetRegAddr));
3713 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->IopResetRegAddr);
3714
3715 /* Write the IopResetVectorValue */
3716 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Value=%x! \n", ioc->name, pFwHeader->IopResetVectorValue));
3717 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, pFwHeader->IopResetVectorValue);
3718
3719 /* Clear the internal flash bad bit - autoincrementing register,
3720 * so must do two writes.
3721 */
3722 if (ioc->bus_type == SPI) {
3723 /*
3724 * 1030 and 1035 H/W errata, workaround to access
3725 * the ClearFlashBadSignatureBit
3726 */
3727 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
3728 diagRwData = CHIPREG_PIO_READ32(&ioc->pio_chip->DiagRwData);
3729 diagRwData |= 0x40000000;
3730 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
3731 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData);
3732
3733 } else /* if((ioc->bus_type == SAS) || (ioc->bus_type == FC)) */ {
3734 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3735 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val |
3736 MPI_DIAG_CLEAR_FLASH_BAD_SIG);
3737
3738 /* wait 1 msec */
3739 if (sleepFlag == CAN_SLEEP) {
3740 msleep (1);
3741 } else {
3742 mdelay (1);
3743 }
3744 }
3745
3746 if (ioc->errata_flag_1064)
3747 pci_disable_io_access(ioc->pcidev);
3748
3749 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3750 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot diag0val=%x, "
3751 "turning off PREVENT_IOC_BOOT, DISABLE_ARM, RW_ENABLE\n",
3752 ioc->name, diag0val));
3753 diag0val &= ~(MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM | MPI_DIAG_RW_ENABLE);
3754 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot now diag0val=%x\n",
3755 ioc->name, diag0val));
3756 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
3757
3758 /* Write 0xFF to reset the sequencer */
3759 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
3760
3761 if (ioc->bus_type == SAS) {
3762 ioc_state = mpt_GetIocState(ioc, 0);
3763 if ( (GetIocFacts(ioc, sleepFlag,
3764 MPT_HOSTEVENT_IOC_BRINGUP)) != 0 ) {
3765 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "GetIocFacts failed: IocState=%x\n",
3766 ioc->name, ioc_state));
3767 return -EFAULT;
3768 }
3769 }
3770
3771 for (count=0; count<HZ*20; count++) {
3772 if ((ioc_state = mpt_GetIocState(ioc, 0)) & MPI_IOC_STATE_READY) {
3773 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3774 "downloadboot successful! (count=%d) IocState=%x\n",
3775 ioc->name, count, ioc_state));
3776 if (ioc->bus_type == SAS) {
3777 return 0;
3778 }
3779 if ((SendIocInit(ioc, sleepFlag)) != 0) {
3780 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3781 "downloadboot: SendIocInit failed\n",
3782 ioc->name));
3783 return -EFAULT;
3784 }
3785 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3786 "downloadboot: SendIocInit successful\n",
3787 ioc->name));
3788 return 0;
3789 }
3790 if (sleepFlag == CAN_SLEEP) {
3791 msleep (10);
3792 } else {
3793 mdelay (10);
3794 }
3795 }
3796 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3797 "downloadboot failed! IocState=%x\n",ioc->name, ioc_state));
3798 return -EFAULT;
3799}
3800
3801/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3802/**
3803 * KickStart - Perform hard reset of MPT adapter.
3804 * @ioc: Pointer to MPT_ADAPTER structure
3805 * @force: Force hard reset
3806 * @sleepFlag: Specifies whether the process can sleep
3807 *
3808 * This routine places MPT adapter in diagnostic mode via the
3809 * WriteSequence register, and then performs a hard reset of adapter
3810 * via the Diagnostic register.
3811 *
3812 * Inputs: sleepflag - CAN_SLEEP (non-interrupt thread)
3813 * or NO_SLEEP (interrupt thread, use mdelay)
3814 * force - 1 if doorbell active, board fault state
3815 * board operational, IOC_RECOVERY or
3816 * IOC_BRINGUP and there is an alt_ioc.
3817 * 0 else
3818 *
3819 * Returns:
3820 * 1 - hard reset, READY
3821 * 0 - no reset due to History bit, READY
3822 * -1 - no reset due to History bit but not READY
3823 * OR reset but failed to come READY
3824 * -2 - no reset, could not enter DIAG mode
3825 * -3 - reset but bad FW bit
3826 */
3827static int
3828KickStart(MPT_ADAPTER *ioc, int force, int sleepFlag)
3829{
3830 int hard_reset_done = 0;
3831 u32 ioc_state=0;
3832 int cnt,cntdn;
3833
3834 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStarting!\n", ioc->name));
3835 if (ioc->bus_type == SPI) {
3836 /* Always issue a Msg Unit Reset first. This will clear some
3837 * SCSI bus hang conditions.
3838 */
3839 SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag);
3840
3841 if (sleepFlag == CAN_SLEEP) {
3842 msleep (1000);
3843 } else {
3844 mdelay (1000);
3845 }
3846 }
3847
3848 hard_reset_done = mpt_diag_reset(ioc, force, sleepFlag);
3849 if (hard_reset_done < 0)
3850 return hard_reset_done;
3851
3852 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset successful!\n",
3853 ioc->name));
3854
3855 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 2; /* 2 seconds */
3856 for (cnt=0; cnt<cntdn; cnt++) {
3857 ioc_state = mpt_GetIocState(ioc, 1);
3858 if ((ioc_state == MPI_IOC_STATE_READY) || (ioc_state == MPI_IOC_STATE_OPERATIONAL)) {
3859 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStart successful! (cnt=%d)\n",
3860 ioc->name, cnt));
3861 return hard_reset_done;
3862 }
3863 if (sleepFlag == CAN_SLEEP) {
3864 msleep (10);
3865 } else {
3866 mdelay (10);
3867 }
3868 }
3869
3870 dinitprintk(ioc, printk(MYIOC_s_ERR_FMT "Failed to come READY after reset! IocState=%x\n",
3871 ioc->name, mpt_GetIocState(ioc, 0)));
3872 return -1;
3873}
3874
3875/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3876/**
3877 * mpt_diag_reset - Perform hard reset of the adapter.
3878 * @ioc: Pointer to MPT_ADAPTER structure
3879 * @ignore: Set if to honor and clear to ignore
3880 * the reset history bit
3881 * @sleepFlag: CAN_SLEEP if called in a non-interrupt thread,
3882 * else set to NO_SLEEP (use mdelay instead)
3883 *
3884 * This routine places the adapter in diagnostic mode via the
3885 * WriteSequence register and then performs a hard reset of adapter
3886 * via the Diagnostic register. Adapter should be in ready state
3887 * upon successful completion.
3888 *
3889 * Returns: 1 hard reset successful
3890 * 0 no reset performed because reset history bit set
3891 * -2 enabling diagnostic mode failed
3892 * -3 diagnostic reset failed
3893 */
3894static int
3895mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag)
3896{
3897 u32 diag0val;
3898 u32 doorbell;
3899 int hard_reset_done = 0;
3900 int count = 0;
3901 u32 diag1val = 0;
3902 MpiFwHeader_t *cached_fw; /* Pointer to FW */
3903 u8 cb_idx;
3904
3905 /* Clear any existing interrupts */
3906 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
3907
3908 if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) {
3909
3910 if (!ignore)
3911 return 0;
3912
3913 drsprintk(ioc, printk(MYIOC_s_WARN_FMT "%s: Doorbell=%p; 1078 reset "
3914 "address=%p\n", ioc->name, __func__,
3915 &ioc->chip->Doorbell, &ioc->chip->Reset_1078));
3916 CHIPREG_WRITE32(&ioc->chip->Reset_1078, 0x07);
3917 if (sleepFlag == CAN_SLEEP)
3918 msleep(1);
3919 else
3920 mdelay(1);
3921
3922 /*
3923 * Call each currently registered protocol IOC reset handler
3924 * with pre-reset indication.
3925 * NOTE: If we're doing _IOC_BRINGUP, there can be no
3926 * MptResetHandlers[] registered yet.
3927 */
3928 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
3929 if (MptResetHandlers[cb_idx])
3930 (*(MptResetHandlers[cb_idx]))(ioc,
3931 MPT_IOC_PRE_RESET);
3932 }
3933
3934 for (count = 0; count < 60; count ++) {
3935 doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
3936 doorbell &= MPI_IOC_STATE_MASK;
3937
3938 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3939 "looking for READY STATE: doorbell=%x"
3940 " count=%d\n",
3941 ioc->name, doorbell, count));
3942
3943 if (doorbell == MPI_IOC_STATE_READY) {
3944 return 1;
3945 }
3946
3947 /* wait 1 sec */
3948 if (sleepFlag == CAN_SLEEP)
3949 msleep(1000);
3950 else
3951 mdelay(1000);
3952 }
3953 return -1;
3954 }
3955
3956 /* Use "Diagnostic reset" method! (only thing available!) */
3957 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3958
3959 if (ioc->debug_level & MPT_DEBUG) {
3960 if (ioc->alt_ioc)
3961 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
3962 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG1: diag0=%08x, diag1=%08x\n",
3963 ioc->name, diag0val, diag1val));
3964 }
3965
3966 /* Do the reset if we are told to ignore the reset history
3967 * or if the reset history is 0
3968 */
3969 if (ignore || !(diag0val & MPI_DIAG_RESET_HISTORY)) {
3970 while ((diag0val & MPI_DIAG_DRWE) == 0) {
3971 /* Write magic sequence to WriteSequence register
3972 * Loop until in diagnostic mode
3973 */
3974 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
3975 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
3976 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
3977 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
3978 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
3979 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
3980
3981 /* wait 100 msec */
3982 if (sleepFlag == CAN_SLEEP) {
3983 msleep (100);
3984 } else {
3985 mdelay (100);
3986 }
3987
3988 count++;
3989 if (count > 20) {
3990 printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n",
3991 ioc->name, diag0val);
3992 return -2;
3993
3994 }
3995
3996 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3997
3998 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wrote magic DiagWriteEn sequence (%x)\n",
3999 ioc->name, diag0val));
4000 }
4001
4002 if (ioc->debug_level & MPT_DEBUG) {
4003 if (ioc->alt_ioc)
4004 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4005 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG2: diag0=%08x, diag1=%08x\n",
4006 ioc->name, diag0val, diag1val));
4007 }
4008 /*
4009 * Disable the ARM (Bug fix)
4010 *
4011 */
4012 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_DISABLE_ARM);
4013 mdelay(1);
4014
4015 /*
4016 * Now hit the reset bit in the Diagnostic register
4017 * (THE BIG HAMMER!) (Clears DRWE bit).
4018 */
4019 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
4020 hard_reset_done = 1;
4021 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset performed\n",
4022 ioc->name));
4023
4024 /*
4025 * Call each currently registered protocol IOC reset handler
4026 * with pre-reset indication.
4027 * NOTE: If we're doing _IOC_BRINGUP, there can be no
4028 * MptResetHandlers[] registered yet.
4029 */
4030 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
4031 if (MptResetHandlers[cb_idx]) {
4032 mpt_signal_reset(cb_idx,
4033 ioc, MPT_IOC_PRE_RESET);
4034 if (ioc->alt_ioc) {
4035 mpt_signal_reset(cb_idx,
4036 ioc->alt_ioc, MPT_IOC_PRE_RESET);
4037 }
4038 }
4039 }
4040
4041 if (ioc->cached_fw)
4042 cached_fw = (MpiFwHeader_t *)ioc->cached_fw;
4043 else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw)
4044 cached_fw = (MpiFwHeader_t *)ioc->alt_ioc->cached_fw;
4045 else
4046 cached_fw = NULL;
4047 if (cached_fw) {
4048 /* If the DownloadBoot operation fails, the
4049 * IOC will be left unusable. This is a fatal error
4050 * case. _diag_reset will return < 0
4051 */
4052 for (count = 0; count < 30; count ++) {
4053 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4054 if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {
4055 break;
4056 }
4057
4058 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "cached_fw: diag0val=%x count=%d\n",
4059 ioc->name, diag0val, count));
4060 /* wait 1 sec */
4061 if (sleepFlag == CAN_SLEEP) {
4062 msleep (1000);
4063 } else {
4064 mdelay (1000);
4065 }
4066 }
4067 if ((count = mpt_downloadboot(ioc, cached_fw, sleepFlag)) < 0) {
4068 printk(MYIOC_s_WARN_FMT
4069 "firmware downloadboot failure (%d)!\n", ioc->name, count);
4070 }
4071
4072 } else {
4073 /* Wait for FW to reload and for board
4074 * to go to the READY state.
4075 * Maximum wait is 60 seconds.
4076 * If fail, no error will check again
4077 * with calling program.
4078 */
4079 for (count = 0; count < 60; count ++) {
4080 doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
4081 doorbell &= MPI_IOC_STATE_MASK;
4082
4083 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4084 "looking for READY STATE: doorbell=%x"
4085 " count=%d\n", ioc->name, doorbell, count));
4086
4087 if (doorbell == MPI_IOC_STATE_READY) {
4088 break;
4089 }
4090
4091 /* wait 1 sec */
4092 if (sleepFlag == CAN_SLEEP) {
4093 msleep (1000);
4094 } else {
4095 mdelay (1000);
4096 }
4097 }
4098
4099 if (doorbell != MPI_IOC_STATE_READY)
4100 printk(MYIOC_s_ERR_FMT "Failed to come READY "
4101 "after reset! IocState=%x", ioc->name,
4102 doorbell);
4103 }
4104 }
4105
4106 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4107 if (ioc->debug_level & MPT_DEBUG) {
4108 if (ioc->alt_ioc)
4109 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4110 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG3: diag0=%08x, diag1=%08x\n",
4111 ioc->name, diag0val, diag1val));
4112 }
4113
4114 /* Clear RESET_HISTORY bit! Place board in the
4115 * diagnostic mode to update the diag register.
4116 */
4117 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4118 count = 0;
4119 while ((diag0val & MPI_DIAG_DRWE) == 0) {
4120 /* Write magic sequence to WriteSequence register
4121 * Loop until in diagnostic mode
4122 */
4123 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
4124 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
4125 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
4126 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
4127 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
4128 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
4129
4130 /* wait 100 msec */
4131 if (sleepFlag == CAN_SLEEP) {
4132 msleep (100);
4133 } else {
4134 mdelay (100);
4135 }
4136
4137 count++;
4138 if (count > 20) {
4139 printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n",
4140 ioc->name, diag0val);
4141 break;
4142 }
4143 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4144 }
4145 diag0val &= ~MPI_DIAG_RESET_HISTORY;
4146 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
4147 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4148 if (diag0val & MPI_DIAG_RESET_HISTORY) {
4149 printk(MYIOC_s_WARN_FMT "ResetHistory bit failed to clear!\n",
4150 ioc->name);
4151 }
4152
4153 /* Disable Diagnostic Mode
4154 */
4155 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFFFFFFFF);
4156
4157 /* Check FW reload status flags.
4158 */
4159 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4160 if (diag0val & (MPI_DIAG_FLASH_BAD_SIG | MPI_DIAG_RESET_ADAPTER | MPI_DIAG_DISABLE_ARM)) {
4161 printk(MYIOC_s_ERR_FMT "Diagnostic reset FAILED! (%02xh)\n",
4162 ioc->name, diag0val);
4163 return -3;
4164 }
4165
4166 if (ioc->debug_level & MPT_DEBUG) {
4167 if (ioc->alt_ioc)
4168 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4169 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG4: diag0=%08x, diag1=%08x\n",
4170 ioc->name, diag0val, diag1val));
4171 }
4172
4173 /*
4174 * Reset flag that says we've enabled event notification
4175 */
4176 ioc->facts.EventState = 0;
4177
4178 if (ioc->alt_ioc)
4179 ioc->alt_ioc->facts.EventState = 0;
4180
4181 return hard_reset_done;
4182}
4183
4184/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4185/**
4186 * SendIocReset - Send IOCReset request to MPT adapter.
4187 * @ioc: Pointer to MPT_ADAPTER structure
4188 * @reset_type: reset type, expected values are
4189 * %MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET or %MPI_FUNCTION_IO_UNIT_RESET
4190 * @sleepFlag: Specifies whether the process can sleep
4191 *
4192 * Send IOCReset request to the MPT adapter.
4193 *
4194 * Returns 0 for success, non-zero for failure.
4195 */
4196static int
4197SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag)
4198{
4199 int r;
4200 u32 state;
4201 int cntdn, count;
4202
4203 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOC reset(0x%02x)!\n",
4204 ioc->name, reset_type));
4205 CHIPREG_WRITE32(&ioc->chip->Doorbell, reset_type<<MPI_DOORBELL_FUNCTION_SHIFT);
4206 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
4207 return r;
4208
4209 /* FW ACK'd request, wait for READY state
4210 */
4211 count = 0;
4212 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 15; /* 15 seconds */
4213
4214 while ((state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) {
4215 cntdn--;
4216 count++;
4217 if (!cntdn) {
4218 if (sleepFlag != CAN_SLEEP)
4219 count *= 10;
4220
4221 printk(MYIOC_s_ERR_FMT
4222 "Wait IOC_READY state (0x%x) timeout(%d)!\n",
4223 ioc->name, state, (int)((count+5)/HZ));
4224 return -ETIME;
4225 }
4226
4227 if (sleepFlag == CAN_SLEEP) {
4228 msleep(1);
4229 } else {
4230 mdelay (1); /* 1 msec delay */
4231 }
4232 }
4233
4234 /* TODO!
4235 * Cleanup all event stuff for this IOC; re-issue EventNotification
4236 * request if needed.
4237 */
4238 if (ioc->facts.Function)
4239 ioc->facts.EventState = 0;
4240
4241 return 0;
4242}
4243
4244/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4245/**
4246 * initChainBuffers - Allocate memory for and initialize chain buffers
4247 * @ioc: Pointer to MPT_ADAPTER structure
4248 *
4249 * Allocates memory for and initializes chain buffers,
4250 * chain buffer control arrays and spinlock.
4251 */
4252static int
4253initChainBuffers(MPT_ADAPTER *ioc)
4254{
4255 u8 *mem;
4256 int sz, ii, num_chain;
4257 int scale, num_sge, numSGE;
4258
4259 /* ReqToChain size must equal the req_depth
4260 * index = req_idx
4261 */
4262 if (ioc->ReqToChain == NULL) {
4263 sz = ioc->req_depth * sizeof(int);
4264 mem = kmalloc(sz, GFP_ATOMIC);
4265 if (mem == NULL)
4266 return -1;
4267
4268 ioc->ReqToChain = (int *) mem;
4269 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReqToChain alloc @ %p, sz=%d bytes\n",
4270 ioc->name, mem, sz));
4271 mem = kmalloc(sz, GFP_ATOMIC);
4272 if (mem == NULL)
4273 return -1;
4274
4275 ioc->RequestNB = (int *) mem;
4276 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestNB alloc @ %p, sz=%d bytes\n",
4277 ioc->name, mem, sz));
4278 }
4279 for (ii = 0; ii < ioc->req_depth; ii++) {
4280 ioc->ReqToChain[ii] = MPT_HOST_NO_CHAIN;
4281 }
4282
4283 /* ChainToChain size must equal the total number
4284 * of chain buffers to be allocated.
4285 * index = chain_idx
4286 *
4287 * Calculate the number of chain buffers needed(plus 1) per I/O
4288 * then multiply the maximum number of simultaneous cmds
4289 *
4290 * num_sge = num sge in request frame + last chain buffer
4291 * scale = num sge per chain buffer if no chain element
4292 */
4293 scale = ioc->req_sz / ioc->SGE_size;
4294 if (ioc->sg_addr_size == sizeof(u64))
4295 num_sge = scale + (ioc->req_sz - 60) / ioc->SGE_size;
4296 else
4297 num_sge = 1 + scale + (ioc->req_sz - 64) / ioc->SGE_size;
4298
4299 if (ioc->sg_addr_size == sizeof(u64)) {
4300 numSGE = (scale - 1) * (ioc->facts.MaxChainDepth-1) + scale +
4301 (ioc->req_sz - 60) / ioc->SGE_size;
4302 } else {
4303 numSGE = 1 + (scale - 1) * (ioc->facts.MaxChainDepth-1) +
4304 scale + (ioc->req_sz - 64) / ioc->SGE_size;
4305 }
4306 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "num_sge=%d numSGE=%d\n",
4307 ioc->name, num_sge, numSGE));
4308
4309 if (ioc->bus_type == FC) {
4310 if (numSGE > MPT_SCSI_FC_SG_DEPTH)
4311 numSGE = MPT_SCSI_FC_SG_DEPTH;
4312 } else {
4313 if (numSGE > MPT_SCSI_SG_DEPTH)
4314 numSGE = MPT_SCSI_SG_DEPTH;
4315 }
4316
4317 num_chain = 1;
4318 while (numSGE - num_sge > 0) {
4319 num_chain++;
4320 num_sge += (scale - 1);
4321 }
4322 num_chain++;
4323
4324 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Now numSGE=%d num_sge=%d num_chain=%d\n",
4325 ioc->name, numSGE, num_sge, num_chain));
4326
4327 if (ioc->bus_type == SPI)
4328 num_chain *= MPT_SCSI_CAN_QUEUE;
4329 else if (ioc->bus_type == SAS)
4330 num_chain *= MPT_SAS_CAN_QUEUE;
4331 else
4332 num_chain *= MPT_FC_CAN_QUEUE;
4333
4334 ioc->num_chain = num_chain;
4335
4336 sz = num_chain * sizeof(int);
4337 if (ioc->ChainToChain == NULL) {
4338 mem = kmalloc(sz, GFP_ATOMIC);
4339 if (mem == NULL)
4340 return -1;
4341
4342 ioc->ChainToChain = (int *) mem;
4343 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainToChain alloc @ %p, sz=%d bytes\n",
4344 ioc->name, mem, sz));
4345 } else {
4346 mem = (u8 *) ioc->ChainToChain;
4347 }
4348 memset(mem, 0xFF, sz);
4349 return num_chain;
4350}
4351
4352/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4353/**
4354 * PrimeIocFifos - Initialize IOC request and reply FIFOs.
4355 * @ioc: Pointer to MPT_ADAPTER structure
4356 *
4357 * This routine allocates memory for the MPT reply and request frame
4358 * pools (if necessary), and primes the IOC reply FIFO with
4359 * reply frames.
4360 *
4361 * Returns 0 for success, non-zero for failure.
4362 */
4363static int
4364PrimeIocFifos(MPT_ADAPTER *ioc)
4365{
4366 MPT_FRAME_HDR *mf;
4367 unsigned long flags;
4368 dma_addr_t alloc_dma;
4369 u8 *mem;
4370 int i, reply_sz, sz, total_size, num_chain;
4371 u64 dma_mask;
4372
4373 dma_mask = 0;
4374
4375 /* Prime reply FIFO... */
4376
4377 if (ioc->reply_frames == NULL) {
4378 if ( (num_chain = initChainBuffers(ioc)) < 0)
4379 return -1;
4380 /*
4381 * 1078 errata workaround for the 36GB limitation
4382 */
4383 if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078 &&
4384 ioc->dma_mask > DMA_BIT_MASK(35)) {
4385 if (!pci_set_dma_mask(ioc->pcidev, DMA_BIT_MASK(32))
4386 && !pci_set_consistent_dma_mask(ioc->pcidev,
4387 DMA_BIT_MASK(32))) {
4388 dma_mask = DMA_BIT_MASK(35);
4389 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4390 "setting 35 bit addressing for "
4391 "Request/Reply/Chain and Sense Buffers\n",
4392 ioc->name));
4393 } else {
4394 /*Reseting DMA mask to 64 bit*/
4395 pci_set_dma_mask(ioc->pcidev,
4396 DMA_BIT_MASK(64));
4397 pci_set_consistent_dma_mask(ioc->pcidev,
4398 DMA_BIT_MASK(64));
4399
4400 printk(MYIOC_s_ERR_FMT
4401 "failed setting 35 bit addressing for "
4402 "Request/Reply/Chain and Sense Buffers\n",
4403 ioc->name);
4404 return -1;
4405 }
4406 }
4407
4408 total_size = reply_sz = (ioc->reply_sz * ioc->reply_depth);
4409 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d bytes, ReplyDepth=%d\n",
4410 ioc->name, ioc->reply_sz, ioc->reply_depth));
4411 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d[%x] bytes\n",
4412 ioc->name, reply_sz, reply_sz));
4413
4414 sz = (ioc->req_sz * ioc->req_depth);
4415 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d bytes, RequestDepth=%d\n",
4416 ioc->name, ioc->req_sz, ioc->req_depth));
4417 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d[%x] bytes\n",
4418 ioc->name, sz, sz));
4419 total_size += sz;
4420
4421 sz = num_chain * ioc->req_sz; /* chain buffer pool size */
4422 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d bytes, ChainDepth=%d\n",
4423 ioc->name, ioc->req_sz, num_chain));
4424 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d[%x] bytes num_chain=%d\n",
4425 ioc->name, sz, sz, num_chain));
4426
4427 total_size += sz;
4428 mem = pci_alloc_consistent(ioc->pcidev, total_size, &alloc_dma);
4429 if (mem == NULL) {
4430 printk(MYIOC_s_ERR_FMT "Unable to allocate Reply, Request, Chain Buffers!\n",
4431 ioc->name);
4432 goto out_fail;
4433 }
4434
4435 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Total alloc @ %p[%p], sz=%d[%x] bytes\n",
4436 ioc->name, mem, (void *)(ulong)alloc_dma, total_size, total_size));
4437
4438 memset(mem, 0, total_size);
4439 ioc->alloc_total += total_size;
4440 ioc->alloc = mem;
4441 ioc->alloc_dma = alloc_dma;
4442 ioc->alloc_sz = total_size;
4443 ioc->reply_frames = (MPT_FRAME_HDR *) mem;
4444 ioc->reply_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF);
4445
4446 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n",
4447 ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma));
4448
4449 alloc_dma += reply_sz;
4450 mem += reply_sz;
4451
4452 /* Request FIFO - WE manage this! */
4453
4454 ioc->req_frames = (MPT_FRAME_HDR *) mem;
4455 ioc->req_frames_dma = alloc_dma;
4456
4457 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffers @ %p[%p]\n",
4458 ioc->name, mem, (void *)(ulong)alloc_dma));
4459
4460 ioc->req_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF);
4461
4462#if defined(CONFIG_MTRR) && 0
4463 /*
4464 * Enable Write Combining MTRR for IOC's memory region.
4465 * (at least as much as we can; "size and base must be
4466 * multiples of 4 kiB"
4467 */
4468 ioc->mtrr_reg = mtrr_add(ioc->req_frames_dma,
4469 sz,
4470 MTRR_TYPE_WRCOMB, 1);
4471 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "MTRR region registered (base:size=%08x:%x)\n",
4472 ioc->name, ioc->req_frames_dma, sz));
4473#endif
4474
4475 for (i = 0; i < ioc->req_depth; i++) {
4476 alloc_dma += ioc->req_sz;
4477 mem += ioc->req_sz;
4478 }
4479
4480 ioc->ChainBuffer = mem;
4481 ioc->ChainBufferDMA = alloc_dma;
4482
4483 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffers @ %p(%p)\n",
4484 ioc->name, ioc->ChainBuffer, (void *)(ulong)ioc->ChainBufferDMA));
4485
4486 /* Initialize the free chain Q.
4487 */
4488
4489 INIT_LIST_HEAD(&ioc->FreeChainQ);
4490
4491 /* Post the chain buffers to the FreeChainQ.
4492 */
4493 mem = (u8 *)ioc->ChainBuffer;
4494 for (i=0; i < num_chain; i++) {
4495 mf = (MPT_FRAME_HDR *) mem;
4496 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeChainQ);
4497 mem += ioc->req_sz;
4498 }
4499
4500 /* Initialize Request frames linked list
4501 */
4502 alloc_dma = ioc->req_frames_dma;
4503 mem = (u8 *) ioc->req_frames;
4504
4505 spin_lock_irqsave(&ioc->FreeQlock, flags);
4506 INIT_LIST_HEAD(&ioc->FreeQ);
4507 for (i = 0; i < ioc->req_depth; i++) {
4508 mf = (MPT_FRAME_HDR *) mem;
4509
4510 /* Queue REQUESTs *internally*! */
4511 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeQ);
4512
4513 mem += ioc->req_sz;
4514 }
4515 spin_unlock_irqrestore(&ioc->FreeQlock, flags);
4516
4517 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
4518 ioc->sense_buf_pool =
4519 pci_alloc_consistent(ioc->pcidev, sz, &ioc->sense_buf_pool_dma);
4520 if (ioc->sense_buf_pool == NULL) {
4521 printk(MYIOC_s_ERR_FMT "Unable to allocate Sense Buffers!\n",
4522 ioc->name);
4523 goto out_fail;
4524 }
4525
4526 ioc->sense_buf_low_dma = (u32) (ioc->sense_buf_pool_dma & 0xFFFFFFFF);
4527 ioc->alloc_total += sz;
4528 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SenseBuffers @ %p[%p]\n",
4529 ioc->name, ioc->sense_buf_pool, (void *)(ulong)ioc->sense_buf_pool_dma));
4530
4531 }
4532
4533 /* Post Reply frames to FIFO
4534 */
4535 alloc_dma = ioc->alloc_dma;
4536 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n",
4537 ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma));
4538
4539 for (i = 0; i < ioc->reply_depth; i++) {
4540 /* Write each address to the IOC! */
4541 CHIPREG_WRITE32(&ioc->chip->ReplyFifo, alloc_dma);
4542 alloc_dma += ioc->reply_sz;
4543 }
4544
4545 if (dma_mask == DMA_BIT_MASK(35) && !pci_set_dma_mask(ioc->pcidev,
4546 ioc->dma_mask) && !pci_set_consistent_dma_mask(ioc->pcidev,
4547 ioc->dma_mask))
4548 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4549 "restoring 64 bit addressing\n", ioc->name));
4550
4551 return 0;
4552
4553out_fail:
4554
4555 if (ioc->alloc != NULL) {
4556 sz = ioc->alloc_sz;
4557 pci_free_consistent(ioc->pcidev,
4558 sz,
4559 ioc->alloc, ioc->alloc_dma);
4560 ioc->reply_frames = NULL;
4561 ioc->req_frames = NULL;
4562 ioc->alloc_total -= sz;
4563 }
4564 if (ioc->sense_buf_pool != NULL) {
4565 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
4566 pci_free_consistent(ioc->pcidev,
4567 sz,
4568 ioc->sense_buf_pool, ioc->sense_buf_pool_dma);
4569 ioc->sense_buf_pool = NULL;
4570 }
4571
4572 if (dma_mask == DMA_BIT_MASK(35) && !pci_set_dma_mask(ioc->pcidev,
4573 DMA_BIT_MASK(64)) && !pci_set_consistent_dma_mask(ioc->pcidev,
4574 DMA_BIT_MASK(64)))
4575 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4576 "restoring 64 bit addressing\n", ioc->name));
4577
4578 return -1;
4579}
4580
4581/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4582/**
4583 * mpt_handshake_req_reply_wait - Send MPT request to and receive reply
4584 * from IOC via doorbell handshake method.
4585 * @ioc: Pointer to MPT_ADAPTER structure
4586 * @reqBytes: Size of the request in bytes
4587 * @req: Pointer to MPT request frame
4588 * @replyBytes: Expected size of the reply in bytes
4589 * @u16reply: Pointer to area where reply should be written
4590 * @maxwait: Max wait time for a reply (in seconds)
4591 * @sleepFlag: Specifies whether the process can sleep
4592 *
4593 * NOTES: It is the callers responsibility to byte-swap fields in the
4594 * request which are greater than 1 byte in size. It is also the
4595 * callers responsibility to byte-swap response fields which are
4596 * greater than 1 byte in size.
4597 *
4598 * Returns 0 for success, non-zero for failure.
4599 */
4600static int
4601mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes, u32 *req,
4602 int replyBytes, u16 *u16reply, int maxwait, int sleepFlag)
4603{
4604 MPIDefaultReply_t *mptReply;
4605 int failcnt = 0;
4606 int t;
4607
4608 /*
4609 * Get ready to cache a handshake reply
4610 */
4611 ioc->hs_reply_idx = 0;
4612 mptReply = (MPIDefaultReply_t *) ioc->hs_reply;
4613 mptReply->MsgLength = 0;
4614
4615 /*
4616 * Make sure there are no doorbells (WRITE 0 to IntStatus reg),
4617 * then tell IOC that we want to handshake a request of N words.
4618 * (WRITE u32val to Doorbell reg).
4619 */
4620 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4621 CHIPREG_WRITE32(&ioc->chip->Doorbell,
4622 ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) |
4623 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT)));
4624
4625 /*
4626 * Wait for IOC's doorbell handshake int
4627 */
4628 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4629 failcnt++;
4630
4631 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request start reqBytes=%d, WaitCnt=%d%s\n",
4632 ioc->name, reqBytes, t, failcnt ? " - MISSING DOORBELL HANDSHAKE!" : ""));
4633
4634 /* Read doorbell and check for active bit */
4635 if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
4636 return -1;
4637
4638 /*
4639 * Clear doorbell int (WRITE 0 to IntStatus reg),
4640 * then wait for IOC to ACKnowledge that it's ready for
4641 * our handshake request.
4642 */
4643 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4644 if (!failcnt && (t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
4645 failcnt++;
4646
4647 if (!failcnt) {
4648 int ii;
4649 u8 *req_as_bytes = (u8 *) req;
4650
4651 /*
4652 * Stuff request words via doorbell handshake,
4653 * with ACK from IOC for each.
4654 */
4655 for (ii = 0; !failcnt && ii < reqBytes/4; ii++) {
4656 u32 word = ((req_as_bytes[(ii*4) + 0] << 0) |
4657 (req_as_bytes[(ii*4) + 1] << 8) |
4658 (req_as_bytes[(ii*4) + 2] << 16) |
4659 (req_as_bytes[(ii*4) + 3] << 24));
4660
4661 CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
4662 if ((t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
4663 failcnt++;
4664 }
4665
4666 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Handshake request frame (@%p) header\n", ioc->name, req));
4667 DBG_DUMP_REQUEST_FRAME_HDR(ioc, (u32 *)req);
4668
4669 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request post done, WaitCnt=%d%s\n",
4670 ioc->name, t, failcnt ? " - MISSING DOORBELL ACK!" : ""));
4671
4672 /*
4673 * Wait for completion of doorbell handshake reply from the IOC
4674 */
4675 if (!failcnt && (t = WaitForDoorbellReply(ioc, maxwait, sleepFlag)) < 0)
4676 failcnt++;
4677
4678 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake reply count=%d%s\n",
4679 ioc->name, t, failcnt ? " - MISSING DOORBELL REPLY!" : ""));
4680
4681 /*
4682 * Copy out the cached reply...
4683 */
4684 for (ii=0; ii < min(replyBytes/2,mptReply->MsgLength*2); ii++)
4685 u16reply[ii] = ioc->hs_reply[ii];
4686 } else {
4687 return -99;
4688 }
4689
4690 return -failcnt;
4691}
4692
4693/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4694/**
4695 * WaitForDoorbellAck - Wait for IOC doorbell handshake acknowledge
4696 * @ioc: Pointer to MPT_ADAPTER structure
4697 * @howlong: How long to wait (in seconds)
4698 * @sleepFlag: Specifies whether the process can sleep
4699 *
4700 * This routine waits (up to ~2 seconds max) for IOC doorbell
4701 * handshake ACKnowledge, indicated by the IOP_DOORBELL_STATUS
4702 * bit in its IntStatus register being clear.
4703 *
4704 * Returns a negative value on failure, else wait loop count.
4705 */
4706static int
4707WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
4708{
4709 int cntdn;
4710 int count = 0;
4711 u32 intstat=0;
4712
4713 cntdn = 1000 * howlong;
4714
4715 if (sleepFlag == CAN_SLEEP) {
4716 while (--cntdn) {
4717 msleep (1);
4718 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4719 if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS))
4720 break;
4721 count++;
4722 }
4723 } else {
4724 while (--cntdn) {
4725 udelay (1000);
4726 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4727 if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS))
4728 break;
4729 count++;
4730 }
4731 }
4732
4733 if (cntdn) {
4734 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell ACK (count=%d)\n",
4735 ioc->name, count));
4736 return count;
4737 }
4738
4739 printk(MYIOC_s_ERR_FMT "Doorbell ACK timeout (count=%d), IntStatus=%x!\n",
4740 ioc->name, count, intstat);
4741 return -1;
4742}
4743
4744/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4745/**
4746 * WaitForDoorbellInt - Wait for IOC to set its doorbell interrupt bit
4747 * @ioc: Pointer to MPT_ADAPTER structure
4748 * @howlong: How long to wait (in seconds)
4749 * @sleepFlag: Specifies whether the process can sleep
4750 *
4751 * This routine waits (up to ~2 seconds max) for IOC doorbell interrupt
4752 * (MPI_HIS_DOORBELL_INTERRUPT) to be set in the IntStatus register.
4753 *
4754 * Returns a negative value on failure, else wait loop count.
4755 */
4756static int
4757WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
4758{
4759 int cntdn;
4760 int count = 0;
4761 u32 intstat=0;
4762
4763 cntdn = 1000 * howlong;
4764 if (sleepFlag == CAN_SLEEP) {
4765 while (--cntdn) {
4766 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4767 if (intstat & MPI_HIS_DOORBELL_INTERRUPT)
4768 break;
4769 msleep(1);
4770 count++;
4771 }
4772 } else {
4773 while (--cntdn) {
4774 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4775 if (intstat & MPI_HIS_DOORBELL_INTERRUPT)
4776 break;
4777 udelay (1000);
4778 count++;
4779 }
4780 }
4781
4782 if (cntdn) {
4783 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell INT (cnt=%d) howlong=%d\n",
4784 ioc->name, count, howlong));
4785 return count;
4786 }
4787
4788 printk(MYIOC_s_ERR_FMT "Doorbell INT timeout (count=%d), IntStatus=%x!\n",
4789 ioc->name, count, intstat);
4790 return -1;
4791}
4792
4793/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4794/**
4795 * WaitForDoorbellReply - Wait for and capture an IOC handshake reply.
4796 * @ioc: Pointer to MPT_ADAPTER structure
4797 * @howlong: How long to wait (in seconds)
4798 * @sleepFlag: Specifies whether the process can sleep
4799 *
4800 * This routine polls the IOC for a handshake reply, 16 bits at a time.
4801 * Reply is cached to IOC private area large enough to hold a maximum
4802 * of 128 bytes of reply data.
4803 *
4804 * Returns a negative value on failure, else size of reply in WORDS.
4805 */
4806static int
4807WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
4808{
4809 int u16cnt = 0;
4810 int failcnt = 0;
4811 int t;
4812 u16 *hs_reply = ioc->hs_reply;
4813 volatile MPIDefaultReply_t *mptReply = (MPIDefaultReply_t *) ioc->hs_reply;
4814 u16 hword;
4815
4816 hs_reply[0] = hs_reply[1] = hs_reply[7] = 0;
4817
4818 /*
4819 * Get first two u16's so we can look at IOC's intended reply MsgLength
4820 */
4821 u16cnt=0;
4822 if ((t = WaitForDoorbellInt(ioc, howlong, sleepFlag)) < 0) {
4823 failcnt++;
4824 } else {
4825 hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
4826 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4827 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4828 failcnt++;
4829 else {
4830 hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
4831 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4832 }
4833 }
4834
4835 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitCnt=%d First handshake reply word=%08x%s\n",
4836 ioc->name, t, le32_to_cpu(*(u32 *)hs_reply),
4837 failcnt ? " - MISSING DOORBELL HANDSHAKE!" : ""));
4838
4839 /*
4840 * If no error (and IOC said MsgLength is > 0), piece together
4841 * reply 16 bits at a time.
4842 */
4843 for (u16cnt=2; !failcnt && u16cnt < (2 * mptReply->MsgLength); u16cnt++) {
4844 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4845 failcnt++;
4846 hword = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
4847 /* don't overflow our IOC hs_reply[] buffer! */
4848 if (u16cnt < ARRAY_SIZE(ioc->hs_reply))
4849 hs_reply[u16cnt] = hword;
4850 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4851 }
4852
4853 if (!failcnt && (t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4854 failcnt++;
4855 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4856
4857 if (failcnt) {
4858 printk(MYIOC_s_ERR_FMT "Handshake reply failure!\n",
4859 ioc->name);
4860 return -failcnt;
4861 }
4862#if 0
4863 else if (u16cnt != (2 * mptReply->MsgLength)) {
4864 return -101;
4865 }
4866 else if ((mptReply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) {
4867 return -102;
4868 }
4869#endif
4870
4871 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got Handshake reply:\n", ioc->name));
4872 DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mptReply);
4873
4874 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell REPLY WaitCnt=%d (sz=%d)\n",
4875 ioc->name, t, u16cnt/2));
4876 return u16cnt/2;
4877}
4878
4879/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4880/**
4881 * GetLanConfigPages - Fetch LANConfig pages.
4882 * @ioc: Pointer to MPT_ADAPTER structure
4883 *
4884 * Return: 0 for success
4885 * -ENOMEM if no memory available
4886 * -EPERM if not allowed due to ISR context
4887 * -EAGAIN if no msg frames currently available
4888 * -EFAULT for non-successful reply or no reply (timeout)
4889 */
4890static int
4891GetLanConfigPages(MPT_ADAPTER *ioc)
4892{
4893 ConfigPageHeader_t hdr;
4894 CONFIGPARMS cfg;
4895 LANPage0_t *ppage0_alloc;
4896 dma_addr_t page0_dma;
4897 LANPage1_t *ppage1_alloc;
4898 dma_addr_t page1_dma;
4899 int rc = 0;
4900 int data_sz;
4901 int copy_sz;
4902
4903 /* Get LAN Page 0 header */
4904 hdr.PageVersion = 0;
4905 hdr.PageLength = 0;
4906 hdr.PageNumber = 0;
4907 hdr.PageType = MPI_CONFIG_PAGETYPE_LAN;
4908 cfg.cfghdr.hdr = &hdr;
4909 cfg.physAddr = -1;
4910 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
4911 cfg.dir = 0;
4912 cfg.pageAddr = 0;
4913 cfg.timeout = 0;
4914
4915 if ((rc = mpt_config(ioc, &cfg)) != 0)
4916 return rc;
4917
4918 if (hdr.PageLength > 0) {
4919 data_sz = hdr.PageLength * 4;
4920 ppage0_alloc = (LANPage0_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page0_dma);
4921 rc = -ENOMEM;
4922 if (ppage0_alloc) {
4923 memset((u8 *)ppage0_alloc, 0, data_sz);
4924 cfg.physAddr = page0_dma;
4925 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
4926
4927 if ((rc = mpt_config(ioc, &cfg)) == 0) {
4928 /* save the data */
4929 copy_sz = min_t(int, sizeof(LANPage0_t), data_sz);
4930 memcpy(&ioc->lan_cnfg_page0, ppage0_alloc, copy_sz);
4931
4932 }
4933
4934 pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage0_alloc, page0_dma);
4935
4936 /* FIXME!
4937 * Normalize endianness of structure data,
4938 * by byte-swapping all > 1 byte fields!
4939 */
4940
4941 }
4942
4943 if (rc)
4944 return rc;
4945 }
4946
4947 /* Get LAN Page 1 header */
4948 hdr.PageVersion = 0;
4949 hdr.PageLength = 0;
4950 hdr.PageNumber = 1;
4951 hdr.PageType = MPI_CONFIG_PAGETYPE_LAN;
4952 cfg.cfghdr.hdr = &hdr;
4953 cfg.physAddr = -1;
4954 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
4955 cfg.dir = 0;
4956 cfg.pageAddr = 0;
4957
4958 if ((rc = mpt_config(ioc, &cfg)) != 0)
4959 return rc;
4960
4961 if (hdr.PageLength == 0)
4962 return 0;
4963
4964 data_sz = hdr.PageLength * 4;
4965 rc = -ENOMEM;
4966 ppage1_alloc = (LANPage1_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page1_dma);
4967 if (ppage1_alloc) {
4968 memset((u8 *)ppage1_alloc, 0, data_sz);
4969 cfg.physAddr = page1_dma;
4970 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
4971
4972 if ((rc = mpt_config(ioc, &cfg)) == 0) {
4973 /* save the data */
4974 copy_sz = min_t(int, sizeof(LANPage1_t), data_sz);
4975 memcpy(&ioc->lan_cnfg_page1, ppage1_alloc, copy_sz);
4976 }
4977
4978 pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage1_alloc, page1_dma);
4979
4980 /* FIXME!
4981 * Normalize endianness of structure data,
4982 * by byte-swapping all > 1 byte fields!
4983 */
4984
4985 }
4986
4987 return rc;
4988}
4989
4990/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4991/**
4992 * mptbase_sas_persist_operation - Perform operation on SAS Persistent Table
4993 * @ioc: Pointer to MPT_ADAPTER structure
4994 * @persist_opcode: see below
4995 *
4996 * MPI_SAS_OP_CLEAR_NOT_PRESENT - Free all persist TargetID mappings for
4997 * devices not currently present.
4998 * MPI_SAS_OP_CLEAR_ALL_PERSISTENT - Clear al persist TargetID mappings
4999 *
5000 * NOTE: Don't use not this function during interrupt time.
5001 *
5002 * Returns 0 for success, non-zero error
5003 */
5004
5005/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5006int
5007mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode)
5008{
5009 SasIoUnitControlRequest_t *sasIoUnitCntrReq;
5010 SasIoUnitControlReply_t *sasIoUnitCntrReply;
5011 MPT_FRAME_HDR *mf = NULL;
5012 MPIHeader_t *mpi_hdr;
5013 int ret = 0;
5014 unsigned long timeleft;
5015
5016 mutex_lock(&ioc->mptbase_cmds.mutex);
5017
5018 /* init the internal cmd struct */
5019 memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE);
5020 INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status)
5021
5022 /* insure garbage is not sent to fw */
5023 switch(persist_opcode) {
5024
5025 case MPI_SAS_OP_CLEAR_NOT_PRESENT:
5026 case MPI_SAS_OP_CLEAR_ALL_PERSISTENT:
5027 break;
5028
5029 default:
5030 ret = -1;
5031 goto out;
5032 }
5033
5034 printk(KERN_DEBUG "%s: persist_opcode=%x\n",
5035 __func__, persist_opcode);
5036
5037 /* Get a MF for this command.
5038 */
5039 if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
5040 printk(KERN_DEBUG "%s: no msg frames!\n", __func__);
5041 ret = -1;
5042 goto out;
5043 }
5044
5045 mpi_hdr = (MPIHeader_t *) mf;
5046 sasIoUnitCntrReq = (SasIoUnitControlRequest_t *)mf;
5047 memset(sasIoUnitCntrReq,0,sizeof(SasIoUnitControlRequest_t));
5048 sasIoUnitCntrReq->Function = MPI_FUNCTION_SAS_IO_UNIT_CONTROL;
5049 sasIoUnitCntrReq->MsgContext = mpi_hdr->MsgContext;
5050 sasIoUnitCntrReq->Operation = persist_opcode;
5051
5052 mpt_put_msg_frame(mpt_base_index, ioc, mf);
5053 timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done, 10*HZ);
5054 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) {
5055 ret = -ETIME;
5056 printk(KERN_DEBUG "%s: failed\n", __func__);
5057 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET)
5058 goto out;
5059 if (!timeleft) {
5060 printk(MYIOC_s_WARN_FMT
5061 "Issuing Reset from %s!!, doorbell=0x%08x\n",
5062 ioc->name, __func__, mpt_GetIocState(ioc, 0));
5063 mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP);
5064 mpt_free_msg_frame(ioc, mf);
5065 }
5066 goto out;
5067 }
5068
5069 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) {
5070 ret = -1;
5071 goto out;
5072 }
5073
5074 sasIoUnitCntrReply =
5075 (SasIoUnitControlReply_t *)ioc->mptbase_cmds.reply;
5076 if (le16_to_cpu(sasIoUnitCntrReply->IOCStatus) != MPI_IOCSTATUS_SUCCESS) {
5077 printk(KERN_DEBUG "%s: IOCStatus=0x%X IOCLogInfo=0x%X\n",
5078 __func__, sasIoUnitCntrReply->IOCStatus,
5079 sasIoUnitCntrReply->IOCLogInfo);
5080 printk(KERN_DEBUG "%s: failed\n", __func__);
5081 ret = -1;
5082 } else
5083 printk(KERN_DEBUG "%s: success\n", __func__);
5084 out:
5085
5086 CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status)
5087 mutex_unlock(&ioc->mptbase_cmds.mutex);
5088 return ret;
5089}
5090
5091/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5092
5093static void
5094mptbase_raid_process_event_data(MPT_ADAPTER *ioc,
5095 MpiEventDataRaid_t * pRaidEventData)
5096{
5097 int volume;
5098 int reason;
5099 int disk;
5100 int status;
5101 int flags;
5102 int state;
5103
5104 volume = pRaidEventData->VolumeID;
5105 reason = pRaidEventData->ReasonCode;
5106 disk = pRaidEventData->PhysDiskNum;
5107 status = le32_to_cpu(pRaidEventData->SettingsStatus);
5108 flags = (status >> 0) & 0xff;
5109 state = (status >> 8) & 0xff;
5110
5111 if (reason == MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED) {
5112 return;
5113 }
5114
5115 if ((reason >= MPI_EVENT_RAID_RC_PHYSDISK_CREATED &&
5116 reason <= MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED) ||
5117 (reason == MPI_EVENT_RAID_RC_SMART_DATA)) {
5118 printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for PhysDisk %d id=%d\n",
5119 ioc->name, disk, volume);
5120 } else {
5121 printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for VolumeID %d\n",
5122 ioc->name, volume);
5123 }
5124
5125 switch(reason) {
5126 case MPI_EVENT_RAID_RC_VOLUME_CREATED:
5127 printk(MYIOC_s_INFO_FMT " volume has been created\n",
5128 ioc->name);
5129 break;
5130
5131 case MPI_EVENT_RAID_RC_VOLUME_DELETED:
5132
5133 printk(MYIOC_s_INFO_FMT " volume has been deleted\n",
5134 ioc->name);
5135 break;
5136
5137 case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED:
5138 printk(MYIOC_s_INFO_FMT " volume settings have been changed\n",
5139 ioc->name);
5140 break;
5141
5142 case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED:
5143 printk(MYIOC_s_INFO_FMT " volume is now %s%s%s%s\n",
5144 ioc->name,
5145 state == MPI_RAIDVOL0_STATUS_STATE_OPTIMAL
5146 ? "optimal"
5147 : state == MPI_RAIDVOL0_STATUS_STATE_DEGRADED
5148 ? "degraded"
5149 : state == MPI_RAIDVOL0_STATUS_STATE_FAILED
5150 ? "failed"
5151 : "state unknown",
5152 flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED
5153 ? ", enabled" : "",
5154 flags & MPI_RAIDVOL0_STATUS_FLAG_QUIESCED
5155 ? ", quiesced" : "",
5156 flags & MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
5157 ? ", resync in progress" : "" );
5158 break;
5159
5160 case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED:
5161 printk(MYIOC_s_INFO_FMT " volume membership of PhysDisk %d has changed\n",
5162 ioc->name, disk);
5163 break;
5164
5165 case MPI_EVENT_RAID_RC_PHYSDISK_CREATED:
5166 printk(MYIOC_s_INFO_FMT " PhysDisk has been created\n",
5167 ioc->name);
5168 break;
5169
5170 case MPI_EVENT_RAID_RC_PHYSDISK_DELETED:
5171 printk(MYIOC_s_INFO_FMT " PhysDisk has been deleted\n",
5172 ioc->name);
5173 break;
5174
5175 case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED:
5176 printk(MYIOC_s_INFO_FMT " PhysDisk settings have been changed\n",
5177 ioc->name);
5178 break;
5179
5180 case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED:
5181 printk(MYIOC_s_INFO_FMT " PhysDisk is now %s%s%s\n",
5182 ioc->name,
5183 state == MPI_PHYSDISK0_STATUS_ONLINE
5184 ? "online"
5185 : state == MPI_PHYSDISK0_STATUS_MISSING
5186 ? "missing"
5187 : state == MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE
5188 ? "not compatible"
5189 : state == MPI_PHYSDISK0_STATUS_FAILED
5190 ? "failed"
5191 : state == MPI_PHYSDISK0_STATUS_INITIALIZING
5192 ? "initializing"
5193 : state == MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED
5194 ? "offline requested"
5195 : state == MPI_PHYSDISK0_STATUS_FAILED_REQUESTED
5196 ? "failed requested"
5197 : state == MPI_PHYSDISK0_STATUS_OTHER_OFFLINE
5198 ? "offline"
5199 : "state unknown",
5200 flags & MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
5201 ? ", out of sync" : "",
5202 flags & MPI_PHYSDISK0_STATUS_FLAG_QUIESCED
5203 ? ", quiesced" : "" );
5204 break;
5205
5206 case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED:
5207 printk(MYIOC_s_INFO_FMT " Domain Validation needed for PhysDisk %d\n",
5208 ioc->name, disk);
5209 break;
5210
5211 case MPI_EVENT_RAID_RC_SMART_DATA:
5212 printk(MYIOC_s_INFO_FMT " SMART data received, ASC/ASCQ = %02xh/%02xh\n",
5213 ioc->name, pRaidEventData->ASC, pRaidEventData->ASCQ);
5214 break;
5215
5216 case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED:
5217 printk(MYIOC_s_INFO_FMT " replacement of PhysDisk %d has started\n",
5218 ioc->name, disk);
5219 break;
5220 }
5221}
5222
5223/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5224/**
5225 * GetIoUnitPage2 - Retrieve BIOS version and boot order information.
5226 * @ioc: Pointer to MPT_ADAPTER structure
5227 *
5228 * Returns: 0 for success
5229 * -ENOMEM if no memory available
5230 * -EPERM if not allowed due to ISR context
5231 * -EAGAIN if no msg frames currently available
5232 * -EFAULT for non-successful reply or no reply (timeout)
5233 */
5234static int
5235GetIoUnitPage2(MPT_ADAPTER *ioc)
5236{
5237 ConfigPageHeader_t hdr;
5238 CONFIGPARMS cfg;
5239 IOUnitPage2_t *ppage_alloc;
5240 dma_addr_t page_dma;
5241 int data_sz;
5242 int rc;
5243
5244 /* Get the page header */
5245 hdr.PageVersion = 0;
5246 hdr.PageLength = 0;
5247 hdr.PageNumber = 2;
5248 hdr.PageType = MPI_CONFIG_PAGETYPE_IO_UNIT;
5249 cfg.cfghdr.hdr = &hdr;
5250 cfg.physAddr = -1;
5251 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5252 cfg.dir = 0;
5253 cfg.pageAddr = 0;
5254 cfg.timeout = 0;
5255
5256 if ((rc = mpt_config(ioc, &cfg)) != 0)
5257 return rc;
5258
5259 if (hdr.PageLength == 0)
5260 return 0;
5261
5262 /* Read the config page */
5263 data_sz = hdr.PageLength * 4;
5264 rc = -ENOMEM;
5265 ppage_alloc = (IOUnitPage2_t *) pci_alloc_consistent(ioc->pcidev, data_sz, &page_dma);
5266 if (ppage_alloc) {
5267 memset((u8 *)ppage_alloc, 0, data_sz);
5268 cfg.physAddr = page_dma;
5269 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5270
5271 /* If Good, save data */
5272 if ((rc = mpt_config(ioc, &cfg)) == 0)
5273 ioc->biosVersion = le32_to_cpu(ppage_alloc->BiosVersion);
5274
5275 pci_free_consistent(ioc->pcidev, data_sz, (u8 *) ppage_alloc, page_dma);
5276 }
5277
5278 return rc;
5279}
5280
5281/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5282/**
5283 * mpt_GetScsiPortSettings - read SCSI Port Page 0 and 2
5284 * @ioc: Pointer to a Adapter Strucutre
5285 * @portnum: IOC port number
5286 *
5287 * Return: -EFAULT if read of config page header fails
5288 * or if no nvram
5289 * If read of SCSI Port Page 0 fails,
5290 * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF)
5291 * Adapter settings: async, narrow
5292 * Return 1
5293 * If read of SCSI Port Page 2 fails,
5294 * Adapter settings valid
5295 * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF)
5296 * Return 1
5297 * Else
5298 * Both valid
5299 * Return 0
5300 * CHECK - what type of locking mechanisms should be used????
5301 */
5302static int
5303mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum)
5304{
5305 u8 *pbuf;
5306 dma_addr_t buf_dma;
5307 CONFIGPARMS cfg;
5308 ConfigPageHeader_t header;
5309 int ii;
5310 int data, rc = 0;
5311
5312 /* Allocate memory
5313 */
5314 if (!ioc->spi_data.nvram) {
5315 int sz;
5316 u8 *mem;
5317 sz = MPT_MAX_SCSI_DEVICES * sizeof(int);
5318 mem = kmalloc(sz, GFP_ATOMIC);
5319 if (mem == NULL)
5320 return -EFAULT;
5321
5322 ioc->spi_data.nvram = (int *) mem;
5323
5324 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SCSI device NVRAM settings @ %p, sz=%d\n",
5325 ioc->name, ioc->spi_data.nvram, sz));
5326 }
5327
5328 /* Invalidate NVRAM information
5329 */
5330 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
5331 ioc->spi_data.nvram[ii] = MPT_HOST_NVRAM_INVALID;
5332 }
5333
5334 /* Read SPP0 header, allocate memory, then read page.
5335 */
5336 header.PageVersion = 0;
5337 header.PageLength = 0;
5338 header.PageNumber = 0;
5339 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT;
5340 cfg.cfghdr.hdr = &header;
5341 cfg.physAddr = -1;
5342 cfg.pageAddr = portnum;
5343 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5344 cfg.dir = 0;
5345 cfg.timeout = 0; /* use default */
5346 if (mpt_config(ioc, &cfg) != 0)
5347 return -EFAULT;
5348
5349 if (header.PageLength > 0) {
5350 pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma);
5351 if (pbuf) {
5352 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5353 cfg.physAddr = buf_dma;
5354 if (mpt_config(ioc, &cfg) != 0) {
5355 ioc->spi_data.maxBusWidth = MPT_NARROW;
5356 ioc->spi_data.maxSyncOffset = 0;
5357 ioc->spi_data.minSyncFactor = MPT_ASYNC;
5358 ioc->spi_data.busType = MPT_HOST_BUS_UNKNOWN;
5359 rc = 1;
5360 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5361 "Unable to read PortPage0 minSyncFactor=%x\n",
5362 ioc->name, ioc->spi_data.minSyncFactor));
5363 } else {
5364 /* Save the Port Page 0 data
5365 */
5366 SCSIPortPage0_t *pPP0 = (SCSIPortPage0_t *) pbuf;
5367 pPP0->Capabilities = le32_to_cpu(pPP0->Capabilities);
5368 pPP0->PhysicalInterface = le32_to_cpu(pPP0->PhysicalInterface);
5369
5370 if ( (pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_QAS) == 0 ) {
5371 ioc->spi_data.noQas |= MPT_TARGET_NO_NEGO_QAS;
5372 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5373 "noQas due to Capabilities=%x\n",
5374 ioc->name, pPP0->Capabilities));
5375 }
5376 ioc->spi_data.maxBusWidth = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_WIDE ? 1 : 0;
5377 data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK;
5378 if (data) {
5379 ioc->spi_data.maxSyncOffset = (u8) (data >> 16);
5380 data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK;
5381 ioc->spi_data.minSyncFactor = (u8) (data >> 8);
5382 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5383 "PortPage0 minSyncFactor=%x\n",
5384 ioc->name, ioc->spi_data.minSyncFactor));
5385 } else {
5386 ioc->spi_data.maxSyncOffset = 0;
5387 ioc->spi_data.minSyncFactor = MPT_ASYNC;
5388 }
5389
5390 ioc->spi_data.busType = pPP0->PhysicalInterface & MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK;
5391
5392 /* Update the minSyncFactor based on bus type.
5393 */
5394 if ((ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD) ||
5395 (ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE)) {
5396
5397 if (ioc->spi_data.minSyncFactor < MPT_ULTRA) {
5398 ioc->spi_data.minSyncFactor = MPT_ULTRA;
5399 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5400 "HVD or SE detected, minSyncFactor=%x\n",
5401 ioc->name, ioc->spi_data.minSyncFactor));
5402 }
5403 }
5404 }
5405 if (pbuf) {
5406 pci_free_consistent(ioc->pcidev, header.PageLength * 4, pbuf, buf_dma);
5407 }
5408 }
5409 }
5410
5411 /* SCSI Port Page 2 - Read the header then the page.
5412 */
5413 header.PageVersion = 0;
5414 header.PageLength = 0;
5415 header.PageNumber = 2;
5416 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT;
5417 cfg.cfghdr.hdr = &header;
5418 cfg.physAddr = -1;
5419 cfg.pageAddr = portnum;
5420 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5421 cfg.dir = 0;
5422 if (mpt_config(ioc, &cfg) != 0)
5423 return -EFAULT;
5424
5425 if (header.PageLength > 0) {
5426 /* Allocate memory and read SCSI Port Page 2
5427 */
5428 pbuf = pci_alloc_consistent(ioc->pcidev, header.PageLength * 4, &buf_dma);
5429 if (pbuf) {
5430 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_NVRAM;
5431 cfg.physAddr = buf_dma;
5432 if (mpt_config(ioc, &cfg) != 0) {
5433 /* Nvram data is left with INVALID mark
5434 */
5435 rc = 1;
5436 } else if (ioc->pcidev->vendor == PCI_VENDOR_ID_ATTO) {
5437
5438 /* This is an ATTO adapter, read Page2 accordingly
5439 */
5440 ATTO_SCSIPortPage2_t *pPP2 = (ATTO_SCSIPortPage2_t *) pbuf;
5441 ATTODeviceInfo_t *pdevice = NULL;
5442 u16 ATTOFlags;
5443
5444 /* Save the Port Page 2 data
5445 * (reformat into a 32bit quantity)
5446 */
5447 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
5448 pdevice = &pPP2->DeviceSettings[ii];
5449 ATTOFlags = le16_to_cpu(pdevice->ATTOFlags);
5450 data = 0;
5451
5452 /* Translate ATTO device flags to LSI format
5453 */
5454 if (ATTOFlags & ATTOFLAG_DISC)
5455 data |= (MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE);
5456 if (ATTOFlags & ATTOFLAG_ID_ENB)
5457 data |= (MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE);
5458 if (ATTOFlags & ATTOFLAG_LUN_ENB)
5459 data |= (MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE);
5460 if (ATTOFlags & ATTOFLAG_TAGGED)
5461 data |= (MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE);
5462 if (!(ATTOFlags & ATTOFLAG_WIDE_ENB))
5463 data |= (MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE);
5464
5465 data = (data << 16) | (pdevice->Period << 8) | 10;
5466 ioc->spi_data.nvram[ii] = data;
5467 }
5468 } else {
5469 SCSIPortPage2_t *pPP2 = (SCSIPortPage2_t *) pbuf;
5470 MpiDeviceInfo_t *pdevice = NULL;
5471
5472 /*
5473 * Save "Set to Avoid SCSI Bus Resets" flag
5474 */
5475 ioc->spi_data.bus_reset =
5476 (le32_to_cpu(pPP2->PortFlags) &
5477 MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET) ?
5478 0 : 1 ;
5479
5480 /* Save the Port Page 2 data
5481 * (reformat into a 32bit quantity)
5482 */
5483 data = le32_to_cpu(pPP2->PortFlags) & MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK;
5484 ioc->spi_data.PortFlags = data;
5485 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
5486 pdevice = &pPP2->DeviceSettings[ii];
5487 data = (le16_to_cpu(pdevice->DeviceFlags) << 16) |
5488 (pdevice->SyncFactor << 8) | pdevice->Timeout;
5489 ioc->spi_data.nvram[ii] = data;
5490 }
5491 }
5492
5493 pci_free_consistent(ioc->pcidev, header.PageLength * 4, pbuf, buf_dma);
5494 }
5495 }
5496
5497 /* Update Adapter limits with those from NVRAM
5498 * Comment: Don't need to do this. Target performance
5499 * parameters will never exceed the adapters limits.
5500 */
5501
5502 return rc;
5503}
5504
5505/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5506/**
5507 * mpt_readScsiDevicePageHeaders - save version and length of SDP1
5508 * @ioc: Pointer to a Adapter Strucutre
5509 * @portnum: IOC port number
5510 *
5511 * Return: -EFAULT if read of config page header fails
5512 * or 0 if success.
5513 */
5514static int
5515mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum)
5516{
5517 CONFIGPARMS cfg;
5518 ConfigPageHeader_t header;
5519
5520 /* Read the SCSI Device Page 1 header
5521 */
5522 header.PageVersion = 0;
5523 header.PageLength = 0;
5524 header.PageNumber = 1;
5525 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
5526 cfg.cfghdr.hdr = &header;
5527 cfg.physAddr = -1;
5528 cfg.pageAddr = portnum;
5529 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5530 cfg.dir = 0;
5531 cfg.timeout = 0;
5532 if (mpt_config(ioc, &cfg) != 0)
5533 return -EFAULT;
5534
5535 ioc->spi_data.sdp1version = cfg.cfghdr.hdr->PageVersion;
5536 ioc->spi_data.sdp1length = cfg.cfghdr.hdr->PageLength;
5537
5538 header.PageVersion = 0;
5539 header.PageLength = 0;
5540 header.PageNumber = 0;
5541 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
5542 if (mpt_config(ioc, &cfg) != 0)
5543 return -EFAULT;
5544
5545 ioc->spi_data.sdp0version = cfg.cfghdr.hdr->PageVersion;
5546 ioc->spi_data.sdp0length = cfg.cfghdr.hdr->PageLength;
5547
5548 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 0: version %d length %d\n",
5549 ioc->name, ioc->spi_data.sdp0version, ioc->spi_data.sdp0length));
5550
5551 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 1: version %d length %d\n",
5552 ioc->name, ioc->spi_data.sdp1version, ioc->spi_data.sdp1length));
5553 return 0;
5554}
5555
5556/**
5557 * mpt_inactive_raid_list_free - This clears this link list.
5558 * @ioc : pointer to per adapter structure
5559 **/
5560static void
5561mpt_inactive_raid_list_free(MPT_ADAPTER *ioc)
5562{
5563 struct inactive_raid_component_info *component_info, *pNext;
5564
5565 if (list_empty(&ioc->raid_data.inactive_list))
5566 return;
5567
5568 mutex_lock(&ioc->raid_data.inactive_list_mutex);
5569 list_for_each_entry_safe(component_info, pNext,
5570 &ioc->raid_data.inactive_list, list) {
5571 list_del(&component_info->list);
5572 kfree(component_info);
5573 }
5574 mutex_unlock(&ioc->raid_data.inactive_list_mutex);
5575}
5576
5577/**
5578 * mpt_inactive_raid_volumes - sets up link list of phy_disk_nums for devices belonging in an inactive volume
5579 *
5580 * @ioc : pointer to per adapter structure
5581 * @channel : volume channel
5582 * @id : volume target id
5583 **/
5584static void
5585mpt_inactive_raid_volumes(MPT_ADAPTER *ioc, u8 channel, u8 id)
5586{
5587 CONFIGPARMS cfg;
5588 ConfigPageHeader_t hdr;
5589 dma_addr_t dma_handle;
5590 pRaidVolumePage0_t buffer = NULL;
5591 int i;
5592 RaidPhysDiskPage0_t phys_disk;
5593 struct inactive_raid_component_info *component_info;
5594 int handle_inactive_volumes;
5595
5596 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5597 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5598 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_VOLUME;
5599 cfg.pageAddr = (channel << 8) + id;
5600 cfg.cfghdr.hdr = &hdr;
5601 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5602
5603 if (mpt_config(ioc, &cfg) != 0)
5604 goto out;
5605
5606 if (!hdr.PageLength)
5607 goto out;
5608
5609 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
5610 &dma_handle);
5611
5612 if (!buffer)
5613 goto out;
5614
5615 cfg.physAddr = dma_handle;
5616 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5617
5618 if (mpt_config(ioc, &cfg) != 0)
5619 goto out;
5620
5621 if (!buffer->NumPhysDisks)
5622 goto out;
5623
5624 handle_inactive_volumes =
5625 (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE ||
5626 (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED) == 0 ||
5627 buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_FAILED ||
5628 buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_MISSING) ? 1 : 0;
5629
5630 if (!handle_inactive_volumes)
5631 goto out;
5632
5633 mutex_lock(&ioc->raid_data.inactive_list_mutex);
5634 for (i = 0; i < buffer->NumPhysDisks; i++) {
5635 if(mpt_raid_phys_disk_pg0(ioc,
5636 buffer->PhysDisk[i].PhysDiskNum, &phys_disk) != 0)
5637 continue;
5638
5639 if ((component_info = kmalloc(sizeof (*component_info),
5640 GFP_KERNEL)) == NULL)
5641 continue;
5642
5643 component_info->volumeID = id;
5644 component_info->volumeBus = channel;
5645 component_info->d.PhysDiskNum = phys_disk.PhysDiskNum;
5646 component_info->d.PhysDiskBus = phys_disk.PhysDiskBus;
5647 component_info->d.PhysDiskID = phys_disk.PhysDiskID;
5648 component_info->d.PhysDiskIOC = phys_disk.PhysDiskIOC;
5649
5650 list_add_tail(&component_info->list,
5651 &ioc->raid_data.inactive_list);
5652 }
5653 mutex_unlock(&ioc->raid_data.inactive_list_mutex);
5654
5655 out:
5656 if (buffer)
5657 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
5658 dma_handle);
5659}
5660
5661/**
5662 * mpt_raid_phys_disk_pg0 - returns phys disk page zero
5663 * @ioc: Pointer to a Adapter Structure
5664 * @phys_disk_num: io unit unique phys disk num generated by the ioc
5665 * @phys_disk: requested payload data returned
5666 *
5667 * Return:
5668 * 0 on success
5669 * -EFAULT if read of config page header fails or data pointer not NULL
5670 * -ENOMEM if pci_alloc failed
5671 **/
5672int
5673mpt_raid_phys_disk_pg0(MPT_ADAPTER *ioc, u8 phys_disk_num,
5674 RaidPhysDiskPage0_t *phys_disk)
5675{
5676 CONFIGPARMS cfg;
5677 ConfigPageHeader_t hdr;
5678 dma_addr_t dma_handle;
5679 pRaidPhysDiskPage0_t buffer = NULL;
5680 int rc;
5681
5682 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5683 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5684 memset(phys_disk, 0, sizeof(RaidPhysDiskPage0_t));
5685
5686 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE0_PAGEVERSION;
5687 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
5688 cfg.cfghdr.hdr = &hdr;
5689 cfg.physAddr = -1;
5690 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5691
5692 if (mpt_config(ioc, &cfg) != 0) {
5693 rc = -EFAULT;
5694 goto out;
5695 }
5696
5697 if (!hdr.PageLength) {
5698 rc = -EFAULT;
5699 goto out;
5700 }
5701
5702 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
5703 &dma_handle);
5704
5705 if (!buffer) {
5706 rc = -ENOMEM;
5707 goto out;
5708 }
5709
5710 cfg.physAddr = dma_handle;
5711 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5712 cfg.pageAddr = phys_disk_num;
5713
5714 if (mpt_config(ioc, &cfg) != 0) {
5715 rc = -EFAULT;
5716 goto out;
5717 }
5718
5719 rc = 0;
5720 memcpy(phys_disk, buffer, sizeof(*buffer));
5721 phys_disk->MaxLBA = le32_to_cpu(buffer->MaxLBA);
5722
5723 out:
5724
5725 if (buffer)
5726 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
5727 dma_handle);
5728
5729 return rc;
5730}
5731
5732/**
5733 * mpt_raid_phys_disk_get_num_paths - returns number paths associated to this phys_num
5734 * @ioc: Pointer to a Adapter Structure
5735 * @phys_disk_num: io unit unique phys disk num generated by the ioc
5736 *
5737 * Return:
5738 * returns number paths
5739 **/
5740int
5741mpt_raid_phys_disk_get_num_paths(MPT_ADAPTER *ioc, u8 phys_disk_num)
5742{
5743 CONFIGPARMS cfg;
5744 ConfigPageHeader_t hdr;
5745 dma_addr_t dma_handle;
5746 pRaidPhysDiskPage1_t buffer = NULL;
5747 int rc;
5748
5749 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5750 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5751
5752 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION;
5753 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
5754 hdr.PageNumber = 1;
5755 cfg.cfghdr.hdr = &hdr;
5756 cfg.physAddr = -1;
5757 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5758
5759 if (mpt_config(ioc, &cfg) != 0) {
5760 rc = 0;
5761 goto out;
5762 }
5763
5764 if (!hdr.PageLength) {
5765 rc = 0;
5766 goto out;
5767 }
5768
5769 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
5770 &dma_handle);
5771
5772 if (!buffer) {
5773 rc = 0;
5774 goto out;
5775 }
5776
5777 cfg.physAddr = dma_handle;
5778 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5779 cfg.pageAddr = phys_disk_num;
5780
5781 if (mpt_config(ioc, &cfg) != 0) {
5782 rc = 0;
5783 goto out;
5784 }
5785
5786 rc = buffer->NumPhysDiskPaths;
5787 out:
5788
5789 if (buffer)
5790 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
5791 dma_handle);
5792
5793 return rc;
5794}
5795EXPORT_SYMBOL(mpt_raid_phys_disk_get_num_paths);
5796
5797/**
5798 * mpt_raid_phys_disk_pg1 - returns phys disk page 1
5799 * @ioc: Pointer to a Adapter Structure
5800 * @phys_disk_num: io unit unique phys disk num generated by the ioc
5801 * @phys_disk: requested payload data returned
5802 *
5803 * Return:
5804 * 0 on success
5805 * -EFAULT if read of config page header fails or data pointer not NULL
5806 * -ENOMEM if pci_alloc failed
5807 **/
5808int
5809mpt_raid_phys_disk_pg1(MPT_ADAPTER *ioc, u8 phys_disk_num,
5810 RaidPhysDiskPage1_t *phys_disk)
5811{
5812 CONFIGPARMS cfg;
5813 ConfigPageHeader_t hdr;
5814 dma_addr_t dma_handle;
5815 pRaidPhysDiskPage1_t buffer = NULL;
5816 int rc;
5817 int i;
5818 __le64 sas_address;
5819
5820 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5821 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5822 rc = 0;
5823
5824 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION;
5825 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
5826 hdr.PageNumber = 1;
5827 cfg.cfghdr.hdr = &hdr;
5828 cfg.physAddr = -1;
5829 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5830
5831 if (mpt_config(ioc, &cfg) != 0) {
5832 rc = -EFAULT;
5833 goto out;
5834 }
5835
5836 if (!hdr.PageLength) {
5837 rc = -EFAULT;
5838 goto out;
5839 }
5840
5841 buffer = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4,
5842 &dma_handle);
5843
5844 if (!buffer) {
5845 rc = -ENOMEM;
5846 goto out;
5847 }
5848
5849 cfg.physAddr = dma_handle;
5850 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5851 cfg.pageAddr = phys_disk_num;
5852
5853 if (mpt_config(ioc, &cfg) != 0) {
5854 rc = -EFAULT;
5855 goto out;
5856 }
5857
5858 phys_disk->NumPhysDiskPaths = buffer->NumPhysDiskPaths;
5859 phys_disk->PhysDiskNum = phys_disk_num;
5860 for (i = 0; i < phys_disk->NumPhysDiskPaths; i++) {
5861 phys_disk->Path[i].PhysDiskID = buffer->Path[i].PhysDiskID;
5862 phys_disk->Path[i].PhysDiskBus = buffer->Path[i].PhysDiskBus;
5863 phys_disk->Path[i].OwnerIdentifier =
5864 buffer->Path[i].OwnerIdentifier;
5865 phys_disk->Path[i].Flags = le16_to_cpu(buffer->Path[i].Flags);
5866 memcpy(&sas_address, &buffer->Path[i].WWID, sizeof(__le64));
5867 sas_address = le64_to_cpu(sas_address);
5868 memcpy(&phys_disk->Path[i].WWID, &sas_address, sizeof(__le64));
5869 memcpy(&sas_address,
5870 &buffer->Path[i].OwnerWWID, sizeof(__le64));
5871 sas_address = le64_to_cpu(sas_address);
5872 memcpy(&phys_disk->Path[i].OwnerWWID,
5873 &sas_address, sizeof(__le64));
5874 }
5875
5876 out:
5877
5878 if (buffer)
5879 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, buffer,
5880 dma_handle);
5881
5882 return rc;
5883}
5884EXPORT_SYMBOL(mpt_raid_phys_disk_pg1);
5885
5886
5887/**
5888 * mpt_findImVolumes - Identify IDs of hidden disks and RAID Volumes
5889 * @ioc: Pointer to a Adapter Strucutre
5890 *
5891 * Return:
5892 * 0 on success
5893 * -EFAULT if read of config page header fails or data pointer not NULL
5894 * -ENOMEM if pci_alloc failed
5895 **/
5896int
5897mpt_findImVolumes(MPT_ADAPTER *ioc)
5898{
5899 IOCPage2_t *pIoc2;
5900 u8 *mem;
5901 dma_addr_t ioc2_dma;
5902 CONFIGPARMS cfg;
5903 ConfigPageHeader_t header;
5904 int rc = 0;
5905 int iocpage2sz;
5906 int i;
5907
5908 if (!ioc->ir_firmware)
5909 return 0;
5910
5911 /* Free the old page
5912 */
5913 kfree(ioc->raid_data.pIocPg2);
5914 ioc->raid_data.pIocPg2 = NULL;
5915 mpt_inactive_raid_list_free(ioc);
5916
5917 /* Read IOCP2 header then the page.
5918 */
5919 header.PageVersion = 0;
5920 header.PageLength = 0;
5921 header.PageNumber = 2;
5922 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
5923 cfg.cfghdr.hdr = &header;
5924 cfg.physAddr = -1;
5925 cfg.pageAddr = 0;
5926 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5927 cfg.dir = 0;
5928 cfg.timeout = 0;
5929 if (mpt_config(ioc, &cfg) != 0)
5930 return -EFAULT;
5931
5932 if (header.PageLength == 0)
5933 return -EFAULT;
5934
5935 iocpage2sz = header.PageLength * 4;
5936 pIoc2 = pci_alloc_consistent(ioc->pcidev, iocpage2sz, &ioc2_dma);
5937 if (!pIoc2)
5938 return -ENOMEM;
5939
5940 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5941 cfg.physAddr = ioc2_dma;
5942 if (mpt_config(ioc, &cfg) != 0)
5943 goto out;
5944
5945 mem = kmalloc(iocpage2sz, GFP_KERNEL);
5946 if (!mem) {
5947 rc = -ENOMEM;
5948 goto out;
5949 }
5950
5951 memcpy(mem, (u8 *)pIoc2, iocpage2sz);
5952 ioc->raid_data.pIocPg2 = (IOCPage2_t *) mem;
5953
5954 mpt_read_ioc_pg_3(ioc);
5955
5956 for (i = 0; i < pIoc2->NumActiveVolumes ; i++)
5957 mpt_inactive_raid_volumes(ioc,
5958 pIoc2->RaidVolume[i].VolumeBus,
5959 pIoc2->RaidVolume[i].VolumeID);
5960
5961 out:
5962 pci_free_consistent(ioc->pcidev, iocpage2sz, pIoc2, ioc2_dma);
5963
5964 return rc;
5965}
5966
5967static int
5968mpt_read_ioc_pg_3(MPT_ADAPTER *ioc)
5969{
5970 IOCPage3_t *pIoc3;
5971 u8 *mem;
5972 CONFIGPARMS cfg;
5973 ConfigPageHeader_t header;
5974 dma_addr_t ioc3_dma;
5975 int iocpage3sz = 0;
5976
5977 /* Free the old page
5978 */
5979 kfree(ioc->raid_data.pIocPg3);
5980 ioc->raid_data.pIocPg3 = NULL;
5981
5982 /* There is at least one physical disk.
5983 * Read and save IOC Page 3
5984 */
5985 header.PageVersion = 0;
5986 header.PageLength = 0;
5987 header.PageNumber = 3;
5988 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
5989 cfg.cfghdr.hdr = &header;
5990 cfg.physAddr = -1;
5991 cfg.pageAddr = 0;
5992 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5993 cfg.dir = 0;
5994 cfg.timeout = 0;
5995 if (mpt_config(ioc, &cfg) != 0)
5996 return 0;
5997
5998 if (header.PageLength == 0)
5999 return 0;
6000
6001 /* Read Header good, alloc memory
6002 */
6003 iocpage3sz = header.PageLength * 4;
6004 pIoc3 = pci_alloc_consistent(ioc->pcidev, iocpage3sz, &ioc3_dma);
6005 if (!pIoc3)
6006 return 0;
6007
6008 /* Read the Page and save the data
6009 * into malloc'd memory.
6010 */
6011 cfg.physAddr = ioc3_dma;
6012 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6013 if (mpt_config(ioc, &cfg) == 0) {
6014 mem = kmalloc(iocpage3sz, GFP_KERNEL);
6015 if (mem) {
6016 memcpy(mem, (u8 *)pIoc3, iocpage3sz);
6017 ioc->raid_data.pIocPg3 = (IOCPage3_t *) mem;
6018 }
6019 }
6020
6021 pci_free_consistent(ioc->pcidev, iocpage3sz, pIoc3, ioc3_dma);
6022
6023 return 0;
6024}
6025
6026static void
6027mpt_read_ioc_pg_4(MPT_ADAPTER *ioc)
6028{
6029 IOCPage4_t *pIoc4;
6030 CONFIGPARMS cfg;
6031 ConfigPageHeader_t header;
6032 dma_addr_t ioc4_dma;
6033 int iocpage4sz;
6034
6035 /* Read and save IOC Page 4
6036 */
6037 header.PageVersion = 0;
6038 header.PageLength = 0;
6039 header.PageNumber = 4;
6040 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
6041 cfg.cfghdr.hdr = &header;
6042 cfg.physAddr = -1;
6043 cfg.pageAddr = 0;
6044 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6045 cfg.dir = 0;
6046 cfg.timeout = 0;
6047 if (mpt_config(ioc, &cfg) != 0)
6048 return;
6049
6050 if (header.PageLength == 0)
6051 return;
6052
6053 if ( (pIoc4 = ioc->spi_data.pIocPg4) == NULL ) {
6054 iocpage4sz = (header.PageLength + 4) * 4; /* Allow 4 additional SEP's */
6055 pIoc4 = pci_alloc_consistent(ioc->pcidev, iocpage4sz, &ioc4_dma);
6056 if (!pIoc4)
6057 return;
6058 ioc->alloc_total += iocpage4sz;
6059 } else {
6060 ioc4_dma = ioc->spi_data.IocPg4_dma;
6061 iocpage4sz = ioc->spi_data.IocPg4Sz;
6062 }
6063
6064 /* Read the Page into dma memory.
6065 */
6066 cfg.physAddr = ioc4_dma;
6067 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6068 if (mpt_config(ioc, &cfg) == 0) {
6069 ioc->spi_data.pIocPg4 = (IOCPage4_t *) pIoc4;
6070 ioc->spi_data.IocPg4_dma = ioc4_dma;
6071 ioc->spi_data.IocPg4Sz = iocpage4sz;
6072 } else {
6073 pci_free_consistent(ioc->pcidev, iocpage4sz, pIoc4, ioc4_dma);
6074 ioc->spi_data.pIocPg4 = NULL;
6075 ioc->alloc_total -= iocpage4sz;
6076 }
6077}
6078
6079static void
6080mpt_read_ioc_pg_1(MPT_ADAPTER *ioc)
6081{
6082 IOCPage1_t *pIoc1;
6083 CONFIGPARMS cfg;
6084 ConfigPageHeader_t header;
6085 dma_addr_t ioc1_dma;
6086 int iocpage1sz = 0;
6087 u32 tmp;
6088
6089 /* Check the Coalescing Timeout in IOC Page 1
6090 */
6091 header.PageVersion = 0;
6092 header.PageLength = 0;
6093 header.PageNumber = 1;
6094 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
6095 cfg.cfghdr.hdr = &header;
6096 cfg.physAddr = -1;
6097 cfg.pageAddr = 0;
6098 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6099 cfg.dir = 0;
6100 cfg.timeout = 0;
6101 if (mpt_config(ioc, &cfg) != 0)
6102 return;
6103
6104 if (header.PageLength == 0)
6105 return;
6106
6107 /* Read Header good, alloc memory
6108 */
6109 iocpage1sz = header.PageLength * 4;
6110 pIoc1 = pci_alloc_consistent(ioc->pcidev, iocpage1sz, &ioc1_dma);
6111 if (!pIoc1)
6112 return;
6113
6114 /* Read the Page and check coalescing timeout
6115 */
6116 cfg.physAddr = ioc1_dma;
6117 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6118 if (mpt_config(ioc, &cfg) == 0) {
6119
6120 tmp = le32_to_cpu(pIoc1->Flags) & MPI_IOCPAGE1_REPLY_COALESCING;
6121 if (tmp == MPI_IOCPAGE1_REPLY_COALESCING) {
6122 tmp = le32_to_cpu(pIoc1->CoalescingTimeout);
6123
6124 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Coalescing Enabled Timeout = %d\n",
6125 ioc->name, tmp));
6126
6127 if (tmp > MPT_COALESCING_TIMEOUT) {
6128 pIoc1->CoalescingTimeout = cpu_to_le32(MPT_COALESCING_TIMEOUT);
6129
6130 /* Write NVRAM and current
6131 */
6132 cfg.dir = 1;
6133 cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT;
6134 if (mpt_config(ioc, &cfg) == 0) {
6135 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Reset Current Coalescing Timeout to = %d\n",
6136 ioc->name, MPT_COALESCING_TIMEOUT));
6137
6138 cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM;
6139 if (mpt_config(ioc, &cfg) == 0) {
6140 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6141 "Reset NVRAM Coalescing Timeout to = %d\n",
6142 ioc->name, MPT_COALESCING_TIMEOUT));
6143 } else {
6144 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6145 "Reset NVRAM Coalescing Timeout Failed\n",
6146 ioc->name));
6147 }
6148
6149 } else {
6150 dprintk(ioc, printk(MYIOC_s_WARN_FMT
6151 "Reset of Current Coalescing Timeout Failed!\n",
6152 ioc->name));
6153 }
6154 }
6155
6156 } else {
6157 dprintk(ioc, printk(MYIOC_s_WARN_FMT "Coalescing Disabled\n", ioc->name));
6158 }
6159 }
6160
6161 pci_free_consistent(ioc->pcidev, iocpage1sz, pIoc1, ioc1_dma);
6162
6163 return;
6164}
6165
6166static void
6167mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc)
6168{
6169 CONFIGPARMS cfg;
6170 ConfigPageHeader_t hdr;
6171 dma_addr_t buf_dma;
6172 ManufacturingPage0_t *pbuf = NULL;
6173
6174 memset(&cfg, 0 , sizeof(CONFIGPARMS));
6175 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
6176
6177 hdr.PageType = MPI_CONFIG_PAGETYPE_MANUFACTURING;
6178 cfg.cfghdr.hdr = &hdr;
6179 cfg.physAddr = -1;
6180 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6181 cfg.timeout = 10;
6182
6183 if (mpt_config(ioc, &cfg) != 0)
6184 goto out;
6185
6186 if (!cfg.cfghdr.hdr->PageLength)
6187 goto out;
6188
6189 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6190 pbuf = pci_alloc_consistent(ioc->pcidev, hdr.PageLength * 4, &buf_dma);
6191 if (!pbuf)
6192 goto out;
6193
6194 cfg.physAddr = buf_dma;
6195
6196 if (mpt_config(ioc, &cfg) != 0)
6197 goto out;
6198
6199 memcpy(ioc->board_name, pbuf->BoardName, sizeof(ioc->board_name));
6200 memcpy(ioc->board_assembly, pbuf->BoardAssembly, sizeof(ioc->board_assembly));
6201 memcpy(ioc->board_tracer, pbuf->BoardTracerNumber, sizeof(ioc->board_tracer));
6202
6203 out:
6204
6205 if (pbuf)
6206 pci_free_consistent(ioc->pcidev, hdr.PageLength * 4, pbuf, buf_dma);
6207}
6208
6209/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6210/**
6211 * SendEventNotification - Send EventNotification (on or off) request to adapter
6212 * @ioc: Pointer to MPT_ADAPTER structure
6213 * @EvSwitch: Event switch flags
6214 * @sleepFlag: Specifies whether the process can sleep
6215 */
6216static int
6217SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch, int sleepFlag)
6218{
6219 EventNotification_t evn;
6220 MPIDefaultReply_t reply_buf;
6221
6222 memset(&evn, 0, sizeof(EventNotification_t));
6223 memset(&reply_buf, 0, sizeof(MPIDefaultReply_t));
6224
6225 evn.Function = MPI_FUNCTION_EVENT_NOTIFICATION;
6226 evn.Switch = EvSwitch;
6227 evn.MsgContext = cpu_to_le32(mpt_base_index << 16);
6228
6229 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6230 "Sending EventNotification (%d) request %p\n",
6231 ioc->name, EvSwitch, &evn));
6232
6233 return mpt_handshake_req_reply_wait(ioc, sizeof(EventNotification_t),
6234 (u32 *)&evn, sizeof(MPIDefaultReply_t), (u16 *)&reply_buf, 30,
6235 sleepFlag);
6236}
6237
6238/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6239/**
6240 * SendEventAck - Send EventAck request to MPT adapter.
6241 * @ioc: Pointer to MPT_ADAPTER structure
6242 * @evnp: Pointer to original EventNotification request
6243 */
6244static int
6245SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp)
6246{
6247 EventAck_t *pAck;
6248
6249 if ((pAck = (EventAck_t *) mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
6250 dfailprintk(ioc, printk(MYIOC_s_WARN_FMT "%s, no msg frames!!\n",
6251 ioc->name, __func__));
6252 return -1;
6253 }
6254
6255 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending EventAck\n", ioc->name));
6256
6257 pAck->Function = MPI_FUNCTION_EVENT_ACK;
6258 pAck->ChainOffset = 0;
6259 pAck->Reserved[0] = pAck->Reserved[1] = 0;
6260 pAck->MsgFlags = 0;
6261 pAck->Reserved1[0] = pAck->Reserved1[1] = pAck->Reserved1[2] = 0;
6262 pAck->Event = evnp->Event;
6263 pAck->EventContext = evnp->EventContext;
6264
6265 mpt_put_msg_frame(mpt_base_index, ioc, (MPT_FRAME_HDR *)pAck);
6266
6267 return 0;
6268}
6269
6270/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6271/**
6272 * mpt_config - Generic function to issue config message
6273 * @ioc: Pointer to an adapter structure
6274 * @pCfg: Pointer to a configuration structure. Struct contains
6275 * action, page address, direction, physical address
6276 * and pointer to a configuration page header
6277 * Page header is updated.
6278 *
6279 * Returns 0 for success
6280 * -EPERM if not allowed due to ISR context
6281 * -EAGAIN if no msg frames currently available
6282 * -EFAULT for non-successful reply or no reply (timeout)
6283 */
6284int
6285mpt_config(MPT_ADAPTER *ioc, CONFIGPARMS *pCfg)
6286{
6287 Config_t *pReq;
6288 ConfigReply_t *pReply;
6289 ConfigExtendedPageHeader_t *pExtHdr = NULL;
6290 MPT_FRAME_HDR *mf;
6291 int ii;
6292 int flagsLength;
6293 long timeout;
6294 int ret;
6295 u8 page_type = 0, extend_page;
6296 unsigned long timeleft;
6297 unsigned long flags;
6298 int in_isr;
6299 u8 issue_hard_reset = 0;
6300 u8 retry_count = 0;
6301
6302 /* Prevent calling wait_event() (below), if caller happens
6303 * to be in ISR context, because that is fatal!
6304 */
6305 in_isr = in_interrupt();
6306 if (in_isr) {
6307 dcprintk(ioc, printk(MYIOC_s_WARN_FMT "Config request not allowed in ISR context!\n",
6308 ioc->name));
6309 return -EPERM;
6310 }
6311
6312 /* don't send a config page during diag reset */
6313 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6314 if (ioc->ioc_reset_in_progress) {
6315 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6316 "%s: busy with host reset\n", ioc->name, __func__));
6317 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6318 return -EBUSY;
6319 }
6320 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6321
6322 /* don't send if no chance of success */
6323 if (!ioc->active ||
6324 mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_OPERATIONAL) {
6325 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6326 "%s: ioc not operational, %d, %xh\n",
6327 ioc->name, __func__, ioc->active,
6328 mpt_GetIocState(ioc, 0)));
6329 return -EFAULT;
6330 }
6331
6332 retry_config:
6333 mutex_lock(&ioc->mptbase_cmds.mutex);
6334 /* init the internal cmd struct */
6335 memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE);
6336 INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status)
6337
6338 /* Get and Populate a free Frame
6339 */
6340 if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
6341 dcprintk(ioc, printk(MYIOC_s_WARN_FMT
6342 "mpt_config: no msg frames!\n", ioc->name));
6343 ret = -EAGAIN;
6344 goto out;
6345 }
6346
6347 pReq = (Config_t *)mf;
6348 pReq->Action = pCfg->action;
6349 pReq->Reserved = 0;
6350 pReq->ChainOffset = 0;
6351 pReq->Function = MPI_FUNCTION_CONFIG;
6352
6353 /* Assume page type is not extended and clear "reserved" fields. */
6354 pReq->ExtPageLength = 0;
6355 pReq->ExtPageType = 0;
6356 pReq->MsgFlags = 0;
6357
6358 for (ii=0; ii < 8; ii++)
6359 pReq->Reserved2[ii] = 0;
6360
6361 pReq->Header.PageVersion = pCfg->cfghdr.hdr->PageVersion;
6362 pReq->Header.PageLength = pCfg->cfghdr.hdr->PageLength;
6363 pReq->Header.PageNumber = pCfg->cfghdr.hdr->PageNumber;
6364 pReq->Header.PageType = (pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK);
6365
6366 if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) == MPI_CONFIG_PAGETYPE_EXTENDED) {
6367 pExtHdr = (ConfigExtendedPageHeader_t *)pCfg->cfghdr.ehdr;
6368 pReq->ExtPageLength = cpu_to_le16(pExtHdr->ExtPageLength);
6369 pReq->ExtPageType = pExtHdr->ExtPageType;
6370 pReq->Header.PageType = MPI_CONFIG_PAGETYPE_EXTENDED;
6371
6372 /* Page Length must be treated as a reserved field for the
6373 * extended header.
6374 */
6375 pReq->Header.PageLength = 0;
6376 }
6377
6378 pReq->PageAddress = cpu_to_le32(pCfg->pageAddr);
6379
6380 /* Add a SGE to the config request.
6381 */
6382 if (pCfg->dir)
6383 flagsLength = MPT_SGE_FLAGS_SSIMPLE_WRITE;
6384 else
6385 flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ;
6386
6387 if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) ==
6388 MPI_CONFIG_PAGETYPE_EXTENDED) {
6389 flagsLength |= pExtHdr->ExtPageLength * 4;
6390 page_type = pReq->ExtPageType;
6391 extend_page = 1;
6392 } else {
6393 flagsLength |= pCfg->cfghdr.hdr->PageLength * 4;
6394 page_type = pReq->Header.PageType;
6395 extend_page = 0;
6396 }
6397
6398 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6399 "Sending Config request type 0x%x, page 0x%x and action %d\n",
6400 ioc->name, page_type, pReq->Header.PageNumber, pReq->Action));
6401
6402 ioc->add_sge((char *)&pReq->PageBufferSGE, flagsLength, pCfg->physAddr);
6403 timeout = (pCfg->timeout < 15) ? HZ*15 : HZ*pCfg->timeout;
6404 mpt_put_msg_frame(mpt_base_index, ioc, mf);
6405 timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done,
6406 timeout);
6407 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) {
6408 ret = -ETIME;
6409 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6410 "Failed Sending Config request type 0x%x, page 0x%x,"
6411 " action %d, status %xh, time left %ld\n\n",
6412 ioc->name, page_type, pReq->Header.PageNumber,
6413 pReq->Action, ioc->mptbase_cmds.status, timeleft));
6414 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET)
6415 goto out;
6416 if (!timeleft)
6417 issue_hard_reset = 1;
6418 goto out;
6419 }
6420
6421 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) {
6422 ret = -1;
6423 goto out;
6424 }
6425 pReply = (ConfigReply_t *)ioc->mptbase_cmds.reply;
6426 ret = le16_to_cpu(pReply->IOCStatus) & MPI_IOCSTATUS_MASK;
6427 if (ret == MPI_IOCSTATUS_SUCCESS) {
6428 if (extend_page) {
6429 pCfg->cfghdr.ehdr->ExtPageLength =
6430 le16_to_cpu(pReply->ExtPageLength);
6431 pCfg->cfghdr.ehdr->ExtPageType =
6432 pReply->ExtPageType;
6433 }
6434 pCfg->cfghdr.hdr->PageVersion = pReply->Header.PageVersion;
6435 pCfg->cfghdr.hdr->PageLength = pReply->Header.PageLength;
6436 pCfg->cfghdr.hdr->PageNumber = pReply->Header.PageNumber;
6437 pCfg->cfghdr.hdr->PageType = pReply->Header.PageType;
6438
6439 }
6440
6441 if (retry_count)
6442 printk(MYIOC_s_INFO_FMT "Retry completed "
6443 "ret=0x%x timeleft=%ld\n",
6444 ioc->name, ret, timeleft);
6445
6446 dcprintk(ioc, printk(KERN_DEBUG "IOCStatus=%04xh, IOCLogInfo=%08xh\n",
6447 ret, le32_to_cpu(pReply->IOCLogInfo)));
6448
6449out:
6450
6451 CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status)
6452 mutex_unlock(&ioc->mptbase_cmds.mutex);
6453 if (issue_hard_reset) {
6454 issue_hard_reset = 0;
6455 printk(MYIOC_s_WARN_FMT
6456 "Issuing Reset from %s!!, doorbell=0x%08x\n",
6457 ioc->name, __func__, mpt_GetIocState(ioc, 0));
6458 if (retry_count == 0) {
6459 if (mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP) != 0)
6460 retry_count++;
6461 } else
6462 mpt_HardResetHandler(ioc, CAN_SLEEP);
6463
6464 mpt_free_msg_frame(ioc, mf);
6465 /* attempt one retry for a timed out command */
6466 if (retry_count < 2) {
6467 printk(MYIOC_s_INFO_FMT
6468 "Attempting Retry Config request"
6469 " type 0x%x, page 0x%x,"
6470 " action %d\n", ioc->name, page_type,
6471 pCfg->cfghdr.hdr->PageNumber, pCfg->action);
6472 retry_count++;
6473 goto retry_config;
6474 }
6475 }
6476 return ret;
6477
6478}
6479
6480/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6481/**
6482 * mpt_ioc_reset - Base cleanup for hard reset
6483 * @ioc: Pointer to the adapter structure
6484 * @reset_phase: Indicates pre- or post-reset functionality
6485 *
6486 * Remark: Frees resources with internally generated commands.
6487 */
6488static int
6489mpt_ioc_reset(MPT_ADAPTER *ioc, int reset_phase)
6490{
6491 switch (reset_phase) {
6492 case MPT_IOC_SETUP_RESET:
6493 ioc->taskmgmt_quiesce_io = 1;
6494 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6495 "%s: MPT_IOC_SETUP_RESET\n", ioc->name, __func__));
6496 break;
6497 case MPT_IOC_PRE_RESET:
6498 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6499 "%s: MPT_IOC_PRE_RESET\n", ioc->name, __func__));
6500 break;
6501 case MPT_IOC_POST_RESET:
6502 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6503 "%s: MPT_IOC_POST_RESET\n", ioc->name, __func__));
6504/* wake up mptbase_cmds */
6505 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) {
6506 ioc->mptbase_cmds.status |=
6507 MPT_MGMT_STATUS_DID_IOCRESET;
6508 complete(&ioc->mptbase_cmds.done);
6509 }
6510/* wake up taskmgmt_cmds */
6511 if (ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_PENDING) {
6512 ioc->taskmgmt_cmds.status |=
6513 MPT_MGMT_STATUS_DID_IOCRESET;
6514 complete(&ioc->taskmgmt_cmds.done);
6515 }
6516 break;
6517 default:
6518 break;
6519 }
6520
6521 return 1; /* currently means nothing really */
6522}
6523
6524
6525#ifdef CONFIG_PROC_FS /* { */
6526/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6527/*
6528 * procfs (%MPT_PROCFS_MPTBASEDIR/...) support stuff...
6529 */
6530/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6531/**
6532 * procmpt_create - Create %MPT_PROCFS_MPTBASEDIR entries.
6533 *
6534 * Returns 0 for success, non-zero for failure.
6535 */
6536static int
6537procmpt_create(void)
6538{
6539 mpt_proc_root_dir = proc_mkdir(MPT_PROCFS_MPTBASEDIR, NULL);
6540 if (mpt_proc_root_dir == NULL)
6541 return -ENOTDIR;
6542
6543 proc_create("summary", S_IRUGO, mpt_proc_root_dir, &mpt_summary_proc_fops);
6544 proc_create("version", S_IRUGO, mpt_proc_root_dir, &mpt_version_proc_fops);
6545 return 0;
6546}
6547
6548/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6549/**
6550 * procmpt_destroy - Tear down %MPT_PROCFS_MPTBASEDIR entries.
6551 *
6552 * Returns 0 for success, non-zero for failure.
6553 */
6554static void
6555procmpt_destroy(void)
6556{
6557 remove_proc_entry("version", mpt_proc_root_dir);
6558 remove_proc_entry("summary", mpt_proc_root_dir);
6559 remove_proc_entry(MPT_PROCFS_MPTBASEDIR, NULL);
6560}
6561
6562/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6563/*
6564 * Handles read request from /proc/mpt/summary or /proc/mpt/iocN/summary.
6565 */
6566static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan);
6567
6568static int mpt_summary_proc_show(struct seq_file *m, void *v)
6569{
6570 MPT_ADAPTER *ioc = m->private;
6571
6572 if (ioc) {
6573 seq_mpt_print_ioc_summary(ioc, m, 1);
6574 } else {
6575 list_for_each_entry(ioc, &ioc_list, list) {
6576 seq_mpt_print_ioc_summary(ioc, m, 1);
6577 }
6578 }
6579
6580 return 0;
6581}
6582
6583static int mpt_summary_proc_open(struct inode *inode, struct file *file)
6584{
6585 return single_open(file, mpt_summary_proc_show, PDE(inode)->data);
6586}
6587
6588static const struct file_operations mpt_summary_proc_fops = {
6589 .owner = THIS_MODULE,
6590 .open = mpt_summary_proc_open,
6591 .read = seq_read,
6592 .llseek = seq_lseek,
6593 .release = single_release,
6594};
6595
6596static int mpt_version_proc_show(struct seq_file *m, void *v)
6597{
6598 u8 cb_idx;
6599 int scsi, fc, sas, lan, ctl, targ, dmp;
6600 char *drvname;
6601
6602 seq_printf(m, "%s-%s\n", "mptlinux", MPT_LINUX_VERSION_COMMON);
6603 seq_printf(m, " Fusion MPT base driver\n");
6604
6605 scsi = fc = sas = lan = ctl = targ = dmp = 0;
6606 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
6607 drvname = NULL;
6608 if (MptCallbacks[cb_idx]) {
6609 switch (MptDriverClass[cb_idx]) {
6610 case MPTSPI_DRIVER:
6611 if (!scsi++) drvname = "SPI host";
6612 break;
6613 case MPTFC_DRIVER:
6614 if (!fc++) drvname = "FC host";
6615 break;
6616 case MPTSAS_DRIVER:
6617 if (!sas++) drvname = "SAS host";
6618 break;
6619 case MPTLAN_DRIVER:
6620 if (!lan++) drvname = "LAN";
6621 break;
6622 case MPTSTM_DRIVER:
6623 if (!targ++) drvname = "SCSI target";
6624 break;
6625 case MPTCTL_DRIVER:
6626 if (!ctl++) drvname = "ioctl";
6627 break;
6628 }
6629
6630 if (drvname)
6631 seq_printf(m, " Fusion MPT %s driver\n", drvname);
6632 }
6633 }
6634
6635 return 0;
6636}
6637
6638static int mpt_version_proc_open(struct inode *inode, struct file *file)
6639{
6640 return single_open(file, mpt_version_proc_show, NULL);
6641}
6642
6643static const struct file_operations mpt_version_proc_fops = {
6644 .owner = THIS_MODULE,
6645 .open = mpt_version_proc_open,
6646 .read = seq_read,
6647 .llseek = seq_lseek,
6648 .release = single_release,
6649};
6650
6651static int mpt_iocinfo_proc_show(struct seq_file *m, void *v)
6652{
6653 MPT_ADAPTER *ioc = m->private;
6654 char expVer[32];
6655 int sz;
6656 int p;
6657
6658 mpt_get_fw_exp_ver(expVer, ioc);
6659
6660 seq_printf(m, "%s:", ioc->name);
6661 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)
6662 seq_printf(m, " (f/w download boot flag set)");
6663// if (ioc->facts.IOCExceptions & MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL)
6664// seq_printf(m, " CONFIG_CHECKSUM_FAIL!");
6665
6666 seq_printf(m, "\n ProductID = 0x%04x (%s)\n",
6667 ioc->facts.ProductID,
6668 ioc->prod_name);
6669 seq_printf(m, " FWVersion = 0x%08x%s", ioc->facts.FWVersion.Word, expVer);
6670 if (ioc->facts.FWImageSize)
6671 seq_printf(m, " (fw_size=%d)", ioc->facts.FWImageSize);
6672 seq_printf(m, "\n MsgVersion = 0x%04x\n", ioc->facts.MsgVersion);
6673 seq_printf(m, " FirstWhoInit = 0x%02x\n", ioc->FirstWhoInit);
6674 seq_printf(m, " EventState = 0x%02x\n", ioc->facts.EventState);
6675
6676 seq_printf(m, " CurrentHostMfaHighAddr = 0x%08x\n",
6677 ioc->facts.CurrentHostMfaHighAddr);
6678 seq_printf(m, " CurrentSenseBufferHighAddr = 0x%08x\n",
6679 ioc->facts.CurrentSenseBufferHighAddr);
6680
6681 seq_printf(m, " MaxChainDepth = 0x%02x frames\n", ioc->facts.MaxChainDepth);
6682 seq_printf(m, " MinBlockSize = 0x%02x bytes\n", 4*ioc->facts.BlockSize);
6683
6684 seq_printf(m, " RequestFrames @ 0x%p (Dma @ 0x%p)\n",
6685 (void *)ioc->req_frames, (void *)(ulong)ioc->req_frames_dma);
6686 /*
6687 * Rounding UP to nearest 4-kB boundary here...
6688 */
6689 sz = (ioc->req_sz * ioc->req_depth) + 128;
6690 sz = ((sz + 0x1000UL - 1UL) / 0x1000) * 0x1000;
6691 seq_printf(m, " {CurReqSz=%d} x {CurReqDepth=%d} = %d bytes ^= 0x%x\n",
6692 ioc->req_sz, ioc->req_depth, ioc->req_sz*ioc->req_depth, sz);
6693 seq_printf(m, " {MaxReqSz=%d} {MaxReqDepth=%d}\n",
6694 4*ioc->facts.RequestFrameSize,
6695 ioc->facts.GlobalCredits);
6696
6697 seq_printf(m, " Frames @ 0x%p (Dma @ 0x%p)\n",
6698 (void *)ioc->alloc, (void *)(ulong)ioc->alloc_dma);
6699 sz = (ioc->reply_sz * ioc->reply_depth) + 128;
6700 seq_printf(m, " {CurRepSz=%d} x {CurRepDepth=%d} = %d bytes ^= 0x%x\n",
6701 ioc->reply_sz, ioc->reply_depth, ioc->reply_sz*ioc->reply_depth, sz);
6702 seq_printf(m, " {MaxRepSz=%d} {MaxRepDepth=%d}\n",
6703 ioc->facts.CurReplyFrameSize,
6704 ioc->facts.ReplyQueueDepth);
6705
6706 seq_printf(m, " MaxDevices = %d\n",
6707 (ioc->facts.MaxDevices==0) ? 255 : ioc->facts.MaxDevices);
6708 seq_printf(m, " MaxBuses = %d\n", ioc->facts.MaxBuses);
6709
6710 /* per-port info */
6711 for (p=0; p < ioc->facts.NumberOfPorts; p++) {
6712 seq_printf(m, " PortNumber = %d (of %d)\n",
6713 p+1,
6714 ioc->facts.NumberOfPorts);
6715 if (ioc->bus_type == FC) {
6716 if (ioc->pfacts[p].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) {
6717 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
6718 seq_printf(m, " LanAddr = %02X:%02X:%02X:%02X:%02X:%02X\n",
6719 a[5], a[4], a[3], a[2], a[1], a[0]);
6720 }
6721 seq_printf(m, " WWN = %08X%08X:%08X%08X\n",
6722 ioc->fc_port_page0[p].WWNN.High,
6723 ioc->fc_port_page0[p].WWNN.Low,
6724 ioc->fc_port_page0[p].WWPN.High,
6725 ioc->fc_port_page0[p].WWPN.Low);
6726 }
6727 }
6728
6729 return 0;
6730}
6731
6732static int mpt_iocinfo_proc_open(struct inode *inode, struct file *file)
6733{
6734 return single_open(file, mpt_iocinfo_proc_show, PDE(inode)->data);
6735}
6736
6737static const struct file_operations mpt_iocinfo_proc_fops = {
6738 .owner = THIS_MODULE,
6739 .open = mpt_iocinfo_proc_open,
6740 .read = seq_read,
6741 .llseek = seq_lseek,
6742 .release = single_release,
6743};
6744#endif /* CONFIG_PROC_FS } */
6745
6746/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6747static void
6748mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc)
6749{
6750 buf[0] ='\0';
6751 if ((ioc->facts.FWVersion.Word >> 24) == 0x0E) {
6752 sprintf(buf, " (Exp %02d%02d)",
6753 (ioc->facts.FWVersion.Word >> 16) & 0x00FF, /* Month */
6754 (ioc->facts.FWVersion.Word >> 8) & 0x1F); /* Day */
6755
6756 /* insider hack! */
6757 if ((ioc->facts.FWVersion.Word >> 8) & 0x80)
6758 strcat(buf, " [MDBG]");
6759 }
6760}
6761
6762/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6763/**
6764 * mpt_print_ioc_summary - Write ASCII summary of IOC to a buffer.
6765 * @ioc: Pointer to MPT_ADAPTER structure
6766 * @buffer: Pointer to buffer where IOC summary info should be written
6767 * @size: Pointer to number of bytes we wrote (set by this routine)
6768 * @len: Offset at which to start writing in buffer
6769 * @showlan: Display LAN stuff?
6770 *
6771 * This routine writes (english readable) ASCII text, which represents
6772 * a summary of IOC information, to a buffer.
6773 */
6774void
6775mpt_print_ioc_summary(MPT_ADAPTER *ioc, char *buffer, int *size, int len, int showlan)
6776{
6777 char expVer[32];
6778 int y;
6779
6780 mpt_get_fw_exp_ver(expVer, ioc);
6781
6782 /*
6783 * Shorter summary of attached ioc's...
6784 */
6785 y = sprintf(buffer+len, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d",
6786 ioc->name,
6787 ioc->prod_name,
6788 MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */
6789 ioc->facts.FWVersion.Word,
6790 expVer,
6791 ioc->facts.NumberOfPorts,
6792 ioc->req_depth);
6793
6794 if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) {
6795 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
6796 y += sprintf(buffer+len+y, ", LanAddr=%02X:%02X:%02X:%02X:%02X:%02X",
6797 a[5], a[4], a[3], a[2], a[1], a[0]);
6798 }
6799
6800 y += sprintf(buffer+len+y, ", IRQ=%d", ioc->pci_irq);
6801
6802 if (!ioc->active)
6803 y += sprintf(buffer+len+y, " (disabled)");
6804
6805 y += sprintf(buffer+len+y, "\n");
6806
6807 *size = y;
6808}
6809
6810static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan)
6811{
6812 char expVer[32];
6813
6814 mpt_get_fw_exp_ver(expVer, ioc);
6815
6816 /*
6817 * Shorter summary of attached ioc's...
6818 */
6819 seq_printf(m, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d",
6820 ioc->name,
6821 ioc->prod_name,
6822 MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */
6823 ioc->facts.FWVersion.Word,
6824 expVer,
6825 ioc->facts.NumberOfPorts,
6826 ioc->req_depth);
6827
6828 if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) {
6829 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
6830 seq_printf(m, ", LanAddr=%02X:%02X:%02X:%02X:%02X:%02X",
6831 a[5], a[4], a[3], a[2], a[1], a[0]);
6832 }
6833
6834 seq_printf(m, ", IRQ=%d", ioc->pci_irq);
6835
6836 if (!ioc->active)
6837 seq_printf(m, " (disabled)");
6838
6839 seq_putc(m, '\n');
6840}
6841
6842/**
6843 * mpt_set_taskmgmt_in_progress_flag - set flags associated with task management
6844 * @ioc: Pointer to MPT_ADAPTER structure
6845 *
6846 * Returns 0 for SUCCESS or -1 if FAILED.
6847 *
6848 * If -1 is return, then it was not possible to set the flags
6849 **/
6850int
6851mpt_set_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc)
6852{
6853 unsigned long flags;
6854 int retval;
6855
6856 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6857 if (ioc->ioc_reset_in_progress || ioc->taskmgmt_in_progress ||
6858 (ioc->alt_ioc && ioc->alt_ioc->taskmgmt_in_progress)) {
6859 retval = -1;
6860 goto out;
6861 }
6862 retval = 0;
6863 ioc->taskmgmt_in_progress = 1;
6864 ioc->taskmgmt_quiesce_io = 1;
6865 if (ioc->alt_ioc) {
6866 ioc->alt_ioc->taskmgmt_in_progress = 1;
6867 ioc->alt_ioc->taskmgmt_quiesce_io = 1;
6868 }
6869 out:
6870 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6871 return retval;
6872}
6873EXPORT_SYMBOL(mpt_set_taskmgmt_in_progress_flag);
6874
6875/**
6876 * mpt_clear_taskmgmt_in_progress_flag - clear flags associated with task management
6877 * @ioc: Pointer to MPT_ADAPTER structure
6878 *
6879 **/
6880void
6881mpt_clear_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc)
6882{
6883 unsigned long flags;
6884
6885 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6886 ioc->taskmgmt_in_progress = 0;
6887 ioc->taskmgmt_quiesce_io = 0;
6888 if (ioc->alt_ioc) {
6889 ioc->alt_ioc->taskmgmt_in_progress = 0;
6890 ioc->alt_ioc->taskmgmt_quiesce_io = 0;
6891 }
6892 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6893}
6894EXPORT_SYMBOL(mpt_clear_taskmgmt_in_progress_flag);
6895
6896
6897/**
6898 * mpt_halt_firmware - Halts the firmware if it is operational and panic
6899 * the kernel
6900 * @ioc: Pointer to MPT_ADAPTER structure
6901 *
6902 **/
6903void
6904mpt_halt_firmware(MPT_ADAPTER *ioc)
6905{
6906 u32 ioc_raw_state;
6907
6908 ioc_raw_state = mpt_GetIocState(ioc, 0);
6909
6910 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
6911 printk(MYIOC_s_ERR_FMT "IOC is in FAULT state (%04xh)!!!\n",
6912 ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK);
6913 panic("%s: IOC Fault (%04xh)!!!\n", ioc->name,
6914 ioc_raw_state & MPI_DOORBELL_DATA_MASK);
6915 } else {
6916 CHIPREG_WRITE32(&ioc->chip->Doorbell, 0xC0FFEE00);
6917 panic("%s: Firmware is halted due to command timeout\n",
6918 ioc->name);
6919 }
6920}
6921EXPORT_SYMBOL(mpt_halt_firmware);
6922
6923/**
6924 * mpt_SoftResetHandler - Issues a less expensive reset
6925 * @ioc: Pointer to MPT_ADAPTER structure
6926 * @sleepFlag: Indicates if sleep or schedule must be called.
6927 *
6928 * Returns 0 for SUCCESS or -1 if FAILED.
6929 *
6930 * Message Unit Reset - instructs the IOC to reset the Reply Post and
6931 * Free FIFO's. All the Message Frames on Reply Free FIFO are discarded.
6932 * All posted buffers are freed, and event notification is turned off.
6933 * IOC doesn't reply to any outstanding request. This will transfer IOC
6934 * to READY state.
6935 **/
6936int
6937mpt_SoftResetHandler(MPT_ADAPTER *ioc, int sleepFlag)
6938{
6939 int rc;
6940 int ii;
6941 u8 cb_idx;
6942 unsigned long flags;
6943 u32 ioc_state;
6944 unsigned long time_count;
6945
6946 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SoftResetHandler Entered!\n",
6947 ioc->name));
6948
6949 ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK;
6950
6951 if (mpt_fwfault_debug)
6952 mpt_halt_firmware(ioc);
6953
6954 if (ioc_state == MPI_IOC_STATE_FAULT ||
6955 ioc_state == MPI_IOC_STATE_RESET) {
6956 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6957 "skipping, either in FAULT or RESET state!\n", ioc->name));
6958 return -1;
6959 }
6960
6961 if (ioc->bus_type == FC) {
6962 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6963 "skipping, because the bus type is FC!\n", ioc->name));
6964 return -1;
6965 }
6966
6967 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6968 if (ioc->ioc_reset_in_progress) {
6969 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6970 return -1;
6971 }
6972 ioc->ioc_reset_in_progress = 1;
6973 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6974
6975 rc = -1;
6976
6977 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
6978 if (MptResetHandlers[cb_idx])
6979 mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET);
6980 }
6981
6982 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6983 if (ioc->taskmgmt_in_progress) {
6984 ioc->ioc_reset_in_progress = 0;
6985 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6986 return -1;
6987 }
6988 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6989 /* Disable reply interrupts (also blocks FreeQ) */
6990 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
6991 ioc->active = 0;
6992 time_count = jiffies;
6993
6994 rc = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag);
6995
6996 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
6997 if (MptResetHandlers[cb_idx])
6998 mpt_signal_reset(cb_idx, ioc, MPT_IOC_PRE_RESET);
6999 }
7000
7001 if (rc)
7002 goto out;
7003
7004 ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK;
7005 if (ioc_state != MPI_IOC_STATE_READY)
7006 goto out;
7007
7008 for (ii = 0; ii < 5; ii++) {
7009 /* Get IOC facts! Allow 5 retries */
7010 rc = GetIocFacts(ioc, sleepFlag,
7011 MPT_HOSTEVENT_IOC_RECOVER);
7012 if (rc == 0)
7013 break;
7014 if (sleepFlag == CAN_SLEEP)
7015 msleep(100);
7016 else
7017 mdelay(100);
7018 }
7019 if (ii == 5)
7020 goto out;
7021
7022 rc = PrimeIocFifos(ioc);
7023 if (rc != 0)
7024 goto out;
7025
7026 rc = SendIocInit(ioc, sleepFlag);
7027 if (rc != 0)
7028 goto out;
7029
7030 rc = SendEventNotification(ioc, 1, sleepFlag);
7031 if (rc != 0)
7032 goto out;
7033
7034 if (ioc->hard_resets < -1)
7035 ioc->hard_resets++;
7036
7037 /*
7038 * At this point, we know soft reset succeeded.
7039 */
7040
7041 ioc->active = 1;
7042 CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM);
7043
7044 out:
7045 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7046 ioc->ioc_reset_in_progress = 0;
7047 ioc->taskmgmt_quiesce_io = 0;
7048 ioc->taskmgmt_in_progress = 0;
7049 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7050
7051 if (ioc->active) { /* otherwise, hard reset coming */
7052 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7053 if (MptResetHandlers[cb_idx])
7054 mpt_signal_reset(cb_idx, ioc,
7055 MPT_IOC_POST_RESET);
7056 }
7057 }
7058
7059 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7060 "SoftResetHandler: completed (%d seconds): %s\n",
7061 ioc->name, jiffies_to_msecs(jiffies - time_count)/1000,
7062 ((rc == 0) ? "SUCCESS" : "FAILED")));
7063
7064 return rc;
7065}
7066
7067/**
7068 * mpt_Soft_Hard_ResetHandler - Try less expensive reset
7069 * @ioc: Pointer to MPT_ADAPTER structure
7070 * @sleepFlag: Indicates if sleep or schedule must be called.
7071 *
7072 * Returns 0 for SUCCESS or -1 if FAILED.
7073 * Try for softreset first, only if it fails go for expensive
7074 * HardReset.
7075 **/
7076int
7077mpt_Soft_Hard_ResetHandler(MPT_ADAPTER *ioc, int sleepFlag) {
7078 int ret = -1;
7079
7080 ret = mpt_SoftResetHandler(ioc, sleepFlag);
7081 if (ret == 0)
7082 return ret;
7083 ret = mpt_HardResetHandler(ioc, sleepFlag);
7084 return ret;
7085}
7086EXPORT_SYMBOL(mpt_Soft_Hard_ResetHandler);
7087
7088/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7089/*
7090 * Reset Handling
7091 */
7092/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7093/**
7094 * mpt_HardResetHandler - Generic reset handler
7095 * @ioc: Pointer to MPT_ADAPTER structure
7096 * @sleepFlag: Indicates if sleep or schedule must be called.
7097 *
7098 * Issues SCSI Task Management call based on input arg values.
7099 * If TaskMgmt fails, returns associated SCSI request.
7100 *
7101 * Remark: _HardResetHandler can be invoked from an interrupt thread (timer)
7102 * or a non-interrupt thread. In the former, must not call schedule().
7103 *
7104 * Note: A return of -1 is a FATAL error case, as it means a
7105 * FW reload/initialization failed.
7106 *
7107 * Returns 0 for SUCCESS or -1 if FAILED.
7108 */
7109int
7110mpt_HardResetHandler(MPT_ADAPTER *ioc, int sleepFlag)
7111{
7112 int rc;
7113 u8 cb_idx;
7114 unsigned long flags;
7115 unsigned long time_count;
7116
7117 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HardResetHandler Entered!\n", ioc->name));
7118#ifdef MFCNT
7119 printk(MYIOC_s_INFO_FMT "HardResetHandler Entered!\n", ioc->name);
7120 printk("MF count 0x%x !\n", ioc->mfcnt);
7121#endif
7122 if (mpt_fwfault_debug)
7123 mpt_halt_firmware(ioc);
7124
7125 /* Reset the adapter. Prevent more than 1 call to
7126 * mpt_do_ioc_recovery at any instant in time.
7127 */
7128 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7129 if (ioc->ioc_reset_in_progress) {
7130 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7131 return 0;
7132 }
7133 ioc->ioc_reset_in_progress = 1;
7134 if (ioc->alt_ioc)
7135 ioc->alt_ioc->ioc_reset_in_progress = 1;
7136 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7137
7138
7139 /* The SCSI driver needs to adjust timeouts on all current
7140 * commands prior to the diagnostic reset being issued.
7141 * Prevents timeouts occurring during a diagnostic reset...very bad.
7142 * For all other protocol drivers, this is a no-op.
7143 */
7144 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7145 if (MptResetHandlers[cb_idx]) {
7146 mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET);
7147 if (ioc->alt_ioc)
7148 mpt_signal_reset(cb_idx, ioc->alt_ioc,
7149 MPT_IOC_SETUP_RESET);
7150 }
7151 }
7152
7153 time_count = jiffies;
7154 rc = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_RECOVER, sleepFlag);
7155 if (rc != 0) {
7156 printk(KERN_WARNING MYNAM
7157 ": WARNING - (%d) Cannot recover %s, doorbell=0x%08x\n",
7158 rc, ioc->name, mpt_GetIocState(ioc, 0));
7159 } else {
7160 if (ioc->hard_resets < -1)
7161 ioc->hard_resets++;
7162 }
7163
7164 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7165 ioc->ioc_reset_in_progress = 0;
7166 ioc->taskmgmt_quiesce_io = 0;
7167 ioc->taskmgmt_in_progress = 0;
7168 if (ioc->alt_ioc) {
7169 ioc->alt_ioc->ioc_reset_in_progress = 0;
7170 ioc->alt_ioc->taskmgmt_quiesce_io = 0;
7171 ioc->alt_ioc->taskmgmt_in_progress = 0;
7172 }
7173 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7174
7175 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7176 if (MptResetHandlers[cb_idx]) {
7177 mpt_signal_reset(cb_idx, ioc, MPT_IOC_POST_RESET);
7178 if (ioc->alt_ioc)
7179 mpt_signal_reset(cb_idx,
7180 ioc->alt_ioc, MPT_IOC_POST_RESET);
7181 }
7182 }
7183
7184 dtmprintk(ioc,
7185 printk(MYIOC_s_DEBUG_FMT
7186 "HardResetHandler: completed (%d seconds): %s\n", ioc->name,
7187 jiffies_to_msecs(jiffies - time_count)/1000, ((rc == 0) ?
7188 "SUCCESS" : "FAILED")));
7189
7190 return rc;
7191}
7192
7193#ifdef CONFIG_FUSION_LOGGING
7194static void
7195mpt_display_event_info(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply)
7196{
7197 char *ds = NULL;
7198 u32 evData0;
7199 int ii;
7200 u8 event;
7201 char *evStr = ioc->evStr;
7202
7203 event = le32_to_cpu(pEventReply->Event) & 0xFF;
7204 evData0 = le32_to_cpu(pEventReply->Data[0]);
7205
7206 switch(event) {
7207 case MPI_EVENT_NONE:
7208 ds = "None";
7209 break;
7210 case MPI_EVENT_LOG_DATA:
7211 ds = "Log Data";
7212 break;
7213 case MPI_EVENT_STATE_CHANGE:
7214 ds = "State Change";
7215 break;
7216 case MPI_EVENT_UNIT_ATTENTION:
7217 ds = "Unit Attention";
7218 break;
7219 case MPI_EVENT_IOC_BUS_RESET:
7220 ds = "IOC Bus Reset";
7221 break;
7222 case MPI_EVENT_EXT_BUS_RESET:
7223 ds = "External Bus Reset";
7224 break;
7225 case MPI_EVENT_RESCAN:
7226 ds = "Bus Rescan Event";
7227 break;
7228 case MPI_EVENT_LINK_STATUS_CHANGE:
7229 if (evData0 == MPI_EVENT_LINK_STATUS_FAILURE)
7230 ds = "Link Status(FAILURE) Change";
7231 else
7232 ds = "Link Status(ACTIVE) Change";
7233 break;
7234 case MPI_EVENT_LOOP_STATE_CHANGE:
7235 if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LIP)
7236 ds = "Loop State(LIP) Change";
7237 else if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LPE)
7238 ds = "Loop State(LPE) Change";
7239 else
7240 ds = "Loop State(LPB) Change";
7241 break;
7242 case MPI_EVENT_LOGOUT:
7243 ds = "Logout";
7244 break;
7245 case MPI_EVENT_EVENT_CHANGE:
7246 if (evData0)
7247 ds = "Events ON";
7248 else
7249 ds = "Events OFF";
7250 break;
7251 case MPI_EVENT_INTEGRATED_RAID:
7252 {
7253 u8 ReasonCode = (u8)(evData0 >> 16);
7254 switch (ReasonCode) {
7255 case MPI_EVENT_RAID_RC_VOLUME_CREATED :
7256 ds = "Integrated Raid: Volume Created";
7257 break;
7258 case MPI_EVENT_RAID_RC_VOLUME_DELETED :
7259 ds = "Integrated Raid: Volume Deleted";
7260 break;
7261 case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED :
7262 ds = "Integrated Raid: Volume Settings Changed";
7263 break;
7264 case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED :
7265 ds = "Integrated Raid: Volume Status Changed";
7266 break;
7267 case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED :
7268 ds = "Integrated Raid: Volume Physdisk Changed";
7269 break;
7270 case MPI_EVENT_RAID_RC_PHYSDISK_CREATED :
7271 ds = "Integrated Raid: Physdisk Created";
7272 break;
7273 case MPI_EVENT_RAID_RC_PHYSDISK_DELETED :
7274 ds = "Integrated Raid: Physdisk Deleted";
7275 break;
7276 case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED :
7277 ds = "Integrated Raid: Physdisk Settings Changed";
7278 break;
7279 case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED :
7280 ds = "Integrated Raid: Physdisk Status Changed";
7281 break;
7282 case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED :
7283 ds = "Integrated Raid: Domain Validation Needed";
7284 break;
7285 case MPI_EVENT_RAID_RC_SMART_DATA :
7286 ds = "Integrated Raid; Smart Data";
7287 break;
7288 case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED :
7289 ds = "Integrated Raid: Replace Action Started";
7290 break;
7291 default:
7292 ds = "Integrated Raid";
7293 break;
7294 }
7295 break;
7296 }
7297 case MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE:
7298 ds = "SCSI Device Status Change";
7299 break;
7300 case MPI_EVENT_SAS_DEVICE_STATUS_CHANGE:
7301 {
7302 u8 id = (u8)(evData0);
7303 u8 channel = (u8)(evData0 >> 8);
7304 u8 ReasonCode = (u8)(evData0 >> 16);
7305 switch (ReasonCode) {
7306 case MPI_EVENT_SAS_DEV_STAT_RC_ADDED:
7307 snprintf(evStr, EVENT_DESCR_STR_SZ,
7308 "SAS Device Status Change: Added: "
7309 "id=%d channel=%d", id, channel);
7310 break;
7311 case MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING:
7312 snprintf(evStr, EVENT_DESCR_STR_SZ,
7313 "SAS Device Status Change: Deleted: "
7314 "id=%d channel=%d", id, channel);
7315 break;
7316 case MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
7317 snprintf(evStr, EVENT_DESCR_STR_SZ,
7318 "SAS Device Status Change: SMART Data: "
7319 "id=%d channel=%d", id, channel);
7320 break;
7321 case MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED:
7322 snprintf(evStr, EVENT_DESCR_STR_SZ,
7323 "SAS Device Status Change: No Persistancy: "
7324 "id=%d channel=%d", id, channel);
7325 break;
7326 case MPI_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
7327 snprintf(evStr, EVENT_DESCR_STR_SZ,
7328 "SAS Device Status Change: Unsupported Device "
7329 "Discovered : id=%d channel=%d", id, channel);
7330 break;
7331 case MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
7332 snprintf(evStr, EVENT_DESCR_STR_SZ,
7333 "SAS Device Status Change: Internal Device "
7334 "Reset : id=%d channel=%d", id, channel);
7335 break;
7336 case MPI_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
7337 snprintf(evStr, EVENT_DESCR_STR_SZ,
7338 "SAS Device Status Change: Internal Task "
7339 "Abort : id=%d channel=%d", id, channel);
7340 break;
7341 case MPI_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
7342 snprintf(evStr, EVENT_DESCR_STR_SZ,
7343 "SAS Device Status Change: Internal Abort "
7344 "Task Set : id=%d channel=%d", id, channel);
7345 break;
7346 case MPI_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
7347 snprintf(evStr, EVENT_DESCR_STR_SZ,
7348 "SAS Device Status Change: Internal Clear "
7349 "Task Set : id=%d channel=%d", id, channel);
7350 break;
7351 case MPI_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
7352 snprintf(evStr, EVENT_DESCR_STR_SZ,
7353 "SAS Device Status Change: Internal Query "
7354 "Task : id=%d channel=%d", id, channel);
7355 break;
7356 default:
7357 snprintf(evStr, EVENT_DESCR_STR_SZ,
7358 "SAS Device Status Change: Unknown: "
7359 "id=%d channel=%d", id, channel);
7360 break;
7361 }
7362 break;
7363 }
7364 case MPI_EVENT_ON_BUS_TIMER_EXPIRED:
7365 ds = "Bus Timer Expired";
7366 break;
7367 case MPI_EVENT_QUEUE_FULL:
7368 {
7369 u16 curr_depth = (u16)(evData0 >> 16);
7370 u8 channel = (u8)(evData0 >> 8);
7371 u8 id = (u8)(evData0);
7372
7373 snprintf(evStr, EVENT_DESCR_STR_SZ,
7374 "Queue Full: channel=%d id=%d depth=%d",
7375 channel, id, curr_depth);
7376 break;
7377 }
7378 case MPI_EVENT_SAS_SES:
7379 ds = "SAS SES Event";
7380 break;
7381 case MPI_EVENT_PERSISTENT_TABLE_FULL:
7382 ds = "Persistent Table Full";
7383 break;
7384 case MPI_EVENT_SAS_PHY_LINK_STATUS:
7385 {
7386 u8 LinkRates = (u8)(evData0 >> 8);
7387 u8 PhyNumber = (u8)(evData0);
7388 LinkRates = (LinkRates & MPI_EVENT_SAS_PLS_LR_CURRENT_MASK) >>
7389 MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT;
7390 switch (LinkRates) {
7391 case MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN:
7392 snprintf(evStr, EVENT_DESCR_STR_SZ,
7393 "SAS PHY Link Status: Phy=%d:"
7394 " Rate Unknown",PhyNumber);
7395 break;
7396 case MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED:
7397 snprintf(evStr, EVENT_DESCR_STR_SZ,
7398 "SAS PHY Link Status: Phy=%d:"
7399 " Phy Disabled",PhyNumber);
7400 break;
7401 case MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION:
7402 snprintf(evStr, EVENT_DESCR_STR_SZ,
7403 "SAS PHY Link Status: Phy=%d:"
7404 " Failed Speed Nego",PhyNumber);
7405 break;
7406 case MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE:
7407 snprintf(evStr, EVENT_DESCR_STR_SZ,
7408 "SAS PHY Link Status: Phy=%d:"
7409 " Sata OOB Completed",PhyNumber);
7410 break;
7411 case MPI_EVENT_SAS_PLS_LR_RATE_1_5:
7412 snprintf(evStr, EVENT_DESCR_STR_SZ,
7413 "SAS PHY Link Status: Phy=%d:"
7414 " Rate 1.5 Gbps",PhyNumber);
7415 break;
7416 case MPI_EVENT_SAS_PLS_LR_RATE_3_0:
7417 snprintf(evStr, EVENT_DESCR_STR_SZ,
7418 "SAS PHY Link Status: Phy=%d:"
7419 " Rate 3.0 Gbps", PhyNumber);
7420 break;
7421 case MPI_EVENT_SAS_PLS_LR_RATE_6_0:
7422 snprintf(evStr, EVENT_DESCR_STR_SZ,
7423 "SAS PHY Link Status: Phy=%d:"
7424 " Rate 6.0 Gbps", PhyNumber);
7425 break;
7426 default:
7427 snprintf(evStr, EVENT_DESCR_STR_SZ,
7428 "SAS PHY Link Status: Phy=%d", PhyNumber);
7429 break;
7430 }
7431 break;
7432 }
7433 case MPI_EVENT_SAS_DISCOVERY_ERROR:
7434 ds = "SAS Discovery Error";
7435 break;
7436 case MPI_EVENT_IR_RESYNC_UPDATE:
7437 {
7438 u8 resync_complete = (u8)(evData0 >> 16);
7439 snprintf(evStr, EVENT_DESCR_STR_SZ,
7440 "IR Resync Update: Complete = %d:",resync_complete);
7441 break;
7442 }
7443 case MPI_EVENT_IR2:
7444 {
7445 u8 id = (u8)(evData0);
7446 u8 channel = (u8)(evData0 >> 8);
7447 u8 phys_num = (u8)(evData0 >> 24);
7448 u8 ReasonCode = (u8)(evData0 >> 16);
7449
7450 switch (ReasonCode) {
7451 case MPI_EVENT_IR2_RC_LD_STATE_CHANGED:
7452 snprintf(evStr, EVENT_DESCR_STR_SZ,
7453 "IR2: LD State Changed: "
7454 "id=%d channel=%d phys_num=%d",
7455 id, channel, phys_num);
7456 break;
7457 case MPI_EVENT_IR2_RC_PD_STATE_CHANGED:
7458 snprintf(evStr, EVENT_DESCR_STR_SZ,
7459 "IR2: PD State Changed "
7460 "id=%d channel=%d phys_num=%d",
7461 id, channel, phys_num);
7462 break;
7463 case MPI_EVENT_IR2_RC_BAD_BLOCK_TABLE_FULL:
7464 snprintf(evStr, EVENT_DESCR_STR_SZ,
7465 "IR2: Bad Block Table Full: "
7466 "id=%d channel=%d phys_num=%d",
7467 id, channel, phys_num);
7468 break;
7469 case MPI_EVENT_IR2_RC_PD_INSERTED:
7470 snprintf(evStr, EVENT_DESCR_STR_SZ,
7471 "IR2: PD Inserted: "
7472 "id=%d channel=%d phys_num=%d",
7473 id, channel, phys_num);
7474 break;
7475 case MPI_EVENT_IR2_RC_PD_REMOVED:
7476 snprintf(evStr, EVENT_DESCR_STR_SZ,
7477 "IR2: PD Removed: "
7478 "id=%d channel=%d phys_num=%d",
7479 id, channel, phys_num);
7480 break;
7481 case MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED:
7482 snprintf(evStr, EVENT_DESCR_STR_SZ,
7483 "IR2: Foreign CFG Detected: "
7484 "id=%d channel=%d phys_num=%d",
7485 id, channel, phys_num);
7486 break;
7487 case MPI_EVENT_IR2_RC_REBUILD_MEDIUM_ERROR:
7488 snprintf(evStr, EVENT_DESCR_STR_SZ,
7489 "IR2: Rebuild Medium Error: "
7490 "id=%d channel=%d phys_num=%d",
7491 id, channel, phys_num);
7492 break;
7493 case MPI_EVENT_IR2_RC_DUAL_PORT_ADDED:
7494 snprintf(evStr, EVENT_DESCR_STR_SZ,
7495 "IR2: Dual Port Added: "
7496 "id=%d channel=%d phys_num=%d",
7497 id, channel, phys_num);
7498 break;
7499 case MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED:
7500 snprintf(evStr, EVENT_DESCR_STR_SZ,
7501 "IR2: Dual Port Removed: "
7502 "id=%d channel=%d phys_num=%d",
7503 id, channel, phys_num);
7504 break;
7505 default:
7506 ds = "IR2";
7507 break;
7508 }
7509 break;
7510 }
7511 case MPI_EVENT_SAS_DISCOVERY:
7512 {
7513 if (evData0)
7514 ds = "SAS Discovery: Start";
7515 else
7516 ds = "SAS Discovery: Stop";
7517 break;
7518 }
7519 case MPI_EVENT_LOG_ENTRY_ADDED:
7520 ds = "SAS Log Entry Added";
7521 break;
7522
7523 case MPI_EVENT_SAS_BROADCAST_PRIMITIVE:
7524 {
7525 u8 phy_num = (u8)(evData0);
7526 u8 port_num = (u8)(evData0 >> 8);
7527 u8 port_width = (u8)(evData0 >> 16);
7528 u8 primative = (u8)(evData0 >> 24);
7529 snprintf(evStr, EVENT_DESCR_STR_SZ,
7530 "SAS Broadcase Primative: phy=%d port=%d "
7531 "width=%d primative=0x%02x",
7532 phy_num, port_num, port_width, primative);
7533 break;
7534 }
7535
7536 case MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
7537 {
7538 u8 reason = (u8)(evData0);
7539
7540 switch (reason) {
7541 case MPI_EVENT_SAS_INIT_RC_ADDED:
7542 ds = "SAS Initiator Status Change: Added";
7543 break;
7544 case MPI_EVENT_SAS_INIT_RC_REMOVED:
7545 ds = "SAS Initiator Status Change: Deleted";
7546 break;
7547 default:
7548 ds = "SAS Initiator Status Change";
7549 break;
7550 }
7551 break;
7552 }
7553
7554 case MPI_EVENT_SAS_INIT_TABLE_OVERFLOW:
7555 {
7556 u8 max_init = (u8)(evData0);
7557 u8 current_init = (u8)(evData0 >> 8);
7558
7559 snprintf(evStr, EVENT_DESCR_STR_SZ,
7560 "SAS Initiator Device Table Overflow: max initiators=%02d "
7561 "current initators=%02d",
7562 max_init, current_init);
7563 break;
7564 }
7565 case MPI_EVENT_SAS_SMP_ERROR:
7566 {
7567 u8 status = (u8)(evData0);
7568 u8 port_num = (u8)(evData0 >> 8);
7569 u8 result = (u8)(evData0 >> 16);
7570
7571 if (status == MPI_EVENT_SAS_SMP_FUNCTION_RESULT_VALID)
7572 snprintf(evStr, EVENT_DESCR_STR_SZ,
7573 "SAS SMP Error: port=%d result=0x%02x",
7574 port_num, result);
7575 else if (status == MPI_EVENT_SAS_SMP_CRC_ERROR)
7576 snprintf(evStr, EVENT_DESCR_STR_SZ,
7577 "SAS SMP Error: port=%d : CRC Error",
7578 port_num);
7579 else if (status == MPI_EVENT_SAS_SMP_TIMEOUT)
7580 snprintf(evStr, EVENT_DESCR_STR_SZ,
7581 "SAS SMP Error: port=%d : Timeout",
7582 port_num);
7583 else if (status == MPI_EVENT_SAS_SMP_NO_DESTINATION)
7584 snprintf(evStr, EVENT_DESCR_STR_SZ,
7585 "SAS SMP Error: port=%d : No Destination",
7586 port_num);
7587 else if (status == MPI_EVENT_SAS_SMP_BAD_DESTINATION)
7588 snprintf(evStr, EVENT_DESCR_STR_SZ,
7589 "SAS SMP Error: port=%d : Bad Destination",
7590 port_num);
7591 else
7592 snprintf(evStr, EVENT_DESCR_STR_SZ,
7593 "SAS SMP Error: port=%d : status=0x%02x",
7594 port_num, status);
7595 break;
7596 }
7597
7598 case MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE:
7599 {
7600 u8 reason = (u8)(evData0);
7601
7602 switch (reason) {
7603 case MPI_EVENT_SAS_EXP_RC_ADDED:
7604 ds = "Expander Status Change: Added";
7605 break;
7606 case MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING:
7607 ds = "Expander Status Change: Deleted";
7608 break;
7609 default:
7610 ds = "Expander Status Change";
7611 break;
7612 }
7613 break;
7614 }
7615
7616 /*
7617 * MPT base "custom" events may be added here...
7618 */
7619 default:
7620 ds = "Unknown";
7621 break;
7622 }
7623 if (ds)
7624 strncpy(evStr, ds, EVENT_DESCR_STR_SZ);
7625
7626
7627 devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7628 "MPT event:(%02Xh) : %s\n",
7629 ioc->name, event, evStr));
7630
7631 devtverboseprintk(ioc, printk(KERN_DEBUG MYNAM
7632 ": Event data:\n"));
7633 for (ii = 0; ii < le16_to_cpu(pEventReply->EventDataLength); ii++)
7634 devtverboseprintk(ioc, printk(" %08x",
7635 le32_to_cpu(pEventReply->Data[ii])));
7636 devtverboseprintk(ioc, printk(KERN_DEBUG "\n"));
7637}
7638#endif
7639/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7640/**
7641 * ProcessEventNotification - Route EventNotificationReply to all event handlers
7642 * @ioc: Pointer to MPT_ADAPTER structure
7643 * @pEventReply: Pointer to EventNotification reply frame
7644 * @evHandlers: Pointer to integer, number of event handlers
7645 *
7646 * Routes a received EventNotificationReply to all currently registered
7647 * event handlers.
7648 * Returns sum of event handlers return values.
7649 */
7650static int
7651ProcessEventNotification(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply, int *evHandlers)
7652{
7653 u16 evDataLen;
7654 u32 evData0 = 0;
7655 int ii;
7656 u8 cb_idx;
7657 int r = 0;
7658 int handlers = 0;
7659 u8 event;
7660
7661 /*
7662 * Do platform normalization of values
7663 */
7664 event = le32_to_cpu(pEventReply->Event) & 0xFF;
7665 evDataLen = le16_to_cpu(pEventReply->EventDataLength);
7666 if (evDataLen) {
7667 evData0 = le32_to_cpu(pEventReply->Data[0]);
7668 }
7669
7670#ifdef CONFIG_FUSION_LOGGING
7671 if (evDataLen)
7672 mpt_display_event_info(ioc, pEventReply);
7673#endif
7674
7675 /*
7676 * Do general / base driver event processing
7677 */
7678 switch(event) {
7679 case MPI_EVENT_EVENT_CHANGE: /* 0A */
7680 if (evDataLen) {
7681 u8 evState = evData0 & 0xFF;
7682
7683 /* CHECKME! What if evState unexpectedly says OFF (0)? */
7684
7685 /* Update EventState field in cached IocFacts */
7686 if (ioc->facts.Function) {
7687 ioc->facts.EventState = evState;
7688 }
7689 }
7690 break;
7691 case MPI_EVENT_INTEGRATED_RAID:
7692 mptbase_raid_process_event_data(ioc,
7693 (MpiEventDataRaid_t *)pEventReply->Data);
7694 break;
7695 default:
7696 break;
7697 }
7698
7699 /*
7700 * Should this event be logged? Events are written sequentially.
7701 * When buffer is full, start again at the top.
7702 */
7703 if (ioc->events && (ioc->eventTypes & ( 1 << event))) {
7704 int idx;
7705
7706 idx = ioc->eventContext % MPTCTL_EVENT_LOG_SIZE;
7707
7708 ioc->events[idx].event = event;
7709 ioc->events[idx].eventContext = ioc->eventContext;
7710
7711 for (ii = 0; ii < 2; ii++) {
7712 if (ii < evDataLen)
7713 ioc->events[idx].data[ii] = le32_to_cpu(pEventReply->Data[ii]);
7714 else
7715 ioc->events[idx].data[ii] = 0;
7716 }
7717
7718 ioc->eventContext++;
7719 }
7720
7721
7722 /*
7723 * Call each currently registered protocol event handler.
7724 */
7725 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7726 if (MptEvHandlers[cb_idx]) {
7727 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7728 "Routing Event to event handler #%d\n",
7729 ioc->name, cb_idx));
7730 r += (*(MptEvHandlers[cb_idx]))(ioc, pEventReply);
7731 handlers++;
7732 }
7733 }
7734 /* FIXME? Examine results here? */
7735
7736 /*
7737 * If needed, send (a single) EventAck.
7738 */
7739 if (pEventReply->AckRequired == MPI_EVENT_NOTIFICATION_ACK_REQUIRED) {
7740 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7741 "EventAck required\n",ioc->name));
7742 if ((ii = SendEventAck(ioc, pEventReply)) != 0) {
7743 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SendEventAck returned %d\n",
7744 ioc->name, ii));
7745 }
7746 }
7747
7748 *evHandlers = handlers;
7749 return r;
7750}
7751
7752/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7753/**
7754 * mpt_fc_log_info - Log information returned from Fibre Channel IOC.
7755 * @ioc: Pointer to MPT_ADAPTER structure
7756 * @log_info: U32 LogInfo reply word from the IOC
7757 *
7758 * Refer to lsi/mpi_log_fc.h.
7759 */
7760static void
7761mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info)
7762{
7763 char *desc = "unknown";
7764
7765 switch (log_info & 0xFF000000) {
7766 case MPI_IOCLOGINFO_FC_INIT_BASE:
7767 desc = "FCP Initiator";
7768 break;
7769 case MPI_IOCLOGINFO_FC_TARGET_BASE:
7770 desc = "FCP Target";
7771 break;
7772 case MPI_IOCLOGINFO_FC_LAN_BASE:
7773 desc = "LAN";
7774 break;
7775 case MPI_IOCLOGINFO_FC_MSG_BASE:
7776 desc = "MPI Message Layer";
7777 break;
7778 case MPI_IOCLOGINFO_FC_LINK_BASE:
7779 desc = "FC Link";
7780 break;
7781 case MPI_IOCLOGINFO_FC_CTX_BASE:
7782 desc = "Context Manager";
7783 break;
7784 case MPI_IOCLOGINFO_FC_INVALID_FIELD_BYTE_OFFSET:
7785 desc = "Invalid Field Offset";
7786 break;
7787 case MPI_IOCLOGINFO_FC_STATE_CHANGE:
7788 desc = "State Change Info";
7789 break;
7790 }
7791
7792 printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): SubClass={%s}, Value=(0x%06x)\n",
7793 ioc->name, log_info, desc, (log_info & 0xFFFFFF));
7794}
7795
7796/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7797/**
7798 * mpt_spi_log_info - Log information returned from SCSI Parallel IOC.
7799 * @ioc: Pointer to MPT_ADAPTER structure
7800 * @log_info: U32 LogInfo word from the IOC
7801 *
7802 * Refer to lsi/sp_log.h.
7803 */
7804static void
7805mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info)
7806{
7807 u32 info = log_info & 0x00FF0000;
7808 char *desc = "unknown";
7809
7810 switch (info) {
7811 case 0x00010000:
7812 desc = "bug! MID not found";
7813 break;
7814
7815 case 0x00020000:
7816 desc = "Parity Error";
7817 break;
7818
7819 case 0x00030000:
7820 desc = "ASYNC Outbound Overrun";
7821 break;
7822
7823 case 0x00040000:
7824 desc = "SYNC Offset Error";
7825 break;
7826
7827 case 0x00050000:
7828 desc = "BM Change";
7829 break;
7830
7831 case 0x00060000:
7832 desc = "Msg In Overflow";
7833 break;
7834
7835 case 0x00070000:
7836 desc = "DMA Error";
7837 break;
7838
7839 case 0x00080000:
7840 desc = "Outbound DMA Overrun";
7841 break;
7842
7843 case 0x00090000:
7844 desc = "Task Management";
7845 break;
7846
7847 case 0x000A0000:
7848 desc = "Device Problem";
7849 break;
7850
7851 case 0x000B0000:
7852 desc = "Invalid Phase Change";
7853 break;
7854
7855 case 0x000C0000:
7856 desc = "Untagged Table Size";
7857 break;
7858
7859 }
7860
7861 printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): F/W: %s\n", ioc->name, log_info, desc);
7862}
7863
7864/* strings for sas loginfo */
7865 static char *originator_str[] = {
7866 "IOP", /* 00h */
7867 "PL", /* 01h */
7868 "IR" /* 02h */
7869 };
7870 static char *iop_code_str[] = {
7871 NULL, /* 00h */
7872 "Invalid SAS Address", /* 01h */
7873 NULL, /* 02h */
7874 "Invalid Page", /* 03h */
7875 "Diag Message Error", /* 04h */
7876 "Task Terminated", /* 05h */
7877 "Enclosure Management", /* 06h */
7878 "Target Mode" /* 07h */
7879 };
7880 static char *pl_code_str[] = {
7881 NULL, /* 00h */
7882 "Open Failure", /* 01h */
7883 "Invalid Scatter Gather List", /* 02h */
7884 "Wrong Relative Offset or Frame Length", /* 03h */
7885 "Frame Transfer Error", /* 04h */
7886 "Transmit Frame Connected Low", /* 05h */
7887 "SATA Non-NCQ RW Error Bit Set", /* 06h */
7888 "SATA Read Log Receive Data Error", /* 07h */
7889 "SATA NCQ Fail All Commands After Error", /* 08h */
7890 "SATA Error in Receive Set Device Bit FIS", /* 09h */
7891 "Receive Frame Invalid Message", /* 0Ah */
7892 "Receive Context Message Valid Error", /* 0Bh */
7893 "Receive Frame Current Frame Error", /* 0Ch */
7894 "SATA Link Down", /* 0Dh */
7895 "Discovery SATA Init W IOS", /* 0Eh */
7896 "Config Invalid Page", /* 0Fh */
7897 "Discovery SATA Init Timeout", /* 10h */
7898 "Reset", /* 11h */
7899 "Abort", /* 12h */
7900 "IO Not Yet Executed", /* 13h */
7901 "IO Executed", /* 14h */
7902 "Persistent Reservation Out Not Affiliation "
7903 "Owner", /* 15h */
7904 "Open Transmit DMA Abort", /* 16h */
7905 "IO Device Missing Delay Retry", /* 17h */
7906 "IO Cancelled Due to Receive Error", /* 18h */
7907 NULL, /* 19h */
7908 NULL, /* 1Ah */
7909 NULL, /* 1Bh */
7910 NULL, /* 1Ch */
7911 NULL, /* 1Dh */
7912 NULL, /* 1Eh */
7913 NULL, /* 1Fh */
7914 "Enclosure Management" /* 20h */
7915 };
7916 static char *ir_code_str[] = {
7917 "Raid Action Error", /* 00h */
7918 NULL, /* 00h */
7919 NULL, /* 01h */
7920 NULL, /* 02h */
7921 NULL, /* 03h */
7922 NULL, /* 04h */
7923 NULL, /* 05h */
7924 NULL, /* 06h */
7925 NULL /* 07h */
7926 };
7927 static char *raid_sub_code_str[] = {
7928 NULL, /* 00h */
7929 "Volume Creation Failed: Data Passed too "
7930 "Large", /* 01h */
7931 "Volume Creation Failed: Duplicate Volumes "
7932 "Attempted", /* 02h */
7933 "Volume Creation Failed: Max Number "
7934 "Supported Volumes Exceeded", /* 03h */
7935 "Volume Creation Failed: DMA Error", /* 04h */
7936 "Volume Creation Failed: Invalid Volume Type", /* 05h */
7937 "Volume Creation Failed: Error Reading "
7938 "MFG Page 4", /* 06h */
7939 "Volume Creation Failed: Creating Internal "
7940 "Structures", /* 07h */
7941 NULL, /* 08h */
7942 NULL, /* 09h */
7943 NULL, /* 0Ah */
7944 NULL, /* 0Bh */
7945 NULL, /* 0Ch */
7946 NULL, /* 0Dh */
7947 NULL, /* 0Eh */
7948 NULL, /* 0Fh */
7949 "Activation failed: Already Active Volume", /* 10h */
7950 "Activation failed: Unsupported Volume Type", /* 11h */
7951 "Activation failed: Too Many Active Volumes", /* 12h */
7952 "Activation failed: Volume ID in Use", /* 13h */
7953 "Activation failed: Reported Failure", /* 14h */
7954 "Activation failed: Importing a Volume", /* 15h */
7955 NULL, /* 16h */
7956 NULL, /* 17h */
7957 NULL, /* 18h */
7958 NULL, /* 19h */
7959 NULL, /* 1Ah */
7960 NULL, /* 1Bh */
7961 NULL, /* 1Ch */
7962 NULL, /* 1Dh */
7963 NULL, /* 1Eh */
7964 NULL, /* 1Fh */
7965 "Phys Disk failed: Too Many Phys Disks", /* 20h */
7966 "Phys Disk failed: Data Passed too Large", /* 21h */
7967 "Phys Disk failed: DMA Error", /* 22h */
7968 "Phys Disk failed: Invalid <channel:id>", /* 23h */
7969 "Phys Disk failed: Creating Phys Disk Config "
7970 "Page", /* 24h */
7971 NULL, /* 25h */
7972 NULL, /* 26h */
7973 NULL, /* 27h */
7974 NULL, /* 28h */
7975 NULL, /* 29h */
7976 NULL, /* 2Ah */
7977 NULL, /* 2Bh */
7978 NULL, /* 2Ch */
7979 NULL, /* 2Dh */
7980 NULL, /* 2Eh */
7981 NULL, /* 2Fh */
7982 "Compatibility Error: IR Disabled", /* 30h */
7983 "Compatibility Error: Inquiry Command Failed", /* 31h */
7984 "Compatibility Error: Device not Direct Access "
7985 "Device ", /* 32h */
7986 "Compatibility Error: Removable Device Found", /* 33h */
7987 "Compatibility Error: Device SCSI Version not "
7988 "2 or Higher", /* 34h */
7989 "Compatibility Error: SATA Device, 48 BIT LBA "
7990 "not Supported", /* 35h */
7991 "Compatibility Error: Device doesn't have "
7992 "512 Byte Block Sizes", /* 36h */
7993 "Compatibility Error: Volume Type Check Failed", /* 37h */
7994 "Compatibility Error: Volume Type is "
7995 "Unsupported by FW", /* 38h */
7996 "Compatibility Error: Disk Drive too Small for "
7997 "use in Volume", /* 39h */
7998 "Compatibility Error: Phys Disk for Create "
7999 "Volume not Found", /* 3Ah */
8000 "Compatibility Error: Too Many or too Few "
8001 "Disks for Volume Type", /* 3Bh */
8002 "Compatibility Error: Disk stripe Sizes "
8003 "Must be 64KB", /* 3Ch */
8004 "Compatibility Error: IME Size Limited to < 2TB", /* 3Dh */
8005 };
8006
8007/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8008/**
8009 * mpt_sas_log_info - Log information returned from SAS IOC.
8010 * @ioc: Pointer to MPT_ADAPTER structure
8011 * @log_info: U32 LogInfo reply word from the IOC
8012 * @cb_idx: callback function's handle
8013 *
8014 * Refer to lsi/mpi_log_sas.h.
8015 **/
8016static void
8017mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info, u8 cb_idx)
8018{
8019union loginfo_type {
8020 u32 loginfo;
8021 struct {
8022 u32 subcode:16;
8023 u32 code:8;
8024 u32 originator:4;
8025 u32 bus_type:4;
8026 }dw;
8027};
8028 union loginfo_type sas_loginfo;
8029 char *originator_desc = NULL;
8030 char *code_desc = NULL;
8031 char *sub_code_desc = NULL;
8032
8033 sas_loginfo.loginfo = log_info;
8034 if ((sas_loginfo.dw.bus_type != 3 /*SAS*/) &&
8035 (sas_loginfo.dw.originator < ARRAY_SIZE(originator_str)))
8036 return;
8037
8038 originator_desc = originator_str[sas_loginfo.dw.originator];
8039
8040 switch (sas_loginfo.dw.originator) {
8041
8042 case 0: /* IOP */
8043 if (sas_loginfo.dw.code <
8044 ARRAY_SIZE(iop_code_str))
8045 code_desc = iop_code_str[sas_loginfo.dw.code];
8046 break;
8047 case 1: /* PL */
8048 if (sas_loginfo.dw.code <
8049 ARRAY_SIZE(pl_code_str))
8050 code_desc = pl_code_str[sas_loginfo.dw.code];
8051 break;
8052 case 2: /* IR */
8053 if (sas_loginfo.dw.code >=
8054 ARRAY_SIZE(ir_code_str))
8055 break;
8056 code_desc = ir_code_str[sas_loginfo.dw.code];
8057 if (sas_loginfo.dw.subcode >=
8058 ARRAY_SIZE(raid_sub_code_str))
8059 break;
8060 if (sas_loginfo.dw.code == 0)
8061 sub_code_desc =
8062 raid_sub_code_str[sas_loginfo.dw.subcode];
8063 break;
8064 default:
8065 return;
8066 }
8067
8068 if (sub_code_desc != NULL)
8069 printk(MYIOC_s_INFO_FMT
8070 "LogInfo(0x%08x): Originator={%s}, Code={%s},"
8071 " SubCode={%s} cb_idx %s\n",
8072 ioc->name, log_info, originator_desc, code_desc,
8073 sub_code_desc, MptCallbacksName[cb_idx]);
8074 else if (code_desc != NULL)
8075 printk(MYIOC_s_INFO_FMT
8076 "LogInfo(0x%08x): Originator={%s}, Code={%s},"
8077 " SubCode(0x%04x) cb_idx %s\n",
8078 ioc->name, log_info, originator_desc, code_desc,
8079 sas_loginfo.dw.subcode, MptCallbacksName[cb_idx]);
8080 else
8081 printk(MYIOC_s_INFO_FMT
8082 "LogInfo(0x%08x): Originator={%s}, Code=(0x%02x),"
8083 " SubCode(0x%04x) cb_idx %s\n",
8084 ioc->name, log_info, originator_desc,
8085 sas_loginfo.dw.code, sas_loginfo.dw.subcode,
8086 MptCallbacksName[cb_idx]);
8087}
8088
8089/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8090/**
8091 * mpt_iocstatus_info_config - IOCSTATUS information for config pages
8092 * @ioc: Pointer to MPT_ADAPTER structure
8093 * @ioc_status: U32 IOCStatus word from IOC
8094 * @mf: Pointer to MPT request frame
8095 *
8096 * Refer to lsi/mpi.h.
8097 **/
8098static void
8099mpt_iocstatus_info_config(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf)
8100{
8101 Config_t *pReq = (Config_t *)mf;
8102 char extend_desc[EVENT_DESCR_STR_SZ];
8103 char *desc = NULL;
8104 u32 form;
8105 u8 page_type;
8106
8107 if (pReq->Header.PageType == MPI_CONFIG_PAGETYPE_EXTENDED)
8108 page_type = pReq->ExtPageType;
8109 else
8110 page_type = pReq->Header.PageType;
8111
8112 /*
8113 * ignore invalid page messages for GET_NEXT_HANDLE
8114 */
8115 form = le32_to_cpu(pReq->PageAddress);
8116 if (ioc_status == MPI_IOCSTATUS_CONFIG_INVALID_PAGE) {
8117 if (page_type == MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE ||
8118 page_type == MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER ||
8119 page_type == MPI_CONFIG_EXTPAGETYPE_ENCLOSURE) {
8120 if ((form >> MPI_SAS_DEVICE_PGAD_FORM_SHIFT) ==
8121 MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE)
8122 return;
8123 }
8124 if (page_type == MPI_CONFIG_PAGETYPE_FC_DEVICE)
8125 if ((form & MPI_FC_DEVICE_PGAD_FORM_MASK) ==
8126 MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
8127 return;
8128 }
8129
8130 snprintf(extend_desc, EVENT_DESCR_STR_SZ,
8131 "type=%02Xh, page=%02Xh, action=%02Xh, form=%08Xh",
8132 page_type, pReq->Header.PageNumber, pReq->Action, form);
8133
8134 switch (ioc_status) {
8135
8136 case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */
8137 desc = "Config Page Invalid Action";
8138 break;
8139
8140 case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */
8141 desc = "Config Page Invalid Type";
8142 break;
8143
8144 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */
8145 desc = "Config Page Invalid Page";
8146 break;
8147
8148 case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */
8149 desc = "Config Page Invalid Data";
8150 break;
8151
8152 case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */
8153 desc = "Config Page No Defaults";
8154 break;
8155
8156 case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */
8157 desc = "Config Page Can't Commit";
8158 break;
8159 }
8160
8161 if (!desc)
8162 return;
8163
8164 dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s: %s\n",
8165 ioc->name, ioc_status, desc, extend_desc));
8166}
8167
8168/**
8169 * mpt_iocstatus_info - IOCSTATUS information returned from IOC.
8170 * @ioc: Pointer to MPT_ADAPTER structure
8171 * @ioc_status: U32 IOCStatus word from IOC
8172 * @mf: Pointer to MPT request frame
8173 *
8174 * Refer to lsi/mpi.h.
8175 **/
8176static void
8177mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf)
8178{
8179 u32 status = ioc_status & MPI_IOCSTATUS_MASK;
8180 char *desc = NULL;
8181
8182 switch (status) {
8183
8184/****************************************************************************/
8185/* Common IOCStatus values for all replies */
8186/****************************************************************************/
8187
8188 case MPI_IOCSTATUS_INVALID_FUNCTION: /* 0x0001 */
8189 desc = "Invalid Function";
8190 break;
8191
8192 case MPI_IOCSTATUS_BUSY: /* 0x0002 */
8193 desc = "Busy";
8194 break;
8195
8196 case MPI_IOCSTATUS_INVALID_SGL: /* 0x0003 */
8197 desc = "Invalid SGL";
8198 break;
8199
8200 case MPI_IOCSTATUS_INTERNAL_ERROR: /* 0x0004 */
8201 desc = "Internal Error";
8202 break;
8203
8204 case MPI_IOCSTATUS_RESERVED: /* 0x0005 */
8205 desc = "Reserved";
8206 break;
8207
8208 case MPI_IOCSTATUS_INSUFFICIENT_RESOURCES: /* 0x0006 */
8209 desc = "Insufficient Resources";
8210 break;
8211
8212 case MPI_IOCSTATUS_INVALID_FIELD: /* 0x0007 */
8213 desc = "Invalid Field";
8214 break;
8215
8216 case MPI_IOCSTATUS_INVALID_STATE: /* 0x0008 */
8217 desc = "Invalid State";
8218 break;
8219
8220/****************************************************************************/
8221/* Config IOCStatus values */
8222/****************************************************************************/
8223
8224 case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */
8225 case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */
8226 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */
8227 case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */
8228 case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */
8229 case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */
8230 mpt_iocstatus_info_config(ioc, status, mf);
8231 break;
8232
8233/****************************************************************************/
8234/* SCSIIO Reply (SPI, FCP, SAS) initiator values */
8235/* */
8236/* Look at mptscsih_iocstatus_info_scsiio in mptscsih.c */
8237/* */
8238/****************************************************************************/
8239
8240 case MPI_IOCSTATUS_SCSI_RECOVERED_ERROR: /* 0x0040 */
8241 case MPI_IOCSTATUS_SCSI_DATA_UNDERRUN: /* 0x0045 */
8242 case MPI_IOCSTATUS_SCSI_INVALID_BUS: /* 0x0041 */
8243 case MPI_IOCSTATUS_SCSI_INVALID_TARGETID: /* 0x0042 */
8244 case MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE: /* 0x0043 */
8245 case MPI_IOCSTATUS_SCSI_DATA_OVERRUN: /* 0x0044 */
8246 case MPI_IOCSTATUS_SCSI_IO_DATA_ERROR: /* 0x0046 */
8247 case MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR: /* 0x0047 */
8248 case MPI_IOCSTATUS_SCSI_TASK_TERMINATED: /* 0x0048 */
8249 case MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: /* 0x0049 */
8250 case MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED: /* 0x004A */
8251 case MPI_IOCSTATUS_SCSI_IOC_TERMINATED: /* 0x004B */
8252 case MPI_IOCSTATUS_SCSI_EXT_TERMINATED: /* 0x004C */
8253 break;
8254
8255/****************************************************************************/
8256/* SCSI Target values */
8257/****************************************************************************/
8258
8259 case MPI_IOCSTATUS_TARGET_PRIORITY_IO: /* 0x0060 */
8260 desc = "Target: Priority IO";
8261 break;
8262
8263 case MPI_IOCSTATUS_TARGET_INVALID_PORT: /* 0x0061 */
8264 desc = "Target: Invalid Port";
8265 break;
8266
8267 case MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX: /* 0x0062 */
8268 desc = "Target Invalid IO Index:";
8269 break;
8270
8271 case MPI_IOCSTATUS_TARGET_ABORTED: /* 0x0063 */
8272 desc = "Target: Aborted";
8273 break;
8274
8275 case MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: /* 0x0064 */
8276 desc = "Target: No Conn Retryable";
8277 break;
8278
8279 case MPI_IOCSTATUS_TARGET_NO_CONNECTION: /* 0x0065 */
8280 desc = "Target: No Connection";
8281 break;
8282
8283 case MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: /* 0x006A */
8284 desc = "Target: Transfer Count Mismatch";
8285 break;
8286
8287 case MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT: /* 0x006B */
8288 desc = "Target: STS Data not Sent";
8289 break;
8290
8291 case MPI_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: /* 0x006D */
8292 desc = "Target: Data Offset Error";
8293 break;
8294
8295 case MPI_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: /* 0x006E */
8296 desc = "Target: Too Much Write Data";
8297 break;
8298
8299 case MPI_IOCSTATUS_TARGET_IU_TOO_SHORT: /* 0x006F */
8300 desc = "Target: IU Too Short";
8301 break;
8302
8303 case MPI_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: /* 0x0070 */
8304 desc = "Target: ACK NAK Timeout";
8305 break;
8306
8307 case MPI_IOCSTATUS_TARGET_NAK_RECEIVED: /* 0x0071 */
8308 desc = "Target: Nak Received";
8309 break;
8310
8311/****************************************************************************/
8312/* Fibre Channel Direct Access values */
8313/****************************************************************************/
8314
8315 case MPI_IOCSTATUS_FC_ABORTED: /* 0x0066 */
8316 desc = "FC: Aborted";
8317 break;
8318
8319 case MPI_IOCSTATUS_FC_RX_ID_INVALID: /* 0x0067 */
8320 desc = "FC: RX ID Invalid";
8321 break;
8322
8323 case MPI_IOCSTATUS_FC_DID_INVALID: /* 0x0068 */
8324 desc = "FC: DID Invalid";
8325 break;
8326
8327 case MPI_IOCSTATUS_FC_NODE_LOGGED_OUT: /* 0x0069 */
8328 desc = "FC: Node Logged Out";
8329 break;
8330
8331 case MPI_IOCSTATUS_FC_EXCHANGE_CANCELED: /* 0x006C */
8332 desc = "FC: Exchange Canceled";
8333 break;
8334
8335/****************************************************************************/
8336/* LAN values */
8337/****************************************************************************/
8338
8339 case MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND: /* 0x0080 */
8340 desc = "LAN: Device not Found";
8341 break;
8342
8343 case MPI_IOCSTATUS_LAN_DEVICE_FAILURE: /* 0x0081 */
8344 desc = "LAN: Device Failure";
8345 break;
8346
8347 case MPI_IOCSTATUS_LAN_TRANSMIT_ERROR: /* 0x0082 */
8348 desc = "LAN: Transmit Error";
8349 break;
8350
8351 case MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED: /* 0x0083 */
8352 desc = "LAN: Transmit Aborted";
8353 break;
8354
8355 case MPI_IOCSTATUS_LAN_RECEIVE_ERROR: /* 0x0084 */
8356 desc = "LAN: Receive Error";
8357 break;
8358
8359 case MPI_IOCSTATUS_LAN_RECEIVE_ABORTED: /* 0x0085 */
8360 desc = "LAN: Receive Aborted";
8361 break;
8362
8363 case MPI_IOCSTATUS_LAN_PARTIAL_PACKET: /* 0x0086 */
8364 desc = "LAN: Partial Packet";
8365 break;
8366
8367 case MPI_IOCSTATUS_LAN_CANCELED: /* 0x0087 */
8368 desc = "LAN: Canceled";
8369 break;
8370
8371/****************************************************************************/
8372/* Serial Attached SCSI values */
8373/****************************************************************************/
8374
8375 case MPI_IOCSTATUS_SAS_SMP_REQUEST_FAILED: /* 0x0090 */
8376 desc = "SAS: SMP Request Failed";
8377 break;
8378
8379 case MPI_IOCSTATUS_SAS_SMP_DATA_OVERRUN: /* 0x0090 */
8380 desc = "SAS: SMP Data Overrun";
8381 break;
8382
8383 default:
8384 desc = "Others";
8385 break;
8386 }
8387
8388 if (!desc)
8389 return;
8390
8391 dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s\n",
8392 ioc->name, status, desc));
8393}
8394
8395/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8396EXPORT_SYMBOL(mpt_attach);
8397EXPORT_SYMBOL(mpt_detach);
8398#ifdef CONFIG_PM
8399EXPORT_SYMBOL(mpt_resume);
8400EXPORT_SYMBOL(mpt_suspend);
8401#endif
8402EXPORT_SYMBOL(ioc_list);
8403EXPORT_SYMBOL(mpt_register);
8404EXPORT_SYMBOL(mpt_deregister);
8405EXPORT_SYMBOL(mpt_event_register);
8406EXPORT_SYMBOL(mpt_event_deregister);
8407EXPORT_SYMBOL(mpt_reset_register);
8408EXPORT_SYMBOL(mpt_reset_deregister);
8409EXPORT_SYMBOL(mpt_device_driver_register);
8410EXPORT_SYMBOL(mpt_device_driver_deregister);
8411EXPORT_SYMBOL(mpt_get_msg_frame);
8412EXPORT_SYMBOL(mpt_put_msg_frame);
8413EXPORT_SYMBOL(mpt_put_msg_frame_hi_pri);
8414EXPORT_SYMBOL(mpt_free_msg_frame);
8415EXPORT_SYMBOL(mpt_send_handshake_request);
8416EXPORT_SYMBOL(mpt_verify_adapter);
8417EXPORT_SYMBOL(mpt_GetIocState);
8418EXPORT_SYMBOL(mpt_print_ioc_summary);
8419EXPORT_SYMBOL(mpt_HardResetHandler);
8420EXPORT_SYMBOL(mpt_config);
8421EXPORT_SYMBOL(mpt_findImVolumes);
8422EXPORT_SYMBOL(mpt_alloc_fw_memory);
8423EXPORT_SYMBOL(mpt_free_fw_memory);
8424EXPORT_SYMBOL(mptbase_sas_persist_operation);
8425EXPORT_SYMBOL(mpt_raid_phys_disk_pg0);
8426
8427/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8428/**
8429 * fusion_init - Fusion MPT base driver initialization routine.
8430 *
8431 * Returns 0 for success, non-zero for failure.
8432 */
8433static int __init
8434fusion_init(void)
8435{
8436 u8 cb_idx;
8437
8438 show_mptmod_ver(my_NAME, my_VERSION);
8439 printk(KERN_INFO COPYRIGHT "\n");
8440
8441 for (cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
8442 MptCallbacks[cb_idx] = NULL;
8443 MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER;
8444 MptEvHandlers[cb_idx] = NULL;
8445 MptResetHandlers[cb_idx] = NULL;
8446 }
8447
8448 /* Register ourselves (mptbase) in order to facilitate
8449 * EventNotification handling.
8450 */
8451 mpt_base_index = mpt_register(mptbase_reply, MPTBASE_DRIVER,
8452 "mptbase_reply");
8453
8454 /* Register for hard reset handling callbacks.
8455 */
8456 mpt_reset_register(mpt_base_index, mpt_ioc_reset);
8457
8458#ifdef CONFIG_PROC_FS
8459 (void) procmpt_create();
8460#endif
8461 return 0;
8462}
8463
8464/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8465/**
8466 * fusion_exit - Perform driver unload cleanup.
8467 *
8468 * This routine frees all resources associated with each MPT adapter
8469 * and removes all %MPT_PROCFS_MPTBASEDIR entries.
8470 */
8471static void __exit
8472fusion_exit(void)
8473{
8474
8475 mpt_reset_deregister(mpt_base_index);
8476
8477#ifdef CONFIG_PROC_FS
8478 procmpt_destroy();
8479#endif
8480}
8481
8482module_init(fusion_init);
8483module_exit(fusion_exit);
1/*
2 * linux/drivers/message/fusion/mptbase.c
3 * This is the Fusion MPT base driver which supports multiple
4 * (SCSI + LAN) specialized protocol drivers.
5 * For use with LSI PCI chip/adapter(s)
6 * running LSI Fusion MPT (Message Passing Technology) firmware.
7 *
8 * Copyright (c) 1999-2008 LSI Corporation
9 * (mailto:DL-MPTFusionLinux@lsi.com)
10 *
11 */
12/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
13/*
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; version 2 of the License.
17
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 NO WARRANTY
24 THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
25 CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
26 LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
27 MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
28 solely responsible for determining the appropriateness of using and
29 distributing the Program and assumes all risks associated with its
30 exercise of rights under this Agreement, including but not limited to
31 the risks and costs of program errors, damage to or loss of data,
32 programs or equipment, and unavailability or interruption of operations.
33
34 DISCLAIMER OF LIABILITY
35 NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
36 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
37 DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
38 ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
39 TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
40 USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
41 HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
42
43 You should have received a copy of the GNU General Public License
44 along with this program; if not, write to the Free Software
45 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
46*/
47/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
48
49#include <linux/kernel.h>
50#include <linux/module.h>
51#include <linux/errno.h>
52#include <linux/init.h>
53#include <linux/seq_file.h>
54#include <linux/slab.h>
55#include <linux/types.h>
56#include <linux/pci.h>
57#include <linux/kdev_t.h>
58#include <linux/blkdev.h>
59#include <linux/delay.h>
60#include <linux/interrupt.h>
61#include <linux/dma-mapping.h>
62#include <linux/kthread.h>
63#include <scsi/scsi_host.h>
64
65#include "mptbase.h"
66#include "lsi/mpi_log_fc.h"
67
68/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
69#define my_NAME "Fusion MPT base driver"
70#define my_VERSION MPT_LINUX_VERSION_COMMON
71#define MYNAM "mptbase"
72
73MODULE_AUTHOR(MODULEAUTHOR);
74MODULE_DESCRIPTION(my_NAME);
75MODULE_LICENSE("GPL");
76MODULE_VERSION(my_VERSION);
77
78/*
79 * cmd line parameters
80 */
81
82static int mpt_msi_enable_spi;
83module_param(mpt_msi_enable_spi, int, 0);
84MODULE_PARM_DESC(mpt_msi_enable_spi,
85 " Enable MSI Support for SPI controllers (default=0)");
86
87static int mpt_msi_enable_fc;
88module_param(mpt_msi_enable_fc, int, 0);
89MODULE_PARM_DESC(mpt_msi_enable_fc,
90 " Enable MSI Support for FC controllers (default=0)");
91
92static int mpt_msi_enable_sas;
93module_param(mpt_msi_enable_sas, int, 0);
94MODULE_PARM_DESC(mpt_msi_enable_sas,
95 " Enable MSI Support for SAS controllers (default=0)");
96
97static int mpt_channel_mapping;
98module_param(mpt_channel_mapping, int, 0);
99MODULE_PARM_DESC(mpt_channel_mapping, " Mapping id's to channels (default=0)");
100
101static int mpt_debug_level;
102static int mpt_set_debug_level(const char *val, const struct kernel_param *kp);
103module_param_call(mpt_debug_level, mpt_set_debug_level, param_get_int,
104 &mpt_debug_level, 0600);
105MODULE_PARM_DESC(mpt_debug_level,
106 " debug level - refer to mptdebug.h - (default=0)");
107
108int mpt_fwfault_debug;
109EXPORT_SYMBOL(mpt_fwfault_debug);
110module_param(mpt_fwfault_debug, int, 0600);
111MODULE_PARM_DESC(mpt_fwfault_debug,
112 "Enable detection of Firmware fault and halt Firmware on fault - (default=0)");
113
114static char MptCallbacksName[MPT_MAX_PROTOCOL_DRIVERS]
115 [MPT_MAX_CALLBACKNAME_LEN+1];
116
117#ifdef MFCNT
118static int mfcounter = 0;
119#define PRINT_MF_COUNT 20000
120#endif
121
122/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
123/*
124 * Public data...
125 */
126
127#define WHOINIT_UNKNOWN 0xAA
128
129/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
130/*
131 * Private data...
132 */
133 /* Adapter link list */
134LIST_HEAD(ioc_list);
135 /* Callback lookup table */
136static MPT_CALLBACK MptCallbacks[MPT_MAX_PROTOCOL_DRIVERS];
137 /* Protocol driver class lookup table */
138static int MptDriverClass[MPT_MAX_PROTOCOL_DRIVERS];
139 /* Event handler lookup table */
140static MPT_EVHANDLER MptEvHandlers[MPT_MAX_PROTOCOL_DRIVERS];
141 /* Reset handler lookup table */
142static MPT_RESETHANDLER MptResetHandlers[MPT_MAX_PROTOCOL_DRIVERS];
143static struct mpt_pci_driver *MptDeviceDriverHandlers[MPT_MAX_PROTOCOL_DRIVERS];
144
145#ifdef CONFIG_PROC_FS
146static struct proc_dir_entry *mpt_proc_root_dir;
147#endif
148
149/*
150 * Driver Callback Index's
151 */
152static u8 mpt_base_index = MPT_MAX_PROTOCOL_DRIVERS;
153static u8 last_drv_idx;
154
155/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
156/*
157 * Forward protos...
158 */
159static irqreturn_t mpt_interrupt(int irq, void *bus_id);
160static int mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req,
161 MPT_FRAME_HDR *reply);
162static int mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes,
163 u32 *req, int replyBytes, u16 *u16reply, int maxwait,
164 int sleepFlag);
165static int mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag);
166static void mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev);
167static void mpt_adapter_disable(MPT_ADAPTER *ioc);
168static void mpt_adapter_dispose(MPT_ADAPTER *ioc);
169
170static void MptDisplayIocCapabilities(MPT_ADAPTER *ioc);
171static int MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag);
172static int GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason);
173static int GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag);
174static int SendIocInit(MPT_ADAPTER *ioc, int sleepFlag);
175static int SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag);
176static int mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag);
177static int mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag);
178static int mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag);
179static int KickStart(MPT_ADAPTER *ioc, int ignore, int sleepFlag);
180static int SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag);
181static int PrimeIocFifos(MPT_ADAPTER *ioc);
182static int WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
183static int WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
184static int WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag);
185static int GetLanConfigPages(MPT_ADAPTER *ioc);
186static int GetIoUnitPage2(MPT_ADAPTER *ioc);
187int mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode);
188static int mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum);
189static int mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum);
190static void mpt_read_ioc_pg_1(MPT_ADAPTER *ioc);
191static void mpt_read_ioc_pg_4(MPT_ADAPTER *ioc);
192static void mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc);
193static int SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch,
194 int sleepFlag);
195static int SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp);
196static int mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag);
197static int mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init);
198
199#ifdef CONFIG_PROC_FS
200static int mpt_summary_proc_show(struct seq_file *m, void *v);
201static int mpt_version_proc_show(struct seq_file *m, void *v);
202static int mpt_iocinfo_proc_show(struct seq_file *m, void *v);
203#endif
204static void mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc);
205
206static int ProcessEventNotification(MPT_ADAPTER *ioc,
207 EventNotificationReply_t *evReply, int *evHandlers);
208static void mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf);
209static void mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info);
210static void mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info);
211static void mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info , u8 cb_idx);
212static int mpt_read_ioc_pg_3(MPT_ADAPTER *ioc);
213static void mpt_inactive_raid_list_free(MPT_ADAPTER *ioc);
214
215/* module entry point */
216static int __init fusion_init (void);
217static void __exit fusion_exit (void);
218
219#define CHIPREG_READ32(addr) readl_relaxed(addr)
220#define CHIPREG_READ32_dmasync(addr) readl(addr)
221#define CHIPREG_WRITE32(addr,val) writel(val, addr)
222#define CHIPREG_PIO_WRITE32(addr,val) outl(val, (unsigned long)addr)
223#define CHIPREG_PIO_READ32(addr) inl((unsigned long)addr)
224
225static void
226pci_disable_io_access(struct pci_dev *pdev)
227{
228 u16 command_reg;
229
230 pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
231 command_reg &= ~1;
232 pci_write_config_word(pdev, PCI_COMMAND, command_reg);
233}
234
235static void
236pci_enable_io_access(struct pci_dev *pdev)
237{
238 u16 command_reg;
239
240 pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
241 command_reg |= 1;
242 pci_write_config_word(pdev, PCI_COMMAND, command_reg);
243}
244
245static int mpt_set_debug_level(const char *val, const struct kernel_param *kp)
246{
247 int ret = param_set_int(val, kp);
248 MPT_ADAPTER *ioc;
249
250 if (ret)
251 return ret;
252
253 list_for_each_entry(ioc, &ioc_list, list)
254 ioc->debug_level = mpt_debug_level;
255 return 0;
256}
257
258/**
259 * mpt_get_cb_idx - obtain cb_idx for registered driver
260 * @dclass: class driver enum
261 *
262 * Returns cb_idx, or zero means it wasn't found
263 **/
264static u8
265mpt_get_cb_idx(MPT_DRIVER_CLASS dclass)
266{
267 u8 cb_idx;
268
269 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--)
270 if (MptDriverClass[cb_idx] == dclass)
271 return cb_idx;
272 return 0;
273}
274
275/**
276 * mpt_is_discovery_complete - determine if discovery has completed
277 * @ioc: per adatper instance
278 *
279 * Returns 1 when discovery completed, else zero.
280 */
281static int
282mpt_is_discovery_complete(MPT_ADAPTER *ioc)
283{
284 ConfigExtendedPageHeader_t hdr;
285 CONFIGPARMS cfg;
286 SasIOUnitPage0_t *buffer;
287 dma_addr_t dma_handle;
288 int rc = 0;
289
290 memset(&hdr, 0, sizeof(ConfigExtendedPageHeader_t));
291 memset(&cfg, 0, sizeof(CONFIGPARMS));
292 hdr.PageVersion = MPI_SASIOUNITPAGE0_PAGEVERSION;
293 hdr.PageType = MPI_CONFIG_PAGETYPE_EXTENDED;
294 hdr.ExtPageType = MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT;
295 cfg.cfghdr.ehdr = &hdr;
296 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
297
298 if ((mpt_config(ioc, &cfg)))
299 goto out;
300 if (!hdr.ExtPageLength)
301 goto out;
302
303 buffer = dma_alloc_coherent(&ioc->pcidev->dev, hdr.ExtPageLength * 4,
304 &dma_handle, GFP_KERNEL);
305 if (!buffer)
306 goto out;
307
308 cfg.physAddr = dma_handle;
309 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
310
311 if ((mpt_config(ioc, &cfg)))
312 goto out_free_consistent;
313
314 if (!(buffer->PhyData[0].PortFlags &
315 MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS))
316 rc = 1;
317
318 out_free_consistent:
319 dma_free_coherent(&ioc->pcidev->dev, hdr.ExtPageLength * 4, buffer,
320 dma_handle);
321 out:
322 return rc;
323}
324
325
326/**
327 * mpt_remove_dead_ioc_func - kthread context to remove dead ioc
328 * @arg: input argument, used to derive ioc
329 *
330 * Return 0 if controller is removed from pci subsystem.
331 * Return -1 for other case.
332 */
333static int mpt_remove_dead_ioc_func(void *arg)
334{
335 MPT_ADAPTER *ioc = (MPT_ADAPTER *)arg;
336 struct pci_dev *pdev;
337
338 if (!ioc)
339 return -1;
340
341 pdev = ioc->pcidev;
342 if (!pdev)
343 return -1;
344
345 pci_stop_and_remove_bus_device_locked(pdev);
346 return 0;
347}
348
349
350
351/**
352 * mpt_fault_reset_work - work performed on workq after ioc fault
353 * @work: input argument, used to derive ioc
354 *
355**/
356static void
357mpt_fault_reset_work(struct work_struct *work)
358{
359 MPT_ADAPTER *ioc =
360 container_of(work, MPT_ADAPTER, fault_reset_work.work);
361 u32 ioc_raw_state;
362 int rc;
363 unsigned long flags;
364 MPT_SCSI_HOST *hd;
365 struct task_struct *p;
366
367 if (ioc->ioc_reset_in_progress || !ioc->active)
368 goto out;
369
370
371 ioc_raw_state = mpt_GetIocState(ioc, 0);
372 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_MASK) {
373 printk(MYIOC_s_INFO_FMT "%s: IOC is non-operational !!!!\n",
374 ioc->name, __func__);
375
376 /*
377 * Call mptscsih_flush_pending_cmds callback so that we
378 * flush all pending commands back to OS.
379 * This call is required to aovid deadlock at block layer.
380 * Dead IOC will fail to do diag reset,and this call is safe
381 * since dead ioc will never return any command back from HW.
382 */
383 hd = shost_priv(ioc->sh);
384 ioc->schedule_dead_ioc_flush_running_cmds(hd);
385
386 /*Remove the Dead Host */
387 p = kthread_run(mpt_remove_dead_ioc_func, ioc,
388 "mpt_dead_ioc_%d", ioc->id);
389 if (IS_ERR(p)) {
390 printk(MYIOC_s_ERR_FMT
391 "%s: Running mpt_dead_ioc thread failed !\n",
392 ioc->name, __func__);
393 } else {
394 printk(MYIOC_s_WARN_FMT
395 "%s: Running mpt_dead_ioc thread success !\n",
396 ioc->name, __func__);
397 }
398 return; /* don't rearm timer */
399 }
400
401 if ((ioc_raw_state & MPI_IOC_STATE_MASK)
402 == MPI_IOC_STATE_FAULT) {
403 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state (%04xh)!!!\n",
404 ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK);
405 printk(MYIOC_s_WARN_FMT "Issuing HardReset from %s!!\n",
406 ioc->name, __func__);
407 rc = mpt_HardResetHandler(ioc, CAN_SLEEP);
408 printk(MYIOC_s_WARN_FMT "%s: HardReset: %s\n", ioc->name,
409 __func__, (rc == 0) ? "success" : "failed");
410 ioc_raw_state = mpt_GetIocState(ioc, 0);
411 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT)
412 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state after "
413 "reset (%04xh)\n", ioc->name, ioc_raw_state &
414 MPI_DOORBELL_DATA_MASK);
415 } else if (ioc->bus_type == SAS && ioc->sas_discovery_quiesce_io) {
416 if ((mpt_is_discovery_complete(ioc))) {
417 devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT "clearing "
418 "discovery_quiesce_io flag\n", ioc->name));
419 ioc->sas_discovery_quiesce_io = 0;
420 }
421 }
422
423 out:
424 /*
425 * Take turns polling alternate controller
426 */
427 if (ioc->alt_ioc)
428 ioc = ioc->alt_ioc;
429
430 /* rearm the timer */
431 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
432 if (ioc->reset_work_q)
433 queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work,
434 msecs_to_jiffies(MPT_POLLING_INTERVAL));
435 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
436}
437
438
439/*
440 * Process turbo (context) reply...
441 */
442static void
443mpt_turbo_reply(MPT_ADAPTER *ioc, u32 pa)
444{
445 MPT_FRAME_HDR *mf = NULL;
446 MPT_FRAME_HDR *mr = NULL;
447 u16 req_idx = 0;
448 u8 cb_idx;
449
450 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got TURBO reply req_idx=%08x\n",
451 ioc->name, pa));
452
453 switch (pa >> MPI_CONTEXT_REPLY_TYPE_SHIFT) {
454 case MPI_CONTEXT_REPLY_TYPE_SCSI_INIT:
455 req_idx = pa & 0x0000FFFF;
456 cb_idx = (pa & 0x00FF0000) >> 16;
457 mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
458 break;
459 case MPI_CONTEXT_REPLY_TYPE_LAN:
460 cb_idx = mpt_get_cb_idx(MPTLAN_DRIVER);
461 /*
462 * Blind set of mf to NULL here was fatal
463 * after lan_reply says "freeme"
464 * Fix sort of combined with an optimization here;
465 * added explicit check for case where lan_reply
466 * was just returning 1 and doing nothing else.
467 * For this case skip the callback, but set up
468 * proper mf value first here:-)
469 */
470 if ((pa & 0x58000000) == 0x58000000) {
471 req_idx = pa & 0x0000FFFF;
472 mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
473 mpt_free_msg_frame(ioc, mf);
474 mb();
475 return;
476 }
477 mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa);
478 break;
479 case MPI_CONTEXT_REPLY_TYPE_SCSI_TARGET:
480 cb_idx = mpt_get_cb_idx(MPTSTM_DRIVER);
481 mr = (MPT_FRAME_HDR *) CAST_U32_TO_PTR(pa);
482 break;
483 default:
484 cb_idx = 0;
485 BUG();
486 }
487
488 /* Check for (valid) IO callback! */
489 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS ||
490 MptCallbacks[cb_idx] == NULL) {
491 printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n",
492 __func__, ioc->name, cb_idx);
493 goto out;
494 }
495
496 if (MptCallbacks[cb_idx](ioc, mf, mr))
497 mpt_free_msg_frame(ioc, mf);
498 out:
499 mb();
500}
501
502static void
503mpt_reply(MPT_ADAPTER *ioc, u32 pa)
504{
505 MPT_FRAME_HDR *mf;
506 MPT_FRAME_HDR *mr;
507 u16 req_idx;
508 u8 cb_idx;
509 int freeme;
510
511 u32 reply_dma_low;
512 u16 ioc_stat;
513
514 /* non-TURBO reply! Hmmm, something may be up...
515 * Newest turbo reply mechanism; get address
516 * via left shift 1 (get rid of MPI_ADDRESS_REPLY_A_BIT)!
517 */
518
519 /* Map DMA address of reply header to cpu address.
520 * pa is 32 bits - but the dma address may be 32 or 64 bits
521 * get offset based only only the low addresses
522 */
523
524 reply_dma_low = (pa <<= 1);
525 mr = (MPT_FRAME_HDR *)((u8 *)ioc->reply_frames +
526 (reply_dma_low - ioc->reply_frames_low_dma));
527
528 req_idx = le16_to_cpu(mr->u.frame.hwhdr.msgctxu.fld.req_idx);
529 cb_idx = mr->u.frame.hwhdr.msgctxu.fld.cb_idx;
530 mf = MPT_INDEX_2_MFPTR(ioc, req_idx);
531
532 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got non-TURBO reply=%p req_idx=%x cb_idx=%x Function=%x\n",
533 ioc->name, mr, req_idx, cb_idx, mr->u.hdr.Function));
534 DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mr);
535
536 /* Check/log IOC log info
537 */
538 ioc_stat = le16_to_cpu(mr->u.reply.IOCStatus);
539 if (ioc_stat & MPI_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
540 u32 log_info = le32_to_cpu(mr->u.reply.IOCLogInfo);
541 if (ioc->bus_type == FC)
542 mpt_fc_log_info(ioc, log_info);
543 else if (ioc->bus_type == SPI)
544 mpt_spi_log_info(ioc, log_info);
545 else if (ioc->bus_type == SAS)
546 mpt_sas_log_info(ioc, log_info, cb_idx);
547 }
548
549 if (ioc_stat & MPI_IOCSTATUS_MASK)
550 mpt_iocstatus_info(ioc, (u32)ioc_stat, mf);
551
552 /* Check for (valid) IO callback! */
553 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS ||
554 MptCallbacks[cb_idx] == NULL) {
555 printk(MYIOC_s_WARN_FMT "%s: Invalid cb_idx (%d)!\n",
556 __func__, ioc->name, cb_idx);
557 freeme = 0;
558 goto out;
559 }
560
561 freeme = MptCallbacks[cb_idx](ioc, mf, mr);
562
563 out:
564 /* Flush (non-TURBO) reply with a WRITE! */
565 CHIPREG_WRITE32(&ioc->chip->ReplyFifo, pa);
566
567 if (freeme)
568 mpt_free_msg_frame(ioc, mf);
569 mb();
570}
571
572/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
573/**
574 * mpt_interrupt - MPT adapter (IOC) specific interrupt handler.
575 * @irq: irq number (not used)
576 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
577 *
578 * This routine is registered via the request_irq() kernel API call,
579 * and handles all interrupts generated from a specific MPT adapter
580 * (also referred to as a IO Controller or IOC).
581 * This routine must clear the interrupt from the adapter and does
582 * so by reading the reply FIFO. Multiple replies may be processed
583 * per single call to this routine.
584 *
585 * This routine handles register-level access of the adapter but
586 * dispatches (calls) a protocol-specific callback routine to handle
587 * the protocol-specific details of the MPT request completion.
588 */
589static irqreturn_t
590mpt_interrupt(int irq, void *bus_id)
591{
592 MPT_ADAPTER *ioc = bus_id;
593 u32 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
594
595 if (pa == 0xFFFFFFFF)
596 return IRQ_NONE;
597
598 /*
599 * Drain the reply FIFO!
600 */
601 do {
602 if (pa & MPI_ADDRESS_REPLY_A_BIT)
603 mpt_reply(ioc, pa);
604 else
605 mpt_turbo_reply(ioc, pa);
606 pa = CHIPREG_READ32_dmasync(&ioc->chip->ReplyFifo);
607 } while (pa != 0xFFFFFFFF);
608
609 return IRQ_HANDLED;
610}
611
612/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
613/**
614 * mptbase_reply - MPT base driver's callback routine
615 * @ioc: Pointer to MPT_ADAPTER structure
616 * @req: Pointer to original MPT request frame
617 * @reply: Pointer to MPT reply frame (NULL if TurboReply)
618 *
619 * MPT base driver's callback routine; all base driver
620 * "internal" request/reply processing is routed here.
621 * Currently used for EventNotification and EventAck handling.
622 *
623 * Returns 1 indicating original alloc'd request frame ptr
624 * should be freed, or 0 if it shouldn't.
625 */
626static int
627mptbase_reply(MPT_ADAPTER *ioc, MPT_FRAME_HDR *req, MPT_FRAME_HDR *reply)
628{
629 EventNotificationReply_t *pEventReply;
630 u8 event;
631 int evHandlers;
632 int freereq = 1;
633
634 switch (reply->u.hdr.Function) {
635 case MPI_FUNCTION_EVENT_NOTIFICATION:
636 pEventReply = (EventNotificationReply_t *)reply;
637 evHandlers = 0;
638 ProcessEventNotification(ioc, pEventReply, &evHandlers);
639 event = le32_to_cpu(pEventReply->Event) & 0xFF;
640 if (pEventReply->MsgFlags & MPI_MSGFLAGS_CONTINUATION_REPLY)
641 freereq = 0;
642 if (event != MPI_EVENT_EVENT_CHANGE)
643 break;
644 fallthrough;
645 case MPI_FUNCTION_CONFIG:
646 case MPI_FUNCTION_SAS_IO_UNIT_CONTROL:
647 ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_COMMAND_GOOD;
648 ioc->mptbase_cmds.status |= MPT_MGMT_STATUS_RF_VALID;
649 memcpy(ioc->mptbase_cmds.reply, reply,
650 min(MPT_DEFAULT_FRAME_SIZE,
651 4 * reply->u.reply.MsgLength));
652 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) {
653 ioc->mptbase_cmds.status &= ~MPT_MGMT_STATUS_PENDING;
654 complete(&ioc->mptbase_cmds.done);
655 } else
656 freereq = 0;
657 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_FREE_MF)
658 freereq = 1;
659 break;
660 case MPI_FUNCTION_EVENT_ACK:
661 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
662 "EventAck reply received\n", ioc->name));
663 break;
664 default:
665 printk(MYIOC_s_ERR_FMT
666 "Unexpected msg function (=%02Xh) reply received!\n",
667 ioc->name, reply->u.hdr.Function);
668 break;
669 }
670
671 /*
672 * Conditionally tell caller to free the original
673 * EventNotification/EventAck/unexpected request frame!
674 */
675 return freereq;
676}
677
678/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
679/**
680 * mpt_register - Register protocol-specific main callback handler.
681 * @cbfunc: callback function pointer
682 * @dclass: Protocol driver's class (%MPT_DRIVER_CLASS enum value)
683 * @func_name: call function's name
684 *
685 * This routine is called by a protocol-specific driver (SCSI host,
686 * LAN, SCSI target) to register its reply callback routine. Each
687 * protocol-specific driver must do this before it will be able to
688 * use any IOC resources, such as obtaining request frames.
689 *
690 * NOTES: The SCSI protocol driver currently calls this routine thrice
691 * in order to register separate callbacks; one for "normal" SCSI IO;
692 * one for MptScsiTaskMgmt requests; one for Scan/DV requests.
693 *
694 * Returns u8 valued "handle" in the range (and S.O.D. order)
695 * {N,...,7,6,5,...,1} if successful.
696 * A return value of MPT_MAX_PROTOCOL_DRIVERS (including zero!) should be
697 * considered an error by the caller.
698 */
699u8
700mpt_register(MPT_CALLBACK cbfunc, MPT_DRIVER_CLASS dclass, char *func_name)
701{
702 u8 cb_idx;
703 last_drv_idx = MPT_MAX_PROTOCOL_DRIVERS;
704
705 /*
706 * Search for empty callback slot in this order: {N,...,7,6,5,...,1}
707 * (slot/handle 0 is reserved!)
708 */
709 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
710 if (MptCallbacks[cb_idx] == NULL) {
711 MptCallbacks[cb_idx] = cbfunc;
712 MptDriverClass[cb_idx] = dclass;
713 MptEvHandlers[cb_idx] = NULL;
714 last_drv_idx = cb_idx;
715 strscpy(MptCallbacksName[cb_idx], func_name,
716 MPT_MAX_CALLBACKNAME_LEN+1);
717 break;
718 }
719 }
720
721 return last_drv_idx;
722}
723
724/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
725/**
726 * mpt_deregister - Deregister a protocol drivers resources.
727 * @cb_idx: previously registered callback handle
728 *
729 * Each protocol-specific driver should call this routine when its
730 * module is unloaded.
731 */
732void
733mpt_deregister(u8 cb_idx)
734{
735 if (cb_idx && (cb_idx < MPT_MAX_PROTOCOL_DRIVERS)) {
736 MptCallbacks[cb_idx] = NULL;
737 MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER;
738 MptEvHandlers[cb_idx] = NULL;
739
740 last_drv_idx++;
741 }
742}
743
744/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
745/**
746 * mpt_event_register - Register protocol-specific event callback handler.
747 * @cb_idx: previously registered (via mpt_register) callback handle
748 * @ev_cbfunc: callback function
749 *
750 * This routine can be called by one or more protocol-specific drivers
751 * if/when they choose to be notified of MPT events.
752 *
753 * Returns 0 for success.
754 */
755int
756mpt_event_register(u8 cb_idx, MPT_EVHANDLER ev_cbfunc)
757{
758 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
759 return -1;
760
761 MptEvHandlers[cb_idx] = ev_cbfunc;
762 return 0;
763}
764
765/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
766/**
767 * mpt_event_deregister - Deregister protocol-specific event callback handler
768 * @cb_idx: previously registered callback handle
769 *
770 * Each protocol-specific driver should call this routine
771 * when it does not (or can no longer) handle events,
772 * or when its module is unloaded.
773 */
774void
775mpt_event_deregister(u8 cb_idx)
776{
777 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
778 return;
779
780 MptEvHandlers[cb_idx] = NULL;
781}
782
783/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
784/**
785 * mpt_reset_register - Register protocol-specific IOC reset handler.
786 * @cb_idx: previously registered (via mpt_register) callback handle
787 * @reset_func: reset function
788 *
789 * This routine can be called by one or more protocol-specific drivers
790 * if/when they choose to be notified of IOC resets.
791 *
792 * Returns 0 for success.
793 */
794int
795mpt_reset_register(u8 cb_idx, MPT_RESETHANDLER reset_func)
796{
797 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
798 return -1;
799
800 MptResetHandlers[cb_idx] = reset_func;
801 return 0;
802}
803
804/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
805/**
806 * mpt_reset_deregister - Deregister protocol-specific IOC reset handler.
807 * @cb_idx: previously registered callback handle
808 *
809 * Each protocol-specific driver should call this routine
810 * when it does not (or can no longer) handle IOC reset handling,
811 * or when its module is unloaded.
812 */
813void
814mpt_reset_deregister(u8 cb_idx)
815{
816 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
817 return;
818
819 MptResetHandlers[cb_idx] = NULL;
820}
821
822/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
823/**
824 * mpt_device_driver_register - Register device driver hooks
825 * @dd_cbfunc: driver callbacks struct
826 * @cb_idx: MPT protocol driver index
827 */
828int
829mpt_device_driver_register(struct mpt_pci_driver * dd_cbfunc, u8 cb_idx)
830{
831 MPT_ADAPTER *ioc;
832
833 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
834 return -EINVAL;
835
836 MptDeviceDriverHandlers[cb_idx] = dd_cbfunc;
837
838 /* call per pci device probe entry point */
839 list_for_each_entry(ioc, &ioc_list, list) {
840 if (dd_cbfunc->probe)
841 dd_cbfunc->probe(ioc->pcidev);
842 }
843
844 return 0;
845}
846
847/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
848/**
849 * mpt_device_driver_deregister - DeRegister device driver hooks
850 * @cb_idx: MPT protocol driver index
851 */
852void
853mpt_device_driver_deregister(u8 cb_idx)
854{
855 struct mpt_pci_driver *dd_cbfunc;
856 MPT_ADAPTER *ioc;
857
858 if (!cb_idx || cb_idx >= MPT_MAX_PROTOCOL_DRIVERS)
859 return;
860
861 dd_cbfunc = MptDeviceDriverHandlers[cb_idx];
862
863 list_for_each_entry(ioc, &ioc_list, list) {
864 if (dd_cbfunc->remove)
865 dd_cbfunc->remove(ioc->pcidev);
866 }
867
868 MptDeviceDriverHandlers[cb_idx] = NULL;
869}
870
871
872/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
873/**
874 * mpt_get_msg_frame - Obtain an MPT request frame from the pool
875 * @cb_idx: Handle of registered MPT protocol driver
876 * @ioc: Pointer to MPT adapter structure
877 *
878 * Obtain an MPT request frame from the pool (of 1024) that are
879 * allocated per MPT adapter.
880 *
881 * Returns pointer to a MPT request frame or %NULL if none are available
882 * or IOC is not active.
883 */
884MPT_FRAME_HDR*
885mpt_get_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc)
886{
887 MPT_FRAME_HDR *mf;
888 unsigned long flags;
889 u16 req_idx; /* Request index */
890
891 /* validate handle and ioc identifier */
892
893#ifdef MFCNT
894 if (!ioc->active)
895 printk(MYIOC_s_WARN_FMT "IOC Not Active! mpt_get_msg_frame "
896 "returning NULL!\n", ioc->name);
897#endif
898
899 /* If interrupts are not attached, do not return a request frame */
900 if (!ioc->active)
901 return NULL;
902
903 spin_lock_irqsave(&ioc->FreeQlock, flags);
904 if (!list_empty(&ioc->FreeQ)) {
905 int req_offset;
906
907 mf = list_entry(ioc->FreeQ.next, MPT_FRAME_HDR,
908 u.frame.linkage.list);
909 list_del(&mf->u.frame.linkage.list);
910 mf->u.frame.linkage.arg1 = 0;
911 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */
912 req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
913 /* u16! */
914 req_idx = req_offset / ioc->req_sz;
915 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
916 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
917 /* Default, will be changed if necessary in SG generation */
918 ioc->RequestNB[req_idx] = ioc->NB_for_64_byte_frame;
919#ifdef MFCNT
920 ioc->mfcnt++;
921#endif
922 }
923 else
924 mf = NULL;
925 spin_unlock_irqrestore(&ioc->FreeQlock, flags);
926
927#ifdef MFCNT
928 if (mf == NULL)
929 printk(MYIOC_s_WARN_FMT "IOC Active. No free Msg Frames! "
930 "Count 0x%x Max 0x%x\n", ioc->name, ioc->mfcnt,
931 ioc->req_depth);
932 mfcounter++;
933 if (mfcounter == PRINT_MF_COUNT)
934 printk(MYIOC_s_INFO_FMT "MF Count 0x%x Max 0x%x \n", ioc->name,
935 ioc->mfcnt, ioc->req_depth);
936#endif
937
938 dmfprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_get_msg_frame(%d,%d), got mf=%p\n",
939 ioc->name, cb_idx, ioc->id, mf));
940 return mf;
941}
942
943/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
944/**
945 * mpt_put_msg_frame - Send a protocol-specific MPT request frame to an IOC
946 * @cb_idx: Handle of registered MPT protocol driver
947 * @ioc: Pointer to MPT adapter structure
948 * @mf: Pointer to MPT request frame
949 *
950 * This routine posts an MPT request frame to the request post FIFO of a
951 * specific MPT adapter.
952 */
953void
954mpt_put_msg_frame(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
955{
956 u32 mf_dma_addr;
957 int req_offset;
958 u16 req_idx; /* Request index */
959
960 /* ensure values are reset properly! */
961 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx; /* byte */
962 req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
963 /* u16! */
964 req_idx = req_offset / ioc->req_sz;
965 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
966 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
967
968 DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf);
969
970 mf_dma_addr = (ioc->req_frames_low_dma + req_offset) | ioc->RequestNB[req_idx];
971 dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d "
972 "RequestNB=%x\n", ioc->name, mf_dma_addr, req_idx,
973 ioc->RequestNB[req_idx]));
974 CHIPREG_WRITE32(&ioc->chip->RequestFifo, mf_dma_addr);
975}
976
977/**
978 * mpt_put_msg_frame_hi_pri - Send a hi-pri protocol-specific MPT request frame
979 * @cb_idx: Handle of registered MPT protocol driver
980 * @ioc: Pointer to MPT adapter structure
981 * @mf: Pointer to MPT request frame
982 *
983 * Send a protocol-specific MPT request frame to an IOC using
984 * hi-priority request queue.
985 *
986 * This routine posts an MPT request frame to the request post FIFO of a
987 * specific MPT adapter.
988 **/
989void
990mpt_put_msg_frame_hi_pri(u8 cb_idx, MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
991{
992 u32 mf_dma_addr;
993 int req_offset;
994 u16 req_idx; /* Request index */
995
996 /* ensure values are reset properly! */
997 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
998 req_offset = (u8 *)mf - (u8 *)ioc->req_frames;
999 req_idx = req_offset / ioc->req_sz;
1000 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(req_idx);
1001 mf->u.frame.hwhdr.msgctxu.fld.rsvd = 0;
1002
1003 DBG_DUMP_PUT_MSG_FRAME(ioc, (u32 *)mf);
1004
1005 mf_dma_addr = (ioc->req_frames_low_dma + req_offset);
1006 dsgprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mf_dma_addr=%x req_idx=%d\n",
1007 ioc->name, mf_dma_addr, req_idx));
1008 CHIPREG_WRITE32(&ioc->chip->RequestHiPriFifo, mf_dma_addr);
1009}
1010
1011/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1012/**
1013 * mpt_free_msg_frame - Place MPT request frame back on FreeQ.
1014 * @ioc: Pointer to MPT adapter structure
1015 * @mf: Pointer to MPT request frame
1016 *
1017 * This routine places a MPT request frame back on the MPT adapter's
1018 * FreeQ.
1019 */
1020void
1021mpt_free_msg_frame(MPT_ADAPTER *ioc, MPT_FRAME_HDR *mf)
1022{
1023 unsigned long flags;
1024
1025 /* Put Request back on FreeQ! */
1026 spin_lock_irqsave(&ioc->FreeQlock, flags);
1027 if (cpu_to_le32(mf->u.frame.linkage.arg1) == 0xdeadbeaf)
1028 goto out;
1029 /* signature to know if this mf is freed */
1030 mf->u.frame.linkage.arg1 = cpu_to_le32(0xdeadbeaf);
1031 list_add(&mf->u.frame.linkage.list, &ioc->FreeQ);
1032#ifdef MFCNT
1033 ioc->mfcnt--;
1034#endif
1035 out:
1036 spin_unlock_irqrestore(&ioc->FreeQlock, flags);
1037}
1038
1039/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1040/**
1041 * mpt_add_sge - Place a simple 32 bit SGE at address pAddr.
1042 * @pAddr: virtual address for SGE
1043 * @flagslength: SGE flags and data transfer length
1044 * @dma_addr: Physical address
1045 *
1046 * This routine places a MPT request frame back on the MPT adapter's
1047 * FreeQ.
1048 */
1049static void
1050mpt_add_sge(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
1051{
1052 SGESimple32_t *pSge = (SGESimple32_t *) pAddr;
1053 pSge->FlagsLength = cpu_to_le32(flagslength);
1054 pSge->Address = cpu_to_le32(dma_addr);
1055}
1056
1057/**
1058 * mpt_add_sge_64bit - Place a simple 64 bit SGE at address pAddr.
1059 * @pAddr: virtual address for SGE
1060 * @flagslength: SGE flags and data transfer length
1061 * @dma_addr: Physical address
1062 *
1063 * This routine places a MPT request frame back on the MPT adapter's
1064 * FreeQ.
1065 **/
1066static void
1067mpt_add_sge_64bit(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
1068{
1069 SGESimple64_t *pSge = (SGESimple64_t *) pAddr;
1070 pSge->Address.Low = cpu_to_le32
1071 (lower_32_bits(dma_addr));
1072 pSge->Address.High = cpu_to_le32
1073 (upper_32_bits(dma_addr));
1074 pSge->FlagsLength = cpu_to_le32
1075 ((flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING));
1076}
1077
1078/**
1079 * mpt_add_sge_64bit_1078 - Place a simple 64 bit SGE at address pAddr (1078 workaround).
1080 * @pAddr: virtual address for SGE
1081 * @flagslength: SGE flags and data transfer length
1082 * @dma_addr: Physical address
1083 *
1084 * This routine places a MPT request frame back on the MPT adapter's
1085 * FreeQ.
1086 **/
1087static void
1088mpt_add_sge_64bit_1078(void *pAddr, u32 flagslength, dma_addr_t dma_addr)
1089{
1090 SGESimple64_t *pSge = (SGESimple64_t *) pAddr;
1091 u32 tmp;
1092
1093 pSge->Address.Low = cpu_to_le32
1094 (lower_32_bits(dma_addr));
1095 tmp = (u32)(upper_32_bits(dma_addr));
1096
1097 /*
1098 * 1078 errata workaround for the 36GB limitation
1099 */
1100 if ((((u64)dma_addr + MPI_SGE_LENGTH(flagslength)) >> 32) == 9) {
1101 flagslength |=
1102 MPI_SGE_SET_FLAGS(MPI_SGE_FLAGS_LOCAL_ADDRESS);
1103 tmp |= (1<<31);
1104 if (mpt_debug_level & MPT_DEBUG_36GB_MEM)
1105 printk(KERN_DEBUG "1078 P0M2 addressing for "
1106 "addr = 0x%llx len = %d\n",
1107 (unsigned long long)dma_addr,
1108 MPI_SGE_LENGTH(flagslength));
1109 }
1110
1111 pSge->Address.High = cpu_to_le32(tmp);
1112 pSge->FlagsLength = cpu_to_le32(
1113 (flagslength | MPT_SGE_FLAGS_64_BIT_ADDRESSING));
1114}
1115
1116/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1117/**
1118 * mpt_add_chain - Place a 32 bit chain SGE at address pAddr.
1119 * @pAddr: virtual address for SGE
1120 * @next: nextChainOffset value (u32's)
1121 * @length: length of next SGL segment
1122 * @dma_addr: Physical address
1123 *
1124 */
1125static void
1126mpt_add_chain(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr)
1127{
1128 SGEChain32_t *pChain = (SGEChain32_t *) pAddr;
1129
1130 pChain->Length = cpu_to_le16(length);
1131 pChain->Flags = MPI_SGE_FLAGS_CHAIN_ELEMENT;
1132 pChain->NextChainOffset = next;
1133 pChain->Address = cpu_to_le32(dma_addr);
1134}
1135
1136/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1137/**
1138 * mpt_add_chain_64bit - Place a 64 bit chain SGE at address pAddr.
1139 * @pAddr: virtual address for SGE
1140 * @next: nextChainOffset value (u32's)
1141 * @length: length of next SGL segment
1142 * @dma_addr: Physical address
1143 *
1144 */
1145static void
1146mpt_add_chain_64bit(void *pAddr, u8 next, u16 length, dma_addr_t dma_addr)
1147{
1148 SGEChain64_t *pChain = (SGEChain64_t *) pAddr;
1149 u32 tmp = dma_addr & 0xFFFFFFFF;
1150
1151 pChain->Length = cpu_to_le16(length);
1152 pChain->Flags = (MPI_SGE_FLAGS_CHAIN_ELEMENT |
1153 MPI_SGE_FLAGS_64_BIT_ADDRESSING);
1154
1155 pChain->NextChainOffset = next;
1156
1157 pChain->Address.Low = cpu_to_le32(tmp);
1158 tmp = (u32)(upper_32_bits(dma_addr));
1159 pChain->Address.High = cpu_to_le32(tmp);
1160}
1161
1162/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1163/**
1164 * mpt_send_handshake_request - Send MPT request via doorbell handshake method.
1165 * @cb_idx: Handle of registered MPT protocol driver
1166 * @ioc: Pointer to MPT adapter structure
1167 * @reqBytes: Size of the request in bytes
1168 * @req: Pointer to MPT request frame
1169 * @sleepFlag: Use schedule if CAN_SLEEP else use udelay.
1170 *
1171 * This routine is used exclusively to send MptScsiTaskMgmt
1172 * requests since they are required to be sent via doorbell handshake.
1173 *
1174 * NOTE: It is the callers responsibility to byte-swap fields in the
1175 * request which are greater than 1 byte in size.
1176 *
1177 * Returns 0 for success, non-zero for failure.
1178 */
1179int
1180mpt_send_handshake_request(u8 cb_idx, MPT_ADAPTER *ioc, int reqBytes, u32 *req, int sleepFlag)
1181{
1182 int r = 0;
1183 u8 *req_as_bytes;
1184 int ii;
1185
1186 /* State is known to be good upon entering
1187 * this function so issue the bus reset
1188 * request.
1189 */
1190
1191 /*
1192 * Emulate what mpt_put_msg_frame() does /wrt to sanity
1193 * setting cb_idx/req_idx. But ONLY if this request
1194 * is in proper (pre-alloc'd) request buffer range...
1195 */
1196 ii = MFPTR_2_MPT_INDEX(ioc,(MPT_FRAME_HDR*)req);
1197 if (reqBytes >= 12 && ii >= 0 && ii < ioc->req_depth) {
1198 MPT_FRAME_HDR *mf = (MPT_FRAME_HDR*)req;
1199 mf->u.frame.hwhdr.msgctxu.fld.req_idx = cpu_to_le16(ii);
1200 mf->u.frame.hwhdr.msgctxu.fld.cb_idx = cb_idx;
1201 }
1202
1203 /* Make sure there are no doorbells */
1204 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1205
1206 CHIPREG_WRITE32(&ioc->chip->Doorbell,
1207 ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) |
1208 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT)));
1209
1210 /* Wait for IOC doorbell int */
1211 if ((ii = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0) {
1212 return ii;
1213 }
1214
1215 /* Read doorbell and check for active bit */
1216 if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
1217 return -5;
1218
1219 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "mpt_send_handshake_request start, WaitCnt=%d\n",
1220 ioc->name, ii));
1221
1222 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1223
1224 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
1225 return -2;
1226 }
1227
1228 /* Send request via doorbell handshake */
1229 req_as_bytes = (u8 *) req;
1230 for (ii = 0; ii < reqBytes/4; ii++) {
1231 u32 word;
1232
1233 word = ((req_as_bytes[(ii*4) + 0] << 0) |
1234 (req_as_bytes[(ii*4) + 1] << 8) |
1235 (req_as_bytes[(ii*4) + 2] << 16) |
1236 (req_as_bytes[(ii*4) + 3] << 24));
1237 CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
1238 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0) {
1239 r = -3;
1240 break;
1241 }
1242 }
1243
1244 if (r >= 0 && WaitForDoorbellInt(ioc, 10, sleepFlag) >= 0)
1245 r = 0;
1246 else
1247 r = -4;
1248
1249 /* Make sure there are no doorbells */
1250 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1251
1252 return r;
1253}
1254
1255/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1256/**
1257 * mpt_host_page_access_control - control the IOC's Host Page Buffer access
1258 * @ioc: Pointer to MPT adapter structure
1259 * @access_control_value: define bits below
1260 * @sleepFlag: Specifies whether the process can sleep
1261 *
1262 * Provides mechanism for the host driver to control the IOC's
1263 * Host Page Buffer access.
1264 *
1265 * Access Control Value - bits[15:12]
1266 * 0h Reserved
1267 * 1h Enable Access { MPI_DB_HPBAC_ENABLE_ACCESS }
1268 * 2h Disable Access { MPI_DB_HPBAC_DISABLE_ACCESS }
1269 * 3h Free Buffer { MPI_DB_HPBAC_FREE_BUFFER }
1270 *
1271 * Returns 0 for success, non-zero for failure.
1272 */
1273
1274static int
1275mpt_host_page_access_control(MPT_ADAPTER *ioc, u8 access_control_value, int sleepFlag)
1276{
1277 /* return if in use */
1278 if (CHIPREG_READ32(&ioc->chip->Doorbell)
1279 & MPI_DOORBELL_ACTIVE)
1280 return -1;
1281
1282 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1283
1284 CHIPREG_WRITE32(&ioc->chip->Doorbell,
1285 ((MPI_FUNCTION_HOST_PAGEBUF_ACCESS_CONTROL
1286 <<MPI_DOORBELL_FUNCTION_SHIFT) |
1287 (access_control_value<<12)));
1288
1289 /* Wait for IOC to clear Doorbell Status bit */
1290 if (WaitForDoorbellAck(ioc, 5, sleepFlag) < 0)
1291 return -2;
1292 else
1293 return 0;
1294}
1295
1296/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1297/**
1298 * mpt_host_page_alloc - allocate system memory for the fw
1299 * @ioc: Pointer to pointer to IOC adapter
1300 * @ioc_init: Pointer to ioc init config page
1301 *
1302 * If we already allocated memory in past, then resend the same pointer.
1303 * Returns 0 for success, non-zero for failure.
1304 */
1305static int
1306mpt_host_page_alloc(MPT_ADAPTER *ioc, pIOCInit_t ioc_init)
1307{
1308 char *psge;
1309 int flags_length;
1310 u32 host_page_buffer_sz=0;
1311
1312 if(!ioc->HostPageBuffer) {
1313
1314 host_page_buffer_sz =
1315 le32_to_cpu(ioc->facts.HostPageBufferSGE.FlagsLength) & 0xFFFFFF;
1316
1317 if(!host_page_buffer_sz)
1318 return 0; /* fw doesn't need any host buffers */
1319
1320 /* spin till we get enough memory */
1321 while (host_page_buffer_sz > 0) {
1322 ioc->HostPageBuffer =
1323 dma_alloc_coherent(&ioc->pcidev->dev,
1324 host_page_buffer_sz,
1325 &ioc->HostPageBuffer_dma,
1326 GFP_KERNEL);
1327 if (ioc->HostPageBuffer) {
1328 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
1329 "host_page_buffer @ %p, dma @ %x, sz=%d bytes\n",
1330 ioc->name, ioc->HostPageBuffer,
1331 (u32)ioc->HostPageBuffer_dma,
1332 host_page_buffer_sz));
1333 ioc->alloc_total += host_page_buffer_sz;
1334 ioc->HostPageBuffer_sz = host_page_buffer_sz;
1335 break;
1336 }
1337
1338 host_page_buffer_sz -= (4*1024);
1339 }
1340 }
1341
1342 if(!ioc->HostPageBuffer) {
1343 printk(MYIOC_s_ERR_FMT
1344 "Failed to alloc memory for host_page_buffer!\n",
1345 ioc->name);
1346 return -999;
1347 }
1348
1349 psge = (char *)&ioc_init->HostPageBufferSGE;
1350 flags_length = MPI_SGE_FLAGS_SIMPLE_ELEMENT |
1351 MPI_SGE_FLAGS_SYSTEM_ADDRESS |
1352 MPI_SGE_FLAGS_HOST_TO_IOC |
1353 MPI_SGE_FLAGS_END_OF_BUFFER;
1354 flags_length = flags_length << MPI_SGE_FLAGS_SHIFT;
1355 flags_length |= ioc->HostPageBuffer_sz;
1356 ioc->add_sge(psge, flags_length, ioc->HostPageBuffer_dma);
1357 ioc->facts.HostPageBufferSGE = ioc_init->HostPageBufferSGE;
1358
1359 return 0;
1360}
1361
1362/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1363/**
1364 * mpt_verify_adapter - Given IOC identifier, set pointer to its adapter structure.
1365 * @iocid: IOC unique identifier (integer)
1366 * @iocpp: Pointer to pointer to IOC adapter
1367 *
1368 * Given a unique IOC identifier, set pointer to the associated MPT
1369 * adapter structure.
1370 *
1371 * Returns iocid and sets iocpp if iocid is found.
1372 * Returns -1 if iocid is not found.
1373 */
1374int
1375mpt_verify_adapter(int iocid, MPT_ADAPTER **iocpp)
1376{
1377 MPT_ADAPTER *ioc;
1378
1379 list_for_each_entry(ioc,&ioc_list,list) {
1380 if (ioc->id == iocid) {
1381 *iocpp =ioc;
1382 return iocid;
1383 }
1384 }
1385
1386 *iocpp = NULL;
1387 return -1;
1388}
1389
1390/**
1391 * mpt_get_product_name - returns product string
1392 * @vendor: pci vendor id
1393 * @device: pci device id
1394 * @revision: pci revision id
1395 *
1396 * Returns product string displayed when driver loads,
1397 * in /proc/mpt/summary and /sysfs/class/scsi_host/host<X>/version_product
1398 *
1399 **/
1400static const char*
1401mpt_get_product_name(u16 vendor, u16 device, u8 revision)
1402{
1403 char *product_str = NULL;
1404
1405 if (vendor == PCI_VENDOR_ID_BROCADE) {
1406 switch (device)
1407 {
1408 case MPI_MANUFACTPAGE_DEVICEID_FC949E:
1409 switch (revision)
1410 {
1411 case 0x00:
1412 product_str = "BRE040 A0";
1413 break;
1414 case 0x01:
1415 product_str = "BRE040 A1";
1416 break;
1417 default:
1418 product_str = "BRE040";
1419 break;
1420 }
1421 break;
1422 }
1423 goto out;
1424 }
1425
1426 switch (device)
1427 {
1428 case MPI_MANUFACTPAGE_DEVICEID_FC909:
1429 product_str = "LSIFC909 B1";
1430 break;
1431 case MPI_MANUFACTPAGE_DEVICEID_FC919:
1432 product_str = "LSIFC919 B0";
1433 break;
1434 case MPI_MANUFACTPAGE_DEVICEID_FC929:
1435 product_str = "LSIFC929 B0";
1436 break;
1437 case MPI_MANUFACTPAGE_DEVICEID_FC919X:
1438 if (revision < 0x80)
1439 product_str = "LSIFC919X A0";
1440 else
1441 product_str = "LSIFC919XL A1";
1442 break;
1443 case MPI_MANUFACTPAGE_DEVICEID_FC929X:
1444 if (revision < 0x80)
1445 product_str = "LSIFC929X A0";
1446 else
1447 product_str = "LSIFC929XL A1";
1448 break;
1449 case MPI_MANUFACTPAGE_DEVICEID_FC939X:
1450 product_str = "LSIFC939X A1";
1451 break;
1452 case MPI_MANUFACTPAGE_DEVICEID_FC949X:
1453 product_str = "LSIFC949X A1";
1454 break;
1455 case MPI_MANUFACTPAGE_DEVICEID_FC949E:
1456 switch (revision)
1457 {
1458 case 0x00:
1459 product_str = "LSIFC949E A0";
1460 break;
1461 case 0x01:
1462 product_str = "LSIFC949E A1";
1463 break;
1464 default:
1465 product_str = "LSIFC949E";
1466 break;
1467 }
1468 break;
1469 case MPI_MANUFACTPAGE_DEVID_53C1030:
1470 switch (revision)
1471 {
1472 case 0x00:
1473 product_str = "LSI53C1030 A0";
1474 break;
1475 case 0x01:
1476 product_str = "LSI53C1030 B0";
1477 break;
1478 case 0x03:
1479 product_str = "LSI53C1030 B1";
1480 break;
1481 case 0x07:
1482 product_str = "LSI53C1030 B2";
1483 break;
1484 case 0x08:
1485 product_str = "LSI53C1030 C0";
1486 break;
1487 case 0x80:
1488 product_str = "LSI53C1030T A0";
1489 break;
1490 case 0x83:
1491 product_str = "LSI53C1030T A2";
1492 break;
1493 case 0x87:
1494 product_str = "LSI53C1030T A3";
1495 break;
1496 case 0xc1:
1497 product_str = "LSI53C1020A A1";
1498 break;
1499 default:
1500 product_str = "LSI53C1030";
1501 break;
1502 }
1503 break;
1504 case MPI_MANUFACTPAGE_DEVID_1030_53C1035:
1505 switch (revision)
1506 {
1507 case 0x03:
1508 product_str = "LSI53C1035 A2";
1509 break;
1510 case 0x04:
1511 product_str = "LSI53C1035 B0";
1512 break;
1513 default:
1514 product_str = "LSI53C1035";
1515 break;
1516 }
1517 break;
1518 case MPI_MANUFACTPAGE_DEVID_SAS1064:
1519 switch (revision)
1520 {
1521 case 0x00:
1522 product_str = "LSISAS1064 A1";
1523 break;
1524 case 0x01:
1525 product_str = "LSISAS1064 A2";
1526 break;
1527 case 0x02:
1528 product_str = "LSISAS1064 A3";
1529 break;
1530 case 0x03:
1531 product_str = "LSISAS1064 A4";
1532 break;
1533 default:
1534 product_str = "LSISAS1064";
1535 break;
1536 }
1537 break;
1538 case MPI_MANUFACTPAGE_DEVID_SAS1064E:
1539 switch (revision)
1540 {
1541 case 0x00:
1542 product_str = "LSISAS1064E A0";
1543 break;
1544 case 0x01:
1545 product_str = "LSISAS1064E B0";
1546 break;
1547 case 0x02:
1548 product_str = "LSISAS1064E B1";
1549 break;
1550 case 0x04:
1551 product_str = "LSISAS1064E B2";
1552 break;
1553 case 0x08:
1554 product_str = "LSISAS1064E B3";
1555 break;
1556 default:
1557 product_str = "LSISAS1064E";
1558 break;
1559 }
1560 break;
1561 case MPI_MANUFACTPAGE_DEVID_SAS1068:
1562 switch (revision)
1563 {
1564 case 0x00:
1565 product_str = "LSISAS1068 A0";
1566 break;
1567 case 0x01:
1568 product_str = "LSISAS1068 B0";
1569 break;
1570 case 0x02:
1571 product_str = "LSISAS1068 B1";
1572 break;
1573 default:
1574 product_str = "LSISAS1068";
1575 break;
1576 }
1577 break;
1578 case MPI_MANUFACTPAGE_DEVID_SAS1068E:
1579 switch (revision)
1580 {
1581 case 0x00:
1582 product_str = "LSISAS1068E A0";
1583 break;
1584 case 0x01:
1585 product_str = "LSISAS1068E B0";
1586 break;
1587 case 0x02:
1588 product_str = "LSISAS1068E B1";
1589 break;
1590 case 0x04:
1591 product_str = "LSISAS1068E B2";
1592 break;
1593 case 0x08:
1594 product_str = "LSISAS1068E B3";
1595 break;
1596 default:
1597 product_str = "LSISAS1068E";
1598 break;
1599 }
1600 break;
1601 case MPI_MANUFACTPAGE_DEVID_SAS1078:
1602 switch (revision)
1603 {
1604 case 0x00:
1605 product_str = "LSISAS1078 A0";
1606 break;
1607 case 0x01:
1608 product_str = "LSISAS1078 B0";
1609 break;
1610 case 0x02:
1611 product_str = "LSISAS1078 C0";
1612 break;
1613 case 0x03:
1614 product_str = "LSISAS1078 C1";
1615 break;
1616 case 0x04:
1617 product_str = "LSISAS1078 C2";
1618 break;
1619 default:
1620 product_str = "LSISAS1078";
1621 break;
1622 }
1623 break;
1624 }
1625
1626 out:
1627 return product_str;
1628}
1629
1630/**
1631 * mpt_mapresources - map in memory mapped io
1632 * @ioc: Pointer to pointer to IOC adapter
1633 *
1634 **/
1635static int
1636mpt_mapresources(MPT_ADAPTER *ioc)
1637{
1638 u8 __iomem *mem;
1639 int ii;
1640 resource_size_t mem_phys;
1641 unsigned long port;
1642 u32 msize;
1643 u32 psize;
1644 int r = -ENODEV;
1645 struct pci_dev *pdev;
1646
1647 pdev = ioc->pcidev;
1648 ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
1649 if (pci_enable_device_mem(pdev)) {
1650 printk(MYIOC_s_ERR_FMT "pci_enable_device_mem() "
1651 "failed\n", ioc->name);
1652 return r;
1653 }
1654 if (pci_request_selected_regions(pdev, ioc->bars, "mpt")) {
1655 printk(MYIOC_s_ERR_FMT "pci_request_selected_regions() with "
1656 "MEM failed\n", ioc->name);
1657 goto out_pci_disable_device;
1658 }
1659
1660 if (sizeof(dma_addr_t) > 4) {
1661 const uint64_t required_mask = dma_get_required_mask
1662 (&pdev->dev);
1663 if (required_mask > DMA_BIT_MASK(32)
1664 && !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))
1665 && !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
1666 ioc->dma_mask = DMA_BIT_MASK(64);
1667 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
1668 ": 64 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
1669 ioc->name));
1670 } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))
1671 && !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) {
1672 ioc->dma_mask = DMA_BIT_MASK(32);
1673 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
1674 ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
1675 ioc->name));
1676 } else {
1677 printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n",
1678 ioc->name, pci_name(pdev));
1679 goto out_pci_release_region;
1680 }
1681 } else {
1682 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))
1683 && !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) {
1684 ioc->dma_mask = DMA_BIT_MASK(32);
1685 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
1686 ": 32 BIT PCI BUS DMA ADDRESSING SUPPORTED\n",
1687 ioc->name));
1688 } else {
1689 printk(MYIOC_s_WARN_FMT "no suitable DMA mask for %s\n",
1690 ioc->name, pci_name(pdev));
1691 goto out_pci_release_region;
1692 }
1693 }
1694
1695 mem_phys = msize = 0;
1696 port = psize = 0;
1697 for (ii = 0; ii < DEVICE_COUNT_RESOURCE; ii++) {
1698 if (pci_resource_flags(pdev, ii) & PCI_BASE_ADDRESS_SPACE_IO) {
1699 if (psize)
1700 continue;
1701 /* Get I/O space! */
1702 port = pci_resource_start(pdev, ii);
1703 psize = pci_resource_len(pdev, ii);
1704 } else {
1705 if (msize)
1706 continue;
1707 /* Get memmap */
1708 mem_phys = pci_resource_start(pdev, ii);
1709 msize = pci_resource_len(pdev, ii);
1710 }
1711 }
1712 ioc->mem_size = msize;
1713
1714 mem = NULL;
1715 /* Get logical ptr for PciMem0 space */
1716 /*mem = ioremap(mem_phys, msize);*/
1717 mem = ioremap(mem_phys, msize);
1718 if (mem == NULL) {
1719 printk(MYIOC_s_ERR_FMT ": ERROR - Unable to map adapter"
1720 " memory!\n", ioc->name);
1721 r = -EINVAL;
1722 goto out_pci_release_region;
1723 }
1724 ioc->memmap = mem;
1725 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "mem = %p, mem_phys = %llx\n",
1726 ioc->name, mem, (unsigned long long)mem_phys));
1727
1728 ioc->mem_phys = mem_phys;
1729 ioc->chip = (SYSIF_REGS __iomem *)mem;
1730
1731 /* Save Port IO values in case we need to do downloadboot */
1732 ioc->pio_mem_phys = port;
1733 ioc->pio_chip = (SYSIF_REGS __iomem *)port;
1734
1735 return 0;
1736
1737out_pci_release_region:
1738 pci_release_selected_regions(pdev, ioc->bars);
1739out_pci_disable_device:
1740 pci_disable_device(pdev);
1741 return r;
1742}
1743
1744/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
1745/**
1746 * mpt_attach - Install a PCI intelligent MPT adapter.
1747 * @pdev: Pointer to pci_dev structure
1748 * @id: PCI device ID information
1749 *
1750 * This routine performs all the steps necessary to bring the IOC of
1751 * a MPT adapter to a OPERATIONAL state. This includes registering
1752 * memory regions, registering the interrupt, and allocating request
1753 * and reply memory pools.
1754 *
1755 * This routine also pre-fetches the LAN MAC address of a Fibre Channel
1756 * MPT adapter.
1757 *
1758 * Returns 0 for success, non-zero for failure.
1759 *
1760 * TODO: Add support for polled controllers
1761 */
1762int
1763mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1764{
1765 MPT_ADAPTER *ioc;
1766 u8 cb_idx;
1767 int r = -ENODEV;
1768 u8 pcixcmd;
1769 static int mpt_ids = 0;
1770#ifdef CONFIG_PROC_FS
1771 struct proc_dir_entry *dent;
1772#endif
1773
1774 ioc = kzalloc(sizeof(MPT_ADAPTER), GFP_KERNEL);
1775 if (ioc == NULL) {
1776 printk(KERN_ERR MYNAM ": ERROR - Insufficient memory to add adapter!\n");
1777 return -ENOMEM;
1778 }
1779
1780 ioc->id = mpt_ids++;
1781 sprintf(ioc->name, "ioc%d", ioc->id);
1782 dinitprintk(ioc, printk(KERN_WARNING MYNAM ": mpt_adapter_install\n"));
1783
1784 /*
1785 * set initial debug level
1786 * (refer to mptdebug.h)
1787 *
1788 */
1789 ioc->debug_level = mpt_debug_level;
1790 if (mpt_debug_level)
1791 printk(KERN_INFO "mpt_debug_level=%xh\n", mpt_debug_level);
1792
1793 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": mpt_adapter_install\n", ioc->name));
1794
1795 ioc->pcidev = pdev;
1796 if (mpt_mapresources(ioc)) {
1797 goto out_free_ioc;
1798 }
1799
1800 /*
1801 * Setting up proper handlers for scatter gather handling
1802 */
1803 if (ioc->dma_mask == DMA_BIT_MASK(64)) {
1804 if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078)
1805 ioc->add_sge = &mpt_add_sge_64bit_1078;
1806 else
1807 ioc->add_sge = &mpt_add_sge_64bit;
1808 ioc->add_chain = &mpt_add_chain_64bit;
1809 ioc->sg_addr_size = 8;
1810 } else {
1811 ioc->add_sge = &mpt_add_sge;
1812 ioc->add_chain = &mpt_add_chain;
1813 ioc->sg_addr_size = 4;
1814 }
1815 ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size;
1816
1817 ioc->alloc_total = sizeof(MPT_ADAPTER);
1818 ioc->req_sz = MPT_DEFAULT_FRAME_SIZE; /* avoid div by zero! */
1819 ioc->reply_sz = MPT_REPLY_FRAME_SIZE;
1820
1821
1822 spin_lock_init(&ioc->taskmgmt_lock);
1823 mutex_init(&ioc->internal_cmds.mutex);
1824 init_completion(&ioc->internal_cmds.done);
1825 mutex_init(&ioc->mptbase_cmds.mutex);
1826 init_completion(&ioc->mptbase_cmds.done);
1827 mutex_init(&ioc->taskmgmt_cmds.mutex);
1828 init_completion(&ioc->taskmgmt_cmds.done);
1829
1830 /* Initialize the event logging.
1831 */
1832 ioc->eventTypes = 0; /* None */
1833 ioc->eventContext = 0;
1834 ioc->eventLogSize = 0;
1835 ioc->events = NULL;
1836
1837#ifdef MFCNT
1838 ioc->mfcnt = 0;
1839#endif
1840
1841 ioc->sh = NULL;
1842 ioc->cached_fw = NULL;
1843
1844 /* Initialize SCSI Config Data structure
1845 */
1846 memset(&ioc->spi_data, 0, sizeof(SpiCfgData));
1847
1848 /* Initialize the fc rport list head.
1849 */
1850 INIT_LIST_HEAD(&ioc->fc_rports);
1851
1852 /* Find lookup slot. */
1853 INIT_LIST_HEAD(&ioc->list);
1854
1855
1856 /* Initialize workqueue */
1857 INIT_DELAYED_WORK(&ioc->fault_reset_work, mpt_fault_reset_work);
1858
1859 snprintf(ioc->reset_work_q_name, MPT_KOBJ_NAME_LEN,
1860 "mpt_poll_%d", ioc->id);
1861 ioc->reset_work_q = alloc_workqueue(ioc->reset_work_q_name,
1862 WQ_MEM_RECLAIM, 0);
1863 if (!ioc->reset_work_q) {
1864 printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n",
1865 ioc->name);
1866 r = -ENOMEM;
1867 goto out_unmap_resources;
1868 }
1869
1870 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "facts @ %p, pfacts[0] @ %p\n",
1871 ioc->name, &ioc->facts, &ioc->pfacts[0]));
1872
1873 ioc->prod_name = mpt_get_product_name(pdev->vendor, pdev->device,
1874 pdev->revision);
1875
1876 switch (pdev->device)
1877 {
1878 case MPI_MANUFACTPAGE_DEVICEID_FC939X:
1879 case MPI_MANUFACTPAGE_DEVICEID_FC949X:
1880 ioc->errata_flag_1064 = 1;
1881 fallthrough;
1882 case MPI_MANUFACTPAGE_DEVICEID_FC909:
1883 case MPI_MANUFACTPAGE_DEVICEID_FC929:
1884 case MPI_MANUFACTPAGE_DEVICEID_FC919:
1885 case MPI_MANUFACTPAGE_DEVICEID_FC949E:
1886 ioc->bus_type = FC;
1887 break;
1888
1889 case MPI_MANUFACTPAGE_DEVICEID_FC929X:
1890 if (pdev->revision < XL_929) {
1891 /* 929X Chip Fix. Set Split transactions level
1892 * for PCIX. Set MOST bits to zero.
1893 */
1894 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1895 pcixcmd &= 0x8F;
1896 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1897 } else {
1898 /* 929XL Chip Fix. Set MMRBC to 0x08.
1899 */
1900 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1901 pcixcmd |= 0x08;
1902 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1903 }
1904 ioc->bus_type = FC;
1905 break;
1906
1907 case MPI_MANUFACTPAGE_DEVICEID_FC919X:
1908 /* 919X Chip Fix. Set Split transactions level
1909 * for PCIX. Set MOST bits to zero.
1910 */
1911 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1912 pcixcmd &= 0x8F;
1913 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1914 ioc->bus_type = FC;
1915 break;
1916
1917 case MPI_MANUFACTPAGE_DEVID_53C1030:
1918 /* 1030 Chip Fix. Disable Split transactions
1919 * for PCIX. Set MOST bits to zero if Rev < C0( = 8).
1920 */
1921 if (pdev->revision < C0_1030) {
1922 pci_read_config_byte(pdev, 0x6a, &pcixcmd);
1923 pcixcmd &= 0x8F;
1924 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1925 }
1926 fallthrough;
1927
1928 case MPI_MANUFACTPAGE_DEVID_1030_53C1035:
1929 ioc->bus_type = SPI;
1930 break;
1931
1932 case MPI_MANUFACTPAGE_DEVID_SAS1064:
1933 case MPI_MANUFACTPAGE_DEVID_SAS1068:
1934 ioc->errata_flag_1064 = 1;
1935 ioc->bus_type = SAS;
1936 break;
1937
1938 case MPI_MANUFACTPAGE_DEVID_SAS1064E:
1939 case MPI_MANUFACTPAGE_DEVID_SAS1068E:
1940 case MPI_MANUFACTPAGE_DEVID_SAS1078:
1941 ioc->bus_type = SAS;
1942 break;
1943 }
1944
1945
1946 switch (ioc->bus_type) {
1947
1948 case SAS:
1949 ioc->msi_enable = mpt_msi_enable_sas;
1950 break;
1951
1952 case SPI:
1953 ioc->msi_enable = mpt_msi_enable_spi;
1954 break;
1955
1956 case FC:
1957 ioc->msi_enable = mpt_msi_enable_fc;
1958 break;
1959
1960 default:
1961 ioc->msi_enable = 0;
1962 break;
1963 }
1964
1965 ioc->fw_events_off = 1;
1966
1967 if (ioc->errata_flag_1064)
1968 pci_disable_io_access(pdev);
1969
1970 spin_lock_init(&ioc->FreeQlock);
1971
1972 /* Disable all! */
1973 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
1974 ioc->active = 0;
1975 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
1976
1977 /* Set IOC ptr in the pcidev's driver data. */
1978 pci_set_drvdata(ioc->pcidev, ioc);
1979
1980 /* Set lookup ptr. */
1981 list_add_tail(&ioc->list, &ioc_list);
1982
1983 /* Check for "bound ports" (929, 929X, 1030, 1035) to reduce redundant resets.
1984 */
1985 mpt_detect_bound_ports(ioc, pdev);
1986
1987 INIT_LIST_HEAD(&ioc->fw_event_list);
1988 spin_lock_init(&ioc->fw_event_lock);
1989 snprintf(ioc->fw_event_q_name, MPT_KOBJ_NAME_LEN, "mpt/%d", ioc->id);
1990 ioc->fw_event_q = alloc_workqueue(ioc->fw_event_q_name,
1991 WQ_MEM_RECLAIM, 0);
1992 if (!ioc->fw_event_q) {
1993 printk(MYIOC_s_ERR_FMT "Insufficient memory to add adapter!\n",
1994 ioc->name);
1995 r = -ENOMEM;
1996 goto out_remove_ioc;
1997 }
1998
1999 if ((r = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP,
2000 CAN_SLEEP)) != 0){
2001 printk(MYIOC_s_ERR_FMT "didn't initialize properly! (%d)\n",
2002 ioc->name, r);
2003
2004 destroy_workqueue(ioc->fw_event_q);
2005 ioc->fw_event_q = NULL;
2006
2007 list_del(&ioc->list);
2008 if (ioc->alt_ioc)
2009 ioc->alt_ioc->alt_ioc = NULL;
2010 iounmap(ioc->memmap);
2011 if (pci_is_enabled(pdev))
2012 pci_disable_device(pdev);
2013 if (r != -5)
2014 pci_release_selected_regions(pdev, ioc->bars);
2015
2016 destroy_workqueue(ioc->reset_work_q);
2017 ioc->reset_work_q = NULL;
2018
2019 kfree(ioc);
2020 return r;
2021 }
2022
2023 /* call per device driver probe entry point */
2024 for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
2025 if(MptDeviceDriverHandlers[cb_idx] &&
2026 MptDeviceDriverHandlers[cb_idx]->probe) {
2027 MptDeviceDriverHandlers[cb_idx]->probe(pdev);
2028 }
2029 }
2030
2031#ifdef CONFIG_PROC_FS
2032 /*
2033 * Create "/proc/mpt/iocN" subdirectory entry for each MPT adapter.
2034 */
2035 dent = proc_mkdir(ioc->name, mpt_proc_root_dir);
2036 if (dent) {
2037 proc_create_single_data("info", S_IRUGO, dent,
2038 mpt_iocinfo_proc_show, ioc);
2039 proc_create_single_data("summary", S_IRUGO, dent,
2040 mpt_summary_proc_show, ioc);
2041 }
2042#endif
2043
2044 if (!ioc->alt_ioc)
2045 queue_delayed_work(ioc->reset_work_q, &ioc->fault_reset_work,
2046 msecs_to_jiffies(MPT_POLLING_INTERVAL));
2047
2048 return 0;
2049
2050out_remove_ioc:
2051 list_del(&ioc->list);
2052 if (ioc->alt_ioc)
2053 ioc->alt_ioc->alt_ioc = NULL;
2054
2055 destroy_workqueue(ioc->reset_work_q);
2056 ioc->reset_work_q = NULL;
2057
2058out_unmap_resources:
2059 iounmap(ioc->memmap);
2060 pci_disable_device(pdev);
2061 pci_release_selected_regions(pdev, ioc->bars);
2062
2063out_free_ioc:
2064 kfree(ioc);
2065
2066 return r;
2067}
2068
2069/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2070/**
2071 * mpt_detach - Remove a PCI intelligent MPT adapter.
2072 * @pdev: Pointer to pci_dev structure
2073 */
2074
2075void
2076mpt_detach(struct pci_dev *pdev)
2077{
2078 MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
2079 char pname[64];
2080 u8 cb_idx;
2081 unsigned long flags;
2082 struct workqueue_struct *wq;
2083
2084 /*
2085 * Stop polling ioc for fault condition
2086 */
2087 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
2088 wq = ioc->reset_work_q;
2089 ioc->reset_work_q = NULL;
2090 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
2091 cancel_delayed_work(&ioc->fault_reset_work);
2092 destroy_workqueue(wq);
2093
2094 spin_lock_irqsave(&ioc->fw_event_lock, flags);
2095 wq = ioc->fw_event_q;
2096 ioc->fw_event_q = NULL;
2097 spin_unlock_irqrestore(&ioc->fw_event_lock, flags);
2098 destroy_workqueue(wq);
2099
2100 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s/summary", ioc->name);
2101 remove_proc_entry(pname, NULL);
2102 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s/info", ioc->name);
2103 remove_proc_entry(pname, NULL);
2104 snprintf(pname, sizeof(pname), MPT_PROCFS_MPTBASEDIR "/%s", ioc->name);
2105 remove_proc_entry(pname, NULL);
2106
2107 /* call per device driver remove entry point */
2108 for(cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
2109 if(MptDeviceDriverHandlers[cb_idx] &&
2110 MptDeviceDriverHandlers[cb_idx]->remove) {
2111 MptDeviceDriverHandlers[cb_idx]->remove(pdev);
2112 }
2113 }
2114
2115 /* Disable interrupts! */
2116 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2117
2118 ioc->active = 0;
2119 synchronize_irq(pdev->irq);
2120
2121 /* Clear any lingering interrupt */
2122 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
2123
2124 CHIPREG_READ32(&ioc->chip->IntStatus);
2125
2126 mpt_adapter_dispose(ioc);
2127
2128}
2129
2130/**************************************************************************
2131 * Power Management
2132 */
2133#ifdef CONFIG_PM
2134/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2135/**
2136 * mpt_suspend - Fusion MPT base driver suspend routine.
2137 * @pdev: Pointer to pci_dev structure
2138 * @state: new state to enter
2139 */
2140int
2141mpt_suspend(struct pci_dev *pdev, pm_message_t state)
2142{
2143 u32 device_state;
2144 MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
2145
2146 device_state = pci_choose_state(pdev, state);
2147 printk(MYIOC_s_INFO_FMT "pci-suspend: pdev=0x%p, slot=%s, Entering "
2148 "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev),
2149 device_state);
2150
2151 /* put ioc into READY_STATE */
2152 if (SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, CAN_SLEEP)) {
2153 printk(MYIOC_s_ERR_FMT
2154 "pci-suspend: IOC msg unit reset failed!\n", ioc->name);
2155 }
2156
2157 /* disable interrupts */
2158 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2159 ioc->active = 0;
2160
2161 /* Clear any lingering interrupt */
2162 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
2163
2164 free_irq(ioc->pci_irq, ioc);
2165 if (ioc->msi_enable)
2166 pci_disable_msi(ioc->pcidev);
2167 ioc->pci_irq = -1;
2168 pci_save_state(pdev);
2169 pci_disable_device(pdev);
2170 pci_release_selected_regions(pdev, ioc->bars);
2171 pci_set_power_state(pdev, device_state);
2172 return 0;
2173}
2174
2175/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2176/**
2177 * mpt_resume - Fusion MPT base driver resume routine.
2178 * @pdev: Pointer to pci_dev structure
2179 */
2180int
2181mpt_resume(struct pci_dev *pdev)
2182{
2183 MPT_ADAPTER *ioc = pci_get_drvdata(pdev);
2184 u32 device_state = pdev->current_state;
2185 int recovery_state;
2186 int err;
2187
2188 printk(MYIOC_s_INFO_FMT "pci-resume: pdev=0x%p, slot=%s, Previous "
2189 "operating state [D%d]\n", ioc->name, pdev, pci_name(pdev),
2190 device_state);
2191
2192 pci_set_power_state(pdev, PCI_D0);
2193 pci_enable_wake(pdev, PCI_D0, 0);
2194 pci_restore_state(pdev);
2195 ioc->pcidev = pdev;
2196 err = mpt_mapresources(ioc);
2197 if (err)
2198 return err;
2199
2200 if (ioc->dma_mask == DMA_BIT_MASK(64)) {
2201 if (pdev->device == MPI_MANUFACTPAGE_DEVID_SAS1078)
2202 ioc->add_sge = &mpt_add_sge_64bit_1078;
2203 else
2204 ioc->add_sge = &mpt_add_sge_64bit;
2205 ioc->add_chain = &mpt_add_chain_64bit;
2206 ioc->sg_addr_size = 8;
2207 } else {
2208
2209 ioc->add_sge = &mpt_add_sge;
2210 ioc->add_chain = &mpt_add_chain;
2211 ioc->sg_addr_size = 4;
2212 }
2213 ioc->SGE_size = sizeof(u32) + ioc->sg_addr_size;
2214
2215 printk(MYIOC_s_INFO_FMT "pci-resume: ioc-state=0x%x,doorbell=0x%x\n",
2216 ioc->name, (mpt_GetIocState(ioc, 1) >> MPI_IOC_STATE_SHIFT),
2217 CHIPREG_READ32(&ioc->chip->Doorbell));
2218
2219 /*
2220 * Errata workaround for SAS pci express:
2221 * Upon returning to the D0 state, the contents of the doorbell will be
2222 * stale data, and this will incorrectly signal to the host driver that
2223 * the firmware is ready to process mpt commands. The workaround is
2224 * to issue a diagnostic reset.
2225 */
2226 if (ioc->bus_type == SAS && (pdev->device ==
2227 MPI_MANUFACTPAGE_DEVID_SAS1068E || pdev->device ==
2228 MPI_MANUFACTPAGE_DEVID_SAS1064E)) {
2229 if (KickStart(ioc, 1, CAN_SLEEP) < 0) {
2230 printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover\n",
2231 ioc->name);
2232 goto out;
2233 }
2234 }
2235
2236 /* bring ioc to operational state */
2237 printk(MYIOC_s_INFO_FMT "Sending mpt_do_ioc_recovery\n", ioc->name);
2238 recovery_state = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_BRINGUP,
2239 CAN_SLEEP);
2240 if (recovery_state != 0)
2241 printk(MYIOC_s_WARN_FMT "pci-resume: Cannot recover, "
2242 "error:[%x]\n", ioc->name, recovery_state);
2243 else
2244 printk(MYIOC_s_INFO_FMT
2245 "pci-resume: success\n", ioc->name);
2246 out:
2247 return 0;
2248
2249}
2250#endif
2251
2252static int
2253mpt_signal_reset(u8 index, MPT_ADAPTER *ioc, int reset_phase)
2254{
2255 if ((MptDriverClass[index] == MPTSPI_DRIVER &&
2256 ioc->bus_type != SPI) ||
2257 (MptDriverClass[index] == MPTFC_DRIVER &&
2258 ioc->bus_type != FC) ||
2259 (MptDriverClass[index] == MPTSAS_DRIVER &&
2260 ioc->bus_type != SAS))
2261 /* make sure we only call the relevant reset handler
2262 * for the bus */
2263 return 0;
2264 return (MptResetHandlers[index])(ioc, reset_phase);
2265}
2266
2267/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2268/**
2269 * mpt_do_ioc_recovery - Initialize or recover MPT adapter.
2270 * @ioc: Pointer to MPT adapter structure
2271 * @reason: Event word / reason
2272 * @sleepFlag: Use schedule if CAN_SLEEP else use udelay.
2273 *
2274 * This routine performs all the steps necessary to bring the IOC
2275 * to a OPERATIONAL state.
2276 *
2277 * This routine also pre-fetches the LAN MAC address of a Fibre Channel
2278 * MPT adapter.
2279 *
2280 * Returns:
2281 * 0 for success
2282 * -1 if failed to get board READY
2283 * -2 if READY but IOCFacts Failed
2284 * -3 if READY but PrimeIOCFifos Failed
2285 * -4 if READY but IOCInit Failed
2286 * -5 if failed to enable_device and/or request_selected_regions
2287 * -6 if failed to upload firmware
2288 */
2289static int
2290mpt_do_ioc_recovery(MPT_ADAPTER *ioc, u32 reason, int sleepFlag)
2291{
2292 int hard_reset_done = 0;
2293 int alt_ioc_ready = 0;
2294 int hard;
2295 int rc=0;
2296 int ii;
2297 int ret = 0;
2298 int reset_alt_ioc_active = 0;
2299 int irq_allocated = 0;
2300 u8 *a;
2301
2302 printk(MYIOC_s_INFO_FMT "Initiating %s\n", ioc->name,
2303 reason == MPT_HOSTEVENT_IOC_BRINGUP ? "bringup" : "recovery");
2304
2305 /* Disable reply interrupts (also blocks FreeQ) */
2306 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2307 ioc->active = 0;
2308
2309 if (ioc->alt_ioc) {
2310 if (ioc->alt_ioc->active ||
2311 reason == MPT_HOSTEVENT_IOC_RECOVER) {
2312 reset_alt_ioc_active = 1;
2313 /* Disable alt-IOC's reply interrupts
2314 * (and FreeQ) for a bit
2315 **/
2316 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask,
2317 0xFFFFFFFF);
2318 ioc->alt_ioc->active = 0;
2319 }
2320 }
2321
2322 hard = 1;
2323 if (reason == MPT_HOSTEVENT_IOC_BRINGUP)
2324 hard = 0;
2325
2326 if ((hard_reset_done = MakeIocReady(ioc, hard, sleepFlag)) < 0) {
2327 if (hard_reset_done == -4) {
2328 printk(MYIOC_s_WARN_FMT "Owned by PEER..skipping!\n",
2329 ioc->name);
2330
2331 if (reset_alt_ioc_active && ioc->alt_ioc) {
2332 /* (re)Enable alt-IOC! (reply interrupt, FreeQ) */
2333 dprintk(ioc, printk(MYIOC_s_INFO_FMT
2334 "alt_ioc reply irq re-enabled\n", ioc->alt_ioc->name));
2335 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask, MPI_HIM_DIM);
2336 ioc->alt_ioc->active = 1;
2337 }
2338
2339 } else {
2340 printk(MYIOC_s_WARN_FMT
2341 "NOT READY WARNING!\n", ioc->name);
2342 }
2343 ret = -1;
2344 goto out;
2345 }
2346
2347 /* hard_reset_done = 0 if a soft reset was performed
2348 * and 1 if a hard reset was performed.
2349 */
2350 if (hard_reset_done && reset_alt_ioc_active && ioc->alt_ioc) {
2351 if ((rc = MakeIocReady(ioc->alt_ioc, 0, sleepFlag)) == 0)
2352 alt_ioc_ready = 1;
2353 else
2354 printk(MYIOC_s_WARN_FMT
2355 ": alt-ioc Not ready WARNING!\n",
2356 ioc->alt_ioc->name);
2357 }
2358
2359 for (ii=0; ii<5; ii++) {
2360 /* Get IOC facts! Allow 5 retries */
2361 if ((rc = GetIocFacts(ioc, sleepFlag, reason)) == 0)
2362 break;
2363 }
2364
2365
2366 if (ii == 5) {
2367 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2368 "Retry IocFacts failed rc=%x\n", ioc->name, rc));
2369 ret = -2;
2370 } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
2371 MptDisplayIocCapabilities(ioc);
2372 }
2373
2374 if (alt_ioc_ready) {
2375 if ((rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason)) != 0) {
2376 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2377 "Initial Alt IocFacts failed rc=%x\n",
2378 ioc->name, rc));
2379 /* Retry - alt IOC was initialized once
2380 */
2381 rc = GetIocFacts(ioc->alt_ioc, sleepFlag, reason);
2382 }
2383 if (rc) {
2384 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2385 "Retry Alt IocFacts failed rc=%x\n", ioc->name, rc));
2386 alt_ioc_ready = 0;
2387 reset_alt_ioc_active = 0;
2388 } else if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
2389 MptDisplayIocCapabilities(ioc->alt_ioc);
2390 }
2391 }
2392
2393 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP) &&
2394 (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)) {
2395 pci_release_selected_regions(ioc->pcidev, ioc->bars);
2396 ioc->bars = pci_select_bars(ioc->pcidev, IORESOURCE_MEM |
2397 IORESOURCE_IO);
2398 if (pci_enable_device(ioc->pcidev))
2399 return -5;
2400 if (pci_request_selected_regions(ioc->pcidev, ioc->bars,
2401 "mpt"))
2402 return -5;
2403 }
2404
2405 /*
2406 * Device is reset now. It must have de-asserted the interrupt line
2407 * (if it was asserted) and it should be safe to register for the
2408 * interrupt now.
2409 */
2410 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) {
2411 ioc->pci_irq = -1;
2412 if (ioc->pcidev->irq) {
2413 if (ioc->msi_enable && !pci_enable_msi(ioc->pcidev))
2414 printk(MYIOC_s_INFO_FMT "PCI-MSI enabled\n",
2415 ioc->name);
2416 else
2417 ioc->msi_enable = 0;
2418 rc = request_irq(ioc->pcidev->irq, mpt_interrupt,
2419 IRQF_SHARED, ioc->name, ioc);
2420 if (rc < 0) {
2421 printk(MYIOC_s_ERR_FMT "Unable to allocate "
2422 "interrupt %d!\n",
2423 ioc->name, ioc->pcidev->irq);
2424 if (ioc->msi_enable)
2425 pci_disable_msi(ioc->pcidev);
2426 ret = -EBUSY;
2427 goto out;
2428 }
2429 irq_allocated = 1;
2430 ioc->pci_irq = ioc->pcidev->irq;
2431 pci_set_master(ioc->pcidev); /* ?? */
2432 pci_set_drvdata(ioc->pcidev, ioc);
2433 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2434 "installed at interrupt %d\n", ioc->name,
2435 ioc->pcidev->irq));
2436 }
2437 }
2438
2439 /* Prime reply & request queues!
2440 * (mucho alloc's) Must be done prior to
2441 * init as upper addresses are needed for init.
2442 * If fails, continue with alt-ioc processing
2443 */
2444 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "PrimeIocFifos\n",
2445 ioc->name));
2446 if ((ret == 0) && ((rc = PrimeIocFifos(ioc)) != 0))
2447 ret = -3;
2448
2449 /* May need to check/upload firmware & data here!
2450 * If fails, continue with alt-ioc processing
2451 */
2452 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT "SendIocInit\n",
2453 ioc->name));
2454 if ((ret == 0) && ((rc = SendIocInit(ioc, sleepFlag)) != 0))
2455 ret = -4;
2456// NEW!
2457 if (alt_ioc_ready && ((rc = PrimeIocFifos(ioc->alt_ioc)) != 0)) {
2458 printk(MYIOC_s_WARN_FMT
2459 ": alt-ioc (%d) FIFO mgmt alloc WARNING!\n",
2460 ioc->alt_ioc->name, rc);
2461 alt_ioc_ready = 0;
2462 reset_alt_ioc_active = 0;
2463 }
2464
2465 if (alt_ioc_ready) {
2466 if ((rc = SendIocInit(ioc->alt_ioc, sleepFlag)) != 0) {
2467 alt_ioc_ready = 0;
2468 reset_alt_ioc_active = 0;
2469 printk(MYIOC_s_WARN_FMT
2470 ": alt-ioc: (%d) init failure WARNING!\n",
2471 ioc->alt_ioc->name, rc);
2472 }
2473 }
2474
2475 if (reason == MPT_HOSTEVENT_IOC_BRINGUP){
2476 if (ioc->upload_fw) {
2477 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2478 "firmware upload required!\n", ioc->name));
2479
2480 /* Controller is not operational, cannot do upload
2481 */
2482 if (ret == 0) {
2483 rc = mpt_do_upload(ioc, sleepFlag);
2484 if (rc == 0) {
2485 if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) {
2486 /*
2487 * Maintain only one pointer to FW memory
2488 * so there will not be two attempt to
2489 * downloadboot onboard dual function
2490 * chips (mpt_adapter_disable,
2491 * mpt_diag_reset)
2492 */
2493 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2494 "mpt_upload: alt_%s has cached_fw=%p \n",
2495 ioc->name, ioc->alt_ioc->name, ioc->alt_ioc->cached_fw));
2496 ioc->cached_fw = NULL;
2497 }
2498 } else {
2499 printk(MYIOC_s_WARN_FMT
2500 "firmware upload failure!\n", ioc->name);
2501 ret = -6;
2502 }
2503 }
2504 }
2505 }
2506
2507 /* Enable MPT base driver management of EventNotification
2508 * and EventAck handling.
2509 */
2510 if ((ret == 0) && (!ioc->facts.EventState)) {
2511 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2512 "SendEventNotification\n",
2513 ioc->name));
2514 ret = SendEventNotification(ioc, 1, sleepFlag); /* 1=Enable */
2515 }
2516
2517 if (ioc->alt_ioc && alt_ioc_ready && !ioc->alt_ioc->facts.EventState)
2518 rc = SendEventNotification(ioc->alt_ioc, 1, sleepFlag);
2519
2520 if (ret == 0) {
2521 /* Enable! (reply interrupt) */
2522 CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM);
2523 ioc->active = 1;
2524 }
2525 if (rc == 0) { /* alt ioc */
2526 if (reset_alt_ioc_active && ioc->alt_ioc) {
2527 /* (re)Enable alt-IOC! (reply interrupt) */
2528 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "alt-ioc"
2529 "reply irq re-enabled\n",
2530 ioc->alt_ioc->name));
2531 CHIPREG_WRITE32(&ioc->alt_ioc->chip->IntMask,
2532 MPI_HIM_DIM);
2533 ioc->alt_ioc->active = 1;
2534 }
2535 }
2536
2537
2538 /* Add additional "reason" check before call to GetLanConfigPages
2539 * (combined with GetIoUnitPage2 call). This prevents a somewhat
2540 * recursive scenario; GetLanConfigPages times out, timer expired
2541 * routine calls HardResetHandler, which calls into here again,
2542 * and we try GetLanConfigPages again...
2543 */
2544 if ((ret == 0) && (reason == MPT_HOSTEVENT_IOC_BRINGUP)) {
2545
2546 /*
2547 * Initialize link list for inactive raid volumes.
2548 */
2549 mutex_init(&ioc->raid_data.inactive_list_mutex);
2550 INIT_LIST_HEAD(&ioc->raid_data.inactive_list);
2551
2552 switch (ioc->bus_type) {
2553
2554 case SAS:
2555 /* clear persistency table */
2556 if(ioc->facts.IOCExceptions &
2557 MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL) {
2558 ret = mptbase_sas_persist_operation(ioc,
2559 MPI_SAS_OP_CLEAR_NOT_PRESENT);
2560 if(ret != 0)
2561 goto out;
2562 }
2563
2564 /* Find IM volumes
2565 */
2566 mpt_findImVolumes(ioc);
2567
2568 /* Check, and possibly reset, the coalescing value
2569 */
2570 mpt_read_ioc_pg_1(ioc);
2571
2572 break;
2573
2574 case FC:
2575 if ((ioc->pfacts[0].ProtocolFlags &
2576 MPI_PORTFACTS_PROTOCOL_LAN) &&
2577 (ioc->lan_cnfg_page0.Header.PageLength == 0)) {
2578 /*
2579 * Pre-fetch the ports LAN MAC address!
2580 * (LANPage1_t stuff)
2581 */
2582 (void) GetLanConfigPages(ioc);
2583 a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
2584 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2585 "LanAddr = %pMR\n", ioc->name, a));
2586 }
2587 break;
2588
2589 case SPI:
2590 /* Get NVRAM and adapter maximums from SPP 0 and 2
2591 */
2592 mpt_GetScsiPortSettings(ioc, 0);
2593
2594 /* Get version and length of SDP 1
2595 */
2596 mpt_readScsiDevicePageHeaders(ioc, 0);
2597
2598 /* Find IM volumes
2599 */
2600 if (ioc->facts.MsgVersion >= MPI_VERSION_01_02)
2601 mpt_findImVolumes(ioc);
2602
2603 /* Check, and possibly reset, the coalescing value
2604 */
2605 mpt_read_ioc_pg_1(ioc);
2606
2607 mpt_read_ioc_pg_4(ioc);
2608
2609 break;
2610 }
2611
2612 GetIoUnitPage2(ioc);
2613 mpt_get_manufacturing_pg_0(ioc);
2614 }
2615
2616 out:
2617 if ((ret != 0) && irq_allocated) {
2618 free_irq(ioc->pci_irq, ioc);
2619 if (ioc->msi_enable)
2620 pci_disable_msi(ioc->pcidev);
2621 }
2622 return ret;
2623}
2624
2625/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2626/**
2627 * mpt_detect_bound_ports - Search for matching PCI bus/dev_function
2628 * @ioc: Pointer to MPT adapter structure
2629 * @pdev: Pointer to (struct pci_dev) structure
2630 *
2631 * Search for PCI bus/dev_function which matches
2632 * PCI bus/dev_function (+/-1) for newly discovered 929,
2633 * 929X, 1030 or 1035.
2634 *
2635 * If match on PCI dev_function +/-1 is found, bind the two MPT adapters
2636 * using alt_ioc pointer fields in their %MPT_ADAPTER structures.
2637 */
2638static void
2639mpt_detect_bound_ports(MPT_ADAPTER *ioc, struct pci_dev *pdev)
2640{
2641 struct pci_dev *peer=NULL;
2642 unsigned int slot = PCI_SLOT(pdev->devfn);
2643 unsigned int func = PCI_FUNC(pdev->devfn);
2644 MPT_ADAPTER *ioc_srch;
2645
2646 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "PCI device %s devfn=%x/%x,"
2647 " searching for devfn match on %x or %x\n",
2648 ioc->name, pci_name(pdev), pdev->bus->number,
2649 pdev->devfn, func-1, func+1));
2650
2651 peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func-1));
2652 if (!peer) {
2653 peer = pci_get_slot(pdev->bus, PCI_DEVFN(slot,func+1));
2654 if (!peer)
2655 return;
2656 }
2657
2658 list_for_each_entry(ioc_srch, &ioc_list, list) {
2659 struct pci_dev *_pcidev = ioc_srch->pcidev;
2660 if (_pcidev == peer) {
2661 /* Paranoia checks */
2662 if (ioc->alt_ioc != NULL) {
2663 printk(MYIOC_s_WARN_FMT
2664 "Oops, already bound (%s <==> %s)!\n",
2665 ioc->name, ioc->name, ioc->alt_ioc->name);
2666 break;
2667 } else if (ioc_srch->alt_ioc != NULL) {
2668 printk(MYIOC_s_WARN_FMT
2669 "Oops, already bound (%s <==> %s)!\n",
2670 ioc_srch->name, ioc_srch->name,
2671 ioc_srch->alt_ioc->name);
2672 break;
2673 }
2674 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2675 "FOUND! binding %s <==> %s\n",
2676 ioc->name, ioc->name, ioc_srch->name));
2677 ioc_srch->alt_ioc = ioc;
2678 ioc->alt_ioc = ioc_srch;
2679 }
2680 }
2681 pci_dev_put(peer);
2682}
2683
2684/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2685/**
2686 * mpt_adapter_disable - Disable misbehaving MPT adapter.
2687 * @ioc: Pointer to MPT adapter structure
2688 */
2689static void
2690mpt_adapter_disable(MPT_ADAPTER *ioc)
2691{
2692 int sz;
2693 int ret;
2694
2695 if (ioc->cached_fw != NULL) {
2696 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2697 "%s: Pushing FW onto adapter\n", __func__, ioc->name));
2698 if ((ret = mpt_downloadboot(ioc, (MpiFwHeader_t *)
2699 ioc->cached_fw, CAN_SLEEP)) < 0) {
2700 printk(MYIOC_s_WARN_FMT
2701 ": firmware downloadboot failure (%d)!\n",
2702 ioc->name, ret);
2703 }
2704 }
2705
2706 /*
2707 * Put the controller into ready state (if its not already)
2708 */
2709 if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY) {
2710 if (!SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET,
2711 CAN_SLEEP)) {
2712 if (mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_READY)
2713 printk(MYIOC_s_ERR_FMT "%s: IOC msg unit "
2714 "reset failed to put ioc in ready state!\n",
2715 ioc->name, __func__);
2716 } else
2717 printk(MYIOC_s_ERR_FMT "%s: IOC msg unit reset "
2718 "failed!\n", ioc->name, __func__);
2719 }
2720
2721
2722 /* Disable adapter interrupts! */
2723 synchronize_irq(ioc->pcidev->irq);
2724 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
2725 ioc->active = 0;
2726
2727 /* Clear any lingering interrupt */
2728 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
2729 CHIPREG_READ32(&ioc->chip->IntStatus);
2730
2731 if (ioc->alloc != NULL) {
2732 sz = ioc->alloc_sz;
2733 dexitprintk(ioc, printk(MYIOC_s_INFO_FMT "free @ %p, sz=%d bytes\n",
2734 ioc->name, ioc->alloc, ioc->alloc_sz));
2735 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->alloc,
2736 ioc->alloc_dma);
2737 ioc->reply_frames = NULL;
2738 ioc->req_frames = NULL;
2739 ioc->alloc = NULL;
2740 ioc->alloc_total -= sz;
2741 }
2742
2743 if (ioc->sense_buf_pool != NULL) {
2744 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
2745 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->sense_buf_pool,
2746 ioc->sense_buf_pool_dma);
2747 ioc->sense_buf_pool = NULL;
2748 ioc->alloc_total -= sz;
2749 }
2750
2751 if (ioc->events != NULL){
2752 sz = MPTCTL_EVENT_LOG_SIZE * sizeof(MPT_IOCTL_EVENTS);
2753 kfree(ioc->events);
2754 ioc->events = NULL;
2755 ioc->alloc_total -= sz;
2756 }
2757
2758 mpt_free_fw_memory(ioc);
2759
2760 kfree(ioc->spi_data.nvram);
2761 mpt_inactive_raid_list_free(ioc);
2762 kfree(ioc->raid_data.pIocPg2);
2763 kfree(ioc->raid_data.pIocPg3);
2764 ioc->spi_data.nvram = NULL;
2765 ioc->raid_data.pIocPg3 = NULL;
2766
2767 if (ioc->spi_data.pIocPg4 != NULL) {
2768 sz = ioc->spi_data.IocPg4Sz;
2769 dma_free_coherent(&ioc->pcidev->dev, sz,
2770 ioc->spi_data.pIocPg4,
2771 ioc->spi_data.IocPg4_dma);
2772 ioc->spi_data.pIocPg4 = NULL;
2773 ioc->alloc_total -= sz;
2774 }
2775
2776 if (ioc->ReqToChain != NULL) {
2777 kfree(ioc->ReqToChain);
2778 kfree(ioc->RequestNB);
2779 ioc->ReqToChain = NULL;
2780 }
2781
2782 kfree(ioc->ChainToChain);
2783 ioc->ChainToChain = NULL;
2784
2785 if (ioc->HostPageBuffer != NULL) {
2786 if((ret = mpt_host_page_access_control(ioc,
2787 MPI_DB_HPBAC_FREE_BUFFER, NO_SLEEP)) != 0) {
2788 printk(MYIOC_s_ERR_FMT
2789 ": %s: host page buffers free failed (%d)!\n",
2790 ioc->name, __func__, ret);
2791 }
2792 dexitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
2793 "HostPageBuffer free @ %p, sz=%d bytes\n",
2794 ioc->name, ioc->HostPageBuffer,
2795 ioc->HostPageBuffer_sz));
2796 dma_free_coherent(&ioc->pcidev->dev, ioc->HostPageBuffer_sz,
2797 ioc->HostPageBuffer, ioc->HostPageBuffer_dma);
2798 ioc->HostPageBuffer = NULL;
2799 ioc->HostPageBuffer_sz = 0;
2800 ioc->alloc_total -= ioc->HostPageBuffer_sz;
2801 }
2802
2803 pci_set_drvdata(ioc->pcidev, NULL);
2804}
2805/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2806/**
2807 * mpt_adapter_dispose - Free all resources associated with an MPT adapter
2808 * @ioc: Pointer to MPT adapter structure
2809 *
2810 * This routine unregisters h/w resources and frees all alloc'd memory
2811 * associated with a MPT adapter structure.
2812 */
2813static void
2814mpt_adapter_dispose(MPT_ADAPTER *ioc)
2815{
2816 int sz_first, sz_last;
2817
2818 if (ioc == NULL)
2819 return;
2820
2821 sz_first = ioc->alloc_total;
2822
2823 mpt_adapter_disable(ioc);
2824
2825 if (ioc->pci_irq != -1) {
2826 free_irq(ioc->pci_irq, ioc);
2827 if (ioc->msi_enable)
2828 pci_disable_msi(ioc->pcidev);
2829 ioc->pci_irq = -1;
2830 }
2831
2832 if (ioc->memmap != NULL) {
2833 iounmap(ioc->memmap);
2834 ioc->memmap = NULL;
2835 }
2836
2837 pci_disable_device(ioc->pcidev);
2838 pci_release_selected_regions(ioc->pcidev, ioc->bars);
2839
2840 /* Zap the adapter lookup ptr! */
2841 list_del(&ioc->list);
2842
2843 sz_last = ioc->alloc_total;
2844 dprintk(ioc, printk(MYIOC_s_INFO_FMT "free'd %d of %d bytes\n",
2845 ioc->name, sz_first-sz_last+(int)sizeof(*ioc), sz_first));
2846
2847 if (ioc->alt_ioc)
2848 ioc->alt_ioc->alt_ioc = NULL;
2849
2850 kfree(ioc);
2851}
2852
2853/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2854/**
2855 * MptDisplayIocCapabilities - Disply IOC's capabilities.
2856 * @ioc: Pointer to MPT adapter structure
2857 */
2858static void
2859MptDisplayIocCapabilities(MPT_ADAPTER *ioc)
2860{
2861 int i = 0;
2862
2863 printk(KERN_INFO "%s: ", ioc->name);
2864 if (ioc->prod_name)
2865 pr_cont("%s: ", ioc->prod_name);
2866 pr_cont("Capabilities={");
2867
2868 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_INITIATOR) {
2869 pr_cont("Initiator");
2870 i++;
2871 }
2872
2873 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) {
2874 pr_cont("%sTarget", i ? "," : "");
2875 i++;
2876 }
2877
2878 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) {
2879 pr_cont("%sLAN", i ? "," : "");
2880 i++;
2881 }
2882
2883#if 0
2884 /*
2885 * This would probably evoke more questions than it's worth
2886 */
2887 if (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_TARGET) {
2888 pr_cont("%sLogBusAddr", i ? "," : "");
2889 i++;
2890 }
2891#endif
2892
2893 pr_cont("}\n");
2894}
2895
2896/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
2897/**
2898 * MakeIocReady - Get IOC to a READY state, using KickStart if needed.
2899 * @ioc: Pointer to MPT_ADAPTER structure
2900 * @force: Force hard KickStart of IOC
2901 * @sleepFlag: Specifies whether the process can sleep
2902 *
2903 * Returns:
2904 * 1 - DIAG reset and READY
2905 * 0 - READY initially OR soft reset and READY
2906 * -1 - Any failure on KickStart
2907 * -2 - Msg Unit Reset Failed
2908 * -3 - IO Unit Reset Failed
2909 * -4 - IOC owned by a PEER
2910 */
2911static int
2912MakeIocReady(MPT_ADAPTER *ioc, int force, int sleepFlag)
2913{
2914 u32 ioc_state;
2915 int statefault = 0;
2916 int cntdn;
2917 int hard_reset_done = 0;
2918 int r;
2919 int ii;
2920 int whoinit;
2921
2922 /* Get current [raw] IOC state */
2923 ioc_state = mpt_GetIocState(ioc, 0);
2924 dhsprintk(ioc, printk(MYIOC_s_INFO_FMT "MakeIocReady [raw] state=%08x\n", ioc->name, ioc_state));
2925
2926 /*
2927 * Check to see if IOC got left/stuck in doorbell handshake
2928 * grip of death. If so, hard reset the IOC.
2929 */
2930 if (ioc_state & MPI_DOORBELL_ACTIVE) {
2931 statefault = 1;
2932 printk(MYIOC_s_WARN_FMT "Unexpected doorbell active!\n",
2933 ioc->name);
2934 }
2935
2936 /* Is it already READY? */
2937 if (!statefault &&
2938 ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_READY)) {
2939 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2940 "IOC is in READY state\n", ioc->name));
2941 return 0;
2942 }
2943
2944 /*
2945 * Check to see if IOC is in FAULT state.
2946 */
2947 if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
2948 statefault = 2;
2949 printk(MYIOC_s_WARN_FMT "IOC is in FAULT state!!!\n",
2950 ioc->name);
2951 printk(MYIOC_s_WARN_FMT " FAULT code = %04xh\n",
2952 ioc->name, ioc_state & MPI_DOORBELL_DATA_MASK);
2953 }
2954
2955 /*
2956 * Hmmm... Did it get left operational?
2957 */
2958 if ((ioc_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_OPERATIONAL) {
2959 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOC operational unexpected\n",
2960 ioc->name));
2961
2962 /* Check WhoInit.
2963 * If PCI Peer, exit.
2964 * Else, if no fault conditions are present, issue a MessageUnitReset
2965 * Else, fall through to KickStart case
2966 */
2967 whoinit = (ioc_state & MPI_DOORBELL_WHO_INIT_MASK) >> MPI_DOORBELL_WHO_INIT_SHIFT;
2968 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT
2969 "whoinit 0x%x statefault %d force %d\n",
2970 ioc->name, whoinit, statefault, force));
2971 if (whoinit == MPI_WHOINIT_PCI_PEER)
2972 return -4;
2973 else {
2974 if ((statefault == 0 ) && (force == 0)) {
2975 if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) == 0)
2976 return 0;
2977 }
2978 statefault = 3;
2979 }
2980 }
2981
2982 hard_reset_done = KickStart(ioc, statefault||force, sleepFlag);
2983 if (hard_reset_done < 0)
2984 return -1;
2985
2986 /*
2987 * Loop here waiting for IOC to come READY.
2988 */
2989 ii = 0;
2990 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 5; /* 5 seconds */
2991
2992 while ((ioc_state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) {
2993 if (ioc_state == MPI_IOC_STATE_OPERATIONAL) {
2994 /*
2995 * BIOS or previous driver load left IOC in OP state.
2996 * Reset messaging FIFOs.
2997 */
2998 if ((r = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag)) != 0) {
2999 printk(MYIOC_s_ERR_FMT "IOC msg unit reset failed!\n", ioc->name);
3000 return -2;
3001 }
3002 } else if (ioc_state == MPI_IOC_STATE_RESET) {
3003 /*
3004 * Something is wrong. Try to get IOC back
3005 * to a known state.
3006 */
3007 if ((r = SendIocReset(ioc, MPI_FUNCTION_IO_UNIT_RESET, sleepFlag)) != 0) {
3008 printk(MYIOC_s_ERR_FMT "IO unit reset failed!\n", ioc->name);
3009 return -3;
3010 }
3011 }
3012
3013 ii++; cntdn--;
3014 if (!cntdn) {
3015 printk(MYIOC_s_ERR_FMT
3016 "Wait IOC_READY state (0x%x) timeout(%d)!\n",
3017 ioc->name, ioc_state, (int)((ii+5)/HZ));
3018 return -ETIME;
3019 }
3020
3021 if (sleepFlag == CAN_SLEEP) {
3022 msleep(1);
3023 } else {
3024 mdelay (1); /* 1 msec delay */
3025 }
3026
3027 }
3028
3029 if (statefault < 3) {
3030 printk(MYIOC_s_INFO_FMT "Recovered from %s\n", ioc->name,
3031 statefault == 1 ? "stuck handshake" : "IOC FAULT");
3032 }
3033
3034 return hard_reset_done;
3035}
3036
3037/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3038/**
3039 * mpt_GetIocState - Get the current state of a MPT adapter.
3040 * @ioc: Pointer to MPT_ADAPTER structure
3041 * @cooked: Request raw or cooked IOC state
3042 *
3043 * Returns all IOC Doorbell register bits if cooked==0, else just the
3044 * Doorbell bits in MPI_IOC_STATE_MASK.
3045 */
3046u32
3047mpt_GetIocState(MPT_ADAPTER *ioc, int cooked)
3048{
3049 u32 s, sc;
3050
3051 /* Get! */
3052 s = CHIPREG_READ32(&ioc->chip->Doorbell);
3053 sc = s & MPI_IOC_STATE_MASK;
3054
3055 /* Save! */
3056 ioc->last_state = sc;
3057
3058 return cooked ? sc : s;
3059}
3060
3061/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3062/**
3063 * GetIocFacts - Send IOCFacts request to MPT adapter.
3064 * @ioc: Pointer to MPT_ADAPTER structure
3065 * @sleepFlag: Specifies whether the process can sleep
3066 * @reason: If recovery, only update facts.
3067 *
3068 * Returns 0 for success, non-zero for failure.
3069 */
3070static int
3071GetIocFacts(MPT_ADAPTER *ioc, int sleepFlag, int reason)
3072{
3073 IOCFacts_t get_facts;
3074 IOCFactsReply_t *facts;
3075 int r;
3076 int req_sz;
3077 int reply_sz;
3078 int sz;
3079 u32 vv;
3080 u8 shiftFactor=1;
3081
3082 /* IOC *must* NOT be in RESET state! */
3083 if (ioc->last_state == MPI_IOC_STATE_RESET) {
3084 printk(KERN_ERR MYNAM
3085 ": ERROR - Can't get IOCFacts, %s NOT READY! (%08x)\n",
3086 ioc->name, ioc->last_state);
3087 return -44;
3088 }
3089
3090 facts = &ioc->facts;
3091
3092 /* Destination (reply area)... */
3093 reply_sz = sizeof(*facts);
3094 memset(facts, 0, reply_sz);
3095
3096 /* Request area (get_facts on the stack right now!) */
3097 req_sz = sizeof(get_facts);
3098 memset(&get_facts, 0, req_sz);
3099
3100 get_facts.Function = MPI_FUNCTION_IOC_FACTS;
3101 /* Assert: All other get_facts fields are zero! */
3102
3103 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3104 "Sending get IocFacts request req_sz=%d reply_sz=%d\n",
3105 ioc->name, req_sz, reply_sz));
3106
3107 /* No non-zero fields in the get_facts request are greater than
3108 * 1 byte in size, so we can just fire it off as is.
3109 */
3110 r = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_facts,
3111 reply_sz, (u16*)facts, 5 /*seconds*/, sleepFlag);
3112 if (r != 0)
3113 return r;
3114
3115 /*
3116 * Now byte swap (GRRR) the necessary fields before any further
3117 * inspection of reply contents.
3118 *
3119 * But need to do some sanity checks on MsgLength (byte) field
3120 * to make sure we don't zero IOC's req_sz!
3121 */
3122 /* Did we get a valid reply? */
3123 if (facts->MsgLength > offsetof(IOCFactsReply_t, RequestFrameSize)/sizeof(u32)) {
3124 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
3125 /*
3126 * If not been here, done that, save off first WhoInit value
3127 */
3128 if (ioc->FirstWhoInit == WHOINIT_UNKNOWN)
3129 ioc->FirstWhoInit = facts->WhoInit;
3130 }
3131
3132 facts->MsgVersion = le16_to_cpu(facts->MsgVersion);
3133 facts->MsgContext = le32_to_cpu(facts->MsgContext);
3134 facts->IOCExceptions = le16_to_cpu(facts->IOCExceptions);
3135 facts->IOCStatus = le16_to_cpu(facts->IOCStatus);
3136 facts->IOCLogInfo = le32_to_cpu(facts->IOCLogInfo);
3137 /* CHECKME! IOCStatus, IOCLogInfo */
3138
3139 facts->ReplyQueueDepth = le16_to_cpu(facts->ReplyQueueDepth);
3140 facts->RequestFrameSize = le16_to_cpu(facts->RequestFrameSize);
3141
3142 /*
3143 * FC f/w version changed between 1.1 and 1.2
3144 * Old: u16{Major(4),Minor(4),SubMinor(8)}
3145 * New: u32{Major(8),Minor(8),Unit(8),Dev(8)}
3146 */
3147 if (facts->MsgVersion < MPI_VERSION_01_02) {
3148 /*
3149 * Handle old FC f/w style, convert to new...
3150 */
3151 u16 oldv = le16_to_cpu(facts->Reserved_0101_FWVersion);
3152 facts->FWVersion.Word =
3153 ((oldv<<12) & 0xFF000000) |
3154 ((oldv<<8) & 0x000FFF00);
3155 } else
3156 facts->FWVersion.Word = le32_to_cpu(facts->FWVersion.Word);
3157
3158 facts->ProductID = le16_to_cpu(facts->ProductID);
3159
3160 if ((ioc->facts.ProductID & MPI_FW_HEADER_PID_PROD_MASK)
3161 > MPI_FW_HEADER_PID_PROD_TARGET_SCSI)
3162 ioc->ir_firmware = 1;
3163
3164 facts->CurrentHostMfaHighAddr =
3165 le32_to_cpu(facts->CurrentHostMfaHighAddr);
3166 facts->GlobalCredits = le16_to_cpu(facts->GlobalCredits);
3167 facts->CurrentSenseBufferHighAddr =
3168 le32_to_cpu(facts->CurrentSenseBufferHighAddr);
3169 facts->CurReplyFrameSize =
3170 le16_to_cpu(facts->CurReplyFrameSize);
3171 facts->IOCCapabilities = le32_to_cpu(facts->IOCCapabilities);
3172
3173 /*
3174 * Handle NEW (!) IOCFactsReply fields in MPI-1.01.xx
3175 * Older MPI-1.00.xx struct had 13 dwords, and enlarged
3176 * to 14 in MPI-1.01.0x.
3177 */
3178 if (facts->MsgLength >= (offsetof(IOCFactsReply_t,FWImageSize) + 7)/4 &&
3179 facts->MsgVersion > MPI_VERSION_01_00) {
3180 facts->FWImageSize = le32_to_cpu(facts->FWImageSize);
3181 }
3182
3183 facts->FWImageSize = ALIGN(facts->FWImageSize, 4);
3184
3185 if (!facts->RequestFrameSize) {
3186 /* Something is wrong! */
3187 printk(MYIOC_s_ERR_FMT "IOC reported invalid 0 request size!\n",
3188 ioc->name);
3189 return -55;
3190 }
3191
3192 r = sz = facts->BlockSize;
3193 vv = ((63 / (sz * 4)) + 1) & 0x03;
3194 ioc->NB_for_64_byte_frame = vv;
3195 while ( sz )
3196 {
3197 shiftFactor++;
3198 sz = sz >> 1;
3199 }
3200 ioc->NBShiftFactor = shiftFactor;
3201 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3202 "NB_for_64_byte_frame=%x NBShiftFactor=%x BlockSize=%x\n",
3203 ioc->name, vv, shiftFactor, r));
3204
3205 if (reason == MPT_HOSTEVENT_IOC_BRINGUP) {
3206 /*
3207 * Set values for this IOC's request & reply frame sizes,
3208 * and request & reply queue depths...
3209 */
3210 ioc->req_sz = min(MPT_DEFAULT_FRAME_SIZE, facts->RequestFrameSize * 4);
3211 ioc->req_depth = min_t(int, MPT_MAX_REQ_DEPTH, facts->GlobalCredits);
3212 ioc->reply_sz = MPT_REPLY_FRAME_SIZE;
3213 ioc->reply_depth = min_t(int, MPT_DEFAULT_REPLY_DEPTH, facts->ReplyQueueDepth);
3214
3215 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "reply_sz=%3d, reply_depth=%4d\n",
3216 ioc->name, ioc->reply_sz, ioc->reply_depth));
3217 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "req_sz =%3d, req_depth =%4d\n",
3218 ioc->name, ioc->req_sz, ioc->req_depth));
3219
3220 /* Get port facts! */
3221 if ( (r = GetPortFacts(ioc, 0, sleepFlag)) != 0 )
3222 return r;
3223 }
3224 } else {
3225 printk(MYIOC_s_ERR_FMT
3226 "Invalid IOC facts reply, msgLength=%d offsetof=%zd!\n",
3227 ioc->name, facts->MsgLength, (offsetof(IOCFactsReply_t,
3228 RequestFrameSize)/sizeof(u32)));
3229 return -66;
3230 }
3231
3232 return 0;
3233}
3234
3235/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3236/**
3237 * GetPortFacts - Send PortFacts request to MPT adapter.
3238 * @ioc: Pointer to MPT_ADAPTER structure
3239 * @portnum: Port number
3240 * @sleepFlag: Specifies whether the process can sleep
3241 *
3242 * Returns 0 for success, non-zero for failure.
3243 */
3244static int
3245GetPortFacts(MPT_ADAPTER *ioc, int portnum, int sleepFlag)
3246{
3247 PortFacts_t get_pfacts;
3248 PortFactsReply_t *pfacts;
3249 int ii;
3250 int req_sz;
3251 int reply_sz;
3252 int max_id;
3253
3254 /* IOC *must* NOT be in RESET state! */
3255 if (ioc->last_state == MPI_IOC_STATE_RESET) {
3256 printk(MYIOC_s_ERR_FMT "Can't get PortFacts NOT READY! (%08x)\n",
3257 ioc->name, ioc->last_state );
3258 return -4;
3259 }
3260
3261 pfacts = &ioc->pfacts[portnum];
3262
3263 /* Destination (reply area)... */
3264 reply_sz = sizeof(*pfacts);
3265 memset(pfacts, 0, reply_sz);
3266
3267 /* Request area (get_pfacts on the stack right now!) */
3268 req_sz = sizeof(get_pfacts);
3269 memset(&get_pfacts, 0, req_sz);
3270
3271 get_pfacts.Function = MPI_FUNCTION_PORT_FACTS;
3272 get_pfacts.PortNumber = portnum;
3273 /* Assert: All other get_pfacts fields are zero! */
3274
3275 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending get PortFacts(%d) request\n",
3276 ioc->name, portnum));
3277
3278 /* No non-zero fields in the get_pfacts request are greater than
3279 * 1 byte in size, so we can just fire it off as is.
3280 */
3281 ii = mpt_handshake_req_reply_wait(ioc, req_sz, (u32*)&get_pfacts,
3282 reply_sz, (u16*)pfacts, 5 /*seconds*/, sleepFlag);
3283 if (ii != 0)
3284 return ii;
3285
3286 /* Did we get a valid reply? */
3287
3288 /* Now byte swap the necessary fields in the response. */
3289 pfacts->MsgContext = le32_to_cpu(pfacts->MsgContext);
3290 pfacts->IOCStatus = le16_to_cpu(pfacts->IOCStatus);
3291 pfacts->IOCLogInfo = le32_to_cpu(pfacts->IOCLogInfo);
3292 pfacts->MaxDevices = le16_to_cpu(pfacts->MaxDevices);
3293 pfacts->PortSCSIID = le16_to_cpu(pfacts->PortSCSIID);
3294 pfacts->ProtocolFlags = le16_to_cpu(pfacts->ProtocolFlags);
3295 pfacts->MaxPostedCmdBuffers = le16_to_cpu(pfacts->MaxPostedCmdBuffers);
3296 pfacts->MaxPersistentIDs = le16_to_cpu(pfacts->MaxPersistentIDs);
3297 pfacts->MaxLanBuckets = le16_to_cpu(pfacts->MaxLanBuckets);
3298
3299 max_id = (ioc->bus_type == SAS) ? pfacts->PortSCSIID :
3300 pfacts->MaxDevices;
3301 ioc->devices_per_bus = (max_id > 255) ? 256 : max_id;
3302 ioc->number_of_buses = (ioc->devices_per_bus < 256) ? 1 : max_id/256;
3303
3304 /*
3305 * Place all the devices on channels
3306 *
3307 * (for debuging)
3308 */
3309 if (mpt_channel_mapping) {
3310 ioc->devices_per_bus = 1;
3311 ioc->number_of_buses = (max_id > 255) ? 255 : max_id;
3312 }
3313
3314 return 0;
3315}
3316
3317/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3318/**
3319 * SendIocInit - Send IOCInit request to MPT adapter.
3320 * @ioc: Pointer to MPT_ADAPTER structure
3321 * @sleepFlag: Specifies whether the process can sleep
3322 *
3323 * Send IOCInit followed by PortEnable to bring IOC to OPERATIONAL state.
3324 *
3325 * Returns 0 for success, non-zero for failure.
3326 */
3327static int
3328SendIocInit(MPT_ADAPTER *ioc, int sleepFlag)
3329{
3330 IOCInit_t ioc_init;
3331 MPIDefaultReply_t init_reply;
3332 u32 state;
3333 int r;
3334 int count;
3335 int cntdn;
3336
3337 memset(&ioc_init, 0, sizeof(ioc_init));
3338 memset(&init_reply, 0, sizeof(init_reply));
3339
3340 ioc_init.WhoInit = MPI_WHOINIT_HOST_DRIVER;
3341 ioc_init.Function = MPI_FUNCTION_IOC_INIT;
3342
3343 /* If we are in a recovery mode and we uploaded the FW image,
3344 * then this pointer is not NULL. Skip the upload a second time.
3345 * Set this flag if cached_fw set for either IOC.
3346 */
3347 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)
3348 ioc->upload_fw = 1;
3349 else
3350 ioc->upload_fw = 0;
3351 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "upload_fw %d facts.Flags=%x\n",
3352 ioc->name, ioc->upload_fw, ioc->facts.Flags));
3353
3354 ioc_init.MaxDevices = (U8)ioc->devices_per_bus;
3355 ioc_init.MaxBuses = (U8)ioc->number_of_buses;
3356
3357 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "facts.MsgVersion=%x\n",
3358 ioc->name, ioc->facts.MsgVersion));
3359 if (ioc->facts.MsgVersion >= MPI_VERSION_01_05) {
3360 // set MsgVersion and HeaderVersion host driver was built with
3361 ioc_init.MsgVersion = cpu_to_le16(MPI_VERSION);
3362 ioc_init.HeaderVersion = cpu_to_le16(MPI_HEADER_VERSION);
3363
3364 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT) {
3365 ioc_init.HostPageBufferSGE = ioc->facts.HostPageBufferSGE;
3366 } else if(mpt_host_page_alloc(ioc, &ioc_init))
3367 return -99;
3368 }
3369 ioc_init.ReplyFrameSize = cpu_to_le16(ioc->reply_sz); /* in BYTES */
3370
3371 if (ioc->sg_addr_size == sizeof(u64)) {
3372 /* Save the upper 32-bits of the request
3373 * (reply) and sense buffers.
3374 */
3375 ioc_init.HostMfaHighAddr = cpu_to_le32((u32)((u64)ioc->alloc_dma >> 32));
3376 ioc_init.SenseBufferHighAddr = cpu_to_le32((u32)((u64)ioc->sense_buf_pool_dma >> 32));
3377 } else {
3378 /* Force 32-bit addressing */
3379 ioc_init.HostMfaHighAddr = cpu_to_le32(0);
3380 ioc_init.SenseBufferHighAddr = cpu_to_le32(0);
3381 }
3382
3383 ioc->facts.CurrentHostMfaHighAddr = ioc_init.HostMfaHighAddr;
3384 ioc->facts.CurrentSenseBufferHighAddr = ioc_init.SenseBufferHighAddr;
3385 ioc->facts.MaxDevices = ioc_init.MaxDevices;
3386 ioc->facts.MaxBuses = ioc_init.MaxBuses;
3387
3388 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOCInit (req @ %p)\n",
3389 ioc->name, &ioc_init));
3390
3391 r = mpt_handshake_req_reply_wait(ioc, sizeof(IOCInit_t), (u32*)&ioc_init,
3392 sizeof(MPIDefaultReply_t), (u16*)&init_reply, 10 /*seconds*/, sleepFlag);
3393 if (r != 0) {
3394 printk(MYIOC_s_ERR_FMT "Sending IOCInit failed(%d)!\n",ioc->name, r);
3395 return r;
3396 }
3397
3398 /* No need to byte swap the multibyte fields in the reply
3399 * since we don't even look at its contents.
3400 */
3401
3402 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending PortEnable (req @ %p)\n",
3403 ioc->name, &ioc_init));
3404
3405 if ((r = SendPortEnable(ioc, 0, sleepFlag)) != 0) {
3406 printk(MYIOC_s_ERR_FMT "Sending PortEnable failed(%d)!\n",ioc->name, r);
3407 return r;
3408 }
3409
3410 /* YIKES! SUPER IMPORTANT!!!
3411 * Poll IocState until _OPERATIONAL while IOC is doing
3412 * LoopInit and TargetDiscovery!
3413 */
3414 count = 0;
3415 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 60; /* 60 seconds */
3416 state = mpt_GetIocState(ioc, 1);
3417 while (state != MPI_IOC_STATE_OPERATIONAL && --cntdn) {
3418 if (sleepFlag == CAN_SLEEP) {
3419 msleep(1);
3420 } else {
3421 mdelay(1);
3422 }
3423
3424 if (!cntdn) {
3425 printk(MYIOC_s_ERR_FMT "Wait IOC_OP state timeout(%d)!\n",
3426 ioc->name, (int)((count+5)/HZ));
3427 return -9;
3428 }
3429
3430 state = mpt_GetIocState(ioc, 1);
3431 count++;
3432 }
3433 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wait IOC_OPERATIONAL state (cnt=%d)\n",
3434 ioc->name, count));
3435
3436 ioc->aen_event_read_flag=0;
3437 return r;
3438}
3439
3440/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3441/**
3442 * SendPortEnable - Send PortEnable request to MPT adapter port.
3443 * @ioc: Pointer to MPT_ADAPTER structure
3444 * @portnum: Port number to enable
3445 * @sleepFlag: Specifies whether the process can sleep
3446 *
3447 * Send PortEnable to bring IOC to OPERATIONAL state.
3448 *
3449 * Returns 0 for success, non-zero for failure.
3450 */
3451static int
3452SendPortEnable(MPT_ADAPTER *ioc, int portnum, int sleepFlag)
3453{
3454 PortEnable_t port_enable;
3455 MPIDefaultReply_t reply_buf;
3456 int rc;
3457 int req_sz;
3458 int reply_sz;
3459
3460 /* Destination... */
3461 reply_sz = sizeof(MPIDefaultReply_t);
3462 memset(&reply_buf, 0, reply_sz);
3463
3464 req_sz = sizeof(PortEnable_t);
3465 memset(&port_enable, 0, req_sz);
3466
3467 port_enable.Function = MPI_FUNCTION_PORT_ENABLE;
3468 port_enable.PortNumber = portnum;
3469/* port_enable.ChainOffset = 0; */
3470/* port_enable.MsgFlags = 0; */
3471/* port_enable.MsgContext = 0; */
3472
3473 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending Port(%d)Enable (req @ %p)\n",
3474 ioc->name, portnum, &port_enable));
3475
3476 /* RAID FW may take a long time to enable
3477 */
3478 if (ioc->ir_firmware || ioc->bus_type == SAS) {
3479 rc = mpt_handshake_req_reply_wait(ioc, req_sz,
3480 (u32*)&port_enable, reply_sz, (u16*)&reply_buf,
3481 300 /*seconds*/, sleepFlag);
3482 } else {
3483 rc = mpt_handshake_req_reply_wait(ioc, req_sz,
3484 (u32*)&port_enable, reply_sz, (u16*)&reply_buf,
3485 30 /*seconds*/, sleepFlag);
3486 }
3487 return rc;
3488}
3489
3490/**
3491 * mpt_alloc_fw_memory - allocate firmware memory
3492 * @ioc: Pointer to MPT_ADAPTER structure
3493 * @size: total FW bytes
3494 *
3495 * If memory has already been allocated, the same (cached) value
3496 * is returned.
3497 *
3498 * Return 0 if successful, or non-zero for failure
3499 **/
3500int
3501mpt_alloc_fw_memory(MPT_ADAPTER *ioc, int size)
3502{
3503 int rc;
3504
3505 if (ioc->cached_fw) {
3506 rc = 0; /* use already allocated memory */
3507 goto out;
3508 }
3509 else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) {
3510 ioc->cached_fw = ioc->alt_ioc->cached_fw; /* use alt_ioc's memory */
3511 ioc->cached_fw_dma = ioc->alt_ioc->cached_fw_dma;
3512 rc = 0;
3513 goto out;
3514 }
3515 ioc->cached_fw = dma_alloc_coherent(&ioc->pcidev->dev, size,
3516 &ioc->cached_fw_dma, GFP_ATOMIC);
3517 if (!ioc->cached_fw) {
3518 printk(MYIOC_s_ERR_FMT "Unable to allocate memory for the cached firmware image!\n",
3519 ioc->name);
3520 rc = -1;
3521 } else {
3522 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Image @ %p[%p], sz=%d[%x] bytes\n",
3523 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, size, size));
3524 ioc->alloc_total += size;
3525 rc = 0;
3526 }
3527 out:
3528 return rc;
3529}
3530
3531/**
3532 * mpt_free_fw_memory - free firmware memory
3533 * @ioc: Pointer to MPT_ADAPTER structure
3534 *
3535 * If alt_img is NULL, delete from ioc structure.
3536 * Else, delete a secondary image in same format.
3537 **/
3538void
3539mpt_free_fw_memory(MPT_ADAPTER *ioc)
3540{
3541 int sz;
3542
3543 if (!ioc->cached_fw)
3544 return;
3545
3546 sz = ioc->facts.FWImageSize;
3547 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "free_fw_memory: FW Image @ %p[%p], sz=%d[%x] bytes\n",
3548 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz));
3549 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->cached_fw,
3550 ioc->cached_fw_dma);
3551 ioc->alloc_total -= sz;
3552 ioc->cached_fw = NULL;
3553}
3554
3555/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3556/**
3557 * mpt_do_upload - Construct and Send FWUpload request to MPT adapter port.
3558 * @ioc: Pointer to MPT_ADAPTER structure
3559 * @sleepFlag: Specifies whether the process can sleep
3560 *
3561 * Returns 0 for success, >0 for handshake failure
3562 * <0 for fw upload failure.
3563 *
3564 * Remark: If bound IOC and a successful FWUpload was performed
3565 * on the bound IOC, the second image is discarded
3566 * and memory is free'd. Both channels must upload to prevent
3567 * IOC from running in degraded mode.
3568 */
3569static int
3570mpt_do_upload(MPT_ADAPTER *ioc, int sleepFlag)
3571{
3572 u8 reply[sizeof(FWUploadReply_t)];
3573 FWUpload_t *prequest;
3574 FWUploadReply_t *preply;
3575 FWUploadTCSGE_t *ptcsge;
3576 u32 flagsLength;
3577 int ii, sz, reply_sz;
3578 int cmdStatus;
3579 int request_size;
3580 /* If the image size is 0, we are done.
3581 */
3582 if ((sz = ioc->facts.FWImageSize) == 0)
3583 return 0;
3584
3585 if (mpt_alloc_fw_memory(ioc, ioc->facts.FWImageSize) != 0)
3586 return -ENOMEM;
3587
3588 dinitprintk(ioc, printk(MYIOC_s_INFO_FMT ": FW Image @ %p[%p], sz=%d[%x] bytes\n",
3589 ioc->name, ioc->cached_fw, (void *)(ulong)ioc->cached_fw_dma, sz, sz));
3590
3591 prequest = (sleepFlag == NO_SLEEP) ? kzalloc(ioc->req_sz, GFP_ATOMIC) :
3592 kzalloc(ioc->req_sz, GFP_KERNEL);
3593 if (!prequest) {
3594 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed "
3595 "while allocating memory \n", ioc->name));
3596 mpt_free_fw_memory(ioc);
3597 return -ENOMEM;
3598 }
3599
3600 preply = (FWUploadReply_t *)&reply;
3601
3602 reply_sz = sizeof(reply);
3603 memset(preply, 0, reply_sz);
3604
3605 prequest->ImageType = MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM;
3606 prequest->Function = MPI_FUNCTION_FW_UPLOAD;
3607
3608 ptcsge = (FWUploadTCSGE_t *) &prequest->SGL;
3609 ptcsge->DetailsLength = 12;
3610 ptcsge->Flags = MPI_SGE_FLAGS_TRANSACTION_ELEMENT;
3611 ptcsge->ImageSize = cpu_to_le32(sz);
3612 ptcsge++;
3613
3614 flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ | sz;
3615 ioc->add_sge((char *)ptcsge, flagsLength, ioc->cached_fw_dma);
3616 request_size = offsetof(FWUpload_t, SGL) + sizeof(FWUploadTCSGE_t) +
3617 ioc->SGE_size;
3618 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending FW Upload "
3619 " (req @ %p) fw_size=%d mf_request_size=%d\n", ioc->name, prequest,
3620 ioc->facts.FWImageSize, request_size));
3621 DBG_DUMP_FW_REQUEST_FRAME(ioc, (u32 *)prequest);
3622
3623 ii = mpt_handshake_req_reply_wait(ioc, request_size, (u32 *)prequest,
3624 reply_sz, (u16 *)preply, 65 /*seconds*/, sleepFlag);
3625
3626 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "FW Upload completed "
3627 "rc=%x \n", ioc->name, ii));
3628
3629 cmdStatus = -EFAULT;
3630 if (ii == 0) {
3631 /* Handshake transfer was complete and successful.
3632 * Check the Reply Frame.
3633 */
3634 int status;
3635 status = le16_to_cpu(preply->IOCStatus) &
3636 MPI_IOCSTATUS_MASK;
3637 if (status == MPI_IOCSTATUS_SUCCESS &&
3638 ioc->facts.FWImageSize ==
3639 le32_to_cpu(preply->ActualImageSize))
3640 cmdStatus = 0;
3641 }
3642 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT ": do_upload cmdStatus=%d \n",
3643 ioc->name, cmdStatus));
3644
3645
3646 if (cmdStatus) {
3647 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "fw upload failed, "
3648 "freeing image \n", ioc->name));
3649 mpt_free_fw_memory(ioc);
3650 }
3651 kfree(prequest);
3652
3653 return cmdStatus;
3654}
3655
3656/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3657/**
3658 * mpt_downloadboot - DownloadBoot code
3659 * @ioc: Pointer to MPT_ADAPTER structure
3660 * @pFwHeader: Pointer to firmware header info
3661 * @sleepFlag: Specifies whether the process can sleep
3662 *
3663 * FwDownloadBoot requires Programmed IO access.
3664 *
3665 * Returns 0 for success
3666 * -1 FW Image size is 0
3667 * -2 No valid cached_fw Pointer
3668 * <0 for fw upload failure.
3669 */
3670static int
3671mpt_downloadboot(MPT_ADAPTER *ioc, MpiFwHeader_t *pFwHeader, int sleepFlag)
3672{
3673 MpiExtImageHeader_t *pExtImage;
3674 u32 fwSize;
3675 u32 diag0val;
3676 int count;
3677 u32 *ptrFw;
3678 u32 diagRwData;
3679 u32 nextImage;
3680 u32 load_addr;
3681 u32 ioc_state=0;
3682
3683 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot: fw size 0x%x (%d), FW Ptr %p\n",
3684 ioc->name, pFwHeader->ImageSize, pFwHeader->ImageSize, pFwHeader));
3685
3686 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
3687 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
3688 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
3689 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
3690 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
3691 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
3692
3693 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM));
3694
3695 /* wait 1 msec */
3696 if (sleepFlag == CAN_SLEEP) {
3697 msleep(1);
3698 } else {
3699 mdelay (1);
3700 }
3701
3702 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3703 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
3704
3705 for (count = 0; count < 30; count ++) {
3706 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3707 if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {
3708 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RESET_ADAPTER cleared, count=%d\n",
3709 ioc->name, count));
3710 break;
3711 }
3712 /* wait .1 sec */
3713 if (sleepFlag == CAN_SLEEP) {
3714 msleep (100);
3715 } else {
3716 mdelay (100);
3717 }
3718 }
3719
3720 if ( count == 30 ) {
3721 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot failed! "
3722 "Unable to get MPI_DIAG_DRWE mode, diag0val=%x\n",
3723 ioc->name, diag0val));
3724 return -3;
3725 }
3726
3727 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
3728 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
3729 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
3730 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
3731 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
3732 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
3733
3734 /* Set the DiagRwEn and Disable ARM bits */
3735 CHIPREG_WRITE32(&ioc->chip->Diagnostic, (MPI_DIAG_RW_ENABLE | MPI_DIAG_DISABLE_ARM));
3736
3737 fwSize = (pFwHeader->ImageSize + 3)/4;
3738 ptrFw = (u32 *) pFwHeader;
3739
3740 /* Write the LoadStartAddress to the DiagRw Address Register
3741 * using Programmed IO
3742 */
3743 if (ioc->errata_flag_1064)
3744 pci_enable_io_access(ioc->pcidev);
3745
3746 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress);
3747 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "LoadStart addr written 0x%x \n",
3748 ioc->name, pFwHeader->LoadStartAddress));
3749
3750 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write FW Image: 0x%x bytes @ %p\n",
3751 ioc->name, fwSize*4, ptrFw));
3752 while (fwSize--) {
3753 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
3754 }
3755
3756 nextImage = pFwHeader->NextImageHeaderOffset;
3757 while (nextImage) {
3758 pExtImage = (MpiExtImageHeader_t *) ((char *)pFwHeader + nextImage);
3759
3760 load_addr = pExtImage->LoadStartAddress;
3761
3762 fwSize = (pExtImage->ImageSize + 3) >> 2;
3763 ptrFw = (u32 *)pExtImage;
3764
3765 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write Ext Image: 0x%x (%d) bytes @ %p load_addr=%x\n",
3766 ioc->name, fwSize*4, fwSize*4, ptrFw, load_addr));
3767 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, load_addr);
3768
3769 while (fwSize--) {
3770 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, *ptrFw++);
3771 }
3772 nextImage = pExtImage->NextImageHeaderOffset;
3773 }
3774
3775 /* Write the IopResetVectorRegAddr */
3776 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Addr=%x! \n", ioc->name, pFwHeader->IopResetRegAddr));
3777 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->IopResetRegAddr);
3778
3779 /* Write the IopResetVectorValue */
3780 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Write IopResetVector Value=%x! \n", ioc->name, pFwHeader->IopResetVectorValue));
3781 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, pFwHeader->IopResetVectorValue);
3782
3783 /* Clear the internal flash bad bit - autoincrementing register,
3784 * so must do two writes.
3785 */
3786 if (ioc->bus_type == SPI) {
3787 /*
3788 * 1030 and 1035 H/W errata, workaround to access
3789 * the ClearFlashBadSignatureBit
3790 */
3791 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
3792 diagRwData = CHIPREG_PIO_READ32(&ioc->pio_chip->DiagRwData);
3793 diagRwData |= 0x40000000;
3794 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
3795 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData);
3796
3797 } else /* if((ioc->bus_type == SAS) || (ioc->bus_type == FC)) */ {
3798 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3799 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val |
3800 MPI_DIAG_CLEAR_FLASH_BAD_SIG);
3801
3802 /* wait 1 msec */
3803 if (sleepFlag == CAN_SLEEP) {
3804 msleep (1);
3805 } else {
3806 mdelay (1);
3807 }
3808 }
3809
3810 if (ioc->errata_flag_1064)
3811 pci_disable_io_access(ioc->pcidev);
3812
3813 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
3814 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot diag0val=%x, "
3815 "turning off PREVENT_IOC_BOOT, DISABLE_ARM, RW_ENABLE\n",
3816 ioc->name, diag0val));
3817 diag0val &= ~(MPI_DIAG_PREVENT_IOC_BOOT | MPI_DIAG_DISABLE_ARM | MPI_DIAG_RW_ENABLE);
3818 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "downloadboot now diag0val=%x\n",
3819 ioc->name, diag0val));
3820 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
3821
3822 /* Write 0xFF to reset the sequencer */
3823 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
3824
3825 if (ioc->bus_type == SAS) {
3826 ioc_state = mpt_GetIocState(ioc, 0);
3827 if ( (GetIocFacts(ioc, sleepFlag,
3828 MPT_HOSTEVENT_IOC_BRINGUP)) != 0 ) {
3829 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT "GetIocFacts failed: IocState=%x\n",
3830 ioc->name, ioc_state));
3831 return -EFAULT;
3832 }
3833 }
3834
3835 for (count=0; count<HZ*20; count++) {
3836 if ((ioc_state = mpt_GetIocState(ioc, 0)) & MPI_IOC_STATE_READY) {
3837 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3838 "downloadboot successful! (count=%d) IocState=%x\n",
3839 ioc->name, count, ioc_state));
3840 if (ioc->bus_type == SAS) {
3841 return 0;
3842 }
3843 if ((SendIocInit(ioc, sleepFlag)) != 0) {
3844 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3845 "downloadboot: SendIocInit failed\n",
3846 ioc->name));
3847 return -EFAULT;
3848 }
3849 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3850 "downloadboot: SendIocInit successful\n",
3851 ioc->name));
3852 return 0;
3853 }
3854 if (sleepFlag == CAN_SLEEP) {
3855 msleep (10);
3856 } else {
3857 mdelay (10);
3858 }
3859 }
3860 ddlprintk(ioc, printk(MYIOC_s_DEBUG_FMT
3861 "downloadboot failed! IocState=%x\n",ioc->name, ioc_state));
3862 return -EFAULT;
3863}
3864
3865/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3866/**
3867 * KickStart - Perform hard reset of MPT adapter.
3868 * @ioc: Pointer to MPT_ADAPTER structure
3869 * @force: Force hard reset
3870 * @sleepFlag: Specifies whether the process can sleep
3871 *
3872 * This routine places MPT adapter in diagnostic mode via the
3873 * WriteSequence register, and then performs a hard reset of adapter
3874 * via the Diagnostic register.
3875 *
3876 * Inputs: sleepflag - CAN_SLEEP (non-interrupt thread)
3877 * or NO_SLEEP (interrupt thread, use mdelay)
3878 * force - 1 if doorbell active, board fault state
3879 * board operational, IOC_RECOVERY or
3880 * IOC_BRINGUP and there is an alt_ioc.
3881 * 0 else
3882 *
3883 * Returns:
3884 * 1 - hard reset, READY
3885 * 0 - no reset due to History bit, READY
3886 * -1 - no reset due to History bit but not READY
3887 * OR reset but failed to come READY
3888 * -2 - no reset, could not enter DIAG mode
3889 * -3 - reset but bad FW bit
3890 */
3891static int
3892KickStart(MPT_ADAPTER *ioc, int force, int sleepFlag)
3893{
3894 int hard_reset_done = 0;
3895 u32 ioc_state=0;
3896 int cnt,cntdn;
3897
3898 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStarting!\n", ioc->name));
3899 if (ioc->bus_type == SPI) {
3900 /* Always issue a Msg Unit Reset first. This will clear some
3901 * SCSI bus hang conditions.
3902 */
3903 SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag);
3904
3905 if (sleepFlag == CAN_SLEEP) {
3906 msleep (1000);
3907 } else {
3908 mdelay (1000);
3909 }
3910 }
3911
3912 hard_reset_done = mpt_diag_reset(ioc, force, sleepFlag);
3913 if (hard_reset_done < 0)
3914 return hard_reset_done;
3915
3916 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset successful!\n",
3917 ioc->name));
3918
3919 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 2; /* 2 seconds */
3920 for (cnt=0; cnt<cntdn; cnt++) {
3921 ioc_state = mpt_GetIocState(ioc, 1);
3922 if ((ioc_state == MPI_IOC_STATE_READY) || (ioc_state == MPI_IOC_STATE_OPERATIONAL)) {
3923 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "KickStart successful! (cnt=%d)\n",
3924 ioc->name, cnt));
3925 return hard_reset_done;
3926 }
3927 if (sleepFlag == CAN_SLEEP) {
3928 msleep (10);
3929 } else {
3930 mdelay (10);
3931 }
3932 }
3933
3934 dinitprintk(ioc, printk(MYIOC_s_ERR_FMT "Failed to come READY after reset! IocState=%x\n",
3935 ioc->name, mpt_GetIocState(ioc, 0)));
3936 return -1;
3937}
3938
3939/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
3940/**
3941 * mpt_diag_reset - Perform hard reset of the adapter.
3942 * @ioc: Pointer to MPT_ADAPTER structure
3943 * @ignore: Set if to honor and clear to ignore
3944 * the reset history bit
3945 * @sleepFlag: CAN_SLEEP if called in a non-interrupt thread,
3946 * else set to NO_SLEEP (use mdelay instead)
3947 *
3948 * This routine places the adapter in diagnostic mode via the
3949 * WriteSequence register and then performs a hard reset of adapter
3950 * via the Diagnostic register. Adapter should be in ready state
3951 * upon successful completion.
3952 *
3953 * Returns: 1 hard reset successful
3954 * 0 no reset performed because reset history bit set
3955 * -2 enabling diagnostic mode failed
3956 * -3 diagnostic reset failed
3957 */
3958static int
3959mpt_diag_reset(MPT_ADAPTER *ioc, int ignore, int sleepFlag)
3960{
3961 u32 diag0val;
3962 u32 doorbell;
3963 int hard_reset_done = 0;
3964 int count = 0;
3965 u32 diag1val = 0;
3966 MpiFwHeader_t *cached_fw; /* Pointer to FW */
3967 u8 cb_idx;
3968
3969 /* Clear any existing interrupts */
3970 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
3971
3972 if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078) {
3973
3974 if (!ignore)
3975 return 0;
3976
3977 drsprintk(ioc, printk(MYIOC_s_WARN_FMT "%s: Doorbell=%p; 1078 reset "
3978 "address=%p\n", ioc->name, __func__,
3979 &ioc->chip->Doorbell, &ioc->chip->Reset_1078));
3980 CHIPREG_WRITE32(&ioc->chip->Reset_1078, 0x07);
3981 if (sleepFlag == CAN_SLEEP)
3982 msleep(1);
3983 else
3984 mdelay(1);
3985
3986 /*
3987 * Call each currently registered protocol IOC reset handler
3988 * with pre-reset indication.
3989 * NOTE: If we're doing _IOC_BRINGUP, there can be no
3990 * MptResetHandlers[] registered yet.
3991 */
3992 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
3993 if (MptResetHandlers[cb_idx])
3994 (*(MptResetHandlers[cb_idx]))(ioc,
3995 MPT_IOC_PRE_RESET);
3996 }
3997
3998 for (count = 0; count < 60; count ++) {
3999 doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
4000 doorbell &= MPI_IOC_STATE_MASK;
4001
4002 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4003 "looking for READY STATE: doorbell=%x"
4004 " count=%d\n",
4005 ioc->name, doorbell, count));
4006
4007 if (doorbell == MPI_IOC_STATE_READY) {
4008 return 1;
4009 }
4010
4011 /* wait 1 sec */
4012 if (sleepFlag == CAN_SLEEP)
4013 msleep(1000);
4014 else
4015 mdelay(1000);
4016 }
4017 return -1;
4018 }
4019
4020 /* Use "Diagnostic reset" method! (only thing available!) */
4021 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4022
4023 if (ioc->debug_level & MPT_DEBUG) {
4024 if (ioc->alt_ioc)
4025 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4026 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG1: diag0=%08x, diag1=%08x\n",
4027 ioc->name, diag0val, diag1val));
4028 }
4029
4030 /* Do the reset if we are told to ignore the reset history
4031 * or if the reset history is 0
4032 */
4033 if (ignore || !(diag0val & MPI_DIAG_RESET_HISTORY)) {
4034 while ((diag0val & MPI_DIAG_DRWE) == 0) {
4035 /* Write magic sequence to WriteSequence register
4036 * Loop until in diagnostic mode
4037 */
4038 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
4039 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
4040 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
4041 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
4042 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
4043 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
4044
4045 /* wait 100 msec */
4046 if (sleepFlag == CAN_SLEEP) {
4047 msleep (100);
4048 } else {
4049 mdelay (100);
4050 }
4051
4052 count++;
4053 if (count > 20) {
4054 printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n",
4055 ioc->name, diag0val);
4056 return -2;
4057
4058 }
4059
4060 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4061
4062 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Wrote magic DiagWriteEn sequence (%x)\n",
4063 ioc->name, diag0val));
4064 }
4065
4066 if (ioc->debug_level & MPT_DEBUG) {
4067 if (ioc->alt_ioc)
4068 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4069 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG2: diag0=%08x, diag1=%08x\n",
4070 ioc->name, diag0val, diag1val));
4071 }
4072 /*
4073 * Disable the ARM (Bug fix)
4074 *
4075 */
4076 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_DISABLE_ARM);
4077 mdelay(1);
4078
4079 /*
4080 * Now hit the reset bit in the Diagnostic register
4081 * (THE BIG HAMMER!) (Clears DRWE bit).
4082 */
4083 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val | MPI_DIAG_RESET_ADAPTER);
4084 hard_reset_done = 1;
4085 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Diagnostic reset performed\n",
4086 ioc->name));
4087
4088 /*
4089 * Call each currently registered protocol IOC reset handler
4090 * with pre-reset indication.
4091 * NOTE: If we're doing _IOC_BRINGUP, there can be no
4092 * MptResetHandlers[] registered yet.
4093 */
4094 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
4095 if (MptResetHandlers[cb_idx]) {
4096 mpt_signal_reset(cb_idx,
4097 ioc, MPT_IOC_PRE_RESET);
4098 if (ioc->alt_ioc) {
4099 mpt_signal_reset(cb_idx,
4100 ioc->alt_ioc, MPT_IOC_PRE_RESET);
4101 }
4102 }
4103 }
4104
4105 if (ioc->cached_fw)
4106 cached_fw = (MpiFwHeader_t *)ioc->cached_fw;
4107 else if (ioc->alt_ioc && ioc->alt_ioc->cached_fw)
4108 cached_fw = (MpiFwHeader_t *)ioc->alt_ioc->cached_fw;
4109 else
4110 cached_fw = NULL;
4111 if (cached_fw) {
4112 /* If the DownloadBoot operation fails, the
4113 * IOC will be left unusable. This is a fatal error
4114 * case. _diag_reset will return < 0
4115 */
4116 for (count = 0; count < 30; count ++) {
4117 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4118 if (!(diag0val & MPI_DIAG_RESET_ADAPTER)) {
4119 break;
4120 }
4121
4122 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "cached_fw: diag0val=%x count=%d\n",
4123 ioc->name, diag0val, count));
4124 /* wait 1 sec */
4125 if (sleepFlag == CAN_SLEEP) {
4126 msleep (1000);
4127 } else {
4128 mdelay (1000);
4129 }
4130 }
4131 if ((count = mpt_downloadboot(ioc, cached_fw, sleepFlag)) < 0) {
4132 printk(MYIOC_s_WARN_FMT
4133 "firmware downloadboot failure (%d)!\n", ioc->name, count);
4134 }
4135
4136 } else {
4137 /* Wait for FW to reload and for board
4138 * to go to the READY state.
4139 * Maximum wait is 60 seconds.
4140 * If fail, no error will check again
4141 * with calling program.
4142 */
4143 for (count = 0; count < 60; count ++) {
4144 doorbell = CHIPREG_READ32(&ioc->chip->Doorbell);
4145 doorbell &= MPI_IOC_STATE_MASK;
4146
4147 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4148 "looking for READY STATE: doorbell=%x"
4149 " count=%d\n", ioc->name, doorbell, count));
4150
4151 if (doorbell == MPI_IOC_STATE_READY) {
4152 break;
4153 }
4154
4155 /* wait 1 sec */
4156 if (sleepFlag == CAN_SLEEP) {
4157 msleep (1000);
4158 } else {
4159 mdelay (1000);
4160 }
4161 }
4162
4163 if (doorbell != MPI_IOC_STATE_READY)
4164 printk(MYIOC_s_ERR_FMT "Failed to come READY "
4165 "after reset! IocState=%x", ioc->name,
4166 doorbell);
4167 }
4168 }
4169
4170 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4171 if (ioc->debug_level & MPT_DEBUG) {
4172 if (ioc->alt_ioc)
4173 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4174 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG3: diag0=%08x, diag1=%08x\n",
4175 ioc->name, diag0val, diag1val));
4176 }
4177
4178 /* Clear RESET_HISTORY bit! Place board in the
4179 * diagnostic mode to update the diag register.
4180 */
4181 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4182 count = 0;
4183 while ((diag0val & MPI_DIAG_DRWE) == 0) {
4184 /* Write magic sequence to WriteSequence register
4185 * Loop until in diagnostic mode
4186 */
4187 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
4188 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
4189 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
4190 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_3RD_KEY_VALUE);
4191 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_4TH_KEY_VALUE);
4192 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_5TH_KEY_VALUE);
4193
4194 /* wait 100 msec */
4195 if (sleepFlag == CAN_SLEEP) {
4196 msleep (100);
4197 } else {
4198 mdelay (100);
4199 }
4200
4201 count++;
4202 if (count > 20) {
4203 printk(MYIOC_s_ERR_FMT "Enable Diagnostic mode FAILED! (%02xh)\n",
4204 ioc->name, diag0val);
4205 break;
4206 }
4207 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4208 }
4209 diag0val &= ~MPI_DIAG_RESET_HISTORY;
4210 CHIPREG_WRITE32(&ioc->chip->Diagnostic, diag0val);
4211 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4212 if (diag0val & MPI_DIAG_RESET_HISTORY) {
4213 printk(MYIOC_s_WARN_FMT "ResetHistory bit failed to clear!\n",
4214 ioc->name);
4215 }
4216
4217 /* Disable Diagnostic Mode
4218 */
4219 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFFFFFFFF);
4220
4221 /* Check FW reload status flags.
4222 */
4223 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
4224 if (diag0val & (MPI_DIAG_FLASH_BAD_SIG | MPI_DIAG_RESET_ADAPTER | MPI_DIAG_DISABLE_ARM)) {
4225 printk(MYIOC_s_ERR_FMT "Diagnostic reset FAILED! (%02xh)\n",
4226 ioc->name, diag0val);
4227 return -3;
4228 }
4229
4230 if (ioc->debug_level & MPT_DEBUG) {
4231 if (ioc->alt_ioc)
4232 diag1val = CHIPREG_READ32(&ioc->alt_ioc->chip->Diagnostic);
4233 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "DbG4: diag0=%08x, diag1=%08x\n",
4234 ioc->name, diag0val, diag1val));
4235 }
4236
4237 /*
4238 * Reset flag that says we've enabled event notification
4239 */
4240 ioc->facts.EventState = 0;
4241
4242 if (ioc->alt_ioc)
4243 ioc->alt_ioc->facts.EventState = 0;
4244
4245 return hard_reset_done;
4246}
4247
4248/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4249/**
4250 * SendIocReset - Send IOCReset request to MPT adapter.
4251 * @ioc: Pointer to MPT_ADAPTER structure
4252 * @reset_type: reset type, expected values are
4253 * %MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET or %MPI_FUNCTION_IO_UNIT_RESET
4254 * @sleepFlag: Specifies whether the process can sleep
4255 *
4256 * Send IOCReset request to the MPT adapter.
4257 *
4258 * Returns 0 for success, non-zero for failure.
4259 */
4260static int
4261SendIocReset(MPT_ADAPTER *ioc, u8 reset_type, int sleepFlag)
4262{
4263 int r;
4264 u32 state;
4265 int cntdn, count;
4266
4267 drsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending IOC reset(0x%02x)!\n",
4268 ioc->name, reset_type));
4269 CHIPREG_WRITE32(&ioc->chip->Doorbell, reset_type<<MPI_DOORBELL_FUNCTION_SHIFT);
4270 if ((r = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
4271 return r;
4272
4273 /* FW ACK'd request, wait for READY state
4274 */
4275 count = 0;
4276 cntdn = ((sleepFlag == CAN_SLEEP) ? HZ : 1000) * 15; /* 15 seconds */
4277
4278 while ((state = mpt_GetIocState(ioc, 1)) != MPI_IOC_STATE_READY) {
4279 cntdn--;
4280 count++;
4281 if (!cntdn) {
4282 if (sleepFlag != CAN_SLEEP)
4283 count *= 10;
4284
4285 printk(MYIOC_s_ERR_FMT
4286 "Wait IOC_READY state (0x%x) timeout(%d)!\n",
4287 ioc->name, state, (int)((count+5)/HZ));
4288 return -ETIME;
4289 }
4290
4291 if (sleepFlag == CAN_SLEEP) {
4292 msleep(1);
4293 } else {
4294 mdelay (1); /* 1 msec delay */
4295 }
4296 }
4297
4298 /* TODO!
4299 * Cleanup all event stuff for this IOC; re-issue EventNotification
4300 * request if needed.
4301 */
4302 if (ioc->facts.Function)
4303 ioc->facts.EventState = 0;
4304
4305 return 0;
4306}
4307
4308/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4309/**
4310 * initChainBuffers - Allocate memory for and initialize chain buffers
4311 * @ioc: Pointer to MPT_ADAPTER structure
4312 *
4313 * Allocates memory for and initializes chain buffers,
4314 * chain buffer control arrays and spinlock.
4315 */
4316static int
4317initChainBuffers(MPT_ADAPTER *ioc)
4318{
4319 u8 *mem;
4320 int sz, ii, num_chain;
4321 int scale, num_sge, numSGE;
4322
4323 /* ReqToChain size must equal the req_depth
4324 * index = req_idx
4325 */
4326 if (ioc->ReqToChain == NULL) {
4327 sz = ioc->req_depth * sizeof(int);
4328 mem = kmalloc(sz, GFP_ATOMIC);
4329 if (mem == NULL)
4330 return -1;
4331
4332 ioc->ReqToChain = (int *) mem;
4333 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReqToChain alloc @ %p, sz=%d bytes\n",
4334 ioc->name, mem, sz));
4335 mem = kmalloc(sz, GFP_ATOMIC);
4336 if (mem == NULL)
4337 return -1;
4338
4339 ioc->RequestNB = (int *) mem;
4340 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestNB alloc @ %p, sz=%d bytes\n",
4341 ioc->name, mem, sz));
4342 }
4343 for (ii = 0; ii < ioc->req_depth; ii++) {
4344 ioc->ReqToChain[ii] = MPT_HOST_NO_CHAIN;
4345 }
4346
4347 /* ChainToChain size must equal the total number
4348 * of chain buffers to be allocated.
4349 * index = chain_idx
4350 *
4351 * Calculate the number of chain buffers needed(plus 1) per I/O
4352 * then multiply the maximum number of simultaneous cmds
4353 *
4354 * num_sge = num sge in request frame + last chain buffer
4355 * scale = num sge per chain buffer if no chain element
4356 */
4357 scale = ioc->req_sz / ioc->SGE_size;
4358 if (ioc->sg_addr_size == sizeof(u64))
4359 num_sge = scale + (ioc->req_sz - 60) / ioc->SGE_size;
4360 else
4361 num_sge = 1 + scale + (ioc->req_sz - 64) / ioc->SGE_size;
4362
4363 if (ioc->sg_addr_size == sizeof(u64)) {
4364 numSGE = (scale - 1) * (ioc->facts.MaxChainDepth-1) + scale +
4365 (ioc->req_sz - 60) / ioc->SGE_size;
4366 } else {
4367 numSGE = 1 + (scale - 1) * (ioc->facts.MaxChainDepth-1) +
4368 scale + (ioc->req_sz - 64) / ioc->SGE_size;
4369 }
4370 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "num_sge=%d numSGE=%d\n",
4371 ioc->name, num_sge, numSGE));
4372
4373 if (ioc->bus_type == FC) {
4374 if (numSGE > MPT_SCSI_FC_SG_DEPTH)
4375 numSGE = MPT_SCSI_FC_SG_DEPTH;
4376 } else {
4377 if (numSGE > MPT_SCSI_SG_DEPTH)
4378 numSGE = MPT_SCSI_SG_DEPTH;
4379 }
4380
4381 num_chain = 1;
4382 while (numSGE - num_sge > 0) {
4383 num_chain++;
4384 num_sge += (scale - 1);
4385 }
4386 num_chain++;
4387
4388 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Now numSGE=%d num_sge=%d num_chain=%d\n",
4389 ioc->name, numSGE, num_sge, num_chain));
4390
4391 if (ioc->bus_type == SPI)
4392 num_chain *= MPT_SCSI_CAN_QUEUE;
4393 else if (ioc->bus_type == SAS)
4394 num_chain *= MPT_SAS_CAN_QUEUE;
4395 else
4396 num_chain *= MPT_FC_CAN_QUEUE;
4397
4398 ioc->num_chain = num_chain;
4399
4400 sz = num_chain * sizeof(int);
4401 if (ioc->ChainToChain == NULL) {
4402 mem = kmalloc(sz, GFP_ATOMIC);
4403 if (mem == NULL)
4404 return -1;
4405
4406 ioc->ChainToChain = (int *) mem;
4407 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainToChain alloc @ %p, sz=%d bytes\n",
4408 ioc->name, mem, sz));
4409 } else {
4410 mem = (u8 *) ioc->ChainToChain;
4411 }
4412 memset(mem, 0xFF, sz);
4413 return num_chain;
4414}
4415
4416/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4417/**
4418 * PrimeIocFifos - Initialize IOC request and reply FIFOs.
4419 * @ioc: Pointer to MPT_ADAPTER structure
4420 *
4421 * This routine allocates memory for the MPT reply and request frame
4422 * pools (if necessary), and primes the IOC reply FIFO with
4423 * reply frames.
4424 *
4425 * Returns 0 for success, non-zero for failure.
4426 */
4427static int
4428PrimeIocFifos(MPT_ADAPTER *ioc)
4429{
4430 MPT_FRAME_HDR *mf;
4431 unsigned long flags;
4432 dma_addr_t alloc_dma;
4433 u8 *mem;
4434 int i, reply_sz, sz, total_size, num_chain;
4435 u64 dma_mask;
4436
4437 dma_mask = 0;
4438
4439 /* Prime reply FIFO... */
4440
4441 if (ioc->reply_frames == NULL) {
4442 if ( (num_chain = initChainBuffers(ioc)) < 0)
4443 return -1;
4444 /*
4445 * 1078 errata workaround for the 36GB limitation
4446 */
4447 if (ioc->pcidev->device == MPI_MANUFACTPAGE_DEVID_SAS1078 &&
4448 ioc->dma_mask > DMA_BIT_MASK(35)) {
4449 if (!dma_set_mask(&ioc->pcidev->dev, DMA_BIT_MASK(32))
4450 && !dma_set_coherent_mask(&ioc->pcidev->dev, DMA_BIT_MASK(32))) {
4451 dma_mask = DMA_BIT_MASK(35);
4452 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4453 "setting 35 bit addressing for "
4454 "Request/Reply/Chain and Sense Buffers\n",
4455 ioc->name));
4456 } else {
4457 /*Reseting DMA mask to 64 bit*/
4458 dma_set_mask(&ioc->pcidev->dev,
4459 DMA_BIT_MASK(64));
4460 dma_set_coherent_mask(&ioc->pcidev->dev,
4461 DMA_BIT_MASK(64));
4462
4463 printk(MYIOC_s_ERR_FMT
4464 "failed setting 35 bit addressing for "
4465 "Request/Reply/Chain and Sense Buffers\n",
4466 ioc->name);
4467 return -1;
4468 }
4469 }
4470
4471 total_size = reply_sz = (ioc->reply_sz * ioc->reply_depth);
4472 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d bytes, ReplyDepth=%d\n",
4473 ioc->name, ioc->reply_sz, ioc->reply_depth));
4474 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffer sz=%d[%x] bytes\n",
4475 ioc->name, reply_sz, reply_sz));
4476
4477 sz = (ioc->req_sz * ioc->req_depth);
4478 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d bytes, RequestDepth=%d\n",
4479 ioc->name, ioc->req_sz, ioc->req_depth));
4480 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffer sz=%d[%x] bytes\n",
4481 ioc->name, sz, sz));
4482 total_size += sz;
4483
4484 sz = num_chain * ioc->req_sz; /* chain buffer pool size */
4485 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d bytes, ChainDepth=%d\n",
4486 ioc->name, ioc->req_sz, num_chain));
4487 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffer sz=%d[%x] bytes num_chain=%d\n",
4488 ioc->name, sz, sz, num_chain));
4489
4490 total_size += sz;
4491 mem = dma_alloc_coherent(&ioc->pcidev->dev, total_size,
4492 &alloc_dma, GFP_KERNEL);
4493 if (mem == NULL) {
4494 printk(MYIOC_s_ERR_FMT "Unable to allocate Reply, Request, Chain Buffers!\n",
4495 ioc->name);
4496 goto out_fail;
4497 }
4498
4499 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Total alloc @ %p[%p], sz=%d[%x] bytes\n",
4500 ioc->name, mem, (void *)(ulong)alloc_dma, total_size, total_size));
4501
4502 memset(mem, 0, total_size);
4503 ioc->alloc_total += total_size;
4504 ioc->alloc = mem;
4505 ioc->alloc_dma = alloc_dma;
4506 ioc->alloc_sz = total_size;
4507 ioc->reply_frames = (MPT_FRAME_HDR *) mem;
4508 ioc->reply_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF);
4509
4510 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n",
4511 ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma));
4512
4513 alloc_dma += reply_sz;
4514 mem += reply_sz;
4515
4516 /* Request FIFO - WE manage this! */
4517
4518 ioc->req_frames = (MPT_FRAME_HDR *) mem;
4519 ioc->req_frames_dma = alloc_dma;
4520
4521 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "RequestBuffers @ %p[%p]\n",
4522 ioc->name, mem, (void *)(ulong)alloc_dma));
4523
4524 ioc->req_frames_low_dma = (u32) (alloc_dma & 0xFFFFFFFF);
4525
4526 for (i = 0; i < ioc->req_depth; i++) {
4527 alloc_dma += ioc->req_sz;
4528 mem += ioc->req_sz;
4529 }
4530
4531 ioc->ChainBuffer = mem;
4532 ioc->ChainBufferDMA = alloc_dma;
4533
4534 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ChainBuffers @ %p(%p)\n",
4535 ioc->name, ioc->ChainBuffer, (void *)(ulong)ioc->ChainBufferDMA));
4536
4537 /* Initialize the free chain Q.
4538 */
4539
4540 INIT_LIST_HEAD(&ioc->FreeChainQ);
4541
4542 /* Post the chain buffers to the FreeChainQ.
4543 */
4544 mem = (u8 *)ioc->ChainBuffer;
4545 for (i=0; i < num_chain; i++) {
4546 mf = (MPT_FRAME_HDR *) mem;
4547 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeChainQ);
4548 mem += ioc->req_sz;
4549 }
4550
4551 /* Initialize Request frames linked list
4552 */
4553 alloc_dma = ioc->req_frames_dma;
4554 mem = (u8 *) ioc->req_frames;
4555
4556 spin_lock_irqsave(&ioc->FreeQlock, flags);
4557 INIT_LIST_HEAD(&ioc->FreeQ);
4558 for (i = 0; i < ioc->req_depth; i++) {
4559 mf = (MPT_FRAME_HDR *) mem;
4560
4561 /* Queue REQUESTs *internally*! */
4562 list_add_tail(&mf->u.frame.linkage.list, &ioc->FreeQ);
4563
4564 mem += ioc->req_sz;
4565 }
4566 spin_unlock_irqrestore(&ioc->FreeQlock, flags);
4567
4568 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
4569 ioc->sense_buf_pool = dma_alloc_coherent(&ioc->pcidev->dev, sz,
4570 &ioc->sense_buf_pool_dma, GFP_KERNEL);
4571 if (ioc->sense_buf_pool == NULL) {
4572 printk(MYIOC_s_ERR_FMT "Unable to allocate Sense Buffers!\n",
4573 ioc->name);
4574 goto out_fail;
4575 }
4576
4577 ioc->sense_buf_low_dma = (u32) (ioc->sense_buf_pool_dma & 0xFFFFFFFF);
4578 ioc->alloc_total += sz;
4579 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SenseBuffers @ %p[%p]\n",
4580 ioc->name, ioc->sense_buf_pool, (void *)(ulong)ioc->sense_buf_pool_dma));
4581
4582 }
4583
4584 /* Post Reply frames to FIFO
4585 */
4586 alloc_dma = ioc->alloc_dma;
4587 dinitprintk(ioc, printk(MYIOC_s_DEBUG_FMT "ReplyBuffers @ %p[%p]\n",
4588 ioc->name, ioc->reply_frames, (void *)(ulong)alloc_dma));
4589
4590 for (i = 0; i < ioc->reply_depth; i++) {
4591 /* Write each address to the IOC! */
4592 CHIPREG_WRITE32(&ioc->chip->ReplyFifo, alloc_dma);
4593 alloc_dma += ioc->reply_sz;
4594 }
4595
4596 if (dma_mask == DMA_BIT_MASK(35) && !dma_set_mask(&ioc->pcidev->dev,
4597 ioc->dma_mask) && !dma_set_coherent_mask(&ioc->pcidev->dev,
4598 ioc->dma_mask))
4599 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4600 "restoring 64 bit addressing\n", ioc->name));
4601
4602 return 0;
4603
4604out_fail:
4605
4606 if (ioc->alloc != NULL) {
4607 sz = ioc->alloc_sz;
4608 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->alloc,
4609 ioc->alloc_dma);
4610 ioc->reply_frames = NULL;
4611 ioc->req_frames = NULL;
4612 ioc->alloc_total -= sz;
4613 }
4614 if (ioc->sense_buf_pool != NULL) {
4615 sz = (ioc->req_depth * MPT_SENSE_BUFFER_ALLOC);
4616 dma_free_coherent(&ioc->pcidev->dev, sz, ioc->sense_buf_pool,
4617 ioc->sense_buf_pool_dma);
4618 ioc->sense_buf_pool = NULL;
4619 }
4620
4621 if (dma_mask == DMA_BIT_MASK(35) && !dma_set_mask(&ioc->pcidev->dev,
4622 DMA_BIT_MASK(64)) && !dma_set_coherent_mask(&ioc->pcidev->dev,
4623 DMA_BIT_MASK(64)))
4624 d36memprintk(ioc, printk(MYIOC_s_DEBUG_FMT
4625 "restoring 64 bit addressing\n", ioc->name));
4626
4627 return -1;
4628}
4629
4630/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4631/**
4632 * mpt_handshake_req_reply_wait - Send MPT request to and receive reply
4633 * from IOC via doorbell handshake method.
4634 * @ioc: Pointer to MPT_ADAPTER structure
4635 * @reqBytes: Size of the request in bytes
4636 * @req: Pointer to MPT request frame
4637 * @replyBytes: Expected size of the reply in bytes
4638 * @u16reply: Pointer to area where reply should be written
4639 * @maxwait: Max wait time for a reply (in seconds)
4640 * @sleepFlag: Specifies whether the process can sleep
4641 *
4642 * NOTES: It is the callers responsibility to byte-swap fields in the
4643 * request which are greater than 1 byte in size. It is also the
4644 * callers responsibility to byte-swap response fields which are
4645 * greater than 1 byte in size.
4646 *
4647 * Returns 0 for success, non-zero for failure.
4648 */
4649static int
4650mpt_handshake_req_reply_wait(MPT_ADAPTER *ioc, int reqBytes, u32 *req,
4651 int replyBytes, u16 *u16reply, int maxwait, int sleepFlag)
4652{
4653 MPIDefaultReply_t *mptReply;
4654 int failcnt = 0;
4655 int t;
4656
4657 /*
4658 * Get ready to cache a handshake reply
4659 */
4660 ioc->hs_reply_idx = 0;
4661 mptReply = (MPIDefaultReply_t *) ioc->hs_reply;
4662 mptReply->MsgLength = 0;
4663
4664 /*
4665 * Make sure there are no doorbells (WRITE 0 to IntStatus reg),
4666 * then tell IOC that we want to handshake a request of N words.
4667 * (WRITE u32val to Doorbell reg).
4668 */
4669 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4670 CHIPREG_WRITE32(&ioc->chip->Doorbell,
4671 ((MPI_FUNCTION_HANDSHAKE<<MPI_DOORBELL_FUNCTION_SHIFT) |
4672 ((reqBytes/4)<<MPI_DOORBELL_ADD_DWORDS_SHIFT)));
4673
4674 /*
4675 * Wait for IOC's doorbell handshake int
4676 */
4677 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4678 failcnt++;
4679
4680 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request start reqBytes=%d, WaitCnt=%d%s\n",
4681 ioc->name, reqBytes, t, failcnt ? " - MISSING DOORBELL HANDSHAKE!" : ""));
4682
4683 /* Read doorbell and check for active bit */
4684 if (!(CHIPREG_READ32(&ioc->chip->Doorbell) & MPI_DOORBELL_ACTIVE))
4685 return -1;
4686
4687 /*
4688 * Clear doorbell int (WRITE 0 to IntStatus reg),
4689 * then wait for IOC to ACKnowledge that it's ready for
4690 * our handshake request.
4691 */
4692 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4693 if (!failcnt && (t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
4694 failcnt++;
4695
4696 if (!failcnt) {
4697 int ii;
4698 u8 *req_as_bytes = (u8 *) req;
4699
4700 /*
4701 * Stuff request words via doorbell handshake,
4702 * with ACK from IOC for each.
4703 */
4704 for (ii = 0; !failcnt && ii < reqBytes/4; ii++) {
4705 u32 word = ((req_as_bytes[(ii*4) + 0] << 0) |
4706 (req_as_bytes[(ii*4) + 1] << 8) |
4707 (req_as_bytes[(ii*4) + 2] << 16) |
4708 (req_as_bytes[(ii*4) + 3] << 24));
4709
4710 CHIPREG_WRITE32(&ioc->chip->Doorbell, word);
4711 if ((t = WaitForDoorbellAck(ioc, 5, sleepFlag)) < 0)
4712 failcnt++;
4713 }
4714
4715 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Handshake request frame (@%p) header\n", ioc->name, req));
4716 DBG_DUMP_REQUEST_FRAME_HDR(ioc, (u32 *)req);
4717
4718 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake request post done, WaitCnt=%d%s\n",
4719 ioc->name, t, failcnt ? " - MISSING DOORBELL ACK!" : ""));
4720
4721 /*
4722 * Wait for completion of doorbell handshake reply from the IOC
4723 */
4724 if (!failcnt && (t = WaitForDoorbellReply(ioc, maxwait, sleepFlag)) < 0)
4725 failcnt++;
4726
4727 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HandShake reply count=%d%s\n",
4728 ioc->name, t, failcnt ? " - MISSING DOORBELL REPLY!" : ""));
4729
4730 /*
4731 * Copy out the cached reply...
4732 */
4733 for (ii=0; ii < min(replyBytes/2,mptReply->MsgLength*2); ii++)
4734 u16reply[ii] = ioc->hs_reply[ii];
4735 } else {
4736 return -99;
4737 }
4738
4739 return -failcnt;
4740}
4741
4742/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4743/**
4744 * WaitForDoorbellAck - Wait for IOC doorbell handshake acknowledge
4745 * @ioc: Pointer to MPT_ADAPTER structure
4746 * @howlong: How long to wait (in seconds)
4747 * @sleepFlag: Specifies whether the process can sleep
4748 *
4749 * This routine waits (up to ~2 seconds max) for IOC doorbell
4750 * handshake ACKnowledge, indicated by the IOP_DOORBELL_STATUS
4751 * bit in its IntStatus register being clear.
4752 *
4753 * Returns a negative value on failure, else wait loop count.
4754 */
4755static int
4756WaitForDoorbellAck(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
4757{
4758 int cntdn;
4759 int count = 0;
4760 u32 intstat=0;
4761
4762 cntdn = 1000 * howlong;
4763
4764 if (sleepFlag == CAN_SLEEP) {
4765 while (--cntdn) {
4766 msleep (1);
4767 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4768 if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS))
4769 break;
4770 count++;
4771 }
4772 } else {
4773 while (--cntdn) {
4774 udelay (1000);
4775 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4776 if (! (intstat & MPI_HIS_IOP_DOORBELL_STATUS))
4777 break;
4778 count++;
4779 }
4780 }
4781
4782 if (cntdn) {
4783 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell ACK (count=%d)\n",
4784 ioc->name, count));
4785 return count;
4786 }
4787
4788 printk(MYIOC_s_ERR_FMT "Doorbell ACK timeout (count=%d), IntStatus=%x!\n",
4789 ioc->name, count, intstat);
4790 return -1;
4791}
4792
4793/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4794/**
4795 * WaitForDoorbellInt - Wait for IOC to set its doorbell interrupt bit
4796 * @ioc: Pointer to MPT_ADAPTER structure
4797 * @howlong: How long to wait (in seconds)
4798 * @sleepFlag: Specifies whether the process can sleep
4799 *
4800 * This routine waits (up to ~2 seconds max) for IOC doorbell interrupt
4801 * (MPI_HIS_DOORBELL_INTERRUPT) to be set in the IntStatus register.
4802 *
4803 * Returns a negative value on failure, else wait loop count.
4804 */
4805static int
4806WaitForDoorbellInt(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
4807{
4808 int cntdn;
4809 int count = 0;
4810 u32 intstat=0;
4811
4812 cntdn = 1000 * howlong;
4813 if (sleepFlag == CAN_SLEEP) {
4814 while (--cntdn) {
4815 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4816 if (intstat & MPI_HIS_DOORBELL_INTERRUPT)
4817 break;
4818 msleep(1);
4819 count++;
4820 }
4821 } else {
4822 while (--cntdn) {
4823 intstat = CHIPREG_READ32(&ioc->chip->IntStatus);
4824 if (intstat & MPI_HIS_DOORBELL_INTERRUPT)
4825 break;
4826 udelay (1000);
4827 count++;
4828 }
4829 }
4830
4831 if (cntdn) {
4832 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell INT (cnt=%d) howlong=%d\n",
4833 ioc->name, count, howlong));
4834 return count;
4835 }
4836
4837 printk(MYIOC_s_ERR_FMT "Doorbell INT timeout (count=%d), IntStatus=%x!\n",
4838 ioc->name, count, intstat);
4839 return -1;
4840}
4841
4842/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4843/**
4844 * WaitForDoorbellReply - Wait for and capture an IOC handshake reply.
4845 * @ioc: Pointer to MPT_ADAPTER structure
4846 * @howlong: How long to wait (in seconds)
4847 * @sleepFlag: Specifies whether the process can sleep
4848 *
4849 * This routine polls the IOC for a handshake reply, 16 bits at a time.
4850 * Reply is cached to IOC private area large enough to hold a maximum
4851 * of 128 bytes of reply data.
4852 *
4853 * Returns a negative value on failure, else size of reply in WORDS.
4854 */
4855static int
4856WaitForDoorbellReply(MPT_ADAPTER *ioc, int howlong, int sleepFlag)
4857{
4858 int u16cnt = 0;
4859 int failcnt = 0;
4860 int t;
4861 u16 *hs_reply = ioc->hs_reply;
4862 volatile MPIDefaultReply_t *mptReply = (MPIDefaultReply_t *) ioc->hs_reply;
4863 u16 hword;
4864
4865 hs_reply[0] = hs_reply[1] = hs_reply[7] = 0;
4866
4867 /*
4868 * Get first two u16's so we can look at IOC's intended reply MsgLength
4869 */
4870 u16cnt=0;
4871 if ((t = WaitForDoorbellInt(ioc, howlong, sleepFlag)) < 0) {
4872 failcnt++;
4873 } else {
4874 hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
4875 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4876 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4877 failcnt++;
4878 else {
4879 hs_reply[u16cnt++] = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
4880 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4881 }
4882 }
4883
4884 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitCnt=%d First handshake reply word=%08x%s\n",
4885 ioc->name, t, le32_to_cpu(*(u32 *)hs_reply),
4886 failcnt ? " - MISSING DOORBELL HANDSHAKE!" : ""));
4887
4888 /*
4889 * If no error (and IOC said MsgLength is > 0), piece together
4890 * reply 16 bits at a time.
4891 */
4892 for (u16cnt=2; !failcnt && u16cnt < (2 * mptReply->MsgLength); u16cnt++) {
4893 if ((t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4894 failcnt++;
4895 hword = le16_to_cpu(CHIPREG_READ32(&ioc->chip->Doorbell) & 0x0000FFFF);
4896 /* don't overflow our IOC hs_reply[] buffer! */
4897 if (u16cnt < ARRAY_SIZE(ioc->hs_reply))
4898 hs_reply[u16cnt] = hword;
4899 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4900 }
4901
4902 if (!failcnt && (t = WaitForDoorbellInt(ioc, 5, sleepFlag)) < 0)
4903 failcnt++;
4904 CHIPREG_WRITE32(&ioc->chip->IntStatus, 0);
4905
4906 if (failcnt) {
4907 printk(MYIOC_s_ERR_FMT "Handshake reply failure!\n",
4908 ioc->name);
4909 return -failcnt;
4910 }
4911#if 0
4912 else if (u16cnt != (2 * mptReply->MsgLength)) {
4913 return -101;
4914 }
4915 else if ((mptReply->IOCStatus & MPI_IOCSTATUS_MASK) != MPI_IOCSTATUS_SUCCESS) {
4916 return -102;
4917 }
4918#endif
4919
4920 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Got Handshake reply:\n", ioc->name));
4921 DBG_DUMP_REPLY_FRAME(ioc, (u32 *)mptReply);
4922
4923 dhsprintk(ioc, printk(MYIOC_s_DEBUG_FMT "WaitForDoorbell REPLY WaitCnt=%d (sz=%d)\n",
4924 ioc->name, t, u16cnt/2));
4925 return u16cnt/2;
4926}
4927
4928/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
4929/**
4930 * GetLanConfigPages - Fetch LANConfig pages.
4931 * @ioc: Pointer to MPT_ADAPTER structure
4932 *
4933 * Return: 0 for success
4934 * -ENOMEM if no memory available
4935 * -EPERM if not allowed due to ISR context
4936 * -EAGAIN if no msg frames currently available
4937 * -EFAULT for non-successful reply or no reply (timeout)
4938 */
4939static int
4940GetLanConfigPages(MPT_ADAPTER *ioc)
4941{
4942 ConfigPageHeader_t hdr;
4943 CONFIGPARMS cfg;
4944 LANPage0_t *ppage0_alloc;
4945 dma_addr_t page0_dma;
4946 LANPage1_t *ppage1_alloc;
4947 dma_addr_t page1_dma;
4948 int rc = 0;
4949 int data_sz;
4950 int copy_sz;
4951
4952 /* Get LAN Page 0 header */
4953 hdr.PageVersion = 0;
4954 hdr.PageLength = 0;
4955 hdr.PageNumber = 0;
4956 hdr.PageType = MPI_CONFIG_PAGETYPE_LAN;
4957 cfg.cfghdr.hdr = &hdr;
4958 cfg.physAddr = -1;
4959 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
4960 cfg.dir = 0;
4961 cfg.pageAddr = 0;
4962 cfg.timeout = 0;
4963
4964 if ((rc = mpt_config(ioc, &cfg)) != 0)
4965 return rc;
4966
4967 if (hdr.PageLength > 0) {
4968 data_sz = hdr.PageLength * 4;
4969 ppage0_alloc = dma_alloc_coherent(&ioc->pcidev->dev, data_sz,
4970 &page0_dma, GFP_KERNEL);
4971 rc = -ENOMEM;
4972 if (ppage0_alloc) {
4973 memset((u8 *)ppage0_alloc, 0, data_sz);
4974 cfg.physAddr = page0_dma;
4975 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
4976
4977 if ((rc = mpt_config(ioc, &cfg)) == 0) {
4978 /* save the data */
4979 copy_sz = min_t(int, sizeof(LANPage0_t), data_sz);
4980 memcpy(&ioc->lan_cnfg_page0, ppage0_alloc, copy_sz);
4981
4982 }
4983
4984 dma_free_coherent(&ioc->pcidev->dev, data_sz,
4985 (u8 *)ppage0_alloc, page0_dma);
4986
4987 /* FIXME!
4988 * Normalize endianness of structure data,
4989 * by byte-swapping all > 1 byte fields!
4990 */
4991
4992 }
4993
4994 if (rc)
4995 return rc;
4996 }
4997
4998 /* Get LAN Page 1 header */
4999 hdr.PageVersion = 0;
5000 hdr.PageLength = 0;
5001 hdr.PageNumber = 1;
5002 hdr.PageType = MPI_CONFIG_PAGETYPE_LAN;
5003 cfg.cfghdr.hdr = &hdr;
5004 cfg.physAddr = -1;
5005 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5006 cfg.dir = 0;
5007 cfg.pageAddr = 0;
5008
5009 if ((rc = mpt_config(ioc, &cfg)) != 0)
5010 return rc;
5011
5012 if (hdr.PageLength == 0)
5013 return 0;
5014
5015 data_sz = hdr.PageLength * 4;
5016 rc = -ENOMEM;
5017 ppage1_alloc = dma_alloc_coherent(&ioc->pcidev->dev, data_sz,
5018 &page1_dma, GFP_KERNEL);
5019 if (ppage1_alloc) {
5020 memset((u8 *)ppage1_alloc, 0, data_sz);
5021 cfg.physAddr = page1_dma;
5022 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5023
5024 if ((rc = mpt_config(ioc, &cfg)) == 0) {
5025 /* save the data */
5026 copy_sz = min_t(int, sizeof(LANPage1_t), data_sz);
5027 memcpy(&ioc->lan_cnfg_page1, ppage1_alloc, copy_sz);
5028 }
5029
5030 dma_free_coherent(&ioc->pcidev->dev, data_sz,
5031 (u8 *)ppage1_alloc, page1_dma);
5032
5033 /* FIXME!
5034 * Normalize endianness of structure data,
5035 * by byte-swapping all > 1 byte fields!
5036 */
5037
5038 }
5039
5040 return rc;
5041}
5042
5043/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5044/**
5045 * mptbase_sas_persist_operation - Perform operation on SAS Persistent Table
5046 * @ioc: Pointer to MPT_ADAPTER structure
5047 * @persist_opcode: see below
5048 *
5049 * =============================== ======================================
5050 * MPI_SAS_OP_CLEAR_NOT_PRESENT Free all persist TargetID mappings for
5051 * devices not currently present.
5052 * MPI_SAS_OP_CLEAR_ALL_PERSISTENT Clear al persist TargetID mappings
5053 * =============================== ======================================
5054 *
5055 * NOTE: Don't use not this function during interrupt time.
5056 *
5057 * Returns 0 for success, non-zero error
5058 */
5059
5060/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5061int
5062mptbase_sas_persist_operation(MPT_ADAPTER *ioc, u8 persist_opcode)
5063{
5064 SasIoUnitControlRequest_t *sasIoUnitCntrReq;
5065 SasIoUnitControlReply_t *sasIoUnitCntrReply;
5066 MPT_FRAME_HDR *mf = NULL;
5067 MPIHeader_t *mpi_hdr;
5068 int ret = 0;
5069 unsigned long timeleft;
5070
5071 mutex_lock(&ioc->mptbase_cmds.mutex);
5072
5073 /* init the internal cmd struct */
5074 memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE);
5075 INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status)
5076
5077 /* insure garbage is not sent to fw */
5078 switch(persist_opcode) {
5079
5080 case MPI_SAS_OP_CLEAR_NOT_PRESENT:
5081 case MPI_SAS_OP_CLEAR_ALL_PERSISTENT:
5082 break;
5083
5084 default:
5085 ret = -1;
5086 goto out;
5087 }
5088
5089 printk(KERN_DEBUG "%s: persist_opcode=%x\n",
5090 __func__, persist_opcode);
5091
5092 /* Get a MF for this command.
5093 */
5094 if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
5095 printk(KERN_DEBUG "%s: no msg frames!\n", __func__);
5096 ret = -1;
5097 goto out;
5098 }
5099
5100 mpi_hdr = (MPIHeader_t *) mf;
5101 sasIoUnitCntrReq = (SasIoUnitControlRequest_t *)mf;
5102 memset(sasIoUnitCntrReq,0,sizeof(SasIoUnitControlRequest_t));
5103 sasIoUnitCntrReq->Function = MPI_FUNCTION_SAS_IO_UNIT_CONTROL;
5104 sasIoUnitCntrReq->MsgContext = mpi_hdr->MsgContext;
5105 sasIoUnitCntrReq->Operation = persist_opcode;
5106
5107 mpt_put_msg_frame(mpt_base_index, ioc, mf);
5108 timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done, 10*HZ);
5109 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) {
5110 ret = -ETIME;
5111 printk(KERN_DEBUG "%s: failed\n", __func__);
5112 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET)
5113 goto out;
5114 if (!timeleft) {
5115 printk(MYIOC_s_WARN_FMT
5116 "Issuing Reset from %s!!, doorbell=0x%08x\n",
5117 ioc->name, __func__, mpt_GetIocState(ioc, 0));
5118 mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP);
5119 mpt_free_msg_frame(ioc, mf);
5120 }
5121 goto out;
5122 }
5123
5124 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) {
5125 ret = -1;
5126 goto out;
5127 }
5128
5129 sasIoUnitCntrReply =
5130 (SasIoUnitControlReply_t *)ioc->mptbase_cmds.reply;
5131 if (le16_to_cpu(sasIoUnitCntrReply->IOCStatus) != MPI_IOCSTATUS_SUCCESS) {
5132 printk(KERN_DEBUG "%s: IOCStatus=0x%X IOCLogInfo=0x%X\n",
5133 __func__, sasIoUnitCntrReply->IOCStatus,
5134 sasIoUnitCntrReply->IOCLogInfo);
5135 printk(KERN_DEBUG "%s: failed\n", __func__);
5136 ret = -1;
5137 } else
5138 printk(KERN_DEBUG "%s: success\n", __func__);
5139 out:
5140
5141 CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status)
5142 mutex_unlock(&ioc->mptbase_cmds.mutex);
5143 return ret;
5144}
5145
5146/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5147
5148static void
5149mptbase_raid_process_event_data(MPT_ADAPTER *ioc,
5150 MpiEventDataRaid_t * pRaidEventData)
5151{
5152 int volume;
5153 int reason;
5154 int disk;
5155 int status;
5156 int flags;
5157 int state;
5158
5159 volume = pRaidEventData->VolumeID;
5160 reason = pRaidEventData->ReasonCode;
5161 disk = pRaidEventData->PhysDiskNum;
5162 status = le32_to_cpu(pRaidEventData->SettingsStatus);
5163 flags = (status >> 0) & 0xff;
5164 state = (status >> 8) & 0xff;
5165
5166 if (reason == MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED) {
5167 return;
5168 }
5169
5170 if ((reason >= MPI_EVENT_RAID_RC_PHYSDISK_CREATED &&
5171 reason <= MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED) ||
5172 (reason == MPI_EVENT_RAID_RC_SMART_DATA)) {
5173 printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for PhysDisk %d id=%d\n",
5174 ioc->name, disk, volume);
5175 } else {
5176 printk(MYIOC_s_INFO_FMT "RAID STATUS CHANGE for VolumeID %d\n",
5177 ioc->name, volume);
5178 }
5179
5180 switch(reason) {
5181 case MPI_EVENT_RAID_RC_VOLUME_CREATED:
5182 printk(MYIOC_s_INFO_FMT " volume has been created\n",
5183 ioc->name);
5184 break;
5185
5186 case MPI_EVENT_RAID_RC_VOLUME_DELETED:
5187
5188 printk(MYIOC_s_INFO_FMT " volume has been deleted\n",
5189 ioc->name);
5190 break;
5191
5192 case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED:
5193 printk(MYIOC_s_INFO_FMT " volume settings have been changed\n",
5194 ioc->name);
5195 break;
5196
5197 case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED:
5198 printk(MYIOC_s_INFO_FMT " volume is now %s%s%s%s\n",
5199 ioc->name,
5200 state == MPI_RAIDVOL0_STATUS_STATE_OPTIMAL
5201 ? "optimal"
5202 : state == MPI_RAIDVOL0_STATUS_STATE_DEGRADED
5203 ? "degraded"
5204 : state == MPI_RAIDVOL0_STATUS_STATE_FAILED
5205 ? "failed"
5206 : "state unknown",
5207 flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED
5208 ? ", enabled" : "",
5209 flags & MPI_RAIDVOL0_STATUS_FLAG_QUIESCED
5210 ? ", quiesced" : "",
5211 flags & MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS
5212 ? ", resync in progress" : "" );
5213 break;
5214
5215 case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED:
5216 printk(MYIOC_s_INFO_FMT " volume membership of PhysDisk %d has changed\n",
5217 ioc->name, disk);
5218 break;
5219
5220 case MPI_EVENT_RAID_RC_PHYSDISK_CREATED:
5221 printk(MYIOC_s_INFO_FMT " PhysDisk has been created\n",
5222 ioc->name);
5223 break;
5224
5225 case MPI_EVENT_RAID_RC_PHYSDISK_DELETED:
5226 printk(MYIOC_s_INFO_FMT " PhysDisk has been deleted\n",
5227 ioc->name);
5228 break;
5229
5230 case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED:
5231 printk(MYIOC_s_INFO_FMT " PhysDisk settings have been changed\n",
5232 ioc->name);
5233 break;
5234
5235 case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED:
5236 printk(MYIOC_s_INFO_FMT " PhysDisk is now %s%s%s\n",
5237 ioc->name,
5238 state == MPI_PHYSDISK0_STATUS_ONLINE
5239 ? "online"
5240 : state == MPI_PHYSDISK0_STATUS_MISSING
5241 ? "missing"
5242 : state == MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE
5243 ? "not compatible"
5244 : state == MPI_PHYSDISK0_STATUS_FAILED
5245 ? "failed"
5246 : state == MPI_PHYSDISK0_STATUS_INITIALIZING
5247 ? "initializing"
5248 : state == MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED
5249 ? "offline requested"
5250 : state == MPI_PHYSDISK0_STATUS_FAILED_REQUESTED
5251 ? "failed requested"
5252 : state == MPI_PHYSDISK0_STATUS_OTHER_OFFLINE
5253 ? "offline"
5254 : "state unknown",
5255 flags & MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC
5256 ? ", out of sync" : "",
5257 flags & MPI_PHYSDISK0_STATUS_FLAG_QUIESCED
5258 ? ", quiesced" : "" );
5259 break;
5260
5261 case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED:
5262 printk(MYIOC_s_INFO_FMT " Domain Validation needed for PhysDisk %d\n",
5263 ioc->name, disk);
5264 break;
5265
5266 case MPI_EVENT_RAID_RC_SMART_DATA:
5267 printk(MYIOC_s_INFO_FMT " SMART data received, ASC/ASCQ = %02xh/%02xh\n",
5268 ioc->name, pRaidEventData->ASC, pRaidEventData->ASCQ);
5269 break;
5270
5271 case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED:
5272 printk(MYIOC_s_INFO_FMT " replacement of PhysDisk %d has started\n",
5273 ioc->name, disk);
5274 break;
5275 }
5276}
5277
5278/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5279/**
5280 * GetIoUnitPage2 - Retrieve BIOS version and boot order information.
5281 * @ioc: Pointer to MPT_ADAPTER structure
5282 *
5283 * Returns: 0 for success
5284 * -ENOMEM if no memory available
5285 * -EPERM if not allowed due to ISR context
5286 * -EAGAIN if no msg frames currently available
5287 * -EFAULT for non-successful reply or no reply (timeout)
5288 */
5289static int
5290GetIoUnitPage2(MPT_ADAPTER *ioc)
5291{
5292 ConfigPageHeader_t hdr;
5293 CONFIGPARMS cfg;
5294 IOUnitPage2_t *ppage_alloc;
5295 dma_addr_t page_dma;
5296 int data_sz;
5297 int rc;
5298
5299 /* Get the page header */
5300 hdr.PageVersion = 0;
5301 hdr.PageLength = 0;
5302 hdr.PageNumber = 2;
5303 hdr.PageType = MPI_CONFIG_PAGETYPE_IO_UNIT;
5304 cfg.cfghdr.hdr = &hdr;
5305 cfg.physAddr = -1;
5306 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5307 cfg.dir = 0;
5308 cfg.pageAddr = 0;
5309 cfg.timeout = 0;
5310
5311 if ((rc = mpt_config(ioc, &cfg)) != 0)
5312 return rc;
5313
5314 if (hdr.PageLength == 0)
5315 return 0;
5316
5317 /* Read the config page */
5318 data_sz = hdr.PageLength * 4;
5319 rc = -ENOMEM;
5320 ppage_alloc = dma_alloc_coherent(&ioc->pcidev->dev, data_sz,
5321 &page_dma, GFP_KERNEL);
5322 if (ppage_alloc) {
5323 memset((u8 *)ppage_alloc, 0, data_sz);
5324 cfg.physAddr = page_dma;
5325 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5326
5327 /* If Good, save data */
5328 if ((rc = mpt_config(ioc, &cfg)) == 0)
5329 ioc->biosVersion = le32_to_cpu(ppage_alloc->BiosVersion);
5330
5331 dma_free_coherent(&ioc->pcidev->dev, data_sz,
5332 (u8 *)ppage_alloc, page_dma);
5333 }
5334
5335 return rc;
5336}
5337
5338/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5339/**
5340 * mpt_GetScsiPortSettings - read SCSI Port Page 0 and 2
5341 * @ioc: Pointer to a Adapter Strucutre
5342 * @portnum: IOC port number
5343 *
5344 * Return: -EFAULT if read of config page header fails
5345 * or if no nvram
5346 * If read of SCSI Port Page 0 fails,
5347 * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF)
5348 * Adapter settings: async, narrow
5349 * Return 1
5350 * If read of SCSI Port Page 2 fails,
5351 * Adapter settings valid
5352 * NVRAM = MPT_HOST_NVRAM_INVALID (0xFFFFFFFF)
5353 * Return 1
5354 * Else
5355 * Both valid
5356 * Return 0
5357 * CHECK - what type of locking mechanisms should be used????
5358 */
5359static int
5360mpt_GetScsiPortSettings(MPT_ADAPTER *ioc, int portnum)
5361{
5362 u8 *pbuf;
5363 dma_addr_t buf_dma;
5364 CONFIGPARMS cfg;
5365 ConfigPageHeader_t header;
5366 int ii;
5367 int data, rc = 0;
5368
5369 /* Allocate memory
5370 */
5371 if (!ioc->spi_data.nvram) {
5372 int sz;
5373 u8 *mem;
5374 sz = MPT_MAX_SCSI_DEVICES * sizeof(int);
5375 mem = kmalloc(sz, GFP_ATOMIC);
5376 if (mem == NULL)
5377 return -EFAULT;
5378
5379 ioc->spi_data.nvram = (int *) mem;
5380
5381 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SCSI device NVRAM settings @ %p, sz=%d\n",
5382 ioc->name, ioc->spi_data.nvram, sz));
5383 }
5384
5385 /* Invalidate NVRAM information
5386 */
5387 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
5388 ioc->spi_data.nvram[ii] = MPT_HOST_NVRAM_INVALID;
5389 }
5390
5391 /* Read SPP0 header, allocate memory, then read page.
5392 */
5393 header.PageVersion = 0;
5394 header.PageLength = 0;
5395 header.PageNumber = 0;
5396 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT;
5397 cfg.cfghdr.hdr = &header;
5398 cfg.physAddr = -1;
5399 cfg.pageAddr = portnum;
5400 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5401 cfg.dir = 0;
5402 cfg.timeout = 0; /* use default */
5403 if (mpt_config(ioc, &cfg) != 0)
5404 return -EFAULT;
5405
5406 if (header.PageLength > 0) {
5407 pbuf = dma_alloc_coherent(&ioc->pcidev->dev,
5408 header.PageLength * 4, &buf_dma,
5409 GFP_KERNEL);
5410 if (pbuf) {
5411 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5412 cfg.physAddr = buf_dma;
5413 if (mpt_config(ioc, &cfg) != 0) {
5414 ioc->spi_data.maxBusWidth = MPT_NARROW;
5415 ioc->spi_data.maxSyncOffset = 0;
5416 ioc->spi_data.minSyncFactor = MPT_ASYNC;
5417 ioc->spi_data.busType = MPT_HOST_BUS_UNKNOWN;
5418 rc = 1;
5419 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5420 "Unable to read PortPage0 minSyncFactor=%x\n",
5421 ioc->name, ioc->spi_data.minSyncFactor));
5422 } else {
5423 /* Save the Port Page 0 data
5424 */
5425 SCSIPortPage0_t *pPP0 = (SCSIPortPage0_t *) pbuf;
5426 pPP0->Capabilities = le32_to_cpu(pPP0->Capabilities);
5427 pPP0->PhysicalInterface = le32_to_cpu(pPP0->PhysicalInterface);
5428
5429 if ( (pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_QAS) == 0 ) {
5430 ioc->spi_data.noQas |= MPT_TARGET_NO_NEGO_QAS;
5431 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5432 "noQas due to Capabilities=%x\n",
5433 ioc->name, pPP0->Capabilities));
5434 }
5435 ioc->spi_data.maxBusWidth = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_WIDE ? 1 : 0;
5436 data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK;
5437 if (data) {
5438 ioc->spi_data.maxSyncOffset = (u8) (data >> 16);
5439 data = pPP0->Capabilities & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK;
5440 ioc->spi_data.minSyncFactor = (u8) (data >> 8);
5441 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5442 "PortPage0 minSyncFactor=%x\n",
5443 ioc->name, ioc->spi_data.minSyncFactor));
5444 } else {
5445 ioc->spi_data.maxSyncOffset = 0;
5446 ioc->spi_data.minSyncFactor = MPT_ASYNC;
5447 }
5448
5449 ioc->spi_data.busType = pPP0->PhysicalInterface & MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK;
5450
5451 /* Update the minSyncFactor based on bus type.
5452 */
5453 if ((ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD) ||
5454 (ioc->spi_data.busType == MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE)) {
5455
5456 if (ioc->spi_data.minSyncFactor < MPT_ULTRA) {
5457 ioc->spi_data.minSyncFactor = MPT_ULTRA;
5458 ddvprintk(ioc, printk(MYIOC_s_DEBUG_FMT
5459 "HVD or SE detected, minSyncFactor=%x\n",
5460 ioc->name, ioc->spi_data.minSyncFactor));
5461 }
5462 }
5463 }
5464 if (pbuf) {
5465 dma_free_coherent(&ioc->pcidev->dev,
5466 header.PageLength * 4, pbuf,
5467 buf_dma);
5468 }
5469 }
5470 }
5471
5472 /* SCSI Port Page 2 - Read the header then the page.
5473 */
5474 header.PageVersion = 0;
5475 header.PageLength = 0;
5476 header.PageNumber = 2;
5477 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_PORT;
5478 cfg.cfghdr.hdr = &header;
5479 cfg.physAddr = -1;
5480 cfg.pageAddr = portnum;
5481 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5482 cfg.dir = 0;
5483 if (mpt_config(ioc, &cfg) != 0)
5484 return -EFAULT;
5485
5486 if (header.PageLength > 0) {
5487 /* Allocate memory and read SCSI Port Page 2
5488 */
5489 pbuf = dma_alloc_coherent(&ioc->pcidev->dev,
5490 header.PageLength * 4, &buf_dma,
5491 GFP_KERNEL);
5492 if (pbuf) {
5493 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_NVRAM;
5494 cfg.physAddr = buf_dma;
5495 if (mpt_config(ioc, &cfg) != 0) {
5496 /* Nvram data is left with INVALID mark
5497 */
5498 rc = 1;
5499 } else if (ioc->pcidev->vendor == PCI_VENDOR_ID_ATTO) {
5500
5501 /* This is an ATTO adapter, read Page2 accordingly
5502 */
5503 ATTO_SCSIPortPage2_t *pPP2 = (ATTO_SCSIPortPage2_t *) pbuf;
5504 ATTODeviceInfo_t *pdevice = NULL;
5505 u16 ATTOFlags;
5506
5507 /* Save the Port Page 2 data
5508 * (reformat into a 32bit quantity)
5509 */
5510 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
5511 pdevice = &pPP2->DeviceSettings[ii];
5512 ATTOFlags = le16_to_cpu(pdevice->ATTOFlags);
5513 data = 0;
5514
5515 /* Translate ATTO device flags to LSI format
5516 */
5517 if (ATTOFlags & ATTOFLAG_DISC)
5518 data |= (MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE);
5519 if (ATTOFlags & ATTOFLAG_ID_ENB)
5520 data |= (MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE);
5521 if (ATTOFlags & ATTOFLAG_LUN_ENB)
5522 data |= (MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE);
5523 if (ATTOFlags & ATTOFLAG_TAGGED)
5524 data |= (MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE);
5525 if (!(ATTOFlags & ATTOFLAG_WIDE_ENB))
5526 data |= (MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE);
5527
5528 data = (data << 16) | (pdevice->Period << 8) | 10;
5529 ioc->spi_data.nvram[ii] = data;
5530 }
5531 } else {
5532 SCSIPortPage2_t *pPP2 = (SCSIPortPage2_t *) pbuf;
5533 MpiDeviceInfo_t *pdevice = NULL;
5534
5535 /*
5536 * Save "Set to Avoid SCSI Bus Resets" flag
5537 */
5538 ioc->spi_data.bus_reset =
5539 (le32_to_cpu(pPP2->PortFlags) &
5540 MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET) ?
5541 0 : 1 ;
5542
5543 /* Save the Port Page 2 data
5544 * (reformat into a 32bit quantity)
5545 */
5546 data = le32_to_cpu(pPP2->PortFlags) & MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK;
5547 ioc->spi_data.PortFlags = data;
5548 for (ii=0; ii < MPT_MAX_SCSI_DEVICES; ii++) {
5549 pdevice = &pPP2->DeviceSettings[ii];
5550 data = (le16_to_cpu(pdevice->DeviceFlags) << 16) |
5551 (pdevice->SyncFactor << 8) | pdevice->Timeout;
5552 ioc->spi_data.nvram[ii] = data;
5553 }
5554 }
5555
5556 dma_free_coherent(&ioc->pcidev->dev,
5557 header.PageLength * 4, pbuf,
5558 buf_dma);
5559 }
5560 }
5561
5562 /* Update Adapter limits with those from NVRAM
5563 * Comment: Don't need to do this. Target performance
5564 * parameters will never exceed the adapters limits.
5565 */
5566
5567 return rc;
5568}
5569
5570/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
5571/**
5572 * mpt_readScsiDevicePageHeaders - save version and length of SDP1
5573 * @ioc: Pointer to a Adapter Strucutre
5574 * @portnum: IOC port number
5575 *
5576 * Return: -EFAULT if read of config page header fails
5577 * or 0 if success.
5578 */
5579static int
5580mpt_readScsiDevicePageHeaders(MPT_ADAPTER *ioc, int portnum)
5581{
5582 CONFIGPARMS cfg;
5583 ConfigPageHeader_t header;
5584
5585 /* Read the SCSI Device Page 1 header
5586 */
5587 header.PageVersion = 0;
5588 header.PageLength = 0;
5589 header.PageNumber = 1;
5590 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
5591 cfg.cfghdr.hdr = &header;
5592 cfg.physAddr = -1;
5593 cfg.pageAddr = portnum;
5594 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5595 cfg.dir = 0;
5596 cfg.timeout = 0;
5597 if (mpt_config(ioc, &cfg) != 0)
5598 return -EFAULT;
5599
5600 ioc->spi_data.sdp1version = cfg.cfghdr.hdr->PageVersion;
5601 ioc->spi_data.sdp1length = cfg.cfghdr.hdr->PageLength;
5602
5603 header.PageVersion = 0;
5604 header.PageLength = 0;
5605 header.PageNumber = 0;
5606 header.PageType = MPI_CONFIG_PAGETYPE_SCSI_DEVICE;
5607 if (mpt_config(ioc, &cfg) != 0)
5608 return -EFAULT;
5609
5610 ioc->spi_data.sdp0version = cfg.cfghdr.hdr->PageVersion;
5611 ioc->spi_data.sdp0length = cfg.cfghdr.hdr->PageLength;
5612
5613 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 0: version %d length %d\n",
5614 ioc->name, ioc->spi_data.sdp0version, ioc->spi_data.sdp0length));
5615
5616 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Headers: 1: version %d length %d\n",
5617 ioc->name, ioc->spi_data.sdp1version, ioc->spi_data.sdp1length));
5618 return 0;
5619}
5620
5621/**
5622 * mpt_inactive_raid_list_free - This clears this link list.
5623 * @ioc : pointer to per adapter structure
5624 **/
5625static void
5626mpt_inactive_raid_list_free(MPT_ADAPTER *ioc)
5627{
5628 struct inactive_raid_component_info *component_info, *pNext;
5629
5630 if (list_empty(&ioc->raid_data.inactive_list))
5631 return;
5632
5633 mutex_lock(&ioc->raid_data.inactive_list_mutex);
5634 list_for_each_entry_safe(component_info, pNext,
5635 &ioc->raid_data.inactive_list, list) {
5636 list_del(&component_info->list);
5637 kfree(component_info);
5638 }
5639 mutex_unlock(&ioc->raid_data.inactive_list_mutex);
5640}
5641
5642/**
5643 * mpt_inactive_raid_volumes - sets up link list of phy_disk_nums for devices belonging in an inactive volume
5644 *
5645 * @ioc : pointer to per adapter structure
5646 * @channel : volume channel
5647 * @id : volume target id
5648 **/
5649static void
5650mpt_inactive_raid_volumes(MPT_ADAPTER *ioc, u8 channel, u8 id)
5651{
5652 CONFIGPARMS cfg;
5653 ConfigPageHeader_t hdr;
5654 dma_addr_t dma_handle;
5655 pRaidVolumePage0_t buffer = NULL;
5656 int i;
5657 RaidPhysDiskPage0_t phys_disk;
5658 struct inactive_raid_component_info *component_info;
5659 int handle_inactive_volumes;
5660
5661 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5662 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5663 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_VOLUME;
5664 cfg.pageAddr = (channel << 8) + id;
5665 cfg.cfghdr.hdr = &hdr;
5666 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5667
5668 if (mpt_config(ioc, &cfg) != 0)
5669 goto out;
5670
5671 if (!hdr.PageLength)
5672 goto out;
5673
5674 buffer = dma_alloc_coherent(&ioc->pcidev->dev, hdr.PageLength * 4,
5675 &dma_handle, GFP_KERNEL);
5676
5677 if (!buffer)
5678 goto out;
5679
5680 cfg.physAddr = dma_handle;
5681 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5682
5683 if (mpt_config(ioc, &cfg) != 0)
5684 goto out;
5685
5686 if (!buffer->NumPhysDisks)
5687 goto out;
5688
5689 handle_inactive_volumes =
5690 (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE ||
5691 (buffer->VolumeStatus.Flags & MPI_RAIDVOL0_STATUS_FLAG_ENABLED) == 0 ||
5692 buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_FAILED ||
5693 buffer->VolumeStatus.State == MPI_RAIDVOL0_STATUS_STATE_MISSING) ? 1 : 0;
5694
5695 if (!handle_inactive_volumes)
5696 goto out;
5697
5698 mutex_lock(&ioc->raid_data.inactive_list_mutex);
5699 for (i = 0; i < buffer->NumPhysDisks; i++) {
5700 if(mpt_raid_phys_disk_pg0(ioc,
5701 buffer->PhysDisk[i].PhysDiskNum, &phys_disk) != 0)
5702 continue;
5703
5704 if ((component_info = kmalloc(sizeof (*component_info),
5705 GFP_KERNEL)) == NULL)
5706 continue;
5707
5708 component_info->volumeID = id;
5709 component_info->volumeBus = channel;
5710 component_info->d.PhysDiskNum = phys_disk.PhysDiskNum;
5711 component_info->d.PhysDiskBus = phys_disk.PhysDiskBus;
5712 component_info->d.PhysDiskID = phys_disk.PhysDiskID;
5713 component_info->d.PhysDiskIOC = phys_disk.PhysDiskIOC;
5714
5715 list_add_tail(&component_info->list,
5716 &ioc->raid_data.inactive_list);
5717 }
5718 mutex_unlock(&ioc->raid_data.inactive_list_mutex);
5719
5720 out:
5721 if (buffer)
5722 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4,
5723 buffer, dma_handle);
5724}
5725
5726/**
5727 * mpt_raid_phys_disk_pg0 - returns phys disk page zero
5728 * @ioc: Pointer to a Adapter Structure
5729 * @phys_disk_num: io unit unique phys disk num generated by the ioc
5730 * @phys_disk: requested payload data returned
5731 *
5732 * Return:
5733 * 0 on success
5734 * -EFAULT if read of config page header fails or data pointer not NULL
5735 * -ENOMEM if pci_alloc failed
5736 **/
5737int
5738mpt_raid_phys_disk_pg0(MPT_ADAPTER *ioc, u8 phys_disk_num,
5739 RaidPhysDiskPage0_t *phys_disk)
5740{
5741 CONFIGPARMS cfg;
5742 ConfigPageHeader_t hdr;
5743 dma_addr_t dma_handle;
5744 pRaidPhysDiskPage0_t buffer = NULL;
5745 int rc;
5746
5747 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5748 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5749 memset(phys_disk, 0, sizeof(RaidPhysDiskPage0_t));
5750
5751 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE0_PAGEVERSION;
5752 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
5753 cfg.cfghdr.hdr = &hdr;
5754 cfg.physAddr = -1;
5755 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5756
5757 if (mpt_config(ioc, &cfg) != 0) {
5758 rc = -EFAULT;
5759 goto out;
5760 }
5761
5762 if (!hdr.PageLength) {
5763 rc = -EFAULT;
5764 goto out;
5765 }
5766
5767 buffer = dma_alloc_coherent(&ioc->pcidev->dev, hdr.PageLength * 4,
5768 &dma_handle, GFP_KERNEL);
5769
5770 if (!buffer) {
5771 rc = -ENOMEM;
5772 goto out;
5773 }
5774
5775 cfg.physAddr = dma_handle;
5776 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5777 cfg.pageAddr = phys_disk_num;
5778
5779 if (mpt_config(ioc, &cfg) != 0) {
5780 rc = -EFAULT;
5781 goto out;
5782 }
5783
5784 rc = 0;
5785 memcpy(phys_disk, buffer, sizeof(*buffer));
5786 phys_disk->MaxLBA = le32_to_cpu(buffer->MaxLBA);
5787
5788 out:
5789
5790 if (buffer)
5791 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4,
5792 buffer, dma_handle);
5793
5794 return rc;
5795}
5796
5797/**
5798 * mpt_raid_phys_disk_get_num_paths - returns number paths associated to this phys_num
5799 * @ioc: Pointer to a Adapter Structure
5800 * @phys_disk_num: io unit unique phys disk num generated by the ioc
5801 *
5802 * Return:
5803 * returns number paths
5804 **/
5805int
5806mpt_raid_phys_disk_get_num_paths(MPT_ADAPTER *ioc, u8 phys_disk_num)
5807{
5808 CONFIGPARMS cfg;
5809 ConfigPageHeader_t hdr;
5810 dma_addr_t dma_handle;
5811 pRaidPhysDiskPage1_t buffer = NULL;
5812 int rc;
5813
5814 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5815 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5816
5817 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION;
5818 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
5819 hdr.PageNumber = 1;
5820 cfg.cfghdr.hdr = &hdr;
5821 cfg.physAddr = -1;
5822 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5823
5824 if (mpt_config(ioc, &cfg) != 0) {
5825 rc = 0;
5826 goto out;
5827 }
5828
5829 if (!hdr.PageLength) {
5830 rc = 0;
5831 goto out;
5832 }
5833
5834 buffer = dma_alloc_coherent(&ioc->pcidev->dev, hdr.PageLength * 4,
5835 &dma_handle, GFP_KERNEL);
5836
5837 if (!buffer) {
5838 rc = 0;
5839 goto out;
5840 }
5841
5842 cfg.physAddr = dma_handle;
5843 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5844 cfg.pageAddr = phys_disk_num;
5845
5846 if (mpt_config(ioc, &cfg) != 0) {
5847 rc = 0;
5848 goto out;
5849 }
5850
5851 rc = buffer->NumPhysDiskPaths;
5852 out:
5853
5854 if (buffer)
5855 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4,
5856 buffer, dma_handle);
5857
5858 return rc;
5859}
5860EXPORT_SYMBOL(mpt_raid_phys_disk_get_num_paths);
5861
5862/**
5863 * mpt_raid_phys_disk_pg1 - returns phys disk page 1
5864 * @ioc: Pointer to a Adapter Structure
5865 * @phys_disk_num: io unit unique phys disk num generated by the ioc
5866 * @phys_disk: requested payload data returned
5867 *
5868 * Return:
5869 * 0 on success
5870 * -EFAULT if read of config page header fails or data pointer not NULL
5871 * -ENOMEM if pci_alloc failed
5872 **/
5873int
5874mpt_raid_phys_disk_pg1(MPT_ADAPTER *ioc, u8 phys_disk_num,
5875 RaidPhysDiskPage1_t *phys_disk)
5876{
5877 CONFIGPARMS cfg;
5878 ConfigPageHeader_t hdr;
5879 dma_addr_t dma_handle;
5880 pRaidPhysDiskPage1_t buffer = NULL;
5881 int rc;
5882 int i;
5883 __le64 sas_address;
5884
5885 memset(&cfg, 0 , sizeof(CONFIGPARMS));
5886 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
5887 rc = 0;
5888
5889 hdr.PageVersion = MPI_RAIDPHYSDISKPAGE1_PAGEVERSION;
5890 hdr.PageType = MPI_CONFIG_PAGETYPE_RAID_PHYSDISK;
5891 hdr.PageNumber = 1;
5892 cfg.cfghdr.hdr = &hdr;
5893 cfg.physAddr = -1;
5894 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5895
5896 if (mpt_config(ioc, &cfg) != 0) {
5897 rc = -EFAULT;
5898 goto out;
5899 }
5900
5901 if (!hdr.PageLength) {
5902 rc = -EFAULT;
5903 goto out;
5904 }
5905
5906 buffer = dma_alloc_coherent(&ioc->pcidev->dev, hdr.PageLength * 4,
5907 &dma_handle, GFP_KERNEL);
5908
5909 if (!buffer) {
5910 rc = -ENOMEM;
5911 goto out;
5912 }
5913
5914 cfg.physAddr = dma_handle;
5915 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
5916 cfg.pageAddr = phys_disk_num;
5917
5918 if (mpt_config(ioc, &cfg) != 0) {
5919 rc = -EFAULT;
5920 goto out;
5921 }
5922
5923 phys_disk->NumPhysDiskPaths = buffer->NumPhysDiskPaths;
5924 phys_disk->PhysDiskNum = phys_disk_num;
5925 for (i = 0; i < phys_disk->NumPhysDiskPaths; i++) {
5926 phys_disk->Path[i].PhysDiskID = buffer->Path[i].PhysDiskID;
5927 phys_disk->Path[i].PhysDiskBus = buffer->Path[i].PhysDiskBus;
5928 phys_disk->Path[i].OwnerIdentifier =
5929 buffer->Path[i].OwnerIdentifier;
5930 phys_disk->Path[i].Flags = le16_to_cpu(buffer->Path[i].Flags);
5931 memcpy(&sas_address, &buffer->Path[i].WWID, sizeof(__le64));
5932 sas_address = le64_to_cpu(sas_address);
5933 memcpy(&phys_disk->Path[i].WWID, &sas_address, sizeof(__le64));
5934 memcpy(&sas_address,
5935 &buffer->Path[i].OwnerWWID, sizeof(__le64));
5936 sas_address = le64_to_cpu(sas_address);
5937 memcpy(&phys_disk->Path[i].OwnerWWID,
5938 &sas_address, sizeof(__le64));
5939 }
5940
5941 out:
5942
5943 if (buffer)
5944 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4,
5945 buffer, dma_handle);
5946
5947 return rc;
5948}
5949EXPORT_SYMBOL(mpt_raid_phys_disk_pg1);
5950
5951
5952/**
5953 * mpt_findImVolumes - Identify IDs of hidden disks and RAID Volumes
5954 * @ioc: Pointer to a Adapter Strucutre
5955 *
5956 * Return:
5957 * 0 on success
5958 * -EFAULT if read of config page header fails or data pointer not NULL
5959 * -ENOMEM if pci_alloc failed
5960 **/
5961int
5962mpt_findImVolumes(MPT_ADAPTER *ioc)
5963{
5964 IOCPage2_t *pIoc2;
5965 u8 *mem;
5966 dma_addr_t ioc2_dma;
5967 CONFIGPARMS cfg;
5968 ConfigPageHeader_t header;
5969 int rc = 0;
5970 int iocpage2sz;
5971 int i;
5972
5973 if (!ioc->ir_firmware)
5974 return 0;
5975
5976 /* Free the old page
5977 */
5978 kfree(ioc->raid_data.pIocPg2);
5979 ioc->raid_data.pIocPg2 = NULL;
5980 mpt_inactive_raid_list_free(ioc);
5981
5982 /* Read IOCP2 header then the page.
5983 */
5984 header.PageVersion = 0;
5985 header.PageLength = 0;
5986 header.PageNumber = 2;
5987 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
5988 cfg.cfghdr.hdr = &header;
5989 cfg.physAddr = -1;
5990 cfg.pageAddr = 0;
5991 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
5992 cfg.dir = 0;
5993 cfg.timeout = 0;
5994 if (mpt_config(ioc, &cfg) != 0)
5995 return -EFAULT;
5996
5997 if (header.PageLength == 0)
5998 return -EFAULT;
5999
6000 iocpage2sz = header.PageLength * 4;
6001 pIoc2 = dma_alloc_coherent(&ioc->pcidev->dev, iocpage2sz, &ioc2_dma,
6002 GFP_KERNEL);
6003 if (!pIoc2)
6004 return -ENOMEM;
6005
6006 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6007 cfg.physAddr = ioc2_dma;
6008 if (mpt_config(ioc, &cfg) != 0)
6009 goto out;
6010
6011 mem = kmemdup(pIoc2, iocpage2sz, GFP_KERNEL);
6012 if (!mem) {
6013 rc = -ENOMEM;
6014 goto out;
6015 }
6016
6017 ioc->raid_data.pIocPg2 = (IOCPage2_t *) mem;
6018
6019 mpt_read_ioc_pg_3(ioc);
6020
6021 for (i = 0; i < pIoc2->NumActiveVolumes ; i++)
6022 mpt_inactive_raid_volumes(ioc,
6023 pIoc2->RaidVolume[i].VolumeBus,
6024 pIoc2->RaidVolume[i].VolumeID);
6025
6026 out:
6027 dma_free_coherent(&ioc->pcidev->dev, iocpage2sz, pIoc2, ioc2_dma);
6028
6029 return rc;
6030}
6031
6032static int
6033mpt_read_ioc_pg_3(MPT_ADAPTER *ioc)
6034{
6035 IOCPage3_t *pIoc3;
6036 u8 *mem;
6037 CONFIGPARMS cfg;
6038 ConfigPageHeader_t header;
6039 dma_addr_t ioc3_dma;
6040 int iocpage3sz = 0;
6041
6042 /* Free the old page
6043 */
6044 kfree(ioc->raid_data.pIocPg3);
6045 ioc->raid_data.pIocPg3 = NULL;
6046
6047 /* There is at least one physical disk.
6048 * Read and save IOC Page 3
6049 */
6050 header.PageVersion = 0;
6051 header.PageLength = 0;
6052 header.PageNumber = 3;
6053 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
6054 cfg.cfghdr.hdr = &header;
6055 cfg.physAddr = -1;
6056 cfg.pageAddr = 0;
6057 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6058 cfg.dir = 0;
6059 cfg.timeout = 0;
6060 if (mpt_config(ioc, &cfg) != 0)
6061 return 0;
6062
6063 if (header.PageLength == 0)
6064 return 0;
6065
6066 /* Read Header good, alloc memory
6067 */
6068 iocpage3sz = header.PageLength * 4;
6069 pIoc3 = dma_alloc_coherent(&ioc->pcidev->dev, iocpage3sz, &ioc3_dma,
6070 GFP_KERNEL);
6071 if (!pIoc3)
6072 return 0;
6073
6074 /* Read the Page and save the data
6075 * into malloc'd memory.
6076 */
6077 cfg.physAddr = ioc3_dma;
6078 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6079 if (mpt_config(ioc, &cfg) == 0) {
6080 mem = kmalloc(iocpage3sz, GFP_KERNEL);
6081 if (mem) {
6082 memcpy(mem, (u8 *)pIoc3, iocpage3sz);
6083 ioc->raid_data.pIocPg3 = (IOCPage3_t *) mem;
6084 }
6085 }
6086
6087 dma_free_coherent(&ioc->pcidev->dev, iocpage3sz, pIoc3, ioc3_dma);
6088
6089 return 0;
6090}
6091
6092static void
6093mpt_read_ioc_pg_4(MPT_ADAPTER *ioc)
6094{
6095 IOCPage4_t *pIoc4;
6096 CONFIGPARMS cfg;
6097 ConfigPageHeader_t header;
6098 dma_addr_t ioc4_dma;
6099 int iocpage4sz;
6100
6101 /* Read and save IOC Page 4
6102 */
6103 header.PageVersion = 0;
6104 header.PageLength = 0;
6105 header.PageNumber = 4;
6106 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
6107 cfg.cfghdr.hdr = &header;
6108 cfg.physAddr = -1;
6109 cfg.pageAddr = 0;
6110 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6111 cfg.dir = 0;
6112 cfg.timeout = 0;
6113 if (mpt_config(ioc, &cfg) != 0)
6114 return;
6115
6116 if (header.PageLength == 0)
6117 return;
6118
6119 if ( (pIoc4 = ioc->spi_data.pIocPg4) == NULL ) {
6120 iocpage4sz = (header.PageLength + 4) * 4; /* Allow 4 additional SEP's */
6121 pIoc4 = dma_alloc_coherent(&ioc->pcidev->dev, iocpage4sz,
6122 &ioc4_dma, GFP_KERNEL);
6123 if (!pIoc4)
6124 return;
6125 ioc->alloc_total += iocpage4sz;
6126 } else {
6127 ioc4_dma = ioc->spi_data.IocPg4_dma;
6128 iocpage4sz = ioc->spi_data.IocPg4Sz;
6129 }
6130
6131 /* Read the Page into dma memory.
6132 */
6133 cfg.physAddr = ioc4_dma;
6134 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6135 if (mpt_config(ioc, &cfg) == 0) {
6136 ioc->spi_data.pIocPg4 = (IOCPage4_t *) pIoc4;
6137 ioc->spi_data.IocPg4_dma = ioc4_dma;
6138 ioc->spi_data.IocPg4Sz = iocpage4sz;
6139 } else {
6140 dma_free_coherent(&ioc->pcidev->dev, iocpage4sz, pIoc4,
6141 ioc4_dma);
6142 ioc->spi_data.pIocPg4 = NULL;
6143 ioc->alloc_total -= iocpage4sz;
6144 }
6145}
6146
6147static void
6148mpt_read_ioc_pg_1(MPT_ADAPTER *ioc)
6149{
6150 IOCPage1_t *pIoc1;
6151 CONFIGPARMS cfg;
6152 ConfigPageHeader_t header;
6153 dma_addr_t ioc1_dma;
6154 int iocpage1sz = 0;
6155 u32 tmp;
6156
6157 /* Check the Coalescing Timeout in IOC Page 1
6158 */
6159 header.PageVersion = 0;
6160 header.PageLength = 0;
6161 header.PageNumber = 1;
6162 header.PageType = MPI_CONFIG_PAGETYPE_IOC;
6163 cfg.cfghdr.hdr = &header;
6164 cfg.physAddr = -1;
6165 cfg.pageAddr = 0;
6166 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6167 cfg.dir = 0;
6168 cfg.timeout = 0;
6169 if (mpt_config(ioc, &cfg) != 0)
6170 return;
6171
6172 if (header.PageLength == 0)
6173 return;
6174
6175 /* Read Header good, alloc memory
6176 */
6177 iocpage1sz = header.PageLength * 4;
6178 pIoc1 = dma_alloc_coherent(&ioc->pcidev->dev, iocpage1sz, &ioc1_dma,
6179 GFP_KERNEL);
6180 if (!pIoc1)
6181 return;
6182
6183 /* Read the Page and check coalescing timeout
6184 */
6185 cfg.physAddr = ioc1_dma;
6186 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6187 if (mpt_config(ioc, &cfg) == 0) {
6188
6189 tmp = le32_to_cpu(pIoc1->Flags) & MPI_IOCPAGE1_REPLY_COALESCING;
6190 if (tmp == MPI_IOCPAGE1_REPLY_COALESCING) {
6191 tmp = le32_to_cpu(pIoc1->CoalescingTimeout);
6192
6193 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Coalescing Enabled Timeout = %d\n",
6194 ioc->name, tmp));
6195
6196 if (tmp > MPT_COALESCING_TIMEOUT) {
6197 pIoc1->CoalescingTimeout = cpu_to_le32(MPT_COALESCING_TIMEOUT);
6198
6199 /* Write NVRAM and current
6200 */
6201 cfg.dir = 1;
6202 cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT;
6203 if (mpt_config(ioc, &cfg) == 0) {
6204 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Reset Current Coalescing Timeout to = %d\n",
6205 ioc->name, MPT_COALESCING_TIMEOUT));
6206
6207 cfg.action = MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM;
6208 if (mpt_config(ioc, &cfg) == 0) {
6209 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6210 "Reset NVRAM Coalescing Timeout to = %d\n",
6211 ioc->name, MPT_COALESCING_TIMEOUT));
6212 } else {
6213 dprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6214 "Reset NVRAM Coalescing Timeout Failed\n",
6215 ioc->name));
6216 }
6217
6218 } else {
6219 dprintk(ioc, printk(MYIOC_s_WARN_FMT
6220 "Reset of Current Coalescing Timeout Failed!\n",
6221 ioc->name));
6222 }
6223 }
6224
6225 } else {
6226 dprintk(ioc, printk(MYIOC_s_WARN_FMT "Coalescing Disabled\n", ioc->name));
6227 }
6228 }
6229
6230 dma_free_coherent(&ioc->pcidev->dev, iocpage1sz, pIoc1, ioc1_dma);
6231
6232 return;
6233}
6234
6235static void
6236mpt_get_manufacturing_pg_0(MPT_ADAPTER *ioc)
6237{
6238 CONFIGPARMS cfg;
6239 ConfigPageHeader_t hdr;
6240 dma_addr_t buf_dma;
6241 ManufacturingPage0_t *pbuf = NULL;
6242
6243 memset(&cfg, 0 , sizeof(CONFIGPARMS));
6244 memset(&hdr, 0 , sizeof(ConfigPageHeader_t));
6245
6246 hdr.PageType = MPI_CONFIG_PAGETYPE_MANUFACTURING;
6247 cfg.cfghdr.hdr = &hdr;
6248 cfg.physAddr = -1;
6249 cfg.action = MPI_CONFIG_ACTION_PAGE_HEADER;
6250 cfg.timeout = 10;
6251
6252 if (mpt_config(ioc, &cfg) != 0)
6253 goto out;
6254
6255 if (!cfg.cfghdr.hdr->PageLength)
6256 goto out;
6257
6258 cfg.action = MPI_CONFIG_ACTION_PAGE_READ_CURRENT;
6259 pbuf = dma_alloc_coherent(&ioc->pcidev->dev, hdr.PageLength * 4,
6260 &buf_dma, GFP_KERNEL);
6261 if (!pbuf)
6262 goto out;
6263
6264 cfg.physAddr = buf_dma;
6265
6266 if (mpt_config(ioc, &cfg) != 0)
6267 goto out;
6268
6269 memcpy(ioc->board_name, pbuf->BoardName, sizeof(ioc->board_name));
6270 memcpy(ioc->board_assembly, pbuf->BoardAssembly, sizeof(ioc->board_assembly));
6271 memcpy(ioc->board_tracer, pbuf->BoardTracerNumber, sizeof(ioc->board_tracer));
6272
6273out:
6274
6275 if (pbuf)
6276 dma_free_coherent(&ioc->pcidev->dev, hdr.PageLength * 4, pbuf,
6277 buf_dma);
6278}
6279
6280/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6281/**
6282 * SendEventNotification - Send EventNotification (on or off) request to adapter
6283 * @ioc: Pointer to MPT_ADAPTER structure
6284 * @EvSwitch: Event switch flags
6285 * @sleepFlag: Specifies whether the process can sleep
6286 */
6287static int
6288SendEventNotification(MPT_ADAPTER *ioc, u8 EvSwitch, int sleepFlag)
6289{
6290 EventNotification_t evn;
6291 MPIDefaultReply_t reply_buf;
6292
6293 memset(&evn, 0, sizeof(EventNotification_t));
6294 memset(&reply_buf, 0, sizeof(MPIDefaultReply_t));
6295
6296 evn.Function = MPI_FUNCTION_EVENT_NOTIFICATION;
6297 evn.Switch = EvSwitch;
6298 evn.MsgContext = cpu_to_le32(mpt_base_index << 16);
6299
6300 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6301 "Sending EventNotification (%d) request %p\n",
6302 ioc->name, EvSwitch, &evn));
6303
6304 return mpt_handshake_req_reply_wait(ioc, sizeof(EventNotification_t),
6305 (u32 *)&evn, sizeof(MPIDefaultReply_t), (u16 *)&reply_buf, 30,
6306 sleepFlag);
6307}
6308
6309/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6310/**
6311 * SendEventAck - Send EventAck request to MPT adapter.
6312 * @ioc: Pointer to MPT_ADAPTER structure
6313 * @evnp: Pointer to original EventNotification request
6314 */
6315static int
6316SendEventAck(MPT_ADAPTER *ioc, EventNotificationReply_t *evnp)
6317{
6318 EventAck_t *pAck;
6319
6320 if ((pAck = (EventAck_t *) mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
6321 dfailprintk(ioc, printk(MYIOC_s_WARN_FMT "%s, no msg frames!!\n",
6322 ioc->name, __func__));
6323 return -1;
6324 }
6325
6326 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "Sending EventAck\n", ioc->name));
6327
6328 pAck->Function = MPI_FUNCTION_EVENT_ACK;
6329 pAck->ChainOffset = 0;
6330 pAck->Reserved[0] = pAck->Reserved[1] = 0;
6331 pAck->MsgFlags = 0;
6332 pAck->Reserved1[0] = pAck->Reserved1[1] = pAck->Reserved1[2] = 0;
6333 pAck->Event = evnp->Event;
6334 pAck->EventContext = evnp->EventContext;
6335
6336 mpt_put_msg_frame(mpt_base_index, ioc, (MPT_FRAME_HDR *)pAck);
6337
6338 return 0;
6339}
6340
6341/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6342/**
6343 * mpt_config - Generic function to issue config message
6344 * @ioc: Pointer to an adapter structure
6345 * @pCfg: Pointer to a configuration structure. Struct contains
6346 * action, page address, direction, physical address
6347 * and pointer to a configuration page header
6348 * Page header is updated.
6349 *
6350 * Returns 0 for success
6351 * -EAGAIN if no msg frames currently available
6352 * -EFAULT for non-successful reply or no reply (timeout)
6353 */
6354int
6355mpt_config(MPT_ADAPTER *ioc, CONFIGPARMS *pCfg)
6356{
6357 Config_t *pReq;
6358 ConfigReply_t *pReply;
6359 ConfigExtendedPageHeader_t *pExtHdr = NULL;
6360 MPT_FRAME_HDR *mf;
6361 int ii;
6362 int flagsLength;
6363 long timeout;
6364 int ret;
6365 u8 page_type = 0, extend_page;
6366 unsigned long timeleft;
6367 unsigned long flags;
6368 u8 issue_hard_reset = 0;
6369 u8 retry_count = 0;
6370
6371 might_sleep();
6372
6373 /* don't send a config page during diag reset */
6374 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6375 if (ioc->ioc_reset_in_progress) {
6376 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6377 "%s: busy with host reset\n", ioc->name, __func__));
6378 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6379 return -EBUSY;
6380 }
6381 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6382
6383 /* don't send if no chance of success */
6384 if (!ioc->active ||
6385 mpt_GetIocState(ioc, 1) != MPI_IOC_STATE_OPERATIONAL) {
6386 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6387 "%s: ioc not operational, %d, %xh\n",
6388 ioc->name, __func__, ioc->active,
6389 mpt_GetIocState(ioc, 0)));
6390 return -EFAULT;
6391 }
6392
6393 retry_config:
6394 mutex_lock(&ioc->mptbase_cmds.mutex);
6395 /* init the internal cmd struct */
6396 memset(ioc->mptbase_cmds.reply, 0 , MPT_DEFAULT_FRAME_SIZE);
6397 INITIALIZE_MGMT_STATUS(ioc->mptbase_cmds.status)
6398
6399 /* Get and Populate a free Frame
6400 */
6401 if ((mf = mpt_get_msg_frame(mpt_base_index, ioc)) == NULL) {
6402 dcprintk(ioc, printk(MYIOC_s_WARN_FMT
6403 "mpt_config: no msg frames!\n", ioc->name));
6404 ret = -EAGAIN;
6405 goto out;
6406 }
6407
6408 pReq = (Config_t *)mf;
6409 pReq->Action = pCfg->action;
6410 pReq->Reserved = 0;
6411 pReq->ChainOffset = 0;
6412 pReq->Function = MPI_FUNCTION_CONFIG;
6413
6414 /* Assume page type is not extended and clear "reserved" fields. */
6415 pReq->ExtPageLength = 0;
6416 pReq->ExtPageType = 0;
6417 pReq->MsgFlags = 0;
6418
6419 for (ii=0; ii < 8; ii++)
6420 pReq->Reserved2[ii] = 0;
6421
6422 pReq->Header.PageVersion = pCfg->cfghdr.hdr->PageVersion;
6423 pReq->Header.PageLength = pCfg->cfghdr.hdr->PageLength;
6424 pReq->Header.PageNumber = pCfg->cfghdr.hdr->PageNumber;
6425 pReq->Header.PageType = (pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK);
6426
6427 if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) == MPI_CONFIG_PAGETYPE_EXTENDED) {
6428 pExtHdr = (ConfigExtendedPageHeader_t *)pCfg->cfghdr.ehdr;
6429 pReq->ExtPageLength = cpu_to_le16(pExtHdr->ExtPageLength);
6430 pReq->ExtPageType = pExtHdr->ExtPageType;
6431 pReq->Header.PageType = MPI_CONFIG_PAGETYPE_EXTENDED;
6432
6433 /* Page Length must be treated as a reserved field for the
6434 * extended header.
6435 */
6436 pReq->Header.PageLength = 0;
6437 }
6438
6439 pReq->PageAddress = cpu_to_le32(pCfg->pageAddr);
6440
6441 /* Add a SGE to the config request.
6442 */
6443 if (pCfg->dir)
6444 flagsLength = MPT_SGE_FLAGS_SSIMPLE_WRITE;
6445 else
6446 flagsLength = MPT_SGE_FLAGS_SSIMPLE_READ;
6447
6448 if ((pCfg->cfghdr.hdr->PageType & MPI_CONFIG_PAGETYPE_MASK) ==
6449 MPI_CONFIG_PAGETYPE_EXTENDED) {
6450 flagsLength |= pExtHdr->ExtPageLength * 4;
6451 page_type = pReq->ExtPageType;
6452 extend_page = 1;
6453 } else {
6454 flagsLength |= pCfg->cfghdr.hdr->PageLength * 4;
6455 page_type = pReq->Header.PageType;
6456 extend_page = 0;
6457 }
6458
6459 dcprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6460 "Sending Config request type 0x%x, page 0x%x and action %d\n",
6461 ioc->name, page_type, pReq->Header.PageNumber, pReq->Action));
6462
6463 ioc->add_sge((char *)&pReq->PageBufferSGE, flagsLength, pCfg->physAddr);
6464 timeout = (pCfg->timeout < 15) ? HZ*15 : HZ*pCfg->timeout;
6465 mpt_put_msg_frame(mpt_base_index, ioc, mf);
6466 timeleft = wait_for_completion_timeout(&ioc->mptbase_cmds.done,
6467 timeout);
6468 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_COMMAND_GOOD)) {
6469 ret = -ETIME;
6470 dfailprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6471 "Failed Sending Config request type 0x%x, page 0x%x,"
6472 " action %d, status %xh, time left %ld\n\n",
6473 ioc->name, page_type, pReq->Header.PageNumber,
6474 pReq->Action, ioc->mptbase_cmds.status, timeleft));
6475 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_DID_IOCRESET)
6476 goto out;
6477 if (!timeleft) {
6478 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6479 if (ioc->ioc_reset_in_progress) {
6480 spin_unlock_irqrestore(&ioc->taskmgmt_lock,
6481 flags);
6482 printk(MYIOC_s_INFO_FMT "%s: host reset in"
6483 " progress mpt_config timed out.!!\n",
6484 __func__, ioc->name);
6485 mutex_unlock(&ioc->mptbase_cmds.mutex);
6486 return -EFAULT;
6487 }
6488 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6489 issue_hard_reset = 1;
6490 }
6491 goto out;
6492 }
6493
6494 if (!(ioc->mptbase_cmds.status & MPT_MGMT_STATUS_RF_VALID)) {
6495 ret = -1;
6496 goto out;
6497 }
6498 pReply = (ConfigReply_t *)ioc->mptbase_cmds.reply;
6499 ret = le16_to_cpu(pReply->IOCStatus) & MPI_IOCSTATUS_MASK;
6500 if (ret == MPI_IOCSTATUS_SUCCESS) {
6501 if (extend_page) {
6502 pCfg->cfghdr.ehdr->ExtPageLength =
6503 le16_to_cpu(pReply->ExtPageLength);
6504 pCfg->cfghdr.ehdr->ExtPageType =
6505 pReply->ExtPageType;
6506 }
6507 pCfg->cfghdr.hdr->PageVersion = pReply->Header.PageVersion;
6508 pCfg->cfghdr.hdr->PageLength = pReply->Header.PageLength;
6509 pCfg->cfghdr.hdr->PageNumber = pReply->Header.PageNumber;
6510 pCfg->cfghdr.hdr->PageType = pReply->Header.PageType;
6511
6512 }
6513
6514 if (retry_count)
6515 printk(MYIOC_s_INFO_FMT "Retry completed "
6516 "ret=0x%x timeleft=%ld\n",
6517 ioc->name, ret, timeleft);
6518
6519 dcprintk(ioc, printk(KERN_DEBUG "IOCStatus=%04xh, IOCLogInfo=%08xh\n",
6520 ret, le32_to_cpu(pReply->IOCLogInfo)));
6521
6522out:
6523
6524 CLEAR_MGMT_STATUS(ioc->mptbase_cmds.status)
6525 mutex_unlock(&ioc->mptbase_cmds.mutex);
6526 if (issue_hard_reset) {
6527 issue_hard_reset = 0;
6528 printk(MYIOC_s_WARN_FMT
6529 "Issuing Reset from %s!!, doorbell=0x%08x\n",
6530 ioc->name, __func__, mpt_GetIocState(ioc, 0));
6531 if (retry_count == 0) {
6532 if (mpt_Soft_Hard_ResetHandler(ioc, CAN_SLEEP) != 0)
6533 retry_count++;
6534 } else
6535 mpt_HardResetHandler(ioc, CAN_SLEEP);
6536
6537 mpt_free_msg_frame(ioc, mf);
6538 /* attempt one retry for a timed out command */
6539 if (retry_count < 2) {
6540 printk(MYIOC_s_INFO_FMT
6541 "Attempting Retry Config request"
6542 " type 0x%x, page 0x%x,"
6543 " action %d\n", ioc->name, page_type,
6544 pCfg->cfghdr.hdr->PageNumber, pCfg->action);
6545 retry_count++;
6546 goto retry_config;
6547 }
6548 }
6549 return ret;
6550
6551}
6552
6553/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6554/**
6555 * mpt_ioc_reset - Base cleanup for hard reset
6556 * @ioc: Pointer to the adapter structure
6557 * @reset_phase: Indicates pre- or post-reset functionality
6558 *
6559 * Remark: Frees resources with internally generated commands.
6560 */
6561static int
6562mpt_ioc_reset(MPT_ADAPTER *ioc, int reset_phase)
6563{
6564 switch (reset_phase) {
6565 case MPT_IOC_SETUP_RESET:
6566 ioc->taskmgmt_quiesce_io = 1;
6567 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6568 "%s: MPT_IOC_SETUP_RESET\n", ioc->name, __func__));
6569 break;
6570 case MPT_IOC_PRE_RESET:
6571 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6572 "%s: MPT_IOC_PRE_RESET\n", ioc->name, __func__));
6573 break;
6574 case MPT_IOC_POST_RESET:
6575 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6576 "%s: MPT_IOC_POST_RESET\n", ioc->name, __func__));
6577/* wake up mptbase_cmds */
6578 if (ioc->mptbase_cmds.status & MPT_MGMT_STATUS_PENDING) {
6579 ioc->mptbase_cmds.status |=
6580 MPT_MGMT_STATUS_DID_IOCRESET;
6581 complete(&ioc->mptbase_cmds.done);
6582 }
6583/* wake up taskmgmt_cmds */
6584 if (ioc->taskmgmt_cmds.status & MPT_MGMT_STATUS_PENDING) {
6585 ioc->taskmgmt_cmds.status |=
6586 MPT_MGMT_STATUS_DID_IOCRESET;
6587 complete(&ioc->taskmgmt_cmds.done);
6588 }
6589 break;
6590 default:
6591 break;
6592 }
6593
6594 return 1; /* currently means nothing really */
6595}
6596
6597
6598#ifdef CONFIG_PROC_FS /* { */
6599/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6600/*
6601 * procfs (%MPT_PROCFS_MPTBASEDIR/...) support stuff...
6602 */
6603/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6604/**
6605 * procmpt_create - Create %MPT_PROCFS_MPTBASEDIR entries.
6606 *
6607 * Returns 0 for success, non-zero for failure.
6608 */
6609static int
6610procmpt_create(void)
6611{
6612 mpt_proc_root_dir = proc_mkdir(MPT_PROCFS_MPTBASEDIR, NULL);
6613 if (mpt_proc_root_dir == NULL)
6614 return -ENOTDIR;
6615
6616 proc_create_single("summary", S_IRUGO, mpt_proc_root_dir,
6617 mpt_summary_proc_show);
6618 proc_create_single("version", S_IRUGO, mpt_proc_root_dir,
6619 mpt_version_proc_show);
6620 return 0;
6621}
6622
6623/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6624/**
6625 * procmpt_destroy - Tear down %MPT_PROCFS_MPTBASEDIR entries.
6626 *
6627 * Returns 0 for success, non-zero for failure.
6628 */
6629static void
6630procmpt_destroy(void)
6631{
6632 remove_proc_entry("version", mpt_proc_root_dir);
6633 remove_proc_entry("summary", mpt_proc_root_dir);
6634 remove_proc_entry(MPT_PROCFS_MPTBASEDIR, NULL);
6635}
6636
6637/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6638/*
6639 * Handles read request from /proc/mpt/summary or /proc/mpt/iocN/summary.
6640 */
6641static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan);
6642
6643static int mpt_summary_proc_show(struct seq_file *m, void *v)
6644{
6645 MPT_ADAPTER *ioc = m->private;
6646
6647 if (ioc) {
6648 seq_mpt_print_ioc_summary(ioc, m, 1);
6649 } else {
6650 list_for_each_entry(ioc, &ioc_list, list) {
6651 seq_mpt_print_ioc_summary(ioc, m, 1);
6652 }
6653 }
6654
6655 return 0;
6656}
6657
6658static int mpt_version_proc_show(struct seq_file *m, void *v)
6659{
6660 u8 cb_idx;
6661 int scsi, fc, sas, lan, ctl, targ;
6662 char *drvname;
6663
6664 seq_printf(m, "%s-%s\n", "mptlinux", MPT_LINUX_VERSION_COMMON);
6665 seq_printf(m, " Fusion MPT base driver\n");
6666
6667 scsi = fc = sas = lan = ctl = targ = 0;
6668 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
6669 drvname = NULL;
6670 if (MptCallbacks[cb_idx]) {
6671 switch (MptDriverClass[cb_idx]) {
6672 case MPTSPI_DRIVER:
6673 if (!scsi++) drvname = "SPI host";
6674 break;
6675 case MPTFC_DRIVER:
6676 if (!fc++) drvname = "FC host";
6677 break;
6678 case MPTSAS_DRIVER:
6679 if (!sas++) drvname = "SAS host";
6680 break;
6681 case MPTLAN_DRIVER:
6682 if (!lan++) drvname = "LAN";
6683 break;
6684 case MPTSTM_DRIVER:
6685 if (!targ++) drvname = "SCSI target";
6686 break;
6687 case MPTCTL_DRIVER:
6688 if (!ctl++) drvname = "ioctl";
6689 break;
6690 }
6691
6692 if (drvname)
6693 seq_printf(m, " Fusion MPT %s driver\n", drvname);
6694 }
6695 }
6696
6697 return 0;
6698}
6699
6700static int mpt_iocinfo_proc_show(struct seq_file *m, void *v)
6701{
6702 MPT_ADAPTER *ioc = m->private;
6703 char expVer[32];
6704 int sz;
6705 int p;
6706
6707 mpt_get_fw_exp_ver(expVer, ioc);
6708
6709 seq_printf(m, "%s:", ioc->name);
6710 if (ioc->facts.Flags & MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT)
6711 seq_printf(m, " (f/w download boot flag set)");
6712// if (ioc->facts.IOCExceptions & MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL)
6713// seq_printf(m, " CONFIG_CHECKSUM_FAIL!");
6714
6715 seq_printf(m, "\n ProductID = 0x%04x (%s)\n",
6716 ioc->facts.ProductID,
6717 ioc->prod_name);
6718 seq_printf(m, " FWVersion = 0x%08x%s", ioc->facts.FWVersion.Word, expVer);
6719 if (ioc->facts.FWImageSize)
6720 seq_printf(m, " (fw_size=%d)", ioc->facts.FWImageSize);
6721 seq_printf(m, "\n MsgVersion = 0x%04x\n", ioc->facts.MsgVersion);
6722 seq_printf(m, " FirstWhoInit = 0x%02x\n", ioc->FirstWhoInit);
6723 seq_printf(m, " EventState = 0x%02x\n", ioc->facts.EventState);
6724
6725 seq_printf(m, " CurrentHostMfaHighAddr = 0x%08x\n",
6726 ioc->facts.CurrentHostMfaHighAddr);
6727 seq_printf(m, " CurrentSenseBufferHighAddr = 0x%08x\n",
6728 ioc->facts.CurrentSenseBufferHighAddr);
6729
6730 seq_printf(m, " MaxChainDepth = 0x%02x frames\n", ioc->facts.MaxChainDepth);
6731 seq_printf(m, " MinBlockSize = 0x%02x bytes\n", 4*ioc->facts.BlockSize);
6732
6733 seq_printf(m, " RequestFrames @ 0x%p (Dma @ 0x%p)\n",
6734 (void *)ioc->req_frames, (void *)(ulong)ioc->req_frames_dma);
6735 /*
6736 * Rounding UP to nearest 4-kB boundary here...
6737 */
6738 sz = (ioc->req_sz * ioc->req_depth) + 128;
6739 sz = ((sz + 0x1000UL - 1UL) / 0x1000) * 0x1000;
6740 seq_printf(m, " {CurReqSz=%d} x {CurReqDepth=%d} = %d bytes ^= 0x%x\n",
6741 ioc->req_sz, ioc->req_depth, ioc->req_sz*ioc->req_depth, sz);
6742 seq_printf(m, " {MaxReqSz=%d} {MaxReqDepth=%d}\n",
6743 4*ioc->facts.RequestFrameSize,
6744 ioc->facts.GlobalCredits);
6745
6746 seq_printf(m, " Frames @ 0x%p (Dma @ 0x%p)\n",
6747 (void *)ioc->alloc, (void *)(ulong)ioc->alloc_dma);
6748 sz = (ioc->reply_sz * ioc->reply_depth) + 128;
6749 seq_printf(m, " {CurRepSz=%d} x {CurRepDepth=%d} = %d bytes ^= 0x%x\n",
6750 ioc->reply_sz, ioc->reply_depth, ioc->reply_sz*ioc->reply_depth, sz);
6751 seq_printf(m, " {MaxRepSz=%d} {MaxRepDepth=%d}\n",
6752 ioc->facts.CurReplyFrameSize,
6753 ioc->facts.ReplyQueueDepth);
6754
6755 seq_printf(m, " MaxDevices = %d\n",
6756 (ioc->facts.MaxDevices==0) ? 255 : ioc->facts.MaxDevices);
6757 seq_printf(m, " MaxBuses = %d\n", ioc->facts.MaxBuses);
6758
6759 /* per-port info */
6760 for (p=0; p < ioc->facts.NumberOfPorts; p++) {
6761 seq_printf(m, " PortNumber = %d (of %d)\n",
6762 p+1,
6763 ioc->facts.NumberOfPorts);
6764 if (ioc->bus_type == FC) {
6765 if (ioc->pfacts[p].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN) {
6766 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
6767 seq_printf(m, " LanAddr = %pMR\n", a);
6768 }
6769 seq_printf(m, " WWN = %08X%08X:%08X%08X\n",
6770 ioc->fc_port_page0[p].WWNN.High,
6771 ioc->fc_port_page0[p].WWNN.Low,
6772 ioc->fc_port_page0[p].WWPN.High,
6773 ioc->fc_port_page0[p].WWPN.Low);
6774 }
6775 }
6776
6777 return 0;
6778}
6779#endif /* CONFIG_PROC_FS } */
6780
6781/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6782static void
6783mpt_get_fw_exp_ver(char *buf, MPT_ADAPTER *ioc)
6784{
6785 buf[0] ='\0';
6786 if ((ioc->facts.FWVersion.Word >> 24) == 0x0E) {
6787 sprintf(buf, " (Exp %02d%02d)",
6788 (ioc->facts.FWVersion.Word >> 16) & 0x00FF, /* Month */
6789 (ioc->facts.FWVersion.Word >> 8) & 0x1F); /* Day */
6790
6791 /* insider hack! */
6792 if ((ioc->facts.FWVersion.Word >> 8) & 0x80)
6793 strcat(buf, " [MDBG]");
6794 }
6795}
6796
6797/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
6798/**
6799 * mpt_print_ioc_summary - Write ASCII summary of IOC to a buffer.
6800 * @ioc: Pointer to MPT_ADAPTER structure
6801 * @buffer: Pointer to buffer where IOC summary info should be written
6802 * @size: Pointer to number of bytes we wrote (set by this routine)
6803 * @len: Offset at which to start writing in buffer
6804 * @showlan: Display LAN stuff?
6805 *
6806 * This routine writes (english readable) ASCII text, which represents
6807 * a summary of IOC information, to a buffer.
6808 */
6809void
6810mpt_print_ioc_summary(MPT_ADAPTER *ioc, char *buffer, int *size, int len, int showlan)
6811{
6812 char expVer[32];
6813 int y;
6814
6815 mpt_get_fw_exp_ver(expVer, ioc);
6816
6817 /*
6818 * Shorter summary of attached ioc's...
6819 */
6820 y = sprintf(buffer+len, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d",
6821 ioc->name,
6822 ioc->prod_name,
6823 MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */
6824 ioc->facts.FWVersion.Word,
6825 expVer,
6826 ioc->facts.NumberOfPorts,
6827 ioc->req_depth);
6828
6829 if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) {
6830 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
6831 y += sprintf(buffer+len+y, ", LanAddr=%pMR", a);
6832 }
6833
6834 y += sprintf(buffer+len+y, ", IRQ=%d", ioc->pci_irq);
6835
6836 if (!ioc->active)
6837 y += sprintf(buffer+len+y, " (disabled)");
6838
6839 y += sprintf(buffer+len+y, "\n");
6840
6841 *size = y;
6842}
6843
6844#ifdef CONFIG_PROC_FS
6845static void seq_mpt_print_ioc_summary(MPT_ADAPTER *ioc, struct seq_file *m, int showlan)
6846{
6847 char expVer[32];
6848
6849 mpt_get_fw_exp_ver(expVer, ioc);
6850
6851 /*
6852 * Shorter summary of attached ioc's...
6853 */
6854 seq_printf(m, "%s: %s, %s%08xh%s, Ports=%d, MaxQ=%d",
6855 ioc->name,
6856 ioc->prod_name,
6857 MPT_FW_REV_MAGIC_ID_STRING, /* "FwRev=" or somesuch */
6858 ioc->facts.FWVersion.Word,
6859 expVer,
6860 ioc->facts.NumberOfPorts,
6861 ioc->req_depth);
6862
6863 if (showlan && (ioc->pfacts[0].ProtocolFlags & MPI_PORTFACTS_PROTOCOL_LAN)) {
6864 u8 *a = (u8*)&ioc->lan_cnfg_page1.HardwareAddressLow;
6865 seq_printf(m, ", LanAddr=%pMR", a);
6866 }
6867
6868 seq_printf(m, ", IRQ=%d", ioc->pci_irq);
6869
6870 if (!ioc->active)
6871 seq_printf(m, " (disabled)");
6872
6873 seq_putc(m, '\n');
6874}
6875#endif
6876
6877/**
6878 * mpt_set_taskmgmt_in_progress_flag - set flags associated with task management
6879 * @ioc: Pointer to MPT_ADAPTER structure
6880 *
6881 * Returns 0 for SUCCESS or -1 if FAILED.
6882 *
6883 * If -1 is return, then it was not possible to set the flags
6884 **/
6885int
6886mpt_set_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc)
6887{
6888 unsigned long flags;
6889 int retval;
6890
6891 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6892 if (ioc->ioc_reset_in_progress || ioc->taskmgmt_in_progress ||
6893 (ioc->alt_ioc && ioc->alt_ioc->taskmgmt_in_progress)) {
6894 retval = -1;
6895 goto out;
6896 }
6897 retval = 0;
6898 ioc->taskmgmt_in_progress = 1;
6899 ioc->taskmgmt_quiesce_io = 1;
6900 if (ioc->alt_ioc) {
6901 ioc->alt_ioc->taskmgmt_in_progress = 1;
6902 ioc->alt_ioc->taskmgmt_quiesce_io = 1;
6903 }
6904 out:
6905 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6906 return retval;
6907}
6908EXPORT_SYMBOL(mpt_set_taskmgmt_in_progress_flag);
6909
6910/**
6911 * mpt_clear_taskmgmt_in_progress_flag - clear flags associated with task management
6912 * @ioc: Pointer to MPT_ADAPTER structure
6913 *
6914 **/
6915void
6916mpt_clear_taskmgmt_in_progress_flag(MPT_ADAPTER *ioc)
6917{
6918 unsigned long flags;
6919
6920 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
6921 ioc->taskmgmt_in_progress = 0;
6922 ioc->taskmgmt_quiesce_io = 0;
6923 if (ioc->alt_ioc) {
6924 ioc->alt_ioc->taskmgmt_in_progress = 0;
6925 ioc->alt_ioc->taskmgmt_quiesce_io = 0;
6926 }
6927 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
6928}
6929EXPORT_SYMBOL(mpt_clear_taskmgmt_in_progress_flag);
6930
6931
6932/**
6933 * mpt_halt_firmware - Halts the firmware if it is operational and panic
6934 * the kernel
6935 * @ioc: Pointer to MPT_ADAPTER structure
6936 *
6937 **/
6938void __noreturn
6939mpt_halt_firmware(MPT_ADAPTER *ioc)
6940{
6941 u32 ioc_raw_state;
6942
6943 ioc_raw_state = mpt_GetIocState(ioc, 0);
6944
6945 if ((ioc_raw_state & MPI_IOC_STATE_MASK) == MPI_IOC_STATE_FAULT) {
6946 printk(MYIOC_s_ERR_FMT "IOC is in FAULT state (%04xh)!!!\n",
6947 ioc->name, ioc_raw_state & MPI_DOORBELL_DATA_MASK);
6948 panic("%s: IOC Fault (%04xh)!!!\n", ioc->name,
6949 ioc_raw_state & MPI_DOORBELL_DATA_MASK);
6950 } else {
6951 CHIPREG_WRITE32(&ioc->chip->Doorbell, 0xC0FFEE00);
6952 panic("%s: Firmware is halted due to command timeout\n",
6953 ioc->name);
6954 }
6955}
6956EXPORT_SYMBOL(mpt_halt_firmware);
6957
6958/**
6959 * mpt_SoftResetHandler - Issues a less expensive reset
6960 * @ioc: Pointer to MPT_ADAPTER structure
6961 * @sleepFlag: Indicates if sleep or schedule must be called.
6962 *
6963 * Returns 0 for SUCCESS or -1 if FAILED.
6964 *
6965 * Message Unit Reset - instructs the IOC to reset the Reply Post and
6966 * Free FIFO's. All the Message Frames on Reply Free FIFO are discarded.
6967 * All posted buffers are freed, and event notification is turned off.
6968 * IOC doesn't reply to any outstanding request. This will transfer IOC
6969 * to READY state.
6970 **/
6971static int
6972mpt_SoftResetHandler(MPT_ADAPTER *ioc, int sleepFlag)
6973{
6974 int rc;
6975 int ii;
6976 u8 cb_idx;
6977 unsigned long flags;
6978 u32 ioc_state;
6979 unsigned long time_count;
6980
6981 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SoftResetHandler Entered!\n",
6982 ioc->name));
6983
6984 ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK;
6985
6986 if (mpt_fwfault_debug)
6987 mpt_halt_firmware(ioc);
6988
6989 if (ioc_state == MPI_IOC_STATE_FAULT ||
6990 ioc_state == MPI_IOC_STATE_RESET) {
6991 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6992 "skipping, either in FAULT or RESET state!\n", ioc->name));
6993 return -1;
6994 }
6995
6996 if (ioc->bus_type == FC) {
6997 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
6998 "skipping, because the bus type is FC!\n", ioc->name));
6999 return -1;
7000 }
7001
7002 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7003 if (ioc->ioc_reset_in_progress) {
7004 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7005 return -1;
7006 }
7007 ioc->ioc_reset_in_progress = 1;
7008 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7009
7010 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7011 if (MptResetHandlers[cb_idx])
7012 mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET);
7013 }
7014
7015 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7016 if (ioc->taskmgmt_in_progress) {
7017 ioc->ioc_reset_in_progress = 0;
7018 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7019 return -1;
7020 }
7021 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7022 /* Disable reply interrupts (also blocks FreeQ) */
7023 CHIPREG_WRITE32(&ioc->chip->IntMask, 0xFFFFFFFF);
7024 ioc->active = 0;
7025 time_count = jiffies;
7026
7027 rc = SendIocReset(ioc, MPI_FUNCTION_IOC_MESSAGE_UNIT_RESET, sleepFlag);
7028
7029 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7030 if (MptResetHandlers[cb_idx])
7031 mpt_signal_reset(cb_idx, ioc, MPT_IOC_PRE_RESET);
7032 }
7033
7034 if (rc)
7035 goto out;
7036
7037 ioc_state = mpt_GetIocState(ioc, 0) & MPI_IOC_STATE_MASK;
7038 if (ioc_state != MPI_IOC_STATE_READY)
7039 goto out;
7040
7041 for (ii = 0; ii < 5; ii++) {
7042 /* Get IOC facts! Allow 5 retries */
7043 rc = GetIocFacts(ioc, sleepFlag,
7044 MPT_HOSTEVENT_IOC_RECOVER);
7045 if (rc == 0)
7046 break;
7047 if (sleepFlag == CAN_SLEEP)
7048 msleep(100);
7049 else
7050 mdelay(100);
7051 }
7052 if (ii == 5)
7053 goto out;
7054
7055 rc = PrimeIocFifos(ioc);
7056 if (rc != 0)
7057 goto out;
7058
7059 rc = SendIocInit(ioc, sleepFlag);
7060 if (rc != 0)
7061 goto out;
7062
7063 rc = SendEventNotification(ioc, 1, sleepFlag);
7064 if (rc != 0)
7065 goto out;
7066
7067 if (ioc->hard_resets < -1)
7068 ioc->hard_resets++;
7069
7070 /*
7071 * At this point, we know soft reset succeeded.
7072 */
7073
7074 ioc->active = 1;
7075 CHIPREG_WRITE32(&ioc->chip->IntMask, MPI_HIM_DIM);
7076
7077 out:
7078 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7079 ioc->ioc_reset_in_progress = 0;
7080 ioc->taskmgmt_quiesce_io = 0;
7081 ioc->taskmgmt_in_progress = 0;
7082 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7083
7084 if (ioc->active) { /* otherwise, hard reset coming */
7085 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7086 if (MptResetHandlers[cb_idx])
7087 mpt_signal_reset(cb_idx, ioc,
7088 MPT_IOC_POST_RESET);
7089 }
7090 }
7091
7092 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7093 "SoftResetHandler: completed (%d seconds): %s\n",
7094 ioc->name, jiffies_to_msecs(jiffies - time_count)/1000,
7095 ((rc == 0) ? "SUCCESS" : "FAILED")));
7096
7097 return rc;
7098}
7099
7100/**
7101 * mpt_Soft_Hard_ResetHandler - Try less expensive reset
7102 * @ioc: Pointer to MPT_ADAPTER structure
7103 * @sleepFlag: Indicates if sleep or schedule must be called.
7104 *
7105 * Returns 0 for SUCCESS or -1 if FAILED.
7106 * Try for softreset first, only if it fails go for expensive
7107 * HardReset.
7108 **/
7109int
7110mpt_Soft_Hard_ResetHandler(MPT_ADAPTER *ioc, int sleepFlag) {
7111 int ret = -1;
7112
7113 ret = mpt_SoftResetHandler(ioc, sleepFlag);
7114 if (ret == 0)
7115 return ret;
7116 ret = mpt_HardResetHandler(ioc, sleepFlag);
7117 return ret;
7118}
7119EXPORT_SYMBOL(mpt_Soft_Hard_ResetHandler);
7120
7121/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7122/*
7123 * Reset Handling
7124 */
7125/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7126/**
7127 * mpt_HardResetHandler - Generic reset handler
7128 * @ioc: Pointer to MPT_ADAPTER structure
7129 * @sleepFlag: Indicates if sleep or schedule must be called.
7130 *
7131 * Issues SCSI Task Management call based on input arg values.
7132 * If TaskMgmt fails, returns associated SCSI request.
7133 *
7134 * Remark: _HardResetHandler can be invoked from an interrupt thread (timer)
7135 * or a non-interrupt thread. In the former, must not call schedule().
7136 *
7137 * Note: A return of -1 is a FATAL error case, as it means a
7138 * FW reload/initialization failed.
7139 *
7140 * Returns 0 for SUCCESS or -1 if FAILED.
7141 */
7142int
7143mpt_HardResetHandler(MPT_ADAPTER *ioc, int sleepFlag)
7144{
7145 int rc;
7146 u8 cb_idx;
7147 unsigned long flags;
7148 unsigned long time_count;
7149
7150 dtmprintk(ioc, printk(MYIOC_s_DEBUG_FMT "HardResetHandler Entered!\n", ioc->name));
7151#ifdef MFCNT
7152 printk(MYIOC_s_INFO_FMT "HardResetHandler Entered!\n", ioc->name);
7153 printk("MF count 0x%x !\n", ioc->mfcnt);
7154#endif
7155 if (mpt_fwfault_debug)
7156 mpt_halt_firmware(ioc);
7157
7158 /* Reset the adapter. Prevent more than 1 call to
7159 * mpt_do_ioc_recovery at any instant in time.
7160 */
7161 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7162 if (ioc->ioc_reset_in_progress) {
7163 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7164 ioc->wait_on_reset_completion = 1;
7165 do {
7166 ssleep(1);
7167 } while (ioc->ioc_reset_in_progress == 1);
7168 ioc->wait_on_reset_completion = 0;
7169 return ioc->reset_status;
7170 }
7171 if (ioc->wait_on_reset_completion) {
7172 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7173 rc = 0;
7174 time_count = jiffies;
7175 goto exit;
7176 }
7177 ioc->ioc_reset_in_progress = 1;
7178 if (ioc->alt_ioc)
7179 ioc->alt_ioc->ioc_reset_in_progress = 1;
7180 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7181
7182
7183 /* The SCSI driver needs to adjust timeouts on all current
7184 * commands prior to the diagnostic reset being issued.
7185 * Prevents timeouts occurring during a diagnostic reset...very bad.
7186 * For all other protocol drivers, this is a no-op.
7187 */
7188 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7189 if (MptResetHandlers[cb_idx]) {
7190 mpt_signal_reset(cb_idx, ioc, MPT_IOC_SETUP_RESET);
7191 if (ioc->alt_ioc)
7192 mpt_signal_reset(cb_idx, ioc->alt_ioc,
7193 MPT_IOC_SETUP_RESET);
7194 }
7195 }
7196
7197 time_count = jiffies;
7198 rc = mpt_do_ioc_recovery(ioc, MPT_HOSTEVENT_IOC_RECOVER, sleepFlag);
7199 if (rc != 0) {
7200 printk(KERN_WARNING MYNAM
7201 ": WARNING - (%d) Cannot recover %s, doorbell=0x%08x\n",
7202 rc, ioc->name, mpt_GetIocState(ioc, 0));
7203 } else {
7204 if (ioc->hard_resets < -1)
7205 ioc->hard_resets++;
7206 }
7207
7208 spin_lock_irqsave(&ioc->taskmgmt_lock, flags);
7209 ioc->ioc_reset_in_progress = 0;
7210 ioc->taskmgmt_quiesce_io = 0;
7211 ioc->taskmgmt_in_progress = 0;
7212 ioc->reset_status = rc;
7213 if (ioc->alt_ioc) {
7214 ioc->alt_ioc->ioc_reset_in_progress = 0;
7215 ioc->alt_ioc->taskmgmt_quiesce_io = 0;
7216 ioc->alt_ioc->taskmgmt_in_progress = 0;
7217 }
7218 spin_unlock_irqrestore(&ioc->taskmgmt_lock, flags);
7219
7220 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7221 if (MptResetHandlers[cb_idx]) {
7222 mpt_signal_reset(cb_idx, ioc, MPT_IOC_POST_RESET);
7223 if (ioc->alt_ioc)
7224 mpt_signal_reset(cb_idx,
7225 ioc->alt_ioc, MPT_IOC_POST_RESET);
7226 }
7227 }
7228exit:
7229 dtmprintk(ioc,
7230 printk(MYIOC_s_DEBUG_FMT
7231 "HardResetHandler: completed (%d seconds): %s\n", ioc->name,
7232 jiffies_to_msecs(jiffies - time_count)/1000, ((rc == 0) ?
7233 "SUCCESS" : "FAILED")));
7234
7235 return rc;
7236}
7237
7238#ifdef CONFIG_FUSION_LOGGING
7239static void
7240mpt_display_event_info(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply)
7241{
7242 char *ds = NULL;
7243 u32 evData0;
7244 int ii;
7245 u8 event;
7246 char *evStr = ioc->evStr;
7247
7248 event = le32_to_cpu(pEventReply->Event) & 0xFF;
7249 evData0 = le32_to_cpu(pEventReply->Data[0]);
7250
7251 switch(event) {
7252 case MPI_EVENT_NONE:
7253 ds = "None";
7254 break;
7255 case MPI_EVENT_LOG_DATA:
7256 ds = "Log Data";
7257 break;
7258 case MPI_EVENT_STATE_CHANGE:
7259 ds = "State Change";
7260 break;
7261 case MPI_EVENT_UNIT_ATTENTION:
7262 ds = "Unit Attention";
7263 break;
7264 case MPI_EVENT_IOC_BUS_RESET:
7265 ds = "IOC Bus Reset";
7266 break;
7267 case MPI_EVENT_EXT_BUS_RESET:
7268 ds = "External Bus Reset";
7269 break;
7270 case MPI_EVENT_RESCAN:
7271 ds = "Bus Rescan Event";
7272 break;
7273 case MPI_EVENT_LINK_STATUS_CHANGE:
7274 if (evData0 == MPI_EVENT_LINK_STATUS_FAILURE)
7275 ds = "Link Status(FAILURE) Change";
7276 else
7277 ds = "Link Status(ACTIVE) Change";
7278 break;
7279 case MPI_EVENT_LOOP_STATE_CHANGE:
7280 if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LIP)
7281 ds = "Loop State(LIP) Change";
7282 else if (evData0 == MPI_EVENT_LOOP_STATE_CHANGE_LPE)
7283 ds = "Loop State(LPE) Change";
7284 else
7285 ds = "Loop State(LPB) Change";
7286 break;
7287 case MPI_EVENT_LOGOUT:
7288 ds = "Logout";
7289 break;
7290 case MPI_EVENT_EVENT_CHANGE:
7291 if (evData0)
7292 ds = "Events ON";
7293 else
7294 ds = "Events OFF";
7295 break;
7296 case MPI_EVENT_INTEGRATED_RAID:
7297 {
7298 u8 ReasonCode = (u8)(evData0 >> 16);
7299 switch (ReasonCode) {
7300 case MPI_EVENT_RAID_RC_VOLUME_CREATED :
7301 ds = "Integrated Raid: Volume Created";
7302 break;
7303 case MPI_EVENT_RAID_RC_VOLUME_DELETED :
7304 ds = "Integrated Raid: Volume Deleted";
7305 break;
7306 case MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED :
7307 ds = "Integrated Raid: Volume Settings Changed";
7308 break;
7309 case MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED :
7310 ds = "Integrated Raid: Volume Status Changed";
7311 break;
7312 case MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED :
7313 ds = "Integrated Raid: Volume Physdisk Changed";
7314 break;
7315 case MPI_EVENT_RAID_RC_PHYSDISK_CREATED :
7316 ds = "Integrated Raid: Physdisk Created";
7317 break;
7318 case MPI_EVENT_RAID_RC_PHYSDISK_DELETED :
7319 ds = "Integrated Raid: Physdisk Deleted";
7320 break;
7321 case MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED :
7322 ds = "Integrated Raid: Physdisk Settings Changed";
7323 break;
7324 case MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED :
7325 ds = "Integrated Raid: Physdisk Status Changed";
7326 break;
7327 case MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED :
7328 ds = "Integrated Raid: Domain Validation Needed";
7329 break;
7330 case MPI_EVENT_RAID_RC_SMART_DATA :
7331 ds = "Integrated Raid; Smart Data";
7332 break;
7333 case MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED :
7334 ds = "Integrated Raid: Replace Action Started";
7335 break;
7336 default:
7337 ds = "Integrated Raid";
7338 break;
7339 }
7340 break;
7341 }
7342 case MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE:
7343 ds = "SCSI Device Status Change";
7344 break;
7345 case MPI_EVENT_SAS_DEVICE_STATUS_CHANGE:
7346 {
7347 u8 id = (u8)(evData0);
7348 u8 channel = (u8)(evData0 >> 8);
7349 u8 ReasonCode = (u8)(evData0 >> 16);
7350 switch (ReasonCode) {
7351 case MPI_EVENT_SAS_DEV_STAT_RC_ADDED:
7352 snprintf(evStr, EVENT_DESCR_STR_SZ,
7353 "SAS Device Status Change: Added: "
7354 "id=%d channel=%d", id, channel);
7355 break;
7356 case MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING:
7357 snprintf(evStr, EVENT_DESCR_STR_SZ,
7358 "SAS Device Status Change: Deleted: "
7359 "id=%d channel=%d", id, channel);
7360 break;
7361 case MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA:
7362 snprintf(evStr, EVENT_DESCR_STR_SZ,
7363 "SAS Device Status Change: SMART Data: "
7364 "id=%d channel=%d", id, channel);
7365 break;
7366 case MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED:
7367 snprintf(evStr, EVENT_DESCR_STR_SZ,
7368 "SAS Device Status Change: No Persistency: "
7369 "id=%d channel=%d", id, channel);
7370 break;
7371 case MPI_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED:
7372 snprintf(evStr, EVENT_DESCR_STR_SZ,
7373 "SAS Device Status Change: Unsupported Device "
7374 "Discovered : id=%d channel=%d", id, channel);
7375 break;
7376 case MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET:
7377 snprintf(evStr, EVENT_DESCR_STR_SZ,
7378 "SAS Device Status Change: Internal Device "
7379 "Reset : id=%d channel=%d", id, channel);
7380 break;
7381 case MPI_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL:
7382 snprintf(evStr, EVENT_DESCR_STR_SZ,
7383 "SAS Device Status Change: Internal Task "
7384 "Abort : id=%d channel=%d", id, channel);
7385 break;
7386 case MPI_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL:
7387 snprintf(evStr, EVENT_DESCR_STR_SZ,
7388 "SAS Device Status Change: Internal Abort "
7389 "Task Set : id=%d channel=%d", id, channel);
7390 break;
7391 case MPI_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL:
7392 snprintf(evStr, EVENT_DESCR_STR_SZ,
7393 "SAS Device Status Change: Internal Clear "
7394 "Task Set : id=%d channel=%d", id, channel);
7395 break;
7396 case MPI_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL:
7397 snprintf(evStr, EVENT_DESCR_STR_SZ,
7398 "SAS Device Status Change: Internal Query "
7399 "Task : id=%d channel=%d", id, channel);
7400 break;
7401 default:
7402 snprintf(evStr, EVENT_DESCR_STR_SZ,
7403 "SAS Device Status Change: Unknown: "
7404 "id=%d channel=%d", id, channel);
7405 break;
7406 }
7407 break;
7408 }
7409 case MPI_EVENT_ON_BUS_TIMER_EXPIRED:
7410 ds = "Bus Timer Expired";
7411 break;
7412 case MPI_EVENT_QUEUE_FULL:
7413 {
7414 u16 curr_depth = (u16)(evData0 >> 16);
7415 u8 channel = (u8)(evData0 >> 8);
7416 u8 id = (u8)(evData0);
7417
7418 snprintf(evStr, EVENT_DESCR_STR_SZ,
7419 "Queue Full: channel=%d id=%d depth=%d",
7420 channel, id, curr_depth);
7421 break;
7422 }
7423 case MPI_EVENT_SAS_SES:
7424 ds = "SAS SES Event";
7425 break;
7426 case MPI_EVENT_PERSISTENT_TABLE_FULL:
7427 ds = "Persistent Table Full";
7428 break;
7429 case MPI_EVENT_SAS_PHY_LINK_STATUS:
7430 {
7431 u8 LinkRates = (u8)(evData0 >> 8);
7432 u8 PhyNumber = (u8)(evData0);
7433 LinkRates = (LinkRates & MPI_EVENT_SAS_PLS_LR_CURRENT_MASK) >>
7434 MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT;
7435 switch (LinkRates) {
7436 case MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN:
7437 snprintf(evStr, EVENT_DESCR_STR_SZ,
7438 "SAS PHY Link Status: Phy=%d:"
7439 " Rate Unknown",PhyNumber);
7440 break;
7441 case MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED:
7442 snprintf(evStr, EVENT_DESCR_STR_SZ,
7443 "SAS PHY Link Status: Phy=%d:"
7444 " Phy Disabled",PhyNumber);
7445 break;
7446 case MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION:
7447 snprintf(evStr, EVENT_DESCR_STR_SZ,
7448 "SAS PHY Link Status: Phy=%d:"
7449 " Failed Speed Nego",PhyNumber);
7450 break;
7451 case MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE:
7452 snprintf(evStr, EVENT_DESCR_STR_SZ,
7453 "SAS PHY Link Status: Phy=%d:"
7454 " Sata OOB Completed",PhyNumber);
7455 break;
7456 case MPI_EVENT_SAS_PLS_LR_RATE_1_5:
7457 snprintf(evStr, EVENT_DESCR_STR_SZ,
7458 "SAS PHY Link Status: Phy=%d:"
7459 " Rate 1.5 Gbps",PhyNumber);
7460 break;
7461 case MPI_EVENT_SAS_PLS_LR_RATE_3_0:
7462 snprintf(evStr, EVENT_DESCR_STR_SZ,
7463 "SAS PHY Link Status: Phy=%d:"
7464 " Rate 3.0 Gbps", PhyNumber);
7465 break;
7466 case MPI_EVENT_SAS_PLS_LR_RATE_6_0:
7467 snprintf(evStr, EVENT_DESCR_STR_SZ,
7468 "SAS PHY Link Status: Phy=%d:"
7469 " Rate 6.0 Gbps", PhyNumber);
7470 break;
7471 default:
7472 snprintf(evStr, EVENT_DESCR_STR_SZ,
7473 "SAS PHY Link Status: Phy=%d", PhyNumber);
7474 break;
7475 }
7476 break;
7477 }
7478 case MPI_EVENT_SAS_DISCOVERY_ERROR:
7479 ds = "SAS Discovery Error";
7480 break;
7481 case MPI_EVENT_IR_RESYNC_UPDATE:
7482 {
7483 u8 resync_complete = (u8)(evData0 >> 16);
7484 snprintf(evStr, EVENT_DESCR_STR_SZ,
7485 "IR Resync Update: Complete = %d:",resync_complete);
7486 break;
7487 }
7488 case MPI_EVENT_IR2:
7489 {
7490 u8 id = (u8)(evData0);
7491 u8 channel = (u8)(evData0 >> 8);
7492 u8 phys_num = (u8)(evData0 >> 24);
7493 u8 ReasonCode = (u8)(evData0 >> 16);
7494
7495 switch (ReasonCode) {
7496 case MPI_EVENT_IR2_RC_LD_STATE_CHANGED:
7497 snprintf(evStr, EVENT_DESCR_STR_SZ,
7498 "IR2: LD State Changed: "
7499 "id=%d channel=%d phys_num=%d",
7500 id, channel, phys_num);
7501 break;
7502 case MPI_EVENT_IR2_RC_PD_STATE_CHANGED:
7503 snprintf(evStr, EVENT_DESCR_STR_SZ,
7504 "IR2: PD State Changed "
7505 "id=%d channel=%d phys_num=%d",
7506 id, channel, phys_num);
7507 break;
7508 case MPI_EVENT_IR2_RC_BAD_BLOCK_TABLE_FULL:
7509 snprintf(evStr, EVENT_DESCR_STR_SZ,
7510 "IR2: Bad Block Table Full: "
7511 "id=%d channel=%d phys_num=%d",
7512 id, channel, phys_num);
7513 break;
7514 case MPI_EVENT_IR2_RC_PD_INSERTED:
7515 snprintf(evStr, EVENT_DESCR_STR_SZ,
7516 "IR2: PD Inserted: "
7517 "id=%d channel=%d phys_num=%d",
7518 id, channel, phys_num);
7519 break;
7520 case MPI_EVENT_IR2_RC_PD_REMOVED:
7521 snprintf(evStr, EVENT_DESCR_STR_SZ,
7522 "IR2: PD Removed: "
7523 "id=%d channel=%d phys_num=%d",
7524 id, channel, phys_num);
7525 break;
7526 case MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED:
7527 snprintf(evStr, EVENT_DESCR_STR_SZ,
7528 "IR2: Foreign CFG Detected: "
7529 "id=%d channel=%d phys_num=%d",
7530 id, channel, phys_num);
7531 break;
7532 case MPI_EVENT_IR2_RC_REBUILD_MEDIUM_ERROR:
7533 snprintf(evStr, EVENT_DESCR_STR_SZ,
7534 "IR2: Rebuild Medium Error: "
7535 "id=%d channel=%d phys_num=%d",
7536 id, channel, phys_num);
7537 break;
7538 case MPI_EVENT_IR2_RC_DUAL_PORT_ADDED:
7539 snprintf(evStr, EVENT_DESCR_STR_SZ,
7540 "IR2: Dual Port Added: "
7541 "id=%d channel=%d phys_num=%d",
7542 id, channel, phys_num);
7543 break;
7544 case MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED:
7545 snprintf(evStr, EVENT_DESCR_STR_SZ,
7546 "IR2: Dual Port Removed: "
7547 "id=%d channel=%d phys_num=%d",
7548 id, channel, phys_num);
7549 break;
7550 default:
7551 ds = "IR2";
7552 break;
7553 }
7554 break;
7555 }
7556 case MPI_EVENT_SAS_DISCOVERY:
7557 {
7558 if (evData0)
7559 ds = "SAS Discovery: Start";
7560 else
7561 ds = "SAS Discovery: Stop";
7562 break;
7563 }
7564 case MPI_EVENT_LOG_ENTRY_ADDED:
7565 ds = "SAS Log Entry Added";
7566 break;
7567
7568 case MPI_EVENT_SAS_BROADCAST_PRIMITIVE:
7569 {
7570 u8 phy_num = (u8)(evData0);
7571 u8 port_num = (u8)(evData0 >> 8);
7572 u8 port_width = (u8)(evData0 >> 16);
7573 u8 primitive = (u8)(evData0 >> 24);
7574 snprintf(evStr, EVENT_DESCR_STR_SZ,
7575 "SAS Broadcast Primitive: phy=%d port=%d "
7576 "width=%d primitive=0x%02x",
7577 phy_num, port_num, port_width, primitive);
7578 break;
7579 }
7580
7581 case MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
7582 {
7583 u8 reason = (u8)(evData0);
7584
7585 switch (reason) {
7586 case MPI_EVENT_SAS_INIT_RC_ADDED:
7587 ds = "SAS Initiator Status Change: Added";
7588 break;
7589 case MPI_EVENT_SAS_INIT_RC_REMOVED:
7590 ds = "SAS Initiator Status Change: Deleted";
7591 break;
7592 default:
7593 ds = "SAS Initiator Status Change";
7594 break;
7595 }
7596 break;
7597 }
7598
7599 case MPI_EVENT_SAS_INIT_TABLE_OVERFLOW:
7600 {
7601 u8 max_init = (u8)(evData0);
7602 u8 current_init = (u8)(evData0 >> 8);
7603
7604 snprintf(evStr, EVENT_DESCR_STR_SZ,
7605 "SAS Initiator Device Table Overflow: max initiators=%02d "
7606 "current initiators=%02d",
7607 max_init, current_init);
7608 break;
7609 }
7610 case MPI_EVENT_SAS_SMP_ERROR:
7611 {
7612 u8 status = (u8)(evData0);
7613 u8 port_num = (u8)(evData0 >> 8);
7614 u8 result = (u8)(evData0 >> 16);
7615
7616 if (status == MPI_EVENT_SAS_SMP_FUNCTION_RESULT_VALID)
7617 snprintf(evStr, EVENT_DESCR_STR_SZ,
7618 "SAS SMP Error: port=%d result=0x%02x",
7619 port_num, result);
7620 else if (status == MPI_EVENT_SAS_SMP_CRC_ERROR)
7621 snprintf(evStr, EVENT_DESCR_STR_SZ,
7622 "SAS SMP Error: port=%d : CRC Error",
7623 port_num);
7624 else if (status == MPI_EVENT_SAS_SMP_TIMEOUT)
7625 snprintf(evStr, EVENT_DESCR_STR_SZ,
7626 "SAS SMP Error: port=%d : Timeout",
7627 port_num);
7628 else if (status == MPI_EVENT_SAS_SMP_NO_DESTINATION)
7629 snprintf(evStr, EVENT_DESCR_STR_SZ,
7630 "SAS SMP Error: port=%d : No Destination",
7631 port_num);
7632 else if (status == MPI_EVENT_SAS_SMP_BAD_DESTINATION)
7633 snprintf(evStr, EVENT_DESCR_STR_SZ,
7634 "SAS SMP Error: port=%d : Bad Destination",
7635 port_num);
7636 else
7637 snprintf(evStr, EVENT_DESCR_STR_SZ,
7638 "SAS SMP Error: port=%d : status=0x%02x",
7639 port_num, status);
7640 break;
7641 }
7642
7643 case MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE:
7644 {
7645 u8 reason = (u8)(evData0);
7646
7647 switch (reason) {
7648 case MPI_EVENT_SAS_EXP_RC_ADDED:
7649 ds = "Expander Status Change: Added";
7650 break;
7651 case MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING:
7652 ds = "Expander Status Change: Deleted";
7653 break;
7654 default:
7655 ds = "Expander Status Change";
7656 break;
7657 }
7658 break;
7659 }
7660
7661 /*
7662 * MPT base "custom" events may be added here...
7663 */
7664 default:
7665 ds = "Unknown";
7666 break;
7667 }
7668 if (ds)
7669 strscpy(evStr, ds, EVENT_DESCR_STR_SZ);
7670
7671
7672 devtprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7673 "MPT event:(%02Xh) : %s\n",
7674 ioc->name, event, evStr));
7675
7676 devtverboseprintk(ioc, printk(KERN_DEBUG MYNAM
7677 ": Event data:\n"));
7678 for (ii = 0; ii < le16_to_cpu(pEventReply->EventDataLength); ii++)
7679 devtverboseprintk(ioc, printk(" %08x",
7680 le32_to_cpu(pEventReply->Data[ii])));
7681 devtverboseprintk(ioc, printk(KERN_DEBUG "\n"));
7682}
7683#endif
7684/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7685/**
7686 * ProcessEventNotification - Route EventNotificationReply to all event handlers
7687 * @ioc: Pointer to MPT_ADAPTER structure
7688 * @pEventReply: Pointer to EventNotification reply frame
7689 * @evHandlers: Pointer to integer, number of event handlers
7690 *
7691 * Routes a received EventNotificationReply to all currently registered
7692 * event handlers.
7693 * Returns sum of event handlers return values.
7694 */
7695static int
7696ProcessEventNotification(MPT_ADAPTER *ioc, EventNotificationReply_t *pEventReply, int *evHandlers)
7697{
7698 u16 evDataLen;
7699 u32 evData0 = 0;
7700 int ii;
7701 u8 cb_idx;
7702 int r = 0;
7703 int handlers = 0;
7704 u8 event;
7705
7706 /*
7707 * Do platform normalization of values
7708 */
7709 event = le32_to_cpu(pEventReply->Event) & 0xFF;
7710 evDataLen = le16_to_cpu(pEventReply->EventDataLength);
7711 if (evDataLen) {
7712 evData0 = le32_to_cpu(pEventReply->Data[0]);
7713 }
7714
7715#ifdef CONFIG_FUSION_LOGGING
7716 if (evDataLen)
7717 mpt_display_event_info(ioc, pEventReply);
7718#endif
7719
7720 /*
7721 * Do general / base driver event processing
7722 */
7723 switch(event) {
7724 case MPI_EVENT_EVENT_CHANGE: /* 0A */
7725 if (evDataLen) {
7726 u8 evState = evData0 & 0xFF;
7727
7728 /* CHECKME! What if evState unexpectedly says OFF (0)? */
7729
7730 /* Update EventState field in cached IocFacts */
7731 if (ioc->facts.Function) {
7732 ioc->facts.EventState = evState;
7733 }
7734 }
7735 break;
7736 case MPI_EVENT_INTEGRATED_RAID:
7737 mptbase_raid_process_event_data(ioc,
7738 (MpiEventDataRaid_t *)pEventReply->Data);
7739 break;
7740 default:
7741 break;
7742 }
7743
7744 /*
7745 * Should this event be logged? Events are written sequentially.
7746 * When buffer is full, start again at the top.
7747 */
7748 if (ioc->events && (ioc->eventTypes & ( 1 << event))) {
7749 int idx;
7750
7751 idx = ioc->eventContext % MPTCTL_EVENT_LOG_SIZE;
7752
7753 ioc->events[idx].event = event;
7754 ioc->events[idx].eventContext = ioc->eventContext;
7755
7756 for (ii = 0; ii < 2; ii++) {
7757 if (ii < evDataLen)
7758 ioc->events[idx].data[ii] = le32_to_cpu(pEventReply->Data[ii]);
7759 else
7760 ioc->events[idx].data[ii] = 0;
7761 }
7762
7763 ioc->eventContext++;
7764 }
7765
7766
7767 /*
7768 * Call each currently registered protocol event handler.
7769 */
7770 for (cb_idx = MPT_MAX_PROTOCOL_DRIVERS-1; cb_idx; cb_idx--) {
7771 if (MptEvHandlers[cb_idx]) {
7772 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7773 "Routing Event to event handler #%d\n",
7774 ioc->name, cb_idx));
7775 r += (*(MptEvHandlers[cb_idx]))(ioc, pEventReply);
7776 handlers++;
7777 }
7778 }
7779 /* FIXME? Examine results here? */
7780
7781 /*
7782 * If needed, send (a single) EventAck.
7783 */
7784 if (pEventReply->AckRequired == MPI_EVENT_NOTIFICATION_ACK_REQUIRED) {
7785 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT
7786 "EventAck required\n",ioc->name));
7787 if ((ii = SendEventAck(ioc, pEventReply)) != 0) {
7788 devtverboseprintk(ioc, printk(MYIOC_s_DEBUG_FMT "SendEventAck returned %d\n",
7789 ioc->name, ii));
7790 }
7791 }
7792
7793 *evHandlers = handlers;
7794 return r;
7795}
7796
7797/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7798/**
7799 * mpt_fc_log_info - Log information returned from Fibre Channel IOC.
7800 * @ioc: Pointer to MPT_ADAPTER structure
7801 * @log_info: U32 LogInfo reply word from the IOC
7802 *
7803 * Refer to lsi/mpi_log_fc.h.
7804 */
7805static void
7806mpt_fc_log_info(MPT_ADAPTER *ioc, u32 log_info)
7807{
7808 char *desc = "unknown";
7809
7810 switch (log_info & 0xFF000000) {
7811 case MPI_IOCLOGINFO_FC_INIT_BASE:
7812 desc = "FCP Initiator";
7813 break;
7814 case MPI_IOCLOGINFO_FC_TARGET_BASE:
7815 desc = "FCP Target";
7816 break;
7817 case MPI_IOCLOGINFO_FC_LAN_BASE:
7818 desc = "LAN";
7819 break;
7820 case MPI_IOCLOGINFO_FC_MSG_BASE:
7821 desc = "MPI Message Layer";
7822 break;
7823 case MPI_IOCLOGINFO_FC_LINK_BASE:
7824 desc = "FC Link";
7825 break;
7826 case MPI_IOCLOGINFO_FC_CTX_BASE:
7827 desc = "Context Manager";
7828 break;
7829 case MPI_IOCLOGINFO_FC_INVALID_FIELD_BYTE_OFFSET:
7830 desc = "Invalid Field Offset";
7831 break;
7832 case MPI_IOCLOGINFO_FC_STATE_CHANGE:
7833 desc = "State Change Info";
7834 break;
7835 }
7836
7837 printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): SubClass={%s}, Value=(0x%06x)\n",
7838 ioc->name, log_info, desc, (log_info & 0xFFFFFF));
7839}
7840
7841/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
7842/**
7843 * mpt_spi_log_info - Log information returned from SCSI Parallel IOC.
7844 * @ioc: Pointer to MPT_ADAPTER structure
7845 * @log_info: U32 LogInfo word from the IOC
7846 *
7847 * Refer to lsi/sp_log.h.
7848 */
7849static void
7850mpt_spi_log_info(MPT_ADAPTER *ioc, u32 log_info)
7851{
7852 u32 info = log_info & 0x00FF0000;
7853 char *desc = "unknown";
7854
7855 switch (info) {
7856 case 0x00010000:
7857 desc = "bug! MID not found";
7858 break;
7859
7860 case 0x00020000:
7861 desc = "Parity Error";
7862 break;
7863
7864 case 0x00030000:
7865 desc = "ASYNC Outbound Overrun";
7866 break;
7867
7868 case 0x00040000:
7869 desc = "SYNC Offset Error";
7870 break;
7871
7872 case 0x00050000:
7873 desc = "BM Change";
7874 break;
7875
7876 case 0x00060000:
7877 desc = "Msg In Overflow";
7878 break;
7879
7880 case 0x00070000:
7881 desc = "DMA Error";
7882 break;
7883
7884 case 0x00080000:
7885 desc = "Outbound DMA Overrun";
7886 break;
7887
7888 case 0x00090000:
7889 desc = "Task Management";
7890 break;
7891
7892 case 0x000A0000:
7893 desc = "Device Problem";
7894 break;
7895
7896 case 0x000B0000:
7897 desc = "Invalid Phase Change";
7898 break;
7899
7900 case 0x000C0000:
7901 desc = "Untagged Table Size";
7902 break;
7903
7904 }
7905
7906 printk(MYIOC_s_INFO_FMT "LogInfo(0x%08x): F/W: %s\n", ioc->name, log_info, desc);
7907}
7908
7909/* strings for sas loginfo */
7910 static char *originator_str[] = {
7911 "IOP", /* 00h */
7912 "PL", /* 01h */
7913 "IR" /* 02h */
7914 };
7915 static char *iop_code_str[] = {
7916 NULL, /* 00h */
7917 "Invalid SAS Address", /* 01h */
7918 NULL, /* 02h */
7919 "Invalid Page", /* 03h */
7920 "Diag Message Error", /* 04h */
7921 "Task Terminated", /* 05h */
7922 "Enclosure Management", /* 06h */
7923 "Target Mode" /* 07h */
7924 };
7925 static char *pl_code_str[] = {
7926 NULL, /* 00h */
7927 "Open Failure", /* 01h */
7928 "Invalid Scatter Gather List", /* 02h */
7929 "Wrong Relative Offset or Frame Length", /* 03h */
7930 "Frame Transfer Error", /* 04h */
7931 "Transmit Frame Connected Low", /* 05h */
7932 "SATA Non-NCQ RW Error Bit Set", /* 06h */
7933 "SATA Read Log Receive Data Error", /* 07h */
7934 "SATA NCQ Fail All Commands After Error", /* 08h */
7935 "SATA Error in Receive Set Device Bit FIS", /* 09h */
7936 "Receive Frame Invalid Message", /* 0Ah */
7937 "Receive Context Message Valid Error", /* 0Bh */
7938 "Receive Frame Current Frame Error", /* 0Ch */
7939 "SATA Link Down", /* 0Dh */
7940 "Discovery SATA Init W IOS", /* 0Eh */
7941 "Config Invalid Page", /* 0Fh */
7942 "Discovery SATA Init Timeout", /* 10h */
7943 "Reset", /* 11h */
7944 "Abort", /* 12h */
7945 "IO Not Yet Executed", /* 13h */
7946 "IO Executed", /* 14h */
7947 "Persistent Reservation Out Not Affiliation "
7948 "Owner", /* 15h */
7949 "Open Transmit DMA Abort", /* 16h */
7950 "IO Device Missing Delay Retry", /* 17h */
7951 "IO Cancelled Due to Receive Error", /* 18h */
7952 NULL, /* 19h */
7953 NULL, /* 1Ah */
7954 NULL, /* 1Bh */
7955 NULL, /* 1Ch */
7956 NULL, /* 1Dh */
7957 NULL, /* 1Eh */
7958 NULL, /* 1Fh */
7959 "Enclosure Management" /* 20h */
7960 };
7961 static char *ir_code_str[] = {
7962 "Raid Action Error", /* 00h */
7963 NULL, /* 00h */
7964 NULL, /* 01h */
7965 NULL, /* 02h */
7966 NULL, /* 03h */
7967 NULL, /* 04h */
7968 NULL, /* 05h */
7969 NULL, /* 06h */
7970 NULL /* 07h */
7971 };
7972 static char *raid_sub_code_str[] = {
7973 NULL, /* 00h */
7974 "Volume Creation Failed: Data Passed too "
7975 "Large", /* 01h */
7976 "Volume Creation Failed: Duplicate Volumes "
7977 "Attempted", /* 02h */
7978 "Volume Creation Failed: Max Number "
7979 "Supported Volumes Exceeded", /* 03h */
7980 "Volume Creation Failed: DMA Error", /* 04h */
7981 "Volume Creation Failed: Invalid Volume Type", /* 05h */
7982 "Volume Creation Failed: Error Reading "
7983 "MFG Page 4", /* 06h */
7984 "Volume Creation Failed: Creating Internal "
7985 "Structures", /* 07h */
7986 NULL, /* 08h */
7987 NULL, /* 09h */
7988 NULL, /* 0Ah */
7989 NULL, /* 0Bh */
7990 NULL, /* 0Ch */
7991 NULL, /* 0Dh */
7992 NULL, /* 0Eh */
7993 NULL, /* 0Fh */
7994 "Activation failed: Already Active Volume", /* 10h */
7995 "Activation failed: Unsupported Volume Type", /* 11h */
7996 "Activation failed: Too Many Active Volumes", /* 12h */
7997 "Activation failed: Volume ID in Use", /* 13h */
7998 "Activation failed: Reported Failure", /* 14h */
7999 "Activation failed: Importing a Volume", /* 15h */
8000 NULL, /* 16h */
8001 NULL, /* 17h */
8002 NULL, /* 18h */
8003 NULL, /* 19h */
8004 NULL, /* 1Ah */
8005 NULL, /* 1Bh */
8006 NULL, /* 1Ch */
8007 NULL, /* 1Dh */
8008 NULL, /* 1Eh */
8009 NULL, /* 1Fh */
8010 "Phys Disk failed: Too Many Phys Disks", /* 20h */
8011 "Phys Disk failed: Data Passed too Large", /* 21h */
8012 "Phys Disk failed: DMA Error", /* 22h */
8013 "Phys Disk failed: Invalid <channel:id>", /* 23h */
8014 "Phys Disk failed: Creating Phys Disk Config "
8015 "Page", /* 24h */
8016 NULL, /* 25h */
8017 NULL, /* 26h */
8018 NULL, /* 27h */
8019 NULL, /* 28h */
8020 NULL, /* 29h */
8021 NULL, /* 2Ah */
8022 NULL, /* 2Bh */
8023 NULL, /* 2Ch */
8024 NULL, /* 2Dh */
8025 NULL, /* 2Eh */
8026 NULL, /* 2Fh */
8027 "Compatibility Error: IR Disabled", /* 30h */
8028 "Compatibility Error: Inquiry Command Failed", /* 31h */
8029 "Compatibility Error: Device not Direct Access "
8030 "Device ", /* 32h */
8031 "Compatibility Error: Removable Device Found", /* 33h */
8032 "Compatibility Error: Device SCSI Version not "
8033 "2 or Higher", /* 34h */
8034 "Compatibility Error: SATA Device, 48 BIT LBA "
8035 "not Supported", /* 35h */
8036 "Compatibility Error: Device doesn't have "
8037 "512 Byte Block Sizes", /* 36h */
8038 "Compatibility Error: Volume Type Check Failed", /* 37h */
8039 "Compatibility Error: Volume Type is "
8040 "Unsupported by FW", /* 38h */
8041 "Compatibility Error: Disk Drive too Small for "
8042 "use in Volume", /* 39h */
8043 "Compatibility Error: Phys Disk for Create "
8044 "Volume not Found", /* 3Ah */
8045 "Compatibility Error: Too Many or too Few "
8046 "Disks for Volume Type", /* 3Bh */
8047 "Compatibility Error: Disk stripe Sizes "
8048 "Must be 64KB", /* 3Ch */
8049 "Compatibility Error: IME Size Limited to < 2TB", /* 3Dh */
8050 };
8051
8052/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8053/**
8054 * mpt_sas_log_info - Log information returned from SAS IOC.
8055 * @ioc: Pointer to MPT_ADAPTER structure
8056 * @log_info: U32 LogInfo reply word from the IOC
8057 * @cb_idx: callback function's handle
8058 *
8059 * Refer to lsi/mpi_log_sas.h.
8060 **/
8061static void
8062mpt_sas_log_info(MPT_ADAPTER *ioc, u32 log_info, u8 cb_idx)
8063{
8064 union loginfo_type {
8065 u32 loginfo;
8066 struct {
8067 u32 subcode:16;
8068 u32 code:8;
8069 u32 originator:4;
8070 u32 bus_type:4;
8071 } dw;
8072 };
8073 union loginfo_type sas_loginfo;
8074 char *originator_desc = NULL;
8075 char *code_desc = NULL;
8076 char *sub_code_desc = NULL;
8077
8078 sas_loginfo.loginfo = log_info;
8079 if ((sas_loginfo.dw.bus_type != 3 /*SAS*/) &&
8080 (sas_loginfo.dw.originator < ARRAY_SIZE(originator_str)))
8081 return;
8082
8083 originator_desc = originator_str[sas_loginfo.dw.originator];
8084
8085 switch (sas_loginfo.dw.originator) {
8086
8087 case 0: /* IOP */
8088 if (sas_loginfo.dw.code <
8089 ARRAY_SIZE(iop_code_str))
8090 code_desc = iop_code_str[sas_loginfo.dw.code];
8091 break;
8092 case 1: /* PL */
8093 if (sas_loginfo.dw.code <
8094 ARRAY_SIZE(pl_code_str))
8095 code_desc = pl_code_str[sas_loginfo.dw.code];
8096 break;
8097 case 2: /* IR */
8098 if (sas_loginfo.dw.code >=
8099 ARRAY_SIZE(ir_code_str))
8100 break;
8101 code_desc = ir_code_str[sas_loginfo.dw.code];
8102 if (sas_loginfo.dw.subcode >=
8103 ARRAY_SIZE(raid_sub_code_str))
8104 break;
8105 if (sas_loginfo.dw.code == 0)
8106 sub_code_desc =
8107 raid_sub_code_str[sas_loginfo.dw.subcode];
8108 break;
8109 default:
8110 return;
8111 }
8112
8113 if (sub_code_desc != NULL)
8114 printk(MYIOC_s_INFO_FMT
8115 "LogInfo(0x%08x): Originator={%s}, Code={%s},"
8116 " SubCode={%s} cb_idx %s\n",
8117 ioc->name, log_info, originator_desc, code_desc,
8118 sub_code_desc, MptCallbacksName[cb_idx]);
8119 else if (code_desc != NULL)
8120 printk(MYIOC_s_INFO_FMT
8121 "LogInfo(0x%08x): Originator={%s}, Code={%s},"
8122 " SubCode(0x%04x) cb_idx %s\n",
8123 ioc->name, log_info, originator_desc, code_desc,
8124 sas_loginfo.dw.subcode, MptCallbacksName[cb_idx]);
8125 else
8126 printk(MYIOC_s_INFO_FMT
8127 "LogInfo(0x%08x): Originator={%s}, Code=(0x%02x),"
8128 " SubCode(0x%04x) cb_idx %s\n",
8129 ioc->name, log_info, originator_desc,
8130 sas_loginfo.dw.code, sas_loginfo.dw.subcode,
8131 MptCallbacksName[cb_idx]);
8132}
8133
8134/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8135/**
8136 * mpt_iocstatus_info_config - IOCSTATUS information for config pages
8137 * @ioc: Pointer to MPT_ADAPTER structure
8138 * @ioc_status: U32 IOCStatus word from IOC
8139 * @mf: Pointer to MPT request frame
8140 *
8141 * Refer to lsi/mpi.h.
8142 **/
8143static void
8144mpt_iocstatus_info_config(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf)
8145{
8146 Config_t *pReq = (Config_t *)mf;
8147 char extend_desc[EVENT_DESCR_STR_SZ];
8148 char *desc = NULL;
8149 u32 form;
8150 u8 page_type;
8151
8152 if (pReq->Header.PageType == MPI_CONFIG_PAGETYPE_EXTENDED)
8153 page_type = pReq->ExtPageType;
8154 else
8155 page_type = pReq->Header.PageType;
8156
8157 /*
8158 * ignore invalid page messages for GET_NEXT_HANDLE
8159 */
8160 form = le32_to_cpu(pReq->PageAddress);
8161 if (ioc_status == MPI_IOCSTATUS_CONFIG_INVALID_PAGE) {
8162 if (page_type == MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE ||
8163 page_type == MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER ||
8164 page_type == MPI_CONFIG_EXTPAGETYPE_ENCLOSURE) {
8165 if ((form >> MPI_SAS_DEVICE_PGAD_FORM_SHIFT) ==
8166 MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE)
8167 return;
8168 }
8169 if (page_type == MPI_CONFIG_PAGETYPE_FC_DEVICE)
8170 if ((form & MPI_FC_DEVICE_PGAD_FORM_MASK) ==
8171 MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
8172 return;
8173 }
8174
8175 snprintf(extend_desc, EVENT_DESCR_STR_SZ,
8176 "type=%02Xh, page=%02Xh, action=%02Xh, form=%08Xh",
8177 page_type, pReq->Header.PageNumber, pReq->Action, form);
8178
8179 switch (ioc_status) {
8180
8181 case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */
8182 desc = "Config Page Invalid Action";
8183 break;
8184
8185 case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */
8186 desc = "Config Page Invalid Type";
8187 break;
8188
8189 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */
8190 desc = "Config Page Invalid Page";
8191 break;
8192
8193 case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */
8194 desc = "Config Page Invalid Data";
8195 break;
8196
8197 case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */
8198 desc = "Config Page No Defaults";
8199 break;
8200
8201 case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */
8202 desc = "Config Page Can't Commit";
8203 break;
8204 }
8205
8206 if (!desc)
8207 return;
8208
8209 dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s: %s\n",
8210 ioc->name, ioc_status, desc, extend_desc));
8211}
8212
8213/**
8214 * mpt_iocstatus_info - IOCSTATUS information returned from IOC.
8215 * @ioc: Pointer to MPT_ADAPTER structure
8216 * @ioc_status: U32 IOCStatus word from IOC
8217 * @mf: Pointer to MPT request frame
8218 *
8219 * Refer to lsi/mpi.h.
8220 **/
8221static void
8222mpt_iocstatus_info(MPT_ADAPTER *ioc, u32 ioc_status, MPT_FRAME_HDR *mf)
8223{
8224 u32 status = ioc_status & MPI_IOCSTATUS_MASK;
8225 char *desc = NULL;
8226
8227 switch (status) {
8228
8229/****************************************************************************/
8230/* Common IOCStatus values for all replies */
8231/****************************************************************************/
8232
8233 case MPI_IOCSTATUS_INVALID_FUNCTION: /* 0x0001 */
8234 desc = "Invalid Function";
8235 break;
8236
8237 case MPI_IOCSTATUS_BUSY: /* 0x0002 */
8238 desc = "Busy";
8239 break;
8240
8241 case MPI_IOCSTATUS_INVALID_SGL: /* 0x0003 */
8242 desc = "Invalid SGL";
8243 break;
8244
8245 case MPI_IOCSTATUS_INTERNAL_ERROR: /* 0x0004 */
8246 desc = "Internal Error";
8247 break;
8248
8249 case MPI_IOCSTATUS_RESERVED: /* 0x0005 */
8250 desc = "Reserved";
8251 break;
8252
8253 case MPI_IOCSTATUS_INSUFFICIENT_RESOURCES: /* 0x0006 */
8254 desc = "Insufficient Resources";
8255 break;
8256
8257 case MPI_IOCSTATUS_INVALID_FIELD: /* 0x0007 */
8258 desc = "Invalid Field";
8259 break;
8260
8261 case MPI_IOCSTATUS_INVALID_STATE: /* 0x0008 */
8262 desc = "Invalid State";
8263 break;
8264
8265/****************************************************************************/
8266/* Config IOCStatus values */
8267/****************************************************************************/
8268
8269 case MPI_IOCSTATUS_CONFIG_INVALID_ACTION: /* 0x0020 */
8270 case MPI_IOCSTATUS_CONFIG_INVALID_TYPE: /* 0x0021 */
8271 case MPI_IOCSTATUS_CONFIG_INVALID_PAGE: /* 0x0022 */
8272 case MPI_IOCSTATUS_CONFIG_INVALID_DATA: /* 0x0023 */
8273 case MPI_IOCSTATUS_CONFIG_NO_DEFAULTS: /* 0x0024 */
8274 case MPI_IOCSTATUS_CONFIG_CANT_COMMIT: /* 0x0025 */
8275 mpt_iocstatus_info_config(ioc, status, mf);
8276 break;
8277
8278/****************************************************************************/
8279/* SCSIIO Reply (SPI, FCP, SAS) initiator values */
8280/* */
8281/* Look at mptscsih_iocstatus_info_scsiio in mptscsih.c */
8282/* */
8283/****************************************************************************/
8284
8285 case MPI_IOCSTATUS_SCSI_RECOVERED_ERROR: /* 0x0040 */
8286 case MPI_IOCSTATUS_SCSI_DATA_UNDERRUN: /* 0x0045 */
8287 case MPI_IOCSTATUS_SCSI_INVALID_BUS: /* 0x0041 */
8288 case MPI_IOCSTATUS_SCSI_INVALID_TARGETID: /* 0x0042 */
8289 case MPI_IOCSTATUS_SCSI_DEVICE_NOT_THERE: /* 0x0043 */
8290 case MPI_IOCSTATUS_SCSI_DATA_OVERRUN: /* 0x0044 */
8291 case MPI_IOCSTATUS_SCSI_IO_DATA_ERROR: /* 0x0046 */
8292 case MPI_IOCSTATUS_SCSI_PROTOCOL_ERROR: /* 0x0047 */
8293 case MPI_IOCSTATUS_SCSI_TASK_TERMINATED: /* 0x0048 */
8294 case MPI_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: /* 0x0049 */
8295 case MPI_IOCSTATUS_SCSI_TASK_MGMT_FAILED: /* 0x004A */
8296 case MPI_IOCSTATUS_SCSI_IOC_TERMINATED: /* 0x004B */
8297 case MPI_IOCSTATUS_SCSI_EXT_TERMINATED: /* 0x004C */
8298 break;
8299
8300/****************************************************************************/
8301/* SCSI Target values */
8302/****************************************************************************/
8303
8304 case MPI_IOCSTATUS_TARGET_PRIORITY_IO: /* 0x0060 */
8305 desc = "Target: Priority IO";
8306 break;
8307
8308 case MPI_IOCSTATUS_TARGET_INVALID_PORT: /* 0x0061 */
8309 desc = "Target: Invalid Port";
8310 break;
8311
8312 case MPI_IOCSTATUS_TARGET_INVALID_IO_INDEX: /* 0x0062 */
8313 desc = "Target Invalid IO Index:";
8314 break;
8315
8316 case MPI_IOCSTATUS_TARGET_ABORTED: /* 0x0063 */
8317 desc = "Target: Aborted";
8318 break;
8319
8320 case MPI_IOCSTATUS_TARGET_NO_CONN_RETRYABLE: /* 0x0064 */
8321 desc = "Target: No Conn Retryable";
8322 break;
8323
8324 case MPI_IOCSTATUS_TARGET_NO_CONNECTION: /* 0x0065 */
8325 desc = "Target: No Connection";
8326 break;
8327
8328 case MPI_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH: /* 0x006A */
8329 desc = "Target: Transfer Count Mismatch";
8330 break;
8331
8332 case MPI_IOCSTATUS_TARGET_STS_DATA_NOT_SENT: /* 0x006B */
8333 desc = "Target: STS Data not Sent";
8334 break;
8335
8336 case MPI_IOCSTATUS_TARGET_DATA_OFFSET_ERROR: /* 0x006D */
8337 desc = "Target: Data Offset Error";
8338 break;
8339
8340 case MPI_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA: /* 0x006E */
8341 desc = "Target: Too Much Write Data";
8342 break;
8343
8344 case MPI_IOCSTATUS_TARGET_IU_TOO_SHORT: /* 0x006F */
8345 desc = "Target: IU Too Short";
8346 break;
8347
8348 case MPI_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT: /* 0x0070 */
8349 desc = "Target: ACK NAK Timeout";
8350 break;
8351
8352 case MPI_IOCSTATUS_TARGET_NAK_RECEIVED: /* 0x0071 */
8353 desc = "Target: Nak Received";
8354 break;
8355
8356/****************************************************************************/
8357/* Fibre Channel Direct Access values */
8358/****************************************************************************/
8359
8360 case MPI_IOCSTATUS_FC_ABORTED: /* 0x0066 */
8361 desc = "FC: Aborted";
8362 break;
8363
8364 case MPI_IOCSTATUS_FC_RX_ID_INVALID: /* 0x0067 */
8365 desc = "FC: RX ID Invalid";
8366 break;
8367
8368 case MPI_IOCSTATUS_FC_DID_INVALID: /* 0x0068 */
8369 desc = "FC: DID Invalid";
8370 break;
8371
8372 case MPI_IOCSTATUS_FC_NODE_LOGGED_OUT: /* 0x0069 */
8373 desc = "FC: Node Logged Out";
8374 break;
8375
8376 case MPI_IOCSTATUS_FC_EXCHANGE_CANCELED: /* 0x006C */
8377 desc = "FC: Exchange Canceled";
8378 break;
8379
8380/****************************************************************************/
8381/* LAN values */
8382/****************************************************************************/
8383
8384 case MPI_IOCSTATUS_LAN_DEVICE_NOT_FOUND: /* 0x0080 */
8385 desc = "LAN: Device not Found";
8386 break;
8387
8388 case MPI_IOCSTATUS_LAN_DEVICE_FAILURE: /* 0x0081 */
8389 desc = "LAN: Device Failure";
8390 break;
8391
8392 case MPI_IOCSTATUS_LAN_TRANSMIT_ERROR: /* 0x0082 */
8393 desc = "LAN: Transmit Error";
8394 break;
8395
8396 case MPI_IOCSTATUS_LAN_TRANSMIT_ABORTED: /* 0x0083 */
8397 desc = "LAN: Transmit Aborted";
8398 break;
8399
8400 case MPI_IOCSTATUS_LAN_RECEIVE_ERROR: /* 0x0084 */
8401 desc = "LAN: Receive Error";
8402 break;
8403
8404 case MPI_IOCSTATUS_LAN_RECEIVE_ABORTED: /* 0x0085 */
8405 desc = "LAN: Receive Aborted";
8406 break;
8407
8408 case MPI_IOCSTATUS_LAN_PARTIAL_PACKET: /* 0x0086 */
8409 desc = "LAN: Partial Packet";
8410 break;
8411
8412 case MPI_IOCSTATUS_LAN_CANCELED: /* 0x0087 */
8413 desc = "LAN: Canceled";
8414 break;
8415
8416/****************************************************************************/
8417/* Serial Attached SCSI values */
8418/****************************************************************************/
8419
8420 case MPI_IOCSTATUS_SAS_SMP_REQUEST_FAILED: /* 0x0090 */
8421 desc = "SAS: SMP Request Failed";
8422 break;
8423
8424 case MPI_IOCSTATUS_SAS_SMP_DATA_OVERRUN: /* 0x0090 */
8425 desc = "SAS: SMP Data Overrun";
8426 break;
8427
8428 default:
8429 desc = "Others";
8430 break;
8431 }
8432
8433 if (!desc)
8434 return;
8435
8436 dreplyprintk(ioc, printk(MYIOC_s_DEBUG_FMT "IOCStatus(0x%04X): %s\n",
8437 ioc->name, status, desc));
8438}
8439
8440/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8441EXPORT_SYMBOL(mpt_attach);
8442EXPORT_SYMBOL(mpt_detach);
8443#ifdef CONFIG_PM
8444EXPORT_SYMBOL(mpt_resume);
8445EXPORT_SYMBOL(mpt_suspend);
8446#endif
8447EXPORT_SYMBOL(ioc_list);
8448EXPORT_SYMBOL(mpt_register);
8449EXPORT_SYMBOL(mpt_deregister);
8450EXPORT_SYMBOL(mpt_event_register);
8451EXPORT_SYMBOL(mpt_event_deregister);
8452EXPORT_SYMBOL(mpt_reset_register);
8453EXPORT_SYMBOL(mpt_reset_deregister);
8454EXPORT_SYMBOL(mpt_device_driver_register);
8455EXPORT_SYMBOL(mpt_device_driver_deregister);
8456EXPORT_SYMBOL(mpt_get_msg_frame);
8457EXPORT_SYMBOL(mpt_put_msg_frame);
8458EXPORT_SYMBOL(mpt_put_msg_frame_hi_pri);
8459EXPORT_SYMBOL(mpt_free_msg_frame);
8460EXPORT_SYMBOL(mpt_send_handshake_request);
8461EXPORT_SYMBOL(mpt_verify_adapter);
8462EXPORT_SYMBOL(mpt_GetIocState);
8463EXPORT_SYMBOL(mpt_print_ioc_summary);
8464EXPORT_SYMBOL(mpt_HardResetHandler);
8465EXPORT_SYMBOL(mpt_config);
8466EXPORT_SYMBOL(mpt_findImVolumes);
8467EXPORT_SYMBOL(mpt_alloc_fw_memory);
8468EXPORT_SYMBOL(mpt_free_fw_memory);
8469EXPORT_SYMBOL(mptbase_sas_persist_operation);
8470EXPORT_SYMBOL(mpt_raid_phys_disk_pg0);
8471
8472/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8473/**
8474 * fusion_init - Fusion MPT base driver initialization routine.
8475 *
8476 * Returns 0 for success, non-zero for failure.
8477 */
8478static int __init
8479fusion_init(void)
8480{
8481 u8 cb_idx;
8482
8483 show_mptmod_ver(my_NAME, my_VERSION);
8484 printk(KERN_INFO COPYRIGHT "\n");
8485
8486 for (cb_idx = 0; cb_idx < MPT_MAX_PROTOCOL_DRIVERS; cb_idx++) {
8487 MptCallbacks[cb_idx] = NULL;
8488 MptDriverClass[cb_idx] = MPTUNKNOWN_DRIVER;
8489 MptEvHandlers[cb_idx] = NULL;
8490 MptResetHandlers[cb_idx] = NULL;
8491 }
8492
8493 /* Register ourselves (mptbase) in order to facilitate
8494 * EventNotification handling.
8495 */
8496 mpt_base_index = mpt_register(mptbase_reply, MPTBASE_DRIVER,
8497 "mptbase_reply");
8498
8499 /* Register for hard reset handling callbacks.
8500 */
8501 mpt_reset_register(mpt_base_index, mpt_ioc_reset);
8502
8503#ifdef CONFIG_PROC_FS
8504 (void) procmpt_create();
8505#endif
8506 return 0;
8507}
8508
8509/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
8510/**
8511 * fusion_exit - Perform driver unload cleanup.
8512 *
8513 * This routine frees all resources associated with each MPT adapter
8514 * and removes all %MPT_PROCFS_MPTBASEDIR entries.
8515 */
8516static void __exit
8517fusion_exit(void)
8518{
8519
8520 mpt_reset_deregister(mpt_base_index);
8521
8522#ifdef CONFIG_PROC_FS
8523 procmpt_destroy();
8524#endif
8525}
8526
8527module_init(fusion_init);
8528module_exit(fusion_exit);