1/* SPDX-License-Identifier: GPL-2.0-only */
 2/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
 3 */
 4
 5#ifndef _DPU_HW_INTERRUPTS_H
 6#define _DPU_HW_INTERRUPTS_H
 7
 8#include <linux/types.h>
 9
10#include "dpu_hwio.h"
11#include "dpu_hw_catalog.h"
12#include "dpu_hw_util.h"
13#include "dpu_hw_mdss.h"
14
15/* When making changes be sure to sync with dpu_intr_set */
16enum dpu_hw_intr_reg {
17	MDP_SSPP_TOP0_INTR,
18	MDP_SSPP_TOP0_INTR2,
19	MDP_SSPP_TOP0_HIST_INTR,
20	/* All MDP_INTFn_INTR should come sequentially */
21	MDP_INTF0_INTR,
22	MDP_INTF1_INTR,
23	MDP_INTF2_INTR,
24	MDP_INTF3_INTR,
25	MDP_INTF4_INTR,
26	MDP_INTF5_INTR,
27	MDP_INTF6_INTR,
28	MDP_INTF7_INTR,
29	MDP_INTF8_INTR,
30	MDP_INTF1_TEAR_INTR,
31	MDP_INTF2_TEAR_INTR,
32	MDP_AD4_0_INTR,
33	MDP_AD4_1_INTR,
34	MDP_INTR_MAX,
35};
36
37#define MDP_INTFn_INTR(intf)	(MDP_INTF0_INTR + (intf - INTF_0))
38
39#define DPU_IRQ_IDX(reg_idx, offset)	(1 + reg_idx * 32 + offset)
40#define DPU_IRQ_REG(irq_idx)	((irq_idx - 1) / 32)
41#define DPU_IRQ_BIT(irq_idx)	((irq_idx - 1) % 32)
42
43#define DPU_NUM_IRQS		(MDP_INTR_MAX * 32)
44
45struct dpu_hw_intr_entry {
46	void (*cb)(void *arg);
47	void *arg;
48	atomic_t count;
49};
50
51/**
52 * struct dpu_hw_intr: hw interrupts handling data structure
53 * @hw:               virtual address mapping
54 * @ops:              function pointer mapping for IRQ handling
55 * @cache_irq_mask:   array of IRQ enable masks reg storage created during init
56 * @save_irq_status:  array of IRQ status reg storage created during init
57 * @irq_lock:         spinlock for accessing IRQ resources
58 * @irq_cb_tbl:       array of IRQ callbacks
59 */
60struct dpu_hw_intr {
61	struct dpu_hw_blk_reg_map hw;
62	u32 cache_irq_mask[MDP_INTR_MAX];
63	u32 *save_irq_status;
64	spinlock_t irq_lock;
65	unsigned long irq_mask;
66	const struct dpu_intr_reg *intr_set;
67
68	struct dpu_hw_intr_entry irq_tbl[DPU_NUM_IRQS];
69};
70
71/**
72 * dpu_hw_intr_init(): Initializes the interrupts hw object
73 * @dev:  Corresponding device for devres management
74 * @addr: mapped register io address of MDP
75 * @m:    pointer to MDSS catalog data
76 */
77struct dpu_hw_intr *dpu_hw_intr_init(struct drm_device *dev,
78				     void __iomem *addr,
79				     const struct dpu_mdss_cfg *m);
80
81#endif