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1/*
2 * arch/arm/mach-ep93xx/clock.c
3 * Clock control for Cirrus EP93xx chips.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or (at
10 * your option) any later version.
11 */
12
13#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
14
15#include <linux/kernel.h>
16#include <linux/clk.h>
17#include <linux/err.h>
18#include <linux/module.h>
19#include <linux/string.h>
20#include <linux/io.h>
21#include <linux/spinlock.h>
22#include <linux/clkdev.h>
23
24#include <mach/hardware.h>
25
26#include <asm/div64.h>
27
28
29struct clk {
30 struct clk *parent;
31 unsigned long rate;
32 int users;
33 int sw_locked;
34 void __iomem *enable_reg;
35 u32 enable_mask;
36
37 unsigned long (*get_rate)(struct clk *clk);
38 int (*set_rate)(struct clk *clk, unsigned long rate);
39};
40
41
42static unsigned long get_uart_rate(struct clk *clk);
43
44static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
45static int set_div_rate(struct clk *clk, unsigned long rate);
46static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
47static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
48
49static struct clk clk_xtali = {
50 .rate = EP93XX_EXT_CLK_RATE,
51};
52static struct clk clk_uart1 = {
53 .parent = &clk_xtali,
54 .sw_locked = 1,
55 .enable_reg = EP93XX_SYSCON_DEVCFG,
56 .enable_mask = EP93XX_SYSCON_DEVCFG_U1EN,
57 .get_rate = get_uart_rate,
58};
59static struct clk clk_uart2 = {
60 .parent = &clk_xtali,
61 .sw_locked = 1,
62 .enable_reg = EP93XX_SYSCON_DEVCFG,
63 .enable_mask = EP93XX_SYSCON_DEVCFG_U2EN,
64 .get_rate = get_uart_rate,
65};
66static struct clk clk_uart3 = {
67 .parent = &clk_xtali,
68 .sw_locked = 1,
69 .enable_reg = EP93XX_SYSCON_DEVCFG,
70 .enable_mask = EP93XX_SYSCON_DEVCFG_U3EN,
71 .get_rate = get_uart_rate,
72};
73static struct clk clk_pll1 = {
74 .parent = &clk_xtali,
75};
76static struct clk clk_f = {
77 .parent = &clk_pll1,
78};
79static struct clk clk_h = {
80 .parent = &clk_pll1,
81};
82static struct clk clk_p = {
83 .parent = &clk_pll1,
84};
85static struct clk clk_pll2 = {
86 .parent = &clk_xtali,
87};
88static struct clk clk_usb_host = {
89 .parent = &clk_pll2,
90 .enable_reg = EP93XX_SYSCON_PWRCNT,
91 .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
92};
93static struct clk clk_keypad = {
94 .parent = &clk_xtali,
95 .sw_locked = 1,
96 .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
97 .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
98 .set_rate = set_keytchclk_rate,
99};
100static struct clk clk_spi = {
101 .parent = &clk_xtali,
102 .rate = EP93XX_EXT_CLK_RATE,
103};
104static struct clk clk_pwm = {
105 .parent = &clk_xtali,
106 .rate = EP93XX_EXT_CLK_RATE,
107};
108
109static struct clk clk_video = {
110 .sw_locked = 1,
111 .enable_reg = EP93XX_SYSCON_VIDCLKDIV,
112 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
113 .set_rate = set_div_rate,
114};
115
116static struct clk clk_i2s_mclk = {
117 .sw_locked = 1,
118 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
119 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
120 .set_rate = set_div_rate,
121};
122
123static struct clk clk_i2s_sclk = {
124 .sw_locked = 1,
125 .parent = &clk_i2s_mclk,
126 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
127 .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
128 .set_rate = set_i2s_sclk_rate,
129};
130
131static struct clk clk_i2s_lrclk = {
132 .sw_locked = 1,
133 .parent = &clk_i2s_sclk,
134 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
135 .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
136 .set_rate = set_i2s_lrclk_rate,
137};
138
139/* DMA Clocks */
140static struct clk clk_m2p0 = {
141 .parent = &clk_h,
142 .enable_reg = EP93XX_SYSCON_PWRCNT,
143 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0,
144};
145static struct clk clk_m2p1 = {
146 .parent = &clk_h,
147 .enable_reg = EP93XX_SYSCON_PWRCNT,
148 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1,
149};
150static struct clk clk_m2p2 = {
151 .parent = &clk_h,
152 .enable_reg = EP93XX_SYSCON_PWRCNT,
153 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2,
154};
155static struct clk clk_m2p3 = {
156 .parent = &clk_h,
157 .enable_reg = EP93XX_SYSCON_PWRCNT,
158 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3,
159};
160static struct clk clk_m2p4 = {
161 .parent = &clk_h,
162 .enable_reg = EP93XX_SYSCON_PWRCNT,
163 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4,
164};
165static struct clk clk_m2p5 = {
166 .parent = &clk_h,
167 .enable_reg = EP93XX_SYSCON_PWRCNT,
168 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5,
169};
170static struct clk clk_m2p6 = {
171 .parent = &clk_h,
172 .enable_reg = EP93XX_SYSCON_PWRCNT,
173 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6,
174};
175static struct clk clk_m2p7 = {
176 .parent = &clk_h,
177 .enable_reg = EP93XX_SYSCON_PWRCNT,
178 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7,
179};
180static struct clk clk_m2p8 = {
181 .parent = &clk_h,
182 .enable_reg = EP93XX_SYSCON_PWRCNT,
183 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8,
184};
185static struct clk clk_m2p9 = {
186 .parent = &clk_h,
187 .enable_reg = EP93XX_SYSCON_PWRCNT,
188 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9,
189};
190static struct clk clk_m2m0 = {
191 .parent = &clk_h,
192 .enable_reg = EP93XX_SYSCON_PWRCNT,
193 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0,
194};
195static struct clk clk_m2m1 = {
196 .parent = &clk_h,
197 .enable_reg = EP93XX_SYSCON_PWRCNT,
198 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1,
199};
200
201#define INIT_CK(dev,con,ck) \
202 { .dev_id = dev, .con_id = con, .clk = ck }
203
204static struct clk_lookup clocks[] = {
205 INIT_CK(NULL, "xtali", &clk_xtali),
206 INIT_CK("apb:uart1", NULL, &clk_uart1),
207 INIT_CK("apb:uart2", NULL, &clk_uart2),
208 INIT_CK("apb:uart3", NULL, &clk_uart3),
209 INIT_CK(NULL, "pll1", &clk_pll1),
210 INIT_CK(NULL, "fclk", &clk_f),
211 INIT_CK(NULL, "hclk", &clk_h),
212 INIT_CK(NULL, "apb_pclk", &clk_p),
213 INIT_CK(NULL, "pll2", &clk_pll2),
214 INIT_CK("ep93xx-ohci", NULL, &clk_usb_host),
215 INIT_CK("ep93xx-keypad", NULL, &clk_keypad),
216 INIT_CK("ep93xx-fb", NULL, &clk_video),
217 INIT_CK("ep93xx-spi.0", NULL, &clk_spi),
218 INIT_CK("ep93xx-i2s", "mclk", &clk_i2s_mclk),
219 INIT_CK("ep93xx-i2s", "sclk", &clk_i2s_sclk),
220 INIT_CK("ep93xx-i2s", "lrclk", &clk_i2s_lrclk),
221 INIT_CK(NULL, "pwm_clk", &clk_pwm),
222 INIT_CK(NULL, "m2p0", &clk_m2p0),
223 INIT_CK(NULL, "m2p1", &clk_m2p1),
224 INIT_CK(NULL, "m2p2", &clk_m2p2),
225 INIT_CK(NULL, "m2p3", &clk_m2p3),
226 INIT_CK(NULL, "m2p4", &clk_m2p4),
227 INIT_CK(NULL, "m2p5", &clk_m2p5),
228 INIT_CK(NULL, "m2p6", &clk_m2p6),
229 INIT_CK(NULL, "m2p7", &clk_m2p7),
230 INIT_CK(NULL, "m2p8", &clk_m2p8),
231 INIT_CK(NULL, "m2p9", &clk_m2p9),
232 INIT_CK(NULL, "m2m0", &clk_m2m0),
233 INIT_CK(NULL, "m2m1", &clk_m2m1),
234};
235
236static DEFINE_SPINLOCK(clk_lock);
237
238static void __clk_enable(struct clk *clk)
239{
240 if (!clk->users++) {
241 if (clk->parent)
242 __clk_enable(clk->parent);
243
244 if (clk->enable_reg) {
245 u32 v;
246
247 v = __raw_readl(clk->enable_reg);
248 v |= clk->enable_mask;
249 if (clk->sw_locked)
250 ep93xx_syscon_swlocked_write(v, clk->enable_reg);
251 else
252 __raw_writel(v, clk->enable_reg);
253 }
254 }
255}
256
257int clk_enable(struct clk *clk)
258{
259 unsigned long flags;
260
261 if (!clk)
262 return -EINVAL;
263
264 spin_lock_irqsave(&clk_lock, flags);
265 __clk_enable(clk);
266 spin_unlock_irqrestore(&clk_lock, flags);
267
268 return 0;
269}
270EXPORT_SYMBOL(clk_enable);
271
272static void __clk_disable(struct clk *clk)
273{
274 if (!--clk->users) {
275 if (clk->enable_reg) {
276 u32 v;
277
278 v = __raw_readl(clk->enable_reg);
279 v &= ~clk->enable_mask;
280 if (clk->sw_locked)
281 ep93xx_syscon_swlocked_write(v, clk->enable_reg);
282 else
283 __raw_writel(v, clk->enable_reg);
284 }
285
286 if (clk->parent)
287 __clk_disable(clk->parent);
288 }
289}
290
291void clk_disable(struct clk *clk)
292{
293 unsigned long flags;
294
295 if (!clk)
296 return;
297
298 spin_lock_irqsave(&clk_lock, flags);
299 __clk_disable(clk);
300 spin_unlock_irqrestore(&clk_lock, flags);
301}
302EXPORT_SYMBOL(clk_disable);
303
304static unsigned long get_uart_rate(struct clk *clk)
305{
306 unsigned long rate = clk_get_rate(clk->parent);
307 u32 value;
308
309 value = __raw_readl(EP93XX_SYSCON_PWRCNT);
310 if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
311 return rate;
312 else
313 return rate / 2;
314}
315
316unsigned long clk_get_rate(struct clk *clk)
317{
318 if (clk->get_rate)
319 return clk->get_rate(clk);
320
321 return clk->rate;
322}
323EXPORT_SYMBOL(clk_get_rate);
324
325static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
326{
327 u32 val;
328 u32 div_bit;
329
330 val = __raw_readl(clk->enable_reg);
331
332 /*
333 * The Key Matrix and ADC clocks are configured using the same
334 * System Controller register. The clock used will be either
335 * 1/4 or 1/16 the external clock rate depending on the
336 * EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV
337 * bit being set or cleared.
338 */
339 div_bit = clk->enable_mask >> 15;
340
341 if (rate == EP93XX_KEYTCHCLK_DIV4)
342 val |= div_bit;
343 else if (rate == EP93XX_KEYTCHCLK_DIV16)
344 val &= ~div_bit;
345 else
346 return -EINVAL;
347
348 ep93xx_syscon_swlocked_write(val, clk->enable_reg);
349 clk->rate = rate;
350 return 0;
351}
352
353static int calc_clk_div(struct clk *clk, unsigned long rate,
354 int *psel, int *esel, int *pdiv, int *div)
355{
356 struct clk *mclk;
357 unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1;
358 int i, found = 0, __div = 0, __pdiv = 0;
359
360 /* Don't exceed the maximum rate */
361 max_rate = max3(clk_pll1.rate / 4, clk_pll2.rate / 4, clk_xtali.rate / 4);
362 rate = min(rate, max_rate);
363
364 /*
365 * Try the two pll's and the external clock
366 * Because the valid predividers are 2, 2.5 and 3, we multiply
367 * all the clocks by 2 to avoid floating point math.
368 *
369 * This is based on the algorithm in the ep93xx raster guide:
370 * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
371 *
372 */
373 for (i = 0; i < 3; i++) {
374 if (i == 0)
375 mclk = &clk_xtali;
376 else if (i == 1)
377 mclk = &clk_pll1;
378 else
379 mclk = &clk_pll2;
380 mclk_rate = mclk->rate * 2;
381
382 /* Try each predivider value */
383 for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
384 __div = mclk_rate / (rate * __pdiv);
385 if (__div < 2 || __div > 127)
386 continue;
387
388 actual_rate = mclk_rate / (__pdiv * __div);
389
390 if (!found || abs(actual_rate - rate) < rate_err) {
391 *pdiv = __pdiv - 3;
392 *div = __div;
393 *psel = (i == 2);
394 *esel = (i != 0);
395 clk->parent = mclk;
396 clk->rate = actual_rate;
397 rate_err = abs(actual_rate - rate);
398 found = 1;
399 }
400 }
401 }
402
403 if (!found)
404 return -EINVAL;
405
406 return 0;
407}
408
409static int set_div_rate(struct clk *clk, unsigned long rate)
410{
411 int err, psel = 0, esel = 0, pdiv = 0, div = 0;
412 u32 val;
413
414 err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div);
415 if (err)
416 return err;
417
418 /* Clear the esel, psel, pdiv and div bits */
419 val = __raw_readl(clk->enable_reg);
420 val &= ~0x7fff;
421
422 /* Set the new esel, psel, pdiv and div bits for the new clock rate */
423 val |= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) |
424 (psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) |
425 (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div;
426 ep93xx_syscon_swlocked_write(val, clk->enable_reg);
427 return 0;
428}
429
430static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate)
431{
432 unsigned val = __raw_readl(clk->enable_reg);
433
434 if (rate == clk_i2s_mclk.rate / 2)
435 ep93xx_syscon_swlocked_write(val & ~EP93XX_I2SCLKDIV_SDIV,
436 clk->enable_reg);
437 else if (rate == clk_i2s_mclk.rate / 4)
438 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_SDIV,
439 clk->enable_reg);
440 else
441 return -EINVAL;
442
443 clk_i2s_sclk.rate = rate;
444 return 0;
445}
446
447static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate)
448{
449 unsigned val = __raw_readl(clk->enable_reg) &
450 ~EP93XX_I2SCLKDIV_LRDIV_MASK;
451
452 if (rate == clk_i2s_sclk.rate / 32)
453 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV32,
454 clk->enable_reg);
455 else if (rate == clk_i2s_sclk.rate / 64)
456 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV64,
457 clk->enable_reg);
458 else if (rate == clk_i2s_sclk.rate / 128)
459 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV128,
460 clk->enable_reg);
461 else
462 return -EINVAL;
463
464 clk_i2s_lrclk.rate = rate;
465 return 0;
466}
467
468int clk_set_rate(struct clk *clk, unsigned long rate)
469{
470 if (clk->set_rate)
471 return clk->set_rate(clk, rate);
472
473 return -EINVAL;
474}
475EXPORT_SYMBOL(clk_set_rate);
476
477
478static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
479static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
480static char pclk_divisors[] = { 1, 2, 4, 8 };
481
482/*
483 * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
484 */
485static unsigned long calc_pll_rate(u32 config_word)
486{
487 unsigned long long rate;
488 int i;
489
490 rate = clk_xtali.rate;
491 rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */
492 rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */
493 do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */
494 for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */
495 rate >>= 1;
496
497 return (unsigned long)rate;
498}
499
500static void __init ep93xx_dma_clock_init(void)
501{
502 clk_m2p0.rate = clk_h.rate;
503 clk_m2p1.rate = clk_h.rate;
504 clk_m2p2.rate = clk_h.rate;
505 clk_m2p3.rate = clk_h.rate;
506 clk_m2p4.rate = clk_h.rate;
507 clk_m2p5.rate = clk_h.rate;
508 clk_m2p6.rate = clk_h.rate;
509 clk_m2p7.rate = clk_h.rate;
510 clk_m2p8.rate = clk_h.rate;
511 clk_m2p9.rate = clk_h.rate;
512 clk_m2m0.rate = clk_h.rate;
513 clk_m2m1.rate = clk_h.rate;
514}
515
516static int __init ep93xx_clock_init(void)
517{
518 u32 value;
519
520 /* Determine the bootloader configured pll1 rate */
521 value = __raw_readl(EP93XX_SYSCON_CLKSET1);
522 if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
523 clk_pll1.rate = clk_xtali.rate;
524 else
525 clk_pll1.rate = calc_pll_rate(value);
526
527 /* Initialize the pll1 derived clocks */
528 clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
529 clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
530 clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
531 ep93xx_dma_clock_init();
532
533 /* Determine the bootloader configured pll2 rate */
534 value = __raw_readl(EP93XX_SYSCON_CLKSET2);
535 if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
536 clk_pll2.rate = clk_xtali.rate;
537 else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
538 clk_pll2.rate = calc_pll_rate(value);
539 else
540 clk_pll2.rate = 0;
541
542 /* Initialize the pll2 derived clocks */
543 clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
544
545 /*
546 * EP93xx SSP clock rate was doubled in version E2. For more information
547 * see:
548 * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
549 */
550 if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2)
551 clk_spi.rate /= 2;
552
553 pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
554 clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
555 pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
556 clk_f.rate / 1000000, clk_h.rate / 1000000,
557 clk_p.rate / 1000000);
558
559 clkdev_add_table(clocks, ARRAY_SIZE(clocks));
560 return 0;
561}
562postcore_initcall(ep93xx_clock_init);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * arch/arm/mach-ep93xx/clock.c
4 * Clock control for Cirrus EP93xx chips.
5 *
6 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
7 */
8
9#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
10
11#include <linux/kernel.h>
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/module.h>
15#include <linux/string.h>
16#include <linux/io.h>
17#include <linux/spinlock.h>
18#include <linux/clkdev.h>
19#include <linux/clk-provider.h>
20#include <linux/soc/cirrus/ep93xx.h>
21
22#include "hardware.h"
23
24#include <asm/div64.h>
25
26#include "soc.h"
27
28static DEFINE_SPINLOCK(clk_lock);
29
30static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
31static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
32static char pclk_divisors[] = { 1, 2, 4, 8 };
33
34static char adc_divisors[] = { 16, 4 };
35static char sclk_divisors[] = { 2, 4 };
36static char lrclk_divisors[] = { 32, 64, 128 };
37
38static const char * const mux_parents[] = {
39 "xtali",
40 "pll1",
41 "pll2"
42};
43
44/*
45 * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
46 */
47static unsigned long calc_pll_rate(unsigned long long rate, u32 config_word)
48{
49 int i;
50
51 rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */
52 rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */
53 do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */
54 for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */
55 rate >>= 1;
56
57 return (unsigned long)rate;
58}
59
60struct clk_psc {
61 struct clk_hw hw;
62 void __iomem *reg;
63 u8 bit_idx;
64 u32 mask;
65 u8 shift;
66 u8 width;
67 char *div;
68 u8 num_div;
69 spinlock_t *lock;
70};
71
72#define to_clk_psc(_hw) container_of(_hw, struct clk_psc, hw)
73
74static int ep93xx_clk_is_enabled(struct clk_hw *hw)
75{
76 struct clk_psc *psc = to_clk_psc(hw);
77 u32 val = readl(psc->reg);
78
79 return (val & BIT(psc->bit_idx)) ? 1 : 0;
80}
81
82static int ep93xx_clk_enable(struct clk_hw *hw)
83{
84 struct clk_psc *psc = to_clk_psc(hw);
85 unsigned long flags = 0;
86 u32 val;
87
88 if (psc->lock)
89 spin_lock_irqsave(psc->lock, flags);
90
91 val = __raw_readl(psc->reg);
92 val |= BIT(psc->bit_idx);
93
94 ep93xx_syscon_swlocked_write(val, psc->reg);
95
96 if (psc->lock)
97 spin_unlock_irqrestore(psc->lock, flags);
98
99 return 0;
100}
101
102static void ep93xx_clk_disable(struct clk_hw *hw)
103{
104 struct clk_psc *psc = to_clk_psc(hw);
105 unsigned long flags = 0;
106 u32 val;
107
108 if (psc->lock)
109 spin_lock_irqsave(psc->lock, flags);
110
111 val = __raw_readl(psc->reg);
112 val &= ~BIT(psc->bit_idx);
113
114 ep93xx_syscon_swlocked_write(val, psc->reg);
115
116 if (psc->lock)
117 spin_unlock_irqrestore(psc->lock, flags);
118}
119
120static const struct clk_ops clk_ep93xx_gate_ops = {
121 .enable = ep93xx_clk_enable,
122 .disable = ep93xx_clk_disable,
123 .is_enabled = ep93xx_clk_is_enabled,
124};
125
126static struct clk_hw *ep93xx_clk_register_gate(const char *name,
127 const char *parent_name,
128 void __iomem *reg,
129 u8 bit_idx)
130{
131 struct clk_init_data init;
132 struct clk_psc *psc;
133 struct clk *clk;
134
135 psc = kzalloc(sizeof(*psc), GFP_KERNEL);
136 if (!psc)
137 return ERR_PTR(-ENOMEM);
138
139 init.name = name;
140 init.ops = &clk_ep93xx_gate_ops;
141 init.flags = CLK_SET_RATE_PARENT;
142 init.parent_names = (parent_name ? &parent_name : NULL);
143 init.num_parents = (parent_name ? 1 : 0);
144
145 psc->reg = reg;
146 psc->bit_idx = bit_idx;
147 psc->hw.init = &init;
148 psc->lock = &clk_lock;
149
150 clk = clk_register(NULL, &psc->hw);
151 if (IS_ERR(clk)) {
152 kfree(psc);
153 return ERR_CAST(clk);
154 }
155
156 return &psc->hw;
157}
158
159static u8 ep93xx_mux_get_parent(struct clk_hw *hw)
160{
161 struct clk_psc *psc = to_clk_psc(hw);
162 u32 val = __raw_readl(psc->reg);
163
164 if (!(val & EP93XX_SYSCON_CLKDIV_ESEL))
165 return 0;
166
167 if (!(val & EP93XX_SYSCON_CLKDIV_PSEL))
168 return 1;
169
170 return 2;
171}
172
173static int ep93xx_mux_set_parent_lock(struct clk_hw *hw, u8 index)
174{
175 struct clk_psc *psc = to_clk_psc(hw);
176 unsigned long flags = 0;
177 u32 val;
178
179 if (index >= ARRAY_SIZE(mux_parents))
180 return -EINVAL;
181
182 if (psc->lock)
183 spin_lock_irqsave(psc->lock, flags);
184
185 val = __raw_readl(psc->reg);
186 val &= ~(EP93XX_SYSCON_CLKDIV_ESEL | EP93XX_SYSCON_CLKDIV_PSEL);
187
188
189 if (index != 0) {
190 val |= EP93XX_SYSCON_CLKDIV_ESEL;
191 val |= (index - 1) ? EP93XX_SYSCON_CLKDIV_PSEL : 0;
192 }
193
194 ep93xx_syscon_swlocked_write(val, psc->reg);
195
196 if (psc->lock)
197 spin_unlock_irqrestore(psc->lock, flags);
198
199 return 0;
200}
201
202static bool is_best(unsigned long rate, unsigned long now,
203 unsigned long best)
204{
205 return abs(rate - now) < abs(rate - best);
206}
207
208static int ep93xx_mux_determine_rate(struct clk_hw *hw,
209 struct clk_rate_request *req)
210{
211 unsigned long rate = req->rate;
212 struct clk *best_parent = NULL;
213 unsigned long __parent_rate;
214 unsigned long best_rate = 0, actual_rate, mclk_rate;
215 unsigned long best_parent_rate;
216 int __div = 0, __pdiv = 0;
217 int i;
218
219 /*
220 * Try the two pll's and the external clock
221 * Because the valid predividers are 2, 2.5 and 3, we multiply
222 * all the clocks by 2 to avoid floating point math.
223 *
224 * This is based on the algorithm in the ep93xx raster guide:
225 * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
226 *
227 */
228 for (i = 0; i < ARRAY_SIZE(mux_parents); i++) {
229 struct clk *parent = clk_get_sys(mux_parents[i], NULL);
230
231 __parent_rate = clk_get_rate(parent);
232 mclk_rate = __parent_rate * 2;
233
234 /* Try each predivider value */
235 for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
236 __div = mclk_rate / (rate * __pdiv);
237 if (__div < 2 || __div > 127)
238 continue;
239
240 actual_rate = mclk_rate / (__pdiv * __div);
241 if (is_best(rate, actual_rate, best_rate)) {
242 best_rate = actual_rate;
243 best_parent_rate = __parent_rate;
244 best_parent = parent;
245 }
246 }
247 }
248
249 if (!best_parent)
250 return -EINVAL;
251
252 req->best_parent_rate = best_parent_rate;
253 req->best_parent_hw = __clk_get_hw(best_parent);
254 req->rate = best_rate;
255
256 return 0;
257}
258
259static unsigned long ep93xx_ddiv_recalc_rate(struct clk_hw *hw,
260 unsigned long parent_rate)
261{
262 struct clk_psc *psc = to_clk_psc(hw);
263 unsigned long rate = 0;
264 u32 val = __raw_readl(psc->reg);
265 int __pdiv = ((val >> EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) & 0x03);
266 int __div = val & 0x7f;
267
268 if (__div > 0)
269 rate = (parent_rate * 2) / ((__pdiv + 3) * __div);
270
271 return rate;
272}
273
274static int ep93xx_ddiv_set_rate(struct clk_hw *hw, unsigned long rate,
275 unsigned long parent_rate)
276{
277 struct clk_psc *psc = to_clk_psc(hw);
278 int pdiv = 0, div = 0;
279 unsigned long best_rate = 0, actual_rate, mclk_rate;
280 int __div = 0, __pdiv = 0;
281 u32 val;
282
283 mclk_rate = parent_rate * 2;
284
285 for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
286 __div = mclk_rate / (rate * __pdiv);
287 if (__div < 2 || __div > 127)
288 continue;
289
290 actual_rate = mclk_rate / (__pdiv * __div);
291 if (is_best(rate, actual_rate, best_rate)) {
292 pdiv = __pdiv - 3;
293 div = __div;
294 best_rate = actual_rate;
295 }
296 }
297
298 if (!best_rate)
299 return -EINVAL;
300
301 val = __raw_readl(psc->reg);
302
303 /* Clear old dividers */
304 val &= ~0x37f;
305
306 /* Set the new pdiv and div bits for the new clock rate */
307 val |= (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div;
308 ep93xx_syscon_swlocked_write(val, psc->reg);
309
310 return 0;
311}
312
313static const struct clk_ops clk_ddiv_ops = {
314 .enable = ep93xx_clk_enable,
315 .disable = ep93xx_clk_disable,
316 .is_enabled = ep93xx_clk_is_enabled,
317 .get_parent = ep93xx_mux_get_parent,
318 .set_parent = ep93xx_mux_set_parent_lock,
319 .determine_rate = ep93xx_mux_determine_rate,
320 .recalc_rate = ep93xx_ddiv_recalc_rate,
321 .set_rate = ep93xx_ddiv_set_rate,
322};
323
324static struct clk_hw *clk_hw_register_ddiv(const char *name,
325 void __iomem *reg,
326 u8 bit_idx)
327{
328 struct clk_init_data init;
329 struct clk_psc *psc;
330 struct clk *clk;
331
332 psc = kzalloc(sizeof(*psc), GFP_KERNEL);
333 if (!psc)
334 return ERR_PTR(-ENOMEM);
335
336 init.name = name;
337 init.ops = &clk_ddiv_ops;
338 init.flags = 0;
339 init.parent_names = mux_parents;
340 init.num_parents = ARRAY_SIZE(mux_parents);
341
342 psc->reg = reg;
343 psc->bit_idx = bit_idx;
344 psc->lock = &clk_lock;
345 psc->hw.init = &init;
346
347 clk = clk_register(NULL, &psc->hw);
348 if (IS_ERR(clk)) {
349 kfree(psc);
350 return ERR_CAST(clk);
351 }
352 return &psc->hw;
353}
354
355static unsigned long ep93xx_div_recalc_rate(struct clk_hw *hw,
356 unsigned long parent_rate)
357{
358 struct clk_psc *psc = to_clk_psc(hw);
359 u32 val = __raw_readl(psc->reg);
360 u8 index = (val & psc->mask) >> psc->shift;
361
362 if (index > psc->num_div)
363 return 0;
364
365 return DIV_ROUND_UP_ULL(parent_rate, psc->div[index]);
366}
367
368static long ep93xx_div_round_rate(struct clk_hw *hw, unsigned long rate,
369 unsigned long *parent_rate)
370{
371 struct clk_psc *psc = to_clk_psc(hw);
372 unsigned long best = 0, now, maxdiv;
373 int i;
374
375 maxdiv = psc->div[psc->num_div - 1];
376
377 for (i = 0; i < psc->num_div; i++) {
378 if ((rate * psc->div[i]) == *parent_rate)
379 return DIV_ROUND_UP_ULL((u64)*parent_rate, psc->div[i]);
380
381 now = DIV_ROUND_UP_ULL((u64)*parent_rate, psc->div[i]);
382
383 if (is_best(rate, now, best))
384 best = now;
385 }
386
387 if (!best)
388 best = DIV_ROUND_UP_ULL(*parent_rate, maxdiv);
389
390 return best;
391}
392
393static int ep93xx_div_set_rate(struct clk_hw *hw, unsigned long rate,
394 unsigned long parent_rate)
395{
396 struct clk_psc *psc = to_clk_psc(hw);
397 u32 val = __raw_readl(psc->reg) & ~psc->mask;
398 int i;
399
400 for (i = 0; i < psc->num_div; i++)
401 if (rate == parent_rate / psc->div[i]) {
402 val |= i << psc->shift;
403 break;
404 }
405
406 if (i == psc->num_div)
407 return -EINVAL;
408
409 ep93xx_syscon_swlocked_write(val, psc->reg);
410
411 return 0;
412}
413
414static const struct clk_ops ep93xx_div_ops = {
415 .enable = ep93xx_clk_enable,
416 .disable = ep93xx_clk_disable,
417 .is_enabled = ep93xx_clk_is_enabled,
418 .recalc_rate = ep93xx_div_recalc_rate,
419 .round_rate = ep93xx_div_round_rate,
420 .set_rate = ep93xx_div_set_rate,
421};
422
423static struct clk_hw *clk_hw_register_div(const char *name,
424 const char *parent_name,
425 void __iomem *reg,
426 u8 enable_bit,
427 u8 shift,
428 u8 width,
429 char *clk_divisors,
430 u8 num_div)
431{
432 struct clk_init_data init;
433 struct clk_psc *psc;
434 struct clk *clk;
435
436 psc = kzalloc(sizeof(*psc), GFP_KERNEL);
437 if (!psc)
438 return ERR_PTR(-ENOMEM);
439
440 init.name = name;
441 init.ops = &ep93xx_div_ops;
442 init.flags = 0;
443 init.parent_names = (parent_name ? &parent_name : NULL);
444 init.num_parents = 1;
445
446 psc->reg = reg;
447 psc->bit_idx = enable_bit;
448 psc->mask = GENMASK(shift + width - 1, shift);
449 psc->shift = shift;
450 psc->div = clk_divisors;
451 psc->num_div = num_div;
452 psc->lock = &clk_lock;
453 psc->hw.init = &init;
454
455 clk = clk_register(NULL, &psc->hw);
456 if (IS_ERR(clk)) {
457 kfree(psc);
458 return ERR_CAST(clk);
459 }
460 return &psc->hw;
461}
462
463struct ep93xx_gate {
464 unsigned int bit;
465 const char *dev_id;
466 const char *con_id;
467};
468
469static struct ep93xx_gate ep93xx_uarts[] = {
470 {EP93XX_SYSCON_DEVCFG_U1EN, "apb:uart1", NULL},
471 {EP93XX_SYSCON_DEVCFG_U2EN, "apb:uart2", NULL},
472 {EP93XX_SYSCON_DEVCFG_U3EN, "apb:uart3", NULL},
473};
474
475static void __init ep93xx_uart_clock_init(void)
476{
477 unsigned int i;
478 struct clk_hw *hw;
479 u32 value;
480 unsigned int clk_uart_div;
481
482 value = __raw_readl(EP93XX_SYSCON_PWRCNT);
483 if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
484 clk_uart_div = 1;
485 else
486 clk_uart_div = 2;
487
488 hw = clk_hw_register_fixed_factor(NULL, "uart", "xtali", 0, 1, clk_uart_div);
489
490 /* parenting uart gate clocks to uart clock */
491 for (i = 0; i < ARRAY_SIZE(ep93xx_uarts); i++) {
492 hw = ep93xx_clk_register_gate(ep93xx_uarts[i].dev_id,
493 "uart",
494 EP93XX_SYSCON_DEVCFG,
495 ep93xx_uarts[i].bit);
496
497 clk_hw_register_clkdev(hw, NULL, ep93xx_uarts[i].dev_id);
498 }
499}
500
501static struct ep93xx_gate ep93xx_dmas[] = {
502 {EP93XX_SYSCON_PWRCNT_DMA_M2P0, NULL, "m2p0"},
503 {EP93XX_SYSCON_PWRCNT_DMA_M2P1, NULL, "m2p1"},
504 {EP93XX_SYSCON_PWRCNT_DMA_M2P2, NULL, "m2p2"},
505 {EP93XX_SYSCON_PWRCNT_DMA_M2P3, NULL, "m2p3"},
506 {EP93XX_SYSCON_PWRCNT_DMA_M2P4, NULL, "m2p4"},
507 {EP93XX_SYSCON_PWRCNT_DMA_M2P5, NULL, "m2p5"},
508 {EP93XX_SYSCON_PWRCNT_DMA_M2P6, NULL, "m2p6"},
509 {EP93XX_SYSCON_PWRCNT_DMA_M2P7, NULL, "m2p7"},
510 {EP93XX_SYSCON_PWRCNT_DMA_M2P8, NULL, "m2p8"},
511 {EP93XX_SYSCON_PWRCNT_DMA_M2P9, NULL, "m2p9"},
512 {EP93XX_SYSCON_PWRCNT_DMA_M2M0, NULL, "m2m0"},
513 {EP93XX_SYSCON_PWRCNT_DMA_M2M1, NULL, "m2m1"},
514};
515
516static void __init ep93xx_dma_clock_init(void)
517{
518 unsigned int i;
519 struct clk_hw *hw;
520 int ret;
521
522 for (i = 0; i < ARRAY_SIZE(ep93xx_dmas); i++) {
523 hw = clk_hw_register_gate(NULL, ep93xx_dmas[i].con_id,
524 "hclk", 0,
525 EP93XX_SYSCON_PWRCNT,
526 ep93xx_dmas[i].bit,
527 0,
528 &clk_lock);
529
530 ret = clk_hw_register_clkdev(hw, ep93xx_dmas[i].con_id, NULL);
531 if (ret)
532 pr_err("%s: failed to register lookup %s\n",
533 __func__, ep93xx_dmas[i].con_id);
534 }
535}
536
537static int __init ep93xx_clock_init(void)
538{
539 u32 value;
540 struct clk_hw *hw;
541 unsigned long clk_pll1_rate;
542 unsigned long clk_f_rate;
543 unsigned long clk_h_rate;
544 unsigned long clk_p_rate;
545 unsigned long clk_pll2_rate;
546 unsigned int clk_f_div;
547 unsigned int clk_h_div;
548 unsigned int clk_p_div;
549 unsigned int clk_usb_div;
550 unsigned long clk_spi_div;
551
552 hw = clk_hw_register_fixed_rate(NULL, "xtali", NULL, 0, EP93XX_EXT_CLK_RATE);
553 clk_hw_register_clkdev(hw, NULL, "xtali");
554
555 /* Determine the bootloader configured pll1 rate */
556 value = __raw_readl(EP93XX_SYSCON_CLKSET1);
557 if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
558 clk_pll1_rate = EP93XX_EXT_CLK_RATE;
559 else
560 clk_pll1_rate = calc_pll_rate(EP93XX_EXT_CLK_RATE, value);
561
562 hw = clk_hw_register_fixed_rate(NULL, "pll1", "xtali", 0, clk_pll1_rate);
563 clk_hw_register_clkdev(hw, NULL, "pll1");
564
565 /* Initialize the pll1 derived clocks */
566 clk_f_div = fclk_divisors[(value >> 25) & 0x7];
567 clk_h_div = hclk_divisors[(value >> 20) & 0x7];
568 clk_p_div = pclk_divisors[(value >> 18) & 0x3];
569
570 hw = clk_hw_register_fixed_factor(NULL, "fclk", "pll1", 0, 1, clk_f_div);
571 clk_f_rate = clk_get_rate(hw->clk);
572 hw = clk_hw_register_fixed_factor(NULL, "hclk", "pll1", 0, 1, clk_h_div);
573 clk_h_rate = clk_get_rate(hw->clk);
574 hw = clk_hw_register_fixed_factor(NULL, "pclk", "hclk", 0, 1, clk_p_div);
575 clk_p_rate = clk_get_rate(hw->clk);
576
577 clk_hw_register_clkdev(hw, "apb_pclk", NULL);
578
579 ep93xx_dma_clock_init();
580
581 /* Determine the bootloader configured pll2 rate */
582 value = __raw_readl(EP93XX_SYSCON_CLKSET2);
583 if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
584 clk_pll2_rate = EP93XX_EXT_CLK_RATE;
585 else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
586 clk_pll2_rate = calc_pll_rate(EP93XX_EXT_CLK_RATE, value);
587 else
588 clk_pll2_rate = 0;
589
590 hw = clk_hw_register_fixed_rate(NULL, "pll2", "xtali", 0, clk_pll2_rate);
591 clk_hw_register_clkdev(hw, NULL, "pll2");
592
593 /* Initialize the pll2 derived clocks */
594 /*
595 * These four bits set the divide ratio between the PLL2
596 * output and the USB clock.
597 * 0000 - Divide by 1
598 * 0001 - Divide by 2
599 * 0010 - Divide by 3
600 * 0011 - Divide by 4
601 * 0100 - Divide by 5
602 * 0101 - Divide by 6
603 * 0110 - Divide by 7
604 * 0111 - Divide by 8
605 * 1000 - Divide by 9
606 * 1001 - Divide by 10
607 * 1010 - Divide by 11
608 * 1011 - Divide by 12
609 * 1100 - Divide by 13
610 * 1101 - Divide by 14
611 * 1110 - Divide by 15
612 * 1111 - Divide by 1
613 * On power-on-reset these bits are reset to 0000b.
614 */
615 clk_usb_div = (((value >> 28) & 0xf) + 1);
616 hw = clk_hw_register_fixed_factor(NULL, "usb_clk", "pll2", 0, 1, clk_usb_div);
617 hw = clk_hw_register_gate(NULL, "ohci-platform",
618 "usb_clk", 0,
619 EP93XX_SYSCON_PWRCNT,
620 EP93XX_SYSCON_PWRCNT_USH_EN,
621 0,
622 &clk_lock);
623 clk_hw_register_clkdev(hw, NULL, "ohci-platform");
624
625 /*
626 * EP93xx SSP clock rate was doubled in version E2. For more information
627 * see:
628 * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
629 */
630 clk_spi_div = 1;
631 if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2)
632 clk_spi_div = 2;
633 hw = clk_hw_register_fixed_factor(NULL, "ep93xx-spi.0", "xtali", 0, 1, clk_spi_div);
634 clk_hw_register_clkdev(hw, NULL, "ep93xx-spi.0");
635
636 /* pwm clock */
637 hw = clk_hw_register_fixed_factor(NULL, "pwm_clk", "xtali", 0, 1, 1);
638 clk_hw_register_clkdev(hw, "pwm_clk", NULL);
639
640 pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
641 clk_pll1_rate / 1000000, clk_pll2_rate / 1000000);
642 pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
643 clk_f_rate / 1000000, clk_h_rate / 1000000,
644 clk_p_rate / 1000000);
645
646 ep93xx_uart_clock_init();
647
648 /* touchscreen/adc clock */
649 hw = clk_hw_register_div("ep93xx-adc",
650 "xtali",
651 EP93XX_SYSCON_KEYTCHCLKDIV,
652 EP93XX_SYSCON_KEYTCHCLKDIV_TSEN,
653 EP93XX_SYSCON_KEYTCHCLKDIV_ADIV,
654 1,
655 adc_divisors,
656 ARRAY_SIZE(adc_divisors));
657
658 clk_hw_register_clkdev(hw, NULL, "ep93xx-adc");
659
660 /* keypad clock */
661 hw = clk_hw_register_div("ep93xx-keypad",
662 "xtali",
663 EP93XX_SYSCON_KEYTCHCLKDIV,
664 EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
665 EP93XX_SYSCON_KEYTCHCLKDIV_KDIV,
666 1,
667 adc_divisors,
668 ARRAY_SIZE(adc_divisors));
669
670 clk_hw_register_clkdev(hw, NULL, "ep93xx-keypad");
671
672 /* On reset PDIV and VDIV is set to zero, while PDIV zero
673 * means clock disable, VDIV shouldn't be zero.
674 * So i set both dividers to minimum.
675 */
676 /* ENA - Enable CLK divider. */
677 /* PDIV - 00 - Disable clock */
678 /* VDIV - at least 2 */
679 /* Check and enable video clk registers */
680 value = __raw_readl(EP93XX_SYSCON_VIDCLKDIV);
681 value |= (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2;
682 ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_VIDCLKDIV);
683
684 /* check and enable i2s clk registers */
685 value = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
686 value |= (1 << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | 2;
687 ep93xx_syscon_swlocked_write(value, EP93XX_SYSCON_I2SCLKDIV);
688
689 /* video clk */
690 hw = clk_hw_register_ddiv("ep93xx-fb",
691 EP93XX_SYSCON_VIDCLKDIV,
692 EP93XX_SYSCON_CLKDIV_ENABLE);
693
694 clk_hw_register_clkdev(hw, NULL, "ep93xx-fb");
695
696 /* i2s clk */
697 hw = clk_hw_register_ddiv("mclk",
698 EP93XX_SYSCON_I2SCLKDIV,
699 EP93XX_SYSCON_CLKDIV_ENABLE);
700
701 clk_hw_register_clkdev(hw, "mclk", "ep93xx-i2s");
702
703 /* i2s sclk */
704#define EP93XX_I2SCLKDIV_SDIV_SHIFT 16
705#define EP93XX_I2SCLKDIV_SDIV_WIDTH 1
706 hw = clk_hw_register_div("sclk",
707 "mclk",
708 EP93XX_SYSCON_I2SCLKDIV,
709 EP93XX_SYSCON_I2SCLKDIV_SENA,
710 EP93XX_I2SCLKDIV_SDIV_SHIFT,
711 EP93XX_I2SCLKDIV_SDIV_WIDTH,
712 sclk_divisors,
713 ARRAY_SIZE(sclk_divisors));
714
715 clk_hw_register_clkdev(hw, "sclk", "ep93xx-i2s");
716
717 /* i2s lrclk */
718#define EP93XX_I2SCLKDIV_LRDIV32_SHIFT 17
719#define EP93XX_I2SCLKDIV_LRDIV32_WIDTH 3
720 hw = clk_hw_register_div("lrclk",
721 "sclk",
722 EP93XX_SYSCON_I2SCLKDIV,
723 EP93XX_SYSCON_I2SCLKDIV_SENA,
724 EP93XX_I2SCLKDIV_LRDIV32_SHIFT,
725 EP93XX_I2SCLKDIV_LRDIV32_WIDTH,
726 lrclk_divisors,
727 ARRAY_SIZE(lrclk_divisors));
728
729 clk_hw_register_clkdev(hw, "lrclk", "ep93xx-i2s");
730
731 return 0;
732}
733postcore_initcall(ep93xx_clock_init);