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1/*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#include <linux/init.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
34#include <linux/moduleparam.h>
35#include <sound/core.h>
36#include <sound/jack.h>
37#include "hda_codec.h"
38#include "hda_local.h"
39
40static bool static_hdmi_pcm;
41module_param(static_hdmi_pcm, bool, 0644);
42MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
43
44/*
45 * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
46 * could support N independent pipes, each of them can be connected to one or
47 * more ports (DVI, HDMI or DisplayPort).
48 *
49 * The HDA correspondence of pipes/ports are converter/pin nodes.
50 */
51#define MAX_HDMI_CVTS 4
52#define MAX_HDMI_PINS 4
53
54struct hdmi_spec_per_cvt {
55 hda_nid_t cvt_nid;
56 int assigned;
57 unsigned int channels_min;
58 unsigned int channels_max;
59 u32 rates;
60 u64 formats;
61 unsigned int maxbps;
62};
63
64struct hdmi_spec_per_pin {
65 hda_nid_t pin_nid;
66 int num_mux_nids;
67 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
68 struct hdmi_eld sink_eld;
69};
70
71struct hdmi_spec {
72 int num_cvts;
73 struct hdmi_spec_per_cvt cvts[MAX_HDMI_CVTS];
74
75 int num_pins;
76 struct hdmi_spec_per_pin pins[MAX_HDMI_PINS];
77 struct hda_pcm pcm_rec[MAX_HDMI_PINS];
78
79 /*
80 * Non-generic ATI/NVIDIA specific
81 */
82 struct hda_multi_out multiout;
83 const struct hda_pcm_stream *pcm_playback;
84};
85
86
87struct hdmi_audio_infoframe {
88 u8 type; /* 0x84 */
89 u8 ver; /* 0x01 */
90 u8 len; /* 0x0a */
91
92 u8 checksum;
93
94 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
95 u8 SS01_SF24;
96 u8 CXT04;
97 u8 CA;
98 u8 LFEPBL01_LSV36_DM_INH7;
99};
100
101struct dp_audio_infoframe {
102 u8 type; /* 0x84 */
103 u8 len; /* 0x1b */
104 u8 ver; /* 0x11 << 2 */
105
106 u8 CC02_CT47; /* match with HDMI infoframe from this on */
107 u8 SS01_SF24;
108 u8 CXT04;
109 u8 CA;
110 u8 LFEPBL01_LSV36_DM_INH7;
111};
112
113union audio_infoframe {
114 struct hdmi_audio_infoframe hdmi;
115 struct dp_audio_infoframe dp;
116 u8 bytes[0];
117};
118
119/*
120 * CEA speaker placement:
121 *
122 * FLH FCH FRH
123 * FLW FL FLC FC FRC FR FRW
124 *
125 * LFE
126 * TC
127 *
128 * RL RLC RC RRC RR
129 *
130 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
131 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
132 */
133enum cea_speaker_placement {
134 FL = (1 << 0), /* Front Left */
135 FC = (1 << 1), /* Front Center */
136 FR = (1 << 2), /* Front Right */
137 FLC = (1 << 3), /* Front Left Center */
138 FRC = (1 << 4), /* Front Right Center */
139 RL = (1 << 5), /* Rear Left */
140 RC = (1 << 6), /* Rear Center */
141 RR = (1 << 7), /* Rear Right */
142 RLC = (1 << 8), /* Rear Left Center */
143 RRC = (1 << 9), /* Rear Right Center */
144 LFE = (1 << 10), /* Low Frequency Effect */
145 FLW = (1 << 11), /* Front Left Wide */
146 FRW = (1 << 12), /* Front Right Wide */
147 FLH = (1 << 13), /* Front Left High */
148 FCH = (1 << 14), /* Front Center High */
149 FRH = (1 << 15), /* Front Right High */
150 TC = (1 << 16), /* Top Center */
151};
152
153/*
154 * ELD SA bits in the CEA Speaker Allocation data block
155 */
156static int eld_speaker_allocation_bits[] = {
157 [0] = FL | FR,
158 [1] = LFE,
159 [2] = FC,
160 [3] = RL | RR,
161 [4] = RC,
162 [5] = FLC | FRC,
163 [6] = RLC | RRC,
164 /* the following are not defined in ELD yet */
165 [7] = FLW | FRW,
166 [8] = FLH | FRH,
167 [9] = TC,
168 [10] = FCH,
169};
170
171struct cea_channel_speaker_allocation {
172 int ca_index;
173 int speakers[8];
174
175 /* derived values, just for convenience */
176 int channels;
177 int spk_mask;
178};
179
180/*
181 * ALSA sequence is:
182 *
183 * surround40 surround41 surround50 surround51 surround71
184 * ch0 front left = = = =
185 * ch1 front right = = = =
186 * ch2 rear left = = = =
187 * ch3 rear right = = = =
188 * ch4 LFE center center center
189 * ch5 LFE LFE
190 * ch6 side left
191 * ch7 side right
192 *
193 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
194 */
195static int hdmi_channel_mapping[0x32][8] = {
196 /* stereo */
197 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
198 /* 2.1 */
199 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
200 /* Dolby Surround */
201 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
202 /* surround40 */
203 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
204 /* 4ch */
205 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
206 /* surround41 */
207 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
208 /* surround50 */
209 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
210 /* surround51 */
211 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
212 /* 7.1 */
213 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
214};
215
216/*
217 * This is an ordered list!
218 *
219 * The preceding ones have better chances to be selected by
220 * hdmi_channel_allocation().
221 */
222static struct cea_channel_speaker_allocation channel_allocations[] = {
223/* channel: 7 6 5 4 3 2 1 0 */
224{ .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
225 /* 2.1 */
226{ .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
227 /* Dolby Surround */
228{ .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
229 /* surround40 */
230{ .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
231 /* surround41 */
232{ .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
233 /* surround50 */
234{ .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
235 /* surround51 */
236{ .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
237 /* 6.1 */
238{ .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
239 /* surround71 */
240{ .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
241
242{ .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
243{ .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
244{ .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
245{ .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
246{ .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
247{ .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
248{ .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
249{ .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
250{ .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
251{ .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
252{ .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
253{ .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
254{ .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
255{ .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
256{ .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
257{ .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
258{ .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
259{ .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
260{ .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
261{ .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
262{ .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
263{ .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
264{ .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
265{ .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
266{ .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
267{ .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
268{ .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
269{ .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
270{ .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
271{ .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
272{ .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
273{ .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
274{ .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
275{ .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
276{ .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
277{ .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
278{ .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
279{ .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
280{ .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
281{ .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
282{ .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
283};
284
285
286/*
287 * HDMI routines
288 */
289
290static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
291{
292 int pin_idx;
293
294 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
295 if (spec->pins[pin_idx].pin_nid == pin_nid)
296 return pin_idx;
297
298 snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
299 return -EINVAL;
300}
301
302static int hinfo_to_pin_index(struct hdmi_spec *spec,
303 struct hda_pcm_stream *hinfo)
304{
305 int pin_idx;
306
307 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
308 if (&spec->pcm_rec[pin_idx].stream[0] == hinfo)
309 return pin_idx;
310
311 snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
312 return -EINVAL;
313}
314
315static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
316{
317 int cvt_idx;
318
319 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
320 if (spec->cvts[cvt_idx].cvt_nid == cvt_nid)
321 return cvt_idx;
322
323 snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
324 return -EINVAL;
325}
326
327#ifdef BE_PARANOID
328static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
329 int *packet_index, int *byte_index)
330{
331 int val;
332
333 val = snd_hda_codec_read(codec, pin_nid, 0,
334 AC_VERB_GET_HDMI_DIP_INDEX, 0);
335
336 *packet_index = val >> 5;
337 *byte_index = val & 0x1f;
338}
339#endif
340
341static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
342 int packet_index, int byte_index)
343{
344 int val;
345
346 val = (packet_index << 5) | (byte_index & 0x1f);
347
348 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
349}
350
351static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
352 unsigned char val)
353{
354 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
355}
356
357static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
358{
359 /* Unmute */
360 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
361 snd_hda_codec_write(codec, pin_nid, 0,
362 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
363 /* Disable pin out until stream is active*/
364 snd_hda_codec_write(codec, pin_nid, 0,
365 AC_VERB_SET_PIN_WIDGET_CONTROL, 0);
366}
367
368static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
369{
370 return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
371 AC_VERB_GET_CVT_CHAN_COUNT, 0);
372}
373
374static void hdmi_set_channel_count(struct hda_codec *codec,
375 hda_nid_t cvt_nid, int chs)
376{
377 if (chs != hdmi_get_channel_count(codec, cvt_nid))
378 snd_hda_codec_write(codec, cvt_nid, 0,
379 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
380}
381
382
383/*
384 * Channel mapping routines
385 */
386
387/*
388 * Compute derived values in channel_allocations[].
389 */
390static void init_channel_allocations(void)
391{
392 int i, j;
393 struct cea_channel_speaker_allocation *p;
394
395 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
396 p = channel_allocations + i;
397 p->channels = 0;
398 p->spk_mask = 0;
399 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
400 if (p->speakers[j]) {
401 p->channels++;
402 p->spk_mask |= p->speakers[j];
403 }
404 }
405}
406
407/*
408 * The transformation takes two steps:
409 *
410 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
411 * spk_mask => (channel_allocations[]) => ai->CA
412 *
413 * TODO: it could select the wrong CA from multiple candidates.
414*/
415static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
416{
417 int i;
418 int ca = 0;
419 int spk_mask = 0;
420 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
421
422 /*
423 * CA defaults to 0 for basic stereo audio
424 */
425 if (channels <= 2)
426 return 0;
427
428 /*
429 * expand ELD's speaker allocation mask
430 *
431 * ELD tells the speaker mask in a compact(paired) form,
432 * expand ELD's notions to match the ones used by Audio InfoFrame.
433 */
434 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
435 if (eld->spk_alloc & (1 << i))
436 spk_mask |= eld_speaker_allocation_bits[i];
437 }
438
439 /* search for the first working match in the CA table */
440 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
441 if (channels == channel_allocations[i].channels &&
442 (spk_mask & channel_allocations[i].spk_mask) ==
443 channel_allocations[i].spk_mask) {
444 ca = channel_allocations[i].ca_index;
445 break;
446 }
447 }
448
449 snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf));
450 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
451 ca, channels, buf);
452
453 return ca;
454}
455
456static void hdmi_debug_channel_mapping(struct hda_codec *codec,
457 hda_nid_t pin_nid)
458{
459#ifdef CONFIG_SND_DEBUG_VERBOSE
460 int i;
461 int slot;
462
463 for (i = 0; i < 8; i++) {
464 slot = snd_hda_codec_read(codec, pin_nid, 0,
465 AC_VERB_GET_HDMI_CHAN_SLOT, i);
466 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
467 slot >> 4, slot & 0xf);
468 }
469#endif
470}
471
472
473static void hdmi_setup_channel_mapping(struct hda_codec *codec,
474 hda_nid_t pin_nid,
475 int ca)
476{
477 int i;
478 int err;
479
480 if (hdmi_channel_mapping[ca][1] == 0) {
481 for (i = 0; i < channel_allocations[ca].channels; i++)
482 hdmi_channel_mapping[ca][i] = i | (i << 4);
483 for (; i < 8; i++)
484 hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
485 }
486
487 for (i = 0; i < 8; i++) {
488 err = snd_hda_codec_write(codec, pin_nid, 0,
489 AC_VERB_SET_HDMI_CHAN_SLOT,
490 hdmi_channel_mapping[ca][i]);
491 if (err) {
492 snd_printdd(KERN_NOTICE
493 "HDMI: channel mapping failed\n");
494 break;
495 }
496 }
497
498 hdmi_debug_channel_mapping(codec, pin_nid);
499}
500
501
502/*
503 * Audio InfoFrame routines
504 */
505
506/*
507 * Enable Audio InfoFrame Transmission
508 */
509static void hdmi_start_infoframe_trans(struct hda_codec *codec,
510 hda_nid_t pin_nid)
511{
512 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
513 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
514 AC_DIPXMIT_BEST);
515}
516
517/*
518 * Disable Audio InfoFrame Transmission
519 */
520static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
521 hda_nid_t pin_nid)
522{
523 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
524 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
525 AC_DIPXMIT_DISABLE);
526}
527
528static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
529{
530#ifdef CONFIG_SND_DEBUG_VERBOSE
531 int i;
532 int size;
533
534 size = snd_hdmi_get_eld_size(codec, pin_nid);
535 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
536
537 for (i = 0; i < 8; i++) {
538 size = snd_hda_codec_read(codec, pin_nid, 0,
539 AC_VERB_GET_HDMI_DIP_SIZE, i);
540 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
541 }
542#endif
543}
544
545static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
546{
547#ifdef BE_PARANOID
548 int i, j;
549 int size;
550 int pi, bi;
551 for (i = 0; i < 8; i++) {
552 size = snd_hda_codec_read(codec, pin_nid, 0,
553 AC_VERB_GET_HDMI_DIP_SIZE, i);
554 if (size == 0)
555 continue;
556
557 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
558 for (j = 1; j < 1000; j++) {
559 hdmi_write_dip_byte(codec, pin_nid, 0x0);
560 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
561 if (pi != i)
562 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
563 bi, pi, i);
564 if (bi == 0) /* byte index wrapped around */
565 break;
566 }
567 snd_printd(KERN_INFO
568 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
569 i, size, j);
570 }
571#endif
572}
573
574static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
575{
576 u8 *bytes = (u8 *)hdmi_ai;
577 u8 sum = 0;
578 int i;
579
580 hdmi_ai->checksum = 0;
581
582 for (i = 0; i < sizeof(*hdmi_ai); i++)
583 sum += bytes[i];
584
585 hdmi_ai->checksum = -sum;
586}
587
588static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
589 hda_nid_t pin_nid,
590 u8 *dip, int size)
591{
592 int i;
593
594 hdmi_debug_dip_size(codec, pin_nid);
595 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
596
597 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
598 for (i = 0; i < size; i++)
599 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
600}
601
602static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
603 u8 *dip, int size)
604{
605 u8 val;
606 int i;
607
608 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
609 != AC_DIPXMIT_BEST)
610 return false;
611
612 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
613 for (i = 0; i < size; i++) {
614 val = snd_hda_codec_read(codec, pin_nid, 0,
615 AC_VERB_GET_HDMI_DIP_DATA, 0);
616 if (val != dip[i])
617 return false;
618 }
619
620 return true;
621}
622
623static void hdmi_setup_audio_infoframe(struct hda_codec *codec, int pin_idx,
624 struct snd_pcm_substream *substream)
625{
626 struct hdmi_spec *spec = codec->spec;
627 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
628 hda_nid_t pin_nid = per_pin->pin_nid;
629 int channels = substream->runtime->channels;
630 struct hdmi_eld *eld;
631 int ca;
632 union audio_infoframe ai;
633
634 eld = &spec->pins[pin_idx].sink_eld;
635 if (!eld->monitor_present)
636 return;
637
638 ca = hdmi_channel_allocation(eld, channels);
639
640 memset(&ai, 0, sizeof(ai));
641 if (eld->conn_type == 0) { /* HDMI */
642 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
643
644 hdmi_ai->type = 0x84;
645 hdmi_ai->ver = 0x01;
646 hdmi_ai->len = 0x0a;
647 hdmi_ai->CC02_CT47 = channels - 1;
648 hdmi_ai->CA = ca;
649 hdmi_checksum_audio_infoframe(hdmi_ai);
650 } else if (eld->conn_type == 1) { /* DisplayPort */
651 struct dp_audio_infoframe *dp_ai = &ai.dp;
652
653 dp_ai->type = 0x84;
654 dp_ai->len = 0x1b;
655 dp_ai->ver = 0x11 << 2;
656 dp_ai->CC02_CT47 = channels - 1;
657 dp_ai->CA = ca;
658 } else {
659 snd_printd("HDMI: unknown connection type at pin %d\n",
660 pin_nid);
661 return;
662 }
663
664 /*
665 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
666 * sizeof(*dp_ai) to avoid partial match/update problems when
667 * the user switches between HDMI/DP monitors.
668 */
669 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
670 sizeof(ai))) {
671 snd_printdd("hdmi_setup_audio_infoframe: "
672 "pin=%d channels=%d\n",
673 pin_nid,
674 channels);
675 hdmi_setup_channel_mapping(codec, pin_nid, ca);
676 hdmi_stop_infoframe_trans(codec, pin_nid);
677 hdmi_fill_audio_infoframe(codec, pin_nid,
678 ai.bytes, sizeof(ai));
679 hdmi_start_infoframe_trans(codec, pin_nid);
680 }
681}
682
683
684/*
685 * Unsolicited events
686 */
687
688static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid,
689 struct hdmi_eld *eld);
690
691static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
692{
693 struct hdmi_spec *spec = codec->spec;
694 int pin_nid = res >> AC_UNSOL_RES_TAG_SHIFT;
695 int pd = !!(res & AC_UNSOL_RES_PD);
696 int eldv = !!(res & AC_UNSOL_RES_ELDV);
697 int pin_idx;
698 struct hdmi_eld *eld;
699
700 printk(KERN_INFO
701 "HDMI hot plug event: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
702 codec->addr, pin_nid, pd, eldv);
703
704 pin_idx = pin_nid_to_pin_index(spec, pin_nid);
705 if (pin_idx < 0)
706 return;
707 eld = &spec->pins[pin_idx].sink_eld;
708
709 hdmi_present_sense(codec, pin_nid, eld);
710
711 /*
712 * HDMI sink's ELD info cannot always be retrieved for now, e.g.
713 * in console or for audio devices. Assume the highest speakers
714 * configuration, to _not_ prohibit multi-channel audio playback.
715 */
716 if (!eld->spk_alloc)
717 eld->spk_alloc = 0xffff;
718}
719
720static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
721{
722 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
723 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
724 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
725 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
726
727 printk(KERN_INFO
728 "HDMI CP event: CODEC=%d PIN=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
729 codec->addr,
730 tag,
731 subtag,
732 cp_state,
733 cp_ready);
734
735 /* TODO */
736 if (cp_state)
737 ;
738 if (cp_ready)
739 ;
740}
741
742
743static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
744{
745 struct hdmi_spec *spec = codec->spec;
746 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
747 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
748
749 if (pin_nid_to_pin_index(spec, tag) < 0) {
750 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
751 return;
752 }
753
754 if (subtag == 0)
755 hdmi_intrinsic_event(codec, res);
756 else
757 hdmi_non_intrinsic_event(codec, res);
758}
759
760/*
761 * Callbacks
762 */
763
764/* HBR should be Non-PCM, 8 channels */
765#define is_hbr_format(format) \
766 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
767
768static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
769 hda_nid_t pin_nid, u32 stream_tag, int format)
770{
771 int pinctl;
772 int new_pinctl = 0;
773
774 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
775 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
776 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
777
778 new_pinctl = pinctl & ~AC_PINCTL_EPT;
779 if (is_hbr_format(format))
780 new_pinctl |= AC_PINCTL_EPT_HBR;
781 else
782 new_pinctl |= AC_PINCTL_EPT_NATIVE;
783
784 snd_printdd("hdmi_setup_stream: "
785 "NID=0x%x, %spinctl=0x%x\n",
786 pin_nid,
787 pinctl == new_pinctl ? "" : "new-",
788 new_pinctl);
789
790 if (pinctl != new_pinctl)
791 snd_hda_codec_write(codec, pin_nid, 0,
792 AC_VERB_SET_PIN_WIDGET_CONTROL,
793 new_pinctl);
794
795 }
796 if (is_hbr_format(format) && !new_pinctl) {
797 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
798 return -EINVAL;
799 }
800
801 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
802 return 0;
803}
804
805/*
806 * HDA PCM callbacks
807 */
808static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
809 struct hda_codec *codec,
810 struct snd_pcm_substream *substream)
811{
812 struct hdmi_spec *spec = codec->spec;
813 struct snd_pcm_runtime *runtime = substream->runtime;
814 int pin_idx, cvt_idx, mux_idx = 0;
815 struct hdmi_spec_per_pin *per_pin;
816 struct hdmi_eld *eld;
817 struct hdmi_spec_per_cvt *per_cvt = NULL;
818 int pinctl;
819
820 /* Validate hinfo */
821 pin_idx = hinfo_to_pin_index(spec, hinfo);
822 if (snd_BUG_ON(pin_idx < 0))
823 return -EINVAL;
824 per_pin = &spec->pins[pin_idx];
825 eld = &per_pin->sink_eld;
826
827 /* Dynamically assign converter to stream */
828 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
829 per_cvt = &spec->cvts[cvt_idx];
830
831 /* Must not already be assigned */
832 if (per_cvt->assigned)
833 continue;
834 /* Must be in pin's mux's list of converters */
835 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
836 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
837 break;
838 /* Not in mux list */
839 if (mux_idx == per_pin->num_mux_nids)
840 continue;
841 break;
842 }
843 /* No free converters */
844 if (cvt_idx == spec->num_cvts)
845 return -ENODEV;
846
847 /* Claim converter */
848 per_cvt->assigned = 1;
849 hinfo->nid = per_cvt->cvt_nid;
850
851 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
852 AC_VERB_SET_CONNECT_SEL,
853 mux_idx);
854 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
855 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
856 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
857 AC_VERB_SET_PIN_WIDGET_CONTROL,
858 pinctl | PIN_OUT);
859 snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
860
861 /* Initially set the converter's capabilities */
862 hinfo->channels_min = per_cvt->channels_min;
863 hinfo->channels_max = per_cvt->channels_max;
864 hinfo->rates = per_cvt->rates;
865 hinfo->formats = per_cvt->formats;
866 hinfo->maxbps = per_cvt->maxbps;
867
868 /* Restrict capabilities by ELD if this isn't disabled */
869 if (!static_hdmi_pcm && eld->eld_valid) {
870 snd_hdmi_eld_update_pcm_info(eld, hinfo);
871 if (hinfo->channels_min > hinfo->channels_max ||
872 !hinfo->rates || !hinfo->formats)
873 return -ENODEV;
874 }
875
876 /* Store the updated parameters */
877 runtime->hw.channels_min = hinfo->channels_min;
878 runtime->hw.channels_max = hinfo->channels_max;
879 runtime->hw.formats = hinfo->formats;
880 runtime->hw.rates = hinfo->rates;
881
882 snd_pcm_hw_constraint_step(substream->runtime, 0,
883 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
884 return 0;
885}
886
887/*
888 * HDA/HDMI auto parsing
889 */
890static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
891{
892 struct hdmi_spec *spec = codec->spec;
893 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
894 hda_nid_t pin_nid = per_pin->pin_nid;
895
896 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
897 snd_printk(KERN_WARNING
898 "HDMI: pin %d wcaps %#x "
899 "does not support connection list\n",
900 pin_nid, get_wcaps(codec, pin_nid));
901 return -EINVAL;
902 }
903
904 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
905 per_pin->mux_nids,
906 HDA_MAX_CONNECTIONS);
907
908 return 0;
909}
910
911static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid,
912 struct hdmi_eld *eld)
913{
914 /*
915 * Always execute a GetPinSense verb here, even when called from
916 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
917 * response's PD bit is not the real PD value, but indicates that
918 * the real PD value changed. An older version of the HD-audio
919 * specification worked this way. Hence, we just ignore the data in
920 * the unsolicited response to avoid custom WARs.
921 */
922 int present = snd_hda_pin_sense(codec, pin_nid);
923
924 memset(eld, 0, sizeof(*eld));
925
926 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
927 if (eld->monitor_present)
928 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
929 else
930 eld->eld_valid = 0;
931
932 printk(KERN_INFO
933 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
934 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
935
936 if (eld->eld_valid)
937 if (!snd_hdmi_get_eld(eld, codec, pin_nid))
938 snd_hdmi_show_eld(eld);
939
940 snd_hda_input_jack_report(codec, pin_nid);
941}
942
943static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
944{
945 struct hdmi_spec *spec = codec->spec;
946 unsigned int caps, config;
947 int pin_idx;
948 struct hdmi_spec_per_pin *per_pin;
949 struct hdmi_eld *eld;
950 int err;
951
952 caps = snd_hda_param_read(codec, pin_nid, AC_PAR_PIN_CAP);
953 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
954 return 0;
955
956 config = snd_hda_codec_read(codec, pin_nid, 0,
957 AC_VERB_GET_CONFIG_DEFAULT, 0);
958 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
959 return 0;
960
961 if (snd_BUG_ON(spec->num_pins >= MAX_HDMI_PINS))
962 return -E2BIG;
963
964 pin_idx = spec->num_pins;
965 per_pin = &spec->pins[pin_idx];
966 eld = &per_pin->sink_eld;
967
968 per_pin->pin_nid = pin_nid;
969
970 err = snd_hda_input_jack_add(codec, pin_nid,
971 SND_JACK_VIDEOOUT, NULL);
972 if (err < 0)
973 return err;
974
975 err = hdmi_read_pin_conn(codec, pin_idx);
976 if (err < 0)
977 return err;
978
979 spec->num_pins++;
980
981 hdmi_present_sense(codec, pin_nid, eld);
982
983 return 0;
984}
985
986static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
987{
988 struct hdmi_spec *spec = codec->spec;
989 int cvt_idx;
990 struct hdmi_spec_per_cvt *per_cvt;
991 unsigned int chans;
992 int err;
993
994 if (snd_BUG_ON(spec->num_cvts >= MAX_HDMI_CVTS))
995 return -E2BIG;
996
997 chans = get_wcaps(codec, cvt_nid);
998 chans = get_wcaps_channels(chans);
999
1000 cvt_idx = spec->num_cvts;
1001 per_cvt = &spec->cvts[cvt_idx];
1002
1003 per_cvt->cvt_nid = cvt_nid;
1004 per_cvt->channels_min = 2;
1005 if (chans <= 16)
1006 per_cvt->channels_max = chans;
1007
1008 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1009 &per_cvt->rates,
1010 &per_cvt->formats,
1011 &per_cvt->maxbps);
1012 if (err < 0)
1013 return err;
1014
1015 spec->num_cvts++;
1016
1017 return 0;
1018}
1019
1020static int hdmi_parse_codec(struct hda_codec *codec)
1021{
1022 hda_nid_t nid;
1023 int i, nodes;
1024
1025 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
1026 if (!nid || nodes < 0) {
1027 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
1028 return -EINVAL;
1029 }
1030
1031 for (i = 0; i < nodes; i++, nid++) {
1032 unsigned int caps;
1033 unsigned int type;
1034
1035 caps = snd_hda_param_read(codec, nid, AC_PAR_AUDIO_WIDGET_CAP);
1036 type = get_wcaps_type(caps);
1037
1038 if (!(caps & AC_WCAP_DIGITAL))
1039 continue;
1040
1041 switch (type) {
1042 case AC_WID_AUD_OUT:
1043 hdmi_add_cvt(codec, nid);
1044 break;
1045 case AC_WID_PIN:
1046 hdmi_add_pin(codec, nid);
1047 break;
1048 }
1049 }
1050
1051 /*
1052 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1053 * can be lost and presence sense verb will become inaccurate if the
1054 * HDA link is powered off at hot plug or hw initialization time.
1055 */
1056#ifdef CONFIG_SND_HDA_POWER_SAVE
1057 if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
1058 AC_PWRST_EPSS))
1059 codec->bus->power_keep_link_on = 1;
1060#endif
1061
1062 return 0;
1063}
1064
1065/*
1066 */
1067static char *generic_hdmi_pcm_names[MAX_HDMI_PINS] = {
1068 "HDMI 0",
1069 "HDMI 1",
1070 "HDMI 2",
1071 "HDMI 3",
1072};
1073
1074/*
1075 * HDMI callbacks
1076 */
1077
1078static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1079 struct hda_codec *codec,
1080 unsigned int stream_tag,
1081 unsigned int format,
1082 struct snd_pcm_substream *substream)
1083{
1084 hda_nid_t cvt_nid = hinfo->nid;
1085 struct hdmi_spec *spec = codec->spec;
1086 int pin_idx = hinfo_to_pin_index(spec, hinfo);
1087 hda_nid_t pin_nid = spec->pins[pin_idx].pin_nid;
1088
1089 hdmi_set_channel_count(codec, cvt_nid, substream->runtime->channels);
1090
1091 hdmi_setup_audio_infoframe(codec, pin_idx, substream);
1092
1093 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
1094}
1095
1096static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1097 struct hda_codec *codec,
1098 struct snd_pcm_substream *substream)
1099{
1100 struct hdmi_spec *spec = codec->spec;
1101 int cvt_idx, pin_idx;
1102 struct hdmi_spec_per_cvt *per_cvt;
1103 struct hdmi_spec_per_pin *per_pin;
1104 int pinctl;
1105
1106 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1107
1108 if (hinfo->nid) {
1109 cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
1110 if (snd_BUG_ON(cvt_idx < 0))
1111 return -EINVAL;
1112 per_cvt = &spec->cvts[cvt_idx];
1113
1114 snd_BUG_ON(!per_cvt->assigned);
1115 per_cvt->assigned = 0;
1116 hinfo->nid = 0;
1117
1118 pin_idx = hinfo_to_pin_index(spec, hinfo);
1119 if (snd_BUG_ON(pin_idx < 0))
1120 return -EINVAL;
1121 per_pin = &spec->pins[pin_idx];
1122
1123 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1124 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1125 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1126 AC_VERB_SET_PIN_WIDGET_CONTROL,
1127 pinctl & ~PIN_OUT);
1128 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1129 }
1130
1131 return 0;
1132}
1133
1134static const struct hda_pcm_ops generic_ops = {
1135 .open = hdmi_pcm_open,
1136 .prepare = generic_hdmi_playback_pcm_prepare,
1137 .cleanup = generic_hdmi_playback_pcm_cleanup,
1138};
1139
1140static int generic_hdmi_build_pcms(struct hda_codec *codec)
1141{
1142 struct hdmi_spec *spec = codec->spec;
1143 int pin_idx;
1144
1145 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1146 struct hda_pcm *info;
1147 struct hda_pcm_stream *pstr;
1148
1149 info = &spec->pcm_rec[pin_idx];
1150 info->name = generic_hdmi_pcm_names[pin_idx];
1151 info->pcm_type = HDA_PCM_TYPE_HDMI;
1152
1153 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1154 pstr->substreams = 1;
1155 pstr->ops = generic_ops;
1156 /* other pstr fields are set in open */
1157 }
1158
1159 codec->num_pcms = spec->num_pins;
1160 codec->pcm_info = spec->pcm_rec;
1161
1162 return 0;
1163}
1164
1165static int generic_hdmi_build_controls(struct hda_codec *codec)
1166{
1167 struct hdmi_spec *spec = codec->spec;
1168 int err;
1169 int pin_idx;
1170
1171 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1172 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1173 err = snd_hda_create_spdif_out_ctls(codec,
1174 per_pin->pin_nid,
1175 per_pin->mux_nids[0]);
1176 if (err < 0)
1177 return err;
1178 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1179 }
1180
1181 return 0;
1182}
1183
1184static int generic_hdmi_init(struct hda_codec *codec)
1185{
1186 struct hdmi_spec *spec = codec->spec;
1187 int pin_idx;
1188
1189 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1190 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1191 hda_nid_t pin_nid = per_pin->pin_nid;
1192 struct hdmi_eld *eld = &per_pin->sink_eld;
1193
1194 hdmi_init_pin(codec, pin_nid);
1195 snd_hda_codec_write(codec, pin_nid, 0,
1196 AC_VERB_SET_UNSOLICITED_ENABLE,
1197 AC_USRSP_EN | pin_nid);
1198
1199 snd_hda_eld_proc_new(codec, eld, pin_idx);
1200 }
1201 return 0;
1202}
1203
1204static void generic_hdmi_free(struct hda_codec *codec)
1205{
1206 struct hdmi_spec *spec = codec->spec;
1207 int pin_idx;
1208
1209 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1210 struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
1211 struct hdmi_eld *eld = &per_pin->sink_eld;
1212
1213 snd_hda_eld_proc_free(codec, eld);
1214 }
1215 snd_hda_input_jack_free(codec);
1216
1217 kfree(spec);
1218}
1219
1220static const struct hda_codec_ops generic_hdmi_patch_ops = {
1221 .init = generic_hdmi_init,
1222 .free = generic_hdmi_free,
1223 .build_pcms = generic_hdmi_build_pcms,
1224 .build_controls = generic_hdmi_build_controls,
1225 .unsol_event = hdmi_unsol_event,
1226};
1227
1228static int patch_generic_hdmi(struct hda_codec *codec)
1229{
1230 struct hdmi_spec *spec;
1231
1232 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1233 if (spec == NULL)
1234 return -ENOMEM;
1235
1236 codec->spec = spec;
1237 if (hdmi_parse_codec(codec) < 0) {
1238 codec->spec = NULL;
1239 kfree(spec);
1240 return -EINVAL;
1241 }
1242 codec->patch_ops = generic_hdmi_patch_ops;
1243
1244 init_channel_allocations();
1245
1246 return 0;
1247}
1248
1249/*
1250 * Shared non-generic implementations
1251 */
1252
1253static int simple_playback_build_pcms(struct hda_codec *codec)
1254{
1255 struct hdmi_spec *spec = codec->spec;
1256 struct hda_pcm *info = spec->pcm_rec;
1257 int i;
1258
1259 codec->num_pcms = spec->num_cvts;
1260 codec->pcm_info = info;
1261
1262 for (i = 0; i < codec->num_pcms; i++, info++) {
1263 unsigned int chans;
1264 struct hda_pcm_stream *pstr;
1265
1266 chans = get_wcaps(codec, spec->cvts[i].cvt_nid);
1267 chans = get_wcaps_channels(chans);
1268
1269 info->name = generic_hdmi_pcm_names[i];
1270 info->pcm_type = HDA_PCM_TYPE_HDMI;
1271 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1272 snd_BUG_ON(!spec->pcm_playback);
1273 *pstr = *spec->pcm_playback;
1274 pstr->nid = spec->cvts[i].cvt_nid;
1275 if (pstr->channels_max <= 2 && chans && chans <= 16)
1276 pstr->channels_max = chans;
1277 }
1278
1279 return 0;
1280}
1281
1282static int simple_playback_build_controls(struct hda_codec *codec)
1283{
1284 struct hdmi_spec *spec = codec->spec;
1285 int err;
1286 int i;
1287
1288 for (i = 0; i < codec->num_pcms; i++) {
1289 err = snd_hda_create_spdif_out_ctls(codec,
1290 spec->cvts[i].cvt_nid,
1291 spec->cvts[i].cvt_nid);
1292 if (err < 0)
1293 return err;
1294 }
1295
1296 return 0;
1297}
1298
1299static void simple_playback_free(struct hda_codec *codec)
1300{
1301 struct hdmi_spec *spec = codec->spec;
1302
1303 kfree(spec);
1304}
1305
1306/*
1307 * Nvidia specific implementations
1308 */
1309
1310#define Nv_VERB_SET_Channel_Allocation 0xF79
1311#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
1312#define Nv_VERB_SET_Audio_Protection_On 0xF98
1313#define Nv_VERB_SET_Audio_Protection_Off 0xF99
1314
1315#define nvhdmi_master_con_nid_7x 0x04
1316#define nvhdmi_master_pin_nid_7x 0x05
1317
1318static const hda_nid_t nvhdmi_con_nids_7x[4] = {
1319 /*front, rear, clfe, rear_surr */
1320 0x6, 0x8, 0xa, 0xc,
1321};
1322
1323static const struct hda_verb nvhdmi_basic_init_7x[] = {
1324 /* set audio protect on */
1325 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
1326 /* enable digital output on pin widget */
1327 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1328 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1329 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1330 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1331 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1332 {} /* terminator */
1333};
1334
1335#ifdef LIMITED_RATE_FMT_SUPPORT
1336/* support only the safe format and rate */
1337#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
1338#define SUPPORTED_MAXBPS 16
1339#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1340#else
1341/* support all rates and formats */
1342#define SUPPORTED_RATES \
1343 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
1344 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
1345 SNDRV_PCM_RATE_192000)
1346#define SUPPORTED_MAXBPS 24
1347#define SUPPORTED_FORMATS \
1348 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1349#endif
1350
1351static int nvhdmi_7x_init(struct hda_codec *codec)
1352{
1353 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x);
1354 return 0;
1355}
1356
1357static unsigned int channels_2_6_8[] = {
1358 2, 6, 8
1359};
1360
1361static unsigned int channels_2_8[] = {
1362 2, 8
1363};
1364
1365static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
1366 .count = ARRAY_SIZE(channels_2_6_8),
1367 .list = channels_2_6_8,
1368 .mask = 0,
1369};
1370
1371static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
1372 .count = ARRAY_SIZE(channels_2_8),
1373 .list = channels_2_8,
1374 .mask = 0,
1375};
1376
1377static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
1378 struct hda_codec *codec,
1379 struct snd_pcm_substream *substream)
1380{
1381 struct hdmi_spec *spec = codec->spec;
1382 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
1383
1384 switch (codec->preset->id) {
1385 case 0x10de0002:
1386 case 0x10de0003:
1387 case 0x10de0005:
1388 case 0x10de0006:
1389 hw_constraints_channels = &hw_constraints_2_8_channels;
1390 break;
1391 case 0x10de0007:
1392 hw_constraints_channels = &hw_constraints_2_6_8_channels;
1393 break;
1394 default:
1395 break;
1396 }
1397
1398 if (hw_constraints_channels != NULL) {
1399 snd_pcm_hw_constraint_list(substream->runtime, 0,
1400 SNDRV_PCM_HW_PARAM_CHANNELS,
1401 hw_constraints_channels);
1402 } else {
1403 snd_pcm_hw_constraint_step(substream->runtime, 0,
1404 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1405 }
1406
1407 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
1408}
1409
1410static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
1411 struct hda_codec *codec,
1412 struct snd_pcm_substream *substream)
1413{
1414 struct hdmi_spec *spec = codec->spec;
1415 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1416}
1417
1418static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1419 struct hda_codec *codec,
1420 unsigned int stream_tag,
1421 unsigned int format,
1422 struct snd_pcm_substream *substream)
1423{
1424 struct hdmi_spec *spec = codec->spec;
1425 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
1426 stream_tag, format, substream);
1427}
1428
1429static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
1430 int channels)
1431{
1432 unsigned int chanmask;
1433 int chan = channels ? (channels - 1) : 1;
1434
1435 switch (channels) {
1436 default:
1437 case 0:
1438 case 2:
1439 chanmask = 0x00;
1440 break;
1441 case 4:
1442 chanmask = 0x08;
1443 break;
1444 case 6:
1445 chanmask = 0x0b;
1446 break;
1447 case 8:
1448 chanmask = 0x13;
1449 break;
1450 }
1451
1452 /* Set the audio infoframe channel allocation and checksum fields. The
1453 * channel count is computed implicitly by the hardware. */
1454 snd_hda_codec_write(codec, 0x1, 0,
1455 Nv_VERB_SET_Channel_Allocation, chanmask);
1456
1457 snd_hda_codec_write(codec, 0x1, 0,
1458 Nv_VERB_SET_Info_Frame_Checksum,
1459 (0x71 - chan - chanmask));
1460}
1461
1462static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
1463 struct hda_codec *codec,
1464 struct snd_pcm_substream *substream)
1465{
1466 struct hdmi_spec *spec = codec->spec;
1467 int i;
1468
1469 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
1470 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
1471 for (i = 0; i < 4; i++) {
1472 /* set the stream id */
1473 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1474 AC_VERB_SET_CHANNEL_STREAMID, 0);
1475 /* set the stream format */
1476 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1477 AC_VERB_SET_STREAM_FORMAT, 0);
1478 }
1479
1480 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
1481 * streams are disabled. */
1482 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
1483
1484 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1485}
1486
1487static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
1488 struct hda_codec *codec,
1489 unsigned int stream_tag,
1490 unsigned int format,
1491 struct snd_pcm_substream *substream)
1492{
1493 int chs;
1494 unsigned int dataDCC1, dataDCC2, channel_id;
1495 int i;
1496 struct hdmi_spec *spec = codec->spec;
1497 struct hda_spdif_out *spdif =
1498 snd_hda_spdif_out_of_nid(codec, spec->cvts[0].cvt_nid);
1499
1500 mutex_lock(&codec->spdif_mutex);
1501
1502 chs = substream->runtime->channels;
1503
1504 dataDCC1 = AC_DIG1_ENABLE | AC_DIG1_COPYRIGHT;
1505 dataDCC2 = 0x2;
1506
1507 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
1508 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
1509 snd_hda_codec_write(codec,
1510 nvhdmi_master_con_nid_7x,
1511 0,
1512 AC_VERB_SET_DIGI_CONVERT_1,
1513 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
1514
1515 /* set the stream id */
1516 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1517 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
1518
1519 /* set the stream format */
1520 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1521 AC_VERB_SET_STREAM_FORMAT, format);
1522
1523 /* turn on again (if needed) */
1524 /* enable and set the channel status audio/data flag */
1525 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
1526 snd_hda_codec_write(codec,
1527 nvhdmi_master_con_nid_7x,
1528 0,
1529 AC_VERB_SET_DIGI_CONVERT_1,
1530 spdif->ctls & 0xff);
1531 snd_hda_codec_write(codec,
1532 nvhdmi_master_con_nid_7x,
1533 0,
1534 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1535 }
1536
1537 for (i = 0; i < 4; i++) {
1538 if (chs == 2)
1539 channel_id = 0;
1540 else
1541 channel_id = i * 2;
1542
1543 /* turn off SPDIF once;
1544 *otherwise the IEC958 bits won't be updated
1545 */
1546 if (codec->spdif_status_reset &&
1547 (spdif->ctls & AC_DIG1_ENABLE))
1548 snd_hda_codec_write(codec,
1549 nvhdmi_con_nids_7x[i],
1550 0,
1551 AC_VERB_SET_DIGI_CONVERT_1,
1552 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
1553 /* set the stream id */
1554 snd_hda_codec_write(codec,
1555 nvhdmi_con_nids_7x[i],
1556 0,
1557 AC_VERB_SET_CHANNEL_STREAMID,
1558 (stream_tag << 4) | channel_id);
1559 /* set the stream format */
1560 snd_hda_codec_write(codec,
1561 nvhdmi_con_nids_7x[i],
1562 0,
1563 AC_VERB_SET_STREAM_FORMAT,
1564 format);
1565 /* turn on again (if needed) */
1566 /* enable and set the channel status audio/data flag */
1567 if (codec->spdif_status_reset &&
1568 (spdif->ctls & AC_DIG1_ENABLE)) {
1569 snd_hda_codec_write(codec,
1570 nvhdmi_con_nids_7x[i],
1571 0,
1572 AC_VERB_SET_DIGI_CONVERT_1,
1573 spdif->ctls & 0xff);
1574 snd_hda_codec_write(codec,
1575 nvhdmi_con_nids_7x[i],
1576 0,
1577 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1578 }
1579 }
1580
1581 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
1582
1583 mutex_unlock(&codec->spdif_mutex);
1584 return 0;
1585}
1586
1587static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
1588 .substreams = 1,
1589 .channels_min = 2,
1590 .channels_max = 8,
1591 .nid = nvhdmi_master_con_nid_7x,
1592 .rates = SUPPORTED_RATES,
1593 .maxbps = SUPPORTED_MAXBPS,
1594 .formats = SUPPORTED_FORMATS,
1595 .ops = {
1596 .open = simple_playback_pcm_open,
1597 .close = nvhdmi_8ch_7x_pcm_close,
1598 .prepare = nvhdmi_8ch_7x_pcm_prepare
1599 },
1600};
1601
1602static const struct hda_pcm_stream nvhdmi_pcm_playback_2ch = {
1603 .substreams = 1,
1604 .channels_min = 2,
1605 .channels_max = 2,
1606 .nid = nvhdmi_master_con_nid_7x,
1607 .rates = SUPPORTED_RATES,
1608 .maxbps = SUPPORTED_MAXBPS,
1609 .formats = SUPPORTED_FORMATS,
1610 .ops = {
1611 .open = simple_playback_pcm_open,
1612 .close = simple_playback_pcm_close,
1613 .prepare = simple_playback_pcm_prepare
1614 },
1615};
1616
1617static const struct hda_codec_ops nvhdmi_patch_ops_8ch_7x = {
1618 .build_controls = simple_playback_build_controls,
1619 .build_pcms = simple_playback_build_pcms,
1620 .init = nvhdmi_7x_init,
1621 .free = simple_playback_free,
1622};
1623
1624static const struct hda_codec_ops nvhdmi_patch_ops_2ch = {
1625 .build_controls = simple_playback_build_controls,
1626 .build_pcms = simple_playback_build_pcms,
1627 .init = nvhdmi_7x_init,
1628 .free = simple_playback_free,
1629};
1630
1631static int patch_nvhdmi_2ch(struct hda_codec *codec)
1632{
1633 struct hdmi_spec *spec;
1634
1635 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1636 if (spec == NULL)
1637 return -ENOMEM;
1638
1639 codec->spec = spec;
1640
1641 spec->multiout.num_dacs = 0; /* no analog */
1642 spec->multiout.max_channels = 2;
1643 spec->multiout.dig_out_nid = nvhdmi_master_con_nid_7x;
1644 spec->num_cvts = 1;
1645 spec->cvts[0].cvt_nid = nvhdmi_master_con_nid_7x;
1646 spec->pcm_playback = &nvhdmi_pcm_playback_2ch;
1647
1648 codec->patch_ops = nvhdmi_patch_ops_2ch;
1649
1650 return 0;
1651}
1652
1653static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
1654{
1655 struct hdmi_spec *spec;
1656 int err = patch_nvhdmi_2ch(codec);
1657
1658 if (err < 0)
1659 return err;
1660 spec = codec->spec;
1661 spec->multiout.max_channels = 8;
1662 spec->pcm_playback = &nvhdmi_pcm_playback_8ch_7x;
1663 codec->patch_ops = nvhdmi_patch_ops_8ch_7x;
1664
1665 /* Initialize the audio infoframe channel mask and checksum to something
1666 * valid */
1667 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
1668
1669 return 0;
1670}
1671
1672/*
1673 * ATI-specific implementations
1674 *
1675 * FIXME: we may omit the whole this and use the generic code once after
1676 * it's confirmed to work.
1677 */
1678
1679#define ATIHDMI_CVT_NID 0x02 /* audio converter */
1680#define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
1681
1682static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1683 struct hda_codec *codec,
1684 unsigned int stream_tag,
1685 unsigned int format,
1686 struct snd_pcm_substream *substream)
1687{
1688 struct hdmi_spec *spec = codec->spec;
1689 int chans = substream->runtime->channels;
1690 int i, err;
1691
1692 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
1693 substream);
1694 if (err < 0)
1695 return err;
1696 snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
1697 AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
1698 /* FIXME: XXX */
1699 for (i = 0; i < chans; i++) {
1700 snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
1701 AC_VERB_SET_HDMI_CHAN_SLOT,
1702 (i << 4) | i);
1703 }
1704 return 0;
1705}
1706
1707static const struct hda_pcm_stream atihdmi_pcm_digital_playback = {
1708 .substreams = 1,
1709 .channels_min = 2,
1710 .channels_max = 2,
1711 .nid = ATIHDMI_CVT_NID,
1712 .ops = {
1713 .open = simple_playback_pcm_open,
1714 .close = simple_playback_pcm_close,
1715 .prepare = atihdmi_playback_pcm_prepare
1716 },
1717};
1718
1719static const struct hda_verb atihdmi_basic_init[] = {
1720 /* enable digital output on pin widget */
1721 { 0x03, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT },
1722 {} /* terminator */
1723};
1724
1725static int atihdmi_init(struct hda_codec *codec)
1726{
1727 struct hdmi_spec *spec = codec->spec;
1728
1729 snd_hda_sequence_write(codec, atihdmi_basic_init);
1730 /* SI codec requires to unmute the pin */
1731 if (get_wcaps(codec, spec->pins[0].pin_nid) & AC_WCAP_OUT_AMP)
1732 snd_hda_codec_write(codec, spec->pins[0].pin_nid, 0,
1733 AC_VERB_SET_AMP_GAIN_MUTE,
1734 AMP_OUT_UNMUTE);
1735 return 0;
1736}
1737
1738static const struct hda_codec_ops atihdmi_patch_ops = {
1739 .build_controls = simple_playback_build_controls,
1740 .build_pcms = simple_playback_build_pcms,
1741 .init = atihdmi_init,
1742 .free = simple_playback_free,
1743};
1744
1745
1746static int patch_atihdmi(struct hda_codec *codec)
1747{
1748 struct hdmi_spec *spec;
1749
1750 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1751 if (spec == NULL)
1752 return -ENOMEM;
1753
1754 codec->spec = spec;
1755
1756 spec->multiout.num_dacs = 0; /* no analog */
1757 spec->multiout.max_channels = 2;
1758 spec->multiout.dig_out_nid = ATIHDMI_CVT_NID;
1759 spec->num_cvts = 1;
1760 spec->cvts[0].cvt_nid = ATIHDMI_CVT_NID;
1761 spec->pins[0].pin_nid = ATIHDMI_PIN_NID;
1762 spec->pcm_playback = &atihdmi_pcm_digital_playback;
1763
1764 codec->patch_ops = atihdmi_patch_ops;
1765
1766 return 0;
1767}
1768
1769
1770/*
1771 * patch entries
1772 */
1773static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
1774{ .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
1775{ .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
1776{ .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
1777{ .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
1778{ .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
1779{ .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
1780{ .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
1781{ .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1782{ .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1783{ .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1784{ .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1785{ .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
1786{ .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
1787{ .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
1788{ .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
1789{ .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
1790{ .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
1791{ .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
1792{ .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
1793{ .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
1794{ .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
1795{ .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
1796{ .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
1797/* 17 is known to be absent */
1798{ .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
1799{ .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
1800{ .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
1801{ .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
1802{ .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
1803{ .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
1804{ .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
1805{ .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
1806{ .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
1807{ .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
1808{ .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
1809{ .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
1810{ .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1811{ .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
1812{ .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
1813{ .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
1814{ .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1815{ .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
1816{ .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
1817{ .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
1818{} /* terminator */
1819};
1820
1821MODULE_ALIAS("snd-hda-codec-id:1002793c");
1822MODULE_ALIAS("snd-hda-codec-id:10027919");
1823MODULE_ALIAS("snd-hda-codec-id:1002791a");
1824MODULE_ALIAS("snd-hda-codec-id:1002aa01");
1825MODULE_ALIAS("snd-hda-codec-id:10951390");
1826MODULE_ALIAS("snd-hda-codec-id:10951392");
1827MODULE_ALIAS("snd-hda-codec-id:10de0002");
1828MODULE_ALIAS("snd-hda-codec-id:10de0003");
1829MODULE_ALIAS("snd-hda-codec-id:10de0005");
1830MODULE_ALIAS("snd-hda-codec-id:10de0006");
1831MODULE_ALIAS("snd-hda-codec-id:10de0007");
1832MODULE_ALIAS("snd-hda-codec-id:10de000a");
1833MODULE_ALIAS("snd-hda-codec-id:10de000b");
1834MODULE_ALIAS("snd-hda-codec-id:10de000c");
1835MODULE_ALIAS("snd-hda-codec-id:10de000d");
1836MODULE_ALIAS("snd-hda-codec-id:10de0010");
1837MODULE_ALIAS("snd-hda-codec-id:10de0011");
1838MODULE_ALIAS("snd-hda-codec-id:10de0012");
1839MODULE_ALIAS("snd-hda-codec-id:10de0013");
1840MODULE_ALIAS("snd-hda-codec-id:10de0014");
1841MODULE_ALIAS("snd-hda-codec-id:10de0015");
1842MODULE_ALIAS("snd-hda-codec-id:10de0016");
1843MODULE_ALIAS("snd-hda-codec-id:10de0018");
1844MODULE_ALIAS("snd-hda-codec-id:10de0019");
1845MODULE_ALIAS("snd-hda-codec-id:10de001a");
1846MODULE_ALIAS("snd-hda-codec-id:10de001b");
1847MODULE_ALIAS("snd-hda-codec-id:10de001c");
1848MODULE_ALIAS("snd-hda-codec-id:10de0040");
1849MODULE_ALIAS("snd-hda-codec-id:10de0041");
1850MODULE_ALIAS("snd-hda-codec-id:10de0042");
1851MODULE_ALIAS("snd-hda-codec-id:10de0043");
1852MODULE_ALIAS("snd-hda-codec-id:10de0044");
1853MODULE_ALIAS("snd-hda-codec-id:10de0067");
1854MODULE_ALIAS("snd-hda-codec-id:10de8001");
1855MODULE_ALIAS("snd-hda-codec-id:17e80047");
1856MODULE_ALIAS("snd-hda-codec-id:80860054");
1857MODULE_ALIAS("snd-hda-codec-id:80862801");
1858MODULE_ALIAS("snd-hda-codec-id:80862802");
1859MODULE_ALIAS("snd-hda-codec-id:80862803");
1860MODULE_ALIAS("snd-hda-codec-id:80862804");
1861MODULE_ALIAS("snd-hda-codec-id:80862805");
1862MODULE_ALIAS("snd-hda-codec-id:80862806");
1863MODULE_ALIAS("snd-hda-codec-id:808629fb");
1864
1865MODULE_LICENSE("GPL");
1866MODULE_DESCRIPTION("HDMI HD-audio codec");
1867MODULE_ALIAS("snd-hda-codec-intelhdmi");
1868MODULE_ALIAS("snd-hda-codec-nvhdmi");
1869MODULE_ALIAS("snd-hda-codec-atihdmi");
1870
1871static struct hda_codec_preset_list intel_list = {
1872 .preset = snd_hda_preset_hdmi,
1873 .owner = THIS_MODULE,
1874};
1875
1876static int __init patch_hdmi_init(void)
1877{
1878 return snd_hda_add_codec_preset(&intel_list);
1879}
1880
1881static void __exit patch_hdmi_exit(void)
1882{
1883 snd_hda_delete_codec_preset(&intel_list);
1884}
1885
1886module_init(patch_hdmi_init)
1887module_exit(patch_hdmi_exit)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 *
6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
7 * Copyright (c) 2006 ATI Technologies Inc.
8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
11 *
12 * Authors:
13 * Wu Fengguang <wfg@linux.intel.com>
14 *
15 * Maintained by:
16 * Wu Fengguang <wfg@linux.intel.com>
17 */
18
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/pci.h>
22#include <linux/slab.h>
23#include <linux/module.h>
24#include <linux/pm_runtime.h>
25#include <sound/core.h>
26#include <sound/jack.h>
27#include <sound/asoundef.h>
28#include <sound/tlv.h>
29#include <sound/hdaudio.h>
30#include <sound/hda_i915.h>
31#include <sound/hda_chmap.h>
32#include <sound/hda_codec.h>
33#include "hda_local.h"
34#include "hda_jack.h"
35#include "hda_controller.h"
36
37static bool static_hdmi_pcm;
38module_param(static_hdmi_pcm, bool, 0644);
39MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
40
41static bool enable_acomp = true;
42module_param(enable_acomp, bool, 0444);
43MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)");
44
45static bool enable_silent_stream =
46IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM);
47module_param(enable_silent_stream, bool, 0644);
48MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
49
50static bool enable_all_pins;
51module_param(enable_all_pins, bool, 0444);
52MODULE_PARM_DESC(enable_all_pins, "Forcibly enable all pins");
53
54struct hdmi_spec_per_cvt {
55 hda_nid_t cvt_nid;
56 bool assigned; /* the stream has been assigned */
57 bool silent_stream; /* silent stream activated */
58 unsigned int channels_min;
59 unsigned int channels_max;
60 u32 rates;
61 u64 formats;
62 unsigned int maxbps;
63};
64
65/* max. connections to a widget */
66#define HDA_MAX_CONNECTIONS 32
67
68struct hdmi_spec_per_pin {
69 hda_nid_t pin_nid;
70 int dev_id;
71 /* pin idx, different device entries on the same pin use the same idx */
72 int pin_nid_idx;
73 int num_mux_nids;
74 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
75 int mux_idx;
76 hda_nid_t cvt_nid;
77
78 struct hda_codec *codec;
79 struct hdmi_eld sink_eld;
80 struct mutex lock;
81 struct delayed_work work;
82 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
83 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
84 int prev_pcm_idx; /* previously assigned pcm index */
85 int repoll_count;
86 bool setup; /* the stream has been set up by prepare callback */
87 bool silent_stream;
88 int channels; /* current number of channels */
89 bool non_pcm;
90 bool chmap_set; /* channel-map override by ALSA API? */
91 unsigned char chmap[8]; /* ALSA API channel-map */
92#ifdef CONFIG_SND_PROC_FS
93 struct snd_info_entry *proc_entry;
94#endif
95};
96
97/* operations used by generic code that can be overridden by patches */
98struct hdmi_ops {
99 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
100 int dev_id, unsigned char *buf, int *eld_size);
101
102 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
103 int dev_id,
104 int ca, int active_channels, int conn_type);
105
106 /* enable/disable HBR (HD passthrough) */
107 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid,
108 int dev_id, bool hbr);
109
110 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
111 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
112 int format);
113
114 void (*pin_cvt_fixup)(struct hda_codec *codec,
115 struct hdmi_spec_per_pin *per_pin,
116 hda_nid_t cvt_nid);
117};
118
119struct hdmi_pcm {
120 struct hda_pcm *pcm;
121 struct snd_jack *jack;
122 struct snd_kcontrol *eld_ctl;
123};
124
125enum {
126 SILENT_STREAM_OFF = 0,
127 SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */
128 SILENT_STREAM_I915, /* Intel i915 extension */
129};
130
131struct hdmi_spec {
132 struct hda_codec *codec;
133 int num_cvts;
134 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
135 hda_nid_t cvt_nids[4]; /* only for haswell fix */
136
137 /*
138 * num_pins is the number of virtual pins
139 * for example, there are 3 pins, and each pin
140 * has 4 device entries, then the num_pins is 12
141 */
142 int num_pins;
143 /*
144 * num_nids is the number of real pins
145 * In the above example, num_nids is 3
146 */
147 int num_nids;
148 /*
149 * dev_num is the number of device entries
150 * on each pin.
151 * In the above example, dev_num is 4
152 */
153 int dev_num;
154 struct snd_array pins; /* struct hdmi_spec_per_pin */
155 struct hdmi_pcm pcm_rec[8];
156 struct mutex pcm_lock;
157 struct mutex bind_lock; /* for audio component binding */
158 /* pcm_bitmap means which pcms have been assigned to pins*/
159 unsigned long pcm_bitmap;
160 int pcm_used; /* counter of pcm_rec[] */
161 /* bitmap shows whether the pcm is opened in user space
162 * bit 0 means the first playback PCM (PCM3);
163 * bit 1 means the second playback PCM, and so on.
164 */
165 unsigned long pcm_in_use;
166
167 struct hdmi_eld temp_eld;
168 struct hdmi_ops ops;
169
170 bool dyn_pin_out;
171 bool static_pcm_mapping;
172 /* hdmi interrupt trigger control flag for Nvidia codec */
173 bool hdmi_intr_trig_ctrl;
174 bool nv_dp_workaround; /* workaround DP audio infoframe for Nvidia */
175
176 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */
177 /*
178 * Non-generic VIA/NVIDIA specific
179 */
180 struct hda_multi_out multiout;
181 struct hda_pcm_stream pcm_playback;
182
183 bool use_acomp_notifier; /* use eld_notify callback for hotplug */
184 bool acomp_registered; /* audio component registered in this driver */
185 bool force_connect; /* force connectivity */
186 struct drm_audio_component_audio_ops drm_audio_ops;
187 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
188
189 struct hdac_chmap chmap;
190 hda_nid_t vendor_nid;
191 const int *port_map;
192 int port_num;
193 int silent_stream_type;
194};
195
196#ifdef CONFIG_SND_HDA_COMPONENT
197static inline bool codec_has_acomp(struct hda_codec *codec)
198{
199 struct hdmi_spec *spec = codec->spec;
200 return spec->use_acomp_notifier;
201}
202#else
203#define codec_has_acomp(codec) false
204#endif
205
206struct hdmi_audio_infoframe {
207 u8 type; /* 0x84 */
208 u8 ver; /* 0x01 */
209 u8 len; /* 0x0a */
210
211 u8 checksum;
212
213 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
214 u8 SS01_SF24;
215 u8 CXT04;
216 u8 CA;
217 u8 LFEPBL01_LSV36_DM_INH7;
218};
219
220struct dp_audio_infoframe {
221 u8 type; /* 0x84 */
222 u8 len; /* 0x1b */
223 u8 ver; /* 0x11 << 2 */
224
225 u8 CC02_CT47; /* match with HDMI infoframe from this on */
226 u8 SS01_SF24;
227 u8 CXT04;
228 u8 CA;
229 u8 LFEPBL01_LSV36_DM_INH7;
230};
231
232union audio_infoframe {
233 struct hdmi_audio_infoframe hdmi;
234 struct dp_audio_infoframe dp;
235 DECLARE_FLEX_ARRAY(u8, bytes);
236};
237
238/*
239 * HDMI routines
240 */
241
242#define get_pin(spec, idx) \
243 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
244#define get_cvt(spec, idx) \
245 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
246/* obtain hdmi_pcm object assigned to idx */
247#define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
248/* obtain hda_pcm object assigned to idx */
249#define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
250
251static int pin_id_to_pin_index(struct hda_codec *codec,
252 hda_nid_t pin_nid, int dev_id)
253{
254 struct hdmi_spec *spec = codec->spec;
255 int pin_idx;
256 struct hdmi_spec_per_pin *per_pin;
257
258 /*
259 * (dev_id == -1) means it is NON-MST pin
260 * return the first virtual pin on this port
261 */
262 if (dev_id == -1)
263 dev_id = 0;
264
265 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
266 per_pin = get_pin(spec, pin_idx);
267 if ((per_pin->pin_nid == pin_nid) &&
268 (per_pin->dev_id == dev_id))
269 return pin_idx;
270 }
271
272 codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid);
273 return -EINVAL;
274}
275
276static int hinfo_to_pcm_index(struct hda_codec *codec,
277 struct hda_pcm_stream *hinfo)
278{
279 struct hdmi_spec *spec = codec->spec;
280 int pcm_idx;
281
282 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
283 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
284 return pcm_idx;
285
286 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo);
287 return -EINVAL;
288}
289
290static int hinfo_to_pin_index(struct hda_codec *codec,
291 struct hda_pcm_stream *hinfo)
292{
293 struct hdmi_spec *spec = codec->spec;
294 struct hdmi_spec_per_pin *per_pin;
295 int pin_idx;
296
297 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
298 per_pin = get_pin(spec, pin_idx);
299 if (per_pin->pcm &&
300 per_pin->pcm->pcm->stream == hinfo)
301 return pin_idx;
302 }
303
304 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo,
305 hinfo_to_pcm_index(codec, hinfo));
306 return -EINVAL;
307}
308
309static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
310 int pcm_idx)
311{
312 int i;
313 struct hdmi_spec_per_pin *per_pin;
314
315 for (i = 0; i < spec->num_pins; i++) {
316 per_pin = get_pin(spec, i);
317 if (per_pin->pcm_idx == pcm_idx)
318 return per_pin;
319 }
320 return NULL;
321}
322
323static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
324{
325 struct hdmi_spec *spec = codec->spec;
326 int cvt_idx;
327
328 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
329 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
330 return cvt_idx;
331
332 codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid);
333 return -EINVAL;
334}
335
336static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
337 struct snd_ctl_elem_info *uinfo)
338{
339 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
340 struct hdmi_spec *spec = codec->spec;
341 struct hdmi_spec_per_pin *per_pin;
342 struct hdmi_eld *eld;
343 int pcm_idx;
344
345 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
346
347 pcm_idx = kcontrol->private_value;
348 mutex_lock(&spec->pcm_lock);
349 per_pin = pcm_idx_to_pin(spec, pcm_idx);
350 if (!per_pin) {
351 /* no pin is bound to the pcm */
352 uinfo->count = 0;
353 goto unlock;
354 }
355 eld = &per_pin->sink_eld;
356 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
357
358 unlock:
359 mutex_unlock(&spec->pcm_lock);
360 return 0;
361}
362
363static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
364 struct snd_ctl_elem_value *ucontrol)
365{
366 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
367 struct hdmi_spec *spec = codec->spec;
368 struct hdmi_spec_per_pin *per_pin;
369 struct hdmi_eld *eld;
370 int pcm_idx;
371 int err = 0;
372
373 pcm_idx = kcontrol->private_value;
374 mutex_lock(&spec->pcm_lock);
375 per_pin = pcm_idx_to_pin(spec, pcm_idx);
376 if (!per_pin) {
377 /* no pin is bound to the pcm */
378 memset(ucontrol->value.bytes.data, 0,
379 ARRAY_SIZE(ucontrol->value.bytes.data));
380 goto unlock;
381 }
382
383 eld = &per_pin->sink_eld;
384 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
385 eld->eld_size > ELD_MAX_SIZE) {
386 snd_BUG();
387 err = -EINVAL;
388 goto unlock;
389 }
390
391 memset(ucontrol->value.bytes.data, 0,
392 ARRAY_SIZE(ucontrol->value.bytes.data));
393 if (eld->eld_valid)
394 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
395 eld->eld_size);
396
397 unlock:
398 mutex_unlock(&spec->pcm_lock);
399 return err;
400}
401
402static const struct snd_kcontrol_new eld_bytes_ctl = {
403 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE |
404 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK,
405 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
406 .name = "ELD",
407 .info = hdmi_eld_ctl_info,
408 .get = hdmi_eld_ctl_get,
409};
410
411static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
412 int device)
413{
414 struct snd_kcontrol *kctl;
415 struct hdmi_spec *spec = codec->spec;
416 int err;
417
418 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
419 if (!kctl)
420 return -ENOMEM;
421 kctl->private_value = pcm_idx;
422 kctl->id.device = device;
423
424 /* no pin nid is associated with the kctl now
425 * tbd: associate pin nid to eld ctl later
426 */
427 err = snd_hda_ctl_add(codec, 0, kctl);
428 if (err < 0)
429 return err;
430
431 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
432 return 0;
433}
434
435#ifdef BE_PARANOID
436static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
437 int *packet_index, int *byte_index)
438{
439 int val;
440
441 val = snd_hda_codec_read(codec, pin_nid, 0,
442 AC_VERB_GET_HDMI_DIP_INDEX, 0);
443
444 *packet_index = val >> 5;
445 *byte_index = val & 0x1f;
446}
447#endif
448
449static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
450 int packet_index, int byte_index)
451{
452 int val;
453
454 val = (packet_index << 5) | (byte_index & 0x1f);
455
456 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
457}
458
459static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
460 unsigned char val)
461{
462 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
463}
464
465static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
466{
467 struct hdmi_spec *spec = codec->spec;
468 int pin_out;
469
470 /* Unmute */
471 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
472 snd_hda_codec_write(codec, pin_nid, 0,
473 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
474
475 if (spec->dyn_pin_out)
476 /* Disable pin out until stream is active */
477 pin_out = 0;
478 else
479 /* Enable pin out: some machines with GM965 gets broken output
480 * when the pin is disabled or changed while using with HDMI
481 */
482 pin_out = PIN_OUT;
483
484 snd_hda_codec_write(codec, pin_nid, 0,
485 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
486}
487
488/*
489 * ELD proc files
490 */
491
492#ifdef CONFIG_SND_PROC_FS
493static void print_eld_info(struct snd_info_entry *entry,
494 struct snd_info_buffer *buffer)
495{
496 struct hdmi_spec_per_pin *per_pin = entry->private_data;
497
498 mutex_lock(&per_pin->lock);
499 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer, per_pin->pin_nid,
500 per_pin->dev_id, per_pin->cvt_nid);
501 mutex_unlock(&per_pin->lock);
502}
503
504static void write_eld_info(struct snd_info_entry *entry,
505 struct snd_info_buffer *buffer)
506{
507 struct hdmi_spec_per_pin *per_pin = entry->private_data;
508
509 mutex_lock(&per_pin->lock);
510 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
511 mutex_unlock(&per_pin->lock);
512}
513
514static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
515{
516 char name[32];
517 struct hda_codec *codec = per_pin->codec;
518 struct snd_info_entry *entry;
519 int err;
520
521 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
522 err = snd_card_proc_new(codec->card, name, &entry);
523 if (err < 0)
524 return err;
525
526 snd_info_set_text_ops(entry, per_pin, print_eld_info);
527 entry->c.text.write = write_eld_info;
528 entry->mode |= 0200;
529 per_pin->proc_entry = entry;
530
531 return 0;
532}
533
534static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
535{
536 if (!per_pin->codec->bus->shutdown) {
537 snd_info_free_entry(per_pin->proc_entry);
538 per_pin->proc_entry = NULL;
539 }
540}
541#else
542static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
543 int index)
544{
545 return 0;
546}
547static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
548{
549}
550#endif
551
552/*
553 * Audio InfoFrame routines
554 */
555
556/*
557 * Enable Audio InfoFrame Transmission
558 */
559static void hdmi_start_infoframe_trans(struct hda_codec *codec,
560 hda_nid_t pin_nid)
561{
562 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
563 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
564 AC_DIPXMIT_BEST);
565}
566
567/*
568 * Disable Audio InfoFrame Transmission
569 */
570static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
571 hda_nid_t pin_nid)
572{
573 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
574 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
575 AC_DIPXMIT_DISABLE);
576}
577
578static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
579{
580#ifdef CONFIG_SND_DEBUG_VERBOSE
581 int i;
582 int size;
583
584 size = snd_hdmi_get_eld_size(codec, pin_nid);
585 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
586
587 for (i = 0; i < 8; i++) {
588 size = snd_hda_codec_read(codec, pin_nid, 0,
589 AC_VERB_GET_HDMI_DIP_SIZE, i);
590 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
591 }
592#endif
593}
594
595static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
596{
597#ifdef BE_PARANOID
598 int i, j;
599 int size;
600 int pi, bi;
601 for (i = 0; i < 8; i++) {
602 size = snd_hda_codec_read(codec, pin_nid, 0,
603 AC_VERB_GET_HDMI_DIP_SIZE, i);
604 if (size == 0)
605 continue;
606
607 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
608 for (j = 1; j < 1000; j++) {
609 hdmi_write_dip_byte(codec, pin_nid, 0x0);
610 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
611 if (pi != i)
612 codec_dbg(codec, "dip index %d: %d != %d\n",
613 bi, pi, i);
614 if (bi == 0) /* byte index wrapped around */
615 break;
616 }
617 codec_dbg(codec,
618 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
619 i, size, j);
620 }
621#endif
622}
623
624static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
625{
626 u8 *bytes = (u8 *)hdmi_ai;
627 u8 sum = 0;
628 int i;
629
630 hdmi_ai->checksum = 0;
631
632 for (i = 0; i < sizeof(*hdmi_ai); i++)
633 sum += bytes[i];
634
635 hdmi_ai->checksum = -sum;
636}
637
638static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
639 hda_nid_t pin_nid,
640 u8 *dip, int size)
641{
642 int i;
643
644 hdmi_debug_dip_size(codec, pin_nid);
645 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
646
647 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
648 for (i = 0; i < size; i++)
649 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
650}
651
652static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
653 u8 *dip, int size)
654{
655 u8 val;
656 int i;
657
658 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
659 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
660 != AC_DIPXMIT_BEST)
661 return false;
662
663 for (i = 0; i < size; i++) {
664 val = snd_hda_codec_read(codec, pin_nid, 0,
665 AC_VERB_GET_HDMI_DIP_DATA, 0);
666 if (val != dip[i])
667 return false;
668 }
669
670 return true;
671}
672
673static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
674 int dev_id, unsigned char *buf, int *eld_size)
675{
676 snd_hda_set_dev_select(codec, nid, dev_id);
677
678 return snd_hdmi_get_eld(codec, nid, buf, eld_size);
679}
680
681static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
682 hda_nid_t pin_nid, int dev_id,
683 int ca, int active_channels,
684 int conn_type)
685{
686 struct hdmi_spec *spec = codec->spec;
687 union audio_infoframe ai;
688
689 memset(&ai, 0, sizeof(ai));
690 if ((conn_type == 0) || /* HDMI */
691 /* Nvidia DisplayPort: Nvidia HW expects same layout as HDMI */
692 (conn_type == 1 && spec->nv_dp_workaround)) {
693 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
694
695 if (conn_type == 0) { /* HDMI */
696 hdmi_ai->type = 0x84;
697 hdmi_ai->ver = 0x01;
698 hdmi_ai->len = 0x0a;
699 } else {/* Nvidia DP */
700 hdmi_ai->type = 0x84;
701 hdmi_ai->ver = 0x1b;
702 hdmi_ai->len = 0x11 << 2;
703 }
704 hdmi_ai->CC02_CT47 = active_channels - 1;
705 hdmi_ai->CA = ca;
706 hdmi_checksum_audio_infoframe(hdmi_ai);
707 } else if (conn_type == 1) { /* DisplayPort */
708 struct dp_audio_infoframe *dp_ai = &ai.dp;
709
710 dp_ai->type = 0x84;
711 dp_ai->len = 0x1b;
712 dp_ai->ver = 0x11 << 2;
713 dp_ai->CC02_CT47 = active_channels - 1;
714 dp_ai->CA = ca;
715 } else {
716 codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid);
717 return;
718 }
719
720 snd_hda_set_dev_select(codec, pin_nid, dev_id);
721
722 /*
723 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
724 * sizeof(*dp_ai) to avoid partial match/update problems when
725 * the user switches between HDMI/DP monitors.
726 */
727 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
728 sizeof(ai))) {
729 codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n",
730 __func__, pin_nid, active_channels, ca);
731 hdmi_stop_infoframe_trans(codec, pin_nid);
732 hdmi_fill_audio_infoframe(codec, pin_nid,
733 ai.bytes, sizeof(ai));
734 hdmi_start_infoframe_trans(codec, pin_nid);
735 }
736}
737
738static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
739 struct hdmi_spec_per_pin *per_pin,
740 bool non_pcm)
741{
742 struct hdmi_spec *spec = codec->spec;
743 struct hdac_chmap *chmap = &spec->chmap;
744 hda_nid_t pin_nid = per_pin->pin_nid;
745 int dev_id = per_pin->dev_id;
746 int channels = per_pin->channels;
747 int active_channels;
748 struct hdmi_eld *eld;
749 int ca;
750
751 if (!channels)
752 return;
753
754 snd_hda_set_dev_select(codec, pin_nid, dev_id);
755
756 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
757 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
758 snd_hda_codec_write(codec, pin_nid, 0,
759 AC_VERB_SET_AMP_GAIN_MUTE,
760 AMP_OUT_UNMUTE);
761
762 eld = &per_pin->sink_eld;
763
764 ca = snd_hdac_channel_allocation(&codec->core,
765 eld->info.spk_alloc, channels,
766 per_pin->chmap_set, non_pcm, per_pin->chmap);
767
768 active_channels = snd_hdac_get_active_channels(ca);
769
770 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
771 active_channels);
772
773 /*
774 * always configure channel mapping, it may have been changed by the
775 * user in the meantime
776 */
777 snd_hdac_setup_channel_mapping(&spec->chmap,
778 pin_nid, non_pcm, ca, channels,
779 per_pin->chmap, per_pin->chmap_set);
780
781 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id,
782 ca, active_channels, eld->info.conn_type);
783
784 per_pin->non_pcm = non_pcm;
785}
786
787/*
788 * Unsolicited events
789 */
790
791static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
792
793static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
794 int dev_id)
795{
796 struct hdmi_spec *spec = codec->spec;
797 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
798
799 if (pin_idx < 0)
800 return;
801 mutex_lock(&spec->pcm_lock);
802 hdmi_present_sense(get_pin(spec, pin_idx), 1);
803 mutex_unlock(&spec->pcm_lock);
804}
805
806static void jack_callback(struct hda_codec *codec,
807 struct hda_jack_callback *jack)
808{
809 /* stop polling when notification is enabled */
810 if (codec_has_acomp(codec))
811 return;
812
813 check_presence_and_report(codec, jack->nid, jack->dev_id);
814}
815
816static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res,
817 struct hda_jack_tbl *jack)
818{
819 jack->jack_dirty = 1;
820
821 codec_dbg(codec,
822 "HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
823 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA),
824 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
825
826 check_presence_and_report(codec, jack->nid, jack->dev_id);
827}
828
829static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
830{
831 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
832 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
833 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
834 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
835
836 codec_info(codec,
837 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
838 codec->addr,
839 tag,
840 subtag,
841 cp_state,
842 cp_ready);
843
844 /* TODO */
845 if (cp_state) {
846 ;
847 }
848 if (cp_ready) {
849 ;
850 }
851}
852
853
854static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
855{
856 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
857 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
858 struct hda_jack_tbl *jack;
859
860 if (codec_has_acomp(codec))
861 return;
862
863 if (codec->dp_mst) {
864 int dev_entry =
865 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
866
867 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry);
868 } else {
869 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0);
870 }
871
872 if (!jack) {
873 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
874 return;
875 }
876
877 if (subtag == 0)
878 hdmi_intrinsic_event(codec, res, jack);
879 else
880 hdmi_non_intrinsic_event(codec, res);
881}
882
883static void haswell_verify_D0(struct hda_codec *codec,
884 hda_nid_t cvt_nid, hda_nid_t nid)
885{
886 int pwr;
887
888 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
889 * thus pins could only choose converter 0 for use. Make sure the
890 * converters are in correct power state */
891 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
892 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
893
894 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
895 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
896 AC_PWRST_D0);
897 msleep(40);
898 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
899 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
900 codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr);
901 }
902}
903
904/*
905 * Callbacks
906 */
907
908/* HBR should be Non-PCM, 8 channels */
909#define is_hbr_format(format) \
910 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
911
912static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
913 int dev_id, bool hbr)
914{
915 int pinctl, new_pinctl;
916
917 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
918 snd_hda_set_dev_select(codec, pin_nid, dev_id);
919 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
920 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
921
922 if (pinctl < 0)
923 return hbr ? -EINVAL : 0;
924
925 new_pinctl = pinctl & ~AC_PINCTL_EPT;
926 if (hbr)
927 new_pinctl |= AC_PINCTL_EPT_HBR;
928 else
929 new_pinctl |= AC_PINCTL_EPT_NATIVE;
930
931 codec_dbg(codec,
932 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
933 pin_nid,
934 pinctl == new_pinctl ? "" : "new-",
935 new_pinctl);
936
937 if (pinctl != new_pinctl)
938 snd_hda_codec_write(codec, pin_nid, 0,
939 AC_VERB_SET_PIN_WIDGET_CONTROL,
940 new_pinctl);
941 } else if (hbr)
942 return -EINVAL;
943
944 return 0;
945}
946
947static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
948 hda_nid_t pin_nid, int dev_id,
949 u32 stream_tag, int format)
950{
951 struct hdmi_spec *spec = codec->spec;
952 unsigned int param;
953 int err;
954
955 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id,
956 is_hbr_format(format));
957
958 if (err) {
959 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
960 return err;
961 }
962
963 if (spec->intel_hsw_fixup) {
964
965 /*
966 * on recent platforms IEC Coding Type is required for HBR
967 * support, read current Digital Converter settings and set
968 * ICT bitfield if needed.
969 */
970 param = snd_hda_codec_read(codec, cvt_nid, 0,
971 AC_VERB_GET_DIGI_CONVERT_1, 0);
972
973 param = (param >> 16) & ~(AC_DIG3_ICT);
974
975 /* on recent platforms ICT mode is required for HBR support */
976 if (is_hbr_format(format))
977 param |= 0x1;
978
979 snd_hda_codec_write(codec, cvt_nid, 0,
980 AC_VERB_SET_DIGI_CONVERT_3, param);
981 }
982
983 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
984 return 0;
985}
986
987/* Try to find an available converter
988 * If pin_idx is less then zero, just try to find an available converter.
989 * Otherwise, try to find an available converter and get the cvt mux index
990 * of the pin.
991 */
992static int hdmi_choose_cvt(struct hda_codec *codec,
993 int pin_idx, int *cvt_id,
994 bool silent)
995{
996 struct hdmi_spec *spec = codec->spec;
997 struct hdmi_spec_per_pin *per_pin;
998 struct hdmi_spec_per_cvt *per_cvt = NULL;
999 int cvt_idx, mux_idx = 0;
1000
1001 /* pin_idx < 0 means no pin will be bound to the converter */
1002 if (pin_idx < 0)
1003 per_pin = NULL;
1004 else
1005 per_pin = get_pin(spec, pin_idx);
1006
1007 if (per_pin && per_pin->silent_stream) {
1008 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
1009 per_cvt = get_cvt(spec, cvt_idx);
1010 if (per_cvt->assigned && !silent)
1011 return -EBUSY;
1012 if (cvt_id)
1013 *cvt_id = cvt_idx;
1014 return 0;
1015 }
1016
1017 /* Dynamically assign converter to stream */
1018 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1019 per_cvt = get_cvt(spec, cvt_idx);
1020
1021 /* Must not already be assigned */
1022 if (per_cvt->assigned || per_cvt->silent_stream)
1023 continue;
1024 if (per_pin == NULL)
1025 break;
1026 /* Must be in pin's mux's list of converters */
1027 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1028 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1029 break;
1030 /* Not in mux list */
1031 if (mux_idx == per_pin->num_mux_nids)
1032 continue;
1033 break;
1034 }
1035
1036 /* No free converters */
1037 if (cvt_idx == spec->num_cvts)
1038 return -EBUSY;
1039
1040 if (per_pin != NULL)
1041 per_pin->mux_idx = mux_idx;
1042
1043 if (cvt_id)
1044 *cvt_id = cvt_idx;
1045
1046 return 0;
1047}
1048
1049/* Assure the pin select the right convetor */
1050static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1051 struct hdmi_spec_per_pin *per_pin)
1052{
1053 hda_nid_t pin_nid = per_pin->pin_nid;
1054 int mux_idx, curr;
1055
1056 mux_idx = per_pin->mux_idx;
1057 curr = snd_hda_codec_read(codec, pin_nid, 0,
1058 AC_VERB_GET_CONNECT_SEL, 0);
1059 if (curr != mux_idx)
1060 snd_hda_codec_write_cache(codec, pin_nid, 0,
1061 AC_VERB_SET_CONNECT_SEL,
1062 mux_idx);
1063}
1064
1065/* get the mux index for the converter of the pins
1066 * converter's mux index is the same for all pins on Intel platform
1067 */
1068static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1069 hda_nid_t cvt_nid)
1070{
1071 int i;
1072
1073 for (i = 0; i < spec->num_cvts; i++)
1074 if (spec->cvt_nids[i] == cvt_nid)
1075 return i;
1076 return -EINVAL;
1077}
1078
1079/* Intel HDMI workaround to fix audio routing issue:
1080 * For some Intel display codecs, pins share the same connection list.
1081 * So a conveter can be selected by multiple pins and playback on any of these
1082 * pins will generate sound on the external display, because audio flows from
1083 * the same converter to the display pipeline. Also muting one pin may make
1084 * other pins have no sound output.
1085 * So this function assures that an assigned converter for a pin is not selected
1086 * by any other pins.
1087 */
1088static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1089 hda_nid_t pin_nid,
1090 int dev_id, int mux_idx)
1091{
1092 struct hdmi_spec *spec = codec->spec;
1093 hda_nid_t nid;
1094 int cvt_idx, curr;
1095 struct hdmi_spec_per_cvt *per_cvt;
1096 struct hdmi_spec_per_pin *per_pin;
1097 int pin_idx;
1098
1099 /* configure the pins connections */
1100 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1101 int dev_id_saved;
1102 int dev_num;
1103
1104 per_pin = get_pin(spec, pin_idx);
1105 /*
1106 * pin not connected to monitor
1107 * no need to operate on it
1108 */
1109 if (!per_pin->pcm)
1110 continue;
1111
1112 if ((per_pin->pin_nid == pin_nid) &&
1113 (per_pin->dev_id == dev_id))
1114 continue;
1115
1116 /*
1117 * if per_pin->dev_id >= dev_num,
1118 * snd_hda_get_dev_select() will fail,
1119 * and the following operation is unpredictable.
1120 * So skip this situation.
1121 */
1122 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1123 if (per_pin->dev_id >= dev_num)
1124 continue;
1125
1126 nid = per_pin->pin_nid;
1127
1128 /*
1129 * Calling this function should not impact
1130 * on the device entry selection
1131 * So let's save the dev id for each pin,
1132 * and restore it when return
1133 */
1134 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1135 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1136 curr = snd_hda_codec_read(codec, nid, 0,
1137 AC_VERB_GET_CONNECT_SEL, 0);
1138 if (curr != mux_idx) {
1139 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1140 continue;
1141 }
1142
1143
1144 /* choose an unassigned converter. The conveters in the
1145 * connection list are in the same order as in the codec.
1146 */
1147 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1148 per_cvt = get_cvt(spec, cvt_idx);
1149 if (!per_cvt->assigned) {
1150 codec_dbg(codec,
1151 "choose cvt %d for pin NID 0x%x\n",
1152 cvt_idx, nid);
1153 snd_hda_codec_write_cache(codec, nid, 0,
1154 AC_VERB_SET_CONNECT_SEL,
1155 cvt_idx);
1156 break;
1157 }
1158 }
1159 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1160 }
1161}
1162
1163/* A wrapper of intel_not_share_asigned_cvt() */
1164static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1165 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1166{
1167 int mux_idx;
1168 struct hdmi_spec *spec = codec->spec;
1169
1170 /* On Intel platform, the mapping of converter nid to
1171 * mux index of the pins are always the same.
1172 * The pin nid may be 0, this means all pins will not
1173 * share the converter.
1174 */
1175 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1176 if (mux_idx >= 0)
1177 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1178}
1179
1180/* skeleton caller of pin_cvt_fixup ops */
1181static void pin_cvt_fixup(struct hda_codec *codec,
1182 struct hdmi_spec_per_pin *per_pin,
1183 hda_nid_t cvt_nid)
1184{
1185 struct hdmi_spec *spec = codec->spec;
1186
1187 if (spec->ops.pin_cvt_fixup)
1188 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1189}
1190
1191/* called in hdmi_pcm_open when no pin is assigned to the PCM */
1192static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1193 struct hda_codec *codec,
1194 struct snd_pcm_substream *substream)
1195{
1196 struct hdmi_spec *spec = codec->spec;
1197 struct snd_pcm_runtime *runtime = substream->runtime;
1198 int cvt_idx, pcm_idx;
1199 struct hdmi_spec_per_cvt *per_cvt = NULL;
1200 int err;
1201
1202 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1203 if (pcm_idx < 0)
1204 return -EINVAL;
1205
1206 err = hdmi_choose_cvt(codec, -1, &cvt_idx, false);
1207 if (err)
1208 return err;
1209
1210 per_cvt = get_cvt(spec, cvt_idx);
1211 per_cvt->assigned = true;
1212 hinfo->nid = per_cvt->cvt_nid;
1213
1214 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1215
1216 set_bit(pcm_idx, &spec->pcm_in_use);
1217 /* todo: setup spdif ctls assign */
1218
1219 /* Initially set the converter's capabilities */
1220 hinfo->channels_min = per_cvt->channels_min;
1221 hinfo->channels_max = per_cvt->channels_max;
1222 hinfo->rates = per_cvt->rates;
1223 hinfo->formats = per_cvt->formats;
1224 hinfo->maxbps = per_cvt->maxbps;
1225
1226 /* Store the updated parameters */
1227 runtime->hw.channels_min = hinfo->channels_min;
1228 runtime->hw.channels_max = hinfo->channels_max;
1229 runtime->hw.formats = hinfo->formats;
1230 runtime->hw.rates = hinfo->rates;
1231
1232 snd_pcm_hw_constraint_step(substream->runtime, 0,
1233 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1234 return 0;
1235}
1236
1237/*
1238 * HDA PCM callbacks
1239 */
1240static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1241 struct hda_codec *codec,
1242 struct snd_pcm_substream *substream)
1243{
1244 struct hdmi_spec *spec = codec->spec;
1245 struct snd_pcm_runtime *runtime = substream->runtime;
1246 int pin_idx, cvt_idx, pcm_idx;
1247 struct hdmi_spec_per_pin *per_pin;
1248 struct hdmi_eld *eld;
1249 struct hdmi_spec_per_cvt *per_cvt = NULL;
1250 int err;
1251
1252 /* Validate hinfo */
1253 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1254 if (pcm_idx < 0)
1255 return -EINVAL;
1256
1257 mutex_lock(&spec->pcm_lock);
1258 pin_idx = hinfo_to_pin_index(codec, hinfo);
1259 /* no pin is assigned to the PCM
1260 * PA need pcm open successfully when probe
1261 */
1262 if (pin_idx < 0) {
1263 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1264 goto unlock;
1265 }
1266
1267 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, false);
1268 if (err < 0)
1269 goto unlock;
1270
1271 per_cvt = get_cvt(spec, cvt_idx);
1272 /* Claim converter */
1273 per_cvt->assigned = true;
1274
1275 set_bit(pcm_idx, &spec->pcm_in_use);
1276 per_pin = get_pin(spec, pin_idx);
1277 per_pin->cvt_nid = per_cvt->cvt_nid;
1278 hinfo->nid = per_cvt->cvt_nid;
1279
1280 /* flip stripe flag for the assigned stream if supported */
1281 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE)
1282 azx_stream(get_azx_dev(substream))->stripe = 1;
1283
1284 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1285 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1286 AC_VERB_SET_CONNECT_SEL,
1287 per_pin->mux_idx);
1288
1289 /* configure unused pins to choose other converters */
1290 pin_cvt_fixup(codec, per_pin, 0);
1291
1292 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1293
1294 /* Initially set the converter's capabilities */
1295 hinfo->channels_min = per_cvt->channels_min;
1296 hinfo->channels_max = per_cvt->channels_max;
1297 hinfo->rates = per_cvt->rates;
1298 hinfo->formats = per_cvt->formats;
1299 hinfo->maxbps = per_cvt->maxbps;
1300
1301 eld = &per_pin->sink_eld;
1302 /* Restrict capabilities by ELD if this isn't disabled */
1303 if (!static_hdmi_pcm && eld->eld_valid) {
1304 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1305 if (hinfo->channels_min > hinfo->channels_max ||
1306 !hinfo->rates || !hinfo->formats) {
1307 per_cvt->assigned = false;
1308 hinfo->nid = 0;
1309 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1310 err = -ENODEV;
1311 goto unlock;
1312 }
1313 }
1314
1315 /* Store the updated parameters */
1316 runtime->hw.channels_min = hinfo->channels_min;
1317 runtime->hw.channels_max = hinfo->channels_max;
1318 runtime->hw.formats = hinfo->formats;
1319 runtime->hw.rates = hinfo->rates;
1320
1321 snd_pcm_hw_constraint_step(substream->runtime, 0,
1322 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1323 unlock:
1324 mutex_unlock(&spec->pcm_lock);
1325 return err;
1326}
1327
1328/*
1329 * HDA/HDMI auto parsing
1330 */
1331static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1332{
1333 struct hdmi_spec *spec = codec->spec;
1334 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1335 hda_nid_t pin_nid = per_pin->pin_nid;
1336 int dev_id = per_pin->dev_id;
1337 int conns;
1338
1339 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1340 codec_warn(codec,
1341 "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n",
1342 pin_nid, get_wcaps(codec, pin_nid));
1343 return -EINVAL;
1344 }
1345
1346 snd_hda_set_dev_select(codec, pin_nid, dev_id);
1347
1348 if (spec->intel_hsw_fixup) {
1349 conns = spec->num_cvts;
1350 memcpy(per_pin->mux_nids, spec->cvt_nids,
1351 sizeof(hda_nid_t) * conns);
1352 } else {
1353 conns = snd_hda_get_raw_connections(codec, pin_nid,
1354 per_pin->mux_nids,
1355 HDA_MAX_CONNECTIONS);
1356 }
1357
1358 /* all the device entries on the same pin have the same conn list */
1359 per_pin->num_mux_nids = conns;
1360
1361 return 0;
1362}
1363
1364static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1365 struct hdmi_spec_per_pin *per_pin)
1366{
1367 int i;
1368
1369 for (i = 0; i < spec->pcm_used; i++) {
1370 if (!test_bit(i, &spec->pcm_bitmap))
1371 return i;
1372 }
1373 return -EBUSY;
1374}
1375
1376static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1377 struct hdmi_spec_per_pin *per_pin)
1378{
1379 int idx;
1380
1381 /* pcm already be attached to the pin */
1382 if (per_pin->pcm)
1383 return;
1384 /* try the previously used slot at first */
1385 idx = per_pin->prev_pcm_idx;
1386 if (idx >= 0) {
1387 if (!test_bit(idx, &spec->pcm_bitmap))
1388 goto found;
1389 per_pin->prev_pcm_idx = -1; /* no longer valid, clear it */
1390 }
1391 idx = hdmi_find_pcm_slot(spec, per_pin);
1392 if (idx == -EBUSY)
1393 return;
1394 found:
1395 per_pin->pcm_idx = idx;
1396 per_pin->pcm = get_hdmi_pcm(spec, idx);
1397 set_bit(idx, &spec->pcm_bitmap);
1398}
1399
1400static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1401 struct hdmi_spec_per_pin *per_pin)
1402{
1403 int idx;
1404
1405 /* pcm already be detached from the pin */
1406 if (!per_pin->pcm)
1407 return;
1408 idx = per_pin->pcm_idx;
1409 per_pin->pcm_idx = -1;
1410 per_pin->prev_pcm_idx = idx; /* remember the previous index */
1411 per_pin->pcm = NULL;
1412 if (idx >= 0 && idx < spec->pcm_used)
1413 clear_bit(idx, &spec->pcm_bitmap);
1414}
1415
1416static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1417 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1418{
1419 int mux_idx;
1420
1421 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1422 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1423 break;
1424 return mux_idx;
1425}
1426
1427static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1428
1429static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1430 struct hdmi_spec_per_pin *per_pin)
1431{
1432 struct hda_codec *codec = per_pin->codec;
1433 struct hda_pcm *pcm;
1434 struct hda_pcm_stream *hinfo;
1435 struct snd_pcm_substream *substream;
1436 int mux_idx;
1437 bool non_pcm;
1438
1439 if (per_pin->pcm_idx < 0 || per_pin->pcm_idx >= spec->pcm_used)
1440 return;
1441 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1442 if (!pcm->pcm)
1443 return;
1444 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1445 return;
1446
1447 /* hdmi audio only uses playback and one substream */
1448 hinfo = pcm->stream;
1449 substream = pcm->pcm->streams[0].substream;
1450
1451 per_pin->cvt_nid = hinfo->nid;
1452
1453 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1454 if (mux_idx < per_pin->num_mux_nids) {
1455 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1456 per_pin->dev_id);
1457 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1458 AC_VERB_SET_CONNECT_SEL,
1459 mux_idx);
1460 }
1461 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1462
1463 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1464 if (substream->runtime)
1465 per_pin->channels = substream->runtime->channels;
1466 per_pin->setup = true;
1467 per_pin->mux_idx = mux_idx;
1468
1469 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1470}
1471
1472static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1473 struct hdmi_spec_per_pin *per_pin)
1474{
1475 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1476 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1477
1478 per_pin->chmap_set = false;
1479 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1480
1481 per_pin->setup = false;
1482 per_pin->channels = 0;
1483}
1484
1485static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec,
1486 struct hdmi_spec_per_pin *per_pin)
1487{
1488 struct hdmi_spec *spec = codec->spec;
1489
1490 if (per_pin->pcm_idx >= 0)
1491 return spec->pcm_rec[per_pin->pcm_idx].jack;
1492 else
1493 return NULL;
1494}
1495
1496/* update per_pin ELD from the given new ELD;
1497 * setup info frame and notification accordingly
1498 * also notify ELD kctl and report jack status changes
1499 */
1500static void update_eld(struct hda_codec *codec,
1501 struct hdmi_spec_per_pin *per_pin,
1502 struct hdmi_eld *eld,
1503 int repoll)
1504{
1505 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1506 struct hdmi_spec *spec = codec->spec;
1507 struct snd_jack *pcm_jack;
1508 bool old_eld_valid = pin_eld->eld_valid;
1509 bool eld_changed;
1510 int pcm_idx;
1511
1512 if (eld->eld_valid) {
1513 if (eld->eld_size <= 0 ||
1514 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1515 eld->eld_size) < 0) {
1516 eld->eld_valid = false;
1517 if (repoll) {
1518 schedule_delayed_work(&per_pin->work,
1519 msecs_to_jiffies(300));
1520 return;
1521 }
1522 }
1523 }
1524
1525 if (!eld->eld_valid || eld->eld_size <= 0 || eld->info.sad_count <= 0) {
1526 eld->eld_valid = false;
1527 eld->eld_size = 0;
1528 }
1529
1530 /* for monitor disconnection, save pcm_idx firstly */
1531 pcm_idx = per_pin->pcm_idx;
1532
1533 /*
1534 * pcm_idx >=0 before update_eld() means it is in monitor
1535 * disconnected event. Jack must be fetched before update_eld().
1536 */
1537 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1538
1539 if (!spec->static_pcm_mapping) {
1540 if (eld->eld_valid) {
1541 hdmi_attach_hda_pcm(spec, per_pin);
1542 hdmi_pcm_setup_pin(spec, per_pin);
1543 } else {
1544 hdmi_pcm_reset_pin(spec, per_pin);
1545 hdmi_detach_hda_pcm(spec, per_pin);
1546 }
1547 }
1548
1549 /* if pcm_idx == -1, it means this is in monitor connection event
1550 * we can get the correct pcm_idx now.
1551 */
1552 if (pcm_idx == -1)
1553 pcm_idx = per_pin->pcm_idx;
1554 if (!pcm_jack)
1555 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1556
1557 if (eld->eld_valid)
1558 snd_hdmi_show_eld(codec, &eld->info);
1559
1560 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1561 eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
1562 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
1563 if (pin_eld->eld_size != eld->eld_size ||
1564 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1565 eld->eld_size) != 0)
1566 eld_changed = true;
1567
1568 if (eld_changed) {
1569 pin_eld->monitor_present = eld->monitor_present;
1570 pin_eld->eld_valid = eld->eld_valid;
1571 pin_eld->eld_size = eld->eld_size;
1572 if (eld->eld_valid)
1573 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1574 eld->eld_size);
1575 pin_eld->info = eld->info;
1576 }
1577
1578 /*
1579 * Re-setup pin and infoframe. This is needed e.g. when
1580 * - sink is first plugged-in
1581 * - transcoder can change during stream playback on Haswell
1582 * and this can make HW reset converter selection on a pin.
1583 */
1584 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1585 pin_cvt_fixup(codec, per_pin, 0);
1586 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1587 }
1588
1589 if (eld_changed && pcm_idx >= 0)
1590 snd_ctl_notify(codec->card,
1591 SNDRV_CTL_EVENT_MASK_VALUE |
1592 SNDRV_CTL_EVENT_MASK_INFO,
1593 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1594
1595 if (eld_changed && pcm_jack)
1596 snd_jack_report(pcm_jack,
1597 (eld->monitor_present && eld->eld_valid) ?
1598 SND_JACK_AVOUT : 0);
1599}
1600
1601/* update ELD and jack state via HD-audio verbs */
1602static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1603 int repoll)
1604{
1605 struct hda_codec *codec = per_pin->codec;
1606 struct hdmi_spec *spec = codec->spec;
1607 struct hdmi_eld *eld = &spec->temp_eld;
1608 struct device *dev = hda_codec_dev(codec);
1609 hda_nid_t pin_nid = per_pin->pin_nid;
1610 int dev_id = per_pin->dev_id;
1611 /*
1612 * Always execute a GetPinSense verb here, even when called from
1613 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1614 * response's PD bit is not the real PD value, but indicates that
1615 * the real PD value changed. An older version of the HD-audio
1616 * specification worked this way. Hence, we just ignore the data in
1617 * the unsolicited response to avoid custom WARs.
1618 */
1619 int present;
1620 int ret;
1621
1622#ifdef CONFIG_PM
1623 if (dev->power.runtime_status == RPM_SUSPENDING)
1624 return;
1625#endif
1626
1627 ret = snd_hda_power_up_pm(codec);
1628 if (ret < 0 && pm_runtime_suspended(dev))
1629 goto out;
1630
1631 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id);
1632
1633 mutex_lock(&per_pin->lock);
1634 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1635 if (eld->monitor_present)
1636 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1637 else
1638 eld->eld_valid = false;
1639
1640 codec_dbg(codec,
1641 "HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n",
1642 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1643
1644 if (eld->eld_valid) {
1645 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id,
1646 eld->eld_buffer, &eld->eld_size) < 0)
1647 eld->eld_valid = false;
1648 }
1649
1650 update_eld(codec, per_pin, eld, repoll);
1651 mutex_unlock(&per_pin->lock);
1652 out:
1653 snd_hda_power_down_pm(codec);
1654}
1655
1656#define I915_SILENT_RATE 48000
1657#define I915_SILENT_CHANNELS 2
1658#define I915_SILENT_FORMAT_BITS 16
1659#define I915_SILENT_FMT_MASK 0xf
1660
1661static void silent_stream_enable_i915(struct hda_codec *codec,
1662 struct hdmi_spec_per_pin *per_pin)
1663{
1664 unsigned int format;
1665
1666 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
1667 per_pin->dev_id, I915_SILENT_RATE);
1668
1669 /* trigger silent stream generation in hw */
1670 format = snd_hdac_stream_format(I915_SILENT_CHANNELS, I915_SILENT_FORMAT_BITS,
1671 I915_SILENT_RATE);
1672 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid,
1673 I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format);
1674 usleep_range(100, 200);
1675 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format);
1676
1677 per_pin->channels = I915_SILENT_CHANNELS;
1678 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1679}
1680
1681static void silent_stream_set_kae(struct hda_codec *codec,
1682 struct hdmi_spec_per_pin *per_pin,
1683 bool enable)
1684{
1685 unsigned int param;
1686
1687 codec_dbg(codec, "HDMI: KAE %d cvt-NID=0x%x\n", enable, per_pin->cvt_nid);
1688
1689 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0);
1690 param = (param >> 16) & 0xff;
1691
1692 if (enable)
1693 param |= AC_DIG3_KAE;
1694 else
1695 param &= ~AC_DIG3_KAE;
1696
1697 snd_hda_codec_write(codec, per_pin->cvt_nid, 0, AC_VERB_SET_DIGI_CONVERT_3, param);
1698}
1699
1700static void silent_stream_enable(struct hda_codec *codec,
1701 struct hdmi_spec_per_pin *per_pin)
1702{
1703 struct hdmi_spec *spec = codec->spec;
1704 struct hdmi_spec_per_cvt *per_cvt;
1705 int cvt_idx, pin_idx, err;
1706 int keep_power = 0;
1707
1708 /*
1709 * Power-up will call hdmi_present_sense, so the PM calls
1710 * have to be done without mutex held.
1711 */
1712
1713 err = snd_hda_power_up_pm(codec);
1714 if (err < 0 && err != -EACCES) {
1715 codec_err(codec,
1716 "Failed to power up codec for silent stream enable ret=[%d]\n", err);
1717 snd_hda_power_down_pm(codec);
1718 return;
1719 }
1720
1721 mutex_lock(&per_pin->lock);
1722
1723 if (per_pin->setup) {
1724 codec_dbg(codec, "hdmi: PCM already open, no silent stream\n");
1725 err = -EBUSY;
1726 goto unlock_out;
1727 }
1728
1729 pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id);
1730 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, true);
1731 if (err) {
1732 codec_err(codec, "hdmi: no free converter to enable silent mode\n");
1733 goto unlock_out;
1734 }
1735
1736 per_cvt = get_cvt(spec, cvt_idx);
1737 per_cvt->silent_stream = true;
1738 per_pin->cvt_nid = per_cvt->cvt_nid;
1739 per_pin->silent_stream = true;
1740
1741 codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n",
1742 per_pin->pin_nid, per_cvt->cvt_nid);
1743
1744 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1745 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1746 AC_VERB_SET_CONNECT_SEL,
1747 per_pin->mux_idx);
1748
1749 /* configure unused pins to choose other converters */
1750 pin_cvt_fixup(codec, per_pin, 0);
1751
1752 switch (spec->silent_stream_type) {
1753 case SILENT_STREAM_KAE:
1754 silent_stream_enable_i915(codec, per_pin);
1755 silent_stream_set_kae(codec, per_pin, true);
1756 break;
1757 case SILENT_STREAM_I915:
1758 silent_stream_enable_i915(codec, per_pin);
1759 keep_power = 1;
1760 break;
1761 default:
1762 break;
1763 }
1764
1765 unlock_out:
1766 mutex_unlock(&per_pin->lock);
1767
1768 if (err || !keep_power)
1769 snd_hda_power_down_pm(codec);
1770}
1771
1772static void silent_stream_disable(struct hda_codec *codec,
1773 struct hdmi_spec_per_pin *per_pin)
1774{
1775 struct hdmi_spec *spec = codec->spec;
1776 struct hdmi_spec_per_cvt *per_cvt;
1777 int cvt_idx, err;
1778
1779 err = snd_hda_power_up_pm(codec);
1780 if (err < 0 && err != -EACCES) {
1781 codec_err(codec,
1782 "Failed to power up codec for silent stream disable ret=[%d]\n",
1783 err);
1784 snd_hda_power_down_pm(codec);
1785 return;
1786 }
1787
1788 mutex_lock(&per_pin->lock);
1789 if (!per_pin->silent_stream)
1790 goto unlock_out;
1791
1792 codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n",
1793 per_pin->pin_nid, per_pin->cvt_nid);
1794
1795 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
1796 if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) {
1797 per_cvt = get_cvt(spec, cvt_idx);
1798 per_cvt->silent_stream = false;
1799 }
1800
1801 if (spec->silent_stream_type == SILENT_STREAM_I915) {
1802 /* release ref taken in silent_stream_enable() */
1803 snd_hda_power_down_pm(codec);
1804 } else if (spec->silent_stream_type == SILENT_STREAM_KAE) {
1805 silent_stream_set_kae(codec, per_pin, false);
1806 }
1807
1808 per_pin->cvt_nid = 0;
1809 per_pin->silent_stream = false;
1810
1811 unlock_out:
1812 mutex_unlock(&per_pin->lock);
1813
1814 snd_hda_power_down_pm(codec);
1815}
1816
1817/* update ELD and jack state via audio component */
1818static void sync_eld_via_acomp(struct hda_codec *codec,
1819 struct hdmi_spec_per_pin *per_pin)
1820{
1821 struct hdmi_spec *spec = codec->spec;
1822 struct hdmi_eld *eld = &spec->temp_eld;
1823 bool monitor_prev, monitor_next;
1824
1825 mutex_lock(&per_pin->lock);
1826 eld->monitor_present = false;
1827 monitor_prev = per_pin->sink_eld.monitor_present;
1828 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1829 per_pin->dev_id, &eld->monitor_present,
1830 eld->eld_buffer, ELD_MAX_SIZE);
1831 eld->eld_valid = (eld->eld_size > 0);
1832 update_eld(codec, per_pin, eld, 0);
1833 monitor_next = per_pin->sink_eld.monitor_present;
1834 mutex_unlock(&per_pin->lock);
1835
1836 if (spec->silent_stream_type) {
1837 if (!monitor_prev && monitor_next)
1838 silent_stream_enable(codec, per_pin);
1839 else if (monitor_prev && !monitor_next)
1840 silent_stream_disable(codec, per_pin);
1841 }
1842}
1843
1844static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1845{
1846 struct hda_codec *codec = per_pin->codec;
1847
1848 if (!codec_has_acomp(codec))
1849 hdmi_present_sense_via_verbs(per_pin, repoll);
1850 else
1851 sync_eld_via_acomp(codec, per_pin);
1852}
1853
1854static void hdmi_repoll_eld(struct work_struct *work)
1855{
1856 struct hdmi_spec_per_pin *per_pin =
1857 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1858 struct hda_codec *codec = per_pin->codec;
1859 struct hdmi_spec *spec = codec->spec;
1860 struct hda_jack_tbl *jack;
1861
1862 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid,
1863 per_pin->dev_id);
1864 if (jack)
1865 jack->jack_dirty = 1;
1866
1867 if (per_pin->repoll_count++ > 6)
1868 per_pin->repoll_count = 0;
1869
1870 mutex_lock(&spec->pcm_lock);
1871 hdmi_present_sense(per_pin, per_pin->repoll_count);
1872 mutex_unlock(&spec->pcm_lock);
1873}
1874
1875static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1876{
1877 struct hdmi_spec *spec = codec->spec;
1878 unsigned int caps, config;
1879 int pin_idx;
1880 struct hdmi_spec_per_pin *per_pin;
1881 int err;
1882 int dev_num, i;
1883
1884 caps = snd_hda_query_pin_caps(codec, pin_nid);
1885 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1886 return 0;
1887
1888 /*
1889 * For DP MST audio, Configuration Default is the same for
1890 * all device entries on the same pin
1891 */
1892 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1893 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE &&
1894 !spec->force_connect)
1895 return 0;
1896
1897 /*
1898 * To simplify the implementation, malloc all
1899 * the virtual pins in the initialization statically
1900 */
1901 if (spec->intel_hsw_fixup) {
1902 /*
1903 * On Intel platforms, device entries count returned
1904 * by AC_PAR_DEVLIST_LEN is dynamic, and depends on
1905 * the type of receiver that is connected. Allocate pin
1906 * structures based on worst case.
1907 */
1908 dev_num = spec->dev_num;
1909 } else if (codec->dp_mst) {
1910 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1911 /*
1912 * spec->dev_num is the maxinum number of device entries
1913 * among all the pins
1914 */
1915 spec->dev_num = (spec->dev_num > dev_num) ?
1916 spec->dev_num : dev_num;
1917 } else {
1918 /*
1919 * If the platform doesn't support DP MST,
1920 * manually set dev_num to 1. This means
1921 * the pin has only one device entry.
1922 */
1923 dev_num = 1;
1924 spec->dev_num = 1;
1925 }
1926
1927 for (i = 0; i < dev_num; i++) {
1928 pin_idx = spec->num_pins;
1929 per_pin = snd_array_new(&spec->pins);
1930
1931 if (!per_pin)
1932 return -ENOMEM;
1933
1934 per_pin->pcm = NULL;
1935 per_pin->pcm_idx = -1;
1936 per_pin->prev_pcm_idx = -1;
1937 per_pin->pin_nid = pin_nid;
1938 per_pin->pin_nid_idx = spec->num_nids;
1939 per_pin->dev_id = i;
1940 per_pin->non_pcm = false;
1941 snd_hda_set_dev_select(codec, pin_nid, i);
1942 err = hdmi_read_pin_conn(codec, pin_idx);
1943 if (err < 0)
1944 return err;
1945 if (!is_jack_detectable(codec, pin_nid))
1946 codec_warn(codec, "HDMI: pin NID 0x%x - jack not detectable\n", pin_nid);
1947 spec->num_pins++;
1948 }
1949 spec->num_nids++;
1950
1951 return 0;
1952}
1953
1954static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1955{
1956 struct hdmi_spec *spec = codec->spec;
1957 struct hdmi_spec_per_cvt *per_cvt;
1958 unsigned int chans;
1959 int err;
1960
1961 chans = get_wcaps(codec, cvt_nid);
1962 chans = get_wcaps_channels(chans);
1963
1964 per_cvt = snd_array_new(&spec->cvts);
1965 if (!per_cvt)
1966 return -ENOMEM;
1967
1968 per_cvt->cvt_nid = cvt_nid;
1969 per_cvt->channels_min = 2;
1970 if (chans <= 16) {
1971 per_cvt->channels_max = chans;
1972 if (chans > spec->chmap.channels_max)
1973 spec->chmap.channels_max = chans;
1974 }
1975
1976 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1977 &per_cvt->rates,
1978 &per_cvt->formats,
1979 NULL,
1980 &per_cvt->maxbps);
1981 if (err < 0)
1982 return err;
1983
1984 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1985 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1986 spec->num_cvts++;
1987
1988 return 0;
1989}
1990
1991static const struct snd_pci_quirk force_connect_list[] = {
1992 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1),
1993 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1),
1994 SND_PCI_QUIRK(0x103c, 0x8711, "HP", 1),
1995 SND_PCI_QUIRK(0x103c, 0x8715, "HP", 1),
1996 SND_PCI_QUIRK(0x1043, 0x86ae, "ASUS", 1), /* Z170 PRO */
1997 SND_PCI_QUIRK(0x1043, 0x86c7, "ASUS", 1), /* Z170M PLUS */
1998 SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1),
1999 SND_PCI_QUIRK(0x8086, 0x2060, "Intel NUC5CPYB", 1),
2000 SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1),
2001 {}
2002};
2003
2004static int hdmi_parse_codec(struct hda_codec *codec)
2005{
2006 struct hdmi_spec *spec = codec->spec;
2007 hda_nid_t start_nid;
2008 unsigned int caps;
2009 int i, nodes;
2010 const struct snd_pci_quirk *q;
2011
2012 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid);
2013 if (!start_nid || nodes < 0) {
2014 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
2015 return -EINVAL;
2016 }
2017
2018 if (enable_all_pins)
2019 spec->force_connect = true;
2020
2021 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list);
2022
2023 if (q && q->value)
2024 spec->force_connect = true;
2025
2026 /*
2027 * hdmi_add_pin() assumes total amount of converters to
2028 * be known, so first discover all converters
2029 */
2030 for (i = 0; i < nodes; i++) {
2031 hda_nid_t nid = start_nid + i;
2032
2033 caps = get_wcaps(codec, nid);
2034
2035 if (!(caps & AC_WCAP_DIGITAL))
2036 continue;
2037
2038 if (get_wcaps_type(caps) == AC_WID_AUD_OUT)
2039 hdmi_add_cvt(codec, nid);
2040 }
2041
2042 /* discover audio pins */
2043 for (i = 0; i < nodes; i++) {
2044 hda_nid_t nid = start_nid + i;
2045
2046 caps = get_wcaps(codec, nid);
2047
2048 if (!(caps & AC_WCAP_DIGITAL))
2049 continue;
2050
2051 if (get_wcaps_type(caps) == AC_WID_PIN)
2052 hdmi_add_pin(codec, nid);
2053 }
2054
2055 return 0;
2056}
2057
2058/*
2059 */
2060static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
2061{
2062 struct hda_spdif_out *spdif;
2063 bool non_pcm;
2064
2065 mutex_lock(&codec->spdif_mutex);
2066 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
2067 /* Add sanity check to pass klockwork check.
2068 * This should never happen.
2069 */
2070 if (WARN_ON(spdif == NULL)) {
2071 mutex_unlock(&codec->spdif_mutex);
2072 return true;
2073 }
2074 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
2075 mutex_unlock(&codec->spdif_mutex);
2076 return non_pcm;
2077}
2078
2079/*
2080 * HDMI callbacks
2081 */
2082
2083static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2084 struct hda_codec *codec,
2085 unsigned int stream_tag,
2086 unsigned int format,
2087 struct snd_pcm_substream *substream)
2088{
2089 hda_nid_t cvt_nid = hinfo->nid;
2090 struct hdmi_spec *spec = codec->spec;
2091 int pin_idx;
2092 struct hdmi_spec_per_pin *per_pin;
2093 struct snd_pcm_runtime *runtime = substream->runtime;
2094 bool non_pcm;
2095 int pinctl, stripe;
2096 int err = 0;
2097
2098 mutex_lock(&spec->pcm_lock);
2099 pin_idx = hinfo_to_pin_index(codec, hinfo);
2100 if (pin_idx < 0) {
2101 /* when pcm is not bound to a pin skip pin setup and return 0
2102 * to make audio playback be ongoing
2103 */
2104 pin_cvt_fixup(codec, NULL, cvt_nid);
2105 snd_hda_codec_setup_stream(codec, cvt_nid,
2106 stream_tag, 0, format);
2107 goto unlock;
2108 }
2109
2110 per_pin = get_pin(spec, pin_idx);
2111
2112 /* Verify pin:cvt selections to avoid silent audio after S3.
2113 * After S3, the audio driver restores pin:cvt selections
2114 * but this can happen before gfx is ready and such selection
2115 * is overlooked by HW. Thus multiple pins can share a same
2116 * default convertor and mute control will affect each other,
2117 * which can cause a resumed audio playback become silent
2118 * after S3.
2119 */
2120 pin_cvt_fixup(codec, per_pin, 0);
2121
2122 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
2123 /* Todo: add DP1.2 MST audio support later */
2124 if (codec_has_acomp(codec))
2125 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
2126 per_pin->dev_id, runtime->rate);
2127
2128 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
2129 mutex_lock(&per_pin->lock);
2130 per_pin->channels = substream->runtime->channels;
2131 per_pin->setup = true;
2132
2133 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
2134 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
2135 substream);
2136 snd_hda_codec_write(codec, cvt_nid, 0,
2137 AC_VERB_SET_STRIPE_CONTROL,
2138 stripe);
2139 }
2140
2141 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
2142 mutex_unlock(&per_pin->lock);
2143 if (spec->dyn_pin_out) {
2144 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2145 per_pin->dev_id);
2146 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2147 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2148 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2149 AC_VERB_SET_PIN_WIDGET_CONTROL,
2150 pinctl | PIN_OUT);
2151 }
2152
2153 /* snd_hda_set_dev_select() has been called before */
2154 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid,
2155 per_pin->dev_id, stream_tag, format);
2156 unlock:
2157 mutex_unlock(&spec->pcm_lock);
2158 return err;
2159}
2160
2161static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2162 struct hda_codec *codec,
2163 struct snd_pcm_substream *substream)
2164{
2165 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2166 return 0;
2167}
2168
2169static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
2170 struct hda_codec *codec,
2171 struct snd_pcm_substream *substream)
2172{
2173 struct hdmi_spec *spec = codec->spec;
2174 int cvt_idx, pin_idx, pcm_idx;
2175 struct hdmi_spec_per_cvt *per_cvt;
2176 struct hdmi_spec_per_pin *per_pin;
2177 int pinctl;
2178 int err = 0;
2179
2180 mutex_lock(&spec->pcm_lock);
2181 if (hinfo->nid) {
2182 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
2183 if (snd_BUG_ON(pcm_idx < 0)) {
2184 err = -EINVAL;
2185 goto unlock;
2186 }
2187 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
2188 if (snd_BUG_ON(cvt_idx < 0)) {
2189 err = -EINVAL;
2190 goto unlock;
2191 }
2192 per_cvt = get_cvt(spec, cvt_idx);
2193 per_cvt->assigned = false;
2194 hinfo->nid = 0;
2195
2196 azx_stream(get_azx_dev(substream))->stripe = 0;
2197
2198 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2199 clear_bit(pcm_idx, &spec->pcm_in_use);
2200 pin_idx = hinfo_to_pin_index(codec, hinfo);
2201 /*
2202 * In such a case, return 0 to match the behavior in
2203 * hdmi_pcm_open()
2204 */
2205 if (pin_idx < 0)
2206 goto unlock;
2207
2208 per_pin = get_pin(spec, pin_idx);
2209
2210 if (spec->dyn_pin_out) {
2211 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2212 per_pin->dev_id);
2213 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2214 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2215 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2216 AC_VERB_SET_PIN_WIDGET_CONTROL,
2217 pinctl & ~PIN_OUT);
2218 }
2219
2220 mutex_lock(&per_pin->lock);
2221 per_pin->chmap_set = false;
2222 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
2223
2224 per_pin->setup = false;
2225 per_pin->channels = 0;
2226 mutex_unlock(&per_pin->lock);
2227 }
2228
2229unlock:
2230 mutex_unlock(&spec->pcm_lock);
2231
2232 return err;
2233}
2234
2235static const struct hda_pcm_ops generic_ops = {
2236 .open = hdmi_pcm_open,
2237 .close = hdmi_pcm_close,
2238 .prepare = generic_hdmi_playback_pcm_prepare,
2239 .cleanup = generic_hdmi_playback_pcm_cleanup,
2240};
2241
2242static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2243{
2244 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2245 struct hdmi_spec *spec = codec->spec;
2246 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2247
2248 if (!per_pin)
2249 return 0;
2250
2251 return per_pin->sink_eld.info.spk_alloc;
2252}
2253
2254static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2255 unsigned char *chmap)
2256{
2257 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2258 struct hdmi_spec *spec = codec->spec;
2259 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2260
2261 /* chmap is already set to 0 in caller */
2262 if (!per_pin)
2263 return;
2264
2265 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2266}
2267
2268static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2269 unsigned char *chmap, int prepared)
2270{
2271 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2272 struct hdmi_spec *spec = codec->spec;
2273 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2274
2275 if (!per_pin)
2276 return;
2277 mutex_lock(&per_pin->lock);
2278 per_pin->chmap_set = true;
2279 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2280 if (prepared)
2281 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2282 mutex_unlock(&per_pin->lock);
2283}
2284
2285static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2286{
2287 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2288 struct hdmi_spec *spec = codec->spec;
2289 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2290
2291 return per_pin ? true:false;
2292}
2293
2294static int generic_hdmi_build_pcms(struct hda_codec *codec)
2295{
2296 struct hdmi_spec *spec = codec->spec;
2297 int idx, pcm_num;
2298
2299 /* limit the PCM devices to the codec converters or available PINs */
2300 pcm_num = min(spec->num_cvts, spec->num_pins);
2301 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num);
2302
2303 for (idx = 0; idx < pcm_num; idx++) {
2304 struct hdmi_spec_per_cvt *per_cvt;
2305 struct hda_pcm *info;
2306 struct hda_pcm_stream *pstr;
2307
2308 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2309 if (!info)
2310 return -ENOMEM;
2311
2312 spec->pcm_rec[idx].pcm = info;
2313 spec->pcm_used++;
2314 info->pcm_type = HDA_PCM_TYPE_HDMI;
2315 info->own_chmap = true;
2316
2317 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2318 pstr->substreams = 1;
2319 pstr->ops = generic_ops;
2320
2321 per_cvt = get_cvt(spec, 0);
2322 pstr->channels_min = per_cvt->channels_min;
2323 pstr->channels_max = per_cvt->channels_max;
2324
2325 /* pcm number is less than pcm_rec array size */
2326 if (spec->pcm_used >= ARRAY_SIZE(spec->pcm_rec))
2327 break;
2328 /* other pstr fields are set in open */
2329 }
2330
2331 return 0;
2332}
2333
2334static void free_hdmi_jack_priv(struct snd_jack *jack)
2335{
2336 struct hdmi_pcm *pcm = jack->private_data;
2337
2338 pcm->jack = NULL;
2339}
2340
2341static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2342{
2343 char hdmi_str[32] = "HDMI/DP";
2344 struct hdmi_spec *spec = codec->spec;
2345 struct snd_jack *jack;
2346 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2347 int err;
2348
2349 if (pcmdev > 0)
2350 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2351
2352 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack,
2353 true, false);
2354 if (err < 0)
2355 return err;
2356
2357 spec->pcm_rec[pcm_idx].jack = jack;
2358 jack->private_data = &spec->pcm_rec[pcm_idx];
2359 jack->private_free = free_hdmi_jack_priv;
2360 return 0;
2361}
2362
2363static int generic_hdmi_build_controls(struct hda_codec *codec)
2364{
2365 struct hdmi_spec *spec = codec->spec;
2366 int dev, err;
2367 int pin_idx, pcm_idx;
2368
2369 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2370 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2371 /* no PCM: mark this for skipping permanently */
2372 set_bit(pcm_idx, &spec->pcm_bitmap);
2373 continue;
2374 }
2375
2376 err = generic_hdmi_build_jack(codec, pcm_idx);
2377 if (err < 0)
2378 return err;
2379
2380 /* create the spdif for each pcm
2381 * pin will be bound when monitor is connected
2382 */
2383 err = snd_hda_create_dig_out_ctls(codec,
2384 0, spec->cvt_nids[0],
2385 HDA_PCM_TYPE_HDMI);
2386 if (err < 0)
2387 return err;
2388 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2389
2390 dev = get_pcm_rec(spec, pcm_idx)->device;
2391 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2392 /* add control for ELD Bytes */
2393 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2394 if (err < 0)
2395 return err;
2396 }
2397 }
2398
2399 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2400 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2401 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
2402
2403 if (spec->static_pcm_mapping) {
2404 hdmi_attach_hda_pcm(spec, per_pin);
2405 hdmi_pcm_setup_pin(spec, per_pin);
2406 }
2407
2408 pin_eld->eld_valid = false;
2409 hdmi_present_sense(per_pin, 0);
2410 }
2411
2412 /* add channel maps */
2413 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2414 struct hda_pcm *pcm;
2415
2416 pcm = get_pcm_rec(spec, pcm_idx);
2417 if (!pcm || !pcm->pcm)
2418 break;
2419 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2420 if (err < 0)
2421 return err;
2422 }
2423
2424 return 0;
2425}
2426
2427static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2428{
2429 struct hdmi_spec *spec = codec->spec;
2430 int pin_idx;
2431
2432 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2433 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2434
2435 per_pin->codec = codec;
2436 mutex_init(&per_pin->lock);
2437 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2438 eld_proc_new(per_pin, pin_idx);
2439 }
2440 return 0;
2441}
2442
2443static int generic_hdmi_init(struct hda_codec *codec)
2444{
2445 struct hdmi_spec *spec = codec->spec;
2446 int pin_idx;
2447
2448 mutex_lock(&spec->bind_lock);
2449 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2450 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2451 hda_nid_t pin_nid = per_pin->pin_nid;
2452 int dev_id = per_pin->dev_id;
2453
2454 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2455 hdmi_init_pin(codec, pin_nid);
2456 if (codec_has_acomp(codec))
2457 continue;
2458 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id,
2459 jack_callback);
2460 }
2461 mutex_unlock(&spec->bind_lock);
2462 return 0;
2463}
2464
2465static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2466{
2467 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2468 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2469}
2470
2471static void hdmi_array_free(struct hdmi_spec *spec)
2472{
2473 snd_array_free(&spec->pins);
2474 snd_array_free(&spec->cvts);
2475}
2476
2477static void generic_spec_free(struct hda_codec *codec)
2478{
2479 struct hdmi_spec *spec = codec->spec;
2480
2481 if (spec) {
2482 hdmi_array_free(spec);
2483 kfree(spec);
2484 codec->spec = NULL;
2485 }
2486 codec->dp_mst = false;
2487}
2488
2489static void generic_hdmi_free(struct hda_codec *codec)
2490{
2491 struct hdmi_spec *spec = codec->spec;
2492 int pin_idx, pcm_idx;
2493
2494 if (spec->acomp_registered) {
2495 snd_hdac_acomp_exit(&codec->bus->core);
2496 } else if (codec_has_acomp(codec)) {
2497 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2498 }
2499 codec->relaxed_resume = 0;
2500
2501 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2502 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2503 cancel_delayed_work_sync(&per_pin->work);
2504 eld_proc_free(per_pin);
2505 }
2506
2507 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2508 if (spec->pcm_rec[pcm_idx].jack == NULL)
2509 continue;
2510 snd_device_free(codec->card, spec->pcm_rec[pcm_idx].jack);
2511 }
2512
2513 generic_spec_free(codec);
2514}
2515
2516#ifdef CONFIG_PM
2517static int generic_hdmi_suspend(struct hda_codec *codec)
2518{
2519 struct hdmi_spec *spec = codec->spec;
2520 int pin_idx;
2521
2522 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2523 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2524 cancel_delayed_work_sync(&per_pin->work);
2525 }
2526 return 0;
2527}
2528
2529static int generic_hdmi_resume(struct hda_codec *codec)
2530{
2531 struct hdmi_spec *spec = codec->spec;
2532 int pin_idx;
2533
2534 codec->patch_ops.init(codec);
2535 snd_hda_regmap_sync(codec);
2536
2537 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2538 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2539 hdmi_present_sense(per_pin, 1);
2540 }
2541 return 0;
2542}
2543#endif
2544
2545static const struct hda_codec_ops generic_hdmi_patch_ops = {
2546 .init = generic_hdmi_init,
2547 .free = generic_hdmi_free,
2548 .build_pcms = generic_hdmi_build_pcms,
2549 .build_controls = generic_hdmi_build_controls,
2550 .unsol_event = hdmi_unsol_event,
2551#ifdef CONFIG_PM
2552 .suspend = generic_hdmi_suspend,
2553 .resume = generic_hdmi_resume,
2554#endif
2555};
2556
2557static const struct hdmi_ops generic_standard_hdmi_ops = {
2558 .pin_get_eld = hdmi_pin_get_eld,
2559 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2560 .pin_hbr_setup = hdmi_pin_hbr_setup,
2561 .setup_stream = hdmi_setup_stream,
2562};
2563
2564/* allocate codec->spec and assign/initialize generic parser ops */
2565static int alloc_generic_hdmi(struct hda_codec *codec)
2566{
2567 struct hdmi_spec *spec;
2568
2569 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2570 if (!spec)
2571 return -ENOMEM;
2572
2573 spec->codec = codec;
2574 spec->ops = generic_standard_hdmi_ops;
2575 spec->dev_num = 1; /* initialize to 1 */
2576 mutex_init(&spec->pcm_lock);
2577 mutex_init(&spec->bind_lock);
2578 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2579
2580 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2581 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2582 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2583 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc;
2584
2585 codec->spec = spec;
2586 hdmi_array_init(spec, 4);
2587
2588 codec->patch_ops = generic_hdmi_patch_ops;
2589
2590 return 0;
2591}
2592
2593/* generic HDMI parser */
2594static int patch_generic_hdmi(struct hda_codec *codec)
2595{
2596 int err;
2597
2598 err = alloc_generic_hdmi(codec);
2599 if (err < 0)
2600 return err;
2601
2602 err = hdmi_parse_codec(codec);
2603 if (err < 0) {
2604 generic_spec_free(codec);
2605 return err;
2606 }
2607
2608 generic_hdmi_init_per_pins(codec);
2609 return 0;
2610}
2611
2612/*
2613 * generic audio component binding
2614 */
2615
2616/* turn on / off the unsol event jack detection dynamically */
2617static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2618 int dev_id, bool use_acomp)
2619{
2620 struct hda_jack_tbl *tbl;
2621
2622 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id);
2623 if (tbl) {
2624 /* clear unsol even if component notifier is used, or re-enable
2625 * if notifier is cleared
2626 */
2627 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
2628 snd_hda_codec_write_cache(codec, nid, 0,
2629 AC_VERB_SET_UNSOLICITED_ENABLE, val);
2630 }
2631}
2632
2633/* set up / clear component notifier dynamically */
2634static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
2635 bool use_acomp)
2636{
2637 struct hdmi_spec *spec;
2638 int i;
2639
2640 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
2641 mutex_lock(&spec->bind_lock);
2642 spec->use_acomp_notifier = use_acomp;
2643 spec->codec->relaxed_resume = use_acomp;
2644 spec->codec->bus->keep_power = 0;
2645 /* reprogram each jack detection logic depending on the notifier */
2646 for (i = 0; i < spec->num_pins; i++)
2647 reprogram_jack_detect(spec->codec,
2648 get_pin(spec, i)->pin_nid,
2649 get_pin(spec, i)->dev_id,
2650 use_acomp);
2651 mutex_unlock(&spec->bind_lock);
2652}
2653
2654/* enable / disable the notifier via master bind / unbind */
2655static int generic_acomp_master_bind(struct device *dev,
2656 struct drm_audio_component *acomp)
2657{
2658 generic_acomp_notifier_set(acomp, true);
2659 return 0;
2660}
2661
2662static void generic_acomp_master_unbind(struct device *dev,
2663 struct drm_audio_component *acomp)
2664{
2665 generic_acomp_notifier_set(acomp, false);
2666}
2667
2668/* check whether both HD-audio and DRM PCI devices belong to the same bus */
2669static int match_bound_vga(struct device *dev, int subtype, void *data)
2670{
2671 struct hdac_bus *bus = data;
2672 struct pci_dev *pci, *master;
2673
2674 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
2675 return 0;
2676 master = to_pci_dev(bus->dev);
2677 pci = to_pci_dev(dev);
2678 return master->bus == pci->bus;
2679}
2680
2681/* audio component notifier for AMD/Nvidia HDMI codecs */
2682static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
2683{
2684 struct hda_codec *codec = audio_ptr;
2685 struct hdmi_spec *spec = codec->spec;
2686 hda_nid_t pin_nid = spec->port2pin(codec, port);
2687
2688 if (!pin_nid)
2689 return;
2690 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
2691 return;
2692 /* skip notification during system suspend (but not in runtime PM);
2693 * the state will be updated at resume
2694 */
2695 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
2696 return;
2697
2698 check_presence_and_report(codec, pin_nid, dev_id);
2699}
2700
2701/* set up the private drm_audio_ops from the template */
2702static void setup_drm_audio_ops(struct hda_codec *codec,
2703 const struct drm_audio_component_audio_ops *ops)
2704{
2705 struct hdmi_spec *spec = codec->spec;
2706
2707 spec->drm_audio_ops.audio_ptr = codec;
2708 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2709 * will call pin_eld_notify with using audio_ptr pointer
2710 * We need make sure audio_ptr is really setup
2711 */
2712 wmb();
2713 spec->drm_audio_ops.pin2port = ops->pin2port;
2714 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
2715 spec->drm_audio_ops.master_bind = ops->master_bind;
2716 spec->drm_audio_ops.master_unbind = ops->master_unbind;
2717}
2718
2719/* initialize the generic HDMI audio component */
2720static void generic_acomp_init(struct hda_codec *codec,
2721 const struct drm_audio_component_audio_ops *ops,
2722 int (*port2pin)(struct hda_codec *, int))
2723{
2724 struct hdmi_spec *spec = codec->spec;
2725
2726 if (!enable_acomp) {
2727 codec_info(codec, "audio component disabled by module option\n");
2728 return;
2729 }
2730
2731 spec->port2pin = port2pin;
2732 setup_drm_audio_ops(codec, ops);
2733 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
2734 match_bound_vga, 0)) {
2735 spec->acomp_registered = true;
2736 }
2737}
2738
2739/*
2740 * Intel codec parsers and helpers
2741 */
2742
2743#define INTEL_GET_VENDOR_VERB 0xf81
2744#define INTEL_SET_VENDOR_VERB 0x781
2745#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2746#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2747
2748static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2749 bool update_tree)
2750{
2751 unsigned int vendor_param;
2752 struct hdmi_spec *spec = codec->spec;
2753
2754 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2755 INTEL_GET_VENDOR_VERB, 0);
2756 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2757 return;
2758
2759 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2760 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2761 INTEL_SET_VENDOR_VERB, vendor_param);
2762 if (vendor_param == -1)
2763 return;
2764
2765 if (update_tree)
2766 snd_hda_codec_update_widgets(codec);
2767}
2768
2769static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2770{
2771 unsigned int vendor_param;
2772 struct hdmi_spec *spec = codec->spec;
2773
2774 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2775 INTEL_GET_VENDOR_VERB, 0);
2776 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2777 return;
2778
2779 /* enable DP1.2 mode */
2780 vendor_param |= INTEL_EN_DP12;
2781 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2782 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2783 INTEL_SET_VENDOR_VERB, vendor_param);
2784}
2785
2786/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2787 * Otherwise you may get severe h/w communication errors.
2788 */
2789static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2790 unsigned int power_state)
2791{
2792 if (power_state == AC_PWRST_D0) {
2793 intel_haswell_enable_all_pins(codec, false);
2794 intel_haswell_fixup_enable_dp12(codec);
2795 }
2796
2797 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2798 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2799}
2800
2801/* There is a fixed mapping between audio pin node and display port.
2802 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2803 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2804 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2805 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2806 *
2807 * on VLV, ILK:
2808 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2809 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2810 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2811 */
2812static int intel_base_nid(struct hda_codec *codec)
2813{
2814 switch (codec->core.vendor_id) {
2815 case 0x80860054: /* ILK */
2816 case 0x80862804: /* ILK */
2817 case 0x80862882: /* VLV */
2818 return 4;
2819 default:
2820 return 5;
2821 }
2822}
2823
2824static int intel_pin2port(void *audio_ptr, int pin_nid)
2825{
2826 struct hda_codec *codec = audio_ptr;
2827 struct hdmi_spec *spec = codec->spec;
2828 int base_nid, i;
2829
2830 if (!spec->port_num) {
2831 base_nid = intel_base_nid(codec);
2832 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2833 return -1;
2834 return pin_nid - base_nid + 1;
2835 }
2836
2837 /*
2838 * looking for the pin number in the mapping table and return
2839 * the index which indicate the port number
2840 */
2841 for (i = 0; i < spec->port_num; i++) {
2842 if (pin_nid == spec->port_map[i])
2843 return i;
2844 }
2845
2846 codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid);
2847 return -1;
2848}
2849
2850static int intel_port2pin(struct hda_codec *codec, int port)
2851{
2852 struct hdmi_spec *spec = codec->spec;
2853
2854 if (!spec->port_num) {
2855 /* we assume only from port-B to port-D */
2856 if (port < 1 || port > 3)
2857 return 0;
2858 return port + intel_base_nid(codec) - 1;
2859 }
2860
2861 if (port < 0 || port >= spec->port_num)
2862 return 0;
2863 return spec->port_map[port];
2864}
2865
2866static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2867{
2868 struct hda_codec *codec = audio_ptr;
2869 int pin_nid;
2870 int dev_id = pipe;
2871
2872 pin_nid = intel_port2pin(codec, port);
2873 if (!pin_nid)
2874 return;
2875 /* skip notification during system suspend (but not in runtime PM);
2876 * the state will be updated at resume
2877 */
2878 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
2879 return;
2880
2881 snd_hdac_i915_set_bclk(&codec->bus->core);
2882 check_presence_and_report(codec, pin_nid, dev_id);
2883}
2884
2885static const struct drm_audio_component_audio_ops intel_audio_ops = {
2886 .pin2port = intel_pin2port,
2887 .pin_eld_notify = intel_pin_eld_notify,
2888};
2889
2890/* register i915 component pin_eld_notify callback */
2891static void register_i915_notifier(struct hda_codec *codec)
2892{
2893 struct hdmi_spec *spec = codec->spec;
2894
2895 spec->use_acomp_notifier = true;
2896 spec->port2pin = intel_port2pin;
2897 setup_drm_audio_ops(codec, &intel_audio_ops);
2898 snd_hdac_acomp_register_notifier(&codec->bus->core,
2899 &spec->drm_audio_ops);
2900 /* no need for forcible resume for jack check thanks to notifier */
2901 codec->relaxed_resume = 1;
2902}
2903
2904/* setup_stream ops override for HSW+ */
2905static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2906 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
2907 int format)
2908{
2909 struct hdmi_spec *spec = codec->spec;
2910 int pin_idx = pin_id_to_pin_index(codec, pin_nid, dev_id);
2911 struct hdmi_spec_per_pin *per_pin;
2912 int res;
2913
2914 if (pin_idx < 0)
2915 per_pin = NULL;
2916 else
2917 per_pin = get_pin(spec, pin_idx);
2918
2919 haswell_verify_D0(codec, cvt_nid, pin_nid);
2920
2921 if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) {
2922 silent_stream_set_kae(codec, per_pin, false);
2923 /* wait for pending transfers in codec to clear */
2924 usleep_range(100, 200);
2925 }
2926
2927 res = hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
2928 stream_tag, format);
2929
2930 if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) {
2931 usleep_range(100, 200);
2932 silent_stream_set_kae(codec, per_pin, true);
2933 }
2934
2935 return res;
2936}
2937
2938/* pin_cvt_fixup ops override for HSW+ and VLV+ */
2939static void i915_pin_cvt_fixup(struct hda_codec *codec,
2940 struct hdmi_spec_per_pin *per_pin,
2941 hda_nid_t cvt_nid)
2942{
2943 if (per_pin) {
2944 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid);
2945 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2946 per_pin->dev_id);
2947 intel_verify_pin_cvt_connect(codec, per_pin);
2948 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2949 per_pin->dev_id, per_pin->mux_idx);
2950 } else {
2951 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2952 }
2953}
2954
2955#ifdef CONFIG_PM
2956static int i915_adlp_hdmi_suspend(struct hda_codec *codec)
2957{
2958 struct hdmi_spec *spec = codec->spec;
2959 bool silent_streams = false;
2960 int pin_idx, res;
2961
2962 res = generic_hdmi_suspend(codec);
2963
2964 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2965 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2966
2967 if (per_pin->silent_stream) {
2968 silent_streams = true;
2969 break;
2970 }
2971 }
2972
2973 if (silent_streams && spec->silent_stream_type == SILENT_STREAM_KAE) {
2974 /*
2975 * stream-id should remain programmed when codec goes
2976 * to runtime suspend
2977 */
2978 codec->no_stream_clean_at_suspend = 1;
2979
2980 /*
2981 * the system might go to S3, in which case keep-alive
2982 * must be reprogrammed upon resume
2983 */
2984 codec->forced_resume = 1;
2985
2986 codec_dbg(codec, "HDMI: KAE active at suspend\n");
2987 } else {
2988 codec->no_stream_clean_at_suspend = 0;
2989 codec->forced_resume = 0;
2990 }
2991
2992 return res;
2993}
2994
2995static int i915_adlp_hdmi_resume(struct hda_codec *codec)
2996{
2997 struct hdmi_spec *spec = codec->spec;
2998 int pin_idx, res;
2999
3000 res = generic_hdmi_resume(codec);
3001
3002 /* KAE not programmed at suspend, nothing to do here */
3003 if (!codec->no_stream_clean_at_suspend)
3004 return res;
3005
3006 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3007 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3008
3009 /*
3010 * If system was in suspend with monitor connected,
3011 * the codec setting may have been lost. Re-enable
3012 * keep-alive.
3013 */
3014 if (per_pin->silent_stream) {
3015 unsigned int param;
3016
3017 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0,
3018 AC_VERB_GET_CONV, 0);
3019 if (!param) {
3020 codec_dbg(codec, "HDMI: KAE: restore stream id\n");
3021 silent_stream_enable_i915(codec, per_pin);
3022 }
3023
3024 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0,
3025 AC_VERB_GET_DIGI_CONVERT_1, 0);
3026 if (!(param & (AC_DIG3_KAE << 16))) {
3027 codec_dbg(codec, "HDMI: KAE: restore DIG3_KAE\n");
3028 silent_stream_set_kae(codec, per_pin, true);
3029 }
3030 }
3031 }
3032
3033 return res;
3034}
3035#endif
3036
3037/* precondition and allocation for Intel codecs */
3038static int alloc_intel_hdmi(struct hda_codec *codec)
3039{
3040 int err;
3041
3042 /* requires i915 binding */
3043 if (!codec->bus->core.audio_component) {
3044 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
3045 /* set probe_id here to prevent generic fallback binding */
3046 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
3047 return -ENODEV;
3048 }
3049
3050 err = alloc_generic_hdmi(codec);
3051 if (err < 0)
3052 return err;
3053 /* no need to handle unsol events */
3054 codec->patch_ops.unsol_event = NULL;
3055 return 0;
3056}
3057
3058/* parse and post-process for Intel codecs */
3059static int parse_intel_hdmi(struct hda_codec *codec)
3060{
3061 int err, retries = 3;
3062
3063 do {
3064 err = hdmi_parse_codec(codec);
3065 } while (err < 0 && retries--);
3066
3067 if (err < 0) {
3068 generic_spec_free(codec);
3069 return err;
3070 }
3071
3072 generic_hdmi_init_per_pins(codec);
3073 register_i915_notifier(codec);
3074 return 0;
3075}
3076
3077/* Intel Haswell and onwards; audio component with eld notifier */
3078static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
3079 const int *port_map, int port_num, int dev_num,
3080 bool send_silent_stream)
3081{
3082 struct hdmi_spec *spec;
3083 int err;
3084
3085 err = alloc_intel_hdmi(codec);
3086 if (err < 0)
3087 return err;
3088 spec = codec->spec;
3089 codec->dp_mst = true;
3090 spec->vendor_nid = vendor_nid;
3091 spec->port_map = port_map;
3092 spec->port_num = port_num;
3093 spec->intel_hsw_fixup = true;
3094 spec->dev_num = dev_num;
3095
3096 intel_haswell_enable_all_pins(codec, true);
3097 intel_haswell_fixup_enable_dp12(codec);
3098
3099 codec->display_power_control = 1;
3100
3101 codec->patch_ops.set_power_state = haswell_set_power_state;
3102 codec->depop_delay = 0;
3103 codec->auto_runtime_pm = 1;
3104
3105 spec->ops.setup_stream = i915_hsw_setup_stream;
3106 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
3107
3108 /*
3109 * Enable silent stream feature, if it is enabled via
3110 * module param or Kconfig option
3111 */
3112 if (send_silent_stream)
3113 spec->silent_stream_type = SILENT_STREAM_I915;
3114
3115 return parse_intel_hdmi(codec);
3116}
3117
3118static int patch_i915_hsw_hdmi(struct hda_codec *codec)
3119{
3120 return intel_hsw_common_init(codec, 0x08, NULL, 0, 3,
3121 enable_silent_stream);
3122}
3123
3124static int patch_i915_glk_hdmi(struct hda_codec *codec)
3125{
3126 /*
3127 * Silent stream calls audio component .get_power() from
3128 * .pin_eld_notify(). On GLK this will deadlock in i915 due
3129 * to the audio vs. CDCLK workaround.
3130 */
3131 return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false);
3132}
3133
3134static int patch_i915_icl_hdmi(struct hda_codec *codec)
3135{
3136 /*
3137 * pin to port mapping table where the value indicate the pin number and
3138 * the index indicate the port number.
3139 */
3140 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
3141
3142 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3,
3143 enable_silent_stream);
3144}
3145
3146static int patch_i915_tgl_hdmi(struct hda_codec *codec)
3147{
3148 /*
3149 * pin to port mapping table where the value indicate the pin number and
3150 * the index indicate the port number.
3151 */
3152 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
3153
3154 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4,
3155 enable_silent_stream);
3156}
3157
3158static int patch_i915_adlp_hdmi(struct hda_codec *codec)
3159{
3160 struct hdmi_spec *spec;
3161 int res;
3162
3163 res = patch_i915_tgl_hdmi(codec);
3164 if (!res) {
3165 spec = codec->spec;
3166
3167 if (spec->silent_stream_type) {
3168 spec->silent_stream_type = SILENT_STREAM_KAE;
3169
3170#ifdef CONFIG_PM
3171 codec->patch_ops.resume = i915_adlp_hdmi_resume;
3172 codec->patch_ops.suspend = i915_adlp_hdmi_suspend;
3173#endif
3174 }
3175 }
3176
3177 return res;
3178}
3179
3180/* Intel Baytrail and Braswell; with eld notifier */
3181static int patch_i915_byt_hdmi(struct hda_codec *codec)
3182{
3183 struct hdmi_spec *spec;
3184 int err;
3185
3186 err = alloc_intel_hdmi(codec);
3187 if (err < 0)
3188 return err;
3189 spec = codec->spec;
3190
3191 /* For Valleyview/Cherryview, only the display codec is in the display
3192 * power well and can use link_power ops to request/release the power.
3193 */
3194 codec->display_power_control = 1;
3195
3196 codec->depop_delay = 0;
3197 codec->auto_runtime_pm = 1;
3198
3199 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
3200
3201 return parse_intel_hdmi(codec);
3202}
3203
3204/* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
3205static int patch_i915_cpt_hdmi(struct hda_codec *codec)
3206{
3207 int err;
3208
3209 err = alloc_intel_hdmi(codec);
3210 if (err < 0)
3211 return err;
3212 return parse_intel_hdmi(codec);
3213}
3214
3215/*
3216 * Shared non-generic implementations
3217 */
3218
3219static int simple_playback_build_pcms(struct hda_codec *codec)
3220{
3221 struct hdmi_spec *spec = codec->spec;
3222 struct hda_pcm *info;
3223 unsigned int chans;
3224 struct hda_pcm_stream *pstr;
3225 struct hdmi_spec_per_cvt *per_cvt;
3226
3227 per_cvt = get_cvt(spec, 0);
3228 chans = get_wcaps(codec, per_cvt->cvt_nid);
3229 chans = get_wcaps_channels(chans);
3230
3231 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
3232 if (!info)
3233 return -ENOMEM;
3234 spec->pcm_rec[0].pcm = info;
3235 info->pcm_type = HDA_PCM_TYPE_HDMI;
3236 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
3237 *pstr = spec->pcm_playback;
3238 pstr->nid = per_cvt->cvt_nid;
3239 if (pstr->channels_max <= 2 && chans && chans <= 16)
3240 pstr->channels_max = chans;
3241
3242 return 0;
3243}
3244
3245/* unsolicited event for jack sensing */
3246static void simple_hdmi_unsol_event(struct hda_codec *codec,
3247 unsigned int res)
3248{
3249 snd_hda_jack_set_dirty_all(codec);
3250 snd_hda_jack_report_sync(codec);
3251}
3252
3253/* generic_hdmi_build_jack can be used for simple_hdmi, too,
3254 * as long as spec->pins[] is set correctly
3255 */
3256#define simple_hdmi_build_jack generic_hdmi_build_jack
3257
3258static int simple_playback_build_controls(struct hda_codec *codec)
3259{
3260 struct hdmi_spec *spec = codec->spec;
3261 struct hdmi_spec_per_cvt *per_cvt;
3262 int err;
3263
3264 per_cvt = get_cvt(spec, 0);
3265 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
3266 per_cvt->cvt_nid,
3267 HDA_PCM_TYPE_HDMI);
3268 if (err < 0)
3269 return err;
3270 return simple_hdmi_build_jack(codec, 0);
3271}
3272
3273static int simple_playback_init(struct hda_codec *codec)
3274{
3275 struct hdmi_spec *spec = codec->spec;
3276 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
3277 hda_nid_t pin = per_pin->pin_nid;
3278
3279 snd_hda_codec_write(codec, pin, 0,
3280 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
3281 /* some codecs require to unmute the pin */
3282 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
3283 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
3284 AMP_OUT_UNMUTE);
3285 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id);
3286 return 0;
3287}
3288
3289static void simple_playback_free(struct hda_codec *codec)
3290{
3291 struct hdmi_spec *spec = codec->spec;
3292
3293 hdmi_array_free(spec);
3294 kfree(spec);
3295}
3296
3297/*
3298 * Nvidia specific implementations
3299 */
3300
3301#define Nv_VERB_SET_Channel_Allocation 0xF79
3302#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
3303#define Nv_VERB_SET_Audio_Protection_On 0xF98
3304#define Nv_VERB_SET_Audio_Protection_Off 0xF99
3305
3306#define nvhdmi_master_con_nid_7x 0x04
3307#define nvhdmi_master_pin_nid_7x 0x05
3308
3309static const hda_nid_t nvhdmi_con_nids_7x[4] = {
3310 /*front, rear, clfe, rear_surr */
3311 0x6, 0x8, 0xa, 0xc,
3312};
3313
3314static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
3315 /* set audio protect on */
3316 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3317 /* enable digital output on pin widget */
3318 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3319 {} /* terminator */
3320};
3321
3322static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
3323 /* set audio protect on */
3324 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3325 /* enable digital output on pin widget */
3326 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3327 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3328 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3329 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3330 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3331 {} /* terminator */
3332};
3333
3334#ifdef LIMITED_RATE_FMT_SUPPORT
3335/* support only the safe format and rate */
3336#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
3337#define SUPPORTED_MAXBPS 16
3338#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
3339#else
3340/* support all rates and formats */
3341#define SUPPORTED_RATES \
3342 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
3343 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
3344 SNDRV_PCM_RATE_192000)
3345#define SUPPORTED_MAXBPS 24
3346#define SUPPORTED_FORMATS \
3347 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
3348#endif
3349
3350static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
3351{
3352 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
3353 return 0;
3354}
3355
3356static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
3357{
3358 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
3359 return 0;
3360}
3361
3362static const unsigned int channels_2_6_8[] = {
3363 2, 6, 8
3364};
3365
3366static const unsigned int channels_2_8[] = {
3367 2, 8
3368};
3369
3370static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
3371 .count = ARRAY_SIZE(channels_2_6_8),
3372 .list = channels_2_6_8,
3373 .mask = 0,
3374};
3375
3376static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
3377 .count = ARRAY_SIZE(channels_2_8),
3378 .list = channels_2_8,
3379 .mask = 0,
3380};
3381
3382static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3383 struct hda_codec *codec,
3384 struct snd_pcm_substream *substream)
3385{
3386 struct hdmi_spec *spec = codec->spec;
3387 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
3388
3389 switch (codec->preset->vendor_id) {
3390 case 0x10de0002:
3391 case 0x10de0003:
3392 case 0x10de0005:
3393 case 0x10de0006:
3394 hw_constraints_channels = &hw_constraints_2_8_channels;
3395 break;
3396 case 0x10de0007:
3397 hw_constraints_channels = &hw_constraints_2_6_8_channels;
3398 break;
3399 default:
3400 break;
3401 }
3402
3403 if (hw_constraints_channels != NULL) {
3404 snd_pcm_hw_constraint_list(substream->runtime, 0,
3405 SNDRV_PCM_HW_PARAM_CHANNELS,
3406 hw_constraints_channels);
3407 } else {
3408 snd_pcm_hw_constraint_step(substream->runtime, 0,
3409 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
3410 }
3411
3412 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3413}
3414
3415static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3416 struct hda_codec *codec,
3417 struct snd_pcm_substream *substream)
3418{
3419 struct hdmi_spec *spec = codec->spec;
3420 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3421}
3422
3423static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3424 struct hda_codec *codec,
3425 unsigned int stream_tag,
3426 unsigned int format,
3427 struct snd_pcm_substream *substream)
3428{
3429 struct hdmi_spec *spec = codec->spec;
3430 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3431 stream_tag, format, substream);
3432}
3433
3434static const struct hda_pcm_stream simple_pcm_playback = {
3435 .substreams = 1,
3436 .channels_min = 2,
3437 .channels_max = 2,
3438 .ops = {
3439 .open = simple_playback_pcm_open,
3440 .close = simple_playback_pcm_close,
3441 .prepare = simple_playback_pcm_prepare
3442 },
3443};
3444
3445static const struct hda_codec_ops simple_hdmi_patch_ops = {
3446 .build_controls = simple_playback_build_controls,
3447 .build_pcms = simple_playback_build_pcms,
3448 .init = simple_playback_init,
3449 .free = simple_playback_free,
3450 .unsol_event = simple_hdmi_unsol_event,
3451};
3452
3453static int patch_simple_hdmi(struct hda_codec *codec,
3454 hda_nid_t cvt_nid, hda_nid_t pin_nid)
3455{
3456 struct hdmi_spec *spec;
3457 struct hdmi_spec_per_cvt *per_cvt;
3458 struct hdmi_spec_per_pin *per_pin;
3459
3460 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3461 if (!spec)
3462 return -ENOMEM;
3463
3464 spec->codec = codec;
3465 codec->spec = spec;
3466 hdmi_array_init(spec, 1);
3467
3468 spec->multiout.num_dacs = 0; /* no analog */
3469 spec->multiout.max_channels = 2;
3470 spec->multiout.dig_out_nid = cvt_nid;
3471 spec->num_cvts = 1;
3472 spec->num_pins = 1;
3473 per_pin = snd_array_new(&spec->pins);
3474 per_cvt = snd_array_new(&spec->cvts);
3475 if (!per_pin || !per_cvt) {
3476 simple_playback_free(codec);
3477 return -ENOMEM;
3478 }
3479 per_cvt->cvt_nid = cvt_nid;
3480 per_pin->pin_nid = pin_nid;
3481 spec->pcm_playback = simple_pcm_playback;
3482
3483 codec->patch_ops = simple_hdmi_patch_ops;
3484
3485 return 0;
3486}
3487
3488static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3489 int channels)
3490{
3491 unsigned int chanmask;
3492 int chan = channels ? (channels - 1) : 1;
3493
3494 switch (channels) {
3495 default:
3496 case 0:
3497 case 2:
3498 chanmask = 0x00;
3499 break;
3500 case 4:
3501 chanmask = 0x08;
3502 break;
3503 case 6:
3504 chanmask = 0x0b;
3505 break;
3506 case 8:
3507 chanmask = 0x13;
3508 break;
3509 }
3510
3511 /* Set the audio infoframe channel allocation and checksum fields. The
3512 * channel count is computed implicitly by the hardware. */
3513 snd_hda_codec_write(codec, 0x1, 0,
3514 Nv_VERB_SET_Channel_Allocation, chanmask);
3515
3516 snd_hda_codec_write(codec, 0x1, 0,
3517 Nv_VERB_SET_Info_Frame_Checksum,
3518 (0x71 - chan - chanmask));
3519}
3520
3521static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3522 struct hda_codec *codec,
3523 struct snd_pcm_substream *substream)
3524{
3525 struct hdmi_spec *spec = codec->spec;
3526 int i;
3527
3528 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3529 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3530 for (i = 0; i < 4; i++) {
3531 /* set the stream id */
3532 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3533 AC_VERB_SET_CHANNEL_STREAMID, 0);
3534 /* set the stream format */
3535 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3536 AC_VERB_SET_STREAM_FORMAT, 0);
3537 }
3538
3539 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3540 * streams are disabled. */
3541 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3542
3543 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3544}
3545
3546static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3547 struct hda_codec *codec,
3548 unsigned int stream_tag,
3549 unsigned int format,
3550 struct snd_pcm_substream *substream)
3551{
3552 int chs;
3553 unsigned int dataDCC2, channel_id;
3554 int i;
3555 struct hdmi_spec *spec = codec->spec;
3556 struct hda_spdif_out *spdif;
3557 struct hdmi_spec_per_cvt *per_cvt;
3558
3559 mutex_lock(&codec->spdif_mutex);
3560 per_cvt = get_cvt(spec, 0);
3561 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3562
3563 chs = substream->runtime->channels;
3564
3565 dataDCC2 = 0x2;
3566
3567 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3568 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3569 snd_hda_codec_write(codec,
3570 nvhdmi_master_con_nid_7x,
3571 0,
3572 AC_VERB_SET_DIGI_CONVERT_1,
3573 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3574
3575 /* set the stream id */
3576 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3577 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3578
3579 /* set the stream format */
3580 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3581 AC_VERB_SET_STREAM_FORMAT, format);
3582
3583 /* turn on again (if needed) */
3584 /* enable and set the channel status audio/data flag */
3585 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3586 snd_hda_codec_write(codec,
3587 nvhdmi_master_con_nid_7x,
3588 0,
3589 AC_VERB_SET_DIGI_CONVERT_1,
3590 spdif->ctls & 0xff);
3591 snd_hda_codec_write(codec,
3592 nvhdmi_master_con_nid_7x,
3593 0,
3594 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3595 }
3596
3597 for (i = 0; i < 4; i++) {
3598 if (chs == 2)
3599 channel_id = 0;
3600 else
3601 channel_id = i * 2;
3602
3603 /* turn off SPDIF once;
3604 *otherwise the IEC958 bits won't be updated
3605 */
3606 if (codec->spdif_status_reset &&
3607 (spdif->ctls & AC_DIG1_ENABLE))
3608 snd_hda_codec_write(codec,
3609 nvhdmi_con_nids_7x[i],
3610 0,
3611 AC_VERB_SET_DIGI_CONVERT_1,
3612 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3613 /* set the stream id */
3614 snd_hda_codec_write(codec,
3615 nvhdmi_con_nids_7x[i],
3616 0,
3617 AC_VERB_SET_CHANNEL_STREAMID,
3618 (stream_tag << 4) | channel_id);
3619 /* set the stream format */
3620 snd_hda_codec_write(codec,
3621 nvhdmi_con_nids_7x[i],
3622 0,
3623 AC_VERB_SET_STREAM_FORMAT,
3624 format);
3625 /* turn on again (if needed) */
3626 /* enable and set the channel status audio/data flag */
3627 if (codec->spdif_status_reset &&
3628 (spdif->ctls & AC_DIG1_ENABLE)) {
3629 snd_hda_codec_write(codec,
3630 nvhdmi_con_nids_7x[i],
3631 0,
3632 AC_VERB_SET_DIGI_CONVERT_1,
3633 spdif->ctls & 0xff);
3634 snd_hda_codec_write(codec,
3635 nvhdmi_con_nids_7x[i],
3636 0,
3637 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3638 }
3639 }
3640
3641 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3642
3643 mutex_unlock(&codec->spdif_mutex);
3644 return 0;
3645}
3646
3647static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3648 .substreams = 1,
3649 .channels_min = 2,
3650 .channels_max = 8,
3651 .nid = nvhdmi_master_con_nid_7x,
3652 .rates = SUPPORTED_RATES,
3653 .maxbps = SUPPORTED_MAXBPS,
3654 .formats = SUPPORTED_FORMATS,
3655 .ops = {
3656 .open = simple_playback_pcm_open,
3657 .close = nvhdmi_8ch_7x_pcm_close,
3658 .prepare = nvhdmi_8ch_7x_pcm_prepare
3659 },
3660};
3661
3662static int patch_nvhdmi_2ch(struct hda_codec *codec)
3663{
3664 struct hdmi_spec *spec;
3665 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3666 nvhdmi_master_pin_nid_7x);
3667 if (err < 0)
3668 return err;
3669
3670 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3671 /* override the PCM rates, etc, as the codec doesn't give full list */
3672 spec = codec->spec;
3673 spec->pcm_playback.rates = SUPPORTED_RATES;
3674 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3675 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3676 spec->nv_dp_workaround = true;
3677 return 0;
3678}
3679
3680static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3681{
3682 struct hdmi_spec *spec = codec->spec;
3683 int err = simple_playback_build_pcms(codec);
3684 if (!err) {
3685 struct hda_pcm *info = get_pcm_rec(spec, 0);
3686 info->own_chmap = true;
3687 }
3688 return err;
3689}
3690
3691static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3692{
3693 struct hdmi_spec *spec = codec->spec;
3694 struct hda_pcm *info;
3695 struct snd_pcm_chmap *chmap;
3696 int err;
3697
3698 err = simple_playback_build_controls(codec);
3699 if (err < 0)
3700 return err;
3701
3702 /* add channel maps */
3703 info = get_pcm_rec(spec, 0);
3704 err = snd_pcm_add_chmap_ctls(info->pcm,
3705 SNDRV_PCM_STREAM_PLAYBACK,
3706 snd_pcm_alt_chmaps, 8, 0, &chmap);
3707 if (err < 0)
3708 return err;
3709 switch (codec->preset->vendor_id) {
3710 case 0x10de0002:
3711 case 0x10de0003:
3712 case 0x10de0005:
3713 case 0x10de0006:
3714 chmap->channel_mask = (1U << 2) | (1U << 8);
3715 break;
3716 case 0x10de0007:
3717 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3718 }
3719 return 0;
3720}
3721
3722static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3723{
3724 struct hdmi_spec *spec;
3725 int err = patch_nvhdmi_2ch(codec);
3726 if (err < 0)
3727 return err;
3728 spec = codec->spec;
3729 spec->multiout.max_channels = 8;
3730 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3731 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3732 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3733 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3734
3735 /* Initialize the audio infoframe channel mask and checksum to something
3736 * valid */
3737 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3738
3739 return 0;
3740}
3741
3742/*
3743 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3744 * - 0x10de0015
3745 * - 0x10de0040
3746 */
3747static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3748 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3749{
3750 if (cap->ca_index == 0x00 && channels == 2)
3751 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3752
3753 /* If the speaker allocation matches the channel count, it is OK. */
3754 if (cap->channels != channels)
3755 return -1;
3756
3757 /* all channels are remappable freely */
3758 return SNDRV_CTL_TLVT_CHMAP_VAR;
3759}
3760
3761static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3762 int ca, int chs, unsigned char *map)
3763{
3764 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3765 return -EINVAL;
3766
3767 return 0;
3768}
3769
3770/* map from pin NID to port; port is 0-based */
3771/* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
3772static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
3773{
3774 return pin_nid - 4;
3775}
3776
3777/* reverse-map from port to pin NID: see above */
3778static int nvhdmi_port2pin(struct hda_codec *codec, int port)
3779{
3780 return port + 4;
3781}
3782
3783static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
3784 .pin2port = nvhdmi_pin2port,
3785 .pin_eld_notify = generic_acomp_pin_eld_notify,
3786 .master_bind = generic_acomp_master_bind,
3787 .master_unbind = generic_acomp_master_unbind,
3788};
3789
3790static int patch_nvhdmi(struct hda_codec *codec)
3791{
3792 struct hdmi_spec *spec;
3793 int err;
3794
3795 err = alloc_generic_hdmi(codec);
3796 if (err < 0)
3797 return err;
3798 codec->dp_mst = true;
3799
3800 spec = codec->spec;
3801
3802 err = hdmi_parse_codec(codec);
3803 if (err < 0) {
3804 generic_spec_free(codec);
3805 return err;
3806 }
3807
3808 generic_hdmi_init_per_pins(codec);
3809
3810 spec->dyn_pin_out = true;
3811
3812 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3813 nvhdmi_chmap_cea_alloc_validate_get_type;
3814 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3815 spec->nv_dp_workaround = true;
3816
3817 codec->link_down_at_suspend = 1;
3818
3819 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);
3820
3821 return 0;
3822}
3823
3824static int patch_nvhdmi_legacy(struct hda_codec *codec)
3825{
3826 struct hdmi_spec *spec;
3827 int err;
3828
3829 err = patch_generic_hdmi(codec);
3830 if (err)
3831 return err;
3832
3833 spec = codec->spec;
3834 spec->dyn_pin_out = true;
3835
3836 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3837 nvhdmi_chmap_cea_alloc_validate_get_type;
3838 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3839 spec->nv_dp_workaround = true;
3840
3841 codec->link_down_at_suspend = 1;
3842
3843 return 0;
3844}
3845
3846/*
3847 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3848 * accessed using vendor-defined verbs. These registers can be used for
3849 * interoperability between the HDA and HDMI drivers.
3850 */
3851
3852/* Audio Function Group node */
3853#define NVIDIA_AFG_NID 0x01
3854
3855/*
3856 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3857 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3858 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3859 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3860 * additional bit (at position 30) to signal the validity of the format.
3861 *
3862 * | 31 | 30 | 29 16 | 15 0 |
3863 * +---------+-------+--------+--------+
3864 * | TRIGGER | VALID | UNUSED | FORMAT |
3865 * +-----------------------------------|
3866 *
3867 * Note that for the trigger bit to take effect it needs to change value
3868 * (i.e. it needs to be toggled). The trigger bit is not applicable from
3869 * TEGRA234 chip onwards, as new verb id 0xf80 will be used for interrupt
3870 * trigger to hdmi.
3871 */
3872#define NVIDIA_SET_HOST_INTR 0xf80
3873#define NVIDIA_GET_SCRATCH0 0xfa6
3874#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3875#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3876#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3877#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3878#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3879#define NVIDIA_SCRATCH_VALID (1 << 6)
3880
3881#define NVIDIA_GET_SCRATCH1 0xfab
3882#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3883#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3884#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3885#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3886
3887/*
3888 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3889 * the format is invalidated so that the HDMI codec can be disabled.
3890 */
3891static void tegra_hdmi_set_format(struct hda_codec *codec,
3892 hda_nid_t cvt_nid,
3893 unsigned int format)
3894{
3895 unsigned int value;
3896 unsigned int nid = NVIDIA_AFG_NID;
3897 struct hdmi_spec *spec = codec->spec;
3898
3899 /*
3900 * Tegra HDA codec design from TEGRA234 chip onwards support DP MST.
3901 * This resulted in moving scratch registers from audio function
3902 * group to converter widget context. So CVT NID should be used for
3903 * scratch register read/write for DP MST supported Tegra HDA codec.
3904 */
3905 if (codec->dp_mst)
3906 nid = cvt_nid;
3907
3908 /* bits [31:30] contain the trigger and valid bits */
3909 value = snd_hda_codec_read(codec, nid, 0,
3910 NVIDIA_GET_SCRATCH0, 0);
3911 value = (value >> 24) & 0xff;
3912
3913 /* bits [15:0] are used to store the HDA format */
3914 snd_hda_codec_write(codec, nid, 0,
3915 NVIDIA_SET_SCRATCH0_BYTE0,
3916 (format >> 0) & 0xff);
3917 snd_hda_codec_write(codec, nid, 0,
3918 NVIDIA_SET_SCRATCH0_BYTE1,
3919 (format >> 8) & 0xff);
3920
3921 /* bits [16:24] are unused */
3922 snd_hda_codec_write(codec, nid, 0,
3923 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3924
3925 /*
3926 * Bit 30 signals that the data is valid and hence that HDMI audio can
3927 * be enabled.
3928 */
3929 if (format == 0)
3930 value &= ~NVIDIA_SCRATCH_VALID;
3931 else
3932 value |= NVIDIA_SCRATCH_VALID;
3933
3934 if (spec->hdmi_intr_trig_ctrl) {
3935 /*
3936 * For Tegra HDA Codec design from TEGRA234 onwards, the
3937 * Interrupt to hdmi driver is triggered by writing
3938 * non-zero values to verb 0xF80 instead of 31st bit of
3939 * scratch register.
3940 */
3941 snd_hda_codec_write(codec, nid, 0,
3942 NVIDIA_SET_SCRATCH0_BYTE3, value);
3943 snd_hda_codec_write(codec, nid, 0,
3944 NVIDIA_SET_HOST_INTR, 0x1);
3945 } else {
3946 /*
3947 * Whenever the 31st trigger bit is toggled, an interrupt is raised
3948 * in the HDMI codec. The HDMI driver will use that as trigger
3949 * to update its configuration.
3950 */
3951 value ^= NVIDIA_SCRATCH_TRIGGER;
3952
3953 snd_hda_codec_write(codec, nid, 0,
3954 NVIDIA_SET_SCRATCH0_BYTE3, value);
3955 }
3956}
3957
3958static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3959 struct hda_codec *codec,
3960 unsigned int stream_tag,
3961 unsigned int format,
3962 struct snd_pcm_substream *substream)
3963{
3964 int err;
3965
3966 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3967 format, substream);
3968 if (err < 0)
3969 return err;
3970
3971 /* notify the HDMI codec of the format change */
3972 tegra_hdmi_set_format(codec, hinfo->nid, format);
3973
3974 return 0;
3975}
3976
3977static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3978 struct hda_codec *codec,
3979 struct snd_pcm_substream *substream)
3980{
3981 /* invalidate the format in the HDMI codec */
3982 tegra_hdmi_set_format(codec, hinfo->nid, 0);
3983
3984 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3985}
3986
3987static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3988{
3989 struct hdmi_spec *spec = codec->spec;
3990 unsigned int i;
3991
3992 for (i = 0; i < spec->num_pins; i++) {
3993 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3994
3995 if (pcm->pcm_type == type)
3996 return pcm;
3997 }
3998
3999 return NULL;
4000}
4001
4002static int tegra_hdmi_build_pcms(struct hda_codec *codec)
4003{
4004 struct hda_pcm_stream *stream;
4005 struct hda_pcm *pcm;
4006 int err;
4007
4008 err = generic_hdmi_build_pcms(codec);
4009 if (err < 0)
4010 return err;
4011
4012 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
4013 if (!pcm)
4014 return -ENODEV;
4015
4016 /*
4017 * Override ->prepare() and ->cleanup() operations to notify the HDMI
4018 * codec about format changes.
4019 */
4020 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
4021 stream->ops.prepare = tegra_hdmi_pcm_prepare;
4022 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
4023
4024 return 0;
4025}
4026
4027static int tegra_hdmi_init(struct hda_codec *codec)
4028{
4029 struct hdmi_spec *spec = codec->spec;
4030 int i, err;
4031
4032 err = hdmi_parse_codec(codec);
4033 if (err < 0) {
4034 generic_spec_free(codec);
4035 return err;
4036 }
4037
4038 for (i = 0; i < spec->num_cvts; i++)
4039 snd_hda_codec_write(codec, spec->cvt_nids[i], 0,
4040 AC_VERB_SET_DIGI_CONVERT_1,
4041 AC_DIG1_ENABLE);
4042
4043 generic_hdmi_init_per_pins(codec);
4044
4045 codec->depop_delay = 10;
4046 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
4047 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4048 nvhdmi_chmap_cea_alloc_validate_get_type;
4049 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
4050
4051 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4052 nvhdmi_chmap_cea_alloc_validate_get_type;
4053 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
4054 spec->nv_dp_workaround = true;
4055
4056 return 0;
4057}
4058
4059static int patch_tegra_hdmi(struct hda_codec *codec)
4060{
4061 int err;
4062
4063 err = alloc_generic_hdmi(codec);
4064 if (err < 0)
4065 return err;
4066
4067 return tegra_hdmi_init(codec);
4068}
4069
4070static int patch_tegra234_hdmi(struct hda_codec *codec)
4071{
4072 struct hdmi_spec *spec;
4073 int err;
4074
4075 err = alloc_generic_hdmi(codec);
4076 if (err < 0)
4077 return err;
4078
4079 codec->dp_mst = true;
4080 spec = codec->spec;
4081 spec->dyn_pin_out = true;
4082 spec->hdmi_intr_trig_ctrl = true;
4083
4084 return tegra_hdmi_init(codec);
4085}
4086
4087/*
4088 * ATI/AMD-specific implementations
4089 */
4090
4091#define is_amdhdmi_rev3_or_later(codec) \
4092 ((codec)->core.vendor_id == 0x1002aa01 && \
4093 ((codec)->core.revision_id & 0xff00) >= 0x0300)
4094#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
4095
4096/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
4097#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
4098#define ATI_VERB_SET_DOWNMIX_INFO 0x772
4099#define ATI_VERB_SET_MULTICHANNEL_01 0x777
4100#define ATI_VERB_SET_MULTICHANNEL_23 0x778
4101#define ATI_VERB_SET_MULTICHANNEL_45 0x779
4102#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
4103#define ATI_VERB_SET_HBR_CONTROL 0x77c
4104#define ATI_VERB_SET_MULTICHANNEL_1 0x785
4105#define ATI_VERB_SET_MULTICHANNEL_3 0x786
4106#define ATI_VERB_SET_MULTICHANNEL_5 0x787
4107#define ATI_VERB_SET_MULTICHANNEL_7 0x788
4108#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
4109#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
4110#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
4111#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
4112#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
4113#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
4114#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
4115#define ATI_VERB_GET_HBR_CONTROL 0xf7c
4116#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
4117#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
4118#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
4119#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
4120#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
4121
4122/* AMD specific HDA cvt verbs */
4123#define ATI_VERB_SET_RAMP_RATE 0x770
4124#define ATI_VERB_GET_RAMP_RATE 0xf70
4125
4126#define ATI_OUT_ENABLE 0x1
4127
4128#define ATI_MULTICHANNEL_MODE_PAIRED 0
4129#define ATI_MULTICHANNEL_MODE_SINGLE 1
4130
4131#define ATI_HBR_CAPABLE 0x01
4132#define ATI_HBR_ENABLE 0x10
4133
4134static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
4135 int dev_id, unsigned char *buf, int *eld_size)
4136{
4137 WARN_ON(dev_id != 0);
4138 /* call hda_eld.c ATI/AMD-specific function */
4139 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
4140 is_amdhdmi_rev3_or_later(codec));
4141}
4142
4143static void atihdmi_pin_setup_infoframe(struct hda_codec *codec,
4144 hda_nid_t pin_nid, int dev_id, int ca,
4145 int active_channels, int conn_type)
4146{
4147 WARN_ON(dev_id != 0);
4148 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
4149}
4150
4151static int atihdmi_paired_swap_fc_lfe(int pos)
4152{
4153 /*
4154 * ATI/AMD have automatic FC/LFE swap built-in
4155 * when in pairwise mapping mode.
4156 */
4157
4158 switch (pos) {
4159 /* see channel_allocations[].speakers[] */
4160 case 2: return 3;
4161 case 3: return 2;
4162 default: break;
4163 }
4164
4165 return pos;
4166}
4167
4168static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
4169 int ca, int chs, unsigned char *map)
4170{
4171 struct hdac_cea_channel_speaker_allocation *cap;
4172 int i, j;
4173
4174 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
4175
4176 cap = snd_hdac_get_ch_alloc_from_ca(ca);
4177 for (i = 0; i < chs; ++i) {
4178 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
4179 bool ok = false;
4180 bool companion_ok = false;
4181
4182 if (!mask)
4183 continue;
4184
4185 for (j = 0 + i % 2; j < 8; j += 2) {
4186 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
4187 if (cap->speakers[chan_idx] == mask) {
4188 /* channel is in a supported position */
4189 ok = true;
4190
4191 if (i % 2 == 0 && i + 1 < chs) {
4192 /* even channel, check the odd companion */
4193 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
4194 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
4195 int comp_mask_act = cap->speakers[comp_chan_idx];
4196
4197 if (comp_mask_req == comp_mask_act)
4198 companion_ok = true;
4199 else
4200 return -EINVAL;
4201 }
4202 break;
4203 }
4204 }
4205
4206 if (!ok)
4207 return -EINVAL;
4208
4209 if (companion_ok)
4210 i++; /* companion channel already checked */
4211 }
4212
4213 return 0;
4214}
4215
4216static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
4217 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
4218{
4219 struct hda_codec *codec = hdac_to_hda_codec(hdac);
4220 int verb;
4221 int ati_channel_setup = 0;
4222
4223 if (hdmi_slot > 7)
4224 return -EINVAL;
4225
4226 if (!has_amd_full_remap_support(codec)) {
4227 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
4228
4229 /* In case this is an odd slot but without stream channel, do not
4230 * disable the slot since the corresponding even slot could have a
4231 * channel. In case neither have a channel, the slot pair will be
4232 * disabled when this function is called for the even slot. */
4233 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
4234 return 0;
4235
4236 hdmi_slot -= hdmi_slot % 2;
4237
4238 if (stream_channel != 0xf)
4239 stream_channel -= stream_channel % 2;
4240 }
4241
4242 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
4243
4244 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
4245
4246 if (stream_channel != 0xf)
4247 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
4248
4249 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
4250}
4251
4252static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
4253 hda_nid_t pin_nid, int asp_slot)
4254{
4255 struct hda_codec *codec = hdac_to_hda_codec(hdac);
4256 bool was_odd = false;
4257 int ati_asp_slot = asp_slot;
4258 int verb;
4259 int ati_channel_setup;
4260
4261 if (asp_slot > 7)
4262 return -EINVAL;
4263
4264 if (!has_amd_full_remap_support(codec)) {
4265 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
4266 if (ati_asp_slot % 2 != 0) {
4267 ati_asp_slot -= 1;
4268 was_odd = true;
4269 }
4270 }
4271
4272 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
4273
4274 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
4275
4276 if (!(ati_channel_setup & ATI_OUT_ENABLE))
4277 return 0xf;
4278
4279 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
4280}
4281
4282static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
4283 struct hdac_chmap *chmap,
4284 struct hdac_cea_channel_speaker_allocation *cap,
4285 int channels)
4286{
4287 int c;
4288
4289 /*
4290 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
4291 * we need to take that into account (a single channel may take 2
4292 * channel slots if we need to carry a silent channel next to it).
4293 * On Rev3+ AMD codecs this function is not used.
4294 */
4295 int chanpairs = 0;
4296
4297 /* We only produce even-numbered channel count TLVs */
4298 if ((channels % 2) != 0)
4299 return -1;
4300
4301 for (c = 0; c < 7; c += 2) {
4302 if (cap->speakers[c] || cap->speakers[c+1])
4303 chanpairs++;
4304 }
4305
4306 if (chanpairs * 2 != channels)
4307 return -1;
4308
4309 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
4310}
4311
4312static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
4313 struct hdac_cea_channel_speaker_allocation *cap,
4314 unsigned int *chmap, int channels)
4315{
4316 /* produce paired maps for pre-rev3 ATI/AMD codecs */
4317 int count = 0;
4318 int c;
4319
4320 for (c = 7; c >= 0; c--) {
4321 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
4322 int spk = cap->speakers[chan];
4323 if (!spk) {
4324 /* add N/A channel if the companion channel is occupied */
4325 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
4326 chmap[count++] = SNDRV_CHMAP_NA;
4327
4328 continue;
4329 }
4330
4331 chmap[count++] = snd_hdac_spk_to_chmap(spk);
4332 }
4333
4334 WARN_ON(count != channels);
4335}
4336
4337static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
4338 int dev_id, bool hbr)
4339{
4340 int hbr_ctl, hbr_ctl_new;
4341
4342 WARN_ON(dev_id != 0);
4343
4344 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
4345 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
4346 if (hbr)
4347 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
4348 else
4349 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
4350
4351 codec_dbg(codec,
4352 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
4353 pin_nid,
4354 hbr_ctl == hbr_ctl_new ? "" : "new-",
4355 hbr_ctl_new);
4356
4357 if (hbr_ctl != hbr_ctl_new)
4358 snd_hda_codec_write(codec, pin_nid, 0,
4359 ATI_VERB_SET_HBR_CONTROL,
4360 hbr_ctl_new);
4361
4362 } else if (hbr)
4363 return -EINVAL;
4364
4365 return 0;
4366}
4367
4368static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
4369 hda_nid_t pin_nid, int dev_id,
4370 u32 stream_tag, int format)
4371{
4372 if (is_amdhdmi_rev3_or_later(codec)) {
4373 int ramp_rate = 180; /* default as per AMD spec */
4374 /* disable ramp-up/down for non-pcm as per AMD spec */
4375 if (format & AC_FMT_TYPE_NON_PCM)
4376 ramp_rate = 0;
4377
4378 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
4379 }
4380
4381 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
4382 stream_tag, format);
4383}
4384
4385
4386static int atihdmi_init(struct hda_codec *codec)
4387{
4388 struct hdmi_spec *spec = codec->spec;
4389 int pin_idx, err;
4390
4391 err = generic_hdmi_init(codec);
4392
4393 if (err)
4394 return err;
4395
4396 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
4397 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
4398
4399 /* make sure downmix information in infoframe is zero */
4400 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
4401
4402 /* enable channel-wise remap mode if supported */
4403 if (has_amd_full_remap_support(codec))
4404 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
4405 ATI_VERB_SET_MULTICHANNEL_MODE,
4406 ATI_MULTICHANNEL_MODE_SINGLE);
4407 }
4408 codec->auto_runtime_pm = 1;
4409
4410 return 0;
4411}
4412
4413/* map from pin NID to port; port is 0-based */
4414/* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
4415static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
4416{
4417 return pin_nid / 2 - 1;
4418}
4419
4420/* reverse-map from port to pin NID: see above */
4421static int atihdmi_port2pin(struct hda_codec *codec, int port)
4422{
4423 return port * 2 + 3;
4424}
4425
4426static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
4427 .pin2port = atihdmi_pin2port,
4428 .pin_eld_notify = generic_acomp_pin_eld_notify,
4429 .master_bind = generic_acomp_master_bind,
4430 .master_unbind = generic_acomp_master_unbind,
4431};
4432
4433static int patch_atihdmi(struct hda_codec *codec)
4434{
4435 struct hdmi_spec *spec;
4436 struct hdmi_spec_per_cvt *per_cvt;
4437 int err, cvt_idx;
4438
4439 err = patch_generic_hdmi(codec);
4440
4441 if (err)
4442 return err;
4443
4444 codec->patch_ops.init = atihdmi_init;
4445
4446 spec = codec->spec;
4447
4448 spec->static_pcm_mapping = true;
4449
4450 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
4451 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
4452 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
4453 spec->ops.setup_stream = atihdmi_setup_stream;
4454
4455 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4456 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4457
4458 if (!has_amd_full_remap_support(codec)) {
4459 /* override to ATI/AMD-specific versions with pairwise mapping */
4460 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4461 atihdmi_paired_chmap_cea_alloc_validate_get_type;
4462 spec->chmap.ops.cea_alloc_to_tlv_chmap =
4463 atihdmi_paired_cea_alloc_to_tlv_chmap;
4464 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
4465 }
4466
4467 /* ATI/AMD converters do not advertise all of their capabilities */
4468 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4469 per_cvt = get_cvt(spec, cvt_idx);
4470 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4471 per_cvt->rates |= SUPPORTED_RATES;
4472 per_cvt->formats |= SUPPORTED_FORMATS;
4473 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4474 }
4475
4476 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
4477
4478 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
4479 * the link-down as is. Tell the core to allow it.
4480 */
4481 codec->link_down_at_suspend = 1;
4482
4483 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
4484
4485 return 0;
4486}
4487
4488/* VIA HDMI Implementation */
4489#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
4490#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
4491
4492static int patch_via_hdmi(struct hda_codec *codec)
4493{
4494 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
4495}
4496
4497static int patch_gf_hdmi(struct hda_codec *codec)
4498{
4499 int err;
4500
4501 err = patch_generic_hdmi(codec);
4502 if (err)
4503 return err;
4504
4505 /*
4506 * Glenfly GPUs have two codecs, stream switches from one codec to
4507 * another, need to do actual clean-ups in codec_cleanup_stream
4508 */
4509 codec->no_sticky_stream = 1;
4510 return 0;
4511}
4512
4513/*
4514 * patch entries
4515 */
4516static const struct hda_device_id snd_hda_id_hdmi[] = {
4517HDA_CODEC_ENTRY(0x00147a47, "Loongson HDMI", patch_generic_hdmi),
4518HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
4519HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
4520HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
4521HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
4522HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
4523HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
4524HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
4525HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
4526HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4527HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4528HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
4529HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4530HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4531HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
4532HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy),
4533HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy),
4534HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy),
4535HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy),
4536HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy),
4537HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy),
4538HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy),
4539HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy),
4540HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy),
4541HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy),
4542HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy),
4543HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy),
4544HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy),
4545/* 17 is known to be absent */
4546HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy),
4547HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy),
4548HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy),
4549HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy),
4550HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy),
4551HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
4552HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
4553HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
4554HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
4555HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
4556HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
4557HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
4558HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
4559HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi),
4560HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
4561HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
4562HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
4563HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
4564HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
4565HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
4566HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
4567HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
4568HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
4569HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
4570HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
4571HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
4572HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
4573HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
4574HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
4575HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
4576HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
4577HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
4578HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
4579HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
4580HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
4581HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
4582HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
4583HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
4584HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
4585HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
4586HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
4587HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
4588HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
4589HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
4590HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
4591HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
4592HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
4593HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
4594HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
4595HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
4596HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
4597HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi),
4598HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi),
4599HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi),
4600HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi),
4601HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi),
4602HDA_CODEC_ENTRY(0x10de00a3, "GPU a3 HDMI/DP", patch_nvhdmi),
4603HDA_CODEC_ENTRY(0x10de00a4, "GPU a4 HDMI/DP", patch_nvhdmi),
4604HDA_CODEC_ENTRY(0x10de00a5, "GPU a5 HDMI/DP", patch_nvhdmi),
4605HDA_CODEC_ENTRY(0x10de00a6, "GPU a6 HDMI/DP", patch_nvhdmi),
4606HDA_CODEC_ENTRY(0x10de00a7, "GPU a7 HDMI/DP", patch_nvhdmi),
4607HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
4608HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
4609HDA_CODEC_ENTRY(0x67663d82, "Arise 82 HDMI/DP", patch_gf_hdmi),
4610HDA_CODEC_ENTRY(0x67663d83, "Arise 83 HDMI/DP", patch_gf_hdmi),
4611HDA_CODEC_ENTRY(0x67663d84, "Arise 84 HDMI/DP", patch_gf_hdmi),
4612HDA_CODEC_ENTRY(0x67663d85, "Arise 85 HDMI/DP", patch_gf_hdmi),
4613HDA_CODEC_ENTRY(0x67663d86, "Arise 86 HDMI/DP", patch_gf_hdmi),
4614HDA_CODEC_ENTRY(0x67663d87, "Arise 87 HDMI/DP", patch_gf_hdmi),
4615HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
4616HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
4617HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
4618HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
4619HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4620HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
4621HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
4622HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
4623HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
4624HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4625HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
4626HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
4627HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
4628HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
4629HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
4630HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
4631HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
4632HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
4633HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
4634HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
4635HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi),
4636HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi),
4637HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi),
4638HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi),
4639HDA_CODEC_ENTRY(0x80862818, "Raptorlake HDMI", patch_i915_tgl_hdmi),
4640HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_tgl_hdmi),
4641HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi),
4642HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi),
4643HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_adlp_hdmi),
4644HDA_CODEC_ENTRY(0x8086281d, "Meteor Lake HDMI", patch_i915_adlp_hdmi),
4645HDA_CODEC_ENTRY(0x8086281f, "Raptor Lake P HDMI", patch_i915_adlp_hdmi),
4646HDA_CODEC_ENTRY(0x80862820, "Lunar Lake HDMI", patch_i915_adlp_hdmi),
4647HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
4648HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
4649HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
4650HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
4651/* special ID for generic HDMI */
4652HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
4653{} /* terminator */
4654};
4655MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
4656
4657MODULE_LICENSE("GPL");
4658MODULE_DESCRIPTION("HDMI HD-audio codec");
4659MODULE_ALIAS("snd-hda-codec-intelhdmi");
4660MODULE_ALIAS("snd-hda-codec-nvhdmi");
4661MODULE_ALIAS("snd-hda-codec-atihdmi");
4662
4663static struct hda_codec_driver hdmi_driver = {
4664 .id = snd_hda_id_hdmi,
4665};
4666
4667module_hda_codec_driver(hdmi_driver);