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1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
25
26#include <linux/delay.h>
27#include <linux/i2c.h>
28
29#include <drm/display/drm_dp.h>
30#include <drm/drm_connector.h>
31
32struct drm_device;
33struct drm_dp_aux;
34struct drm_panel;
35
36bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
37 int lane_count);
38bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
39 int lane_count);
40u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
41 int lane);
42u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
43 int lane);
44u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
45 int lane);
46
47int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
48 enum drm_dp_phy dp_phy, bool uhbr);
49int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
50 enum drm_dp_phy dp_phy, bool uhbr);
51
52void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
53 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
54void drm_dp_lttpr_link_train_clock_recovery_delay(void);
55void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
57void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
58 const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
59
60int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux);
61bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
62 int lane_count);
63bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
64 int lane_count);
65bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
66bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
67bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]);
68
69u8 drm_dp_link_rate_to_bw_code(int link_rate);
70int drm_dp_bw_code_to_link_rate(u8 link_bw);
71
72const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
73
74/**
75 * struct drm_dp_vsc_sdp - drm DP VSC SDP
76 *
77 * This structure represents a DP VSC SDP of drm
78 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
79 * [Table 2-117: VSC SDP Payload for DB16 through DB18]
80 *
81 * @sdp_type: secondary-data packet type
82 * @revision: revision number
83 * @length: number of valid data bytes
84 * @pixelformat: pixel encoding format
85 * @colorimetry: colorimetry format
86 * @bpc: bit per color
87 * @dynamic_range: dynamic range information
88 * @content_type: CTA-861-G defines content types and expected processing by a sink device
89 */
90struct drm_dp_vsc_sdp {
91 unsigned char sdp_type;
92 unsigned char revision;
93 unsigned char length;
94 enum dp_pixelformat pixelformat;
95 enum dp_colorimetry colorimetry;
96 int bpc;
97 enum dp_dynamic_range dynamic_range;
98 enum dp_content_type content_type;
99};
100
101void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
102 const struct drm_dp_vsc_sdp *vsc);
103
104int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
105
106static inline int
107drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
108{
109 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
110}
111
112static inline u8
113drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
114{
115 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
116}
117
118static inline bool
119drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
120{
121 return dpcd[DP_DPCD_REV] >= 0x11 &&
122 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
123}
124
125static inline bool
126drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
127{
128 return dpcd[DP_DPCD_REV] >= 0x11 &&
129 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
130}
131
132static inline bool
133drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
134{
135 return dpcd[DP_DPCD_REV] >= 0x12 &&
136 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
137}
138
139static inline bool
140drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
141{
142 return dpcd[DP_DPCD_REV] >= 0x11 ||
143 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5;
144}
145
146static inline bool
147drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
148{
149 return dpcd[DP_DPCD_REV] >= 0x14 &&
150 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
151}
152
153static inline u8
154drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
155{
156 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
157 DP_TRAINING_PATTERN_MASK;
158}
159
160static inline bool
161drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
162{
163 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
164}
165
166/* DP/eDP DSC support */
167u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
168u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
169 bool is_edp);
170u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
171int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
172 u8 dsc_bpc[3]);
173
174static inline bool
175drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
176{
177 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
178 DP_DSC_DECOMPRESSION_IS_SUPPORTED;
179}
180
181static inline u16
182drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
183{
184 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
185 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
186 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK) << 8);
187}
188
189static inline u32
190drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
191{
192 /* Max Slicewidth = Number of Pixels * 320 */
193 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
194 DP_DSC_SLICE_WIDTH_MULTIPLIER;
195}
196
197/**
198 * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format
199 * @dsc_dpcd : DSC-capability DPCDs of the sink
200 * @output_format: output_format which is to be checked
201 *
202 * Returns true if the sink supports DSC with the given output_format, false otherwise.
203 */
204static inline bool
205drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format)
206{
207 return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format;
208}
209
210/* Forward Error Correction Support on DP 1.4 */
211static inline bool
212drm_dp_sink_supports_fec(const u8 fec_capable)
213{
214 return fec_capable & DP_FEC_CAPABLE;
215}
216
217static inline bool
218drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
219{
220 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
221}
222
223static inline bool
224drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
225{
226 return dpcd[DP_EDP_CONFIGURATION_CAP] &
227 DP_ALTERNATE_SCRAMBLER_RESET_CAP;
228}
229
230/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
231static inline bool
232drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
233{
234 return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
235 DP_MSA_TIMING_PAR_IGNORED;
236}
237
238/**
239 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
240 * @edp_dpcd: The DPCD to check
241 *
242 * Note that currently this function will return %false for panels which support various DPCD
243 * backlight features but which require the brightness be set through PWM, and don't support setting
244 * the brightness level via the DPCD.
245 *
246 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
247 * otherwise
248 */
249static inline bool
250drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
251{
252 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP);
253}
254
255/**
256 * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR
257 * @link_rate: link rate in 10kbits/s units
258 *
259 * Determine if the provided link rate is an UHBR rate.
260 *
261 * Returns: %True if @link_rate is an UHBR rate.
262 */
263static inline bool drm_dp_is_uhbr_rate(int link_rate)
264{
265 return link_rate >= 1000000;
266}
267
268/*
269 * DisplayPort AUX channel
270 */
271
272/**
273 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
274 * @address: address of the (first) register to access
275 * @request: contains the type of transaction (see DP_AUX_* macros)
276 * @reply: upon completion, contains the reply type of the transaction
277 * @buffer: pointer to a transmission or reception buffer
278 * @size: size of @buffer
279 */
280struct drm_dp_aux_msg {
281 unsigned int address;
282 u8 request;
283 u8 reply;
284 void *buffer;
285 size_t size;
286};
287
288struct cec_adapter;
289struct drm_connector;
290struct drm_edid;
291
292/**
293 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
294 * @lock: mutex protecting this struct
295 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
296 * @connector: the connector this CEC adapter is associated with
297 * @unregister_work: unregister the CEC adapter
298 */
299struct drm_dp_aux_cec {
300 struct mutex lock;
301 struct cec_adapter *adap;
302 struct drm_connector *connector;
303 struct delayed_work unregister_work;
304};
305
306/**
307 * struct drm_dp_aux - DisplayPort AUX channel
308 *
309 * An AUX channel can also be used to transport I2C messages to a sink. A
310 * typical application of that is to access an EDID that's present in the sink
311 * device. The @transfer() function can also be used to execute such
312 * transactions. The drm_dp_aux_register() function registers an I2C adapter
313 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call
314 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long
315 * transfers by default; if a partial response is received, the adapter will
316 * drop down to the size given by the partial response for this transaction
317 * only.
318 */
319struct drm_dp_aux {
320 /**
321 * @name: user-visible name of this AUX channel and the
322 * I2C-over-AUX adapter.
323 *
324 * It's also used to specify the name of the I2C adapter. If set
325 * to %NULL, dev_name() of @dev will be used.
326 */
327 const char *name;
328
329 /**
330 * @ddc: I2C adapter that can be used for I2C-over-AUX
331 * communication
332 */
333 struct i2c_adapter ddc;
334
335 /**
336 * @dev: pointer to struct device that is the parent for this
337 * AUX channel.
338 */
339 struct device *dev;
340
341 /**
342 * @drm_dev: pointer to the &drm_device that owns this AUX channel.
343 * Beware, this may be %NULL before drm_dp_aux_register() has been
344 * called.
345 *
346 * It should be set to the &drm_device that will be using this AUX
347 * channel as early as possible. For many graphics drivers this should
348 * happen before drm_dp_aux_init(), however it's perfectly fine to set
349 * this field later so long as it's assigned before calling
350 * drm_dp_aux_register().
351 */
352 struct drm_device *drm_dev;
353
354 /**
355 * @crtc: backpointer to the crtc that is currently using this
356 * AUX channel
357 */
358 struct drm_crtc *crtc;
359
360 /**
361 * @hw_mutex: internal mutex used for locking transfers.
362 *
363 * Note that if the underlying hardware is shared among multiple
364 * channels, the driver needs to do additional locking to
365 * prevent concurrent access.
366 */
367 struct mutex hw_mutex;
368
369 /**
370 * @crc_work: worker that captures CRCs for each frame
371 */
372 struct work_struct crc_work;
373
374 /**
375 * @crc_count: counter of captured frame CRCs
376 */
377 u8 crc_count;
378
379 /**
380 * @transfer: transfers a message representing a single AUX
381 * transaction.
382 *
383 * This is a hardware-specific implementation of how
384 * transactions are executed that the drivers must provide.
385 *
386 * A pointer to a &drm_dp_aux_msg structure describing the
387 * transaction is passed into this function. Upon success, the
388 * implementation should return the number of payload bytes that
389 * were transferred, or a negative error-code on failure.
390 *
391 * Helpers will propagate these errors, with the exception of
392 * the %-EBUSY error, which causes a transaction to be retried.
393 * On a short, helpers will return %-EPROTO to make it simpler
394 * to check for failure.
395 *
396 * The @transfer() function must only modify the reply field of
397 * the &drm_dp_aux_msg structure. The retry logic and i2c
398 * helpers assume this is the case.
399 *
400 * Also note that this callback can be called no matter the
401 * state @dev is in and also no matter what state the panel is
402 * in. It's expected:
403 *
404 * - If the @dev providing the AUX bus is currently unpowered then
405 * it will power itself up for the transfer.
406 *
407 * - If we're on eDP (using a drm_panel) and the panel is not in a
408 * state where it can respond (it's not powered or it's in a
409 * low power state) then this function may return an error, but
410 * not crash. It's up to the caller of this code to make sure that
411 * the panel is powered on if getting an error back is not OK. If a
412 * drm_panel driver is initiating a DP AUX transfer it may power
413 * itself up however it wants. All other code should ensure that
414 * the pre_enable() bridge chain (which eventually calls the
415 * drm_panel prepare function) has powered the panel.
416 */
417 ssize_t (*transfer)(struct drm_dp_aux *aux,
418 struct drm_dp_aux_msg *msg);
419
420 /**
421 * @wait_hpd_asserted: wait for HPD to be asserted
422 *
423 * This is mainly useful for eDP panels drivers to wait for an eDP
424 * panel to finish powering on. This is an optional function.
425 *
426 * This function will efficiently wait for the HPD signal to be
427 * asserted. The `wait_us` parameter that is passed in says that we
428 * know that the HPD signal is expected to be asserted within `wait_us`
429 * microseconds. This function could wait for longer than `wait_us` if
430 * the logic in the DP controller has a long debouncing time. The
431 * important thing is that if this function returns success that the
432 * DP controller is ready to send AUX transactions.
433 *
434 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time
435 * expired and HPD wasn't asserted. This function should not print
436 * timeout errors to the log.
437 *
438 * The semantics of this function are designed to match the
439 * readx_poll_timeout() function. That means a `wait_us` of 0 means
440 * to wait forever. Like readx_poll_timeout(), this function may sleep.
441 *
442 * NOTE: this function specifically reports the state of the HPD pin
443 * that's associated with the DP AUX channel. This is different from
444 * the HPD concept in much of the rest of DRM which is more about
445 * physical presence of a display. For eDP, for instance, a display is
446 * assumed always present even if the HPD pin is deasserted.
447 */
448 int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us);
449
450 /**
451 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
452 */
453 unsigned i2c_nack_count;
454 /**
455 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
456 */
457 unsigned i2c_defer_count;
458 /**
459 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
460 */
461 struct drm_dp_aux_cec cec;
462 /**
463 * @is_remote: Is this AUX CH actually using sideband messaging.
464 */
465 bool is_remote;
466};
467
468int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset);
469ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
470 void *buffer, size_t size);
471ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
472 void *buffer, size_t size);
473
474/**
475 * drm_dp_dpcd_readb() - read a single byte from the DPCD
476 * @aux: DisplayPort AUX channel
477 * @offset: address of the register to read
478 * @valuep: location where the value of the register will be stored
479 *
480 * Returns the number of bytes transferred (1) on success, or a negative
481 * error code on failure.
482 */
483static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
484 unsigned int offset, u8 *valuep)
485{
486 return drm_dp_dpcd_read(aux, offset, valuep, 1);
487}
488
489/**
490 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
491 * @aux: DisplayPort AUX channel
492 * @offset: address of the register to write
493 * @value: value to write to the register
494 *
495 * Returns the number of bytes transferred (1) on success, or a negative
496 * error code on failure.
497 */
498static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
499 unsigned int offset, u8 value)
500{
501 return drm_dp_dpcd_write(aux, offset, &value, 1);
502}
503
504int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
505 u8 dpcd[DP_RECEIVER_CAP_SIZE]);
506
507int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
508 u8 status[DP_LINK_STATUS_SIZE]);
509
510int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
511 enum drm_dp_phy dp_phy,
512 u8 link_status[DP_LINK_STATUS_SIZE]);
513
514bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
515 u8 real_edid_checksum);
516
517int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
518 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
519 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
520bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
521 const u8 port_cap[4], u8 type);
522bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
523 const u8 port_cap[4],
524 const struct drm_edid *drm_edid);
525int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
526 const u8 port_cap[4]);
527int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
528 const u8 port_cap[4],
529 const struct drm_edid *drm_edid);
530int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
531 const u8 port_cap[4],
532 const struct drm_edid *drm_edid);
533int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
534 const u8 port_cap[4],
535 const struct drm_edid *drm_edid);
536bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
537 const u8 port_cap[4]);
538bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
539 const u8 port_cap[4]);
540struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
541 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
542 const u8 port_cap[4]);
543int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
544void drm_dp_downstream_debug(struct seq_file *m,
545 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
546 const u8 port_cap[4],
547 const struct drm_edid *drm_edid,
548 struct drm_dp_aux *aux);
549enum drm_mode_subconnector
550drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
551 const u8 port_cap[4]);
552void drm_dp_set_subconnector_property(struct drm_connector *connector,
553 enum drm_connector_status status,
554 const u8 *dpcd,
555 const u8 port_cap[4]);
556
557struct drm_dp_desc;
558bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
559 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
560 const struct drm_dp_desc *desc);
561int drm_dp_read_sink_count(struct drm_dp_aux *aux);
562
563int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
564 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
565 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
566int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
567 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
568 enum drm_dp_phy dp_phy,
569 u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
570int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
571int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
572int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
573bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
574bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
575
576void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
577void drm_dp_aux_init(struct drm_dp_aux *aux);
578int drm_dp_aux_register(struct drm_dp_aux *aux);
579void drm_dp_aux_unregister(struct drm_dp_aux *aux);
580
581int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
582int drm_dp_stop_crc(struct drm_dp_aux *aux);
583
584struct drm_dp_dpcd_ident {
585 u8 oui[3];
586 u8 device_id[6];
587 u8 hw_rev;
588 u8 sw_major_rev;
589 u8 sw_minor_rev;
590} __packed;
591
592/**
593 * struct drm_dp_desc - DP branch/sink device descriptor
594 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
595 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
596 */
597struct drm_dp_desc {
598 struct drm_dp_dpcd_ident ident;
599 u32 quirks;
600};
601
602int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
603 bool is_branch);
604
605/**
606 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
607 *
608 * Display Port sink and branch devices in the wild have a variety of bugs, try
609 * to collect them here. The quirks are shared, but it's up to the drivers to
610 * implement workarounds for them.
611 */
612enum drm_dp_quirk {
613 /**
614 * @DP_DPCD_QUIRK_CONSTANT_N:
615 *
616 * The device requires main link attributes Mvid and Nvid to be limited
617 * to 16 bits. So will give a constant value (0x8000) for compatability.
618 */
619 DP_DPCD_QUIRK_CONSTANT_N,
620 /**
621 * @DP_DPCD_QUIRK_NO_PSR:
622 *
623 * The device does not support PSR even if reports that it supports or
624 * driver still need to implement proper handling for such device.
625 */
626 DP_DPCD_QUIRK_NO_PSR,
627 /**
628 * @DP_DPCD_QUIRK_NO_SINK_COUNT:
629 *
630 * The device does not set SINK_COUNT to a non-zero value.
631 * The driver should ignore SINK_COUNT during detection. Note that
632 * drm_dp_read_sink_count_cap() automatically checks for this quirk.
633 */
634 DP_DPCD_QUIRK_NO_SINK_COUNT,
635 /**
636 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
637 *
638 * The device supports MST DSC despite not supporting Virtual DPCD.
639 * The DSC caps can be read from the physical aux instead.
640 */
641 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
642 /**
643 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS:
644 *
645 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
646 * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
647 */
648 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
649 /**
650 * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC:
651 *
652 * The device applies HBLANK expansion for some modes, but this
653 * requires enabling DSC.
654 */
655 DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC,
656};
657
658/**
659 * drm_dp_has_quirk() - does the DP device have a specific quirk
660 * @desc: Device descriptor filled by drm_dp_read_desc()
661 * @quirk: Quirk to query for
662 *
663 * Return true if DP device identified by @desc has @quirk.
664 */
665static inline bool
666drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
667{
668 return desc->quirks & BIT(quirk);
669}
670
671/**
672 * struct drm_edp_backlight_info - Probed eDP backlight info struct
673 * @pwmgen_bit_count: The pwmgen bit count
674 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
675 * @max: The maximum backlight level that may be set
676 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
677 * @aux_enable: Does the panel support the AUX enable cap?
678 * @aux_set: Does the panel support setting the brightness through AUX?
679 *
680 * This structure contains various data about an eDP backlight, which can be populated by using
681 * drm_edp_backlight_init().
682 */
683struct drm_edp_backlight_info {
684 u8 pwmgen_bit_count;
685 u8 pwm_freq_pre_divider;
686 u16 max;
687
688 bool lsb_reg_used : 1;
689 bool aux_enable : 1;
690 bool aux_set : 1;
691};
692
693int
694drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
695 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
696 u16 *current_level, u8 *current_mode);
697int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
698 u16 level);
699int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
700 u16 level);
701int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
702
703#if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
704 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)))
705
706int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux);
707
708#else
709
710static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel,
711 struct drm_dp_aux *aux)
712{
713 return 0;
714}
715
716#endif
717
718#ifdef CONFIG_DRM_DP_CEC
719void drm_dp_cec_irq(struct drm_dp_aux *aux);
720void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
721 struct drm_connector *connector);
722void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
723void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address);
724void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
725void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
726#else
727static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
728{
729}
730
731static inline void
732drm_dp_cec_register_connector(struct drm_dp_aux *aux,
733 struct drm_connector *connector)
734{
735}
736
737static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
738{
739}
740
741static inline void drm_dp_cec_attach(struct drm_dp_aux *aux,
742 u16 source_physical_address)
743{
744}
745
746static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
747 const struct edid *edid)
748{
749}
750
751static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
752{
753}
754
755#endif
756
757/**
758 * struct drm_dp_phy_test_params - DP Phy Compliance parameters
759 * @link_rate: Requested Link rate from DPCD 0x219
760 * @num_lanes: Number of lanes requested by sing through DPCD 0x220
761 * @phy_pattern: DP Phy test pattern from DPCD 0x248
762 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
763 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
764 * @enhanced_frame_cap: flag for enhanced frame capability.
765 */
766struct drm_dp_phy_test_params {
767 int link_rate;
768 u8 num_lanes;
769 u8 phy_pattern;
770 u8 hbr2_reset[2];
771 u8 custom80[10];
772 bool enhanced_frame_cap;
773};
774
775int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
776 struct drm_dp_phy_test_params *data);
777int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
778 struct drm_dp_phy_test_params *data, u8 dp_rev);
779int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
780 const u8 port_cap[4]);
781int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
782bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
783int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
784 u8 frl_mode);
785int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
786 u8 frl_type);
787int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
788int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
789
790bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
791int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
792void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
793 struct drm_connector *connector);
794bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
795int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
796int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
797int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
798int drm_dp_pcon_pps_default(struct drm_dp_aux *aux);
799int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);
800int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]);
801bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
802 const u8 port_cap[4], u8 color_spc);
803int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
804
805#define DRM_DP_BW_OVERHEAD_MST BIT(0)
806#define DRM_DP_BW_OVERHEAD_UHBR BIT(1)
807#define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2)
808#define DRM_DP_BW_OVERHEAD_FEC BIT(3)
809#define DRM_DP_BW_OVERHEAD_DSC BIT(4)
810
811int drm_dp_bw_overhead(int lane_count, int hactive,
812 int dsc_slice_count,
813 int bpp_x16, unsigned long flags);
814int drm_dp_bw_channel_coding_efficiency(bool is_uhbr);
815
816#endif /* _DRM_DP_HELPER_H_ */