Loading...
Note: File does not exist in v6.8.
1/*
2 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
3 *
4 * Copyright (C) 2005-2007 AMD (http://www.amd.com)
5 * Author: Thomas Dahlmann
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22/*
23 * The AMD5536 UDC is part of the x86 southbridge AMD Geode CS5536.
24 * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
25 * provides 4 IN and 4 OUT endpoints (bulk or interrupt type).
26 *
27 * Make sure that UDC is assigned to port 4 by BIOS settings (port can also
28 * be used as host port) and UOC bits PAD_EN and APU are set (should be done
29 * by BIOS init).
30 *
31 * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
32 * work without updating NET_IP_ALIGN. Or PIO mode (module param "use_dma=0")
33 * can be used with gadget ether.
34 */
35
36/* debug control */
37/* #define UDC_VERBOSE */
38
39/* Driver strings */
40#define UDC_MOD_DESCRIPTION "AMD 5536 UDC - USB Device Controller"
41#define UDC_DRIVER_VERSION_STRING "01.00.0206 - $Revision: #3 $"
42
43/* system */
44#include <linux/module.h>
45#include <linux/pci.h>
46#include <linux/kernel.h>
47#include <linux/delay.h>
48#include <linux/ioport.h>
49#include <linux/sched.h>
50#include <linux/slab.h>
51#include <linux/errno.h>
52#include <linux/init.h>
53#include <linux/timer.h>
54#include <linux/list.h>
55#include <linux/interrupt.h>
56#include <linux/ioctl.h>
57#include <linux/fs.h>
58#include <linux/dmapool.h>
59#include <linux/moduleparam.h>
60#include <linux/device.h>
61#include <linux/io.h>
62#include <linux/irq.h>
63#include <linux/prefetch.h>
64
65#include <asm/byteorder.h>
66#include <asm/system.h>
67#include <asm/unaligned.h>
68
69/* gadget stack */
70#include <linux/usb/ch9.h>
71#include <linux/usb/gadget.h>
72
73/* udc specific */
74#include "amd5536udc.h"
75
76
77static void udc_tasklet_disconnect(unsigned long);
78static void empty_req_queue(struct udc_ep *);
79static int udc_probe(struct udc *dev);
80static void udc_basic_init(struct udc *dev);
81static void udc_setup_endpoints(struct udc *dev);
82static void udc_soft_reset(struct udc *dev);
83static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep);
84static void udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq);
85static int udc_free_dma_chain(struct udc *dev, struct udc_request *req);
86static int udc_create_dma_chain(struct udc_ep *ep, struct udc_request *req,
87 unsigned long buf_len, gfp_t gfp_flags);
88static int udc_remote_wakeup(struct udc *dev);
89static int udc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
90static void udc_pci_remove(struct pci_dev *pdev);
91
92/* description */
93static const char mod_desc[] = UDC_MOD_DESCRIPTION;
94static const char name[] = "amd5536udc";
95
96/* structure to hold endpoint function pointers */
97static const struct usb_ep_ops udc_ep_ops;
98
99/* received setup data */
100static union udc_setup_data setup_data;
101
102/* pointer to device object */
103static struct udc *udc;
104
105/* irq spin lock for soft reset */
106static DEFINE_SPINLOCK(udc_irq_spinlock);
107/* stall spin lock */
108static DEFINE_SPINLOCK(udc_stall_spinlock);
109
110/*
111* slave mode: pending bytes in rx fifo after nyet,
112* used if EPIN irq came but no req was available
113*/
114static unsigned int udc_rxfifo_pending;
115
116/* count soft resets after suspend to avoid loop */
117static int soft_reset_occured;
118static int soft_reset_after_usbreset_occured;
119
120/* timer */
121static struct timer_list udc_timer;
122static int stop_timer;
123
124/* set_rde -- Is used to control enabling of RX DMA. Problem is
125 * that UDC has only one bit (RDE) to enable/disable RX DMA for
126 * all OUT endpoints. So we have to handle race conditions like
127 * when OUT data reaches the fifo but no request was queued yet.
128 * This cannot be solved by letting the RX DMA disabled until a
129 * request gets queued because there may be other OUT packets
130 * in the FIFO (important for not blocking control traffic).
131 * The value of set_rde controls the correspondig timer.
132 *
133 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
134 * set_rde 0 == do not touch RDE, do no start the RDE timer
135 * set_rde 1 == timer function will look whether FIFO has data
136 * set_rde 2 == set by timer function to enable RX DMA on next call
137 */
138static int set_rde = -1;
139
140static DECLARE_COMPLETION(on_exit);
141static struct timer_list udc_pollstall_timer;
142static int stop_pollstall_timer;
143static DECLARE_COMPLETION(on_pollstall_exit);
144
145/* tasklet for usb disconnect */
146static DECLARE_TASKLET(disconnect_tasklet, udc_tasklet_disconnect,
147 (unsigned long) &udc);
148
149
150/* endpoint names used for print */
151static const char ep0_string[] = "ep0in";
152static const char *ep_string[] = {
153 ep0_string,
154 "ep1in-int", "ep2in-bulk", "ep3in-bulk", "ep4in-bulk", "ep5in-bulk",
155 "ep6in-bulk", "ep7in-bulk", "ep8in-bulk", "ep9in-bulk", "ep10in-bulk",
156 "ep11in-bulk", "ep12in-bulk", "ep13in-bulk", "ep14in-bulk",
157 "ep15in-bulk", "ep0out", "ep1out-bulk", "ep2out-bulk", "ep3out-bulk",
158 "ep4out-bulk", "ep5out-bulk", "ep6out-bulk", "ep7out-bulk",
159 "ep8out-bulk", "ep9out-bulk", "ep10out-bulk", "ep11out-bulk",
160 "ep12out-bulk", "ep13out-bulk", "ep14out-bulk", "ep15out-bulk"
161};
162
163/* DMA usage flag */
164static int use_dma = 1;
165/* packet per buffer dma */
166static int use_dma_ppb = 1;
167/* with per descr. update */
168static int use_dma_ppb_du;
169/* buffer fill mode */
170static int use_dma_bufferfill_mode;
171/* full speed only mode */
172static int use_fullspeed;
173/* tx buffer size for high speed */
174static unsigned long hs_tx_buf = UDC_EPIN_BUFF_SIZE;
175
176/* module parameters */
177module_param(use_dma, bool, S_IRUGO);
178MODULE_PARM_DESC(use_dma, "true for DMA");
179module_param(use_dma_ppb, bool, S_IRUGO);
180MODULE_PARM_DESC(use_dma_ppb, "true for DMA in packet per buffer mode");
181module_param(use_dma_ppb_du, bool, S_IRUGO);
182MODULE_PARM_DESC(use_dma_ppb_du,
183 "true for DMA in packet per buffer mode with descriptor update");
184module_param(use_fullspeed, bool, S_IRUGO);
185MODULE_PARM_DESC(use_fullspeed, "true for fullspeed only");
186
187/*---------------------------------------------------------------------------*/
188/* Prints UDC device registers and endpoint irq registers */
189static void print_regs(struct udc *dev)
190{
191 DBG(dev, "------- Device registers -------\n");
192 DBG(dev, "dev config = %08x\n", readl(&dev->regs->cfg));
193 DBG(dev, "dev control = %08x\n", readl(&dev->regs->ctl));
194 DBG(dev, "dev status = %08x\n", readl(&dev->regs->sts));
195 DBG(dev, "\n");
196 DBG(dev, "dev int's = %08x\n", readl(&dev->regs->irqsts));
197 DBG(dev, "dev intmask = %08x\n", readl(&dev->regs->irqmsk));
198 DBG(dev, "\n");
199 DBG(dev, "dev ep int's = %08x\n", readl(&dev->regs->ep_irqsts));
200 DBG(dev, "dev ep intmask = %08x\n", readl(&dev->regs->ep_irqmsk));
201 DBG(dev, "\n");
202 DBG(dev, "USE DMA = %d\n", use_dma);
203 if (use_dma && use_dma_ppb && !use_dma_ppb_du) {
204 DBG(dev, "DMA mode = PPBNDU (packet per buffer "
205 "WITHOUT desc. update)\n");
206 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBNDU");
207 } else if (use_dma && use_dma_ppb && use_dma_ppb_du) {
208 DBG(dev, "DMA mode = PPBDU (packet per buffer "
209 "WITH desc. update)\n");
210 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBDU");
211 }
212 if (use_dma && use_dma_bufferfill_mode) {
213 DBG(dev, "DMA mode = BF (buffer fill mode)\n");
214 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "BF");
215 }
216 if (!use_dma) {
217 dev_info(&dev->pdev->dev, "FIFO mode\n");
218 }
219 DBG(dev, "-------------------------------------------------------\n");
220}
221
222/* Masks unused interrupts */
223static int udc_mask_unused_interrupts(struct udc *dev)
224{
225 u32 tmp;
226
227 /* mask all dev interrupts */
228 tmp = AMD_BIT(UDC_DEVINT_SVC) |
229 AMD_BIT(UDC_DEVINT_ENUM) |
230 AMD_BIT(UDC_DEVINT_US) |
231 AMD_BIT(UDC_DEVINT_UR) |
232 AMD_BIT(UDC_DEVINT_ES) |
233 AMD_BIT(UDC_DEVINT_SI) |
234 AMD_BIT(UDC_DEVINT_SOF)|
235 AMD_BIT(UDC_DEVINT_SC);
236 writel(tmp, &dev->regs->irqmsk);
237
238 /* mask all ep interrupts */
239 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk);
240
241 return 0;
242}
243
244/* Enables endpoint 0 interrupts */
245static int udc_enable_ep0_interrupts(struct udc *dev)
246{
247 u32 tmp;
248
249 DBG(dev, "udc_enable_ep0_interrupts()\n");
250
251 /* read irq mask */
252 tmp = readl(&dev->regs->ep_irqmsk);
253 /* enable ep0 irq's */
254 tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0)
255 & AMD_UNMASK_BIT(UDC_EPINT_OUT_EP0);
256 writel(tmp, &dev->regs->ep_irqmsk);
257
258 return 0;
259}
260
261/* Enables device interrupts for SET_INTF and SET_CONFIG */
262static int udc_enable_dev_setup_interrupts(struct udc *dev)
263{
264 u32 tmp;
265
266 DBG(dev, "enable device interrupts for setup data\n");
267
268 /* read irq mask */
269 tmp = readl(&dev->regs->irqmsk);
270
271 /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
272 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI)
273 & AMD_UNMASK_BIT(UDC_DEVINT_SC)
274 & AMD_UNMASK_BIT(UDC_DEVINT_UR)
275 & AMD_UNMASK_BIT(UDC_DEVINT_SVC)
276 & AMD_UNMASK_BIT(UDC_DEVINT_ENUM);
277 writel(tmp, &dev->regs->irqmsk);
278
279 return 0;
280}
281
282/* Calculates fifo start of endpoint based on preceding endpoints */
283static int udc_set_txfifo_addr(struct udc_ep *ep)
284{
285 struct udc *dev;
286 u32 tmp;
287 int i;
288
289 if (!ep || !(ep->in))
290 return -EINVAL;
291
292 dev = ep->dev;
293 ep->txfifo = dev->txfifo;
294
295 /* traverse ep's */
296 for (i = 0; i < ep->num; i++) {
297 if (dev->ep[i].regs) {
298 /* read fifo size */
299 tmp = readl(&dev->ep[i].regs->bufin_framenum);
300 tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE);
301 ep->txfifo += tmp;
302 }
303 }
304 return 0;
305}
306
307/* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
308static u32 cnak_pending;
309
310static void UDC_QUEUE_CNAK(struct udc_ep *ep, unsigned num)
311{
312 if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) {
313 DBG(ep->dev, "NAK could not be cleared for ep%d\n", num);
314 cnak_pending |= 1 << (num);
315 ep->naking = 1;
316 } else
317 cnak_pending = cnak_pending & (~(1 << (num)));
318}
319
320
321/* Enables endpoint, is called by gadget driver */
322static int
323udc_ep_enable(struct usb_ep *usbep, const struct usb_endpoint_descriptor *desc)
324{
325 struct udc_ep *ep;
326 struct udc *dev;
327 u32 tmp;
328 unsigned long iflags;
329 u8 udc_csr_epix;
330 unsigned maxpacket;
331
332 if (!usbep
333 || usbep->name == ep0_string
334 || !desc
335 || desc->bDescriptorType != USB_DT_ENDPOINT)
336 return -EINVAL;
337
338 ep = container_of(usbep, struct udc_ep, ep);
339 dev = ep->dev;
340
341 DBG(dev, "udc_ep_enable() ep %d\n", ep->num);
342
343 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
344 return -ESHUTDOWN;
345
346 spin_lock_irqsave(&dev->lock, iflags);
347 ep->desc = desc;
348
349 ep->halted = 0;
350
351 /* set traffic type */
352 tmp = readl(&dev->ep[ep->num].regs->ctl);
353 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET);
354 writel(tmp, &dev->ep[ep->num].regs->ctl);
355
356 /* set max packet size */
357 maxpacket = le16_to_cpu(desc->wMaxPacketSize);
358 tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt);
359 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE);
360 ep->ep.maxpacket = maxpacket;
361 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt);
362
363 /* IN ep */
364 if (ep->in) {
365
366 /* ep ix in UDC CSR register space */
367 udc_csr_epix = ep->num;
368
369 /* set buffer size (tx fifo entries) */
370 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum);
371 /* double buffering: fifo size = 2 x max packet size */
372 tmp = AMD_ADDBITS(
373 tmp,
374 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
375 / UDC_DWORD_BYTES,
376 UDC_EPIN_BUFF_SIZE);
377 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum);
378
379 /* calc. tx fifo base addr */
380 udc_set_txfifo_addr(ep);
381
382 /* flush fifo */
383 tmp = readl(&ep->regs->ctl);
384 tmp |= AMD_BIT(UDC_EPCTL_F);
385 writel(tmp, &ep->regs->ctl);
386
387 /* OUT ep */
388 } else {
389 /* ep ix in UDC CSR register space */
390 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
391
392 /* set max packet size UDC CSR */
393 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
394 tmp = AMD_ADDBITS(tmp, maxpacket,
395 UDC_CSR_NE_MAX_PKT);
396 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
397
398 if (use_dma && !ep->in) {
399 /* alloc and init BNA dummy request */
400 ep->bna_dummy_req = udc_alloc_bna_dummy(ep);
401 ep->bna_occurred = 0;
402 }
403
404 if (ep->num != UDC_EP0OUT_IX)
405 dev->data_ep_enabled = 1;
406 }
407
408 /* set ep values */
409 tmp = readl(&dev->csr->ne[udc_csr_epix]);
410 /* max packet */
411 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT);
412 /* ep number */
413 tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM);
414 /* ep direction */
415 tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR);
416 /* ep type */
417 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE);
418 /* ep config */
419 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG);
420 /* ep interface */
421 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF);
422 /* ep alt */
423 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT);
424 /* write reg */
425 writel(tmp, &dev->csr->ne[udc_csr_epix]);
426
427 /* enable ep irq */
428 tmp = readl(&dev->regs->ep_irqmsk);
429 tmp &= AMD_UNMASK_BIT(ep->num);
430 writel(tmp, &dev->regs->ep_irqmsk);
431
432 /*
433 * clear NAK by writing CNAK
434 * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
435 */
436 if (!use_dma || ep->in) {
437 tmp = readl(&ep->regs->ctl);
438 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
439 writel(tmp, &ep->regs->ctl);
440 ep->naking = 0;
441 UDC_QUEUE_CNAK(ep, ep->num);
442 }
443 tmp = desc->bEndpointAddress;
444 DBG(dev, "%s enabled\n", usbep->name);
445
446 spin_unlock_irqrestore(&dev->lock, iflags);
447 return 0;
448}
449
450/* Resets endpoint */
451static void ep_init(struct udc_regs __iomem *regs, struct udc_ep *ep)
452{
453 u32 tmp;
454
455 VDBG(ep->dev, "ep-%d reset\n", ep->num);
456 ep->desc = NULL;
457 ep->ep.ops = &udc_ep_ops;
458 INIT_LIST_HEAD(&ep->queue);
459
460 ep->ep.maxpacket = (u16) ~0;
461 /* set NAK */
462 tmp = readl(&ep->regs->ctl);
463 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
464 writel(tmp, &ep->regs->ctl);
465 ep->naking = 1;
466
467 /* disable interrupt */
468 tmp = readl(®s->ep_irqmsk);
469 tmp |= AMD_BIT(ep->num);
470 writel(tmp, ®s->ep_irqmsk);
471
472 if (ep->in) {
473 /* unset P and IN bit of potential former DMA */
474 tmp = readl(&ep->regs->ctl);
475 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P);
476 writel(tmp, &ep->regs->ctl);
477
478 tmp = readl(&ep->regs->sts);
479 tmp |= AMD_BIT(UDC_EPSTS_IN);
480 writel(tmp, &ep->regs->sts);
481
482 /* flush the fifo */
483 tmp = readl(&ep->regs->ctl);
484 tmp |= AMD_BIT(UDC_EPCTL_F);
485 writel(tmp, &ep->regs->ctl);
486
487 }
488 /* reset desc pointer */
489 writel(0, &ep->regs->desptr);
490}
491
492/* Disables endpoint, is called by gadget driver */
493static int udc_ep_disable(struct usb_ep *usbep)
494{
495 struct udc_ep *ep = NULL;
496 unsigned long iflags;
497
498 if (!usbep)
499 return -EINVAL;
500
501 ep = container_of(usbep, struct udc_ep, ep);
502 if (usbep->name == ep0_string || !ep->desc)
503 return -EINVAL;
504
505 DBG(ep->dev, "Disable ep-%d\n", ep->num);
506
507 spin_lock_irqsave(&ep->dev->lock, iflags);
508 udc_free_request(&ep->ep, &ep->bna_dummy_req->req);
509 empty_req_queue(ep);
510 ep_init(ep->dev->regs, ep);
511 spin_unlock_irqrestore(&ep->dev->lock, iflags);
512
513 return 0;
514}
515
516/* Allocates request packet, called by gadget driver */
517static struct usb_request *
518udc_alloc_request(struct usb_ep *usbep, gfp_t gfp)
519{
520 struct udc_request *req;
521 struct udc_data_dma *dma_desc;
522 struct udc_ep *ep;
523
524 if (!usbep)
525 return NULL;
526
527 ep = container_of(usbep, struct udc_ep, ep);
528
529 VDBG(ep->dev, "udc_alloc_req(): ep%d\n", ep->num);
530 req = kzalloc(sizeof(struct udc_request), gfp);
531 if (!req)
532 return NULL;
533
534 req->req.dma = DMA_DONT_USE;
535 INIT_LIST_HEAD(&req->queue);
536
537 if (ep->dma) {
538 /* ep0 in requests are allocated from data pool here */
539 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
540 &req->td_phys);
541 if (!dma_desc) {
542 kfree(req);
543 return NULL;
544 }
545
546 VDBG(ep->dev, "udc_alloc_req: req = %p dma_desc = %p, "
547 "td_phys = %lx\n",
548 req, dma_desc,
549 (unsigned long)req->td_phys);
550 /* prevent from using desc. - set HOST BUSY */
551 dma_desc->status = AMD_ADDBITS(dma_desc->status,
552 UDC_DMA_STP_STS_BS_HOST_BUSY,
553 UDC_DMA_STP_STS_BS);
554 dma_desc->bufptr = cpu_to_le32(DMA_DONT_USE);
555 req->td_data = dma_desc;
556 req->td_data_last = NULL;
557 req->chain_len = 1;
558 }
559
560 return &req->req;
561}
562
563/* Frees request packet, called by gadget driver */
564static void
565udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq)
566{
567 struct udc_ep *ep;
568 struct udc_request *req;
569
570 if (!usbep || !usbreq)
571 return;
572
573 ep = container_of(usbep, struct udc_ep, ep);
574 req = container_of(usbreq, struct udc_request, req);
575 VDBG(ep->dev, "free_req req=%p\n", req);
576 BUG_ON(!list_empty(&req->queue));
577 if (req->td_data) {
578 VDBG(ep->dev, "req->td_data=%p\n", req->td_data);
579
580 /* free dma chain if created */
581 if (req->chain_len > 1) {
582 udc_free_dma_chain(ep->dev, req);
583 }
584
585 pci_pool_free(ep->dev->data_requests, req->td_data,
586 req->td_phys);
587 }
588 kfree(req);
589}
590
591/* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
592static void udc_init_bna_dummy(struct udc_request *req)
593{
594 if (req) {
595 /* set last bit */
596 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
597 /* set next pointer to itself */
598 req->td_data->next = req->td_phys;
599 /* set HOST BUSY */
600 req->td_data->status
601 = AMD_ADDBITS(req->td_data->status,
602 UDC_DMA_STP_STS_BS_DMA_DONE,
603 UDC_DMA_STP_STS_BS);
604#ifdef UDC_VERBOSE
605 pr_debug("bna desc = %p, sts = %08x\n",
606 req->td_data, req->td_data->status);
607#endif
608 }
609}
610
611/* Allocate BNA dummy descriptor */
612static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep)
613{
614 struct udc_request *req = NULL;
615 struct usb_request *_req = NULL;
616
617 /* alloc the dummy request */
618 _req = udc_alloc_request(&ep->ep, GFP_ATOMIC);
619 if (_req) {
620 req = container_of(_req, struct udc_request, req);
621 ep->bna_dummy_req = req;
622 udc_init_bna_dummy(req);
623 }
624 return req;
625}
626
627/* Write data to TX fifo for IN packets */
628static void
629udc_txfifo_write(struct udc_ep *ep, struct usb_request *req)
630{
631 u8 *req_buf;
632 u32 *buf;
633 int i, j;
634 unsigned bytes = 0;
635 unsigned remaining = 0;
636
637 if (!req || !ep)
638 return;
639
640 req_buf = req->buf + req->actual;
641 prefetch(req_buf);
642 remaining = req->length - req->actual;
643
644 buf = (u32 *) req_buf;
645
646 bytes = ep->ep.maxpacket;
647 if (bytes > remaining)
648 bytes = remaining;
649
650 /* dwords first */
651 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++) {
652 writel(*(buf + i), ep->txfifo);
653 }
654
655 /* remaining bytes must be written by byte access */
656 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
657 writeb((u8)(*(buf + i) >> (j << UDC_BITS_PER_BYTE_SHIFT)),
658 ep->txfifo);
659 }
660
661 /* dummy write confirm */
662 writel(0, &ep->regs->confirm);
663}
664
665/* Read dwords from RX fifo for OUT transfers */
666static int udc_rxfifo_read_dwords(struct udc *dev, u32 *buf, int dwords)
667{
668 int i;
669
670 VDBG(dev, "udc_read_dwords(): %d dwords\n", dwords);
671
672 for (i = 0; i < dwords; i++) {
673 *(buf + i) = readl(dev->rxfifo);
674 }
675 return 0;
676}
677
678/* Read bytes from RX fifo for OUT transfers */
679static int udc_rxfifo_read_bytes(struct udc *dev, u8 *buf, int bytes)
680{
681 int i, j;
682 u32 tmp;
683
684 VDBG(dev, "udc_read_bytes(): %d bytes\n", bytes);
685
686 /* dwords first */
687 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++) {
688 *((u32 *)(buf + (i<<2))) = readl(dev->rxfifo);
689 }
690
691 /* remaining bytes must be read by byte access */
692 if (bytes % UDC_DWORD_BYTES) {
693 tmp = readl(dev->rxfifo);
694 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
695 *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK);
696 tmp = tmp >> UDC_BITS_PER_BYTE;
697 }
698 }
699
700 return 0;
701}
702
703/* Read data from RX fifo for OUT transfers */
704static int
705udc_rxfifo_read(struct udc_ep *ep, struct udc_request *req)
706{
707 u8 *buf;
708 unsigned buf_space;
709 unsigned bytes = 0;
710 unsigned finished = 0;
711
712 /* received number bytes */
713 bytes = readl(&ep->regs->sts);
714 bytes = AMD_GETBITS(bytes, UDC_EPSTS_RX_PKT_SIZE);
715
716 buf_space = req->req.length - req->req.actual;
717 buf = req->req.buf + req->req.actual;
718 if (bytes > buf_space) {
719 if ((buf_space % ep->ep.maxpacket) != 0) {
720 DBG(ep->dev,
721 "%s: rx %d bytes, rx-buf space = %d bytesn\n",
722 ep->ep.name, bytes, buf_space);
723 req->req.status = -EOVERFLOW;
724 }
725 bytes = buf_space;
726 }
727 req->req.actual += bytes;
728
729 /* last packet ? */
730 if (((bytes % ep->ep.maxpacket) != 0) || (!bytes)
731 || ((req->req.actual == req->req.length) && !req->req.zero))
732 finished = 1;
733
734 /* read rx fifo bytes */
735 VDBG(ep->dev, "ep %s: rxfifo read %d bytes\n", ep->ep.name, bytes);
736 udc_rxfifo_read_bytes(ep->dev, buf, bytes);
737
738 return finished;
739}
740
741/* create/re-init a DMA descriptor or a DMA descriptor chain */
742static int prep_dma(struct udc_ep *ep, struct udc_request *req, gfp_t gfp)
743{
744 int retval = 0;
745 u32 tmp;
746
747 VDBG(ep->dev, "prep_dma\n");
748 VDBG(ep->dev, "prep_dma ep%d req->td_data=%p\n",
749 ep->num, req->td_data);
750
751 /* set buffer pointer */
752 req->td_data->bufptr = req->req.dma;
753
754 /* set last bit */
755 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
756
757 /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
758 if (use_dma_ppb) {
759
760 retval = udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
761 if (retval != 0) {
762 if (retval == -ENOMEM)
763 DBG(ep->dev, "Out of DMA memory\n");
764 return retval;
765 }
766 if (ep->in) {
767 if (req->req.length == ep->ep.maxpacket) {
768 /* write tx bytes */
769 req->td_data->status =
770 AMD_ADDBITS(req->td_data->status,
771 ep->ep.maxpacket,
772 UDC_DMA_IN_STS_TXBYTES);
773
774 }
775 }
776
777 }
778
779 if (ep->in) {
780 VDBG(ep->dev, "IN: use_dma_ppb=%d req->req.len=%d "
781 "maxpacket=%d ep%d\n",
782 use_dma_ppb, req->req.length,
783 ep->ep.maxpacket, ep->num);
784 /*
785 * if bytes < max packet then tx bytes must
786 * be written in packet per buffer mode
787 */
788 if (!use_dma_ppb || req->req.length < ep->ep.maxpacket
789 || ep->num == UDC_EP0OUT_IX
790 || ep->num == UDC_EP0IN_IX) {
791 /* write tx bytes */
792 req->td_data->status =
793 AMD_ADDBITS(req->td_data->status,
794 req->req.length,
795 UDC_DMA_IN_STS_TXBYTES);
796 /* reset frame num */
797 req->td_data->status =
798 AMD_ADDBITS(req->td_data->status,
799 0,
800 UDC_DMA_IN_STS_FRAMENUM);
801 }
802 /* set HOST BUSY */
803 req->td_data->status =
804 AMD_ADDBITS(req->td_data->status,
805 UDC_DMA_STP_STS_BS_HOST_BUSY,
806 UDC_DMA_STP_STS_BS);
807 } else {
808 VDBG(ep->dev, "OUT set host ready\n");
809 /* set HOST READY */
810 req->td_data->status =
811 AMD_ADDBITS(req->td_data->status,
812 UDC_DMA_STP_STS_BS_HOST_READY,
813 UDC_DMA_STP_STS_BS);
814
815
816 /* clear NAK by writing CNAK */
817 if (ep->naking) {
818 tmp = readl(&ep->regs->ctl);
819 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
820 writel(tmp, &ep->regs->ctl);
821 ep->naking = 0;
822 UDC_QUEUE_CNAK(ep, ep->num);
823 }
824
825 }
826
827 return retval;
828}
829
830/* Completes request packet ... caller MUST hold lock */
831static void
832complete_req(struct udc_ep *ep, struct udc_request *req, int sts)
833__releases(ep->dev->lock)
834__acquires(ep->dev->lock)
835{
836 struct udc *dev;
837 unsigned halted;
838
839 VDBG(ep->dev, "complete_req(): ep%d\n", ep->num);
840
841 dev = ep->dev;
842 /* unmap DMA */
843 if (req->dma_mapping) {
844 if (ep->in)
845 pci_unmap_single(dev->pdev,
846 req->req.dma,
847 req->req.length,
848 PCI_DMA_TODEVICE);
849 else
850 pci_unmap_single(dev->pdev,
851 req->req.dma,
852 req->req.length,
853 PCI_DMA_FROMDEVICE);
854 req->dma_mapping = 0;
855 req->req.dma = DMA_DONT_USE;
856 }
857
858 halted = ep->halted;
859 ep->halted = 1;
860
861 /* set new status if pending */
862 if (req->req.status == -EINPROGRESS)
863 req->req.status = sts;
864
865 /* remove from ep queue */
866 list_del_init(&req->queue);
867
868 VDBG(ep->dev, "req %p => complete %d bytes at %s with sts %d\n",
869 &req->req, req->req.length, ep->ep.name, sts);
870
871 spin_unlock(&dev->lock);
872 req->req.complete(&ep->ep, &req->req);
873 spin_lock(&dev->lock);
874 ep->halted = halted;
875}
876
877/* frees pci pool descriptors of a DMA chain */
878static int udc_free_dma_chain(struct udc *dev, struct udc_request *req)
879{
880
881 int ret_val = 0;
882 struct udc_data_dma *td;
883 struct udc_data_dma *td_last = NULL;
884 unsigned int i;
885
886 DBG(dev, "free chain req = %p\n", req);
887
888 /* do not free first desc., will be done by free for request */
889 td_last = req->td_data;
890 td = phys_to_virt(td_last->next);
891
892 for (i = 1; i < req->chain_len; i++) {
893
894 pci_pool_free(dev->data_requests, td,
895 (dma_addr_t) td_last->next);
896 td_last = td;
897 td = phys_to_virt(td_last->next);
898 }
899
900 return ret_val;
901}
902
903/* Iterates to the end of a DMA chain and returns last descriptor */
904static struct udc_data_dma *udc_get_last_dma_desc(struct udc_request *req)
905{
906 struct udc_data_dma *td;
907
908 td = req->td_data;
909 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
910 td = phys_to_virt(td->next);
911 }
912
913 return td;
914
915}
916
917/* Iterates to the end of a DMA chain and counts bytes received */
918static u32 udc_get_ppbdu_rxbytes(struct udc_request *req)
919{
920 struct udc_data_dma *td;
921 u32 count;
922
923 td = req->td_data;
924 /* received number bytes */
925 count = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES);
926
927 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
928 td = phys_to_virt(td->next);
929 /* received number bytes */
930 if (td) {
931 count += AMD_GETBITS(td->status,
932 UDC_DMA_OUT_STS_RXBYTES);
933 }
934 }
935
936 return count;
937
938}
939
940/* Creates or re-inits a DMA chain */
941static int udc_create_dma_chain(
942 struct udc_ep *ep,
943 struct udc_request *req,
944 unsigned long buf_len, gfp_t gfp_flags
945)
946{
947 unsigned long bytes = req->req.length;
948 unsigned int i;
949 dma_addr_t dma_addr;
950 struct udc_data_dma *td = NULL;
951 struct udc_data_dma *last = NULL;
952 unsigned long txbytes;
953 unsigned create_new_chain = 0;
954 unsigned len;
955
956 VDBG(ep->dev, "udc_create_dma_chain: bytes=%ld buf_len=%ld\n",
957 bytes, buf_len);
958 dma_addr = DMA_DONT_USE;
959
960 /* unset L bit in first desc for OUT */
961 if (!ep->in) {
962 req->td_data->status &= AMD_CLEAR_BIT(UDC_DMA_IN_STS_L);
963 }
964
965 /* alloc only new desc's if not already available */
966 len = req->req.length / ep->ep.maxpacket;
967 if (req->req.length % ep->ep.maxpacket) {
968 len++;
969 }
970
971 if (len > req->chain_len) {
972 /* shorter chain already allocated before */
973 if (req->chain_len > 1) {
974 udc_free_dma_chain(ep->dev, req);
975 }
976 req->chain_len = len;
977 create_new_chain = 1;
978 }
979
980 td = req->td_data;
981 /* gen. required number of descriptors and buffers */
982 for (i = buf_len; i < bytes; i += buf_len) {
983 /* create or determine next desc. */
984 if (create_new_chain) {
985
986 td = pci_pool_alloc(ep->dev->data_requests,
987 gfp_flags, &dma_addr);
988 if (!td)
989 return -ENOMEM;
990
991 td->status = 0;
992 } else if (i == buf_len) {
993 /* first td */
994 td = (struct udc_data_dma *) phys_to_virt(
995 req->td_data->next);
996 td->status = 0;
997 } else {
998 td = (struct udc_data_dma *) phys_to_virt(last->next);
999 td->status = 0;
1000 }
1001
1002
1003 if (td)
1004 td->bufptr = req->req.dma + i; /* assign buffer */
1005 else
1006 break;
1007
1008 /* short packet ? */
1009 if ((bytes - i) >= buf_len) {
1010 txbytes = buf_len;
1011 } else {
1012 /* short packet */
1013 txbytes = bytes - i;
1014 }
1015
1016 /* link td and assign tx bytes */
1017 if (i == buf_len) {
1018 if (create_new_chain) {
1019 req->td_data->next = dma_addr;
1020 } else {
1021 /* req->td_data->next = virt_to_phys(td); */
1022 }
1023 /* write tx bytes */
1024 if (ep->in) {
1025 /* first desc */
1026 req->td_data->status =
1027 AMD_ADDBITS(req->td_data->status,
1028 ep->ep.maxpacket,
1029 UDC_DMA_IN_STS_TXBYTES);
1030 /* second desc */
1031 td->status = AMD_ADDBITS(td->status,
1032 txbytes,
1033 UDC_DMA_IN_STS_TXBYTES);
1034 }
1035 } else {
1036 if (create_new_chain) {
1037 last->next = dma_addr;
1038 } else {
1039 /* last->next = virt_to_phys(td); */
1040 }
1041 if (ep->in) {
1042 /* write tx bytes */
1043 td->status = AMD_ADDBITS(td->status,
1044 txbytes,
1045 UDC_DMA_IN_STS_TXBYTES);
1046 }
1047 }
1048 last = td;
1049 }
1050 /* set last bit */
1051 if (td) {
1052 td->status |= AMD_BIT(UDC_DMA_IN_STS_L);
1053 /* last desc. points to itself */
1054 req->td_data_last = td;
1055 }
1056
1057 return 0;
1058}
1059
1060/* Enabling RX DMA */
1061static void udc_set_rde(struct udc *dev)
1062{
1063 u32 tmp;
1064
1065 VDBG(dev, "udc_set_rde()\n");
1066 /* stop RDE timer */
1067 if (timer_pending(&udc_timer)) {
1068 set_rde = 0;
1069 mod_timer(&udc_timer, jiffies - 1);
1070 }
1071 /* set RDE */
1072 tmp = readl(&dev->regs->ctl);
1073 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1074 writel(tmp, &dev->regs->ctl);
1075}
1076
1077/* Queues a request packet, called by gadget driver */
1078static int
1079udc_queue(struct usb_ep *usbep, struct usb_request *usbreq, gfp_t gfp)
1080{
1081 int retval = 0;
1082 u8 open_rxfifo = 0;
1083 unsigned long iflags;
1084 struct udc_ep *ep;
1085 struct udc_request *req;
1086 struct udc *dev;
1087 u32 tmp;
1088
1089 /* check the inputs */
1090 req = container_of(usbreq, struct udc_request, req);
1091
1092 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf
1093 || !list_empty(&req->queue))
1094 return -EINVAL;
1095
1096 ep = container_of(usbep, struct udc_ep, ep);
1097 if (!ep->desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1098 return -EINVAL;
1099
1100 VDBG(ep->dev, "udc_queue(): ep%d-in=%d\n", ep->num, ep->in);
1101 dev = ep->dev;
1102
1103 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1104 return -ESHUTDOWN;
1105
1106 /* map dma (usually done before) */
1107 if (ep->dma && usbreq->length != 0
1108 && (usbreq->dma == DMA_DONT_USE || usbreq->dma == 0)) {
1109 VDBG(dev, "DMA map req %p\n", req);
1110 if (ep->in)
1111 usbreq->dma = pci_map_single(dev->pdev,
1112 usbreq->buf,
1113 usbreq->length,
1114 PCI_DMA_TODEVICE);
1115 else
1116 usbreq->dma = pci_map_single(dev->pdev,
1117 usbreq->buf,
1118 usbreq->length,
1119 PCI_DMA_FROMDEVICE);
1120 req->dma_mapping = 1;
1121 }
1122
1123 VDBG(dev, "%s queue req %p, len %d req->td_data=%p buf %p\n",
1124 usbep->name, usbreq, usbreq->length,
1125 req->td_data, usbreq->buf);
1126
1127 spin_lock_irqsave(&dev->lock, iflags);
1128 usbreq->actual = 0;
1129 usbreq->status = -EINPROGRESS;
1130 req->dma_done = 0;
1131
1132 /* on empty queue just do first transfer */
1133 if (list_empty(&ep->queue)) {
1134 /* zlp */
1135 if (usbreq->length == 0) {
1136 /* IN zlp's are handled by hardware */
1137 complete_req(ep, req, 0);
1138 VDBG(dev, "%s: zlp\n", ep->ep.name);
1139 /*
1140 * if set_config or set_intf is waiting for ack by zlp
1141 * then set CSR_DONE
1142 */
1143 if (dev->set_cfg_not_acked) {
1144 tmp = readl(&dev->regs->ctl);
1145 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE);
1146 writel(tmp, &dev->regs->ctl);
1147 dev->set_cfg_not_acked = 0;
1148 }
1149 /* setup command is ACK'ed now by zlp */
1150 if (dev->waiting_zlp_ack_ep0in) {
1151 /* clear NAK by writing CNAK in EP0_IN */
1152 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1153 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1154 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1155 dev->ep[UDC_EP0IN_IX].naking = 0;
1156 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX],
1157 UDC_EP0IN_IX);
1158 dev->waiting_zlp_ack_ep0in = 0;
1159 }
1160 goto finished;
1161 }
1162 if (ep->dma) {
1163 retval = prep_dma(ep, req, gfp);
1164 if (retval != 0)
1165 goto finished;
1166 /* write desc pointer to enable DMA */
1167 if (ep->in) {
1168 /* set HOST READY */
1169 req->td_data->status =
1170 AMD_ADDBITS(req->td_data->status,
1171 UDC_DMA_IN_STS_BS_HOST_READY,
1172 UDC_DMA_IN_STS_BS);
1173 }
1174
1175 /* disabled rx dma while descriptor update */
1176 if (!ep->in) {
1177 /* stop RDE timer */
1178 if (timer_pending(&udc_timer)) {
1179 set_rde = 0;
1180 mod_timer(&udc_timer, jiffies - 1);
1181 }
1182 /* clear RDE */
1183 tmp = readl(&dev->regs->ctl);
1184 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1185 writel(tmp, &dev->regs->ctl);
1186 open_rxfifo = 1;
1187
1188 /*
1189 * if BNA occurred then let BNA dummy desc.
1190 * point to current desc.
1191 */
1192 if (ep->bna_occurred) {
1193 VDBG(dev, "copy to BNA dummy desc.\n");
1194 memcpy(ep->bna_dummy_req->td_data,
1195 req->td_data,
1196 sizeof(struct udc_data_dma));
1197 }
1198 }
1199 /* write desc pointer */
1200 writel(req->td_phys, &ep->regs->desptr);
1201
1202 /* clear NAK by writing CNAK */
1203 if (ep->naking) {
1204 tmp = readl(&ep->regs->ctl);
1205 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1206 writel(tmp, &ep->regs->ctl);
1207 ep->naking = 0;
1208 UDC_QUEUE_CNAK(ep, ep->num);
1209 }
1210
1211 if (ep->in) {
1212 /* enable ep irq */
1213 tmp = readl(&dev->regs->ep_irqmsk);
1214 tmp &= AMD_UNMASK_BIT(ep->num);
1215 writel(tmp, &dev->regs->ep_irqmsk);
1216 }
1217 } else if (ep->in) {
1218 /* enable ep irq */
1219 tmp = readl(&dev->regs->ep_irqmsk);
1220 tmp &= AMD_UNMASK_BIT(ep->num);
1221 writel(tmp, &dev->regs->ep_irqmsk);
1222 }
1223
1224 } else if (ep->dma) {
1225
1226 /*
1227 * prep_dma not used for OUT ep's, this is not possible
1228 * for PPB modes, because of chain creation reasons
1229 */
1230 if (ep->in) {
1231 retval = prep_dma(ep, req, gfp);
1232 if (retval != 0)
1233 goto finished;
1234 }
1235 }
1236 VDBG(dev, "list_add\n");
1237 /* add request to ep queue */
1238 if (req) {
1239
1240 list_add_tail(&req->queue, &ep->queue);
1241
1242 /* open rxfifo if out data queued */
1243 if (open_rxfifo) {
1244 /* enable DMA */
1245 req->dma_going = 1;
1246 udc_set_rde(dev);
1247 if (ep->num != UDC_EP0OUT_IX)
1248 dev->data_ep_queued = 1;
1249 }
1250 /* stop OUT naking */
1251 if (!ep->in) {
1252 if (!use_dma && udc_rxfifo_pending) {
1253 DBG(dev, "udc_queue(): pending bytes in "
1254 "rxfifo after nyet\n");
1255 /*
1256 * read pending bytes afer nyet:
1257 * referring to isr
1258 */
1259 if (udc_rxfifo_read(ep, req)) {
1260 /* finish */
1261 complete_req(ep, req, 0);
1262 }
1263 udc_rxfifo_pending = 0;
1264
1265 }
1266 }
1267 }
1268
1269finished:
1270 spin_unlock_irqrestore(&dev->lock, iflags);
1271 return retval;
1272}
1273
1274/* Empty request queue of an endpoint; caller holds spinlock */
1275static void empty_req_queue(struct udc_ep *ep)
1276{
1277 struct udc_request *req;
1278
1279 ep->halted = 1;
1280 while (!list_empty(&ep->queue)) {
1281 req = list_entry(ep->queue.next,
1282 struct udc_request,
1283 queue);
1284 complete_req(ep, req, -ESHUTDOWN);
1285 }
1286}
1287
1288/* Dequeues a request packet, called by gadget driver */
1289static int udc_dequeue(struct usb_ep *usbep, struct usb_request *usbreq)
1290{
1291 struct udc_ep *ep;
1292 struct udc_request *req;
1293 unsigned halted;
1294 unsigned long iflags;
1295
1296 ep = container_of(usbep, struct udc_ep, ep);
1297 if (!usbep || !usbreq || (!ep->desc && (ep->num != 0
1298 && ep->num != UDC_EP0OUT_IX)))
1299 return -EINVAL;
1300
1301 req = container_of(usbreq, struct udc_request, req);
1302
1303 spin_lock_irqsave(&ep->dev->lock, iflags);
1304 halted = ep->halted;
1305 ep->halted = 1;
1306 /* request in processing or next one */
1307 if (ep->queue.next == &req->queue) {
1308 if (ep->dma && req->dma_going) {
1309 if (ep->in)
1310 ep->cancel_transfer = 1;
1311 else {
1312 u32 tmp;
1313 u32 dma_sts;
1314 /* stop potential receive DMA */
1315 tmp = readl(&udc->regs->ctl);
1316 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE),
1317 &udc->regs->ctl);
1318 /*
1319 * Cancel transfer later in ISR
1320 * if descriptor was touched.
1321 */
1322 dma_sts = AMD_GETBITS(req->td_data->status,
1323 UDC_DMA_OUT_STS_BS);
1324 if (dma_sts != UDC_DMA_OUT_STS_BS_HOST_READY)
1325 ep->cancel_transfer = 1;
1326 else {
1327 udc_init_bna_dummy(ep->req);
1328 writel(ep->bna_dummy_req->td_phys,
1329 &ep->regs->desptr);
1330 }
1331 writel(tmp, &udc->regs->ctl);
1332 }
1333 }
1334 }
1335 complete_req(ep, req, -ECONNRESET);
1336 ep->halted = halted;
1337
1338 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1339 return 0;
1340}
1341
1342/* Halt or clear halt of endpoint */
1343static int
1344udc_set_halt(struct usb_ep *usbep, int halt)
1345{
1346 struct udc_ep *ep;
1347 u32 tmp;
1348 unsigned long iflags;
1349 int retval = 0;
1350
1351 if (!usbep)
1352 return -EINVAL;
1353
1354 pr_debug("set_halt %s: halt=%d\n", usbep->name, halt);
1355
1356 ep = container_of(usbep, struct udc_ep, ep);
1357 if (!ep->desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1358 return -EINVAL;
1359 if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN)
1360 return -ESHUTDOWN;
1361
1362 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1363 /* halt or clear halt */
1364 if (halt) {
1365 if (ep->num == 0)
1366 ep->dev->stall_ep0in = 1;
1367 else {
1368 /*
1369 * set STALL
1370 * rxfifo empty not taken into acount
1371 */
1372 tmp = readl(&ep->regs->ctl);
1373 tmp |= AMD_BIT(UDC_EPCTL_S);
1374 writel(tmp, &ep->regs->ctl);
1375 ep->halted = 1;
1376
1377 /* setup poll timer */
1378 if (!timer_pending(&udc_pollstall_timer)) {
1379 udc_pollstall_timer.expires = jiffies +
1380 HZ * UDC_POLLSTALL_TIMER_USECONDS
1381 / (1000 * 1000);
1382 if (!stop_pollstall_timer) {
1383 DBG(ep->dev, "start polltimer\n");
1384 add_timer(&udc_pollstall_timer);
1385 }
1386 }
1387 }
1388 } else {
1389 /* ep is halted by set_halt() before */
1390 if (ep->halted) {
1391 tmp = readl(&ep->regs->ctl);
1392 /* clear stall bit */
1393 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
1394 /* clear NAK by writing CNAK */
1395 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1396 writel(tmp, &ep->regs->ctl);
1397 ep->halted = 0;
1398 UDC_QUEUE_CNAK(ep, ep->num);
1399 }
1400 }
1401 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1402 return retval;
1403}
1404
1405/* gadget interface */
1406static const struct usb_ep_ops udc_ep_ops = {
1407 .enable = udc_ep_enable,
1408 .disable = udc_ep_disable,
1409
1410 .alloc_request = udc_alloc_request,
1411 .free_request = udc_free_request,
1412
1413 .queue = udc_queue,
1414 .dequeue = udc_dequeue,
1415
1416 .set_halt = udc_set_halt,
1417 /* fifo ops not implemented */
1418};
1419
1420/*-------------------------------------------------------------------------*/
1421
1422/* Get frame counter (not implemented) */
1423static int udc_get_frame(struct usb_gadget *gadget)
1424{
1425 return -EOPNOTSUPP;
1426}
1427
1428/* Remote wakeup gadget interface */
1429static int udc_wakeup(struct usb_gadget *gadget)
1430{
1431 struct udc *dev;
1432
1433 if (!gadget)
1434 return -EINVAL;
1435 dev = container_of(gadget, struct udc, gadget);
1436 udc_remote_wakeup(dev);
1437
1438 return 0;
1439}
1440
1441static int amd5536_start(struct usb_gadget_driver *driver,
1442 int (*bind)(struct usb_gadget *));
1443static int amd5536_stop(struct usb_gadget_driver *driver);
1444/* gadget operations */
1445static const struct usb_gadget_ops udc_ops = {
1446 .wakeup = udc_wakeup,
1447 .get_frame = udc_get_frame,
1448 .start = amd5536_start,
1449 .stop = amd5536_stop,
1450};
1451
1452/* Setups endpoint parameters, adds endpoints to linked list */
1453static void make_ep_lists(struct udc *dev)
1454{
1455 /* make gadget ep lists */
1456 INIT_LIST_HEAD(&dev->gadget.ep_list);
1457 list_add_tail(&dev->ep[UDC_EPIN_STATUS_IX].ep.ep_list,
1458 &dev->gadget.ep_list);
1459 list_add_tail(&dev->ep[UDC_EPIN_IX].ep.ep_list,
1460 &dev->gadget.ep_list);
1461 list_add_tail(&dev->ep[UDC_EPOUT_IX].ep.ep_list,
1462 &dev->gadget.ep_list);
1463
1464 /* fifo config */
1465 dev->ep[UDC_EPIN_STATUS_IX].fifo_depth = UDC_EPIN_SMALLINT_BUFF_SIZE;
1466 if (dev->gadget.speed == USB_SPEED_FULL)
1467 dev->ep[UDC_EPIN_IX].fifo_depth = UDC_FS_EPIN_BUFF_SIZE;
1468 else if (dev->gadget.speed == USB_SPEED_HIGH)
1469 dev->ep[UDC_EPIN_IX].fifo_depth = hs_tx_buf;
1470 dev->ep[UDC_EPOUT_IX].fifo_depth = UDC_RXFIFO_SIZE;
1471}
1472
1473/* init registers at driver load time */
1474static int startup_registers(struct udc *dev)
1475{
1476 u32 tmp;
1477
1478 /* init controller by soft reset */
1479 udc_soft_reset(dev);
1480
1481 /* mask not needed interrupts */
1482 udc_mask_unused_interrupts(dev);
1483
1484 /* put into initial config */
1485 udc_basic_init(dev);
1486 /* link up all endpoints */
1487 udc_setup_endpoints(dev);
1488
1489 /* program speed */
1490 tmp = readl(&dev->regs->cfg);
1491 if (use_fullspeed) {
1492 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1493 } else {
1494 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD);
1495 }
1496 writel(tmp, &dev->regs->cfg);
1497
1498 return 0;
1499}
1500
1501/* Inits UDC context */
1502static void udc_basic_init(struct udc *dev)
1503{
1504 u32 tmp;
1505
1506 DBG(dev, "udc_basic_init()\n");
1507
1508 dev->gadget.speed = USB_SPEED_UNKNOWN;
1509
1510 /* stop RDE timer */
1511 if (timer_pending(&udc_timer)) {
1512 set_rde = 0;
1513 mod_timer(&udc_timer, jiffies - 1);
1514 }
1515 /* stop poll stall timer */
1516 if (timer_pending(&udc_pollstall_timer)) {
1517 mod_timer(&udc_pollstall_timer, jiffies - 1);
1518 }
1519 /* disable DMA */
1520 tmp = readl(&dev->regs->ctl);
1521 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1522 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE);
1523 writel(tmp, &dev->regs->ctl);
1524
1525 /* enable dynamic CSR programming */
1526 tmp = readl(&dev->regs->cfg);
1527 tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG);
1528 /* set self powered */
1529 tmp |= AMD_BIT(UDC_DEVCFG_SP);
1530 /* set remote wakeupable */
1531 tmp |= AMD_BIT(UDC_DEVCFG_RWKP);
1532 writel(tmp, &dev->regs->cfg);
1533
1534 make_ep_lists(dev);
1535
1536 dev->data_ep_enabled = 0;
1537 dev->data_ep_queued = 0;
1538}
1539
1540/* Sets initial endpoint parameters */
1541static void udc_setup_endpoints(struct udc *dev)
1542{
1543 struct udc_ep *ep;
1544 u32 tmp;
1545 u32 reg;
1546
1547 DBG(dev, "udc_setup_endpoints()\n");
1548
1549 /* read enum speed */
1550 tmp = readl(&dev->regs->sts);
1551 tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED);
1552 if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH) {
1553 dev->gadget.speed = USB_SPEED_HIGH;
1554 } else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL) {
1555 dev->gadget.speed = USB_SPEED_FULL;
1556 }
1557
1558 /* set basic ep parameters */
1559 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1560 ep = &dev->ep[tmp];
1561 ep->dev = dev;
1562 ep->ep.name = ep_string[tmp];
1563 ep->num = tmp;
1564 /* txfifo size is calculated at enable time */
1565 ep->txfifo = dev->txfifo;
1566
1567 /* fifo size */
1568 if (tmp < UDC_EPIN_NUM) {
1569 ep->fifo_depth = UDC_TXFIFO_SIZE;
1570 ep->in = 1;
1571 } else {
1572 ep->fifo_depth = UDC_RXFIFO_SIZE;
1573 ep->in = 0;
1574
1575 }
1576 ep->regs = &dev->ep_regs[tmp];
1577 /*
1578 * ep will be reset only if ep was not enabled before to avoid
1579 * disabling ep interrupts when ENUM interrupt occurs but ep is
1580 * not enabled by gadget driver
1581 */
1582 if (!ep->desc) {
1583 ep_init(dev->regs, ep);
1584 }
1585
1586 if (use_dma) {
1587 /*
1588 * ep->dma is not really used, just to indicate that
1589 * DMA is active: remove this
1590 * dma regs = dev control regs
1591 */
1592 ep->dma = &dev->regs->ctl;
1593
1594 /* nak OUT endpoints until enable - not for ep0 */
1595 if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX
1596 && tmp > UDC_EPIN_NUM) {
1597 /* set NAK */
1598 reg = readl(&dev->ep[tmp].regs->ctl);
1599 reg |= AMD_BIT(UDC_EPCTL_SNAK);
1600 writel(reg, &dev->ep[tmp].regs->ctl);
1601 dev->ep[tmp].naking = 1;
1602
1603 }
1604 }
1605 }
1606 /* EP0 max packet */
1607 if (dev->gadget.speed == USB_SPEED_FULL) {
1608 dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_FS_EP0IN_MAX_PKT_SIZE;
1609 dev->ep[UDC_EP0OUT_IX].ep.maxpacket =
1610 UDC_FS_EP0OUT_MAX_PKT_SIZE;
1611 } else if (dev->gadget.speed == USB_SPEED_HIGH) {
1612 dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
1613 dev->ep[UDC_EP0OUT_IX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
1614 }
1615
1616 /*
1617 * with suspend bug workaround, ep0 params for gadget driver
1618 * are set at gadget driver bind() call
1619 */
1620 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
1621 dev->ep[UDC_EP0IN_IX].halted = 0;
1622 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1623
1624 /* init cfg/alt/int */
1625 dev->cur_config = 0;
1626 dev->cur_intf = 0;
1627 dev->cur_alt = 0;
1628}
1629
1630/* Bringup after Connect event, initial bringup to be ready for ep0 events */
1631static void usb_connect(struct udc *dev)
1632{
1633
1634 dev_info(&dev->pdev->dev, "USB Connect\n");
1635
1636 dev->connected = 1;
1637
1638 /* put into initial config */
1639 udc_basic_init(dev);
1640
1641 /* enable device setup interrupts */
1642 udc_enable_dev_setup_interrupts(dev);
1643}
1644
1645/*
1646 * Calls gadget with disconnect event and resets the UDC and makes
1647 * initial bringup to be ready for ep0 events
1648 */
1649static void usb_disconnect(struct udc *dev)
1650{
1651
1652 dev_info(&dev->pdev->dev, "USB Disconnect\n");
1653
1654 dev->connected = 0;
1655
1656 /* mask interrupts */
1657 udc_mask_unused_interrupts(dev);
1658
1659 /* REVISIT there doesn't seem to be a point to having this
1660 * talk to a tasklet ... do it directly, we already hold
1661 * the spinlock needed to process the disconnect.
1662 */
1663
1664 tasklet_schedule(&disconnect_tasklet);
1665}
1666
1667/* Tasklet for disconnect to be outside of interrupt context */
1668static void udc_tasklet_disconnect(unsigned long par)
1669{
1670 struct udc *dev = (struct udc *)(*((struct udc **) par));
1671 u32 tmp;
1672
1673 DBG(dev, "Tasklet disconnect\n");
1674 spin_lock_irq(&dev->lock);
1675
1676 if (dev->driver) {
1677 spin_unlock(&dev->lock);
1678 dev->driver->disconnect(&dev->gadget);
1679 spin_lock(&dev->lock);
1680
1681 /* empty queues */
1682 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1683 empty_req_queue(&dev->ep[tmp]);
1684 }
1685
1686 }
1687
1688 /* disable ep0 */
1689 ep_init(dev->regs,
1690 &dev->ep[UDC_EP0IN_IX]);
1691
1692
1693 if (!soft_reset_occured) {
1694 /* init controller by soft reset */
1695 udc_soft_reset(dev);
1696 soft_reset_occured++;
1697 }
1698
1699 /* re-enable dev interrupts */
1700 udc_enable_dev_setup_interrupts(dev);
1701 /* back to full speed ? */
1702 if (use_fullspeed) {
1703 tmp = readl(&dev->regs->cfg);
1704 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1705 writel(tmp, &dev->regs->cfg);
1706 }
1707
1708 spin_unlock_irq(&dev->lock);
1709}
1710
1711/* Reset the UDC core */
1712static void udc_soft_reset(struct udc *dev)
1713{
1714 unsigned long flags;
1715
1716 DBG(dev, "Soft reset\n");
1717 /*
1718 * reset possible waiting interrupts, because int.
1719 * status is lost after soft reset,
1720 * ep int. status reset
1721 */
1722 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts);
1723 /* device int. status reset */
1724 writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts);
1725
1726 spin_lock_irqsave(&udc_irq_spinlock, flags);
1727 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
1728 readl(&dev->regs->cfg);
1729 spin_unlock_irqrestore(&udc_irq_spinlock, flags);
1730
1731}
1732
1733/* RDE timer callback to set RDE bit */
1734static void udc_timer_function(unsigned long v)
1735{
1736 u32 tmp;
1737
1738 spin_lock_irq(&udc_irq_spinlock);
1739
1740 if (set_rde > 0) {
1741 /*
1742 * open the fifo if fifo was filled on last timer call
1743 * conditionally
1744 */
1745 if (set_rde > 1) {
1746 /* set RDE to receive setup data */
1747 tmp = readl(&udc->regs->ctl);
1748 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1749 writel(tmp, &udc->regs->ctl);
1750 set_rde = -1;
1751 } else if (readl(&udc->regs->sts)
1752 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
1753 /*
1754 * if fifo empty setup polling, do not just
1755 * open the fifo
1756 */
1757 udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV;
1758 if (!stop_timer) {
1759 add_timer(&udc_timer);
1760 }
1761 } else {
1762 /*
1763 * fifo contains data now, setup timer for opening
1764 * the fifo when timer expires to be able to receive
1765 * setup packets, when data packets gets queued by
1766 * gadget layer then timer will forced to expire with
1767 * set_rde=0 (RDE is set in udc_queue())
1768 */
1769 set_rde++;
1770 /* debug: lhadmot_timer_start = 221070 */
1771 udc_timer.expires = jiffies + HZ*UDC_RDE_TIMER_SECONDS;
1772 if (!stop_timer) {
1773 add_timer(&udc_timer);
1774 }
1775 }
1776
1777 } else
1778 set_rde = -1; /* RDE was set by udc_queue() */
1779 spin_unlock_irq(&udc_irq_spinlock);
1780 if (stop_timer)
1781 complete(&on_exit);
1782
1783}
1784
1785/* Handle halt state, used in stall poll timer */
1786static void udc_handle_halt_state(struct udc_ep *ep)
1787{
1788 u32 tmp;
1789 /* set stall as long not halted */
1790 if (ep->halted == 1) {
1791 tmp = readl(&ep->regs->ctl);
1792 /* STALL cleared ? */
1793 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) {
1794 /*
1795 * FIXME: MSC spec requires that stall remains
1796 * even on receivng of CLEAR_FEATURE HALT. So
1797 * we would set STALL again here to be compliant.
1798 * But with current mass storage drivers this does
1799 * not work (would produce endless host retries).
1800 * So we clear halt on CLEAR_FEATURE.
1801 *
1802 DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1803 tmp |= AMD_BIT(UDC_EPCTL_S);
1804 writel(tmp, &ep->regs->ctl);*/
1805
1806 /* clear NAK by writing CNAK */
1807 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1808 writel(tmp, &ep->regs->ctl);
1809 ep->halted = 0;
1810 UDC_QUEUE_CNAK(ep, ep->num);
1811 }
1812 }
1813}
1814
1815/* Stall timer callback to poll S bit and set it again after */
1816static void udc_pollstall_timer_function(unsigned long v)
1817{
1818 struct udc_ep *ep;
1819 int halted = 0;
1820
1821 spin_lock_irq(&udc_stall_spinlock);
1822 /*
1823 * only one IN and OUT endpoints are handled
1824 * IN poll stall
1825 */
1826 ep = &udc->ep[UDC_EPIN_IX];
1827 udc_handle_halt_state(ep);
1828 if (ep->halted)
1829 halted = 1;
1830 /* OUT poll stall */
1831 ep = &udc->ep[UDC_EPOUT_IX];
1832 udc_handle_halt_state(ep);
1833 if (ep->halted)
1834 halted = 1;
1835
1836 /* setup timer again when still halted */
1837 if (!stop_pollstall_timer && halted) {
1838 udc_pollstall_timer.expires = jiffies +
1839 HZ * UDC_POLLSTALL_TIMER_USECONDS
1840 / (1000 * 1000);
1841 add_timer(&udc_pollstall_timer);
1842 }
1843 spin_unlock_irq(&udc_stall_spinlock);
1844
1845 if (stop_pollstall_timer)
1846 complete(&on_pollstall_exit);
1847}
1848
1849/* Inits endpoint 0 so that SETUP packets are processed */
1850static void activate_control_endpoints(struct udc *dev)
1851{
1852 u32 tmp;
1853
1854 DBG(dev, "activate_control_endpoints\n");
1855
1856 /* flush fifo */
1857 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1858 tmp |= AMD_BIT(UDC_EPCTL_F);
1859 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1860
1861 /* set ep0 directions */
1862 dev->ep[UDC_EP0IN_IX].in = 1;
1863 dev->ep[UDC_EP0OUT_IX].in = 0;
1864
1865 /* set buffer size (tx fifo entries) of EP0_IN */
1866 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1867 if (dev->gadget.speed == USB_SPEED_FULL)
1868 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE,
1869 UDC_EPIN_BUFF_SIZE);
1870 else if (dev->gadget.speed == USB_SPEED_HIGH)
1871 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE,
1872 UDC_EPIN_BUFF_SIZE);
1873 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1874
1875 /* set max packet size of EP0_IN */
1876 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1877 if (dev->gadget.speed == USB_SPEED_FULL)
1878 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE,
1879 UDC_EP_MAX_PKT_SIZE);
1880 else if (dev->gadget.speed == USB_SPEED_HIGH)
1881 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE,
1882 UDC_EP_MAX_PKT_SIZE);
1883 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1884
1885 /* set max packet size of EP0_OUT */
1886 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1887 if (dev->gadget.speed == USB_SPEED_FULL)
1888 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1889 UDC_EP_MAX_PKT_SIZE);
1890 else if (dev->gadget.speed == USB_SPEED_HIGH)
1891 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1892 UDC_EP_MAX_PKT_SIZE);
1893 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1894
1895 /* set max packet size of EP0 in UDC CSR */
1896 tmp = readl(&dev->csr->ne[0]);
1897 if (dev->gadget.speed == USB_SPEED_FULL)
1898 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1899 UDC_CSR_NE_MAX_PKT);
1900 else if (dev->gadget.speed == USB_SPEED_HIGH)
1901 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1902 UDC_CSR_NE_MAX_PKT);
1903 writel(tmp, &dev->csr->ne[0]);
1904
1905 if (use_dma) {
1906 dev->ep[UDC_EP0OUT_IX].td->status |=
1907 AMD_BIT(UDC_DMA_OUT_STS_L);
1908 /* write dma desc address */
1909 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma,
1910 &dev->ep[UDC_EP0OUT_IX].regs->subptr);
1911 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
1912 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
1913 /* stop RDE timer */
1914 if (timer_pending(&udc_timer)) {
1915 set_rde = 0;
1916 mod_timer(&udc_timer, jiffies - 1);
1917 }
1918 /* stop pollstall timer */
1919 if (timer_pending(&udc_pollstall_timer)) {
1920 mod_timer(&udc_pollstall_timer, jiffies - 1);
1921 }
1922 /* enable DMA */
1923 tmp = readl(&dev->regs->ctl);
1924 tmp |= AMD_BIT(UDC_DEVCTL_MODE)
1925 | AMD_BIT(UDC_DEVCTL_RDE)
1926 | AMD_BIT(UDC_DEVCTL_TDE);
1927 if (use_dma_bufferfill_mode) {
1928 tmp |= AMD_BIT(UDC_DEVCTL_BF);
1929 } else if (use_dma_ppb_du) {
1930 tmp |= AMD_BIT(UDC_DEVCTL_DU);
1931 }
1932 writel(tmp, &dev->regs->ctl);
1933 }
1934
1935 /* clear NAK by writing CNAK for EP0IN */
1936 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1937 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1938 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1939 dev->ep[UDC_EP0IN_IX].naking = 0;
1940 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
1941
1942 /* clear NAK by writing CNAK for EP0OUT */
1943 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
1944 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1945 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
1946 dev->ep[UDC_EP0OUT_IX].naking = 0;
1947 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
1948}
1949
1950/* Make endpoint 0 ready for control traffic */
1951static int setup_ep0(struct udc *dev)
1952{
1953 activate_control_endpoints(dev);
1954 /* enable ep0 interrupts */
1955 udc_enable_ep0_interrupts(dev);
1956 /* enable device setup interrupts */
1957 udc_enable_dev_setup_interrupts(dev);
1958
1959 return 0;
1960}
1961
1962/* Called by gadget driver to register itself */
1963static int amd5536_start(struct usb_gadget_driver *driver,
1964 int (*bind)(struct usb_gadget *))
1965{
1966 struct udc *dev = udc;
1967 int retval;
1968 u32 tmp;
1969
1970 if (!driver || !bind || !driver->setup
1971 || driver->speed != USB_SPEED_HIGH)
1972 return -EINVAL;
1973 if (!dev)
1974 return -ENODEV;
1975 if (dev->driver)
1976 return -EBUSY;
1977
1978 driver->driver.bus = NULL;
1979 dev->driver = driver;
1980 dev->gadget.dev.driver = &driver->driver;
1981
1982 retval = bind(&dev->gadget);
1983
1984 /* Some gadget drivers use both ep0 directions.
1985 * NOTE: to gadget driver, ep0 is just one endpoint...
1986 */
1987 dev->ep[UDC_EP0OUT_IX].ep.driver_data =
1988 dev->ep[UDC_EP0IN_IX].ep.driver_data;
1989
1990 if (retval) {
1991 DBG(dev, "binding to %s returning %d\n",
1992 driver->driver.name, retval);
1993 dev->driver = NULL;
1994 dev->gadget.dev.driver = NULL;
1995 return retval;
1996 }
1997
1998 /* get ready for ep0 traffic */
1999 setup_ep0(dev);
2000
2001 /* clear SD */
2002 tmp = readl(&dev->regs->ctl);
2003 tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD);
2004 writel(tmp, &dev->regs->ctl);
2005
2006 usb_connect(dev);
2007
2008 return 0;
2009}
2010
2011/* shutdown requests and disconnect from gadget */
2012static void
2013shutdown(struct udc *dev, struct usb_gadget_driver *driver)
2014__releases(dev->lock)
2015__acquires(dev->lock)
2016{
2017 int tmp;
2018
2019 if (dev->gadget.speed != USB_SPEED_UNKNOWN) {
2020 spin_unlock(&dev->lock);
2021 driver->disconnect(&dev->gadget);
2022 spin_lock(&dev->lock);
2023 }
2024
2025 /* empty queues and init hardware */
2026 udc_basic_init(dev);
2027 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
2028 empty_req_queue(&dev->ep[tmp]);
2029
2030 udc_setup_endpoints(dev);
2031}
2032
2033/* Called by gadget driver to unregister itself */
2034static int amd5536_stop(struct usb_gadget_driver *driver)
2035{
2036 struct udc *dev = udc;
2037 unsigned long flags;
2038 u32 tmp;
2039
2040 if (!dev)
2041 return -ENODEV;
2042 if (!driver || driver != dev->driver || !driver->unbind)
2043 return -EINVAL;
2044
2045 spin_lock_irqsave(&dev->lock, flags);
2046 udc_mask_unused_interrupts(dev);
2047 shutdown(dev, driver);
2048 spin_unlock_irqrestore(&dev->lock, flags);
2049
2050 driver->unbind(&dev->gadget);
2051 dev->gadget.dev.driver = NULL;
2052 dev->driver = NULL;
2053
2054 /* set SD */
2055 tmp = readl(&dev->regs->ctl);
2056 tmp |= AMD_BIT(UDC_DEVCTL_SD);
2057 writel(tmp, &dev->regs->ctl);
2058
2059
2060 DBG(dev, "%s: unregistered\n", driver->driver.name);
2061
2062 return 0;
2063}
2064
2065/* Clear pending NAK bits */
2066static void udc_process_cnak_queue(struct udc *dev)
2067{
2068 u32 tmp;
2069 u32 reg;
2070
2071 /* check epin's */
2072 DBG(dev, "CNAK pending queue processing\n");
2073 for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) {
2074 if (cnak_pending & (1 << tmp)) {
2075 DBG(dev, "CNAK pending for ep%d\n", tmp);
2076 /* clear NAK by writing CNAK */
2077 reg = readl(&dev->ep[tmp].regs->ctl);
2078 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2079 writel(reg, &dev->ep[tmp].regs->ctl);
2080 dev->ep[tmp].naking = 0;
2081 UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num);
2082 }
2083 }
2084 /* ... and ep0out */
2085 if (cnak_pending & (1 << UDC_EP0OUT_IX)) {
2086 DBG(dev, "CNAK pending for ep%d\n", UDC_EP0OUT_IX);
2087 /* clear NAK by writing CNAK */
2088 reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2089 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2090 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2091 dev->ep[UDC_EP0OUT_IX].naking = 0;
2092 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX],
2093 dev->ep[UDC_EP0OUT_IX].num);
2094 }
2095}
2096
2097/* Enabling RX DMA after setup packet */
2098static void udc_ep0_set_rde(struct udc *dev)
2099{
2100 if (use_dma) {
2101 /*
2102 * only enable RXDMA when no data endpoint enabled
2103 * or data is queued
2104 */
2105 if (!dev->data_ep_enabled || dev->data_ep_queued) {
2106 udc_set_rde(dev);
2107 } else {
2108 /*
2109 * setup timer for enabling RDE (to not enable
2110 * RXFIFO DMA for data endpoints to early)
2111 */
2112 if (set_rde != 0 && !timer_pending(&udc_timer)) {
2113 udc_timer.expires =
2114 jiffies + HZ/UDC_RDE_TIMER_DIV;
2115 set_rde = 1;
2116 if (!stop_timer) {
2117 add_timer(&udc_timer);
2118 }
2119 }
2120 }
2121 }
2122}
2123
2124
2125/* Interrupt handler for data OUT traffic */
2126static irqreturn_t udc_data_out_isr(struct udc *dev, int ep_ix)
2127{
2128 irqreturn_t ret_val = IRQ_NONE;
2129 u32 tmp;
2130 struct udc_ep *ep;
2131 struct udc_request *req;
2132 unsigned int count;
2133 struct udc_data_dma *td = NULL;
2134 unsigned dma_done;
2135
2136 VDBG(dev, "ep%d irq\n", ep_ix);
2137 ep = &dev->ep[ep_ix];
2138
2139 tmp = readl(&ep->regs->sts);
2140 if (use_dma) {
2141 /* BNA event ? */
2142 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2143 DBG(dev, "BNA ep%dout occurred - DESPTR = %x \n",
2144 ep->num, readl(&ep->regs->desptr));
2145 /* clear BNA */
2146 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts);
2147 if (!ep->cancel_transfer)
2148 ep->bna_occurred = 1;
2149 else
2150 ep->cancel_transfer = 0;
2151 ret_val = IRQ_HANDLED;
2152 goto finished;
2153 }
2154 }
2155 /* HE event ? */
2156 if (tmp & AMD_BIT(UDC_EPSTS_HE)) {
2157 dev_err(&dev->pdev->dev, "HE ep%dout occurred\n", ep->num);
2158
2159 /* clear HE */
2160 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2161 ret_val = IRQ_HANDLED;
2162 goto finished;
2163 }
2164
2165 if (!list_empty(&ep->queue)) {
2166
2167 /* next request */
2168 req = list_entry(ep->queue.next,
2169 struct udc_request, queue);
2170 } else {
2171 req = NULL;
2172 udc_rxfifo_pending = 1;
2173 }
2174 VDBG(dev, "req = %p\n", req);
2175 /* fifo mode */
2176 if (!use_dma) {
2177
2178 /* read fifo */
2179 if (req && udc_rxfifo_read(ep, req)) {
2180 ret_val = IRQ_HANDLED;
2181
2182 /* finish */
2183 complete_req(ep, req, 0);
2184 /* next request */
2185 if (!list_empty(&ep->queue) && !ep->halted) {
2186 req = list_entry(ep->queue.next,
2187 struct udc_request, queue);
2188 } else
2189 req = NULL;
2190 }
2191
2192 /* DMA */
2193 } else if (!ep->cancel_transfer && req != NULL) {
2194 ret_val = IRQ_HANDLED;
2195
2196 /* check for DMA done */
2197 if (!use_dma_ppb) {
2198 dma_done = AMD_GETBITS(req->td_data->status,
2199 UDC_DMA_OUT_STS_BS);
2200 /* packet per buffer mode - rx bytes */
2201 } else {
2202 /*
2203 * if BNA occurred then recover desc. from
2204 * BNA dummy desc.
2205 */
2206 if (ep->bna_occurred) {
2207 VDBG(dev, "Recover desc. from BNA dummy\n");
2208 memcpy(req->td_data, ep->bna_dummy_req->td_data,
2209 sizeof(struct udc_data_dma));
2210 ep->bna_occurred = 0;
2211 udc_init_bna_dummy(ep->req);
2212 }
2213 td = udc_get_last_dma_desc(req);
2214 dma_done = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_BS);
2215 }
2216 if (dma_done == UDC_DMA_OUT_STS_BS_DMA_DONE) {
2217 /* buffer fill mode - rx bytes */
2218 if (!use_dma_ppb) {
2219 /* received number bytes */
2220 count = AMD_GETBITS(req->td_data->status,
2221 UDC_DMA_OUT_STS_RXBYTES);
2222 VDBG(dev, "rx bytes=%u\n", count);
2223 /* packet per buffer mode - rx bytes */
2224 } else {
2225 VDBG(dev, "req->td_data=%p\n", req->td_data);
2226 VDBG(dev, "last desc = %p\n", td);
2227 /* received number bytes */
2228 if (use_dma_ppb_du) {
2229 /* every desc. counts bytes */
2230 count = udc_get_ppbdu_rxbytes(req);
2231 } else {
2232 /* last desc. counts bytes */
2233 count = AMD_GETBITS(td->status,
2234 UDC_DMA_OUT_STS_RXBYTES);
2235 if (!count && req->req.length
2236 == UDC_DMA_MAXPACKET) {
2237 /*
2238 * on 64k packets the RXBYTES
2239 * field is zero
2240 */
2241 count = UDC_DMA_MAXPACKET;
2242 }
2243 }
2244 VDBG(dev, "last desc rx bytes=%u\n", count);
2245 }
2246
2247 tmp = req->req.length - req->req.actual;
2248 if (count > tmp) {
2249 if ((tmp % ep->ep.maxpacket) != 0) {
2250 DBG(dev, "%s: rx %db, space=%db\n",
2251 ep->ep.name, count, tmp);
2252 req->req.status = -EOVERFLOW;
2253 }
2254 count = tmp;
2255 }
2256 req->req.actual += count;
2257 req->dma_going = 0;
2258 /* complete request */
2259 complete_req(ep, req, 0);
2260
2261 /* next request */
2262 if (!list_empty(&ep->queue) && !ep->halted) {
2263 req = list_entry(ep->queue.next,
2264 struct udc_request,
2265 queue);
2266 /*
2267 * DMA may be already started by udc_queue()
2268 * called by gadget drivers completion
2269 * routine. This happens when queue
2270 * holds one request only.
2271 */
2272 if (req->dma_going == 0) {
2273 /* next dma */
2274 if (prep_dma(ep, req, GFP_ATOMIC) != 0)
2275 goto finished;
2276 /* write desc pointer */
2277 writel(req->td_phys,
2278 &ep->regs->desptr);
2279 req->dma_going = 1;
2280 /* enable DMA */
2281 udc_set_rde(dev);
2282 }
2283 } else {
2284 /*
2285 * implant BNA dummy descriptor to allow
2286 * RXFIFO opening by RDE
2287 */
2288 if (ep->bna_dummy_req) {
2289 /* write desc pointer */
2290 writel(ep->bna_dummy_req->td_phys,
2291 &ep->regs->desptr);
2292 ep->bna_occurred = 0;
2293 }
2294
2295 /*
2296 * schedule timer for setting RDE if queue
2297 * remains empty to allow ep0 packets pass
2298 * through
2299 */
2300 if (set_rde != 0
2301 && !timer_pending(&udc_timer)) {
2302 udc_timer.expires =
2303 jiffies
2304 + HZ*UDC_RDE_TIMER_SECONDS;
2305 set_rde = 1;
2306 if (!stop_timer) {
2307 add_timer(&udc_timer);
2308 }
2309 }
2310 if (ep->num != UDC_EP0OUT_IX)
2311 dev->data_ep_queued = 0;
2312 }
2313
2314 } else {
2315 /*
2316 * RX DMA must be reenabled for each desc in PPBDU mode
2317 * and must be enabled for PPBNDU mode in case of BNA
2318 */
2319 udc_set_rde(dev);
2320 }
2321
2322 } else if (ep->cancel_transfer) {
2323 ret_val = IRQ_HANDLED;
2324 ep->cancel_transfer = 0;
2325 }
2326
2327 /* check pending CNAKS */
2328 if (cnak_pending) {
2329 /* CNAk processing when rxfifo empty only */
2330 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
2331 udc_process_cnak_queue(dev);
2332 }
2333 }
2334
2335 /* clear OUT bits in ep status */
2336 writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts);
2337finished:
2338 return ret_val;
2339}
2340
2341/* Interrupt handler for data IN traffic */
2342static irqreturn_t udc_data_in_isr(struct udc *dev, int ep_ix)
2343{
2344 irqreturn_t ret_val = IRQ_NONE;
2345 u32 tmp;
2346 u32 epsts;
2347 struct udc_ep *ep;
2348 struct udc_request *req;
2349 struct udc_data_dma *td;
2350 unsigned dma_done;
2351 unsigned len;
2352
2353 ep = &dev->ep[ep_ix];
2354
2355 epsts = readl(&ep->regs->sts);
2356 if (use_dma) {
2357 /* BNA ? */
2358 if (epsts & AMD_BIT(UDC_EPSTS_BNA)) {
2359 dev_err(&dev->pdev->dev,
2360 "BNA ep%din occurred - DESPTR = %08lx \n",
2361 ep->num,
2362 (unsigned long) readl(&ep->regs->desptr));
2363
2364 /* clear BNA */
2365 writel(epsts, &ep->regs->sts);
2366 ret_val = IRQ_HANDLED;
2367 goto finished;
2368 }
2369 }
2370 /* HE event ? */
2371 if (epsts & AMD_BIT(UDC_EPSTS_HE)) {
2372 dev_err(&dev->pdev->dev,
2373 "HE ep%dn occurred - DESPTR = %08lx \n",
2374 ep->num, (unsigned long) readl(&ep->regs->desptr));
2375
2376 /* clear HE */
2377 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2378 ret_val = IRQ_HANDLED;
2379 goto finished;
2380 }
2381
2382 /* DMA completion */
2383 if (epsts & AMD_BIT(UDC_EPSTS_TDC)) {
2384 VDBG(dev, "TDC set- completion\n");
2385 ret_val = IRQ_HANDLED;
2386 if (!ep->cancel_transfer && !list_empty(&ep->queue)) {
2387 req = list_entry(ep->queue.next,
2388 struct udc_request, queue);
2389 /*
2390 * length bytes transferred
2391 * check dma done of last desc. in PPBDU mode
2392 */
2393 if (use_dma_ppb_du) {
2394 td = udc_get_last_dma_desc(req);
2395 if (td) {
2396 dma_done =
2397 AMD_GETBITS(td->status,
2398 UDC_DMA_IN_STS_BS);
2399 /* don't care DMA done */
2400 req->req.actual = req->req.length;
2401 }
2402 } else {
2403 /* assume all bytes transferred */
2404 req->req.actual = req->req.length;
2405 }
2406
2407 if (req->req.actual == req->req.length) {
2408 /* complete req */
2409 complete_req(ep, req, 0);
2410 req->dma_going = 0;
2411 /* further request available ? */
2412 if (list_empty(&ep->queue)) {
2413 /* disable interrupt */
2414 tmp = readl(&dev->regs->ep_irqmsk);
2415 tmp |= AMD_BIT(ep->num);
2416 writel(tmp, &dev->regs->ep_irqmsk);
2417 }
2418 }
2419 }
2420 ep->cancel_transfer = 0;
2421
2422 }
2423 /*
2424 * status reg has IN bit set and TDC not set (if TDC was handled,
2425 * IN must not be handled (UDC defect) ?
2426 */
2427 if ((epsts & AMD_BIT(UDC_EPSTS_IN))
2428 && !(epsts & AMD_BIT(UDC_EPSTS_TDC))) {
2429 ret_val = IRQ_HANDLED;
2430 if (!list_empty(&ep->queue)) {
2431 /* next request */
2432 req = list_entry(ep->queue.next,
2433 struct udc_request, queue);
2434 /* FIFO mode */
2435 if (!use_dma) {
2436 /* write fifo */
2437 udc_txfifo_write(ep, &req->req);
2438 len = req->req.length - req->req.actual;
2439 if (len > ep->ep.maxpacket)
2440 len = ep->ep.maxpacket;
2441 req->req.actual += len;
2442 if (req->req.actual == req->req.length
2443 || (len != ep->ep.maxpacket)) {
2444 /* complete req */
2445 complete_req(ep, req, 0);
2446 }
2447 /* DMA */
2448 } else if (req && !req->dma_going) {
2449 VDBG(dev, "IN DMA : req=%p req->td_data=%p\n",
2450 req, req->td_data);
2451 if (req->td_data) {
2452
2453 req->dma_going = 1;
2454
2455 /*
2456 * unset L bit of first desc.
2457 * for chain
2458 */
2459 if (use_dma_ppb && req->req.length >
2460 ep->ep.maxpacket) {
2461 req->td_data->status &=
2462 AMD_CLEAR_BIT(
2463 UDC_DMA_IN_STS_L);
2464 }
2465
2466 /* write desc pointer */
2467 writel(req->td_phys, &ep->regs->desptr);
2468
2469 /* set HOST READY */
2470 req->td_data->status =
2471 AMD_ADDBITS(
2472 req->td_data->status,
2473 UDC_DMA_IN_STS_BS_HOST_READY,
2474 UDC_DMA_IN_STS_BS);
2475
2476 /* set poll demand bit */
2477 tmp = readl(&ep->regs->ctl);
2478 tmp |= AMD_BIT(UDC_EPCTL_P);
2479 writel(tmp, &ep->regs->ctl);
2480 }
2481 }
2482
2483 } else if (!use_dma && ep->in) {
2484 /* disable interrupt */
2485 tmp = readl(
2486 &dev->regs->ep_irqmsk);
2487 tmp |= AMD_BIT(ep->num);
2488 writel(tmp,
2489 &dev->regs->ep_irqmsk);
2490 }
2491 }
2492 /* clear status bits */
2493 writel(epsts, &ep->regs->sts);
2494
2495finished:
2496 return ret_val;
2497
2498}
2499
2500/* Interrupt handler for Control OUT traffic */
2501static irqreturn_t udc_control_out_isr(struct udc *dev)
2502__releases(dev->lock)
2503__acquires(dev->lock)
2504{
2505 irqreturn_t ret_val = IRQ_NONE;
2506 u32 tmp;
2507 int setup_supported;
2508 u32 count;
2509 int set = 0;
2510 struct udc_ep *ep;
2511 struct udc_ep *ep_tmp;
2512
2513 ep = &dev->ep[UDC_EP0OUT_IX];
2514
2515 /* clear irq */
2516 writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts);
2517
2518 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2519 /* check BNA and clear if set */
2520 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2521 VDBG(dev, "ep0: BNA set\n");
2522 writel(AMD_BIT(UDC_EPSTS_BNA),
2523 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2524 ep->bna_occurred = 1;
2525 ret_val = IRQ_HANDLED;
2526 goto finished;
2527 }
2528
2529 /* type of data: SETUP or DATA 0 bytes */
2530 tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT);
2531 VDBG(dev, "data_typ = %x\n", tmp);
2532
2533 /* setup data */
2534 if (tmp == UDC_EPSTS_OUT_SETUP) {
2535 ret_val = IRQ_HANDLED;
2536
2537 ep->dev->stall_ep0in = 0;
2538 dev->waiting_zlp_ack_ep0in = 0;
2539
2540 /* set NAK for EP0_IN */
2541 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2542 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
2543 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2544 dev->ep[UDC_EP0IN_IX].naking = 1;
2545 /* get setup data */
2546 if (use_dma) {
2547
2548 /* clear OUT bits in ep status */
2549 writel(UDC_EPSTS_OUT_CLEAR,
2550 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2551
2552 setup_data.data[0] =
2553 dev->ep[UDC_EP0OUT_IX].td_stp->data12;
2554 setup_data.data[1] =
2555 dev->ep[UDC_EP0OUT_IX].td_stp->data34;
2556 /* set HOST READY */
2557 dev->ep[UDC_EP0OUT_IX].td_stp->status =
2558 UDC_DMA_STP_STS_BS_HOST_READY;
2559 } else {
2560 /* read fifo */
2561 udc_rxfifo_read_dwords(dev, setup_data.data, 2);
2562 }
2563
2564 /* determine direction of control data */
2565 if ((setup_data.request.bRequestType & USB_DIR_IN) != 0) {
2566 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
2567 /* enable RDE */
2568 udc_ep0_set_rde(dev);
2569 set = 0;
2570 } else {
2571 dev->gadget.ep0 = &dev->ep[UDC_EP0OUT_IX].ep;
2572 /*
2573 * implant BNA dummy descriptor to allow RXFIFO opening
2574 * by RDE
2575 */
2576 if (ep->bna_dummy_req) {
2577 /* write desc pointer */
2578 writel(ep->bna_dummy_req->td_phys,
2579 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2580 ep->bna_occurred = 0;
2581 }
2582
2583 set = 1;
2584 dev->ep[UDC_EP0OUT_IX].naking = 1;
2585 /*
2586 * setup timer for enabling RDE (to not enable
2587 * RXFIFO DMA for data to early)
2588 */
2589 set_rde = 1;
2590 if (!timer_pending(&udc_timer)) {
2591 udc_timer.expires = jiffies +
2592 HZ/UDC_RDE_TIMER_DIV;
2593 if (!stop_timer) {
2594 add_timer(&udc_timer);
2595 }
2596 }
2597 }
2598
2599 /*
2600 * mass storage reset must be processed here because
2601 * next packet may be a CLEAR_FEATURE HALT which would not
2602 * clear the stall bit when no STALL handshake was received
2603 * before (autostall can cause this)
2604 */
2605 if (setup_data.data[0] == UDC_MSCRES_DWORD0
2606 && setup_data.data[1] == UDC_MSCRES_DWORD1) {
2607 DBG(dev, "MSC Reset\n");
2608 /*
2609 * clear stall bits
2610 * only one IN and OUT endpoints are handled
2611 */
2612 ep_tmp = &udc->ep[UDC_EPIN_IX];
2613 udc_set_halt(&ep_tmp->ep, 0);
2614 ep_tmp = &udc->ep[UDC_EPOUT_IX];
2615 udc_set_halt(&ep_tmp->ep, 0);
2616 }
2617
2618 /* call gadget with setup data received */
2619 spin_unlock(&dev->lock);
2620 setup_supported = dev->driver->setup(&dev->gadget,
2621 &setup_data.request);
2622 spin_lock(&dev->lock);
2623
2624 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2625 /* ep0 in returns data (not zlp) on IN phase */
2626 if (setup_supported >= 0 && setup_supported <
2627 UDC_EP0IN_MAXPACKET) {
2628 /* clear NAK by writing CNAK in EP0_IN */
2629 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2630 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2631 dev->ep[UDC_EP0IN_IX].naking = 0;
2632 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
2633
2634 /* if unsupported request then stall */
2635 } else if (setup_supported < 0) {
2636 tmp |= AMD_BIT(UDC_EPCTL_S);
2637 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2638 } else
2639 dev->waiting_zlp_ack_ep0in = 1;
2640
2641
2642 /* clear NAK by writing CNAK in EP0_OUT */
2643 if (!set) {
2644 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2645 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2646 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2647 dev->ep[UDC_EP0OUT_IX].naking = 0;
2648 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
2649 }
2650
2651 if (!use_dma) {
2652 /* clear OUT bits in ep status */
2653 writel(UDC_EPSTS_OUT_CLEAR,
2654 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2655 }
2656
2657 /* data packet 0 bytes */
2658 } else if (tmp == UDC_EPSTS_OUT_DATA) {
2659 /* clear OUT bits in ep status */
2660 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
2661
2662 /* get setup data: only 0 packet */
2663 if (use_dma) {
2664 /* no req if 0 packet, just reactivate */
2665 if (list_empty(&dev->ep[UDC_EP0OUT_IX].queue)) {
2666 VDBG(dev, "ZLP\n");
2667
2668 /* set HOST READY */
2669 dev->ep[UDC_EP0OUT_IX].td->status =
2670 AMD_ADDBITS(
2671 dev->ep[UDC_EP0OUT_IX].td->status,
2672 UDC_DMA_OUT_STS_BS_HOST_READY,
2673 UDC_DMA_OUT_STS_BS);
2674 /* enable RDE */
2675 udc_ep0_set_rde(dev);
2676 ret_val = IRQ_HANDLED;
2677
2678 } else {
2679 /* control write */
2680 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2681 /* re-program desc. pointer for possible ZLPs */
2682 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
2683 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2684 /* enable RDE */
2685 udc_ep0_set_rde(dev);
2686 }
2687 } else {
2688
2689 /* received number bytes */
2690 count = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2691 count = AMD_GETBITS(count, UDC_EPSTS_RX_PKT_SIZE);
2692 /* out data for fifo mode not working */
2693 count = 0;
2694
2695 /* 0 packet or real data ? */
2696 if (count != 0) {
2697 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2698 } else {
2699 /* dummy read confirm */
2700 readl(&dev->ep[UDC_EP0OUT_IX].regs->confirm);
2701 ret_val = IRQ_HANDLED;
2702 }
2703 }
2704 }
2705
2706 /* check pending CNAKS */
2707 if (cnak_pending) {
2708 /* CNAk processing when rxfifo empty only */
2709 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
2710 udc_process_cnak_queue(dev);
2711 }
2712 }
2713
2714finished:
2715 return ret_val;
2716}
2717
2718/* Interrupt handler for Control IN traffic */
2719static irqreturn_t udc_control_in_isr(struct udc *dev)
2720{
2721 irqreturn_t ret_val = IRQ_NONE;
2722 u32 tmp;
2723 struct udc_ep *ep;
2724 struct udc_request *req;
2725 unsigned len;
2726
2727 ep = &dev->ep[UDC_EP0IN_IX];
2728
2729 /* clear irq */
2730 writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts);
2731
2732 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);
2733 /* DMA completion */
2734 if (tmp & AMD_BIT(UDC_EPSTS_TDC)) {
2735 VDBG(dev, "isr: TDC clear \n");
2736 ret_val = IRQ_HANDLED;
2737
2738 /* clear TDC bit */
2739 writel(AMD_BIT(UDC_EPSTS_TDC),
2740 &dev->ep[UDC_EP0IN_IX].regs->sts);
2741
2742 /* status reg has IN bit set ? */
2743 } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) {
2744 ret_val = IRQ_HANDLED;
2745
2746 if (ep->dma) {
2747 /* clear IN bit */
2748 writel(AMD_BIT(UDC_EPSTS_IN),
2749 &dev->ep[UDC_EP0IN_IX].regs->sts);
2750 }
2751 if (dev->stall_ep0in) {
2752 DBG(dev, "stall ep0in\n");
2753 /* halt ep0in */
2754 tmp = readl(&ep->regs->ctl);
2755 tmp |= AMD_BIT(UDC_EPCTL_S);
2756 writel(tmp, &ep->regs->ctl);
2757 } else {
2758 if (!list_empty(&ep->queue)) {
2759 /* next request */
2760 req = list_entry(ep->queue.next,
2761 struct udc_request, queue);
2762
2763 if (ep->dma) {
2764 /* write desc pointer */
2765 writel(req->td_phys, &ep->regs->desptr);
2766 /* set HOST READY */
2767 req->td_data->status =
2768 AMD_ADDBITS(
2769 req->td_data->status,
2770 UDC_DMA_STP_STS_BS_HOST_READY,
2771 UDC_DMA_STP_STS_BS);
2772
2773 /* set poll demand bit */
2774 tmp =
2775 readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2776 tmp |= AMD_BIT(UDC_EPCTL_P);
2777 writel(tmp,
2778 &dev->ep[UDC_EP0IN_IX].regs->ctl);
2779
2780 /* all bytes will be transferred */
2781 req->req.actual = req->req.length;
2782
2783 /* complete req */
2784 complete_req(ep, req, 0);
2785
2786 } else {
2787 /* write fifo */
2788 udc_txfifo_write(ep, &req->req);
2789
2790 /* lengh bytes transferred */
2791 len = req->req.length - req->req.actual;
2792 if (len > ep->ep.maxpacket)
2793 len = ep->ep.maxpacket;
2794
2795 req->req.actual += len;
2796 if (req->req.actual == req->req.length
2797 || (len != ep->ep.maxpacket)) {
2798 /* complete req */
2799 complete_req(ep, req, 0);
2800 }
2801 }
2802
2803 }
2804 }
2805 ep->halted = 0;
2806 dev->stall_ep0in = 0;
2807 if (!ep->dma) {
2808 /* clear IN bit */
2809 writel(AMD_BIT(UDC_EPSTS_IN),
2810 &dev->ep[UDC_EP0IN_IX].regs->sts);
2811 }
2812 }
2813
2814 return ret_val;
2815}
2816
2817
2818/* Interrupt handler for global device events */
2819static irqreturn_t udc_dev_isr(struct udc *dev, u32 dev_irq)
2820__releases(dev->lock)
2821__acquires(dev->lock)
2822{
2823 irqreturn_t ret_val = IRQ_NONE;
2824 u32 tmp;
2825 u32 cfg;
2826 struct udc_ep *ep;
2827 u16 i;
2828 u8 udc_csr_epix;
2829
2830 /* SET_CONFIG irq ? */
2831 if (dev_irq & AMD_BIT(UDC_DEVINT_SC)) {
2832 ret_val = IRQ_HANDLED;
2833
2834 /* read config value */
2835 tmp = readl(&dev->regs->sts);
2836 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG);
2837 DBG(dev, "SET_CONFIG interrupt: config=%d\n", cfg);
2838 dev->cur_config = cfg;
2839 dev->set_cfg_not_acked = 1;
2840
2841 /* make usb request for gadget driver */
2842 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2843 setup_data.request.bRequest = USB_REQ_SET_CONFIGURATION;
2844 setup_data.request.wValue = cpu_to_le16(dev->cur_config);
2845
2846 /* programm the NE registers */
2847 for (i = 0; i < UDC_EP_NUM; i++) {
2848 ep = &dev->ep[i];
2849 if (ep->in) {
2850
2851 /* ep ix in UDC CSR register space */
2852 udc_csr_epix = ep->num;
2853
2854
2855 /* OUT ep */
2856 } else {
2857 /* ep ix in UDC CSR register space */
2858 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2859 }
2860
2861 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2862 /* ep cfg */
2863 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config,
2864 UDC_CSR_NE_CFG);
2865 /* write reg */
2866 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2867
2868 /* clear stall bits */
2869 ep->halted = 0;
2870 tmp = readl(&ep->regs->ctl);
2871 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2872 writel(tmp, &ep->regs->ctl);
2873 }
2874 /* call gadget zero with setup data received */
2875 spin_unlock(&dev->lock);
2876 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2877 spin_lock(&dev->lock);
2878
2879 } /* SET_INTERFACE ? */
2880 if (dev_irq & AMD_BIT(UDC_DEVINT_SI)) {
2881 ret_val = IRQ_HANDLED;
2882
2883 dev->set_cfg_not_acked = 1;
2884 /* read interface and alt setting values */
2885 tmp = readl(&dev->regs->sts);
2886 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT);
2887 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF);
2888
2889 /* make usb request for gadget driver */
2890 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2891 setup_data.request.bRequest = USB_REQ_SET_INTERFACE;
2892 setup_data.request.bRequestType = USB_RECIP_INTERFACE;
2893 setup_data.request.wValue = cpu_to_le16(dev->cur_alt);
2894 setup_data.request.wIndex = cpu_to_le16(dev->cur_intf);
2895
2896 DBG(dev, "SET_INTERFACE interrupt: alt=%d intf=%d\n",
2897 dev->cur_alt, dev->cur_intf);
2898
2899 /* programm the NE registers */
2900 for (i = 0; i < UDC_EP_NUM; i++) {
2901 ep = &dev->ep[i];
2902 if (ep->in) {
2903
2904 /* ep ix in UDC CSR register space */
2905 udc_csr_epix = ep->num;
2906
2907
2908 /* OUT ep */
2909 } else {
2910 /* ep ix in UDC CSR register space */
2911 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2912 }
2913
2914 /* UDC CSR reg */
2915 /* set ep values */
2916 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2917 /* ep interface */
2918 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf,
2919 UDC_CSR_NE_INTF);
2920 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2921 /* ep alt */
2922 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt,
2923 UDC_CSR_NE_ALT);
2924 /* write reg */
2925 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2926
2927 /* clear stall bits */
2928 ep->halted = 0;
2929 tmp = readl(&ep->regs->ctl);
2930 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2931 writel(tmp, &ep->regs->ctl);
2932 }
2933
2934 /* call gadget zero with setup data received */
2935 spin_unlock(&dev->lock);
2936 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2937 spin_lock(&dev->lock);
2938
2939 } /* USB reset */
2940 if (dev_irq & AMD_BIT(UDC_DEVINT_UR)) {
2941 DBG(dev, "USB Reset interrupt\n");
2942 ret_val = IRQ_HANDLED;
2943
2944 /* allow soft reset when suspend occurs */
2945 soft_reset_occured = 0;
2946
2947 dev->waiting_zlp_ack_ep0in = 0;
2948 dev->set_cfg_not_acked = 0;
2949
2950 /* mask not needed interrupts */
2951 udc_mask_unused_interrupts(dev);
2952
2953 /* call gadget to resume and reset configs etc. */
2954 spin_unlock(&dev->lock);
2955 if (dev->sys_suspended && dev->driver->resume) {
2956 dev->driver->resume(&dev->gadget);
2957 dev->sys_suspended = 0;
2958 }
2959 dev->driver->disconnect(&dev->gadget);
2960 spin_lock(&dev->lock);
2961
2962 /* disable ep0 to empty req queue */
2963 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2964 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2965
2966 /* soft reset when rxfifo not empty */
2967 tmp = readl(&dev->regs->sts);
2968 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2969 && !soft_reset_after_usbreset_occured) {
2970 udc_soft_reset(dev);
2971 soft_reset_after_usbreset_occured++;
2972 }
2973
2974 /*
2975 * DMA reset to kill potential old DMA hw hang,
2976 * POLL bit is already reset by ep_init() through
2977 * disconnect()
2978 */
2979 DBG(dev, "DMA machine reset\n");
2980 tmp = readl(&dev->regs->cfg);
2981 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
2982 writel(tmp, &dev->regs->cfg);
2983
2984 /* put into initial config */
2985 udc_basic_init(dev);
2986
2987 /* enable device setup interrupts */
2988 udc_enable_dev_setup_interrupts(dev);
2989
2990 /* enable suspend interrupt */
2991 tmp = readl(&dev->regs->irqmsk);
2992 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US);
2993 writel(tmp, &dev->regs->irqmsk);
2994
2995 } /* USB suspend */
2996 if (dev_irq & AMD_BIT(UDC_DEVINT_US)) {
2997 DBG(dev, "USB Suspend interrupt\n");
2998 ret_val = IRQ_HANDLED;
2999 if (dev->driver->suspend) {
3000 spin_unlock(&dev->lock);
3001 dev->sys_suspended = 1;
3002 dev->driver->suspend(&dev->gadget);
3003 spin_lock(&dev->lock);
3004 }
3005 } /* new speed ? */
3006 if (dev_irq & AMD_BIT(UDC_DEVINT_ENUM)) {
3007 DBG(dev, "ENUM interrupt\n");
3008 ret_val = IRQ_HANDLED;
3009 soft_reset_after_usbreset_occured = 0;
3010
3011 /* disable ep0 to empty req queue */
3012 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
3013 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
3014
3015 /* link up all endpoints */
3016 udc_setup_endpoints(dev);
3017 if (dev->gadget.speed == USB_SPEED_HIGH) {
3018 dev_info(&dev->pdev->dev, "Connect: speed = %s\n",
3019 "high");
3020 } else if (dev->gadget.speed == USB_SPEED_FULL) {
3021 dev_info(&dev->pdev->dev, "Connect: speed = %s\n",
3022 "full");
3023 }
3024
3025 /* init ep 0 */
3026 activate_control_endpoints(dev);
3027
3028 /* enable ep0 interrupts */
3029 udc_enable_ep0_interrupts(dev);
3030 }
3031 /* session valid change interrupt */
3032 if (dev_irq & AMD_BIT(UDC_DEVINT_SVC)) {
3033 DBG(dev, "USB SVC interrupt\n");
3034 ret_val = IRQ_HANDLED;
3035
3036 /* check that session is not valid to detect disconnect */
3037 tmp = readl(&dev->regs->sts);
3038 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) {
3039 /* disable suspend interrupt */
3040 tmp = readl(&dev->regs->irqmsk);
3041 tmp |= AMD_BIT(UDC_DEVINT_US);
3042 writel(tmp, &dev->regs->irqmsk);
3043 DBG(dev, "USB Disconnect (session valid low)\n");
3044 /* cleanup on disconnect */
3045 usb_disconnect(udc);
3046 }
3047
3048 }
3049
3050 return ret_val;
3051}
3052
3053/* Interrupt Service Routine, see Linux Kernel Doc for parameters */
3054static irqreturn_t udc_irq(int irq, void *pdev)
3055{
3056 struct udc *dev = pdev;
3057 u32 reg;
3058 u16 i;
3059 u32 ep_irq;
3060 irqreturn_t ret_val = IRQ_NONE;
3061
3062 spin_lock(&dev->lock);
3063
3064 /* check for ep irq */
3065 reg = readl(&dev->regs->ep_irqsts);
3066 if (reg) {
3067 if (reg & AMD_BIT(UDC_EPINT_OUT_EP0))
3068 ret_val |= udc_control_out_isr(dev);
3069 if (reg & AMD_BIT(UDC_EPINT_IN_EP0))
3070 ret_val |= udc_control_in_isr(dev);
3071
3072 /*
3073 * data endpoint
3074 * iterate ep's
3075 */
3076 for (i = 1; i < UDC_EP_NUM; i++) {
3077 ep_irq = 1 << i;
3078 if (!(reg & ep_irq) || i == UDC_EPINT_OUT_EP0)
3079 continue;
3080
3081 /* clear irq status */
3082 writel(ep_irq, &dev->regs->ep_irqsts);
3083
3084 /* irq for out ep ? */
3085 if (i > UDC_EPIN_NUM)
3086 ret_val |= udc_data_out_isr(dev, i);
3087 else
3088 ret_val |= udc_data_in_isr(dev, i);
3089 }
3090
3091 }
3092
3093
3094 /* check for dev irq */
3095 reg = readl(&dev->regs->irqsts);
3096 if (reg) {
3097 /* clear irq */
3098 writel(reg, &dev->regs->irqsts);
3099 ret_val |= udc_dev_isr(dev, reg);
3100 }
3101
3102
3103 spin_unlock(&dev->lock);
3104 return ret_val;
3105}
3106
3107/* Tears down device */
3108static void gadget_release(struct device *pdev)
3109{
3110 struct amd5536udc *dev = dev_get_drvdata(pdev);
3111 kfree(dev);
3112}
3113
3114/* Cleanup on device remove */
3115static void udc_remove(struct udc *dev)
3116{
3117 /* remove timer */
3118 stop_timer++;
3119 if (timer_pending(&udc_timer))
3120 wait_for_completion(&on_exit);
3121 if (udc_timer.data)
3122 del_timer_sync(&udc_timer);
3123 /* remove pollstall timer */
3124 stop_pollstall_timer++;
3125 if (timer_pending(&udc_pollstall_timer))
3126 wait_for_completion(&on_pollstall_exit);
3127 if (udc_pollstall_timer.data)
3128 del_timer_sync(&udc_pollstall_timer);
3129 udc = NULL;
3130}
3131
3132/* Reset all pci context */
3133static void udc_pci_remove(struct pci_dev *pdev)
3134{
3135 struct udc *dev;
3136
3137 dev = pci_get_drvdata(pdev);
3138
3139 usb_del_gadget_udc(&udc->gadget);
3140 /* gadget driver must not be registered */
3141 BUG_ON(dev->driver != NULL);
3142
3143 /* dma pool cleanup */
3144 if (dev->data_requests)
3145 pci_pool_destroy(dev->data_requests);
3146
3147 if (dev->stp_requests) {
3148 /* cleanup DMA desc's for ep0in */
3149 pci_pool_free(dev->stp_requests,
3150 dev->ep[UDC_EP0OUT_IX].td_stp,
3151 dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3152 pci_pool_free(dev->stp_requests,
3153 dev->ep[UDC_EP0OUT_IX].td,
3154 dev->ep[UDC_EP0OUT_IX].td_phys);
3155
3156 pci_pool_destroy(dev->stp_requests);
3157 }
3158
3159 /* reset controller */
3160 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
3161 if (dev->irq_registered)
3162 free_irq(pdev->irq, dev);
3163 if (dev->regs)
3164 iounmap(dev->regs);
3165 if (dev->mem_region)
3166 release_mem_region(pci_resource_start(pdev, 0),
3167 pci_resource_len(pdev, 0));
3168 if (dev->active)
3169 pci_disable_device(pdev);
3170
3171 device_unregister(&dev->gadget.dev);
3172 pci_set_drvdata(pdev, NULL);
3173
3174 udc_remove(dev);
3175}
3176
3177/* create dma pools on init */
3178static int init_dma_pools(struct udc *dev)
3179{
3180 struct udc_stp_dma *td_stp;
3181 struct udc_data_dma *td_data;
3182 int retval;
3183
3184 /* consistent DMA mode setting ? */
3185 if (use_dma_ppb) {
3186 use_dma_bufferfill_mode = 0;
3187 } else {
3188 use_dma_ppb_du = 0;
3189 use_dma_bufferfill_mode = 1;
3190 }
3191
3192 /* DMA setup */
3193 dev->data_requests = dma_pool_create("data_requests", NULL,
3194 sizeof(struct udc_data_dma), 0, 0);
3195 if (!dev->data_requests) {
3196 DBG(dev, "can't get request data pool\n");
3197 retval = -ENOMEM;
3198 goto finished;
3199 }
3200
3201 /* EP0 in dma regs = dev control regs */
3202 dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;
3203
3204 /* dma desc for setup data */
3205 dev->stp_requests = dma_pool_create("setup requests", NULL,
3206 sizeof(struct udc_stp_dma), 0, 0);
3207 if (!dev->stp_requests) {
3208 DBG(dev, "can't get stp request pool\n");
3209 retval = -ENOMEM;
3210 goto finished;
3211 }
3212 /* setup */
3213 td_stp = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3214 &dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3215 if (td_stp == NULL) {
3216 retval = -ENOMEM;
3217 goto finished;
3218 }
3219 dev->ep[UDC_EP0OUT_IX].td_stp = td_stp;
3220
3221 /* data: 0 packets !? */
3222 td_data = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3223 &dev->ep[UDC_EP0OUT_IX].td_phys);
3224 if (td_data == NULL) {
3225 retval = -ENOMEM;
3226 goto finished;
3227 }
3228 dev->ep[UDC_EP0OUT_IX].td = td_data;
3229 return 0;
3230
3231finished:
3232 return retval;
3233}
3234
3235/* Called by pci bus driver to init pci context */
3236static int udc_pci_probe(
3237 struct pci_dev *pdev,
3238 const struct pci_device_id *id
3239)
3240{
3241 struct udc *dev;
3242 unsigned long resource;
3243 unsigned long len;
3244 int retval = 0;
3245
3246 /* one udc only */
3247 if (udc) {
3248 dev_dbg(&pdev->dev, "already probed\n");
3249 return -EBUSY;
3250 }
3251
3252 /* init */
3253 dev = kzalloc(sizeof(struct udc), GFP_KERNEL);
3254 if (!dev) {
3255 retval = -ENOMEM;
3256 goto finished;
3257 }
3258
3259 /* pci setup */
3260 if (pci_enable_device(pdev) < 0) {
3261 kfree(dev);
3262 dev = NULL;
3263 retval = -ENODEV;
3264 goto finished;
3265 }
3266 dev->active = 1;
3267
3268 /* PCI resource allocation */
3269 resource = pci_resource_start(pdev, 0);
3270 len = pci_resource_len(pdev, 0);
3271
3272 if (!request_mem_region(resource, len, name)) {
3273 dev_dbg(&pdev->dev, "pci device used already\n");
3274 kfree(dev);
3275 dev = NULL;
3276 retval = -EBUSY;
3277 goto finished;
3278 }
3279 dev->mem_region = 1;
3280
3281 dev->virt_addr = ioremap_nocache(resource, len);
3282 if (dev->virt_addr == NULL) {
3283 dev_dbg(&pdev->dev, "start address cannot be mapped\n");
3284 kfree(dev);
3285 dev = NULL;
3286 retval = -EFAULT;
3287 goto finished;
3288 }
3289
3290 if (!pdev->irq) {
3291 dev_err(&dev->pdev->dev, "irq not set\n");
3292 kfree(dev);
3293 dev = NULL;
3294 retval = -ENODEV;
3295 goto finished;
3296 }
3297
3298 spin_lock_init(&dev->lock);
3299 /* udc csr registers base */
3300 dev->csr = dev->virt_addr + UDC_CSR_ADDR;
3301 /* dev registers base */
3302 dev->regs = dev->virt_addr + UDC_DEVCFG_ADDR;
3303 /* ep registers base */
3304 dev->ep_regs = dev->virt_addr + UDC_EPREGS_ADDR;
3305 /* fifo's base */
3306 dev->rxfifo = (u32 __iomem *)(dev->virt_addr + UDC_RXFIFO_ADDR);
3307 dev->txfifo = (u32 __iomem *)(dev->virt_addr + UDC_TXFIFO_ADDR);
3308
3309 if (request_irq(pdev->irq, udc_irq, IRQF_SHARED, name, dev) != 0) {
3310 dev_dbg(&dev->pdev->dev, "request_irq(%d) fail\n", pdev->irq);
3311 kfree(dev);
3312 dev = NULL;
3313 retval = -EBUSY;
3314 goto finished;
3315 }
3316 dev->irq_registered = 1;
3317
3318 pci_set_drvdata(pdev, dev);
3319
3320 /* chip revision for Hs AMD5536 */
3321 dev->chiprev = pdev->revision;
3322
3323 pci_set_master(pdev);
3324 pci_try_set_mwi(pdev);
3325
3326 /* init dma pools */
3327 if (use_dma) {
3328 retval = init_dma_pools(dev);
3329 if (retval != 0)
3330 goto finished;
3331 }
3332
3333 dev->phys_addr = resource;
3334 dev->irq = pdev->irq;
3335 dev->pdev = pdev;
3336 dev->gadget.dev.parent = &pdev->dev;
3337 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
3338
3339 /* general probing */
3340 if (udc_probe(dev) == 0)
3341 return 0;
3342
3343finished:
3344 if (dev)
3345 udc_pci_remove(pdev);
3346 return retval;
3347}
3348
3349/* general probe */
3350static int udc_probe(struct udc *dev)
3351{
3352 char tmp[128];
3353 u32 reg;
3354 int retval;
3355
3356 /* mark timer as not initialized */
3357 udc_timer.data = 0;
3358 udc_pollstall_timer.data = 0;
3359
3360 /* device struct setup */
3361 dev->gadget.ops = &udc_ops;
3362
3363 dev_set_name(&dev->gadget.dev, "gadget");
3364 dev->gadget.dev.release = gadget_release;
3365 dev->gadget.name = name;
3366 dev->gadget.is_dualspeed = 1;
3367
3368 /* init registers, interrupts, ... */
3369 startup_registers(dev);
3370
3371 dev_info(&dev->pdev->dev, "%s\n", mod_desc);
3372
3373 snprintf(tmp, sizeof tmp, "%d", dev->irq);
3374 dev_info(&dev->pdev->dev,
3375 "irq %s, pci mem %08lx, chip rev %02x(Geode5536 %s)\n",
3376 tmp, dev->phys_addr, dev->chiprev,
3377 (dev->chiprev == UDC_HSA0_REV) ? "A0" : "B1");
3378 strcpy(tmp, UDC_DRIVER_VERSION_STRING);
3379 if (dev->chiprev == UDC_HSA0_REV) {
3380 dev_err(&dev->pdev->dev, "chip revision is A0; too old\n");
3381 retval = -ENODEV;
3382 goto finished;
3383 }
3384 dev_info(&dev->pdev->dev,
3385 "driver version: %s(for Geode5536 B1)\n", tmp);
3386 udc = dev;
3387
3388 retval = usb_add_gadget_udc(&udc->pdev->dev, &dev->gadget);
3389 if (retval)
3390 goto finished;
3391
3392 retval = device_register(&dev->gadget.dev);
3393 if (retval) {
3394 usb_del_gadget_udc(&dev->gadget);
3395 put_device(&dev->gadget.dev);
3396 goto finished;
3397 }
3398
3399 /* timer init */
3400 init_timer(&udc_timer);
3401 udc_timer.function = udc_timer_function;
3402 udc_timer.data = 1;
3403 /* timer pollstall init */
3404 init_timer(&udc_pollstall_timer);
3405 udc_pollstall_timer.function = udc_pollstall_timer_function;
3406 udc_pollstall_timer.data = 1;
3407
3408 /* set SD */
3409 reg = readl(&dev->regs->ctl);
3410 reg |= AMD_BIT(UDC_DEVCTL_SD);
3411 writel(reg, &dev->regs->ctl);
3412
3413 /* print dev register info */
3414 print_regs(dev);
3415
3416 return 0;
3417
3418finished:
3419 return retval;
3420}
3421
3422/* Initiates a remote wakeup */
3423static int udc_remote_wakeup(struct udc *dev)
3424{
3425 unsigned long flags;
3426 u32 tmp;
3427
3428 DBG(dev, "UDC initiates remote wakeup\n");
3429
3430 spin_lock_irqsave(&dev->lock, flags);
3431
3432 tmp = readl(&dev->regs->ctl);
3433 tmp |= AMD_BIT(UDC_DEVCTL_RES);
3434 writel(tmp, &dev->regs->ctl);
3435 tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES);
3436 writel(tmp, &dev->regs->ctl);
3437
3438 spin_unlock_irqrestore(&dev->lock, flags);
3439 return 0;
3440}
3441
3442/* PCI device parameters */
3443static const struct pci_device_id pci_id[] = {
3444 {
3445 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x2096),
3446 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3447 .class_mask = 0xffffffff,
3448 },
3449 {},
3450};
3451MODULE_DEVICE_TABLE(pci, pci_id);
3452
3453/* PCI functions */
3454static struct pci_driver udc_pci_driver = {
3455 .name = (char *) name,
3456 .id_table = pci_id,
3457 .probe = udc_pci_probe,
3458 .remove = udc_pci_remove,
3459};
3460
3461/* Inits driver */
3462static int __init init(void)
3463{
3464 return pci_register_driver(&udc_pci_driver);
3465}
3466module_init(init);
3467
3468/* Cleans driver */
3469static void __exit cleanup(void)
3470{
3471 pci_unregister_driver(&udc_pci_driver);
3472}
3473module_exit(cleanup);
3474
3475MODULE_DESCRIPTION(UDC_MOD_DESCRIPTION);
3476MODULE_AUTHOR("Thomas Dahlmann");
3477MODULE_LICENSE("GPL");
3478