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1/*
2 * Device driver for Microgate SyncLink GT serial adapters.
3 *
4 * written by Paul Fulghum for Microgate Corporation
5 * paulkf@microgate.com
6 *
7 * Microgate and SyncLink are trademarks of Microgate Corporation
8 *
9 * This code is released under the GNU General Public License (GPL)
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
13 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
14 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
15 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
18 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
19 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
21 * OF THE POSSIBILITY OF SUCH DAMAGE.
22 */
23
24/*
25 * DEBUG OUTPUT DEFINITIONS
26 *
27 * uncomment lines below to enable specific types of debug output
28 *
29 * DBGINFO information - most verbose output
30 * DBGERR serious errors
31 * DBGBH bottom half service routine debugging
32 * DBGISR interrupt service routine debugging
33 * DBGDATA output receive and transmit data
34 * DBGTBUF output transmit DMA buffers and registers
35 * DBGRBUF output receive DMA buffers and registers
36 */
37
38#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
39#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
40#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
41#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
42#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
43/*#define DBGTBUF(info) dump_tbufs(info)*/
44/*#define DBGRBUF(info) dump_rbufs(info)*/
45
46
47#include <linux/module.h>
48#include <linux/errno.h>
49#include <linux/signal.h>
50#include <linux/sched.h>
51#include <linux/timer.h>
52#include <linux/interrupt.h>
53#include <linux/pci.h>
54#include <linux/tty.h>
55#include <linux/tty_flip.h>
56#include <linux/serial.h>
57#include <linux/major.h>
58#include <linux/string.h>
59#include <linux/fcntl.h>
60#include <linux/ptrace.h>
61#include <linux/ioport.h>
62#include <linux/mm.h>
63#include <linux/seq_file.h>
64#include <linux/slab.h>
65#include <linux/netdevice.h>
66#include <linux/vmalloc.h>
67#include <linux/init.h>
68#include <linux/delay.h>
69#include <linux/ioctl.h>
70#include <linux/termios.h>
71#include <linux/bitops.h>
72#include <linux/workqueue.h>
73#include <linux/hdlc.h>
74#include <linux/synclink.h>
75
76#include <asm/system.h>
77#include <asm/io.h>
78#include <asm/irq.h>
79#include <asm/dma.h>
80#include <asm/types.h>
81#include <asm/uaccess.h>
82
83#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
84#define SYNCLINK_GENERIC_HDLC 1
85#else
86#define SYNCLINK_GENERIC_HDLC 0
87#endif
88
89/*
90 * module identification
91 */
92static char *driver_name = "SyncLink GT";
93static char *tty_driver_name = "synclink_gt";
94static char *tty_dev_prefix = "ttySLG";
95MODULE_LICENSE("GPL");
96#define MGSL_MAGIC 0x5401
97#define MAX_DEVICES 32
98
99static struct pci_device_id pci_table[] = {
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
104 {0,}, /* terminate list */
105};
106MODULE_DEVICE_TABLE(pci, pci_table);
107
108static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
109static void remove_one(struct pci_dev *dev);
110static struct pci_driver pci_driver = {
111 .name = "synclink_gt",
112 .id_table = pci_table,
113 .probe = init_one,
114 .remove = __devexit_p(remove_one),
115};
116
117static bool pci_registered;
118
119/*
120 * module configuration and status
121 */
122static struct slgt_info *slgt_device_list;
123static int slgt_device_count;
124
125static int ttymajor;
126static int debug_level;
127static int maxframe[MAX_DEVICES];
128
129module_param(ttymajor, int, 0);
130module_param(debug_level, int, 0);
131module_param_array(maxframe, int, NULL, 0);
132
133MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
134MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
135MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
136
137/*
138 * tty support and callbacks
139 */
140static struct tty_driver *serial_driver;
141
142static int open(struct tty_struct *tty, struct file * filp);
143static void close(struct tty_struct *tty, struct file * filp);
144static void hangup(struct tty_struct *tty);
145static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
146
147static int write(struct tty_struct *tty, const unsigned char *buf, int count);
148static int put_char(struct tty_struct *tty, unsigned char ch);
149static void send_xchar(struct tty_struct *tty, char ch);
150static void wait_until_sent(struct tty_struct *tty, int timeout);
151static int write_room(struct tty_struct *tty);
152static void flush_chars(struct tty_struct *tty);
153static void flush_buffer(struct tty_struct *tty);
154static void tx_hold(struct tty_struct *tty);
155static void tx_release(struct tty_struct *tty);
156
157static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
158static int chars_in_buffer(struct tty_struct *tty);
159static void throttle(struct tty_struct * tty);
160static void unthrottle(struct tty_struct * tty);
161static int set_break(struct tty_struct *tty, int break_state);
162
163/*
164 * generic HDLC support and callbacks
165 */
166#if SYNCLINK_GENERIC_HDLC
167#define dev_to_port(D) (dev_to_hdlc(D)->priv)
168static void hdlcdev_tx_done(struct slgt_info *info);
169static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
170static int hdlcdev_init(struct slgt_info *info);
171static void hdlcdev_exit(struct slgt_info *info);
172#endif
173
174
175/*
176 * device specific structures, macros and functions
177 */
178
179#define SLGT_MAX_PORTS 4
180#define SLGT_REG_SIZE 256
181
182/*
183 * conditional wait facility
184 */
185struct cond_wait {
186 struct cond_wait *next;
187 wait_queue_head_t q;
188 wait_queue_t wait;
189 unsigned int data;
190};
191static void init_cond_wait(struct cond_wait *w, unsigned int data);
192static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
193static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
194static void flush_cond_wait(struct cond_wait **head);
195
196/*
197 * DMA buffer descriptor and access macros
198 */
199struct slgt_desc
200{
201 __le16 count;
202 __le16 status;
203 __le32 pbuf; /* physical address of data buffer */
204 __le32 next; /* physical address of next descriptor */
205
206 /* driver book keeping */
207 char *buf; /* virtual address of data buffer */
208 unsigned int pdesc; /* physical address of this descriptor */
209 dma_addr_t buf_dma_addr;
210 unsigned short buf_count;
211};
212
213#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
214#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
215#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
216#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
217#define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
218#define desc_count(a) (le16_to_cpu((a).count))
219#define desc_status(a) (le16_to_cpu((a).status))
220#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
221#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
222#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
223#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
224#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
225
226struct _input_signal_events {
227 int ri_up;
228 int ri_down;
229 int dsr_up;
230 int dsr_down;
231 int dcd_up;
232 int dcd_down;
233 int cts_up;
234 int cts_down;
235};
236
237/*
238 * device instance data structure
239 */
240struct slgt_info {
241 void *if_ptr; /* General purpose pointer (used by SPPP) */
242 struct tty_port port;
243
244 struct slgt_info *next_device; /* device list link */
245
246 int magic;
247
248 char device_name[25];
249 struct pci_dev *pdev;
250
251 int port_count; /* count of ports on adapter */
252 int adapter_num; /* adapter instance number */
253 int port_num; /* port instance number */
254
255 /* array of pointers to port contexts on this adapter */
256 struct slgt_info *port_array[SLGT_MAX_PORTS];
257
258 int line; /* tty line instance number */
259
260 struct mgsl_icount icount;
261
262 int timeout;
263 int x_char; /* xon/xoff character */
264 unsigned int read_status_mask;
265 unsigned int ignore_status_mask;
266
267 wait_queue_head_t status_event_wait_q;
268 wait_queue_head_t event_wait_q;
269 struct timer_list tx_timer;
270 struct timer_list rx_timer;
271
272 unsigned int gpio_present;
273 struct cond_wait *gpio_wait_q;
274
275 spinlock_t lock; /* spinlock for synchronizing with ISR */
276
277 struct work_struct task;
278 u32 pending_bh;
279 bool bh_requested;
280 bool bh_running;
281
282 int isr_overflow;
283 bool irq_requested; /* true if IRQ requested */
284 bool irq_occurred; /* for diagnostics use */
285
286 /* device configuration */
287
288 unsigned int bus_type;
289 unsigned int irq_level;
290 unsigned long irq_flags;
291
292 unsigned char __iomem * reg_addr; /* memory mapped registers address */
293 u32 phys_reg_addr;
294 bool reg_addr_requested;
295
296 MGSL_PARAMS params; /* communications parameters */
297 u32 idle_mode;
298 u32 max_frame_size; /* as set by device config */
299
300 unsigned int rbuf_fill_level;
301 unsigned int rx_pio;
302 unsigned int if_mode;
303 unsigned int base_clock;
304 unsigned int xsync;
305 unsigned int xctrl;
306
307 /* device status */
308
309 bool rx_enabled;
310 bool rx_restart;
311
312 bool tx_enabled;
313 bool tx_active;
314
315 unsigned char signals; /* serial signal states */
316 int init_error; /* initialization error */
317
318 unsigned char *tx_buf;
319 int tx_count;
320
321 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
322 char char_buf[MAX_ASYNC_BUFFER_SIZE];
323 bool drop_rts_on_tx_done;
324 struct _input_signal_events input_signal_events;
325
326 int dcd_chkcount; /* check counts to prevent */
327 int cts_chkcount; /* too many IRQs if a signal */
328 int dsr_chkcount; /* is floating */
329 int ri_chkcount;
330
331 char *bufs; /* virtual address of DMA buffer lists */
332 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
333
334 unsigned int rbuf_count;
335 struct slgt_desc *rbufs;
336 unsigned int rbuf_current;
337 unsigned int rbuf_index;
338 unsigned int rbuf_fill_index;
339 unsigned short rbuf_fill_count;
340
341 unsigned int tbuf_count;
342 struct slgt_desc *tbufs;
343 unsigned int tbuf_current;
344 unsigned int tbuf_start;
345
346 unsigned char *tmp_rbuf;
347 unsigned int tmp_rbuf_count;
348
349 /* SPPP/Cisco HDLC device parts */
350
351 int netcount;
352 spinlock_t netlock;
353#if SYNCLINK_GENERIC_HDLC
354 struct net_device *netdev;
355#endif
356
357};
358
359static MGSL_PARAMS default_params = {
360 .mode = MGSL_MODE_HDLC,
361 .loopback = 0,
362 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
363 .encoding = HDLC_ENCODING_NRZI_SPACE,
364 .clock_speed = 0,
365 .addr_filter = 0xff,
366 .crc_type = HDLC_CRC_16_CCITT,
367 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
368 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
369 .data_rate = 9600,
370 .data_bits = 8,
371 .stop_bits = 1,
372 .parity = ASYNC_PARITY_NONE
373};
374
375
376#define BH_RECEIVE 1
377#define BH_TRANSMIT 2
378#define BH_STATUS 4
379#define IO_PIN_SHUTDOWN_LIMIT 100
380
381#define DMABUFSIZE 256
382#define DESC_LIST_SIZE 4096
383
384#define MASK_PARITY BIT1
385#define MASK_FRAMING BIT0
386#define MASK_BREAK BIT14
387#define MASK_OVERRUN BIT4
388
389#define GSR 0x00 /* global status */
390#define JCR 0x04 /* JTAG control */
391#define IODR 0x08 /* GPIO direction */
392#define IOER 0x0c /* GPIO interrupt enable */
393#define IOVR 0x10 /* GPIO value */
394#define IOSR 0x14 /* GPIO interrupt status */
395#define TDR 0x80 /* tx data */
396#define RDR 0x80 /* rx data */
397#define TCR 0x82 /* tx control */
398#define TIR 0x84 /* tx idle */
399#define TPR 0x85 /* tx preamble */
400#define RCR 0x86 /* rx control */
401#define VCR 0x88 /* V.24 control */
402#define CCR 0x89 /* clock control */
403#define BDR 0x8a /* baud divisor */
404#define SCR 0x8c /* serial control */
405#define SSR 0x8e /* serial status */
406#define RDCSR 0x90 /* rx DMA control/status */
407#define TDCSR 0x94 /* tx DMA control/status */
408#define RDDAR 0x98 /* rx DMA descriptor address */
409#define TDDAR 0x9c /* tx DMA descriptor address */
410#define XSR 0x40 /* extended sync pattern */
411#define XCR 0x44 /* extended control */
412
413#define RXIDLE BIT14
414#define RXBREAK BIT14
415#define IRQ_TXDATA BIT13
416#define IRQ_TXIDLE BIT12
417#define IRQ_TXUNDER BIT11 /* HDLC */
418#define IRQ_RXDATA BIT10
419#define IRQ_RXIDLE BIT9 /* HDLC */
420#define IRQ_RXBREAK BIT9 /* async */
421#define IRQ_RXOVER BIT8
422#define IRQ_DSR BIT7
423#define IRQ_CTS BIT6
424#define IRQ_DCD BIT5
425#define IRQ_RI BIT4
426#define IRQ_ALL 0x3ff0
427#define IRQ_MASTER BIT0
428
429#define slgt_irq_on(info, mask) \
430 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
431#define slgt_irq_off(info, mask) \
432 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
433
434static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
435static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
436static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
437static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
438static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
439static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
440
441static void msc_set_vcr(struct slgt_info *info);
442
443static int startup(struct slgt_info *info);
444static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
445static void shutdown(struct slgt_info *info);
446static void program_hw(struct slgt_info *info);
447static void change_params(struct slgt_info *info);
448
449static int register_test(struct slgt_info *info);
450static int irq_test(struct slgt_info *info);
451static int loopback_test(struct slgt_info *info);
452static int adapter_test(struct slgt_info *info);
453
454static void reset_adapter(struct slgt_info *info);
455static void reset_port(struct slgt_info *info);
456static void async_mode(struct slgt_info *info);
457static void sync_mode(struct slgt_info *info);
458
459static void rx_stop(struct slgt_info *info);
460static void rx_start(struct slgt_info *info);
461static void reset_rbufs(struct slgt_info *info);
462static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
463static void rdma_reset(struct slgt_info *info);
464static bool rx_get_frame(struct slgt_info *info);
465static bool rx_get_buf(struct slgt_info *info);
466
467static void tx_start(struct slgt_info *info);
468static void tx_stop(struct slgt_info *info);
469static void tx_set_idle(struct slgt_info *info);
470static unsigned int free_tbuf_count(struct slgt_info *info);
471static unsigned int tbuf_bytes(struct slgt_info *info);
472static void reset_tbufs(struct slgt_info *info);
473static void tdma_reset(struct slgt_info *info);
474static bool tx_load(struct slgt_info *info, const char *buf, unsigned int count);
475
476static void get_signals(struct slgt_info *info);
477static void set_signals(struct slgt_info *info);
478static void enable_loopback(struct slgt_info *info);
479static void set_rate(struct slgt_info *info, u32 data_rate);
480
481static int bh_action(struct slgt_info *info);
482static void bh_handler(struct work_struct *work);
483static void bh_transmit(struct slgt_info *info);
484static void isr_serial(struct slgt_info *info);
485static void isr_rdma(struct slgt_info *info);
486static void isr_txeom(struct slgt_info *info, unsigned short status);
487static void isr_tdma(struct slgt_info *info);
488
489static int alloc_dma_bufs(struct slgt_info *info);
490static void free_dma_bufs(struct slgt_info *info);
491static int alloc_desc(struct slgt_info *info);
492static void free_desc(struct slgt_info *info);
493static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
494static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
495
496static int alloc_tmp_rbuf(struct slgt_info *info);
497static void free_tmp_rbuf(struct slgt_info *info);
498
499static void tx_timeout(unsigned long context);
500static void rx_timeout(unsigned long context);
501
502/*
503 * ioctl handlers
504 */
505static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
506static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
507static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
508static int get_txidle(struct slgt_info *info, int __user *idle_mode);
509static int set_txidle(struct slgt_info *info, int idle_mode);
510static int tx_enable(struct slgt_info *info, int enable);
511static int tx_abort(struct slgt_info *info);
512static int rx_enable(struct slgt_info *info, int enable);
513static int modem_input_wait(struct slgt_info *info,int arg);
514static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
515static int tiocmget(struct tty_struct *tty);
516static int tiocmset(struct tty_struct *tty,
517 unsigned int set, unsigned int clear);
518static int set_break(struct tty_struct *tty, int break_state);
519static int get_interface(struct slgt_info *info, int __user *if_mode);
520static int set_interface(struct slgt_info *info, int if_mode);
521static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
522static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
523static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
524static int get_xsync(struct slgt_info *info, int __user *if_mode);
525static int set_xsync(struct slgt_info *info, int if_mode);
526static int get_xctrl(struct slgt_info *info, int __user *if_mode);
527static int set_xctrl(struct slgt_info *info, int if_mode);
528
529/*
530 * driver functions
531 */
532static void add_device(struct slgt_info *info);
533static void device_init(int adapter_num, struct pci_dev *pdev);
534static int claim_resources(struct slgt_info *info);
535static void release_resources(struct slgt_info *info);
536
537/*
538 * DEBUG OUTPUT CODE
539 */
540#ifndef DBGINFO
541#define DBGINFO(fmt)
542#endif
543#ifndef DBGERR
544#define DBGERR(fmt)
545#endif
546#ifndef DBGBH
547#define DBGBH(fmt)
548#endif
549#ifndef DBGISR
550#define DBGISR(fmt)
551#endif
552
553#ifdef DBGDATA
554static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
555{
556 int i;
557 int linecount;
558 printk("%s %s data:\n",info->device_name, label);
559 while(count) {
560 linecount = (count > 16) ? 16 : count;
561 for(i=0; i < linecount; i++)
562 printk("%02X ",(unsigned char)data[i]);
563 for(;i<17;i++)
564 printk(" ");
565 for(i=0;i<linecount;i++) {
566 if (data[i]>=040 && data[i]<=0176)
567 printk("%c",data[i]);
568 else
569 printk(".");
570 }
571 printk("\n");
572 data += linecount;
573 count -= linecount;
574 }
575}
576#else
577#define DBGDATA(info, buf, size, label)
578#endif
579
580#ifdef DBGTBUF
581static void dump_tbufs(struct slgt_info *info)
582{
583 int i;
584 printk("tbuf_current=%d\n", info->tbuf_current);
585 for (i=0 ; i < info->tbuf_count ; i++) {
586 printk("%d: count=%04X status=%04X\n",
587 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
588 }
589}
590#else
591#define DBGTBUF(info)
592#endif
593
594#ifdef DBGRBUF
595static void dump_rbufs(struct slgt_info *info)
596{
597 int i;
598 printk("rbuf_current=%d\n", info->rbuf_current);
599 for (i=0 ; i < info->rbuf_count ; i++) {
600 printk("%d: count=%04X status=%04X\n",
601 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
602 }
603}
604#else
605#define DBGRBUF(info)
606#endif
607
608static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
609{
610#ifdef SANITY_CHECK
611 if (!info) {
612 printk("null struct slgt_info for (%s) in %s\n", devname, name);
613 return 1;
614 }
615 if (info->magic != MGSL_MAGIC) {
616 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
617 return 1;
618 }
619#else
620 if (!info)
621 return 1;
622#endif
623 return 0;
624}
625
626/**
627 * line discipline callback wrappers
628 *
629 * The wrappers maintain line discipline references
630 * while calling into the line discipline.
631 *
632 * ldisc_receive_buf - pass receive data to line discipline
633 */
634static void ldisc_receive_buf(struct tty_struct *tty,
635 const __u8 *data, char *flags, int count)
636{
637 struct tty_ldisc *ld;
638 if (!tty)
639 return;
640 ld = tty_ldisc_ref(tty);
641 if (ld) {
642 if (ld->ops->receive_buf)
643 ld->ops->receive_buf(tty, data, flags, count);
644 tty_ldisc_deref(ld);
645 }
646}
647
648/* tty callbacks */
649
650static int open(struct tty_struct *tty, struct file *filp)
651{
652 struct slgt_info *info;
653 int retval, line;
654 unsigned long flags;
655
656 line = tty->index;
657 if ((line < 0) || (line >= slgt_device_count)) {
658 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
659 return -ENODEV;
660 }
661
662 info = slgt_device_list;
663 while(info && info->line != line)
664 info = info->next_device;
665 if (sanity_check(info, tty->name, "open"))
666 return -ENODEV;
667 if (info->init_error) {
668 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
669 return -ENODEV;
670 }
671
672 tty->driver_data = info;
673 info->port.tty = tty;
674
675 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
676
677 /* If port is closing, signal caller to try again */
678 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
679 if (info->port.flags & ASYNC_CLOSING)
680 interruptible_sleep_on(&info->port.close_wait);
681 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
682 -EAGAIN : -ERESTARTSYS);
683 goto cleanup;
684 }
685
686 mutex_lock(&info->port.mutex);
687 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
688
689 spin_lock_irqsave(&info->netlock, flags);
690 if (info->netcount) {
691 retval = -EBUSY;
692 spin_unlock_irqrestore(&info->netlock, flags);
693 mutex_unlock(&info->port.mutex);
694 goto cleanup;
695 }
696 info->port.count++;
697 spin_unlock_irqrestore(&info->netlock, flags);
698
699 if (info->port.count == 1) {
700 /* 1st open on this device, init hardware */
701 retval = startup(info);
702 if (retval < 0) {
703 mutex_unlock(&info->port.mutex);
704 goto cleanup;
705 }
706 }
707 mutex_unlock(&info->port.mutex);
708 retval = block_til_ready(tty, filp, info);
709 if (retval) {
710 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
711 goto cleanup;
712 }
713
714 retval = 0;
715
716cleanup:
717 if (retval) {
718 if (tty->count == 1)
719 info->port.tty = NULL; /* tty layer will release tty struct */
720 if(info->port.count)
721 info->port.count--;
722 }
723
724 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
725 return retval;
726}
727
728static void close(struct tty_struct *tty, struct file *filp)
729{
730 struct slgt_info *info = tty->driver_data;
731
732 if (sanity_check(info, tty->name, "close"))
733 return;
734 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
735
736 if (tty_port_close_start(&info->port, tty, filp) == 0)
737 goto cleanup;
738
739 mutex_lock(&info->port.mutex);
740 if (info->port.flags & ASYNC_INITIALIZED)
741 wait_until_sent(tty, info->timeout);
742 flush_buffer(tty);
743 tty_ldisc_flush(tty);
744
745 shutdown(info);
746 mutex_unlock(&info->port.mutex);
747
748 tty_port_close_end(&info->port, tty);
749 info->port.tty = NULL;
750cleanup:
751 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
752}
753
754static void hangup(struct tty_struct *tty)
755{
756 struct slgt_info *info = tty->driver_data;
757 unsigned long flags;
758
759 if (sanity_check(info, tty->name, "hangup"))
760 return;
761 DBGINFO(("%s hangup\n", info->device_name));
762
763 flush_buffer(tty);
764
765 mutex_lock(&info->port.mutex);
766 shutdown(info);
767
768 spin_lock_irqsave(&info->port.lock, flags);
769 info->port.count = 0;
770 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
771 info->port.tty = NULL;
772 spin_unlock_irqrestore(&info->port.lock, flags);
773 mutex_unlock(&info->port.mutex);
774
775 wake_up_interruptible(&info->port.open_wait);
776}
777
778static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
779{
780 struct slgt_info *info = tty->driver_data;
781 unsigned long flags;
782
783 DBGINFO(("%s set_termios\n", tty->driver->name));
784
785 change_params(info);
786
787 /* Handle transition to B0 status */
788 if (old_termios->c_cflag & CBAUD &&
789 !(tty->termios->c_cflag & CBAUD)) {
790 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
791 spin_lock_irqsave(&info->lock,flags);
792 set_signals(info);
793 spin_unlock_irqrestore(&info->lock,flags);
794 }
795
796 /* Handle transition away from B0 status */
797 if (!(old_termios->c_cflag & CBAUD) &&
798 tty->termios->c_cflag & CBAUD) {
799 info->signals |= SerialSignal_DTR;
800 if (!(tty->termios->c_cflag & CRTSCTS) ||
801 !test_bit(TTY_THROTTLED, &tty->flags)) {
802 info->signals |= SerialSignal_RTS;
803 }
804 spin_lock_irqsave(&info->lock,flags);
805 set_signals(info);
806 spin_unlock_irqrestore(&info->lock,flags);
807 }
808
809 /* Handle turning off CRTSCTS */
810 if (old_termios->c_cflag & CRTSCTS &&
811 !(tty->termios->c_cflag & CRTSCTS)) {
812 tty->hw_stopped = 0;
813 tx_release(tty);
814 }
815}
816
817static void update_tx_timer(struct slgt_info *info)
818{
819 /*
820 * use worst case speed of 1200bps to calculate transmit timeout
821 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
822 */
823 if (info->params.mode == MGSL_MODE_HDLC) {
824 int timeout = (tbuf_bytes(info) * 7) + 1000;
825 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
826 }
827}
828
829static int write(struct tty_struct *tty,
830 const unsigned char *buf, int count)
831{
832 int ret = 0;
833 struct slgt_info *info = tty->driver_data;
834 unsigned long flags;
835
836 if (sanity_check(info, tty->name, "write"))
837 return -EIO;
838
839 DBGINFO(("%s write count=%d\n", info->device_name, count));
840
841 if (!info->tx_buf || (count > info->max_frame_size))
842 return -EIO;
843
844 if (!count || tty->stopped || tty->hw_stopped)
845 return 0;
846
847 spin_lock_irqsave(&info->lock, flags);
848
849 if (info->tx_count) {
850 /* send accumulated data from send_char() */
851 if (!tx_load(info, info->tx_buf, info->tx_count))
852 goto cleanup;
853 info->tx_count = 0;
854 }
855
856 if (tx_load(info, buf, count))
857 ret = count;
858
859cleanup:
860 spin_unlock_irqrestore(&info->lock, flags);
861 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
862 return ret;
863}
864
865static int put_char(struct tty_struct *tty, unsigned char ch)
866{
867 struct slgt_info *info = tty->driver_data;
868 unsigned long flags;
869 int ret = 0;
870
871 if (sanity_check(info, tty->name, "put_char"))
872 return 0;
873 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
874 if (!info->tx_buf)
875 return 0;
876 spin_lock_irqsave(&info->lock,flags);
877 if (info->tx_count < info->max_frame_size) {
878 info->tx_buf[info->tx_count++] = ch;
879 ret = 1;
880 }
881 spin_unlock_irqrestore(&info->lock,flags);
882 return ret;
883}
884
885static void send_xchar(struct tty_struct *tty, char ch)
886{
887 struct slgt_info *info = tty->driver_data;
888 unsigned long flags;
889
890 if (sanity_check(info, tty->name, "send_xchar"))
891 return;
892 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
893 info->x_char = ch;
894 if (ch) {
895 spin_lock_irqsave(&info->lock,flags);
896 if (!info->tx_enabled)
897 tx_start(info);
898 spin_unlock_irqrestore(&info->lock,flags);
899 }
900}
901
902static void wait_until_sent(struct tty_struct *tty, int timeout)
903{
904 struct slgt_info *info = tty->driver_data;
905 unsigned long orig_jiffies, char_time;
906
907 if (!info )
908 return;
909 if (sanity_check(info, tty->name, "wait_until_sent"))
910 return;
911 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
912 if (!(info->port.flags & ASYNC_INITIALIZED))
913 goto exit;
914
915 orig_jiffies = jiffies;
916
917 /* Set check interval to 1/5 of estimated time to
918 * send a character, and make it at least 1. The check
919 * interval should also be less than the timeout.
920 * Note: use tight timings here to satisfy the NIST-PCTS.
921 */
922
923 if (info->params.data_rate) {
924 char_time = info->timeout/(32 * 5);
925 if (!char_time)
926 char_time++;
927 } else
928 char_time = 1;
929
930 if (timeout)
931 char_time = min_t(unsigned long, char_time, timeout);
932
933 while (info->tx_active) {
934 msleep_interruptible(jiffies_to_msecs(char_time));
935 if (signal_pending(current))
936 break;
937 if (timeout && time_after(jiffies, orig_jiffies + timeout))
938 break;
939 }
940exit:
941 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
942}
943
944static int write_room(struct tty_struct *tty)
945{
946 struct slgt_info *info = tty->driver_data;
947 int ret;
948
949 if (sanity_check(info, tty->name, "write_room"))
950 return 0;
951 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
952 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
953 return ret;
954}
955
956static void flush_chars(struct tty_struct *tty)
957{
958 struct slgt_info *info = tty->driver_data;
959 unsigned long flags;
960
961 if (sanity_check(info, tty->name, "flush_chars"))
962 return;
963 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
964
965 if (info->tx_count <= 0 || tty->stopped ||
966 tty->hw_stopped || !info->tx_buf)
967 return;
968
969 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
970
971 spin_lock_irqsave(&info->lock,flags);
972 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
973 info->tx_count = 0;
974 spin_unlock_irqrestore(&info->lock,flags);
975}
976
977static void flush_buffer(struct tty_struct *tty)
978{
979 struct slgt_info *info = tty->driver_data;
980 unsigned long flags;
981
982 if (sanity_check(info, tty->name, "flush_buffer"))
983 return;
984 DBGINFO(("%s flush_buffer\n", info->device_name));
985
986 spin_lock_irqsave(&info->lock, flags);
987 info->tx_count = 0;
988 spin_unlock_irqrestore(&info->lock, flags);
989
990 tty_wakeup(tty);
991}
992
993/*
994 * throttle (stop) transmitter
995 */
996static void tx_hold(struct tty_struct *tty)
997{
998 struct slgt_info *info = tty->driver_data;
999 unsigned long flags;
1000
1001 if (sanity_check(info, tty->name, "tx_hold"))
1002 return;
1003 DBGINFO(("%s tx_hold\n", info->device_name));
1004 spin_lock_irqsave(&info->lock,flags);
1005 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
1006 tx_stop(info);
1007 spin_unlock_irqrestore(&info->lock,flags);
1008}
1009
1010/*
1011 * release (start) transmitter
1012 */
1013static void tx_release(struct tty_struct *tty)
1014{
1015 struct slgt_info *info = tty->driver_data;
1016 unsigned long flags;
1017
1018 if (sanity_check(info, tty->name, "tx_release"))
1019 return;
1020 DBGINFO(("%s tx_release\n", info->device_name));
1021 spin_lock_irqsave(&info->lock, flags);
1022 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
1023 info->tx_count = 0;
1024 spin_unlock_irqrestore(&info->lock, flags);
1025}
1026
1027/*
1028 * Service an IOCTL request
1029 *
1030 * Arguments
1031 *
1032 * tty pointer to tty instance data
1033 * cmd IOCTL command code
1034 * arg command argument/context
1035 *
1036 * Return 0 if success, otherwise error code
1037 */
1038static int ioctl(struct tty_struct *tty,
1039 unsigned int cmd, unsigned long arg)
1040{
1041 struct slgt_info *info = tty->driver_data;
1042 void __user *argp = (void __user *)arg;
1043 int ret;
1044
1045 if (sanity_check(info, tty->name, "ioctl"))
1046 return -ENODEV;
1047 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1048
1049 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1050 (cmd != TIOCMIWAIT)) {
1051 if (tty->flags & (1 << TTY_IO_ERROR))
1052 return -EIO;
1053 }
1054
1055 switch (cmd) {
1056 case MGSL_IOCWAITEVENT:
1057 return wait_mgsl_event(info, argp);
1058 case TIOCMIWAIT:
1059 return modem_input_wait(info,(int)arg);
1060 case MGSL_IOCSGPIO:
1061 return set_gpio(info, argp);
1062 case MGSL_IOCGGPIO:
1063 return get_gpio(info, argp);
1064 case MGSL_IOCWAITGPIO:
1065 return wait_gpio(info, argp);
1066 case MGSL_IOCGXSYNC:
1067 return get_xsync(info, argp);
1068 case MGSL_IOCSXSYNC:
1069 return set_xsync(info, (int)arg);
1070 case MGSL_IOCGXCTRL:
1071 return get_xctrl(info, argp);
1072 case MGSL_IOCSXCTRL:
1073 return set_xctrl(info, (int)arg);
1074 }
1075 mutex_lock(&info->port.mutex);
1076 switch (cmd) {
1077 case MGSL_IOCGPARAMS:
1078 ret = get_params(info, argp);
1079 break;
1080 case MGSL_IOCSPARAMS:
1081 ret = set_params(info, argp);
1082 break;
1083 case MGSL_IOCGTXIDLE:
1084 ret = get_txidle(info, argp);
1085 break;
1086 case MGSL_IOCSTXIDLE:
1087 ret = set_txidle(info, (int)arg);
1088 break;
1089 case MGSL_IOCTXENABLE:
1090 ret = tx_enable(info, (int)arg);
1091 break;
1092 case MGSL_IOCRXENABLE:
1093 ret = rx_enable(info, (int)arg);
1094 break;
1095 case MGSL_IOCTXABORT:
1096 ret = tx_abort(info);
1097 break;
1098 case MGSL_IOCGSTATS:
1099 ret = get_stats(info, argp);
1100 break;
1101 case MGSL_IOCGIF:
1102 ret = get_interface(info, argp);
1103 break;
1104 case MGSL_IOCSIF:
1105 ret = set_interface(info,(int)arg);
1106 break;
1107 default:
1108 ret = -ENOIOCTLCMD;
1109 }
1110 mutex_unlock(&info->port.mutex);
1111 return ret;
1112}
1113
1114static int get_icount(struct tty_struct *tty,
1115 struct serial_icounter_struct *icount)
1116
1117{
1118 struct slgt_info *info = tty->driver_data;
1119 struct mgsl_icount cnow; /* kernel counter temps */
1120 unsigned long flags;
1121
1122 spin_lock_irqsave(&info->lock,flags);
1123 cnow = info->icount;
1124 spin_unlock_irqrestore(&info->lock,flags);
1125
1126 icount->cts = cnow.cts;
1127 icount->dsr = cnow.dsr;
1128 icount->rng = cnow.rng;
1129 icount->dcd = cnow.dcd;
1130 icount->rx = cnow.rx;
1131 icount->tx = cnow.tx;
1132 icount->frame = cnow.frame;
1133 icount->overrun = cnow.overrun;
1134 icount->parity = cnow.parity;
1135 icount->brk = cnow.brk;
1136 icount->buf_overrun = cnow.buf_overrun;
1137
1138 return 0;
1139}
1140
1141/*
1142 * support for 32 bit ioctl calls on 64 bit systems
1143 */
1144#ifdef CONFIG_COMPAT
1145static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1146{
1147 struct MGSL_PARAMS32 tmp_params;
1148
1149 DBGINFO(("%s get_params32\n", info->device_name));
1150 memset(&tmp_params, 0, sizeof(tmp_params));
1151 tmp_params.mode = (compat_ulong_t)info->params.mode;
1152 tmp_params.loopback = info->params.loopback;
1153 tmp_params.flags = info->params.flags;
1154 tmp_params.encoding = info->params.encoding;
1155 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1156 tmp_params.addr_filter = info->params.addr_filter;
1157 tmp_params.crc_type = info->params.crc_type;
1158 tmp_params.preamble_length = info->params.preamble_length;
1159 tmp_params.preamble = info->params.preamble;
1160 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1161 tmp_params.data_bits = info->params.data_bits;
1162 tmp_params.stop_bits = info->params.stop_bits;
1163 tmp_params.parity = info->params.parity;
1164 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1165 return -EFAULT;
1166 return 0;
1167}
1168
1169static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1170{
1171 struct MGSL_PARAMS32 tmp_params;
1172
1173 DBGINFO(("%s set_params32\n", info->device_name));
1174 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1175 return -EFAULT;
1176
1177 spin_lock(&info->lock);
1178 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1179 info->base_clock = tmp_params.clock_speed;
1180 } else {
1181 info->params.mode = tmp_params.mode;
1182 info->params.loopback = tmp_params.loopback;
1183 info->params.flags = tmp_params.flags;
1184 info->params.encoding = tmp_params.encoding;
1185 info->params.clock_speed = tmp_params.clock_speed;
1186 info->params.addr_filter = tmp_params.addr_filter;
1187 info->params.crc_type = tmp_params.crc_type;
1188 info->params.preamble_length = tmp_params.preamble_length;
1189 info->params.preamble = tmp_params.preamble;
1190 info->params.data_rate = tmp_params.data_rate;
1191 info->params.data_bits = tmp_params.data_bits;
1192 info->params.stop_bits = tmp_params.stop_bits;
1193 info->params.parity = tmp_params.parity;
1194 }
1195 spin_unlock(&info->lock);
1196
1197 program_hw(info);
1198
1199 return 0;
1200}
1201
1202static long slgt_compat_ioctl(struct tty_struct *tty,
1203 unsigned int cmd, unsigned long arg)
1204{
1205 struct slgt_info *info = tty->driver_data;
1206 int rc = -ENOIOCTLCMD;
1207
1208 if (sanity_check(info, tty->name, "compat_ioctl"))
1209 return -ENODEV;
1210 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1211
1212 switch (cmd) {
1213
1214 case MGSL_IOCSPARAMS32:
1215 rc = set_params32(info, compat_ptr(arg));
1216 break;
1217
1218 case MGSL_IOCGPARAMS32:
1219 rc = get_params32(info, compat_ptr(arg));
1220 break;
1221
1222 case MGSL_IOCGPARAMS:
1223 case MGSL_IOCSPARAMS:
1224 case MGSL_IOCGTXIDLE:
1225 case MGSL_IOCGSTATS:
1226 case MGSL_IOCWAITEVENT:
1227 case MGSL_IOCGIF:
1228 case MGSL_IOCSGPIO:
1229 case MGSL_IOCGGPIO:
1230 case MGSL_IOCWAITGPIO:
1231 case MGSL_IOCGXSYNC:
1232 case MGSL_IOCGXCTRL:
1233 case MGSL_IOCSTXIDLE:
1234 case MGSL_IOCTXENABLE:
1235 case MGSL_IOCRXENABLE:
1236 case MGSL_IOCTXABORT:
1237 case TIOCMIWAIT:
1238 case MGSL_IOCSIF:
1239 case MGSL_IOCSXSYNC:
1240 case MGSL_IOCSXCTRL:
1241 rc = ioctl(tty, cmd, arg);
1242 break;
1243 }
1244
1245 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1246 return rc;
1247}
1248#else
1249#define slgt_compat_ioctl NULL
1250#endif /* ifdef CONFIG_COMPAT */
1251
1252/*
1253 * proc fs support
1254 */
1255static inline void line_info(struct seq_file *m, struct slgt_info *info)
1256{
1257 char stat_buf[30];
1258 unsigned long flags;
1259
1260 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1261 info->device_name, info->phys_reg_addr,
1262 info->irq_level, info->max_frame_size);
1263
1264 /* output current serial signal states */
1265 spin_lock_irqsave(&info->lock,flags);
1266 get_signals(info);
1267 spin_unlock_irqrestore(&info->lock,flags);
1268
1269 stat_buf[0] = 0;
1270 stat_buf[1] = 0;
1271 if (info->signals & SerialSignal_RTS)
1272 strcat(stat_buf, "|RTS");
1273 if (info->signals & SerialSignal_CTS)
1274 strcat(stat_buf, "|CTS");
1275 if (info->signals & SerialSignal_DTR)
1276 strcat(stat_buf, "|DTR");
1277 if (info->signals & SerialSignal_DSR)
1278 strcat(stat_buf, "|DSR");
1279 if (info->signals & SerialSignal_DCD)
1280 strcat(stat_buf, "|CD");
1281 if (info->signals & SerialSignal_RI)
1282 strcat(stat_buf, "|RI");
1283
1284 if (info->params.mode != MGSL_MODE_ASYNC) {
1285 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1286 info->icount.txok, info->icount.rxok);
1287 if (info->icount.txunder)
1288 seq_printf(m, " txunder:%d", info->icount.txunder);
1289 if (info->icount.txabort)
1290 seq_printf(m, " txabort:%d", info->icount.txabort);
1291 if (info->icount.rxshort)
1292 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1293 if (info->icount.rxlong)
1294 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1295 if (info->icount.rxover)
1296 seq_printf(m, " rxover:%d", info->icount.rxover);
1297 if (info->icount.rxcrc)
1298 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1299 } else {
1300 seq_printf(m, "\tASYNC tx:%d rx:%d",
1301 info->icount.tx, info->icount.rx);
1302 if (info->icount.frame)
1303 seq_printf(m, " fe:%d", info->icount.frame);
1304 if (info->icount.parity)
1305 seq_printf(m, " pe:%d", info->icount.parity);
1306 if (info->icount.brk)
1307 seq_printf(m, " brk:%d", info->icount.brk);
1308 if (info->icount.overrun)
1309 seq_printf(m, " oe:%d", info->icount.overrun);
1310 }
1311
1312 /* Append serial signal status to end */
1313 seq_printf(m, " %s\n", stat_buf+1);
1314
1315 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1316 info->tx_active,info->bh_requested,info->bh_running,
1317 info->pending_bh);
1318}
1319
1320/* Called to print information about devices
1321 */
1322static int synclink_gt_proc_show(struct seq_file *m, void *v)
1323{
1324 struct slgt_info *info;
1325
1326 seq_puts(m, "synclink_gt driver\n");
1327
1328 info = slgt_device_list;
1329 while( info ) {
1330 line_info(m, info);
1331 info = info->next_device;
1332 }
1333 return 0;
1334}
1335
1336static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1337{
1338 return single_open(file, synclink_gt_proc_show, NULL);
1339}
1340
1341static const struct file_operations synclink_gt_proc_fops = {
1342 .owner = THIS_MODULE,
1343 .open = synclink_gt_proc_open,
1344 .read = seq_read,
1345 .llseek = seq_lseek,
1346 .release = single_release,
1347};
1348
1349/*
1350 * return count of bytes in transmit buffer
1351 */
1352static int chars_in_buffer(struct tty_struct *tty)
1353{
1354 struct slgt_info *info = tty->driver_data;
1355 int count;
1356 if (sanity_check(info, tty->name, "chars_in_buffer"))
1357 return 0;
1358 count = tbuf_bytes(info);
1359 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1360 return count;
1361}
1362
1363/*
1364 * signal remote device to throttle send data (our receive data)
1365 */
1366static void throttle(struct tty_struct * tty)
1367{
1368 struct slgt_info *info = tty->driver_data;
1369 unsigned long flags;
1370
1371 if (sanity_check(info, tty->name, "throttle"))
1372 return;
1373 DBGINFO(("%s throttle\n", info->device_name));
1374 if (I_IXOFF(tty))
1375 send_xchar(tty, STOP_CHAR(tty));
1376 if (tty->termios->c_cflag & CRTSCTS) {
1377 spin_lock_irqsave(&info->lock,flags);
1378 info->signals &= ~SerialSignal_RTS;
1379 set_signals(info);
1380 spin_unlock_irqrestore(&info->lock,flags);
1381 }
1382}
1383
1384/*
1385 * signal remote device to stop throttling send data (our receive data)
1386 */
1387static void unthrottle(struct tty_struct * tty)
1388{
1389 struct slgt_info *info = tty->driver_data;
1390 unsigned long flags;
1391
1392 if (sanity_check(info, tty->name, "unthrottle"))
1393 return;
1394 DBGINFO(("%s unthrottle\n", info->device_name));
1395 if (I_IXOFF(tty)) {
1396 if (info->x_char)
1397 info->x_char = 0;
1398 else
1399 send_xchar(tty, START_CHAR(tty));
1400 }
1401 if (tty->termios->c_cflag & CRTSCTS) {
1402 spin_lock_irqsave(&info->lock,flags);
1403 info->signals |= SerialSignal_RTS;
1404 set_signals(info);
1405 spin_unlock_irqrestore(&info->lock,flags);
1406 }
1407}
1408
1409/*
1410 * set or clear transmit break condition
1411 * break_state -1=set break condition, 0=clear
1412 */
1413static int set_break(struct tty_struct *tty, int break_state)
1414{
1415 struct slgt_info *info = tty->driver_data;
1416 unsigned short value;
1417 unsigned long flags;
1418
1419 if (sanity_check(info, tty->name, "set_break"))
1420 return -EINVAL;
1421 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1422
1423 spin_lock_irqsave(&info->lock,flags);
1424 value = rd_reg16(info, TCR);
1425 if (break_state == -1)
1426 value |= BIT6;
1427 else
1428 value &= ~BIT6;
1429 wr_reg16(info, TCR, value);
1430 spin_unlock_irqrestore(&info->lock,flags);
1431 return 0;
1432}
1433
1434#if SYNCLINK_GENERIC_HDLC
1435
1436/**
1437 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1438 * set encoding and frame check sequence (FCS) options
1439 *
1440 * dev pointer to network device structure
1441 * encoding serial encoding setting
1442 * parity FCS setting
1443 *
1444 * returns 0 if success, otherwise error code
1445 */
1446static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1447 unsigned short parity)
1448{
1449 struct slgt_info *info = dev_to_port(dev);
1450 unsigned char new_encoding;
1451 unsigned short new_crctype;
1452
1453 /* return error if TTY interface open */
1454 if (info->port.count)
1455 return -EBUSY;
1456
1457 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1458
1459 switch (encoding)
1460 {
1461 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1462 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1463 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1464 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1465 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1466 default: return -EINVAL;
1467 }
1468
1469 switch (parity)
1470 {
1471 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1472 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1473 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1474 default: return -EINVAL;
1475 }
1476
1477 info->params.encoding = new_encoding;
1478 info->params.crc_type = new_crctype;
1479
1480 /* if network interface up, reprogram hardware */
1481 if (info->netcount)
1482 program_hw(info);
1483
1484 return 0;
1485}
1486
1487/**
1488 * called by generic HDLC layer to send frame
1489 *
1490 * skb socket buffer containing HDLC frame
1491 * dev pointer to network device structure
1492 */
1493static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1494 struct net_device *dev)
1495{
1496 struct slgt_info *info = dev_to_port(dev);
1497 unsigned long flags;
1498
1499 DBGINFO(("%s hdlc_xmit\n", dev->name));
1500
1501 if (!skb->len)
1502 return NETDEV_TX_OK;
1503
1504 /* stop sending until this frame completes */
1505 netif_stop_queue(dev);
1506
1507 /* update network statistics */
1508 dev->stats.tx_packets++;
1509 dev->stats.tx_bytes += skb->len;
1510
1511 /* save start time for transmit timeout detection */
1512 dev->trans_start = jiffies;
1513
1514 spin_lock_irqsave(&info->lock, flags);
1515 tx_load(info, skb->data, skb->len);
1516 spin_unlock_irqrestore(&info->lock, flags);
1517
1518 /* done with socket buffer, so free it */
1519 dev_kfree_skb(skb);
1520
1521 return NETDEV_TX_OK;
1522}
1523
1524/**
1525 * called by network layer when interface enabled
1526 * claim resources and initialize hardware
1527 *
1528 * dev pointer to network device structure
1529 *
1530 * returns 0 if success, otherwise error code
1531 */
1532static int hdlcdev_open(struct net_device *dev)
1533{
1534 struct slgt_info *info = dev_to_port(dev);
1535 int rc;
1536 unsigned long flags;
1537
1538 if (!try_module_get(THIS_MODULE))
1539 return -EBUSY;
1540
1541 DBGINFO(("%s hdlcdev_open\n", dev->name));
1542
1543 /* generic HDLC layer open processing */
1544 if ((rc = hdlc_open(dev)))
1545 return rc;
1546
1547 /* arbitrate between network and tty opens */
1548 spin_lock_irqsave(&info->netlock, flags);
1549 if (info->port.count != 0 || info->netcount != 0) {
1550 DBGINFO(("%s hdlc_open busy\n", dev->name));
1551 spin_unlock_irqrestore(&info->netlock, flags);
1552 return -EBUSY;
1553 }
1554 info->netcount=1;
1555 spin_unlock_irqrestore(&info->netlock, flags);
1556
1557 /* claim resources and init adapter */
1558 if ((rc = startup(info)) != 0) {
1559 spin_lock_irqsave(&info->netlock, flags);
1560 info->netcount=0;
1561 spin_unlock_irqrestore(&info->netlock, flags);
1562 return rc;
1563 }
1564
1565 /* assert DTR and RTS, apply hardware settings */
1566 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1567 program_hw(info);
1568
1569 /* enable network layer transmit */
1570 dev->trans_start = jiffies;
1571 netif_start_queue(dev);
1572
1573 /* inform generic HDLC layer of current DCD status */
1574 spin_lock_irqsave(&info->lock, flags);
1575 get_signals(info);
1576 spin_unlock_irqrestore(&info->lock, flags);
1577 if (info->signals & SerialSignal_DCD)
1578 netif_carrier_on(dev);
1579 else
1580 netif_carrier_off(dev);
1581 return 0;
1582}
1583
1584/**
1585 * called by network layer when interface is disabled
1586 * shutdown hardware and release resources
1587 *
1588 * dev pointer to network device structure
1589 *
1590 * returns 0 if success, otherwise error code
1591 */
1592static int hdlcdev_close(struct net_device *dev)
1593{
1594 struct slgt_info *info = dev_to_port(dev);
1595 unsigned long flags;
1596
1597 DBGINFO(("%s hdlcdev_close\n", dev->name));
1598
1599 netif_stop_queue(dev);
1600
1601 /* shutdown adapter and release resources */
1602 shutdown(info);
1603
1604 hdlc_close(dev);
1605
1606 spin_lock_irqsave(&info->netlock, flags);
1607 info->netcount=0;
1608 spin_unlock_irqrestore(&info->netlock, flags);
1609
1610 module_put(THIS_MODULE);
1611 return 0;
1612}
1613
1614/**
1615 * called by network layer to process IOCTL call to network device
1616 *
1617 * dev pointer to network device structure
1618 * ifr pointer to network interface request structure
1619 * cmd IOCTL command code
1620 *
1621 * returns 0 if success, otherwise error code
1622 */
1623static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1624{
1625 const size_t size = sizeof(sync_serial_settings);
1626 sync_serial_settings new_line;
1627 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1628 struct slgt_info *info = dev_to_port(dev);
1629 unsigned int flags;
1630
1631 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1632
1633 /* return error if TTY interface open */
1634 if (info->port.count)
1635 return -EBUSY;
1636
1637 if (cmd != SIOCWANDEV)
1638 return hdlc_ioctl(dev, ifr, cmd);
1639
1640 memset(&new_line, 0, sizeof(new_line));
1641
1642 switch(ifr->ifr_settings.type) {
1643 case IF_GET_IFACE: /* return current sync_serial_settings */
1644
1645 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1646 if (ifr->ifr_settings.size < size) {
1647 ifr->ifr_settings.size = size; /* data size wanted */
1648 return -ENOBUFS;
1649 }
1650
1651 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1652 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1653 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1654 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1655
1656 switch (flags){
1657 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1658 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1659 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1660 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1661 default: new_line.clock_type = CLOCK_DEFAULT;
1662 }
1663
1664 new_line.clock_rate = info->params.clock_speed;
1665 new_line.loopback = info->params.loopback ? 1:0;
1666
1667 if (copy_to_user(line, &new_line, size))
1668 return -EFAULT;
1669 return 0;
1670
1671 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1672
1673 if(!capable(CAP_NET_ADMIN))
1674 return -EPERM;
1675 if (copy_from_user(&new_line, line, size))
1676 return -EFAULT;
1677
1678 switch (new_line.clock_type)
1679 {
1680 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1681 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1682 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1683 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1684 case CLOCK_DEFAULT: flags = info->params.flags &
1685 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1686 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1687 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1688 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1689 default: return -EINVAL;
1690 }
1691
1692 if (new_line.loopback != 0 && new_line.loopback != 1)
1693 return -EINVAL;
1694
1695 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1696 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1697 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1698 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1699 info->params.flags |= flags;
1700
1701 info->params.loopback = new_line.loopback;
1702
1703 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1704 info->params.clock_speed = new_line.clock_rate;
1705 else
1706 info->params.clock_speed = 0;
1707
1708 /* if network interface up, reprogram hardware */
1709 if (info->netcount)
1710 program_hw(info);
1711 return 0;
1712
1713 default:
1714 return hdlc_ioctl(dev, ifr, cmd);
1715 }
1716}
1717
1718/**
1719 * called by network layer when transmit timeout is detected
1720 *
1721 * dev pointer to network device structure
1722 */
1723static void hdlcdev_tx_timeout(struct net_device *dev)
1724{
1725 struct slgt_info *info = dev_to_port(dev);
1726 unsigned long flags;
1727
1728 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1729
1730 dev->stats.tx_errors++;
1731 dev->stats.tx_aborted_errors++;
1732
1733 spin_lock_irqsave(&info->lock,flags);
1734 tx_stop(info);
1735 spin_unlock_irqrestore(&info->lock,flags);
1736
1737 netif_wake_queue(dev);
1738}
1739
1740/**
1741 * called by device driver when transmit completes
1742 * reenable network layer transmit if stopped
1743 *
1744 * info pointer to device instance information
1745 */
1746static void hdlcdev_tx_done(struct slgt_info *info)
1747{
1748 if (netif_queue_stopped(info->netdev))
1749 netif_wake_queue(info->netdev);
1750}
1751
1752/**
1753 * called by device driver when frame received
1754 * pass frame to network layer
1755 *
1756 * info pointer to device instance information
1757 * buf pointer to buffer contianing frame data
1758 * size count of data bytes in buf
1759 */
1760static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1761{
1762 struct sk_buff *skb = dev_alloc_skb(size);
1763 struct net_device *dev = info->netdev;
1764
1765 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1766
1767 if (skb == NULL) {
1768 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1769 dev->stats.rx_dropped++;
1770 return;
1771 }
1772
1773 memcpy(skb_put(skb, size), buf, size);
1774
1775 skb->protocol = hdlc_type_trans(skb, dev);
1776
1777 dev->stats.rx_packets++;
1778 dev->stats.rx_bytes += size;
1779
1780 netif_rx(skb);
1781}
1782
1783static const struct net_device_ops hdlcdev_ops = {
1784 .ndo_open = hdlcdev_open,
1785 .ndo_stop = hdlcdev_close,
1786 .ndo_change_mtu = hdlc_change_mtu,
1787 .ndo_start_xmit = hdlc_start_xmit,
1788 .ndo_do_ioctl = hdlcdev_ioctl,
1789 .ndo_tx_timeout = hdlcdev_tx_timeout,
1790};
1791
1792/**
1793 * called by device driver when adding device instance
1794 * do generic HDLC initialization
1795 *
1796 * info pointer to device instance information
1797 *
1798 * returns 0 if success, otherwise error code
1799 */
1800static int hdlcdev_init(struct slgt_info *info)
1801{
1802 int rc;
1803 struct net_device *dev;
1804 hdlc_device *hdlc;
1805
1806 /* allocate and initialize network and HDLC layer objects */
1807
1808 if (!(dev = alloc_hdlcdev(info))) {
1809 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1810 return -ENOMEM;
1811 }
1812
1813 /* for network layer reporting purposes only */
1814 dev->mem_start = info->phys_reg_addr;
1815 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1816 dev->irq = info->irq_level;
1817
1818 /* network layer callbacks and settings */
1819 dev->netdev_ops = &hdlcdev_ops;
1820 dev->watchdog_timeo = 10 * HZ;
1821 dev->tx_queue_len = 50;
1822
1823 /* generic HDLC layer callbacks and settings */
1824 hdlc = dev_to_hdlc(dev);
1825 hdlc->attach = hdlcdev_attach;
1826 hdlc->xmit = hdlcdev_xmit;
1827
1828 /* register objects with HDLC layer */
1829 if ((rc = register_hdlc_device(dev))) {
1830 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1831 free_netdev(dev);
1832 return rc;
1833 }
1834
1835 info->netdev = dev;
1836 return 0;
1837}
1838
1839/**
1840 * called by device driver when removing device instance
1841 * do generic HDLC cleanup
1842 *
1843 * info pointer to device instance information
1844 */
1845static void hdlcdev_exit(struct slgt_info *info)
1846{
1847 unregister_hdlc_device(info->netdev);
1848 free_netdev(info->netdev);
1849 info->netdev = NULL;
1850}
1851
1852#endif /* ifdef CONFIG_HDLC */
1853
1854/*
1855 * get async data from rx DMA buffers
1856 */
1857static void rx_async(struct slgt_info *info)
1858{
1859 struct tty_struct *tty = info->port.tty;
1860 struct mgsl_icount *icount = &info->icount;
1861 unsigned int start, end;
1862 unsigned char *p;
1863 unsigned char status;
1864 struct slgt_desc *bufs = info->rbufs;
1865 int i, count;
1866 int chars = 0;
1867 int stat;
1868 unsigned char ch;
1869
1870 start = end = info->rbuf_current;
1871
1872 while(desc_complete(bufs[end])) {
1873 count = desc_count(bufs[end]) - info->rbuf_index;
1874 p = bufs[end].buf + info->rbuf_index;
1875
1876 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1877 DBGDATA(info, p, count, "rx");
1878
1879 for(i=0 ; i < count; i+=2, p+=2) {
1880 ch = *p;
1881 icount->rx++;
1882
1883 stat = 0;
1884
1885 if ((status = *(p+1) & (BIT1 + BIT0))) {
1886 if (status & BIT1)
1887 icount->parity++;
1888 else if (status & BIT0)
1889 icount->frame++;
1890 /* discard char if tty control flags say so */
1891 if (status & info->ignore_status_mask)
1892 continue;
1893 if (status & BIT1)
1894 stat = TTY_PARITY;
1895 else if (status & BIT0)
1896 stat = TTY_FRAME;
1897 }
1898 if (tty) {
1899 tty_insert_flip_char(tty, ch, stat);
1900 chars++;
1901 }
1902 }
1903
1904 if (i < count) {
1905 /* receive buffer not completed */
1906 info->rbuf_index += i;
1907 mod_timer(&info->rx_timer, jiffies + 1);
1908 break;
1909 }
1910
1911 info->rbuf_index = 0;
1912 free_rbufs(info, end, end);
1913
1914 if (++end == info->rbuf_count)
1915 end = 0;
1916
1917 /* if entire list searched then no frame available */
1918 if (end == start)
1919 break;
1920 }
1921
1922 if (tty && chars)
1923 tty_flip_buffer_push(tty);
1924}
1925
1926/*
1927 * return next bottom half action to perform
1928 */
1929static int bh_action(struct slgt_info *info)
1930{
1931 unsigned long flags;
1932 int rc;
1933
1934 spin_lock_irqsave(&info->lock,flags);
1935
1936 if (info->pending_bh & BH_RECEIVE) {
1937 info->pending_bh &= ~BH_RECEIVE;
1938 rc = BH_RECEIVE;
1939 } else if (info->pending_bh & BH_TRANSMIT) {
1940 info->pending_bh &= ~BH_TRANSMIT;
1941 rc = BH_TRANSMIT;
1942 } else if (info->pending_bh & BH_STATUS) {
1943 info->pending_bh &= ~BH_STATUS;
1944 rc = BH_STATUS;
1945 } else {
1946 /* Mark BH routine as complete */
1947 info->bh_running = false;
1948 info->bh_requested = false;
1949 rc = 0;
1950 }
1951
1952 spin_unlock_irqrestore(&info->lock,flags);
1953
1954 return rc;
1955}
1956
1957/*
1958 * perform bottom half processing
1959 */
1960static void bh_handler(struct work_struct *work)
1961{
1962 struct slgt_info *info = container_of(work, struct slgt_info, task);
1963 int action;
1964
1965 if (!info)
1966 return;
1967 info->bh_running = true;
1968
1969 while((action = bh_action(info))) {
1970 switch (action) {
1971 case BH_RECEIVE:
1972 DBGBH(("%s bh receive\n", info->device_name));
1973 switch(info->params.mode) {
1974 case MGSL_MODE_ASYNC:
1975 rx_async(info);
1976 break;
1977 case MGSL_MODE_HDLC:
1978 while(rx_get_frame(info));
1979 break;
1980 case MGSL_MODE_RAW:
1981 case MGSL_MODE_MONOSYNC:
1982 case MGSL_MODE_BISYNC:
1983 case MGSL_MODE_XSYNC:
1984 while(rx_get_buf(info));
1985 break;
1986 }
1987 /* restart receiver if rx DMA buffers exhausted */
1988 if (info->rx_restart)
1989 rx_start(info);
1990 break;
1991 case BH_TRANSMIT:
1992 bh_transmit(info);
1993 break;
1994 case BH_STATUS:
1995 DBGBH(("%s bh status\n", info->device_name));
1996 info->ri_chkcount = 0;
1997 info->dsr_chkcount = 0;
1998 info->dcd_chkcount = 0;
1999 info->cts_chkcount = 0;
2000 break;
2001 default:
2002 DBGBH(("%s unknown action\n", info->device_name));
2003 break;
2004 }
2005 }
2006 DBGBH(("%s bh_handler exit\n", info->device_name));
2007}
2008
2009static void bh_transmit(struct slgt_info *info)
2010{
2011 struct tty_struct *tty = info->port.tty;
2012
2013 DBGBH(("%s bh_transmit\n", info->device_name));
2014 if (tty)
2015 tty_wakeup(tty);
2016}
2017
2018static void dsr_change(struct slgt_info *info, unsigned short status)
2019{
2020 if (status & BIT3) {
2021 info->signals |= SerialSignal_DSR;
2022 info->input_signal_events.dsr_up++;
2023 } else {
2024 info->signals &= ~SerialSignal_DSR;
2025 info->input_signal_events.dsr_down++;
2026 }
2027 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2028 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2029 slgt_irq_off(info, IRQ_DSR);
2030 return;
2031 }
2032 info->icount.dsr++;
2033 wake_up_interruptible(&info->status_event_wait_q);
2034 wake_up_interruptible(&info->event_wait_q);
2035 info->pending_bh |= BH_STATUS;
2036}
2037
2038static void cts_change(struct slgt_info *info, unsigned short status)
2039{
2040 if (status & BIT2) {
2041 info->signals |= SerialSignal_CTS;
2042 info->input_signal_events.cts_up++;
2043 } else {
2044 info->signals &= ~SerialSignal_CTS;
2045 info->input_signal_events.cts_down++;
2046 }
2047 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2048 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2049 slgt_irq_off(info, IRQ_CTS);
2050 return;
2051 }
2052 info->icount.cts++;
2053 wake_up_interruptible(&info->status_event_wait_q);
2054 wake_up_interruptible(&info->event_wait_q);
2055 info->pending_bh |= BH_STATUS;
2056
2057 if (info->port.flags & ASYNC_CTS_FLOW) {
2058 if (info->port.tty) {
2059 if (info->port.tty->hw_stopped) {
2060 if (info->signals & SerialSignal_CTS) {
2061 info->port.tty->hw_stopped = 0;
2062 info->pending_bh |= BH_TRANSMIT;
2063 return;
2064 }
2065 } else {
2066 if (!(info->signals & SerialSignal_CTS))
2067 info->port.tty->hw_stopped = 1;
2068 }
2069 }
2070 }
2071}
2072
2073static void dcd_change(struct slgt_info *info, unsigned short status)
2074{
2075 if (status & BIT1) {
2076 info->signals |= SerialSignal_DCD;
2077 info->input_signal_events.dcd_up++;
2078 } else {
2079 info->signals &= ~SerialSignal_DCD;
2080 info->input_signal_events.dcd_down++;
2081 }
2082 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2083 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2084 slgt_irq_off(info, IRQ_DCD);
2085 return;
2086 }
2087 info->icount.dcd++;
2088#if SYNCLINK_GENERIC_HDLC
2089 if (info->netcount) {
2090 if (info->signals & SerialSignal_DCD)
2091 netif_carrier_on(info->netdev);
2092 else
2093 netif_carrier_off(info->netdev);
2094 }
2095#endif
2096 wake_up_interruptible(&info->status_event_wait_q);
2097 wake_up_interruptible(&info->event_wait_q);
2098 info->pending_bh |= BH_STATUS;
2099
2100 if (info->port.flags & ASYNC_CHECK_CD) {
2101 if (info->signals & SerialSignal_DCD)
2102 wake_up_interruptible(&info->port.open_wait);
2103 else {
2104 if (info->port.tty)
2105 tty_hangup(info->port.tty);
2106 }
2107 }
2108}
2109
2110static void ri_change(struct slgt_info *info, unsigned short status)
2111{
2112 if (status & BIT0) {
2113 info->signals |= SerialSignal_RI;
2114 info->input_signal_events.ri_up++;
2115 } else {
2116 info->signals &= ~SerialSignal_RI;
2117 info->input_signal_events.ri_down++;
2118 }
2119 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2120 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2121 slgt_irq_off(info, IRQ_RI);
2122 return;
2123 }
2124 info->icount.rng++;
2125 wake_up_interruptible(&info->status_event_wait_q);
2126 wake_up_interruptible(&info->event_wait_q);
2127 info->pending_bh |= BH_STATUS;
2128}
2129
2130static void isr_rxdata(struct slgt_info *info)
2131{
2132 unsigned int count = info->rbuf_fill_count;
2133 unsigned int i = info->rbuf_fill_index;
2134 unsigned short reg;
2135
2136 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2137 reg = rd_reg16(info, RDR);
2138 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2139 if (desc_complete(info->rbufs[i])) {
2140 /* all buffers full */
2141 rx_stop(info);
2142 info->rx_restart = 1;
2143 continue;
2144 }
2145 info->rbufs[i].buf[count++] = (unsigned char)reg;
2146 /* async mode saves status byte to buffer for each data byte */
2147 if (info->params.mode == MGSL_MODE_ASYNC)
2148 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2149 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2150 /* buffer full or end of frame */
2151 set_desc_count(info->rbufs[i], count);
2152 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2153 info->rbuf_fill_count = count = 0;
2154 if (++i == info->rbuf_count)
2155 i = 0;
2156 info->pending_bh |= BH_RECEIVE;
2157 }
2158 }
2159
2160 info->rbuf_fill_index = i;
2161 info->rbuf_fill_count = count;
2162}
2163
2164static void isr_serial(struct slgt_info *info)
2165{
2166 unsigned short status = rd_reg16(info, SSR);
2167
2168 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2169
2170 wr_reg16(info, SSR, status); /* clear pending */
2171
2172 info->irq_occurred = true;
2173
2174 if (info->params.mode == MGSL_MODE_ASYNC) {
2175 if (status & IRQ_TXIDLE) {
2176 if (info->tx_active)
2177 isr_txeom(info, status);
2178 }
2179 if (info->rx_pio && (status & IRQ_RXDATA))
2180 isr_rxdata(info);
2181 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2182 info->icount.brk++;
2183 /* process break detection if tty control allows */
2184 if (info->port.tty) {
2185 if (!(status & info->ignore_status_mask)) {
2186 if (info->read_status_mask & MASK_BREAK) {
2187 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2188 if (info->port.flags & ASYNC_SAK)
2189 do_SAK(info->port.tty);
2190 }
2191 }
2192 }
2193 }
2194 } else {
2195 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2196 isr_txeom(info, status);
2197 if (info->rx_pio && (status & IRQ_RXDATA))
2198 isr_rxdata(info);
2199 if (status & IRQ_RXIDLE) {
2200 if (status & RXIDLE)
2201 info->icount.rxidle++;
2202 else
2203 info->icount.exithunt++;
2204 wake_up_interruptible(&info->event_wait_q);
2205 }
2206
2207 if (status & IRQ_RXOVER)
2208 rx_start(info);
2209 }
2210
2211 if (status & IRQ_DSR)
2212 dsr_change(info, status);
2213 if (status & IRQ_CTS)
2214 cts_change(info, status);
2215 if (status & IRQ_DCD)
2216 dcd_change(info, status);
2217 if (status & IRQ_RI)
2218 ri_change(info, status);
2219}
2220
2221static void isr_rdma(struct slgt_info *info)
2222{
2223 unsigned int status = rd_reg32(info, RDCSR);
2224
2225 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2226
2227 /* RDCSR (rx DMA control/status)
2228 *
2229 * 31..07 reserved
2230 * 06 save status byte to DMA buffer
2231 * 05 error
2232 * 04 eol (end of list)
2233 * 03 eob (end of buffer)
2234 * 02 IRQ enable
2235 * 01 reset
2236 * 00 enable
2237 */
2238 wr_reg32(info, RDCSR, status); /* clear pending */
2239
2240 if (status & (BIT5 + BIT4)) {
2241 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2242 info->rx_restart = true;
2243 }
2244 info->pending_bh |= BH_RECEIVE;
2245}
2246
2247static void isr_tdma(struct slgt_info *info)
2248{
2249 unsigned int status = rd_reg32(info, TDCSR);
2250
2251 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2252
2253 /* TDCSR (tx DMA control/status)
2254 *
2255 * 31..06 reserved
2256 * 05 error
2257 * 04 eol (end of list)
2258 * 03 eob (end of buffer)
2259 * 02 IRQ enable
2260 * 01 reset
2261 * 00 enable
2262 */
2263 wr_reg32(info, TDCSR, status); /* clear pending */
2264
2265 if (status & (BIT5 + BIT4 + BIT3)) {
2266 // another transmit buffer has completed
2267 // run bottom half to get more send data from user
2268 info->pending_bh |= BH_TRANSMIT;
2269 }
2270}
2271
2272/*
2273 * return true if there are unsent tx DMA buffers, otherwise false
2274 *
2275 * if there are unsent buffers then info->tbuf_start
2276 * is set to index of first unsent buffer
2277 */
2278static bool unsent_tbufs(struct slgt_info *info)
2279{
2280 unsigned int i = info->tbuf_current;
2281 bool rc = false;
2282
2283 /*
2284 * search backwards from last loaded buffer (precedes tbuf_current)
2285 * for first unsent buffer (desc_count > 0)
2286 */
2287
2288 do {
2289 if (i)
2290 i--;
2291 else
2292 i = info->tbuf_count - 1;
2293 if (!desc_count(info->tbufs[i]))
2294 break;
2295 info->tbuf_start = i;
2296 rc = true;
2297 } while (i != info->tbuf_current);
2298
2299 return rc;
2300}
2301
2302static void isr_txeom(struct slgt_info *info, unsigned short status)
2303{
2304 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2305
2306 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2307 tdma_reset(info);
2308 if (status & IRQ_TXUNDER) {
2309 unsigned short val = rd_reg16(info, TCR);
2310 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2311 wr_reg16(info, TCR, val); /* clear reset bit */
2312 }
2313
2314 if (info->tx_active) {
2315 if (info->params.mode != MGSL_MODE_ASYNC) {
2316 if (status & IRQ_TXUNDER)
2317 info->icount.txunder++;
2318 else if (status & IRQ_TXIDLE)
2319 info->icount.txok++;
2320 }
2321
2322 if (unsent_tbufs(info)) {
2323 tx_start(info);
2324 update_tx_timer(info);
2325 return;
2326 }
2327 info->tx_active = false;
2328
2329 del_timer(&info->tx_timer);
2330
2331 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2332 info->signals &= ~SerialSignal_RTS;
2333 info->drop_rts_on_tx_done = false;
2334 set_signals(info);
2335 }
2336
2337#if SYNCLINK_GENERIC_HDLC
2338 if (info->netcount)
2339 hdlcdev_tx_done(info);
2340 else
2341#endif
2342 {
2343 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2344 tx_stop(info);
2345 return;
2346 }
2347 info->pending_bh |= BH_TRANSMIT;
2348 }
2349 }
2350}
2351
2352static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2353{
2354 struct cond_wait *w, *prev;
2355
2356 /* wake processes waiting for specific transitions */
2357 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2358 if (w->data & changed) {
2359 w->data = state;
2360 wake_up_interruptible(&w->q);
2361 if (prev != NULL)
2362 prev->next = w->next;
2363 else
2364 info->gpio_wait_q = w->next;
2365 } else
2366 prev = w;
2367 }
2368}
2369
2370/* interrupt service routine
2371 *
2372 * irq interrupt number
2373 * dev_id device ID supplied during interrupt registration
2374 */
2375static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2376{
2377 struct slgt_info *info = dev_id;
2378 unsigned int gsr;
2379 unsigned int i;
2380
2381 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2382
2383 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2384 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2385 info->irq_occurred = true;
2386 for(i=0; i < info->port_count ; i++) {
2387 if (info->port_array[i] == NULL)
2388 continue;
2389 spin_lock(&info->port_array[i]->lock);
2390 if (gsr & (BIT8 << i))
2391 isr_serial(info->port_array[i]);
2392 if (gsr & (BIT16 << (i*2)))
2393 isr_rdma(info->port_array[i]);
2394 if (gsr & (BIT17 << (i*2)))
2395 isr_tdma(info->port_array[i]);
2396 spin_unlock(&info->port_array[i]->lock);
2397 }
2398 }
2399
2400 if (info->gpio_present) {
2401 unsigned int state;
2402 unsigned int changed;
2403 spin_lock(&info->lock);
2404 while ((changed = rd_reg32(info, IOSR)) != 0) {
2405 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2406 /* read latched state of GPIO signals */
2407 state = rd_reg32(info, IOVR);
2408 /* clear pending GPIO interrupt bits */
2409 wr_reg32(info, IOSR, changed);
2410 for (i=0 ; i < info->port_count ; i++) {
2411 if (info->port_array[i] != NULL)
2412 isr_gpio(info->port_array[i], changed, state);
2413 }
2414 }
2415 spin_unlock(&info->lock);
2416 }
2417
2418 for(i=0; i < info->port_count ; i++) {
2419 struct slgt_info *port = info->port_array[i];
2420 if (port == NULL)
2421 continue;
2422 spin_lock(&port->lock);
2423 if ((port->port.count || port->netcount) &&
2424 port->pending_bh && !port->bh_running &&
2425 !port->bh_requested) {
2426 DBGISR(("%s bh queued\n", port->device_name));
2427 schedule_work(&port->task);
2428 port->bh_requested = true;
2429 }
2430 spin_unlock(&port->lock);
2431 }
2432
2433 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2434 return IRQ_HANDLED;
2435}
2436
2437static int startup(struct slgt_info *info)
2438{
2439 DBGINFO(("%s startup\n", info->device_name));
2440
2441 if (info->port.flags & ASYNC_INITIALIZED)
2442 return 0;
2443
2444 if (!info->tx_buf) {
2445 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2446 if (!info->tx_buf) {
2447 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2448 return -ENOMEM;
2449 }
2450 }
2451
2452 info->pending_bh = 0;
2453
2454 memset(&info->icount, 0, sizeof(info->icount));
2455
2456 /* program hardware for current parameters */
2457 change_params(info);
2458
2459 if (info->port.tty)
2460 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2461
2462 info->port.flags |= ASYNC_INITIALIZED;
2463
2464 return 0;
2465}
2466
2467/*
2468 * called by close() and hangup() to shutdown hardware
2469 */
2470static void shutdown(struct slgt_info *info)
2471{
2472 unsigned long flags;
2473
2474 if (!(info->port.flags & ASYNC_INITIALIZED))
2475 return;
2476
2477 DBGINFO(("%s shutdown\n", info->device_name));
2478
2479 /* clear status wait queue because status changes */
2480 /* can't happen after shutting down the hardware */
2481 wake_up_interruptible(&info->status_event_wait_q);
2482 wake_up_interruptible(&info->event_wait_q);
2483
2484 del_timer_sync(&info->tx_timer);
2485 del_timer_sync(&info->rx_timer);
2486
2487 kfree(info->tx_buf);
2488 info->tx_buf = NULL;
2489
2490 spin_lock_irqsave(&info->lock,flags);
2491
2492 tx_stop(info);
2493 rx_stop(info);
2494
2495 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2496
2497 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2498 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2499 set_signals(info);
2500 }
2501
2502 flush_cond_wait(&info->gpio_wait_q);
2503
2504 spin_unlock_irqrestore(&info->lock,flags);
2505
2506 if (info->port.tty)
2507 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2508
2509 info->port.flags &= ~ASYNC_INITIALIZED;
2510}
2511
2512static void program_hw(struct slgt_info *info)
2513{
2514 unsigned long flags;
2515
2516 spin_lock_irqsave(&info->lock,flags);
2517
2518 rx_stop(info);
2519 tx_stop(info);
2520
2521 if (info->params.mode != MGSL_MODE_ASYNC ||
2522 info->netcount)
2523 sync_mode(info);
2524 else
2525 async_mode(info);
2526
2527 set_signals(info);
2528
2529 info->dcd_chkcount = 0;
2530 info->cts_chkcount = 0;
2531 info->ri_chkcount = 0;
2532 info->dsr_chkcount = 0;
2533
2534 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2535 get_signals(info);
2536
2537 if (info->netcount ||
2538 (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2539 rx_start(info);
2540
2541 spin_unlock_irqrestore(&info->lock,flags);
2542}
2543
2544/*
2545 * reconfigure adapter based on new parameters
2546 */
2547static void change_params(struct slgt_info *info)
2548{
2549 unsigned cflag;
2550 int bits_per_char;
2551
2552 if (!info->port.tty || !info->port.tty->termios)
2553 return;
2554 DBGINFO(("%s change_params\n", info->device_name));
2555
2556 cflag = info->port.tty->termios->c_cflag;
2557
2558 /* if B0 rate (hangup) specified then negate DTR and RTS */
2559 /* otherwise assert DTR and RTS */
2560 if (cflag & CBAUD)
2561 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2562 else
2563 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2564
2565 /* byte size and parity */
2566
2567 switch (cflag & CSIZE) {
2568 case CS5: info->params.data_bits = 5; break;
2569 case CS6: info->params.data_bits = 6; break;
2570 case CS7: info->params.data_bits = 7; break;
2571 case CS8: info->params.data_bits = 8; break;
2572 default: info->params.data_bits = 7; break;
2573 }
2574
2575 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2576
2577 if (cflag & PARENB)
2578 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2579 else
2580 info->params.parity = ASYNC_PARITY_NONE;
2581
2582 /* calculate number of jiffies to transmit a full
2583 * FIFO (32 bytes) at specified data rate
2584 */
2585 bits_per_char = info->params.data_bits +
2586 info->params.stop_bits + 1;
2587
2588 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2589
2590 if (info->params.data_rate) {
2591 info->timeout = (32*HZ*bits_per_char) /
2592 info->params.data_rate;
2593 }
2594 info->timeout += HZ/50; /* Add .02 seconds of slop */
2595
2596 if (cflag & CRTSCTS)
2597 info->port.flags |= ASYNC_CTS_FLOW;
2598 else
2599 info->port.flags &= ~ASYNC_CTS_FLOW;
2600
2601 if (cflag & CLOCAL)
2602 info->port.flags &= ~ASYNC_CHECK_CD;
2603 else
2604 info->port.flags |= ASYNC_CHECK_CD;
2605
2606 /* process tty input control flags */
2607
2608 info->read_status_mask = IRQ_RXOVER;
2609 if (I_INPCK(info->port.tty))
2610 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2611 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2612 info->read_status_mask |= MASK_BREAK;
2613 if (I_IGNPAR(info->port.tty))
2614 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2615 if (I_IGNBRK(info->port.tty)) {
2616 info->ignore_status_mask |= MASK_BREAK;
2617 /* If ignoring parity and break indicators, ignore
2618 * overruns too. (For real raw support).
2619 */
2620 if (I_IGNPAR(info->port.tty))
2621 info->ignore_status_mask |= MASK_OVERRUN;
2622 }
2623
2624 program_hw(info);
2625}
2626
2627static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2628{
2629 DBGINFO(("%s get_stats\n", info->device_name));
2630 if (!user_icount) {
2631 memset(&info->icount, 0, sizeof(info->icount));
2632 } else {
2633 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2634 return -EFAULT;
2635 }
2636 return 0;
2637}
2638
2639static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2640{
2641 DBGINFO(("%s get_params\n", info->device_name));
2642 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2643 return -EFAULT;
2644 return 0;
2645}
2646
2647static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2648{
2649 unsigned long flags;
2650 MGSL_PARAMS tmp_params;
2651
2652 DBGINFO(("%s set_params\n", info->device_name));
2653 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2654 return -EFAULT;
2655
2656 spin_lock_irqsave(&info->lock, flags);
2657 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2658 info->base_clock = tmp_params.clock_speed;
2659 else
2660 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2661 spin_unlock_irqrestore(&info->lock, flags);
2662
2663 program_hw(info);
2664
2665 return 0;
2666}
2667
2668static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2669{
2670 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2671 if (put_user(info->idle_mode, idle_mode))
2672 return -EFAULT;
2673 return 0;
2674}
2675
2676static int set_txidle(struct slgt_info *info, int idle_mode)
2677{
2678 unsigned long flags;
2679 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2680 spin_lock_irqsave(&info->lock,flags);
2681 info->idle_mode = idle_mode;
2682 if (info->params.mode != MGSL_MODE_ASYNC)
2683 tx_set_idle(info);
2684 spin_unlock_irqrestore(&info->lock,flags);
2685 return 0;
2686}
2687
2688static int tx_enable(struct slgt_info *info, int enable)
2689{
2690 unsigned long flags;
2691 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2692 spin_lock_irqsave(&info->lock,flags);
2693 if (enable) {
2694 if (!info->tx_enabled)
2695 tx_start(info);
2696 } else {
2697 if (info->tx_enabled)
2698 tx_stop(info);
2699 }
2700 spin_unlock_irqrestore(&info->lock,flags);
2701 return 0;
2702}
2703
2704/*
2705 * abort transmit HDLC frame
2706 */
2707static int tx_abort(struct slgt_info *info)
2708{
2709 unsigned long flags;
2710 DBGINFO(("%s tx_abort\n", info->device_name));
2711 spin_lock_irqsave(&info->lock,flags);
2712 tdma_reset(info);
2713 spin_unlock_irqrestore(&info->lock,flags);
2714 return 0;
2715}
2716
2717static int rx_enable(struct slgt_info *info, int enable)
2718{
2719 unsigned long flags;
2720 unsigned int rbuf_fill_level;
2721 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2722 spin_lock_irqsave(&info->lock,flags);
2723 /*
2724 * enable[31..16] = receive DMA buffer fill level
2725 * 0 = noop (leave fill level unchanged)
2726 * fill level must be multiple of 4 and <= buffer size
2727 */
2728 rbuf_fill_level = ((unsigned int)enable) >> 16;
2729 if (rbuf_fill_level) {
2730 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2731 spin_unlock_irqrestore(&info->lock, flags);
2732 return -EINVAL;
2733 }
2734 info->rbuf_fill_level = rbuf_fill_level;
2735 if (rbuf_fill_level < 128)
2736 info->rx_pio = 1; /* PIO mode */
2737 else
2738 info->rx_pio = 0; /* DMA mode */
2739 rx_stop(info); /* restart receiver to use new fill level */
2740 }
2741
2742 /*
2743 * enable[1..0] = receiver enable command
2744 * 0 = disable
2745 * 1 = enable
2746 * 2 = enable or force hunt mode if already enabled
2747 */
2748 enable &= 3;
2749 if (enable) {
2750 if (!info->rx_enabled)
2751 rx_start(info);
2752 else if (enable == 2) {
2753 /* force hunt mode (write 1 to RCR[3]) */
2754 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2755 }
2756 } else {
2757 if (info->rx_enabled)
2758 rx_stop(info);
2759 }
2760 spin_unlock_irqrestore(&info->lock,flags);
2761 return 0;
2762}
2763
2764/*
2765 * wait for specified event to occur
2766 */
2767static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2768{
2769 unsigned long flags;
2770 int s;
2771 int rc=0;
2772 struct mgsl_icount cprev, cnow;
2773 int events;
2774 int mask;
2775 struct _input_signal_events oldsigs, newsigs;
2776 DECLARE_WAITQUEUE(wait, current);
2777
2778 if (get_user(mask, mask_ptr))
2779 return -EFAULT;
2780
2781 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2782
2783 spin_lock_irqsave(&info->lock,flags);
2784
2785 /* return immediately if state matches requested events */
2786 get_signals(info);
2787 s = info->signals;
2788
2789 events = mask &
2790 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2791 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2792 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2793 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2794 if (events) {
2795 spin_unlock_irqrestore(&info->lock,flags);
2796 goto exit;
2797 }
2798
2799 /* save current irq counts */
2800 cprev = info->icount;
2801 oldsigs = info->input_signal_events;
2802
2803 /* enable hunt and idle irqs if needed */
2804 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2805 unsigned short val = rd_reg16(info, SCR);
2806 if (!(val & IRQ_RXIDLE))
2807 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2808 }
2809
2810 set_current_state(TASK_INTERRUPTIBLE);
2811 add_wait_queue(&info->event_wait_q, &wait);
2812
2813 spin_unlock_irqrestore(&info->lock,flags);
2814
2815 for(;;) {
2816 schedule();
2817 if (signal_pending(current)) {
2818 rc = -ERESTARTSYS;
2819 break;
2820 }
2821
2822 /* get current irq counts */
2823 spin_lock_irqsave(&info->lock,flags);
2824 cnow = info->icount;
2825 newsigs = info->input_signal_events;
2826 set_current_state(TASK_INTERRUPTIBLE);
2827 spin_unlock_irqrestore(&info->lock,flags);
2828
2829 /* if no change, wait aborted for some reason */
2830 if (newsigs.dsr_up == oldsigs.dsr_up &&
2831 newsigs.dsr_down == oldsigs.dsr_down &&
2832 newsigs.dcd_up == oldsigs.dcd_up &&
2833 newsigs.dcd_down == oldsigs.dcd_down &&
2834 newsigs.cts_up == oldsigs.cts_up &&
2835 newsigs.cts_down == oldsigs.cts_down &&
2836 newsigs.ri_up == oldsigs.ri_up &&
2837 newsigs.ri_down == oldsigs.ri_down &&
2838 cnow.exithunt == cprev.exithunt &&
2839 cnow.rxidle == cprev.rxidle) {
2840 rc = -EIO;
2841 break;
2842 }
2843
2844 events = mask &
2845 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2846 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2847 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2848 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2849 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2850 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2851 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2852 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2853 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2854 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2855 if (events)
2856 break;
2857
2858 cprev = cnow;
2859 oldsigs = newsigs;
2860 }
2861
2862 remove_wait_queue(&info->event_wait_q, &wait);
2863 set_current_state(TASK_RUNNING);
2864
2865
2866 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2867 spin_lock_irqsave(&info->lock,flags);
2868 if (!waitqueue_active(&info->event_wait_q)) {
2869 /* disable enable exit hunt mode/idle rcvd IRQs */
2870 wr_reg16(info, SCR,
2871 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2872 }
2873 spin_unlock_irqrestore(&info->lock,flags);
2874 }
2875exit:
2876 if (rc == 0)
2877 rc = put_user(events, mask_ptr);
2878 return rc;
2879}
2880
2881static int get_interface(struct slgt_info *info, int __user *if_mode)
2882{
2883 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2884 if (put_user(info->if_mode, if_mode))
2885 return -EFAULT;
2886 return 0;
2887}
2888
2889static int set_interface(struct slgt_info *info, int if_mode)
2890{
2891 unsigned long flags;
2892 unsigned short val;
2893
2894 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2895 spin_lock_irqsave(&info->lock,flags);
2896 info->if_mode = if_mode;
2897
2898 msc_set_vcr(info);
2899
2900 /* TCR (tx control) 07 1=RTS driver control */
2901 val = rd_reg16(info, TCR);
2902 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2903 val |= BIT7;
2904 else
2905 val &= ~BIT7;
2906 wr_reg16(info, TCR, val);
2907
2908 spin_unlock_irqrestore(&info->lock,flags);
2909 return 0;
2910}
2911
2912static int get_xsync(struct slgt_info *info, int __user *xsync)
2913{
2914 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2915 if (put_user(info->xsync, xsync))
2916 return -EFAULT;
2917 return 0;
2918}
2919
2920/*
2921 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2922 *
2923 * sync pattern is contained in least significant bytes of value
2924 * most significant byte of sync pattern is oldest (1st sent/detected)
2925 */
2926static int set_xsync(struct slgt_info *info, int xsync)
2927{
2928 unsigned long flags;
2929
2930 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2931 spin_lock_irqsave(&info->lock, flags);
2932 info->xsync = xsync;
2933 wr_reg32(info, XSR, xsync);
2934 spin_unlock_irqrestore(&info->lock, flags);
2935 return 0;
2936}
2937
2938static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2939{
2940 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2941 if (put_user(info->xctrl, xctrl))
2942 return -EFAULT;
2943 return 0;
2944}
2945
2946/*
2947 * set extended control options
2948 *
2949 * xctrl[31:19] reserved, must be zero
2950 * xctrl[18:17] extended sync pattern length in bytes
2951 * 00 = 1 byte in xsr[7:0]
2952 * 01 = 2 bytes in xsr[15:0]
2953 * 10 = 3 bytes in xsr[23:0]
2954 * 11 = 4 bytes in xsr[31:0]
2955 * xctrl[16] 1 = enable terminal count, 0=disabled
2956 * xctrl[15:0] receive terminal count for fixed length packets
2957 * value is count minus one (0 = 1 byte packet)
2958 * when terminal count is reached, receiver
2959 * automatically returns to hunt mode and receive
2960 * FIFO contents are flushed to DMA buffers with
2961 * end of frame (EOF) status
2962 */
2963static int set_xctrl(struct slgt_info *info, int xctrl)
2964{
2965 unsigned long flags;
2966
2967 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2968 spin_lock_irqsave(&info->lock, flags);
2969 info->xctrl = xctrl;
2970 wr_reg32(info, XCR, xctrl);
2971 spin_unlock_irqrestore(&info->lock, flags);
2972 return 0;
2973}
2974
2975/*
2976 * set general purpose IO pin state and direction
2977 *
2978 * user_gpio fields:
2979 * state each bit indicates a pin state
2980 * smask set bit indicates pin state to set
2981 * dir each bit indicates a pin direction (0=input, 1=output)
2982 * dmask set bit indicates pin direction to set
2983 */
2984static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2985{
2986 unsigned long flags;
2987 struct gpio_desc gpio;
2988 __u32 data;
2989
2990 if (!info->gpio_present)
2991 return -EINVAL;
2992 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2993 return -EFAULT;
2994 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2995 info->device_name, gpio.state, gpio.smask,
2996 gpio.dir, gpio.dmask));
2997
2998 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2999 if (gpio.dmask) {
3000 data = rd_reg32(info, IODR);
3001 data |= gpio.dmask & gpio.dir;
3002 data &= ~(gpio.dmask & ~gpio.dir);
3003 wr_reg32(info, IODR, data);
3004 }
3005 if (gpio.smask) {
3006 data = rd_reg32(info, IOVR);
3007 data |= gpio.smask & gpio.state;
3008 data &= ~(gpio.smask & ~gpio.state);
3009 wr_reg32(info, IOVR, data);
3010 }
3011 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3012
3013 return 0;
3014}
3015
3016/*
3017 * get general purpose IO pin state and direction
3018 */
3019static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3020{
3021 struct gpio_desc gpio;
3022 if (!info->gpio_present)
3023 return -EINVAL;
3024 gpio.state = rd_reg32(info, IOVR);
3025 gpio.smask = 0xffffffff;
3026 gpio.dir = rd_reg32(info, IODR);
3027 gpio.dmask = 0xffffffff;
3028 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3029 return -EFAULT;
3030 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
3031 info->device_name, gpio.state, gpio.dir));
3032 return 0;
3033}
3034
3035/*
3036 * conditional wait facility
3037 */
3038static void init_cond_wait(struct cond_wait *w, unsigned int data)
3039{
3040 init_waitqueue_head(&w->q);
3041 init_waitqueue_entry(&w->wait, current);
3042 w->data = data;
3043}
3044
3045static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
3046{
3047 set_current_state(TASK_INTERRUPTIBLE);
3048 add_wait_queue(&w->q, &w->wait);
3049 w->next = *head;
3050 *head = w;
3051}
3052
3053static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
3054{
3055 struct cond_wait *w, *prev;
3056 remove_wait_queue(&cw->q, &cw->wait);
3057 set_current_state(TASK_RUNNING);
3058 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
3059 if (w == cw) {
3060 if (prev != NULL)
3061 prev->next = w->next;
3062 else
3063 *head = w->next;
3064 break;
3065 }
3066 }
3067}
3068
3069static void flush_cond_wait(struct cond_wait **head)
3070{
3071 while (*head != NULL) {
3072 wake_up_interruptible(&(*head)->q);
3073 *head = (*head)->next;
3074 }
3075}
3076
3077/*
3078 * wait for general purpose I/O pin(s) to enter specified state
3079 *
3080 * user_gpio fields:
3081 * state - bit indicates target pin state
3082 * smask - set bit indicates watched pin
3083 *
3084 * The wait ends when at least one watched pin enters the specified
3085 * state. When 0 (no error) is returned, user_gpio->state is set to the
3086 * state of all GPIO pins when the wait ends.
3087 *
3088 * Note: Each pin may be a dedicated input, dedicated output, or
3089 * configurable input/output. The number and configuration of pins
3090 * varies with the specific adapter model. Only input pins (dedicated
3091 * or configured) can be monitored with this function.
3092 */
3093static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
3094{
3095 unsigned long flags;
3096 int rc = 0;
3097 struct gpio_desc gpio;
3098 struct cond_wait wait;
3099 u32 state;
3100
3101 if (!info->gpio_present)
3102 return -EINVAL;
3103 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
3104 return -EFAULT;
3105 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
3106 info->device_name, gpio.state, gpio.smask));
3107 /* ignore output pins identified by set IODR bit */
3108 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
3109 return -EINVAL;
3110 init_cond_wait(&wait, gpio.smask);
3111
3112 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3113 /* enable interrupts for watched pins */
3114 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
3115 /* get current pin states */
3116 state = rd_reg32(info, IOVR);
3117
3118 if (gpio.smask & ~(state ^ gpio.state)) {
3119 /* already in target state */
3120 gpio.state = state;
3121 } else {
3122 /* wait for target state */
3123 add_cond_wait(&info->gpio_wait_q, &wait);
3124 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3125 schedule();
3126 if (signal_pending(current))
3127 rc = -ERESTARTSYS;
3128 else
3129 gpio.state = wait.data;
3130 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3131 remove_cond_wait(&info->gpio_wait_q, &wait);
3132 }
3133
3134 /* disable all GPIO interrupts if no waiting processes */
3135 if (info->gpio_wait_q == NULL)
3136 wr_reg32(info, IOER, 0);
3137 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3138
3139 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3140 rc = -EFAULT;
3141 return rc;
3142}
3143
3144static int modem_input_wait(struct slgt_info *info,int arg)
3145{
3146 unsigned long flags;
3147 int rc;
3148 struct mgsl_icount cprev, cnow;
3149 DECLARE_WAITQUEUE(wait, current);
3150
3151 /* save current irq counts */
3152 spin_lock_irqsave(&info->lock,flags);
3153 cprev = info->icount;
3154 add_wait_queue(&info->status_event_wait_q, &wait);
3155 set_current_state(TASK_INTERRUPTIBLE);
3156 spin_unlock_irqrestore(&info->lock,flags);
3157
3158 for(;;) {
3159 schedule();
3160 if (signal_pending(current)) {
3161 rc = -ERESTARTSYS;
3162 break;
3163 }
3164
3165 /* get new irq counts */
3166 spin_lock_irqsave(&info->lock,flags);
3167 cnow = info->icount;
3168 set_current_state(TASK_INTERRUPTIBLE);
3169 spin_unlock_irqrestore(&info->lock,flags);
3170
3171 /* if no change, wait aborted for some reason */
3172 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3173 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3174 rc = -EIO;
3175 break;
3176 }
3177
3178 /* check for change in caller specified modem input */
3179 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3180 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3181 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3182 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3183 rc = 0;
3184 break;
3185 }
3186
3187 cprev = cnow;
3188 }
3189 remove_wait_queue(&info->status_event_wait_q, &wait);
3190 set_current_state(TASK_RUNNING);
3191 return rc;
3192}
3193
3194/*
3195 * return state of serial control and status signals
3196 */
3197static int tiocmget(struct tty_struct *tty)
3198{
3199 struct slgt_info *info = tty->driver_data;
3200 unsigned int result;
3201 unsigned long flags;
3202
3203 spin_lock_irqsave(&info->lock,flags);
3204 get_signals(info);
3205 spin_unlock_irqrestore(&info->lock,flags);
3206
3207 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3208 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3209 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3210 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3211 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3212 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3213
3214 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3215 return result;
3216}
3217
3218/*
3219 * set modem control signals (DTR/RTS)
3220 *
3221 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3222 * TIOCMSET = set/clear signal values
3223 * value bit mask for command
3224 */
3225static int tiocmset(struct tty_struct *tty,
3226 unsigned int set, unsigned int clear)
3227{
3228 struct slgt_info *info = tty->driver_data;
3229 unsigned long flags;
3230
3231 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3232
3233 if (set & TIOCM_RTS)
3234 info->signals |= SerialSignal_RTS;
3235 if (set & TIOCM_DTR)
3236 info->signals |= SerialSignal_DTR;
3237 if (clear & TIOCM_RTS)
3238 info->signals &= ~SerialSignal_RTS;
3239 if (clear & TIOCM_DTR)
3240 info->signals &= ~SerialSignal_DTR;
3241
3242 spin_lock_irqsave(&info->lock,flags);
3243 set_signals(info);
3244 spin_unlock_irqrestore(&info->lock,flags);
3245 return 0;
3246}
3247
3248static int carrier_raised(struct tty_port *port)
3249{
3250 unsigned long flags;
3251 struct slgt_info *info = container_of(port, struct slgt_info, port);
3252
3253 spin_lock_irqsave(&info->lock,flags);
3254 get_signals(info);
3255 spin_unlock_irqrestore(&info->lock,flags);
3256 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3257}
3258
3259static void dtr_rts(struct tty_port *port, int on)
3260{
3261 unsigned long flags;
3262 struct slgt_info *info = container_of(port, struct slgt_info, port);
3263
3264 spin_lock_irqsave(&info->lock,flags);
3265 if (on)
3266 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3267 else
3268 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3269 set_signals(info);
3270 spin_unlock_irqrestore(&info->lock,flags);
3271}
3272
3273
3274/*
3275 * block current process until the device is ready to open
3276 */
3277static int block_til_ready(struct tty_struct *tty, struct file *filp,
3278 struct slgt_info *info)
3279{
3280 DECLARE_WAITQUEUE(wait, current);
3281 int retval;
3282 bool do_clocal = false;
3283 bool extra_count = false;
3284 unsigned long flags;
3285 int cd;
3286 struct tty_port *port = &info->port;
3287
3288 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3289
3290 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3291 /* nonblock mode is set or port is not enabled */
3292 port->flags |= ASYNC_NORMAL_ACTIVE;
3293 return 0;
3294 }
3295
3296 if (tty->termios->c_cflag & CLOCAL)
3297 do_clocal = true;
3298
3299 /* Wait for carrier detect and the line to become
3300 * free (i.e., not in use by the callout). While we are in
3301 * this loop, port->count is dropped by one, so that
3302 * close() knows when to free things. We restore it upon
3303 * exit, either normal or abnormal.
3304 */
3305
3306 retval = 0;
3307 add_wait_queue(&port->open_wait, &wait);
3308
3309 spin_lock_irqsave(&info->lock, flags);
3310 if (!tty_hung_up_p(filp)) {
3311 extra_count = true;
3312 port->count--;
3313 }
3314 spin_unlock_irqrestore(&info->lock, flags);
3315 port->blocked_open++;
3316
3317 while (1) {
3318 if ((tty->termios->c_cflag & CBAUD))
3319 tty_port_raise_dtr_rts(port);
3320
3321 set_current_state(TASK_INTERRUPTIBLE);
3322
3323 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3324 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3325 -EAGAIN : -ERESTARTSYS;
3326 break;
3327 }
3328
3329 cd = tty_port_carrier_raised(port);
3330
3331 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3332 break;
3333
3334 if (signal_pending(current)) {
3335 retval = -ERESTARTSYS;
3336 break;
3337 }
3338
3339 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3340 tty_unlock();
3341 schedule();
3342 tty_lock();
3343 }
3344
3345 set_current_state(TASK_RUNNING);
3346 remove_wait_queue(&port->open_wait, &wait);
3347
3348 if (extra_count)
3349 port->count++;
3350 port->blocked_open--;
3351
3352 if (!retval)
3353 port->flags |= ASYNC_NORMAL_ACTIVE;
3354
3355 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3356 return retval;
3357}
3358
3359static int alloc_tmp_rbuf(struct slgt_info *info)
3360{
3361 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3362 if (info->tmp_rbuf == NULL)
3363 return -ENOMEM;
3364 return 0;
3365}
3366
3367static void free_tmp_rbuf(struct slgt_info *info)
3368{
3369 kfree(info->tmp_rbuf);
3370 info->tmp_rbuf = NULL;
3371}
3372
3373/*
3374 * allocate DMA descriptor lists.
3375 */
3376static int alloc_desc(struct slgt_info *info)
3377{
3378 unsigned int i;
3379 unsigned int pbufs;
3380
3381 /* allocate memory to hold descriptor lists */
3382 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3383 if (info->bufs == NULL)
3384 return -ENOMEM;
3385
3386 memset(info->bufs, 0, DESC_LIST_SIZE);
3387
3388 info->rbufs = (struct slgt_desc*)info->bufs;
3389 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3390
3391 pbufs = (unsigned int)info->bufs_dma_addr;
3392
3393 /*
3394 * Build circular lists of descriptors
3395 */
3396
3397 for (i=0; i < info->rbuf_count; i++) {
3398 /* physical address of this descriptor */
3399 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3400
3401 /* physical address of next descriptor */
3402 if (i == info->rbuf_count - 1)
3403 info->rbufs[i].next = cpu_to_le32(pbufs);
3404 else
3405 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3406 set_desc_count(info->rbufs[i], DMABUFSIZE);
3407 }
3408
3409 for (i=0; i < info->tbuf_count; i++) {
3410 /* physical address of this descriptor */
3411 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3412
3413 /* physical address of next descriptor */
3414 if (i == info->tbuf_count - 1)
3415 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3416 else
3417 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3418 }
3419
3420 return 0;
3421}
3422
3423static void free_desc(struct slgt_info *info)
3424{
3425 if (info->bufs != NULL) {
3426 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3427 info->bufs = NULL;
3428 info->rbufs = NULL;
3429 info->tbufs = NULL;
3430 }
3431}
3432
3433static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3434{
3435 int i;
3436 for (i=0; i < count; i++) {
3437 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3438 return -ENOMEM;
3439 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3440 }
3441 return 0;
3442}
3443
3444static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3445{
3446 int i;
3447 for (i=0; i < count; i++) {
3448 if (bufs[i].buf == NULL)
3449 continue;
3450 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3451 bufs[i].buf = NULL;
3452 }
3453}
3454
3455static int alloc_dma_bufs(struct slgt_info *info)
3456{
3457 info->rbuf_count = 32;
3458 info->tbuf_count = 32;
3459
3460 if (alloc_desc(info) < 0 ||
3461 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3462 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3463 alloc_tmp_rbuf(info) < 0) {
3464 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3465 return -ENOMEM;
3466 }
3467 reset_rbufs(info);
3468 return 0;
3469}
3470
3471static void free_dma_bufs(struct slgt_info *info)
3472{
3473 if (info->bufs) {
3474 free_bufs(info, info->rbufs, info->rbuf_count);
3475 free_bufs(info, info->tbufs, info->tbuf_count);
3476 free_desc(info);
3477 }
3478 free_tmp_rbuf(info);
3479}
3480
3481static int claim_resources(struct slgt_info *info)
3482{
3483 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3484 DBGERR(("%s reg addr conflict, addr=%08X\n",
3485 info->device_name, info->phys_reg_addr));
3486 info->init_error = DiagStatus_AddressConflict;
3487 goto errout;
3488 }
3489 else
3490 info->reg_addr_requested = true;
3491
3492 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3493 if (!info->reg_addr) {
3494 DBGERR(("%s can't map device registers, addr=%08X\n",
3495 info->device_name, info->phys_reg_addr));
3496 info->init_error = DiagStatus_CantAssignPciResources;
3497 goto errout;
3498 }
3499 return 0;
3500
3501errout:
3502 release_resources(info);
3503 return -ENODEV;
3504}
3505
3506static void release_resources(struct slgt_info *info)
3507{
3508 if (info->irq_requested) {
3509 free_irq(info->irq_level, info);
3510 info->irq_requested = false;
3511 }
3512
3513 if (info->reg_addr_requested) {
3514 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3515 info->reg_addr_requested = false;
3516 }
3517
3518 if (info->reg_addr) {
3519 iounmap(info->reg_addr);
3520 info->reg_addr = NULL;
3521 }
3522}
3523
3524/* Add the specified device instance data structure to the
3525 * global linked list of devices and increment the device count.
3526 */
3527static void add_device(struct slgt_info *info)
3528{
3529 char *devstr;
3530
3531 info->next_device = NULL;
3532 info->line = slgt_device_count;
3533 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3534
3535 if (info->line < MAX_DEVICES) {
3536 if (maxframe[info->line])
3537 info->max_frame_size = maxframe[info->line];
3538 }
3539
3540 slgt_device_count++;
3541
3542 if (!slgt_device_list)
3543 slgt_device_list = info;
3544 else {
3545 struct slgt_info *current_dev = slgt_device_list;
3546 while(current_dev->next_device)
3547 current_dev = current_dev->next_device;
3548 current_dev->next_device = info;
3549 }
3550
3551 if (info->max_frame_size < 4096)
3552 info->max_frame_size = 4096;
3553 else if (info->max_frame_size > 65535)
3554 info->max_frame_size = 65535;
3555
3556 switch(info->pdev->device) {
3557 case SYNCLINK_GT_DEVICE_ID:
3558 devstr = "GT";
3559 break;
3560 case SYNCLINK_GT2_DEVICE_ID:
3561 devstr = "GT2";
3562 break;
3563 case SYNCLINK_GT4_DEVICE_ID:
3564 devstr = "GT4";
3565 break;
3566 case SYNCLINK_AC_DEVICE_ID:
3567 devstr = "AC";
3568 info->params.mode = MGSL_MODE_ASYNC;
3569 break;
3570 default:
3571 devstr = "(unknown model)";
3572 }
3573 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3574 devstr, info->device_name, info->phys_reg_addr,
3575 info->irq_level, info->max_frame_size);
3576
3577#if SYNCLINK_GENERIC_HDLC
3578 hdlcdev_init(info);
3579#endif
3580}
3581
3582static const struct tty_port_operations slgt_port_ops = {
3583 .carrier_raised = carrier_raised,
3584 .dtr_rts = dtr_rts,
3585};
3586
3587/*
3588 * allocate device instance structure, return NULL on failure
3589 */
3590static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3591{
3592 struct slgt_info *info;
3593
3594 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3595
3596 if (!info) {
3597 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3598 driver_name, adapter_num, port_num));
3599 } else {
3600 tty_port_init(&info->port);
3601 info->port.ops = &slgt_port_ops;
3602 info->magic = MGSL_MAGIC;
3603 INIT_WORK(&info->task, bh_handler);
3604 info->max_frame_size = 4096;
3605 info->base_clock = 14745600;
3606 info->rbuf_fill_level = DMABUFSIZE;
3607 info->port.close_delay = 5*HZ/10;
3608 info->port.closing_wait = 30*HZ;
3609 init_waitqueue_head(&info->status_event_wait_q);
3610 init_waitqueue_head(&info->event_wait_q);
3611 spin_lock_init(&info->netlock);
3612 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3613 info->idle_mode = HDLC_TXIDLE_FLAGS;
3614 info->adapter_num = adapter_num;
3615 info->port_num = port_num;
3616
3617 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3618 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3619
3620 /* Copy configuration info to device instance data */
3621 info->pdev = pdev;
3622 info->irq_level = pdev->irq;
3623 info->phys_reg_addr = pci_resource_start(pdev,0);
3624
3625 info->bus_type = MGSL_BUS_TYPE_PCI;
3626 info->irq_flags = IRQF_SHARED;
3627
3628 info->init_error = -1; /* assume error, set to 0 on successful init */
3629 }
3630
3631 return info;
3632}
3633
3634static void device_init(int adapter_num, struct pci_dev *pdev)
3635{
3636 struct slgt_info *port_array[SLGT_MAX_PORTS];
3637 int i;
3638 int port_count = 1;
3639
3640 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3641 port_count = 2;
3642 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3643 port_count = 4;
3644
3645 /* allocate device instances for all ports */
3646 for (i=0; i < port_count; ++i) {
3647 port_array[i] = alloc_dev(adapter_num, i, pdev);
3648 if (port_array[i] == NULL) {
3649 for (--i; i >= 0; --i)
3650 kfree(port_array[i]);
3651 return;
3652 }
3653 }
3654
3655 /* give copy of port_array to all ports and add to device list */
3656 for (i=0; i < port_count; ++i) {
3657 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3658 add_device(port_array[i]);
3659 port_array[i]->port_count = port_count;
3660 spin_lock_init(&port_array[i]->lock);
3661 }
3662
3663 /* Allocate and claim adapter resources */
3664 if (!claim_resources(port_array[0])) {
3665
3666 alloc_dma_bufs(port_array[0]);
3667
3668 /* copy resource information from first port to others */
3669 for (i = 1; i < port_count; ++i) {
3670 port_array[i]->irq_level = port_array[0]->irq_level;
3671 port_array[i]->reg_addr = port_array[0]->reg_addr;
3672 alloc_dma_bufs(port_array[i]);
3673 }
3674
3675 if (request_irq(port_array[0]->irq_level,
3676 slgt_interrupt,
3677 port_array[0]->irq_flags,
3678 port_array[0]->device_name,
3679 port_array[0]) < 0) {
3680 DBGERR(("%s request_irq failed IRQ=%d\n",
3681 port_array[0]->device_name,
3682 port_array[0]->irq_level));
3683 } else {
3684 port_array[0]->irq_requested = true;
3685 adapter_test(port_array[0]);
3686 for (i=1 ; i < port_count ; i++) {
3687 port_array[i]->init_error = port_array[0]->init_error;
3688 port_array[i]->gpio_present = port_array[0]->gpio_present;
3689 }
3690 }
3691 }
3692
3693 for (i=0; i < port_count; ++i)
3694 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3695}
3696
3697static int __devinit init_one(struct pci_dev *dev,
3698 const struct pci_device_id *ent)
3699{
3700 if (pci_enable_device(dev)) {
3701 printk("error enabling pci device %p\n", dev);
3702 return -EIO;
3703 }
3704 pci_set_master(dev);
3705 device_init(slgt_device_count, dev);
3706 return 0;
3707}
3708
3709static void __devexit remove_one(struct pci_dev *dev)
3710{
3711}
3712
3713static const struct tty_operations ops = {
3714 .open = open,
3715 .close = close,
3716 .write = write,
3717 .put_char = put_char,
3718 .flush_chars = flush_chars,
3719 .write_room = write_room,
3720 .chars_in_buffer = chars_in_buffer,
3721 .flush_buffer = flush_buffer,
3722 .ioctl = ioctl,
3723 .compat_ioctl = slgt_compat_ioctl,
3724 .throttle = throttle,
3725 .unthrottle = unthrottle,
3726 .send_xchar = send_xchar,
3727 .break_ctl = set_break,
3728 .wait_until_sent = wait_until_sent,
3729 .set_termios = set_termios,
3730 .stop = tx_hold,
3731 .start = tx_release,
3732 .hangup = hangup,
3733 .tiocmget = tiocmget,
3734 .tiocmset = tiocmset,
3735 .get_icount = get_icount,
3736 .proc_fops = &synclink_gt_proc_fops,
3737};
3738
3739static void slgt_cleanup(void)
3740{
3741 int rc;
3742 struct slgt_info *info;
3743 struct slgt_info *tmp;
3744
3745 printk(KERN_INFO "unload %s\n", driver_name);
3746
3747 if (serial_driver) {
3748 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3749 tty_unregister_device(serial_driver, info->line);
3750 if ((rc = tty_unregister_driver(serial_driver)))
3751 DBGERR(("tty_unregister_driver error=%d\n", rc));
3752 put_tty_driver(serial_driver);
3753 }
3754
3755 /* reset devices */
3756 info = slgt_device_list;
3757 while(info) {
3758 reset_port(info);
3759 info = info->next_device;
3760 }
3761
3762 /* release devices */
3763 info = slgt_device_list;
3764 while(info) {
3765#if SYNCLINK_GENERIC_HDLC
3766 hdlcdev_exit(info);
3767#endif
3768 free_dma_bufs(info);
3769 free_tmp_rbuf(info);
3770 if (info->port_num == 0)
3771 release_resources(info);
3772 tmp = info;
3773 info = info->next_device;
3774 kfree(tmp);
3775 }
3776
3777 if (pci_registered)
3778 pci_unregister_driver(&pci_driver);
3779}
3780
3781/*
3782 * Driver initialization entry point.
3783 */
3784static int __init slgt_init(void)
3785{
3786 int rc;
3787
3788 printk(KERN_INFO "%s\n", driver_name);
3789
3790 serial_driver = alloc_tty_driver(MAX_DEVICES);
3791 if (!serial_driver) {
3792 printk("%s can't allocate tty driver\n", driver_name);
3793 return -ENOMEM;
3794 }
3795
3796 /* Initialize the tty_driver structure */
3797
3798 serial_driver->owner = THIS_MODULE;
3799 serial_driver->driver_name = tty_driver_name;
3800 serial_driver->name = tty_dev_prefix;
3801 serial_driver->major = ttymajor;
3802 serial_driver->minor_start = 64;
3803 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3804 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3805 serial_driver->init_termios = tty_std_termios;
3806 serial_driver->init_termios.c_cflag =
3807 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3808 serial_driver->init_termios.c_ispeed = 9600;
3809 serial_driver->init_termios.c_ospeed = 9600;
3810 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3811 tty_set_operations(serial_driver, &ops);
3812 if ((rc = tty_register_driver(serial_driver)) < 0) {
3813 DBGERR(("%s can't register serial driver\n", driver_name));
3814 put_tty_driver(serial_driver);
3815 serial_driver = NULL;
3816 goto error;
3817 }
3818
3819 printk(KERN_INFO "%s, tty major#%d\n",
3820 driver_name, serial_driver->major);
3821
3822 slgt_device_count = 0;
3823 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3824 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3825 goto error;
3826 }
3827 pci_registered = true;
3828
3829 if (!slgt_device_list)
3830 printk("%s no devices found\n",driver_name);
3831
3832 return 0;
3833
3834error:
3835 slgt_cleanup();
3836 return rc;
3837}
3838
3839static void __exit slgt_exit(void)
3840{
3841 slgt_cleanup();
3842}
3843
3844module_init(slgt_init);
3845module_exit(slgt_exit);
3846
3847/*
3848 * register access routines
3849 */
3850
3851#define CALC_REGADDR() \
3852 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3853 if (addr >= 0x80) \
3854 reg_addr += (info->port_num) * 32; \
3855 else if (addr >= 0x40) \
3856 reg_addr += (info->port_num) * 16;
3857
3858static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3859{
3860 CALC_REGADDR();
3861 return readb((void __iomem *)reg_addr);
3862}
3863
3864static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3865{
3866 CALC_REGADDR();
3867 writeb(value, (void __iomem *)reg_addr);
3868}
3869
3870static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3871{
3872 CALC_REGADDR();
3873 return readw((void __iomem *)reg_addr);
3874}
3875
3876static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3877{
3878 CALC_REGADDR();
3879 writew(value, (void __iomem *)reg_addr);
3880}
3881
3882static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3883{
3884 CALC_REGADDR();
3885 return readl((void __iomem *)reg_addr);
3886}
3887
3888static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3889{
3890 CALC_REGADDR();
3891 writel(value, (void __iomem *)reg_addr);
3892}
3893
3894static void rdma_reset(struct slgt_info *info)
3895{
3896 unsigned int i;
3897
3898 /* set reset bit */
3899 wr_reg32(info, RDCSR, BIT1);
3900
3901 /* wait for enable bit cleared */
3902 for(i=0 ; i < 1000 ; i++)
3903 if (!(rd_reg32(info, RDCSR) & BIT0))
3904 break;
3905}
3906
3907static void tdma_reset(struct slgt_info *info)
3908{
3909 unsigned int i;
3910
3911 /* set reset bit */
3912 wr_reg32(info, TDCSR, BIT1);
3913
3914 /* wait for enable bit cleared */
3915 for(i=0 ; i < 1000 ; i++)
3916 if (!(rd_reg32(info, TDCSR) & BIT0))
3917 break;
3918}
3919
3920/*
3921 * enable internal loopback
3922 * TxCLK and RxCLK are generated from BRG
3923 * and TxD is looped back to RxD internally.
3924 */
3925static void enable_loopback(struct slgt_info *info)
3926{
3927 /* SCR (serial control) BIT2=looopback enable */
3928 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3929
3930 if (info->params.mode != MGSL_MODE_ASYNC) {
3931 /* CCR (clock control)
3932 * 07..05 tx clock source (010 = BRG)
3933 * 04..02 rx clock source (010 = BRG)
3934 * 01 auxclk enable (0 = disable)
3935 * 00 BRG enable (1 = enable)
3936 *
3937 * 0100 1001
3938 */
3939 wr_reg8(info, CCR, 0x49);
3940
3941 /* set speed if available, otherwise use default */
3942 if (info->params.clock_speed)
3943 set_rate(info, info->params.clock_speed);
3944 else
3945 set_rate(info, 3686400);
3946 }
3947}
3948
3949/*
3950 * set baud rate generator to specified rate
3951 */
3952static void set_rate(struct slgt_info *info, u32 rate)
3953{
3954 unsigned int div;
3955 unsigned int osc = info->base_clock;
3956
3957 /* div = osc/rate - 1
3958 *
3959 * Round div up if osc/rate is not integer to
3960 * force to next slowest rate.
3961 */
3962
3963 if (rate) {
3964 div = osc/rate;
3965 if (!(osc % rate) && div)
3966 div--;
3967 wr_reg16(info, BDR, (unsigned short)div);
3968 }
3969}
3970
3971static void rx_stop(struct slgt_info *info)
3972{
3973 unsigned short val;
3974
3975 /* disable and reset receiver */
3976 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3977 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3978 wr_reg16(info, RCR, val); /* clear reset bit */
3979
3980 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3981
3982 /* clear pending rx interrupts */
3983 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3984
3985 rdma_reset(info);
3986
3987 info->rx_enabled = false;
3988 info->rx_restart = false;
3989}
3990
3991static void rx_start(struct slgt_info *info)
3992{
3993 unsigned short val;
3994
3995 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3996
3997 /* clear pending rx overrun IRQ */
3998 wr_reg16(info, SSR, IRQ_RXOVER);
3999
4000 /* reset and disable receiver */
4001 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
4002 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
4003 wr_reg16(info, RCR, val); /* clear reset bit */
4004
4005 rdma_reset(info);
4006 reset_rbufs(info);
4007
4008 if (info->rx_pio) {
4009 /* rx request when rx FIFO not empty */
4010 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
4011 slgt_irq_on(info, IRQ_RXDATA);
4012 if (info->params.mode == MGSL_MODE_ASYNC) {
4013 /* enable saving of rx status */
4014 wr_reg32(info, RDCSR, BIT6);
4015 }
4016 } else {
4017 /* rx request when rx FIFO half full */
4018 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
4019 /* set 1st descriptor address */
4020 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
4021
4022 if (info->params.mode != MGSL_MODE_ASYNC) {
4023 /* enable rx DMA and DMA interrupt */
4024 wr_reg32(info, RDCSR, (BIT2 + BIT0));
4025 } else {
4026 /* enable saving of rx status, rx DMA and DMA interrupt */
4027 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
4028 }
4029 }
4030
4031 slgt_irq_on(info, IRQ_RXOVER);
4032
4033 /* enable receiver */
4034 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
4035
4036 info->rx_restart = false;
4037 info->rx_enabled = true;
4038}
4039
4040static void tx_start(struct slgt_info *info)
4041{
4042 if (!info->tx_enabled) {
4043 wr_reg16(info, TCR,
4044 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
4045 info->tx_enabled = true;
4046 }
4047
4048 if (desc_count(info->tbufs[info->tbuf_start])) {
4049 info->drop_rts_on_tx_done = false;
4050
4051 if (info->params.mode != MGSL_MODE_ASYNC) {
4052 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
4053 get_signals(info);
4054 if (!(info->signals & SerialSignal_RTS)) {
4055 info->signals |= SerialSignal_RTS;
4056 set_signals(info);
4057 info->drop_rts_on_tx_done = true;
4058 }
4059 }
4060
4061 slgt_irq_off(info, IRQ_TXDATA);
4062 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
4063 /* clear tx idle and underrun status bits */
4064 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4065 } else {
4066 slgt_irq_off(info, IRQ_TXDATA);
4067 slgt_irq_on(info, IRQ_TXIDLE);
4068 /* clear tx idle status bit */
4069 wr_reg16(info, SSR, IRQ_TXIDLE);
4070 }
4071 /* set 1st descriptor address and start DMA */
4072 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
4073 wr_reg32(info, TDCSR, BIT2 + BIT0);
4074 info->tx_active = true;
4075 }
4076}
4077
4078static void tx_stop(struct slgt_info *info)
4079{
4080 unsigned short val;
4081
4082 del_timer(&info->tx_timer);
4083
4084 tdma_reset(info);
4085
4086 /* reset and disable transmitter */
4087 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
4088 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
4089
4090 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
4091
4092 /* clear tx idle and underrun status bit */
4093 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
4094
4095 reset_tbufs(info);
4096
4097 info->tx_enabled = false;
4098 info->tx_active = false;
4099}
4100
4101static void reset_port(struct slgt_info *info)
4102{
4103 if (!info->reg_addr)
4104 return;
4105
4106 tx_stop(info);
4107 rx_stop(info);
4108
4109 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4110 set_signals(info);
4111
4112 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4113}
4114
4115static void reset_adapter(struct slgt_info *info)
4116{
4117 int i;
4118 for (i=0; i < info->port_count; ++i) {
4119 if (info->port_array[i])
4120 reset_port(info->port_array[i]);
4121 }
4122}
4123
4124static void async_mode(struct slgt_info *info)
4125{
4126 unsigned short val;
4127
4128 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4129 tx_stop(info);
4130 rx_stop(info);
4131
4132 /* TCR (tx control)
4133 *
4134 * 15..13 mode, 010=async
4135 * 12..10 encoding, 000=NRZ
4136 * 09 parity enable
4137 * 08 1=odd parity, 0=even parity
4138 * 07 1=RTS driver control
4139 * 06 1=break enable
4140 * 05..04 character length
4141 * 00=5 bits
4142 * 01=6 bits
4143 * 10=7 bits
4144 * 11=8 bits
4145 * 03 0=1 stop bit, 1=2 stop bits
4146 * 02 reset
4147 * 01 enable
4148 * 00 auto-CTS enable
4149 */
4150 val = 0x4000;
4151
4152 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4153 val |= BIT7;
4154
4155 if (info->params.parity != ASYNC_PARITY_NONE) {
4156 val |= BIT9;
4157 if (info->params.parity == ASYNC_PARITY_ODD)
4158 val |= BIT8;
4159 }
4160
4161 switch (info->params.data_bits)
4162 {
4163 case 6: val |= BIT4; break;
4164 case 7: val |= BIT5; break;
4165 case 8: val |= BIT5 + BIT4; break;
4166 }
4167
4168 if (info->params.stop_bits != 1)
4169 val |= BIT3;
4170
4171 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4172 val |= BIT0;
4173
4174 wr_reg16(info, TCR, val);
4175
4176 /* RCR (rx control)
4177 *
4178 * 15..13 mode, 010=async
4179 * 12..10 encoding, 000=NRZ
4180 * 09 parity enable
4181 * 08 1=odd parity, 0=even parity
4182 * 07..06 reserved, must be 0
4183 * 05..04 character length
4184 * 00=5 bits
4185 * 01=6 bits
4186 * 10=7 bits
4187 * 11=8 bits
4188 * 03 reserved, must be zero
4189 * 02 reset
4190 * 01 enable
4191 * 00 auto-DCD enable
4192 */
4193 val = 0x4000;
4194
4195 if (info->params.parity != ASYNC_PARITY_NONE) {
4196 val |= BIT9;
4197 if (info->params.parity == ASYNC_PARITY_ODD)
4198 val |= BIT8;
4199 }
4200
4201 switch (info->params.data_bits)
4202 {
4203 case 6: val |= BIT4; break;
4204 case 7: val |= BIT5; break;
4205 case 8: val |= BIT5 + BIT4; break;
4206 }
4207
4208 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4209 val |= BIT0;
4210
4211 wr_reg16(info, RCR, val);
4212
4213 /* CCR (clock control)
4214 *
4215 * 07..05 011 = tx clock source is BRG/16
4216 * 04..02 010 = rx clock source is BRG
4217 * 01 0 = auxclk disabled
4218 * 00 1 = BRG enabled
4219 *
4220 * 0110 1001
4221 */
4222 wr_reg8(info, CCR, 0x69);
4223
4224 msc_set_vcr(info);
4225
4226 /* SCR (serial control)
4227 *
4228 * 15 1=tx req on FIFO half empty
4229 * 14 1=rx req on FIFO half full
4230 * 13 tx data IRQ enable
4231 * 12 tx idle IRQ enable
4232 * 11 rx break on IRQ enable
4233 * 10 rx data IRQ enable
4234 * 09 rx break off IRQ enable
4235 * 08 overrun IRQ enable
4236 * 07 DSR IRQ enable
4237 * 06 CTS IRQ enable
4238 * 05 DCD IRQ enable
4239 * 04 RI IRQ enable
4240 * 03 0=16x sampling, 1=8x sampling
4241 * 02 1=txd->rxd internal loopback enable
4242 * 01 reserved, must be zero
4243 * 00 1=master IRQ enable
4244 */
4245 val = BIT15 + BIT14 + BIT0;
4246 /* JCR[8] : 1 = x8 async mode feature available */
4247 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4248 ((info->base_clock < (info->params.data_rate * 16)) ||
4249 (info->base_clock % (info->params.data_rate * 16)))) {
4250 /* use 8x sampling */
4251 val |= BIT3;
4252 set_rate(info, info->params.data_rate * 8);
4253 } else {
4254 /* use 16x sampling */
4255 set_rate(info, info->params.data_rate * 16);
4256 }
4257 wr_reg16(info, SCR, val);
4258
4259 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4260
4261 if (info->params.loopback)
4262 enable_loopback(info);
4263}
4264
4265static void sync_mode(struct slgt_info *info)
4266{
4267 unsigned short val;
4268
4269 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4270 tx_stop(info);
4271 rx_stop(info);
4272
4273 /* TCR (tx control)
4274 *
4275 * 15..13 mode
4276 * 000=HDLC/SDLC
4277 * 001=raw bit synchronous
4278 * 010=asynchronous/isochronous
4279 * 011=monosync byte synchronous
4280 * 100=bisync byte synchronous
4281 * 101=xsync byte synchronous
4282 * 12..10 encoding
4283 * 09 CRC enable
4284 * 08 CRC32
4285 * 07 1=RTS driver control
4286 * 06 preamble enable
4287 * 05..04 preamble length
4288 * 03 share open/close flag
4289 * 02 reset
4290 * 01 enable
4291 * 00 auto-CTS enable
4292 */
4293 val = BIT2;
4294
4295 switch(info->params.mode) {
4296 case MGSL_MODE_XSYNC:
4297 val |= BIT15 + BIT13;
4298 break;
4299 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4300 case MGSL_MODE_BISYNC: val |= BIT15; break;
4301 case MGSL_MODE_RAW: val |= BIT13; break;
4302 }
4303 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4304 val |= BIT7;
4305
4306 switch(info->params.encoding)
4307 {
4308 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4309 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4310 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4311 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4312 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4313 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4314 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4315 }
4316
4317 switch (info->params.crc_type & HDLC_CRC_MASK)
4318 {
4319 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4320 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4321 }
4322
4323 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4324 val |= BIT6;
4325
4326 switch (info->params.preamble_length)
4327 {
4328 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4329 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4330 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4331 }
4332
4333 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4334 val |= BIT0;
4335
4336 wr_reg16(info, TCR, val);
4337
4338 /* TPR (transmit preamble) */
4339
4340 switch (info->params.preamble)
4341 {
4342 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4343 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4344 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4345 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4346 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4347 default: val = 0x7e; break;
4348 }
4349 wr_reg8(info, TPR, (unsigned char)val);
4350
4351 /* RCR (rx control)
4352 *
4353 * 15..13 mode
4354 * 000=HDLC/SDLC
4355 * 001=raw bit synchronous
4356 * 010=asynchronous/isochronous
4357 * 011=monosync byte synchronous
4358 * 100=bisync byte synchronous
4359 * 101=xsync byte synchronous
4360 * 12..10 encoding
4361 * 09 CRC enable
4362 * 08 CRC32
4363 * 07..03 reserved, must be 0
4364 * 02 reset
4365 * 01 enable
4366 * 00 auto-DCD enable
4367 */
4368 val = 0;
4369
4370 switch(info->params.mode) {
4371 case MGSL_MODE_XSYNC:
4372 val |= BIT15 + BIT13;
4373 break;
4374 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4375 case MGSL_MODE_BISYNC: val |= BIT15; break;
4376 case MGSL_MODE_RAW: val |= BIT13; break;
4377 }
4378
4379 switch(info->params.encoding)
4380 {
4381 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4382 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4383 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4384 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4385 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4386 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4387 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4388 }
4389
4390 switch (info->params.crc_type & HDLC_CRC_MASK)
4391 {
4392 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4393 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4394 }
4395
4396 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4397 val |= BIT0;
4398
4399 wr_reg16(info, RCR, val);
4400
4401 /* CCR (clock control)
4402 *
4403 * 07..05 tx clock source
4404 * 04..02 rx clock source
4405 * 01 auxclk enable
4406 * 00 BRG enable
4407 */
4408 val = 0;
4409
4410 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4411 {
4412 // when RxC source is DPLL, BRG generates 16X DPLL
4413 // reference clock, so take TxC from BRG/16 to get
4414 // transmit clock at actual data rate
4415 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4416 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4417 else
4418 val |= BIT6; /* 010, txclk = BRG */
4419 }
4420 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4421 val |= BIT7; /* 100, txclk = DPLL Input */
4422 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4423 val |= BIT5; /* 001, txclk = RXC Input */
4424
4425 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4426 val |= BIT3; /* 010, rxclk = BRG */
4427 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4428 val |= BIT4; /* 100, rxclk = DPLL */
4429 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4430 val |= BIT2; /* 001, rxclk = TXC Input */
4431
4432 if (info->params.clock_speed)
4433 val |= BIT1 + BIT0;
4434
4435 wr_reg8(info, CCR, (unsigned char)val);
4436
4437 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4438 {
4439 // program DPLL mode
4440 switch(info->params.encoding)
4441 {
4442 case HDLC_ENCODING_BIPHASE_MARK:
4443 case HDLC_ENCODING_BIPHASE_SPACE:
4444 val = BIT7; break;
4445 case HDLC_ENCODING_BIPHASE_LEVEL:
4446 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4447 val = BIT7 + BIT6; break;
4448 default: val = BIT6; // NRZ encodings
4449 }
4450 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4451
4452 // DPLL requires a 16X reference clock from BRG
4453 set_rate(info, info->params.clock_speed * 16);
4454 }
4455 else
4456 set_rate(info, info->params.clock_speed);
4457
4458 tx_set_idle(info);
4459
4460 msc_set_vcr(info);
4461
4462 /* SCR (serial control)
4463 *
4464 * 15 1=tx req on FIFO half empty
4465 * 14 1=rx req on FIFO half full
4466 * 13 tx data IRQ enable
4467 * 12 tx idle IRQ enable
4468 * 11 underrun IRQ enable
4469 * 10 rx data IRQ enable
4470 * 09 rx idle IRQ enable
4471 * 08 overrun IRQ enable
4472 * 07 DSR IRQ enable
4473 * 06 CTS IRQ enable
4474 * 05 DCD IRQ enable
4475 * 04 RI IRQ enable
4476 * 03 reserved, must be zero
4477 * 02 1=txd->rxd internal loopback enable
4478 * 01 reserved, must be zero
4479 * 00 1=master IRQ enable
4480 */
4481 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4482
4483 if (info->params.loopback)
4484 enable_loopback(info);
4485}
4486
4487/*
4488 * set transmit idle mode
4489 */
4490static void tx_set_idle(struct slgt_info *info)
4491{
4492 unsigned char val;
4493 unsigned short tcr;
4494
4495 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4496 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4497 */
4498 tcr = rd_reg16(info, TCR);
4499 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4500 /* disable preamble, set idle size to 16 bits */
4501 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4502 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4503 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4504 } else if (!(tcr & BIT6)) {
4505 /* preamble is disabled, set idle size to 8 bits */
4506 tcr &= ~(BIT5 + BIT4);
4507 }
4508 wr_reg16(info, TCR, tcr);
4509
4510 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4511 /* LSB of custom tx idle specified in tx idle register */
4512 val = (unsigned char)(info->idle_mode & 0xff);
4513 } else {
4514 /* standard 8 bit idle patterns */
4515 switch(info->idle_mode)
4516 {
4517 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4518 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4519 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4520 case HDLC_TXIDLE_ZEROS:
4521 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4522 default: val = 0xff;
4523 }
4524 }
4525
4526 wr_reg8(info, TIR, val);
4527}
4528
4529/*
4530 * get state of V24 status (input) signals
4531 */
4532static void get_signals(struct slgt_info *info)
4533{
4534 unsigned short status = rd_reg16(info, SSR);
4535
4536 /* clear all serial signals except DTR and RTS */
4537 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4538
4539 if (status & BIT3)
4540 info->signals |= SerialSignal_DSR;
4541 if (status & BIT2)
4542 info->signals |= SerialSignal_CTS;
4543 if (status & BIT1)
4544 info->signals |= SerialSignal_DCD;
4545 if (status & BIT0)
4546 info->signals |= SerialSignal_RI;
4547}
4548
4549/*
4550 * set V.24 Control Register based on current configuration
4551 */
4552static void msc_set_vcr(struct slgt_info *info)
4553{
4554 unsigned char val = 0;
4555
4556 /* VCR (V.24 control)
4557 *
4558 * 07..04 serial IF select
4559 * 03 DTR
4560 * 02 RTS
4561 * 01 LL
4562 * 00 RL
4563 */
4564
4565 switch(info->if_mode & MGSL_INTERFACE_MASK)
4566 {
4567 case MGSL_INTERFACE_RS232:
4568 val |= BIT5; /* 0010 */
4569 break;
4570 case MGSL_INTERFACE_V35:
4571 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4572 break;
4573 case MGSL_INTERFACE_RS422:
4574 val |= BIT6; /* 0100 */
4575 break;
4576 }
4577
4578 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4579 val |= BIT4;
4580 if (info->signals & SerialSignal_DTR)
4581 val |= BIT3;
4582 if (info->signals & SerialSignal_RTS)
4583 val |= BIT2;
4584 if (info->if_mode & MGSL_INTERFACE_LL)
4585 val |= BIT1;
4586 if (info->if_mode & MGSL_INTERFACE_RL)
4587 val |= BIT0;
4588 wr_reg8(info, VCR, val);
4589}
4590
4591/*
4592 * set state of V24 control (output) signals
4593 */
4594static void set_signals(struct slgt_info *info)
4595{
4596 unsigned char val = rd_reg8(info, VCR);
4597 if (info->signals & SerialSignal_DTR)
4598 val |= BIT3;
4599 else
4600 val &= ~BIT3;
4601 if (info->signals & SerialSignal_RTS)
4602 val |= BIT2;
4603 else
4604 val &= ~BIT2;
4605 wr_reg8(info, VCR, val);
4606}
4607
4608/*
4609 * free range of receive DMA buffers (i to last)
4610 */
4611static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4612{
4613 int done = 0;
4614
4615 while(!done) {
4616 /* reset current buffer for reuse */
4617 info->rbufs[i].status = 0;
4618 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4619 if (i == last)
4620 done = 1;
4621 if (++i == info->rbuf_count)
4622 i = 0;
4623 }
4624 info->rbuf_current = i;
4625}
4626
4627/*
4628 * mark all receive DMA buffers as free
4629 */
4630static void reset_rbufs(struct slgt_info *info)
4631{
4632 free_rbufs(info, 0, info->rbuf_count - 1);
4633 info->rbuf_fill_index = 0;
4634 info->rbuf_fill_count = 0;
4635}
4636
4637/*
4638 * pass receive HDLC frame to upper layer
4639 *
4640 * return true if frame available, otherwise false
4641 */
4642static bool rx_get_frame(struct slgt_info *info)
4643{
4644 unsigned int start, end;
4645 unsigned short status;
4646 unsigned int framesize = 0;
4647 unsigned long flags;
4648 struct tty_struct *tty = info->port.tty;
4649 unsigned char addr_field = 0xff;
4650 unsigned int crc_size = 0;
4651
4652 switch (info->params.crc_type & HDLC_CRC_MASK) {
4653 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4654 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4655 }
4656
4657check_again:
4658
4659 framesize = 0;
4660 addr_field = 0xff;
4661 start = end = info->rbuf_current;
4662
4663 for (;;) {
4664 if (!desc_complete(info->rbufs[end]))
4665 goto cleanup;
4666
4667 if (framesize == 0 && info->params.addr_filter != 0xff)
4668 addr_field = info->rbufs[end].buf[0];
4669
4670 framesize += desc_count(info->rbufs[end]);
4671
4672 if (desc_eof(info->rbufs[end]))
4673 break;
4674
4675 if (++end == info->rbuf_count)
4676 end = 0;
4677
4678 if (end == info->rbuf_current) {
4679 if (info->rx_enabled){
4680 spin_lock_irqsave(&info->lock,flags);
4681 rx_start(info);
4682 spin_unlock_irqrestore(&info->lock,flags);
4683 }
4684 goto cleanup;
4685 }
4686 }
4687
4688 /* status
4689 *
4690 * 15 buffer complete
4691 * 14..06 reserved
4692 * 05..04 residue
4693 * 02 eof (end of frame)
4694 * 01 CRC error
4695 * 00 abort
4696 */
4697 status = desc_status(info->rbufs[end]);
4698
4699 /* ignore CRC bit if not using CRC (bit is undefined) */
4700 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4701 status &= ~BIT1;
4702
4703 if (framesize == 0 ||
4704 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4705 free_rbufs(info, start, end);
4706 goto check_again;
4707 }
4708
4709 if (framesize < (2 + crc_size) || status & BIT0) {
4710 info->icount.rxshort++;
4711 framesize = 0;
4712 } else if (status & BIT1) {
4713 info->icount.rxcrc++;
4714 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4715 framesize = 0;
4716 }
4717
4718#if SYNCLINK_GENERIC_HDLC
4719 if (framesize == 0) {
4720 info->netdev->stats.rx_errors++;
4721 info->netdev->stats.rx_frame_errors++;
4722 }
4723#endif
4724
4725 DBGBH(("%s rx frame status=%04X size=%d\n",
4726 info->device_name, status, framesize));
4727 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4728
4729 if (framesize) {
4730 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4731 framesize -= crc_size;
4732 crc_size = 0;
4733 }
4734
4735 if (framesize > info->max_frame_size + crc_size)
4736 info->icount.rxlong++;
4737 else {
4738 /* copy dma buffer(s) to contiguous temp buffer */
4739 int copy_count = framesize;
4740 int i = start;
4741 unsigned char *p = info->tmp_rbuf;
4742 info->tmp_rbuf_count = framesize;
4743
4744 info->icount.rxok++;
4745
4746 while(copy_count) {
4747 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4748 memcpy(p, info->rbufs[i].buf, partial_count);
4749 p += partial_count;
4750 copy_count -= partial_count;
4751 if (++i == info->rbuf_count)
4752 i = 0;
4753 }
4754
4755 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4756 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4757 framesize++;
4758 }
4759
4760#if SYNCLINK_GENERIC_HDLC
4761 if (info->netcount)
4762 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4763 else
4764#endif
4765 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4766 }
4767 }
4768 free_rbufs(info, start, end);
4769 return true;
4770
4771cleanup:
4772 return false;
4773}
4774
4775/*
4776 * pass receive buffer (RAW synchronous mode) to tty layer
4777 * return true if buffer available, otherwise false
4778 */
4779static bool rx_get_buf(struct slgt_info *info)
4780{
4781 unsigned int i = info->rbuf_current;
4782 unsigned int count;
4783
4784 if (!desc_complete(info->rbufs[i]))
4785 return false;
4786 count = desc_count(info->rbufs[i]);
4787 switch(info->params.mode) {
4788 case MGSL_MODE_MONOSYNC:
4789 case MGSL_MODE_BISYNC:
4790 case MGSL_MODE_XSYNC:
4791 /* ignore residue in byte synchronous modes */
4792 if (desc_residue(info->rbufs[i]))
4793 count--;
4794 break;
4795 }
4796 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4797 DBGINFO(("rx_get_buf size=%d\n", count));
4798 if (count)
4799 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4800 info->flag_buf, count);
4801 free_rbufs(info, i, i);
4802 return true;
4803}
4804
4805static void reset_tbufs(struct slgt_info *info)
4806{
4807 unsigned int i;
4808 info->tbuf_current = 0;
4809 for (i=0 ; i < info->tbuf_count ; i++) {
4810 info->tbufs[i].status = 0;
4811 info->tbufs[i].count = 0;
4812 }
4813}
4814
4815/*
4816 * return number of free transmit DMA buffers
4817 */
4818static unsigned int free_tbuf_count(struct slgt_info *info)
4819{
4820 unsigned int count = 0;
4821 unsigned int i = info->tbuf_current;
4822
4823 do
4824 {
4825 if (desc_count(info->tbufs[i]))
4826 break; /* buffer in use */
4827 ++count;
4828 if (++i == info->tbuf_count)
4829 i=0;
4830 } while (i != info->tbuf_current);
4831
4832 /* if tx DMA active, last zero count buffer is in use */
4833 if (count && (rd_reg32(info, TDCSR) & BIT0))
4834 --count;
4835
4836 return count;
4837}
4838
4839/*
4840 * return number of bytes in unsent transmit DMA buffers
4841 * and the serial controller tx FIFO
4842 */
4843static unsigned int tbuf_bytes(struct slgt_info *info)
4844{
4845 unsigned int total_count = 0;
4846 unsigned int i = info->tbuf_current;
4847 unsigned int reg_value;
4848 unsigned int count;
4849 unsigned int active_buf_count = 0;
4850
4851 /*
4852 * Add descriptor counts for all tx DMA buffers.
4853 * If count is zero (cleared by DMA controller after read),
4854 * the buffer is complete or is actively being read from.
4855 *
4856 * Record buf_count of last buffer with zero count starting
4857 * from current ring position. buf_count is mirror
4858 * copy of count and is not cleared by serial controller.
4859 * If DMA controller is active, that buffer is actively
4860 * being read so add to total.
4861 */
4862 do {
4863 count = desc_count(info->tbufs[i]);
4864 if (count)
4865 total_count += count;
4866 else if (!total_count)
4867 active_buf_count = info->tbufs[i].buf_count;
4868 if (++i == info->tbuf_count)
4869 i = 0;
4870 } while (i != info->tbuf_current);
4871
4872 /* read tx DMA status register */
4873 reg_value = rd_reg32(info, TDCSR);
4874
4875 /* if tx DMA active, last zero count buffer is in use */
4876 if (reg_value & BIT0)
4877 total_count += active_buf_count;
4878
4879 /* add tx FIFO count = reg_value[15..8] */
4880 total_count += (reg_value >> 8) & 0xff;
4881
4882 /* if transmitter active add one byte for shift register */
4883 if (info->tx_active)
4884 total_count++;
4885
4886 return total_count;
4887}
4888
4889/*
4890 * load data into transmit DMA buffer ring and start transmitter if needed
4891 * return true if data accepted, otherwise false (buffers full)
4892 */
4893static bool tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4894{
4895 unsigned short count;
4896 unsigned int i;
4897 struct slgt_desc *d;
4898
4899 /* check required buffer space */
4900 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4901 return false;
4902
4903 DBGDATA(info, buf, size, "tx");
4904
4905 /*
4906 * copy data to one or more DMA buffers in circular ring
4907 * tbuf_start = first buffer for this data
4908 * tbuf_current = next free buffer
4909 *
4910 * Copy all data before making data visible to DMA controller by
4911 * setting descriptor count of the first buffer.
4912 * This prevents an active DMA controller from reading the first DMA
4913 * buffers of a frame and stopping before the final buffers are filled.
4914 */
4915
4916 info->tbuf_start = i = info->tbuf_current;
4917
4918 while (size) {
4919 d = &info->tbufs[i];
4920
4921 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4922 memcpy(d->buf, buf, count);
4923
4924 size -= count;
4925 buf += count;
4926
4927 /*
4928 * set EOF bit for last buffer of HDLC frame or
4929 * for every buffer in raw mode
4930 */
4931 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4932 info->params.mode == MGSL_MODE_RAW)
4933 set_desc_eof(*d, 1);
4934 else
4935 set_desc_eof(*d, 0);
4936
4937 /* set descriptor count for all but first buffer */
4938 if (i != info->tbuf_start)
4939 set_desc_count(*d, count);
4940 d->buf_count = count;
4941
4942 if (++i == info->tbuf_count)
4943 i = 0;
4944 }
4945
4946 info->tbuf_current = i;
4947
4948 /* set first buffer count to make new data visible to DMA controller */
4949 d = &info->tbufs[info->tbuf_start];
4950 set_desc_count(*d, d->buf_count);
4951
4952 /* start transmitter if needed and update transmit timeout */
4953 if (!info->tx_active)
4954 tx_start(info);
4955 update_tx_timer(info);
4956
4957 return true;
4958}
4959
4960static int register_test(struct slgt_info *info)
4961{
4962 static unsigned short patterns[] =
4963 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4964 static unsigned int count = ARRAY_SIZE(patterns);
4965 unsigned int i;
4966 int rc = 0;
4967
4968 for (i=0 ; i < count ; i++) {
4969 wr_reg16(info, TIR, patterns[i]);
4970 wr_reg16(info, BDR, patterns[(i+1)%count]);
4971 if ((rd_reg16(info, TIR) != patterns[i]) ||
4972 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4973 rc = -ENODEV;
4974 break;
4975 }
4976 }
4977 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4978 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4979 return rc;
4980}
4981
4982static int irq_test(struct slgt_info *info)
4983{
4984 unsigned long timeout;
4985 unsigned long flags;
4986 struct tty_struct *oldtty = info->port.tty;
4987 u32 speed = info->params.data_rate;
4988
4989 info->params.data_rate = 921600;
4990 info->port.tty = NULL;
4991
4992 spin_lock_irqsave(&info->lock, flags);
4993 async_mode(info);
4994 slgt_irq_on(info, IRQ_TXIDLE);
4995
4996 /* enable transmitter */
4997 wr_reg16(info, TCR,
4998 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4999
5000 /* write one byte and wait for tx idle */
5001 wr_reg16(info, TDR, 0);
5002
5003 /* assume failure */
5004 info->init_error = DiagStatus_IrqFailure;
5005 info->irq_occurred = false;
5006
5007 spin_unlock_irqrestore(&info->lock, flags);
5008
5009 timeout=100;
5010 while(timeout-- && !info->irq_occurred)
5011 msleep_interruptible(10);
5012
5013 spin_lock_irqsave(&info->lock,flags);
5014 reset_port(info);
5015 spin_unlock_irqrestore(&info->lock,flags);
5016
5017 info->params.data_rate = speed;
5018 info->port.tty = oldtty;
5019
5020 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
5021 return info->irq_occurred ? 0 : -ENODEV;
5022}
5023
5024static int loopback_test_rx(struct slgt_info *info)
5025{
5026 unsigned char *src, *dest;
5027 int count;
5028
5029 if (desc_complete(info->rbufs[0])) {
5030 count = desc_count(info->rbufs[0]);
5031 src = info->rbufs[0].buf;
5032 dest = info->tmp_rbuf;
5033
5034 for( ; count ; count-=2, src+=2) {
5035 /* src=data byte (src+1)=status byte */
5036 if (!(*(src+1) & (BIT9 + BIT8))) {
5037 *dest = *src;
5038 dest++;
5039 info->tmp_rbuf_count++;
5040 }
5041 }
5042 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
5043 return 1;
5044 }
5045 return 0;
5046}
5047
5048static int loopback_test(struct slgt_info *info)
5049{
5050#define TESTFRAMESIZE 20
5051
5052 unsigned long timeout;
5053 u16 count = TESTFRAMESIZE;
5054 unsigned char buf[TESTFRAMESIZE];
5055 int rc = -ENODEV;
5056 unsigned long flags;
5057
5058 struct tty_struct *oldtty = info->port.tty;
5059 MGSL_PARAMS params;
5060
5061 memcpy(¶ms, &info->params, sizeof(params));
5062
5063 info->params.mode = MGSL_MODE_ASYNC;
5064 info->params.data_rate = 921600;
5065 info->params.loopback = 1;
5066 info->port.tty = NULL;
5067
5068 /* build and send transmit frame */
5069 for (count = 0; count < TESTFRAMESIZE; ++count)
5070 buf[count] = (unsigned char)count;
5071
5072 info->tmp_rbuf_count = 0;
5073 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
5074
5075 /* program hardware for HDLC and enabled receiver */
5076 spin_lock_irqsave(&info->lock,flags);
5077 async_mode(info);
5078 rx_start(info);
5079 tx_load(info, buf, count);
5080 spin_unlock_irqrestore(&info->lock, flags);
5081
5082 /* wait for receive complete */
5083 for (timeout = 100; timeout; --timeout) {
5084 msleep_interruptible(10);
5085 if (loopback_test_rx(info)) {
5086 rc = 0;
5087 break;
5088 }
5089 }
5090
5091 /* verify received frame length and contents */
5092 if (!rc && (info->tmp_rbuf_count != count ||
5093 memcmp(buf, info->tmp_rbuf, count))) {
5094 rc = -ENODEV;
5095 }
5096
5097 spin_lock_irqsave(&info->lock,flags);
5098 reset_adapter(info);
5099 spin_unlock_irqrestore(&info->lock,flags);
5100
5101 memcpy(&info->params, ¶ms, sizeof(info->params));
5102 info->port.tty = oldtty;
5103
5104 info->init_error = rc ? DiagStatus_DmaFailure : 0;
5105 return rc;
5106}
5107
5108static int adapter_test(struct slgt_info *info)
5109{
5110 DBGINFO(("testing %s\n", info->device_name));
5111 if (register_test(info) < 0) {
5112 printk("register test failure %s addr=%08X\n",
5113 info->device_name, info->phys_reg_addr);
5114 } else if (irq_test(info) < 0) {
5115 printk("IRQ test failure %s IRQ=%d\n",
5116 info->device_name, info->irq_level);
5117 } else if (loopback_test(info) < 0) {
5118 printk("loopback test failure %s\n", info->device_name);
5119 }
5120 return info->init_error;
5121}
5122
5123/*
5124 * transmit timeout handler
5125 */
5126static void tx_timeout(unsigned long context)
5127{
5128 struct slgt_info *info = (struct slgt_info*)context;
5129 unsigned long flags;
5130
5131 DBGINFO(("%s tx_timeout\n", info->device_name));
5132 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5133 info->icount.txtimeout++;
5134 }
5135 spin_lock_irqsave(&info->lock,flags);
5136 tx_stop(info);
5137 spin_unlock_irqrestore(&info->lock,flags);
5138
5139#if SYNCLINK_GENERIC_HDLC
5140 if (info->netcount)
5141 hdlcdev_tx_done(info);
5142 else
5143#endif
5144 bh_transmit(info);
5145}
5146
5147/*
5148 * receive buffer polling timer
5149 */
5150static void rx_timeout(unsigned long context)
5151{
5152 struct slgt_info *info = (struct slgt_info*)context;
5153 unsigned long flags;
5154
5155 DBGINFO(("%s rx_timeout\n", info->device_name));
5156 spin_lock_irqsave(&info->lock, flags);
5157 info->pending_bh |= BH_RECEIVE;
5158 spin_unlock_irqrestore(&info->lock, flags);
5159 bh_handler(&info->task);
5160}
5161
1// SPDX-License-Identifier: GPL-1.0+
2/*
3 * Device driver for Microgate SyncLink GT serial adapters.
4 *
5 * written by Paul Fulghum for Microgate Corporation
6 * paulkf@microgate.com
7 *
8 * Microgate and SyncLink are trademarks of Microgate Corporation
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
13 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
14 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
15 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
16 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
17 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
18 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
19 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
20 * OF THE POSSIBILITY OF SUCH DAMAGE.
21 */
22
23/*
24 * DEBUG OUTPUT DEFINITIONS
25 *
26 * uncomment lines below to enable specific types of debug output
27 *
28 * DBGINFO information - most verbose output
29 * DBGERR serious errors
30 * DBGBH bottom half service routine debugging
31 * DBGISR interrupt service routine debugging
32 * DBGDATA output receive and transmit data
33 * DBGTBUF output transmit DMA buffers and registers
34 * DBGRBUF output receive DMA buffers and registers
35 */
36
37#define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
38#define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
39#define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
40#define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
41#define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
42/*#define DBGTBUF(info) dump_tbufs(info)*/
43/*#define DBGRBUF(info) dump_rbufs(info)*/
44
45
46#include <linux/module.h>
47#include <linux/errno.h>
48#include <linux/signal.h>
49#include <linux/sched.h>
50#include <linux/timer.h>
51#include <linux/interrupt.h>
52#include <linux/pci.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
55#include <linux/serial.h>
56#include <linux/major.h>
57#include <linux/string.h>
58#include <linux/fcntl.h>
59#include <linux/ptrace.h>
60#include <linux/ioport.h>
61#include <linux/mm.h>
62#include <linux/seq_file.h>
63#include <linux/slab.h>
64#include <linux/netdevice.h>
65#include <linux/vmalloc.h>
66#include <linux/init.h>
67#include <linux/delay.h>
68#include <linux/ioctl.h>
69#include <linux/termios.h>
70#include <linux/bitops.h>
71#include <linux/workqueue.h>
72#include <linux/hdlc.h>
73#include <linux/synclink.h>
74
75#include <asm/io.h>
76#include <asm/irq.h>
77#include <asm/dma.h>
78#include <asm/types.h>
79#include <linux/uaccess.h>
80
81#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
82#define SYNCLINK_GENERIC_HDLC 1
83#else
84#define SYNCLINK_GENERIC_HDLC 0
85#endif
86
87/*
88 * module identification
89 */
90static const char driver_name[] = "SyncLink GT";
91static const char tty_dev_prefix[] = "ttySLG";
92MODULE_LICENSE("GPL");
93#define MAX_DEVICES 32
94
95static const struct pci_device_id pci_table[] = {
96 { PCI_VDEVICE(MICROGATE, SYNCLINK_GT_DEVICE_ID) },
97 { PCI_VDEVICE(MICROGATE, SYNCLINK_GT2_DEVICE_ID) },
98 { PCI_VDEVICE(MICROGATE, SYNCLINK_GT4_DEVICE_ID) },
99 { PCI_VDEVICE(MICROGATE, SYNCLINK_AC_DEVICE_ID) },
100 { 0 }, /* terminate list */
101};
102MODULE_DEVICE_TABLE(pci, pci_table);
103
104static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
105static void remove_one(struct pci_dev *dev);
106static struct pci_driver pci_driver = {
107 .name = "synclink_gt",
108 .id_table = pci_table,
109 .probe = init_one,
110 .remove = remove_one,
111};
112
113static bool pci_registered;
114
115/*
116 * module configuration and status
117 */
118static struct slgt_info *slgt_device_list;
119static int slgt_device_count;
120
121static int ttymajor;
122static int debug_level;
123static int maxframe[MAX_DEVICES];
124
125module_param(ttymajor, int, 0);
126module_param(debug_level, int, 0);
127module_param_array(maxframe, int, NULL, 0);
128
129MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
130MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
131MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
132
133/*
134 * tty support and callbacks
135 */
136static struct tty_driver *serial_driver;
137
138static void wait_until_sent(struct tty_struct *tty, int timeout);
139static void flush_buffer(struct tty_struct *tty);
140static void tx_release(struct tty_struct *tty);
141
142/*
143 * generic HDLC support
144 */
145#define dev_to_port(D) (dev_to_hdlc(D)->priv)
146
147
148/*
149 * device specific structures, macros and functions
150 */
151
152#define SLGT_MAX_PORTS 4
153#define SLGT_REG_SIZE 256
154
155/*
156 * conditional wait facility
157 */
158struct cond_wait {
159 struct cond_wait *next;
160 wait_queue_head_t q;
161 wait_queue_entry_t wait;
162 unsigned int data;
163};
164static void flush_cond_wait(struct cond_wait **head);
165
166/*
167 * DMA buffer descriptor and access macros
168 */
169struct slgt_desc
170{
171 __le16 count;
172 __le16 status;
173 __le32 pbuf; /* physical address of data buffer */
174 __le32 next; /* physical address of next descriptor */
175
176 /* driver book keeping */
177 char *buf; /* virtual address of data buffer */
178 unsigned int pdesc; /* physical address of this descriptor */
179 dma_addr_t buf_dma_addr;
180 unsigned short buf_count;
181};
182
183#define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
184#define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
185#define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
186#define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
187#define set_desc_status(a, b) (a).status = cpu_to_le16((unsigned short)(b))
188#define desc_count(a) (le16_to_cpu((a).count))
189#define desc_status(a) (le16_to_cpu((a).status))
190#define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
191#define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
192#define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
193#define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
194#define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
195
196struct _input_signal_events {
197 int ri_up;
198 int ri_down;
199 int dsr_up;
200 int dsr_down;
201 int dcd_up;
202 int dcd_down;
203 int cts_up;
204 int cts_down;
205};
206
207/*
208 * device instance data structure
209 */
210struct slgt_info {
211 void *if_ptr; /* General purpose pointer (used by SPPP) */
212 struct tty_port port;
213
214 struct slgt_info *next_device; /* device list link */
215
216 char device_name[25];
217 struct pci_dev *pdev;
218
219 int port_count; /* count of ports on adapter */
220 int adapter_num; /* adapter instance number */
221 int port_num; /* port instance number */
222
223 /* array of pointers to port contexts on this adapter */
224 struct slgt_info *port_array[SLGT_MAX_PORTS];
225
226 int line; /* tty line instance number */
227
228 struct mgsl_icount icount;
229
230 int timeout;
231 int x_char; /* xon/xoff character */
232 unsigned int read_status_mask;
233 unsigned int ignore_status_mask;
234
235 wait_queue_head_t status_event_wait_q;
236 wait_queue_head_t event_wait_q;
237 struct timer_list tx_timer;
238 struct timer_list rx_timer;
239
240 unsigned int gpio_present;
241 struct cond_wait *gpio_wait_q;
242
243 spinlock_t lock; /* spinlock for synchronizing with ISR */
244
245 struct work_struct task;
246 u32 pending_bh;
247 bool bh_requested;
248 bool bh_running;
249
250 int isr_overflow;
251 bool irq_requested; /* true if IRQ requested */
252 bool irq_occurred; /* for diagnostics use */
253
254 /* device configuration */
255
256 unsigned int bus_type;
257 unsigned int irq_level;
258 unsigned long irq_flags;
259
260 unsigned char __iomem * reg_addr; /* memory mapped registers address */
261 u32 phys_reg_addr;
262 bool reg_addr_requested;
263
264 MGSL_PARAMS params; /* communications parameters */
265 u32 idle_mode;
266 u32 max_frame_size; /* as set by device config */
267
268 unsigned int rbuf_fill_level;
269 unsigned int rx_pio;
270 unsigned int if_mode;
271 unsigned int base_clock;
272 unsigned int xsync;
273 unsigned int xctrl;
274
275 /* device status */
276
277 bool rx_enabled;
278 bool rx_restart;
279
280 bool tx_enabled;
281 bool tx_active;
282
283 unsigned char signals; /* serial signal states */
284 int init_error; /* initialization error */
285
286 unsigned char *tx_buf;
287 int tx_count;
288
289 bool drop_rts_on_tx_done;
290 struct _input_signal_events input_signal_events;
291
292 int dcd_chkcount; /* check counts to prevent */
293 int cts_chkcount; /* too many IRQs if a signal */
294 int dsr_chkcount; /* is floating */
295 int ri_chkcount;
296
297 char *bufs; /* virtual address of DMA buffer lists */
298 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
299
300 unsigned int rbuf_count;
301 struct slgt_desc *rbufs;
302 unsigned int rbuf_current;
303 unsigned int rbuf_index;
304 unsigned int rbuf_fill_index;
305 unsigned short rbuf_fill_count;
306
307 unsigned int tbuf_count;
308 struct slgt_desc *tbufs;
309 unsigned int tbuf_current;
310 unsigned int tbuf_start;
311
312 unsigned char *tmp_rbuf;
313 unsigned int tmp_rbuf_count;
314
315 /* SPPP/Cisco HDLC device parts */
316
317 int netcount;
318 spinlock_t netlock;
319#if SYNCLINK_GENERIC_HDLC
320 struct net_device *netdev;
321#endif
322
323};
324
325static const MGSL_PARAMS default_params = {
326 .mode = MGSL_MODE_HDLC,
327 .loopback = 0,
328 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
329 .encoding = HDLC_ENCODING_NRZI_SPACE,
330 .clock_speed = 0,
331 .addr_filter = 0xff,
332 .crc_type = HDLC_CRC_16_CCITT,
333 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
334 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
335 .data_rate = 9600,
336 .data_bits = 8,
337 .stop_bits = 1,
338 .parity = ASYNC_PARITY_NONE
339};
340
341
342#define BH_RECEIVE 1
343#define BH_TRANSMIT 2
344#define BH_STATUS 4
345#define IO_PIN_SHUTDOWN_LIMIT 100
346
347#define DMABUFSIZE 256
348#define DESC_LIST_SIZE 4096
349
350#define MASK_PARITY BIT1
351#define MASK_FRAMING BIT0
352#define MASK_BREAK BIT14
353#define MASK_OVERRUN BIT4
354
355#define GSR 0x00 /* global status */
356#define JCR 0x04 /* JTAG control */
357#define IODR 0x08 /* GPIO direction */
358#define IOER 0x0c /* GPIO interrupt enable */
359#define IOVR 0x10 /* GPIO value */
360#define IOSR 0x14 /* GPIO interrupt status */
361#define TDR 0x80 /* tx data */
362#define RDR 0x80 /* rx data */
363#define TCR 0x82 /* tx control */
364#define TIR 0x84 /* tx idle */
365#define TPR 0x85 /* tx preamble */
366#define RCR 0x86 /* rx control */
367#define VCR 0x88 /* V.24 control */
368#define CCR 0x89 /* clock control */
369#define BDR 0x8a /* baud divisor */
370#define SCR 0x8c /* serial control */
371#define SSR 0x8e /* serial status */
372#define RDCSR 0x90 /* rx DMA control/status */
373#define TDCSR 0x94 /* tx DMA control/status */
374#define RDDAR 0x98 /* rx DMA descriptor address */
375#define TDDAR 0x9c /* tx DMA descriptor address */
376#define XSR 0x40 /* extended sync pattern */
377#define XCR 0x44 /* extended control */
378
379#define RXIDLE BIT14
380#define RXBREAK BIT14
381#define IRQ_TXDATA BIT13
382#define IRQ_TXIDLE BIT12
383#define IRQ_TXUNDER BIT11 /* HDLC */
384#define IRQ_RXDATA BIT10
385#define IRQ_RXIDLE BIT9 /* HDLC */
386#define IRQ_RXBREAK BIT9 /* async */
387#define IRQ_RXOVER BIT8
388#define IRQ_DSR BIT7
389#define IRQ_CTS BIT6
390#define IRQ_DCD BIT5
391#define IRQ_RI BIT4
392#define IRQ_ALL 0x3ff0
393#define IRQ_MASTER BIT0
394
395#define slgt_irq_on(info, mask) \
396 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
397#define slgt_irq_off(info, mask) \
398 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
399
400static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
401static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
402static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
403static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
404static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
405static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
406
407static void msc_set_vcr(struct slgt_info *info);
408
409static int startup(struct slgt_info *info);
410static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
411static void shutdown(struct slgt_info *info);
412static void program_hw(struct slgt_info *info);
413static void change_params(struct slgt_info *info);
414
415static int adapter_test(struct slgt_info *info);
416
417static void reset_port(struct slgt_info *info);
418static void async_mode(struct slgt_info *info);
419static void sync_mode(struct slgt_info *info);
420
421static void rx_stop(struct slgt_info *info);
422static void rx_start(struct slgt_info *info);
423static void reset_rbufs(struct slgt_info *info);
424static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
425static bool rx_get_frame(struct slgt_info *info);
426static bool rx_get_buf(struct slgt_info *info);
427
428static void tx_start(struct slgt_info *info);
429static void tx_stop(struct slgt_info *info);
430static void tx_set_idle(struct slgt_info *info);
431static unsigned int tbuf_bytes(struct slgt_info *info);
432static void reset_tbufs(struct slgt_info *info);
433static void tdma_reset(struct slgt_info *info);
434static bool tx_load(struct slgt_info *info, const u8 *buf, unsigned int count);
435
436static void get_gtsignals(struct slgt_info *info);
437static void set_gtsignals(struct slgt_info *info);
438static void set_rate(struct slgt_info *info, u32 data_rate);
439
440static void bh_transmit(struct slgt_info *info);
441static void isr_txeom(struct slgt_info *info, unsigned short status);
442
443static void tx_timeout(struct timer_list *t);
444static void rx_timeout(struct timer_list *t);
445
446/*
447 * ioctl handlers
448 */
449static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
450static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
451static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
452static int get_txidle(struct slgt_info *info, int __user *idle_mode);
453static int set_txidle(struct slgt_info *info, int idle_mode);
454static int tx_enable(struct slgt_info *info, int enable);
455static int tx_abort(struct slgt_info *info);
456static int rx_enable(struct slgt_info *info, int enable);
457static int modem_input_wait(struct slgt_info *info,int arg);
458static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
459static int get_interface(struct slgt_info *info, int __user *if_mode);
460static int set_interface(struct slgt_info *info, int if_mode);
461static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
462static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
463static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
464static int get_xsync(struct slgt_info *info, int __user *if_mode);
465static int set_xsync(struct slgt_info *info, int if_mode);
466static int get_xctrl(struct slgt_info *info, int __user *if_mode);
467static int set_xctrl(struct slgt_info *info, int if_mode);
468
469/*
470 * driver functions
471 */
472static void release_resources(struct slgt_info *info);
473
474/*
475 * DEBUG OUTPUT CODE
476 */
477#ifndef DBGINFO
478#define DBGINFO(fmt)
479#endif
480#ifndef DBGERR
481#define DBGERR(fmt)
482#endif
483#ifndef DBGBH
484#define DBGBH(fmt)
485#endif
486#ifndef DBGISR
487#define DBGISR(fmt)
488#endif
489
490#ifdef DBGDATA
491static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
492{
493 int i;
494 int linecount;
495 printk("%s %s data:\n",info->device_name, label);
496 while(count) {
497 linecount = (count > 16) ? 16 : count;
498 for(i=0; i < linecount; i++)
499 printk("%02X ",(unsigned char)data[i]);
500 for(;i<17;i++)
501 printk(" ");
502 for(i=0;i<linecount;i++) {
503 if (data[i]>=040 && data[i]<=0176)
504 printk("%c",data[i]);
505 else
506 printk(".");
507 }
508 printk("\n");
509 data += linecount;
510 count -= linecount;
511 }
512}
513#else
514#define DBGDATA(info, buf, size, label)
515#endif
516
517#ifdef DBGTBUF
518static void dump_tbufs(struct slgt_info *info)
519{
520 int i;
521 printk("tbuf_current=%d\n", info->tbuf_current);
522 for (i=0 ; i < info->tbuf_count ; i++) {
523 printk("%d: count=%04X status=%04X\n",
524 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
525 }
526}
527#else
528#define DBGTBUF(info)
529#endif
530
531#ifdef DBGRBUF
532static void dump_rbufs(struct slgt_info *info)
533{
534 int i;
535 printk("rbuf_current=%d\n", info->rbuf_current);
536 for (i=0 ; i < info->rbuf_count ; i++) {
537 printk("%d: count=%04X status=%04X\n",
538 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
539 }
540}
541#else
542#define DBGRBUF(info)
543#endif
544
545static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
546{
547#ifdef SANITY_CHECK
548 if (!info) {
549 printk("null struct slgt_info for (%s) in %s\n", devname, name);
550 return 1;
551 }
552#else
553 if (!info)
554 return 1;
555#endif
556 return 0;
557}
558
559/*
560 * line discipline callback wrappers
561 *
562 * The wrappers maintain line discipline references
563 * while calling into the line discipline.
564 *
565 * ldisc_receive_buf - pass receive data to line discipline
566 */
567static void ldisc_receive_buf(struct tty_struct *tty,
568 const __u8 *data, char *flags, int count)
569{
570 struct tty_ldisc *ld;
571 if (!tty)
572 return;
573 ld = tty_ldisc_ref(tty);
574 if (ld) {
575 if (ld->ops->receive_buf)
576 ld->ops->receive_buf(tty, data, flags, count);
577 tty_ldisc_deref(ld);
578 }
579}
580
581/* tty callbacks */
582
583static int open(struct tty_struct *tty, struct file *filp)
584{
585 struct slgt_info *info;
586 int retval, line;
587 unsigned long flags;
588
589 line = tty->index;
590 if (line >= slgt_device_count) {
591 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
592 return -ENODEV;
593 }
594
595 info = slgt_device_list;
596 while(info && info->line != line)
597 info = info->next_device;
598 if (sanity_check(info, tty->name, "open"))
599 return -ENODEV;
600 if (info->init_error) {
601 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
602 return -ENODEV;
603 }
604
605 tty->driver_data = info;
606 info->port.tty = tty;
607
608 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
609
610 mutex_lock(&info->port.mutex);
611
612 spin_lock_irqsave(&info->netlock, flags);
613 if (info->netcount) {
614 retval = -EBUSY;
615 spin_unlock_irqrestore(&info->netlock, flags);
616 mutex_unlock(&info->port.mutex);
617 goto cleanup;
618 }
619 info->port.count++;
620 spin_unlock_irqrestore(&info->netlock, flags);
621
622 if (info->port.count == 1) {
623 /* 1st open on this device, init hardware */
624 retval = startup(info);
625 if (retval < 0) {
626 mutex_unlock(&info->port.mutex);
627 goto cleanup;
628 }
629 }
630 mutex_unlock(&info->port.mutex);
631 retval = block_til_ready(tty, filp, info);
632 if (retval) {
633 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
634 goto cleanup;
635 }
636
637 retval = 0;
638
639cleanup:
640 if (retval) {
641 if (tty->count == 1)
642 info->port.tty = NULL; /* tty layer will release tty struct */
643 if(info->port.count)
644 info->port.count--;
645 }
646
647 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
648 return retval;
649}
650
651static void close(struct tty_struct *tty, struct file *filp)
652{
653 struct slgt_info *info = tty->driver_data;
654
655 if (sanity_check(info, tty->name, "close"))
656 return;
657 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
658
659 if (tty_port_close_start(&info->port, tty, filp) == 0)
660 goto cleanup;
661
662 mutex_lock(&info->port.mutex);
663 if (tty_port_initialized(&info->port))
664 wait_until_sent(tty, info->timeout);
665 flush_buffer(tty);
666 tty_ldisc_flush(tty);
667
668 shutdown(info);
669 mutex_unlock(&info->port.mutex);
670
671 tty_port_close_end(&info->port, tty);
672 info->port.tty = NULL;
673cleanup:
674 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
675}
676
677static void hangup(struct tty_struct *tty)
678{
679 struct slgt_info *info = tty->driver_data;
680 unsigned long flags;
681
682 if (sanity_check(info, tty->name, "hangup"))
683 return;
684 DBGINFO(("%s hangup\n", info->device_name));
685
686 flush_buffer(tty);
687
688 mutex_lock(&info->port.mutex);
689 shutdown(info);
690
691 spin_lock_irqsave(&info->port.lock, flags);
692 info->port.count = 0;
693 info->port.tty = NULL;
694 spin_unlock_irqrestore(&info->port.lock, flags);
695 tty_port_set_active(&info->port, false);
696 mutex_unlock(&info->port.mutex);
697
698 wake_up_interruptible(&info->port.open_wait);
699}
700
701static void set_termios(struct tty_struct *tty,
702 const struct ktermios *old_termios)
703{
704 struct slgt_info *info = tty->driver_data;
705 unsigned long flags;
706
707 DBGINFO(("%s set_termios\n", tty->driver->name));
708
709 change_params(info);
710
711 /* Handle transition to B0 status */
712 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
713 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
714 spin_lock_irqsave(&info->lock,flags);
715 set_gtsignals(info);
716 spin_unlock_irqrestore(&info->lock,flags);
717 }
718
719 /* Handle transition away from B0 status */
720 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
721 info->signals |= SerialSignal_DTR;
722 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
723 info->signals |= SerialSignal_RTS;
724 spin_lock_irqsave(&info->lock,flags);
725 set_gtsignals(info);
726 spin_unlock_irqrestore(&info->lock,flags);
727 }
728
729 /* Handle turning off CRTSCTS */
730 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
731 tty->hw_stopped = false;
732 tx_release(tty);
733 }
734}
735
736static void update_tx_timer(struct slgt_info *info)
737{
738 /*
739 * use worst case speed of 1200bps to calculate transmit timeout
740 * based on data in buffers (tbuf_bytes) and FIFO (128 bytes)
741 */
742 if (info->params.mode == MGSL_MODE_HDLC) {
743 int timeout = (tbuf_bytes(info) * 7) + 1000;
744 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(timeout));
745 }
746}
747
748static ssize_t write(struct tty_struct *tty, const u8 *buf, size_t count)
749{
750 int ret = 0;
751 struct slgt_info *info = tty->driver_data;
752 unsigned long flags;
753
754 if (sanity_check(info, tty->name, "write"))
755 return -EIO;
756
757 DBGINFO(("%s write count=%zu\n", info->device_name, count));
758
759 if (!info->tx_buf || (count > info->max_frame_size))
760 return -EIO;
761
762 if (!count || tty->flow.stopped || tty->hw_stopped)
763 return 0;
764
765 spin_lock_irqsave(&info->lock, flags);
766
767 if (info->tx_count) {
768 /* send accumulated data from send_char() */
769 if (!tx_load(info, info->tx_buf, info->tx_count))
770 goto cleanup;
771 info->tx_count = 0;
772 }
773
774 if (tx_load(info, buf, count))
775 ret = count;
776
777cleanup:
778 spin_unlock_irqrestore(&info->lock, flags);
779 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
780 return ret;
781}
782
783static int put_char(struct tty_struct *tty, u8 ch)
784{
785 struct slgt_info *info = tty->driver_data;
786 unsigned long flags;
787 int ret = 0;
788
789 if (sanity_check(info, tty->name, "put_char"))
790 return 0;
791 DBGINFO(("%s put_char(%u)\n", info->device_name, ch));
792 if (!info->tx_buf)
793 return 0;
794 spin_lock_irqsave(&info->lock,flags);
795 if (info->tx_count < info->max_frame_size) {
796 info->tx_buf[info->tx_count++] = ch;
797 ret = 1;
798 }
799 spin_unlock_irqrestore(&info->lock,flags);
800 return ret;
801}
802
803static void send_xchar(struct tty_struct *tty, char ch)
804{
805 struct slgt_info *info = tty->driver_data;
806 unsigned long flags;
807
808 if (sanity_check(info, tty->name, "send_xchar"))
809 return;
810 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
811 info->x_char = ch;
812 if (ch) {
813 spin_lock_irqsave(&info->lock,flags);
814 if (!info->tx_enabled)
815 tx_start(info);
816 spin_unlock_irqrestore(&info->lock,flags);
817 }
818}
819
820static void wait_until_sent(struct tty_struct *tty, int timeout)
821{
822 struct slgt_info *info = tty->driver_data;
823 unsigned long orig_jiffies, char_time;
824
825 if (!info )
826 return;
827 if (sanity_check(info, tty->name, "wait_until_sent"))
828 return;
829 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
830 if (!tty_port_initialized(&info->port))
831 goto exit;
832
833 orig_jiffies = jiffies;
834
835 /* Set check interval to 1/5 of estimated time to
836 * send a character, and make it at least 1. The check
837 * interval should also be less than the timeout.
838 * Note: use tight timings here to satisfy the NIST-PCTS.
839 */
840
841 if (info->params.data_rate) {
842 char_time = info->timeout/(32 * 5);
843 if (!char_time)
844 char_time++;
845 } else
846 char_time = 1;
847
848 if (timeout)
849 char_time = min_t(unsigned long, char_time, timeout);
850
851 while (info->tx_active) {
852 msleep_interruptible(jiffies_to_msecs(char_time));
853 if (signal_pending(current))
854 break;
855 if (timeout && time_after(jiffies, orig_jiffies + timeout))
856 break;
857 }
858exit:
859 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
860}
861
862static unsigned int write_room(struct tty_struct *tty)
863{
864 struct slgt_info *info = tty->driver_data;
865 unsigned int ret;
866
867 if (sanity_check(info, tty->name, "write_room"))
868 return 0;
869 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
870 DBGINFO(("%s write_room=%u\n", info->device_name, ret));
871 return ret;
872}
873
874static void flush_chars(struct tty_struct *tty)
875{
876 struct slgt_info *info = tty->driver_data;
877 unsigned long flags;
878
879 if (sanity_check(info, tty->name, "flush_chars"))
880 return;
881 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
882
883 if (info->tx_count <= 0 || tty->flow.stopped ||
884 tty->hw_stopped || !info->tx_buf)
885 return;
886
887 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
888
889 spin_lock_irqsave(&info->lock,flags);
890 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
891 info->tx_count = 0;
892 spin_unlock_irqrestore(&info->lock,flags);
893}
894
895static void flush_buffer(struct tty_struct *tty)
896{
897 struct slgt_info *info = tty->driver_data;
898 unsigned long flags;
899
900 if (sanity_check(info, tty->name, "flush_buffer"))
901 return;
902 DBGINFO(("%s flush_buffer\n", info->device_name));
903
904 spin_lock_irqsave(&info->lock, flags);
905 info->tx_count = 0;
906 spin_unlock_irqrestore(&info->lock, flags);
907
908 tty_wakeup(tty);
909}
910
911/*
912 * throttle (stop) transmitter
913 */
914static void tx_hold(struct tty_struct *tty)
915{
916 struct slgt_info *info = tty->driver_data;
917 unsigned long flags;
918
919 if (sanity_check(info, tty->name, "tx_hold"))
920 return;
921 DBGINFO(("%s tx_hold\n", info->device_name));
922 spin_lock_irqsave(&info->lock,flags);
923 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
924 tx_stop(info);
925 spin_unlock_irqrestore(&info->lock,flags);
926}
927
928/*
929 * release (start) transmitter
930 */
931static void tx_release(struct tty_struct *tty)
932{
933 struct slgt_info *info = tty->driver_data;
934 unsigned long flags;
935
936 if (sanity_check(info, tty->name, "tx_release"))
937 return;
938 DBGINFO(("%s tx_release\n", info->device_name));
939 spin_lock_irqsave(&info->lock, flags);
940 if (info->tx_count && tx_load(info, info->tx_buf, info->tx_count))
941 info->tx_count = 0;
942 spin_unlock_irqrestore(&info->lock, flags);
943}
944
945/*
946 * Service an IOCTL request
947 *
948 * Arguments
949 *
950 * tty pointer to tty instance data
951 * cmd IOCTL command code
952 * arg command argument/context
953 *
954 * Return 0 if success, otherwise error code
955 */
956static int ioctl(struct tty_struct *tty,
957 unsigned int cmd, unsigned long arg)
958{
959 struct slgt_info *info = tty->driver_data;
960 void __user *argp = (void __user *)arg;
961 int ret;
962
963 if (sanity_check(info, tty->name, "ioctl"))
964 return -ENODEV;
965 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
966
967 if (cmd != TIOCMIWAIT) {
968 if (tty_io_error(tty))
969 return -EIO;
970 }
971
972 switch (cmd) {
973 case MGSL_IOCWAITEVENT:
974 return wait_mgsl_event(info, argp);
975 case TIOCMIWAIT:
976 return modem_input_wait(info,(int)arg);
977 case MGSL_IOCSGPIO:
978 return set_gpio(info, argp);
979 case MGSL_IOCGGPIO:
980 return get_gpio(info, argp);
981 case MGSL_IOCWAITGPIO:
982 return wait_gpio(info, argp);
983 case MGSL_IOCGXSYNC:
984 return get_xsync(info, argp);
985 case MGSL_IOCSXSYNC:
986 return set_xsync(info, (int)arg);
987 case MGSL_IOCGXCTRL:
988 return get_xctrl(info, argp);
989 case MGSL_IOCSXCTRL:
990 return set_xctrl(info, (int)arg);
991 }
992 mutex_lock(&info->port.mutex);
993 switch (cmd) {
994 case MGSL_IOCGPARAMS:
995 ret = get_params(info, argp);
996 break;
997 case MGSL_IOCSPARAMS:
998 ret = set_params(info, argp);
999 break;
1000 case MGSL_IOCGTXIDLE:
1001 ret = get_txidle(info, argp);
1002 break;
1003 case MGSL_IOCSTXIDLE:
1004 ret = set_txidle(info, (int)arg);
1005 break;
1006 case MGSL_IOCTXENABLE:
1007 ret = tx_enable(info, (int)arg);
1008 break;
1009 case MGSL_IOCRXENABLE:
1010 ret = rx_enable(info, (int)arg);
1011 break;
1012 case MGSL_IOCTXABORT:
1013 ret = tx_abort(info);
1014 break;
1015 case MGSL_IOCGSTATS:
1016 ret = get_stats(info, argp);
1017 break;
1018 case MGSL_IOCGIF:
1019 ret = get_interface(info, argp);
1020 break;
1021 case MGSL_IOCSIF:
1022 ret = set_interface(info,(int)arg);
1023 break;
1024 default:
1025 ret = -ENOIOCTLCMD;
1026 }
1027 mutex_unlock(&info->port.mutex);
1028 return ret;
1029}
1030
1031static int get_icount(struct tty_struct *tty,
1032 struct serial_icounter_struct *icount)
1033
1034{
1035 struct slgt_info *info = tty->driver_data;
1036 struct mgsl_icount cnow; /* kernel counter temps */
1037 unsigned long flags;
1038
1039 spin_lock_irqsave(&info->lock,flags);
1040 cnow = info->icount;
1041 spin_unlock_irqrestore(&info->lock,flags);
1042
1043 icount->cts = cnow.cts;
1044 icount->dsr = cnow.dsr;
1045 icount->rng = cnow.rng;
1046 icount->dcd = cnow.dcd;
1047 icount->rx = cnow.rx;
1048 icount->tx = cnow.tx;
1049 icount->frame = cnow.frame;
1050 icount->overrun = cnow.overrun;
1051 icount->parity = cnow.parity;
1052 icount->brk = cnow.brk;
1053 icount->buf_overrun = cnow.buf_overrun;
1054
1055 return 0;
1056}
1057
1058/*
1059 * support for 32 bit ioctl calls on 64 bit systems
1060 */
1061#ifdef CONFIG_COMPAT
1062static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1063{
1064 struct MGSL_PARAMS32 tmp_params;
1065
1066 DBGINFO(("%s get_params32\n", info->device_name));
1067 memset(&tmp_params, 0, sizeof(tmp_params));
1068 tmp_params.mode = (compat_ulong_t)info->params.mode;
1069 tmp_params.loopback = info->params.loopback;
1070 tmp_params.flags = info->params.flags;
1071 tmp_params.encoding = info->params.encoding;
1072 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1073 tmp_params.addr_filter = info->params.addr_filter;
1074 tmp_params.crc_type = info->params.crc_type;
1075 tmp_params.preamble_length = info->params.preamble_length;
1076 tmp_params.preamble = info->params.preamble;
1077 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1078 tmp_params.data_bits = info->params.data_bits;
1079 tmp_params.stop_bits = info->params.stop_bits;
1080 tmp_params.parity = info->params.parity;
1081 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1082 return -EFAULT;
1083 return 0;
1084}
1085
1086static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1087{
1088 struct MGSL_PARAMS32 tmp_params;
1089 unsigned long flags;
1090
1091 DBGINFO(("%s set_params32\n", info->device_name));
1092 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1093 return -EFAULT;
1094
1095 spin_lock_irqsave(&info->lock, flags);
1096 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1097 info->base_clock = tmp_params.clock_speed;
1098 } else {
1099 info->params.mode = tmp_params.mode;
1100 info->params.loopback = tmp_params.loopback;
1101 info->params.flags = tmp_params.flags;
1102 info->params.encoding = tmp_params.encoding;
1103 info->params.clock_speed = tmp_params.clock_speed;
1104 info->params.addr_filter = tmp_params.addr_filter;
1105 info->params.crc_type = tmp_params.crc_type;
1106 info->params.preamble_length = tmp_params.preamble_length;
1107 info->params.preamble = tmp_params.preamble;
1108 info->params.data_rate = tmp_params.data_rate;
1109 info->params.data_bits = tmp_params.data_bits;
1110 info->params.stop_bits = tmp_params.stop_bits;
1111 info->params.parity = tmp_params.parity;
1112 }
1113 spin_unlock_irqrestore(&info->lock, flags);
1114
1115 program_hw(info);
1116
1117 return 0;
1118}
1119
1120static long slgt_compat_ioctl(struct tty_struct *tty,
1121 unsigned int cmd, unsigned long arg)
1122{
1123 struct slgt_info *info = tty->driver_data;
1124 int rc;
1125
1126 if (sanity_check(info, tty->name, "compat_ioctl"))
1127 return -ENODEV;
1128 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1129
1130 switch (cmd) {
1131 case MGSL_IOCSPARAMS32:
1132 rc = set_params32(info, compat_ptr(arg));
1133 break;
1134
1135 case MGSL_IOCGPARAMS32:
1136 rc = get_params32(info, compat_ptr(arg));
1137 break;
1138
1139 case MGSL_IOCGPARAMS:
1140 case MGSL_IOCSPARAMS:
1141 case MGSL_IOCGTXIDLE:
1142 case MGSL_IOCGSTATS:
1143 case MGSL_IOCWAITEVENT:
1144 case MGSL_IOCGIF:
1145 case MGSL_IOCSGPIO:
1146 case MGSL_IOCGGPIO:
1147 case MGSL_IOCWAITGPIO:
1148 case MGSL_IOCGXSYNC:
1149 case MGSL_IOCGXCTRL:
1150 rc = ioctl(tty, cmd, (unsigned long)compat_ptr(arg));
1151 break;
1152 default:
1153 rc = ioctl(tty, cmd, arg);
1154 }
1155 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1156 return rc;
1157}
1158#else
1159#define slgt_compat_ioctl NULL
1160#endif /* ifdef CONFIG_COMPAT */
1161
1162/*
1163 * proc fs support
1164 */
1165static inline void line_info(struct seq_file *m, struct slgt_info *info)
1166{
1167 char stat_buf[30];
1168 unsigned long flags;
1169
1170 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1171 info->device_name, info->phys_reg_addr,
1172 info->irq_level, info->max_frame_size);
1173
1174 /* output current serial signal states */
1175 spin_lock_irqsave(&info->lock,flags);
1176 get_gtsignals(info);
1177 spin_unlock_irqrestore(&info->lock,flags);
1178
1179 stat_buf[0] = 0;
1180 stat_buf[1] = 0;
1181 if (info->signals & SerialSignal_RTS)
1182 strcat(stat_buf, "|RTS");
1183 if (info->signals & SerialSignal_CTS)
1184 strcat(stat_buf, "|CTS");
1185 if (info->signals & SerialSignal_DTR)
1186 strcat(stat_buf, "|DTR");
1187 if (info->signals & SerialSignal_DSR)
1188 strcat(stat_buf, "|DSR");
1189 if (info->signals & SerialSignal_DCD)
1190 strcat(stat_buf, "|CD");
1191 if (info->signals & SerialSignal_RI)
1192 strcat(stat_buf, "|RI");
1193
1194 if (info->params.mode != MGSL_MODE_ASYNC) {
1195 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1196 info->icount.txok, info->icount.rxok);
1197 if (info->icount.txunder)
1198 seq_printf(m, " txunder:%d", info->icount.txunder);
1199 if (info->icount.txabort)
1200 seq_printf(m, " txabort:%d", info->icount.txabort);
1201 if (info->icount.rxshort)
1202 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1203 if (info->icount.rxlong)
1204 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1205 if (info->icount.rxover)
1206 seq_printf(m, " rxover:%d", info->icount.rxover);
1207 if (info->icount.rxcrc)
1208 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1209 } else {
1210 seq_printf(m, "\tASYNC tx:%d rx:%d",
1211 info->icount.tx, info->icount.rx);
1212 if (info->icount.frame)
1213 seq_printf(m, " fe:%d", info->icount.frame);
1214 if (info->icount.parity)
1215 seq_printf(m, " pe:%d", info->icount.parity);
1216 if (info->icount.brk)
1217 seq_printf(m, " brk:%d", info->icount.brk);
1218 if (info->icount.overrun)
1219 seq_printf(m, " oe:%d", info->icount.overrun);
1220 }
1221
1222 /* Append serial signal status to end */
1223 seq_printf(m, " %s\n", stat_buf+1);
1224
1225 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1226 info->tx_active,info->bh_requested,info->bh_running,
1227 info->pending_bh);
1228}
1229
1230/* Called to print information about devices
1231 */
1232static int synclink_gt_proc_show(struct seq_file *m, void *v)
1233{
1234 struct slgt_info *info;
1235
1236 seq_puts(m, "synclink_gt driver\n");
1237
1238 info = slgt_device_list;
1239 while( info ) {
1240 line_info(m, info);
1241 info = info->next_device;
1242 }
1243 return 0;
1244}
1245
1246/*
1247 * return count of bytes in transmit buffer
1248 */
1249static unsigned int chars_in_buffer(struct tty_struct *tty)
1250{
1251 struct slgt_info *info = tty->driver_data;
1252 unsigned int count;
1253 if (sanity_check(info, tty->name, "chars_in_buffer"))
1254 return 0;
1255 count = tbuf_bytes(info);
1256 DBGINFO(("%s chars_in_buffer()=%u\n", info->device_name, count));
1257 return count;
1258}
1259
1260/*
1261 * signal remote device to throttle send data (our receive data)
1262 */
1263static void throttle(struct tty_struct * tty)
1264{
1265 struct slgt_info *info = tty->driver_data;
1266 unsigned long flags;
1267
1268 if (sanity_check(info, tty->name, "throttle"))
1269 return;
1270 DBGINFO(("%s throttle\n", info->device_name));
1271 if (I_IXOFF(tty))
1272 send_xchar(tty, STOP_CHAR(tty));
1273 if (C_CRTSCTS(tty)) {
1274 spin_lock_irqsave(&info->lock,flags);
1275 info->signals &= ~SerialSignal_RTS;
1276 set_gtsignals(info);
1277 spin_unlock_irqrestore(&info->lock,flags);
1278 }
1279}
1280
1281/*
1282 * signal remote device to stop throttling send data (our receive data)
1283 */
1284static void unthrottle(struct tty_struct * tty)
1285{
1286 struct slgt_info *info = tty->driver_data;
1287 unsigned long flags;
1288
1289 if (sanity_check(info, tty->name, "unthrottle"))
1290 return;
1291 DBGINFO(("%s unthrottle\n", info->device_name));
1292 if (I_IXOFF(tty)) {
1293 if (info->x_char)
1294 info->x_char = 0;
1295 else
1296 send_xchar(tty, START_CHAR(tty));
1297 }
1298 if (C_CRTSCTS(tty)) {
1299 spin_lock_irqsave(&info->lock,flags);
1300 info->signals |= SerialSignal_RTS;
1301 set_gtsignals(info);
1302 spin_unlock_irqrestore(&info->lock,flags);
1303 }
1304}
1305
1306/*
1307 * set or clear transmit break condition
1308 * break_state -1=set break condition, 0=clear
1309 */
1310static int set_break(struct tty_struct *tty, int break_state)
1311{
1312 struct slgt_info *info = tty->driver_data;
1313 unsigned short value;
1314 unsigned long flags;
1315
1316 if (sanity_check(info, tty->name, "set_break"))
1317 return -EINVAL;
1318 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1319
1320 spin_lock_irqsave(&info->lock,flags);
1321 value = rd_reg16(info, TCR);
1322 if (break_state == -1)
1323 value |= BIT6;
1324 else
1325 value &= ~BIT6;
1326 wr_reg16(info, TCR, value);
1327 spin_unlock_irqrestore(&info->lock,flags);
1328 return 0;
1329}
1330
1331#if SYNCLINK_GENERIC_HDLC
1332
1333/**
1334 * hdlcdev_attach - called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1335 * @dev: pointer to network device structure
1336 * @encoding: serial encoding setting
1337 * @parity: FCS setting
1338 *
1339 * Set encoding and frame check sequence (FCS) options.
1340 *
1341 * Return: 0 if success, otherwise error code
1342 */
1343static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1344 unsigned short parity)
1345{
1346 struct slgt_info *info = dev_to_port(dev);
1347 unsigned char new_encoding;
1348 unsigned short new_crctype;
1349
1350 /* return error if TTY interface open */
1351 if (info->port.count)
1352 return -EBUSY;
1353
1354 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1355
1356 switch (encoding)
1357 {
1358 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1359 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1360 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1361 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1362 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1363 default: return -EINVAL;
1364 }
1365
1366 switch (parity)
1367 {
1368 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1369 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1370 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1371 default: return -EINVAL;
1372 }
1373
1374 info->params.encoding = new_encoding;
1375 info->params.crc_type = new_crctype;
1376
1377 /* if network interface up, reprogram hardware */
1378 if (info->netcount)
1379 program_hw(info);
1380
1381 return 0;
1382}
1383
1384/**
1385 * hdlcdev_xmit - called by generic HDLC layer to send a frame
1386 * @skb: socket buffer containing HDLC frame
1387 * @dev: pointer to network device structure
1388 */
1389static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1390 struct net_device *dev)
1391{
1392 struct slgt_info *info = dev_to_port(dev);
1393 unsigned long flags;
1394
1395 DBGINFO(("%s hdlc_xmit\n", dev->name));
1396
1397 if (!skb->len)
1398 return NETDEV_TX_OK;
1399
1400 /* stop sending until this frame completes */
1401 netif_stop_queue(dev);
1402
1403 /* update network statistics */
1404 dev->stats.tx_packets++;
1405 dev->stats.tx_bytes += skb->len;
1406
1407 /* save start time for transmit timeout detection */
1408 netif_trans_update(dev);
1409
1410 spin_lock_irqsave(&info->lock, flags);
1411 tx_load(info, skb->data, skb->len);
1412 spin_unlock_irqrestore(&info->lock, flags);
1413
1414 /* done with socket buffer, so free it */
1415 dev_kfree_skb(skb);
1416
1417 return NETDEV_TX_OK;
1418}
1419
1420/**
1421 * hdlcdev_open - called by network layer when interface enabled
1422 * @dev: pointer to network device structure
1423 *
1424 * Claim resources and initialize hardware.
1425 *
1426 * Return: 0 if success, otherwise error code
1427 */
1428static int hdlcdev_open(struct net_device *dev)
1429{
1430 struct slgt_info *info = dev_to_port(dev);
1431 int rc;
1432 unsigned long flags;
1433
1434 DBGINFO(("%s hdlcdev_open\n", dev->name));
1435
1436 /* arbitrate between network and tty opens */
1437 spin_lock_irqsave(&info->netlock, flags);
1438 if (info->port.count != 0 || info->netcount != 0) {
1439 DBGINFO(("%s hdlc_open busy\n", dev->name));
1440 spin_unlock_irqrestore(&info->netlock, flags);
1441 return -EBUSY;
1442 }
1443 info->netcount=1;
1444 spin_unlock_irqrestore(&info->netlock, flags);
1445
1446 /* claim resources and init adapter */
1447 if ((rc = startup(info)) != 0) {
1448 spin_lock_irqsave(&info->netlock, flags);
1449 info->netcount=0;
1450 spin_unlock_irqrestore(&info->netlock, flags);
1451 return rc;
1452 }
1453
1454 /* generic HDLC layer open processing */
1455 rc = hdlc_open(dev);
1456 if (rc) {
1457 shutdown(info);
1458 spin_lock_irqsave(&info->netlock, flags);
1459 info->netcount = 0;
1460 spin_unlock_irqrestore(&info->netlock, flags);
1461 return rc;
1462 }
1463
1464 /* assert RTS and DTR, apply hardware settings */
1465 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
1466 program_hw(info);
1467
1468 /* enable network layer transmit */
1469 netif_trans_update(dev);
1470 netif_start_queue(dev);
1471
1472 /* inform generic HDLC layer of current DCD status */
1473 spin_lock_irqsave(&info->lock, flags);
1474 get_gtsignals(info);
1475 spin_unlock_irqrestore(&info->lock, flags);
1476 if (info->signals & SerialSignal_DCD)
1477 netif_carrier_on(dev);
1478 else
1479 netif_carrier_off(dev);
1480 return 0;
1481}
1482
1483/**
1484 * hdlcdev_close - called by network layer when interface is disabled
1485 * @dev: pointer to network device structure
1486 *
1487 * Shutdown hardware and release resources.
1488 *
1489 * Return: 0 if success, otherwise error code
1490 */
1491static int hdlcdev_close(struct net_device *dev)
1492{
1493 struct slgt_info *info = dev_to_port(dev);
1494 unsigned long flags;
1495
1496 DBGINFO(("%s hdlcdev_close\n", dev->name));
1497
1498 netif_stop_queue(dev);
1499
1500 /* shutdown adapter and release resources */
1501 shutdown(info);
1502
1503 hdlc_close(dev);
1504
1505 spin_lock_irqsave(&info->netlock, flags);
1506 info->netcount=0;
1507 spin_unlock_irqrestore(&info->netlock, flags);
1508
1509 return 0;
1510}
1511
1512/**
1513 * hdlcdev_ioctl - called by network layer to process IOCTL call to network device
1514 * @dev: pointer to network device structure
1515 * @ifr: pointer to network interface request structure
1516 * @cmd: IOCTL command code
1517 *
1518 * Return: 0 if success, otherwise error code
1519 */
1520static int hdlcdev_ioctl(struct net_device *dev, struct if_settings *ifs)
1521{
1522 const size_t size = sizeof(sync_serial_settings);
1523 sync_serial_settings new_line;
1524 sync_serial_settings __user *line = ifs->ifs_ifsu.sync;
1525 struct slgt_info *info = dev_to_port(dev);
1526 unsigned int flags;
1527
1528 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1529
1530 /* return error if TTY interface open */
1531 if (info->port.count)
1532 return -EBUSY;
1533
1534 memset(&new_line, 0, sizeof(new_line));
1535
1536 switch (ifs->type) {
1537 case IF_GET_IFACE: /* return current sync_serial_settings */
1538
1539 ifs->type = IF_IFACE_SYNC_SERIAL;
1540 if (ifs->size < size) {
1541 ifs->size = size; /* data size wanted */
1542 return -ENOBUFS;
1543 }
1544
1545 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1546 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1547 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1548 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1549
1550 switch (flags){
1551 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1552 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1553 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1554 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1555 default: new_line.clock_type = CLOCK_DEFAULT;
1556 }
1557
1558 new_line.clock_rate = info->params.clock_speed;
1559 new_line.loopback = info->params.loopback ? 1:0;
1560
1561 if (copy_to_user(line, &new_line, size))
1562 return -EFAULT;
1563 return 0;
1564
1565 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1566
1567 if(!capable(CAP_NET_ADMIN))
1568 return -EPERM;
1569 if (copy_from_user(&new_line, line, size))
1570 return -EFAULT;
1571
1572 switch (new_line.clock_type)
1573 {
1574 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1575 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1576 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1577 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1578 case CLOCK_DEFAULT: flags = info->params.flags &
1579 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1580 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1581 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1582 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1583 default: return -EINVAL;
1584 }
1585
1586 if (new_line.loopback != 0 && new_line.loopback != 1)
1587 return -EINVAL;
1588
1589 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1590 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1591 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1592 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1593 info->params.flags |= flags;
1594
1595 info->params.loopback = new_line.loopback;
1596
1597 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1598 info->params.clock_speed = new_line.clock_rate;
1599 else
1600 info->params.clock_speed = 0;
1601
1602 /* if network interface up, reprogram hardware */
1603 if (info->netcount)
1604 program_hw(info);
1605 return 0;
1606
1607 default:
1608 return hdlc_ioctl(dev, ifs);
1609 }
1610}
1611
1612/**
1613 * hdlcdev_tx_timeout - called by network layer when transmit timeout is detected
1614 * @dev: pointer to network device structure
1615 * @txqueue: unused
1616 */
1617static void hdlcdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
1618{
1619 struct slgt_info *info = dev_to_port(dev);
1620 unsigned long flags;
1621
1622 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1623
1624 dev->stats.tx_errors++;
1625 dev->stats.tx_aborted_errors++;
1626
1627 spin_lock_irqsave(&info->lock,flags);
1628 tx_stop(info);
1629 spin_unlock_irqrestore(&info->lock,flags);
1630
1631 netif_wake_queue(dev);
1632}
1633
1634/**
1635 * hdlcdev_tx_done - called by device driver when transmit completes
1636 * @info: pointer to device instance information
1637 *
1638 * Reenable network layer transmit if stopped.
1639 */
1640static void hdlcdev_tx_done(struct slgt_info *info)
1641{
1642 if (netif_queue_stopped(info->netdev))
1643 netif_wake_queue(info->netdev);
1644}
1645
1646/**
1647 * hdlcdev_rx - called by device driver when frame received
1648 * @info: pointer to device instance information
1649 * @buf: pointer to buffer contianing frame data
1650 * @size: count of data bytes in buf
1651 *
1652 * Pass frame to network layer.
1653 */
1654static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1655{
1656 struct sk_buff *skb = dev_alloc_skb(size);
1657 struct net_device *dev = info->netdev;
1658
1659 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1660
1661 if (skb == NULL) {
1662 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1663 dev->stats.rx_dropped++;
1664 return;
1665 }
1666
1667 skb_put_data(skb, buf, size);
1668
1669 skb->protocol = hdlc_type_trans(skb, dev);
1670
1671 dev->stats.rx_packets++;
1672 dev->stats.rx_bytes += size;
1673
1674 netif_rx(skb);
1675}
1676
1677static const struct net_device_ops hdlcdev_ops = {
1678 .ndo_open = hdlcdev_open,
1679 .ndo_stop = hdlcdev_close,
1680 .ndo_start_xmit = hdlc_start_xmit,
1681 .ndo_siocwandev = hdlcdev_ioctl,
1682 .ndo_tx_timeout = hdlcdev_tx_timeout,
1683};
1684
1685/**
1686 * hdlcdev_init - called by device driver when adding device instance
1687 * @info: pointer to device instance information
1688 *
1689 * Do generic HDLC initialization.
1690 *
1691 * Return: 0 if success, otherwise error code
1692 */
1693static int hdlcdev_init(struct slgt_info *info)
1694{
1695 int rc;
1696 struct net_device *dev;
1697 hdlc_device *hdlc;
1698
1699 /* allocate and initialize network and HDLC layer objects */
1700
1701 dev = alloc_hdlcdev(info);
1702 if (!dev) {
1703 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1704 return -ENOMEM;
1705 }
1706
1707 /* for network layer reporting purposes only */
1708 dev->mem_start = info->phys_reg_addr;
1709 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1710 dev->irq = info->irq_level;
1711
1712 /* network layer callbacks and settings */
1713 dev->netdev_ops = &hdlcdev_ops;
1714 dev->watchdog_timeo = 10 * HZ;
1715 dev->tx_queue_len = 50;
1716
1717 /* generic HDLC layer callbacks and settings */
1718 hdlc = dev_to_hdlc(dev);
1719 hdlc->attach = hdlcdev_attach;
1720 hdlc->xmit = hdlcdev_xmit;
1721
1722 /* register objects with HDLC layer */
1723 rc = register_hdlc_device(dev);
1724 if (rc) {
1725 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1726 free_netdev(dev);
1727 return rc;
1728 }
1729
1730 info->netdev = dev;
1731 return 0;
1732}
1733
1734/**
1735 * hdlcdev_exit - called by device driver when removing device instance
1736 * @info: pointer to device instance information
1737 *
1738 * Do generic HDLC cleanup.
1739 */
1740static void hdlcdev_exit(struct slgt_info *info)
1741{
1742 if (!info->netdev)
1743 return;
1744 unregister_hdlc_device(info->netdev);
1745 free_netdev(info->netdev);
1746 info->netdev = NULL;
1747}
1748
1749#endif /* ifdef CONFIG_HDLC */
1750
1751/*
1752 * get async data from rx DMA buffers
1753 */
1754static void rx_async(struct slgt_info *info)
1755{
1756 struct mgsl_icount *icount = &info->icount;
1757 unsigned int start, end;
1758 unsigned char *p;
1759 unsigned char status;
1760 struct slgt_desc *bufs = info->rbufs;
1761 int i, count;
1762 int chars = 0;
1763 int stat;
1764 unsigned char ch;
1765
1766 start = end = info->rbuf_current;
1767
1768 while(desc_complete(bufs[end])) {
1769 count = desc_count(bufs[end]) - info->rbuf_index;
1770 p = bufs[end].buf + info->rbuf_index;
1771
1772 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1773 DBGDATA(info, p, count, "rx");
1774
1775 for(i=0 ; i < count; i+=2, p+=2) {
1776 ch = *p;
1777 icount->rx++;
1778
1779 stat = 0;
1780
1781 status = *(p + 1) & (BIT1 + BIT0);
1782 if (status) {
1783 if (status & BIT1)
1784 icount->parity++;
1785 else if (status & BIT0)
1786 icount->frame++;
1787 /* discard char if tty control flags say so */
1788 if (status & info->ignore_status_mask)
1789 continue;
1790 if (status & BIT1)
1791 stat = TTY_PARITY;
1792 else if (status & BIT0)
1793 stat = TTY_FRAME;
1794 }
1795 tty_insert_flip_char(&info->port, ch, stat);
1796 chars++;
1797 }
1798
1799 if (i < count) {
1800 /* receive buffer not completed */
1801 info->rbuf_index += i;
1802 mod_timer(&info->rx_timer, jiffies + 1);
1803 break;
1804 }
1805
1806 info->rbuf_index = 0;
1807 free_rbufs(info, end, end);
1808
1809 if (++end == info->rbuf_count)
1810 end = 0;
1811
1812 /* if entire list searched then no frame available */
1813 if (end == start)
1814 break;
1815 }
1816
1817 if (chars)
1818 tty_flip_buffer_push(&info->port);
1819}
1820
1821/*
1822 * return next bottom half action to perform
1823 */
1824static int bh_action(struct slgt_info *info)
1825{
1826 unsigned long flags;
1827 int rc;
1828
1829 spin_lock_irqsave(&info->lock,flags);
1830
1831 if (info->pending_bh & BH_RECEIVE) {
1832 info->pending_bh &= ~BH_RECEIVE;
1833 rc = BH_RECEIVE;
1834 } else if (info->pending_bh & BH_TRANSMIT) {
1835 info->pending_bh &= ~BH_TRANSMIT;
1836 rc = BH_TRANSMIT;
1837 } else if (info->pending_bh & BH_STATUS) {
1838 info->pending_bh &= ~BH_STATUS;
1839 rc = BH_STATUS;
1840 } else {
1841 /* Mark BH routine as complete */
1842 info->bh_running = false;
1843 info->bh_requested = false;
1844 rc = 0;
1845 }
1846
1847 spin_unlock_irqrestore(&info->lock,flags);
1848
1849 return rc;
1850}
1851
1852/*
1853 * perform bottom half processing
1854 */
1855static void bh_handler(struct work_struct *work)
1856{
1857 struct slgt_info *info = container_of(work, struct slgt_info, task);
1858 int action;
1859
1860 info->bh_running = true;
1861
1862 while((action = bh_action(info))) {
1863 switch (action) {
1864 case BH_RECEIVE:
1865 DBGBH(("%s bh receive\n", info->device_name));
1866 switch(info->params.mode) {
1867 case MGSL_MODE_ASYNC:
1868 rx_async(info);
1869 break;
1870 case MGSL_MODE_HDLC:
1871 while(rx_get_frame(info));
1872 break;
1873 case MGSL_MODE_RAW:
1874 case MGSL_MODE_MONOSYNC:
1875 case MGSL_MODE_BISYNC:
1876 case MGSL_MODE_XSYNC:
1877 while(rx_get_buf(info));
1878 break;
1879 }
1880 /* restart receiver if rx DMA buffers exhausted */
1881 if (info->rx_restart)
1882 rx_start(info);
1883 break;
1884 case BH_TRANSMIT:
1885 bh_transmit(info);
1886 break;
1887 case BH_STATUS:
1888 DBGBH(("%s bh status\n", info->device_name));
1889 info->ri_chkcount = 0;
1890 info->dsr_chkcount = 0;
1891 info->dcd_chkcount = 0;
1892 info->cts_chkcount = 0;
1893 break;
1894 default:
1895 DBGBH(("%s unknown action\n", info->device_name));
1896 break;
1897 }
1898 }
1899 DBGBH(("%s bh_handler exit\n", info->device_name));
1900}
1901
1902static void bh_transmit(struct slgt_info *info)
1903{
1904 struct tty_struct *tty = info->port.tty;
1905
1906 DBGBH(("%s bh_transmit\n", info->device_name));
1907 if (tty)
1908 tty_wakeup(tty);
1909}
1910
1911static void dsr_change(struct slgt_info *info, unsigned short status)
1912{
1913 if (status & BIT3) {
1914 info->signals |= SerialSignal_DSR;
1915 info->input_signal_events.dsr_up++;
1916 } else {
1917 info->signals &= ~SerialSignal_DSR;
1918 info->input_signal_events.dsr_down++;
1919 }
1920 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
1921 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1922 slgt_irq_off(info, IRQ_DSR);
1923 return;
1924 }
1925 info->icount.dsr++;
1926 wake_up_interruptible(&info->status_event_wait_q);
1927 wake_up_interruptible(&info->event_wait_q);
1928 info->pending_bh |= BH_STATUS;
1929}
1930
1931static void cts_change(struct slgt_info *info, unsigned short status)
1932{
1933 if (status & BIT2) {
1934 info->signals |= SerialSignal_CTS;
1935 info->input_signal_events.cts_up++;
1936 } else {
1937 info->signals &= ~SerialSignal_CTS;
1938 info->input_signal_events.cts_down++;
1939 }
1940 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
1941 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1942 slgt_irq_off(info, IRQ_CTS);
1943 return;
1944 }
1945 info->icount.cts++;
1946 wake_up_interruptible(&info->status_event_wait_q);
1947 wake_up_interruptible(&info->event_wait_q);
1948 info->pending_bh |= BH_STATUS;
1949
1950 if (tty_port_cts_enabled(&info->port)) {
1951 if (info->port.tty) {
1952 if (info->port.tty->hw_stopped) {
1953 if (info->signals & SerialSignal_CTS) {
1954 info->port.tty->hw_stopped = false;
1955 info->pending_bh |= BH_TRANSMIT;
1956 return;
1957 }
1958 } else {
1959 if (!(info->signals & SerialSignal_CTS))
1960 info->port.tty->hw_stopped = true;
1961 }
1962 }
1963 }
1964}
1965
1966static void dcd_change(struct slgt_info *info, unsigned short status)
1967{
1968 if (status & BIT1) {
1969 info->signals |= SerialSignal_DCD;
1970 info->input_signal_events.dcd_up++;
1971 } else {
1972 info->signals &= ~SerialSignal_DCD;
1973 info->input_signal_events.dcd_down++;
1974 }
1975 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
1976 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
1977 slgt_irq_off(info, IRQ_DCD);
1978 return;
1979 }
1980 info->icount.dcd++;
1981#if SYNCLINK_GENERIC_HDLC
1982 if (info->netcount) {
1983 if (info->signals & SerialSignal_DCD)
1984 netif_carrier_on(info->netdev);
1985 else
1986 netif_carrier_off(info->netdev);
1987 }
1988#endif
1989 wake_up_interruptible(&info->status_event_wait_q);
1990 wake_up_interruptible(&info->event_wait_q);
1991 info->pending_bh |= BH_STATUS;
1992
1993 if (tty_port_check_carrier(&info->port)) {
1994 if (info->signals & SerialSignal_DCD)
1995 wake_up_interruptible(&info->port.open_wait);
1996 else {
1997 if (info->port.tty)
1998 tty_hangup(info->port.tty);
1999 }
2000 }
2001}
2002
2003static void ri_change(struct slgt_info *info, unsigned short status)
2004{
2005 if (status & BIT0) {
2006 info->signals |= SerialSignal_RI;
2007 info->input_signal_events.ri_up++;
2008 } else {
2009 info->signals &= ~SerialSignal_RI;
2010 info->input_signal_events.ri_down++;
2011 }
2012 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2013 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2014 slgt_irq_off(info, IRQ_RI);
2015 return;
2016 }
2017 info->icount.rng++;
2018 wake_up_interruptible(&info->status_event_wait_q);
2019 wake_up_interruptible(&info->event_wait_q);
2020 info->pending_bh |= BH_STATUS;
2021}
2022
2023static void isr_rxdata(struct slgt_info *info)
2024{
2025 unsigned int count = info->rbuf_fill_count;
2026 unsigned int i = info->rbuf_fill_index;
2027 unsigned short reg;
2028
2029 while (rd_reg16(info, SSR) & IRQ_RXDATA) {
2030 reg = rd_reg16(info, RDR);
2031 DBGISR(("isr_rxdata %s RDR=%04X\n", info->device_name, reg));
2032 if (desc_complete(info->rbufs[i])) {
2033 /* all buffers full */
2034 rx_stop(info);
2035 info->rx_restart = true;
2036 continue;
2037 }
2038 info->rbufs[i].buf[count++] = (unsigned char)reg;
2039 /* async mode saves status byte to buffer for each data byte */
2040 if (info->params.mode == MGSL_MODE_ASYNC)
2041 info->rbufs[i].buf[count++] = (unsigned char)(reg >> 8);
2042 if (count == info->rbuf_fill_level || (reg & BIT10)) {
2043 /* buffer full or end of frame */
2044 set_desc_count(info->rbufs[i], count);
2045 set_desc_status(info->rbufs[i], BIT15 | (reg >> 8));
2046 info->rbuf_fill_count = count = 0;
2047 if (++i == info->rbuf_count)
2048 i = 0;
2049 info->pending_bh |= BH_RECEIVE;
2050 }
2051 }
2052
2053 info->rbuf_fill_index = i;
2054 info->rbuf_fill_count = count;
2055}
2056
2057static void isr_serial(struct slgt_info *info)
2058{
2059 unsigned short status = rd_reg16(info, SSR);
2060
2061 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2062
2063 wr_reg16(info, SSR, status); /* clear pending */
2064
2065 info->irq_occurred = true;
2066
2067 if (info->params.mode == MGSL_MODE_ASYNC) {
2068 if (status & IRQ_TXIDLE) {
2069 if (info->tx_active)
2070 isr_txeom(info, status);
2071 }
2072 if (info->rx_pio && (status & IRQ_RXDATA))
2073 isr_rxdata(info);
2074 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2075 info->icount.brk++;
2076 /* process break detection if tty control allows */
2077 if (info->port.tty) {
2078 if (!(status & info->ignore_status_mask)) {
2079 if (info->read_status_mask & MASK_BREAK) {
2080 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2081 if (info->port.flags & ASYNC_SAK)
2082 do_SAK(info->port.tty);
2083 }
2084 }
2085 }
2086 }
2087 } else {
2088 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2089 isr_txeom(info, status);
2090 if (info->rx_pio && (status & IRQ_RXDATA))
2091 isr_rxdata(info);
2092 if (status & IRQ_RXIDLE) {
2093 if (status & RXIDLE)
2094 info->icount.rxidle++;
2095 else
2096 info->icount.exithunt++;
2097 wake_up_interruptible(&info->event_wait_q);
2098 }
2099
2100 if (status & IRQ_RXOVER)
2101 rx_start(info);
2102 }
2103
2104 if (status & IRQ_DSR)
2105 dsr_change(info, status);
2106 if (status & IRQ_CTS)
2107 cts_change(info, status);
2108 if (status & IRQ_DCD)
2109 dcd_change(info, status);
2110 if (status & IRQ_RI)
2111 ri_change(info, status);
2112}
2113
2114static void isr_rdma(struct slgt_info *info)
2115{
2116 unsigned int status = rd_reg32(info, RDCSR);
2117
2118 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2119
2120 /* RDCSR (rx DMA control/status)
2121 *
2122 * 31..07 reserved
2123 * 06 save status byte to DMA buffer
2124 * 05 error
2125 * 04 eol (end of list)
2126 * 03 eob (end of buffer)
2127 * 02 IRQ enable
2128 * 01 reset
2129 * 00 enable
2130 */
2131 wr_reg32(info, RDCSR, status); /* clear pending */
2132
2133 if (status & (BIT5 + BIT4)) {
2134 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2135 info->rx_restart = true;
2136 }
2137 info->pending_bh |= BH_RECEIVE;
2138}
2139
2140static void isr_tdma(struct slgt_info *info)
2141{
2142 unsigned int status = rd_reg32(info, TDCSR);
2143
2144 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2145
2146 /* TDCSR (tx DMA control/status)
2147 *
2148 * 31..06 reserved
2149 * 05 error
2150 * 04 eol (end of list)
2151 * 03 eob (end of buffer)
2152 * 02 IRQ enable
2153 * 01 reset
2154 * 00 enable
2155 */
2156 wr_reg32(info, TDCSR, status); /* clear pending */
2157
2158 if (status & (BIT5 + BIT4 + BIT3)) {
2159 // another transmit buffer has completed
2160 // run bottom half to get more send data from user
2161 info->pending_bh |= BH_TRANSMIT;
2162 }
2163}
2164
2165/*
2166 * return true if there are unsent tx DMA buffers, otherwise false
2167 *
2168 * if there are unsent buffers then info->tbuf_start
2169 * is set to index of first unsent buffer
2170 */
2171static bool unsent_tbufs(struct slgt_info *info)
2172{
2173 unsigned int i = info->tbuf_current;
2174 bool rc = false;
2175
2176 /*
2177 * search backwards from last loaded buffer (precedes tbuf_current)
2178 * for first unsent buffer (desc_count > 0)
2179 */
2180
2181 do {
2182 if (i)
2183 i--;
2184 else
2185 i = info->tbuf_count - 1;
2186 if (!desc_count(info->tbufs[i]))
2187 break;
2188 info->tbuf_start = i;
2189 rc = true;
2190 } while (i != info->tbuf_current);
2191
2192 return rc;
2193}
2194
2195static void isr_txeom(struct slgt_info *info, unsigned short status)
2196{
2197 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2198
2199 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2200 tdma_reset(info);
2201 if (status & IRQ_TXUNDER) {
2202 unsigned short val = rd_reg16(info, TCR);
2203 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2204 wr_reg16(info, TCR, val); /* clear reset bit */
2205 }
2206
2207 if (info->tx_active) {
2208 if (info->params.mode != MGSL_MODE_ASYNC) {
2209 if (status & IRQ_TXUNDER)
2210 info->icount.txunder++;
2211 else if (status & IRQ_TXIDLE)
2212 info->icount.txok++;
2213 }
2214
2215 if (unsent_tbufs(info)) {
2216 tx_start(info);
2217 update_tx_timer(info);
2218 return;
2219 }
2220 info->tx_active = false;
2221
2222 del_timer(&info->tx_timer);
2223
2224 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2225 info->signals &= ~SerialSignal_RTS;
2226 info->drop_rts_on_tx_done = false;
2227 set_gtsignals(info);
2228 }
2229
2230#if SYNCLINK_GENERIC_HDLC
2231 if (info->netcount)
2232 hdlcdev_tx_done(info);
2233 else
2234#endif
2235 {
2236 if (info->port.tty && (info->port.tty->flow.stopped || info->port.tty->hw_stopped)) {
2237 tx_stop(info);
2238 return;
2239 }
2240 info->pending_bh |= BH_TRANSMIT;
2241 }
2242 }
2243}
2244
2245static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2246{
2247 struct cond_wait *w, *prev;
2248
2249 /* wake processes waiting for specific transitions */
2250 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2251 if (w->data & changed) {
2252 w->data = state;
2253 wake_up_interruptible(&w->q);
2254 if (prev != NULL)
2255 prev->next = w->next;
2256 else
2257 info->gpio_wait_q = w->next;
2258 } else
2259 prev = w;
2260 }
2261}
2262
2263/* interrupt service routine
2264 *
2265 * irq interrupt number
2266 * dev_id device ID supplied during interrupt registration
2267 */
2268static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2269{
2270 struct slgt_info *info = dev_id;
2271 unsigned int gsr;
2272 unsigned int i;
2273
2274 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2275
2276 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2277 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2278 info->irq_occurred = true;
2279 for(i=0; i < info->port_count ; i++) {
2280 if (info->port_array[i] == NULL)
2281 continue;
2282 spin_lock(&info->port_array[i]->lock);
2283 if (gsr & (BIT8 << i))
2284 isr_serial(info->port_array[i]);
2285 if (gsr & (BIT16 << (i*2)))
2286 isr_rdma(info->port_array[i]);
2287 if (gsr & (BIT17 << (i*2)))
2288 isr_tdma(info->port_array[i]);
2289 spin_unlock(&info->port_array[i]->lock);
2290 }
2291 }
2292
2293 if (info->gpio_present) {
2294 unsigned int state;
2295 unsigned int changed;
2296 spin_lock(&info->lock);
2297 while ((changed = rd_reg32(info, IOSR)) != 0) {
2298 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2299 /* read latched state of GPIO signals */
2300 state = rd_reg32(info, IOVR);
2301 /* clear pending GPIO interrupt bits */
2302 wr_reg32(info, IOSR, changed);
2303 for (i=0 ; i < info->port_count ; i++) {
2304 if (info->port_array[i] != NULL)
2305 isr_gpio(info->port_array[i], changed, state);
2306 }
2307 }
2308 spin_unlock(&info->lock);
2309 }
2310
2311 for(i=0; i < info->port_count ; i++) {
2312 struct slgt_info *port = info->port_array[i];
2313 if (port == NULL)
2314 continue;
2315 spin_lock(&port->lock);
2316 if ((port->port.count || port->netcount) &&
2317 port->pending_bh && !port->bh_running &&
2318 !port->bh_requested) {
2319 DBGISR(("%s bh queued\n", port->device_name));
2320 schedule_work(&port->task);
2321 port->bh_requested = true;
2322 }
2323 spin_unlock(&port->lock);
2324 }
2325
2326 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2327 return IRQ_HANDLED;
2328}
2329
2330static int startup(struct slgt_info *info)
2331{
2332 DBGINFO(("%s startup\n", info->device_name));
2333
2334 if (tty_port_initialized(&info->port))
2335 return 0;
2336
2337 if (!info->tx_buf) {
2338 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2339 if (!info->tx_buf) {
2340 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2341 return -ENOMEM;
2342 }
2343 }
2344
2345 info->pending_bh = 0;
2346
2347 memset(&info->icount, 0, sizeof(info->icount));
2348
2349 /* program hardware for current parameters */
2350 change_params(info);
2351
2352 if (info->port.tty)
2353 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2354
2355 tty_port_set_initialized(&info->port, true);
2356
2357 return 0;
2358}
2359
2360/*
2361 * called by close() and hangup() to shutdown hardware
2362 */
2363static void shutdown(struct slgt_info *info)
2364{
2365 unsigned long flags;
2366
2367 if (!tty_port_initialized(&info->port))
2368 return;
2369
2370 DBGINFO(("%s shutdown\n", info->device_name));
2371
2372 /* clear status wait queue because status changes */
2373 /* can't happen after shutting down the hardware */
2374 wake_up_interruptible(&info->status_event_wait_q);
2375 wake_up_interruptible(&info->event_wait_q);
2376
2377 del_timer_sync(&info->tx_timer);
2378 del_timer_sync(&info->rx_timer);
2379
2380 kfree(info->tx_buf);
2381 info->tx_buf = NULL;
2382
2383 spin_lock_irqsave(&info->lock,flags);
2384
2385 tx_stop(info);
2386 rx_stop(info);
2387
2388 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2389
2390 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2391 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2392 set_gtsignals(info);
2393 }
2394
2395 flush_cond_wait(&info->gpio_wait_q);
2396
2397 spin_unlock_irqrestore(&info->lock,flags);
2398
2399 if (info->port.tty)
2400 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2401
2402 tty_port_set_initialized(&info->port, false);
2403}
2404
2405static void program_hw(struct slgt_info *info)
2406{
2407 unsigned long flags;
2408
2409 spin_lock_irqsave(&info->lock,flags);
2410
2411 rx_stop(info);
2412 tx_stop(info);
2413
2414 if (info->params.mode != MGSL_MODE_ASYNC ||
2415 info->netcount)
2416 sync_mode(info);
2417 else
2418 async_mode(info);
2419
2420 set_gtsignals(info);
2421
2422 info->dcd_chkcount = 0;
2423 info->cts_chkcount = 0;
2424 info->ri_chkcount = 0;
2425 info->dsr_chkcount = 0;
2426
2427 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2428 get_gtsignals(info);
2429
2430 if (info->netcount ||
2431 (info->port.tty && info->port.tty->termios.c_cflag & CREAD))
2432 rx_start(info);
2433
2434 spin_unlock_irqrestore(&info->lock,flags);
2435}
2436
2437/*
2438 * reconfigure adapter based on new parameters
2439 */
2440static void change_params(struct slgt_info *info)
2441{
2442 unsigned cflag;
2443 int bits_per_char;
2444
2445 if (!info->port.tty)
2446 return;
2447 DBGINFO(("%s change_params\n", info->device_name));
2448
2449 cflag = info->port.tty->termios.c_cflag;
2450
2451 /* if B0 rate (hangup) specified then negate RTS and DTR */
2452 /* otherwise assert RTS and DTR */
2453 if (cflag & CBAUD)
2454 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
2455 else
2456 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2457
2458 /* byte size and parity */
2459
2460 info->params.data_bits = tty_get_char_size(cflag);
2461 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2462
2463 if (cflag & PARENB)
2464 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2465 else
2466 info->params.parity = ASYNC_PARITY_NONE;
2467
2468 /* calculate number of jiffies to transmit a full
2469 * FIFO (32 bytes) at specified data rate
2470 */
2471 bits_per_char = info->params.data_bits +
2472 info->params.stop_bits + 1;
2473
2474 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2475
2476 if (info->params.data_rate) {
2477 info->timeout = (32*HZ*bits_per_char) /
2478 info->params.data_rate;
2479 }
2480 info->timeout += HZ/50; /* Add .02 seconds of slop */
2481
2482 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2483 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2484
2485 /* process tty input control flags */
2486
2487 info->read_status_mask = IRQ_RXOVER;
2488 if (I_INPCK(info->port.tty))
2489 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2490 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2491 info->read_status_mask |= MASK_BREAK;
2492 if (I_IGNPAR(info->port.tty))
2493 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2494 if (I_IGNBRK(info->port.tty)) {
2495 info->ignore_status_mask |= MASK_BREAK;
2496 /* If ignoring parity and break indicators, ignore
2497 * overruns too. (For real raw support).
2498 */
2499 if (I_IGNPAR(info->port.tty))
2500 info->ignore_status_mask |= MASK_OVERRUN;
2501 }
2502
2503 program_hw(info);
2504}
2505
2506static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2507{
2508 DBGINFO(("%s get_stats\n", info->device_name));
2509 if (!user_icount) {
2510 memset(&info->icount, 0, sizeof(info->icount));
2511 } else {
2512 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2513 return -EFAULT;
2514 }
2515 return 0;
2516}
2517
2518static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2519{
2520 DBGINFO(("%s get_params\n", info->device_name));
2521 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2522 return -EFAULT;
2523 return 0;
2524}
2525
2526static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2527{
2528 unsigned long flags;
2529 MGSL_PARAMS tmp_params;
2530
2531 DBGINFO(("%s set_params\n", info->device_name));
2532 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2533 return -EFAULT;
2534
2535 spin_lock_irqsave(&info->lock, flags);
2536 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2537 info->base_clock = tmp_params.clock_speed;
2538 else
2539 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2540 spin_unlock_irqrestore(&info->lock, flags);
2541
2542 program_hw(info);
2543
2544 return 0;
2545}
2546
2547static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2548{
2549 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2550 if (put_user(info->idle_mode, idle_mode))
2551 return -EFAULT;
2552 return 0;
2553}
2554
2555static int set_txidle(struct slgt_info *info, int idle_mode)
2556{
2557 unsigned long flags;
2558 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2559 spin_lock_irqsave(&info->lock,flags);
2560 info->idle_mode = idle_mode;
2561 if (info->params.mode != MGSL_MODE_ASYNC)
2562 tx_set_idle(info);
2563 spin_unlock_irqrestore(&info->lock,flags);
2564 return 0;
2565}
2566
2567static int tx_enable(struct slgt_info *info, int enable)
2568{
2569 unsigned long flags;
2570 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2571 spin_lock_irqsave(&info->lock,flags);
2572 if (enable) {
2573 if (!info->tx_enabled)
2574 tx_start(info);
2575 } else {
2576 if (info->tx_enabled)
2577 tx_stop(info);
2578 }
2579 spin_unlock_irqrestore(&info->lock,flags);
2580 return 0;
2581}
2582
2583/*
2584 * abort transmit HDLC frame
2585 */
2586static int tx_abort(struct slgt_info *info)
2587{
2588 unsigned long flags;
2589 DBGINFO(("%s tx_abort\n", info->device_name));
2590 spin_lock_irqsave(&info->lock,flags);
2591 tdma_reset(info);
2592 spin_unlock_irqrestore(&info->lock,flags);
2593 return 0;
2594}
2595
2596static int rx_enable(struct slgt_info *info, int enable)
2597{
2598 unsigned long flags;
2599 unsigned int rbuf_fill_level;
2600 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2601 spin_lock_irqsave(&info->lock,flags);
2602 /*
2603 * enable[31..16] = receive DMA buffer fill level
2604 * 0 = noop (leave fill level unchanged)
2605 * fill level must be multiple of 4 and <= buffer size
2606 */
2607 rbuf_fill_level = ((unsigned int)enable) >> 16;
2608 if (rbuf_fill_level) {
2609 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2610 spin_unlock_irqrestore(&info->lock, flags);
2611 return -EINVAL;
2612 }
2613 info->rbuf_fill_level = rbuf_fill_level;
2614 if (rbuf_fill_level < 128)
2615 info->rx_pio = 1; /* PIO mode */
2616 else
2617 info->rx_pio = 0; /* DMA mode */
2618 rx_stop(info); /* restart receiver to use new fill level */
2619 }
2620
2621 /*
2622 * enable[1..0] = receiver enable command
2623 * 0 = disable
2624 * 1 = enable
2625 * 2 = enable or force hunt mode if already enabled
2626 */
2627 enable &= 3;
2628 if (enable) {
2629 if (!info->rx_enabled)
2630 rx_start(info);
2631 else if (enable == 2) {
2632 /* force hunt mode (write 1 to RCR[3]) */
2633 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2634 }
2635 } else {
2636 if (info->rx_enabled)
2637 rx_stop(info);
2638 }
2639 spin_unlock_irqrestore(&info->lock,flags);
2640 return 0;
2641}
2642
2643/*
2644 * wait for specified event to occur
2645 */
2646static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2647{
2648 unsigned long flags;
2649 int s;
2650 int rc=0;
2651 struct mgsl_icount cprev, cnow;
2652 int events;
2653 int mask;
2654 struct _input_signal_events oldsigs, newsigs;
2655 DECLARE_WAITQUEUE(wait, current);
2656
2657 if (get_user(mask, mask_ptr))
2658 return -EFAULT;
2659
2660 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2661
2662 spin_lock_irqsave(&info->lock,flags);
2663
2664 /* return immediately if state matches requested events */
2665 get_gtsignals(info);
2666 s = info->signals;
2667
2668 events = mask &
2669 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2670 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2671 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2672 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2673 if (events) {
2674 spin_unlock_irqrestore(&info->lock,flags);
2675 goto exit;
2676 }
2677
2678 /* save current irq counts */
2679 cprev = info->icount;
2680 oldsigs = info->input_signal_events;
2681
2682 /* enable hunt and idle irqs if needed */
2683 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2684 unsigned short val = rd_reg16(info, SCR);
2685 if (!(val & IRQ_RXIDLE))
2686 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2687 }
2688
2689 set_current_state(TASK_INTERRUPTIBLE);
2690 add_wait_queue(&info->event_wait_q, &wait);
2691
2692 spin_unlock_irqrestore(&info->lock,flags);
2693
2694 for(;;) {
2695 schedule();
2696 if (signal_pending(current)) {
2697 rc = -ERESTARTSYS;
2698 break;
2699 }
2700
2701 /* get current irq counts */
2702 spin_lock_irqsave(&info->lock,flags);
2703 cnow = info->icount;
2704 newsigs = info->input_signal_events;
2705 set_current_state(TASK_INTERRUPTIBLE);
2706 spin_unlock_irqrestore(&info->lock,flags);
2707
2708 /* if no change, wait aborted for some reason */
2709 if (newsigs.dsr_up == oldsigs.dsr_up &&
2710 newsigs.dsr_down == oldsigs.dsr_down &&
2711 newsigs.dcd_up == oldsigs.dcd_up &&
2712 newsigs.dcd_down == oldsigs.dcd_down &&
2713 newsigs.cts_up == oldsigs.cts_up &&
2714 newsigs.cts_down == oldsigs.cts_down &&
2715 newsigs.ri_up == oldsigs.ri_up &&
2716 newsigs.ri_down == oldsigs.ri_down &&
2717 cnow.exithunt == cprev.exithunt &&
2718 cnow.rxidle == cprev.rxidle) {
2719 rc = -EIO;
2720 break;
2721 }
2722
2723 events = mask &
2724 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2725 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2726 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2727 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2728 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2729 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2730 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2731 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2732 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2733 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2734 if (events)
2735 break;
2736
2737 cprev = cnow;
2738 oldsigs = newsigs;
2739 }
2740
2741 remove_wait_queue(&info->event_wait_q, &wait);
2742 set_current_state(TASK_RUNNING);
2743
2744
2745 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2746 spin_lock_irqsave(&info->lock,flags);
2747 if (!waitqueue_active(&info->event_wait_q)) {
2748 /* disable enable exit hunt mode/idle rcvd IRQs */
2749 wr_reg16(info, SCR,
2750 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2751 }
2752 spin_unlock_irqrestore(&info->lock,flags);
2753 }
2754exit:
2755 if (rc == 0)
2756 rc = put_user(events, mask_ptr);
2757 return rc;
2758}
2759
2760static int get_interface(struct slgt_info *info, int __user *if_mode)
2761{
2762 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2763 if (put_user(info->if_mode, if_mode))
2764 return -EFAULT;
2765 return 0;
2766}
2767
2768static int set_interface(struct slgt_info *info, int if_mode)
2769{
2770 unsigned long flags;
2771 unsigned short val;
2772
2773 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2774 spin_lock_irqsave(&info->lock,flags);
2775 info->if_mode = if_mode;
2776
2777 msc_set_vcr(info);
2778
2779 /* TCR (tx control) 07 1=RTS driver control */
2780 val = rd_reg16(info, TCR);
2781 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2782 val |= BIT7;
2783 else
2784 val &= ~BIT7;
2785 wr_reg16(info, TCR, val);
2786
2787 spin_unlock_irqrestore(&info->lock,flags);
2788 return 0;
2789}
2790
2791static int get_xsync(struct slgt_info *info, int __user *xsync)
2792{
2793 DBGINFO(("%s get_xsync=%x\n", info->device_name, info->xsync));
2794 if (put_user(info->xsync, xsync))
2795 return -EFAULT;
2796 return 0;
2797}
2798
2799/*
2800 * set extended sync pattern (1 to 4 bytes) for extended sync mode
2801 *
2802 * sync pattern is contained in least significant bytes of value
2803 * most significant byte of sync pattern is oldest (1st sent/detected)
2804 */
2805static int set_xsync(struct slgt_info *info, int xsync)
2806{
2807 unsigned long flags;
2808
2809 DBGINFO(("%s set_xsync=%x)\n", info->device_name, xsync));
2810 spin_lock_irqsave(&info->lock, flags);
2811 info->xsync = xsync;
2812 wr_reg32(info, XSR, xsync);
2813 spin_unlock_irqrestore(&info->lock, flags);
2814 return 0;
2815}
2816
2817static int get_xctrl(struct slgt_info *info, int __user *xctrl)
2818{
2819 DBGINFO(("%s get_xctrl=%x\n", info->device_name, info->xctrl));
2820 if (put_user(info->xctrl, xctrl))
2821 return -EFAULT;
2822 return 0;
2823}
2824
2825/*
2826 * set extended control options
2827 *
2828 * xctrl[31:19] reserved, must be zero
2829 * xctrl[18:17] extended sync pattern length in bytes
2830 * 00 = 1 byte in xsr[7:0]
2831 * 01 = 2 bytes in xsr[15:0]
2832 * 10 = 3 bytes in xsr[23:0]
2833 * 11 = 4 bytes in xsr[31:0]
2834 * xctrl[16] 1 = enable terminal count, 0=disabled
2835 * xctrl[15:0] receive terminal count for fixed length packets
2836 * value is count minus one (0 = 1 byte packet)
2837 * when terminal count is reached, receiver
2838 * automatically returns to hunt mode and receive
2839 * FIFO contents are flushed to DMA buffers with
2840 * end of frame (EOF) status
2841 */
2842static int set_xctrl(struct slgt_info *info, int xctrl)
2843{
2844 unsigned long flags;
2845
2846 DBGINFO(("%s set_xctrl=%x)\n", info->device_name, xctrl));
2847 spin_lock_irqsave(&info->lock, flags);
2848 info->xctrl = xctrl;
2849 wr_reg32(info, XCR, xctrl);
2850 spin_unlock_irqrestore(&info->lock, flags);
2851 return 0;
2852}
2853
2854/*
2855 * set general purpose IO pin state and direction
2856 *
2857 * user_gpio fields:
2858 * state each bit indicates a pin state
2859 * smask set bit indicates pin state to set
2860 * dir each bit indicates a pin direction (0=input, 1=output)
2861 * dmask set bit indicates pin direction to set
2862 */
2863static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2864{
2865 unsigned long flags;
2866 struct gpio_desc gpio;
2867 __u32 data;
2868
2869 if (!info->gpio_present)
2870 return -EINVAL;
2871 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2872 return -EFAULT;
2873 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2874 info->device_name, gpio.state, gpio.smask,
2875 gpio.dir, gpio.dmask));
2876
2877 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2878 if (gpio.dmask) {
2879 data = rd_reg32(info, IODR);
2880 data |= gpio.dmask & gpio.dir;
2881 data &= ~(gpio.dmask & ~gpio.dir);
2882 wr_reg32(info, IODR, data);
2883 }
2884 if (gpio.smask) {
2885 data = rd_reg32(info, IOVR);
2886 data |= gpio.smask & gpio.state;
2887 data &= ~(gpio.smask & ~gpio.state);
2888 wr_reg32(info, IOVR, data);
2889 }
2890 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
2891
2892 return 0;
2893}
2894
2895/*
2896 * get general purpose IO pin state and direction
2897 */
2898static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2899{
2900 struct gpio_desc gpio;
2901 if (!info->gpio_present)
2902 return -EINVAL;
2903 gpio.state = rd_reg32(info, IOVR);
2904 gpio.smask = 0xffffffff;
2905 gpio.dir = rd_reg32(info, IODR);
2906 gpio.dmask = 0xffffffff;
2907 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2908 return -EFAULT;
2909 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2910 info->device_name, gpio.state, gpio.dir));
2911 return 0;
2912}
2913
2914/*
2915 * conditional wait facility
2916 */
2917static void init_cond_wait(struct cond_wait *w, unsigned int data)
2918{
2919 init_waitqueue_head(&w->q);
2920 init_waitqueue_entry(&w->wait, current);
2921 w->data = data;
2922}
2923
2924static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2925{
2926 set_current_state(TASK_INTERRUPTIBLE);
2927 add_wait_queue(&w->q, &w->wait);
2928 w->next = *head;
2929 *head = w;
2930}
2931
2932static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2933{
2934 struct cond_wait *w, *prev;
2935 remove_wait_queue(&cw->q, &cw->wait);
2936 set_current_state(TASK_RUNNING);
2937 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2938 if (w == cw) {
2939 if (prev != NULL)
2940 prev->next = w->next;
2941 else
2942 *head = w->next;
2943 break;
2944 }
2945 }
2946}
2947
2948static void flush_cond_wait(struct cond_wait **head)
2949{
2950 while (*head != NULL) {
2951 wake_up_interruptible(&(*head)->q);
2952 *head = (*head)->next;
2953 }
2954}
2955
2956/*
2957 * wait for general purpose I/O pin(s) to enter specified state
2958 *
2959 * user_gpio fields:
2960 * state - bit indicates target pin state
2961 * smask - set bit indicates watched pin
2962 *
2963 * The wait ends when at least one watched pin enters the specified
2964 * state. When 0 (no error) is returned, user_gpio->state is set to the
2965 * state of all GPIO pins when the wait ends.
2966 *
2967 * Note: Each pin may be a dedicated input, dedicated output, or
2968 * configurable input/output. The number and configuration of pins
2969 * varies with the specific adapter model. Only input pins (dedicated
2970 * or configured) can be monitored with this function.
2971 */
2972static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2973{
2974 unsigned long flags;
2975 int rc = 0;
2976 struct gpio_desc gpio;
2977 struct cond_wait wait;
2978 u32 state;
2979
2980 if (!info->gpio_present)
2981 return -EINVAL;
2982 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2983 return -EFAULT;
2984 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2985 info->device_name, gpio.state, gpio.smask));
2986 /* ignore output pins identified by set IODR bit */
2987 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2988 return -EINVAL;
2989 init_cond_wait(&wait, gpio.smask);
2990
2991 spin_lock_irqsave(&info->port_array[0]->lock, flags);
2992 /* enable interrupts for watched pins */
2993 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2994 /* get current pin states */
2995 state = rd_reg32(info, IOVR);
2996
2997 if (gpio.smask & ~(state ^ gpio.state)) {
2998 /* already in target state */
2999 gpio.state = state;
3000 } else {
3001 /* wait for target state */
3002 add_cond_wait(&info->gpio_wait_q, &wait);
3003 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3004 schedule();
3005 if (signal_pending(current))
3006 rc = -ERESTARTSYS;
3007 else
3008 gpio.state = wait.data;
3009 spin_lock_irqsave(&info->port_array[0]->lock, flags);
3010 remove_cond_wait(&info->gpio_wait_q, &wait);
3011 }
3012
3013 /* disable all GPIO interrupts if no waiting processes */
3014 if (info->gpio_wait_q == NULL)
3015 wr_reg32(info, IOER, 0);
3016 spin_unlock_irqrestore(&info->port_array[0]->lock, flags);
3017
3018 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
3019 rc = -EFAULT;
3020 return rc;
3021}
3022
3023static int modem_input_wait(struct slgt_info *info,int arg)
3024{
3025 unsigned long flags;
3026 int rc;
3027 struct mgsl_icount cprev, cnow;
3028 DECLARE_WAITQUEUE(wait, current);
3029
3030 /* save current irq counts */
3031 spin_lock_irqsave(&info->lock,flags);
3032 cprev = info->icount;
3033 add_wait_queue(&info->status_event_wait_q, &wait);
3034 set_current_state(TASK_INTERRUPTIBLE);
3035 spin_unlock_irqrestore(&info->lock,flags);
3036
3037 for(;;) {
3038 schedule();
3039 if (signal_pending(current)) {
3040 rc = -ERESTARTSYS;
3041 break;
3042 }
3043
3044 /* get new irq counts */
3045 spin_lock_irqsave(&info->lock,flags);
3046 cnow = info->icount;
3047 set_current_state(TASK_INTERRUPTIBLE);
3048 spin_unlock_irqrestore(&info->lock,flags);
3049
3050 /* if no change, wait aborted for some reason */
3051 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3052 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3053 rc = -EIO;
3054 break;
3055 }
3056
3057 /* check for change in caller specified modem input */
3058 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3059 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3060 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3061 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3062 rc = 0;
3063 break;
3064 }
3065
3066 cprev = cnow;
3067 }
3068 remove_wait_queue(&info->status_event_wait_q, &wait);
3069 set_current_state(TASK_RUNNING);
3070 return rc;
3071}
3072
3073/*
3074 * return state of serial control and status signals
3075 */
3076static int tiocmget(struct tty_struct *tty)
3077{
3078 struct slgt_info *info = tty->driver_data;
3079 unsigned int result;
3080 unsigned long flags;
3081
3082 spin_lock_irqsave(&info->lock,flags);
3083 get_gtsignals(info);
3084 spin_unlock_irqrestore(&info->lock,flags);
3085
3086 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3087 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3088 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3089 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3090 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3091 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3092
3093 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3094 return result;
3095}
3096
3097/*
3098 * set modem control signals (DTR/RTS)
3099 *
3100 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3101 * TIOCMSET = set/clear signal values
3102 * value bit mask for command
3103 */
3104static int tiocmset(struct tty_struct *tty,
3105 unsigned int set, unsigned int clear)
3106{
3107 struct slgt_info *info = tty->driver_data;
3108 unsigned long flags;
3109
3110 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3111
3112 if (set & TIOCM_RTS)
3113 info->signals |= SerialSignal_RTS;
3114 if (set & TIOCM_DTR)
3115 info->signals |= SerialSignal_DTR;
3116 if (clear & TIOCM_RTS)
3117 info->signals &= ~SerialSignal_RTS;
3118 if (clear & TIOCM_DTR)
3119 info->signals &= ~SerialSignal_DTR;
3120
3121 spin_lock_irqsave(&info->lock,flags);
3122 set_gtsignals(info);
3123 spin_unlock_irqrestore(&info->lock,flags);
3124 return 0;
3125}
3126
3127static bool carrier_raised(struct tty_port *port)
3128{
3129 unsigned long flags;
3130 struct slgt_info *info = container_of(port, struct slgt_info, port);
3131
3132 spin_lock_irqsave(&info->lock,flags);
3133 get_gtsignals(info);
3134 spin_unlock_irqrestore(&info->lock,flags);
3135
3136 return info->signals & SerialSignal_DCD;
3137}
3138
3139static void dtr_rts(struct tty_port *port, bool active)
3140{
3141 unsigned long flags;
3142 struct slgt_info *info = container_of(port, struct slgt_info, port);
3143
3144 spin_lock_irqsave(&info->lock,flags);
3145 if (active)
3146 info->signals |= SerialSignal_RTS | SerialSignal_DTR;
3147 else
3148 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3149 set_gtsignals(info);
3150 spin_unlock_irqrestore(&info->lock,flags);
3151}
3152
3153
3154/*
3155 * block current process until the device is ready to open
3156 */
3157static int block_til_ready(struct tty_struct *tty, struct file *filp,
3158 struct slgt_info *info)
3159{
3160 DECLARE_WAITQUEUE(wait, current);
3161 int retval;
3162 bool do_clocal = false;
3163 unsigned long flags;
3164 bool cd;
3165 struct tty_port *port = &info->port;
3166
3167 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3168
3169 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3170 /* nonblock mode is set or port is not enabled */
3171 tty_port_set_active(port, true);
3172 return 0;
3173 }
3174
3175 if (C_CLOCAL(tty))
3176 do_clocal = true;
3177
3178 /* Wait for carrier detect and the line to become
3179 * free (i.e., not in use by the callout). While we are in
3180 * this loop, port->count is dropped by one, so that
3181 * close() knows when to free things. We restore it upon
3182 * exit, either normal or abnormal.
3183 */
3184
3185 retval = 0;
3186 add_wait_queue(&port->open_wait, &wait);
3187
3188 spin_lock_irqsave(&info->lock, flags);
3189 port->count--;
3190 spin_unlock_irqrestore(&info->lock, flags);
3191 port->blocked_open++;
3192
3193 while (1) {
3194 if (C_BAUD(tty) && tty_port_initialized(port))
3195 tty_port_raise_dtr_rts(port);
3196
3197 set_current_state(TASK_INTERRUPTIBLE);
3198
3199 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3200 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3201 -EAGAIN : -ERESTARTSYS;
3202 break;
3203 }
3204
3205 cd = tty_port_carrier_raised(port);
3206 if (do_clocal || cd)
3207 break;
3208
3209 if (signal_pending(current)) {
3210 retval = -ERESTARTSYS;
3211 break;
3212 }
3213
3214 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3215 tty_unlock(tty);
3216 schedule();
3217 tty_lock(tty);
3218 }
3219
3220 set_current_state(TASK_RUNNING);
3221 remove_wait_queue(&port->open_wait, &wait);
3222
3223 if (!tty_hung_up_p(filp))
3224 port->count++;
3225 port->blocked_open--;
3226
3227 if (!retval)
3228 tty_port_set_active(port, true);
3229
3230 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3231 return retval;
3232}
3233
3234/*
3235 * allocate buffers used for calling line discipline receive_buf
3236 * directly in synchronous mode
3237 * note: add 5 bytes to max frame size to allow appending
3238 * 32-bit CRC and status byte when configured to do so
3239 */
3240static int alloc_tmp_rbuf(struct slgt_info *info)
3241{
3242 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3243 if (info->tmp_rbuf == NULL)
3244 return -ENOMEM;
3245
3246 return 0;
3247}
3248
3249static void free_tmp_rbuf(struct slgt_info *info)
3250{
3251 kfree(info->tmp_rbuf);
3252 info->tmp_rbuf = NULL;
3253}
3254
3255/*
3256 * allocate DMA descriptor lists.
3257 */
3258static int alloc_desc(struct slgt_info *info)
3259{
3260 unsigned int i;
3261 unsigned int pbufs;
3262
3263 /* allocate memory to hold descriptor lists */
3264 info->bufs = dma_alloc_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3265 &info->bufs_dma_addr, GFP_KERNEL);
3266 if (info->bufs == NULL)
3267 return -ENOMEM;
3268
3269 info->rbufs = (struct slgt_desc*)info->bufs;
3270 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3271
3272 pbufs = (unsigned int)info->bufs_dma_addr;
3273
3274 /*
3275 * Build circular lists of descriptors
3276 */
3277
3278 for (i=0; i < info->rbuf_count; i++) {
3279 /* physical address of this descriptor */
3280 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3281
3282 /* physical address of next descriptor */
3283 if (i == info->rbuf_count - 1)
3284 info->rbufs[i].next = cpu_to_le32(pbufs);
3285 else
3286 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3287 set_desc_count(info->rbufs[i], DMABUFSIZE);
3288 }
3289
3290 for (i=0; i < info->tbuf_count; i++) {
3291 /* physical address of this descriptor */
3292 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3293
3294 /* physical address of next descriptor */
3295 if (i == info->tbuf_count - 1)
3296 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3297 else
3298 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3299 }
3300
3301 return 0;
3302}
3303
3304static void free_desc(struct slgt_info *info)
3305{
3306 if (info->bufs != NULL) {
3307 dma_free_coherent(&info->pdev->dev, DESC_LIST_SIZE,
3308 info->bufs, info->bufs_dma_addr);
3309 info->bufs = NULL;
3310 info->rbufs = NULL;
3311 info->tbufs = NULL;
3312 }
3313}
3314
3315static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3316{
3317 int i;
3318 for (i=0; i < count; i++) {
3319 bufs[i].buf = dma_alloc_coherent(&info->pdev->dev, DMABUFSIZE,
3320 &bufs[i].buf_dma_addr, GFP_KERNEL);
3321 if (!bufs[i].buf)
3322 return -ENOMEM;
3323 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3324 }
3325 return 0;
3326}
3327
3328static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3329{
3330 int i;
3331 for (i=0; i < count; i++) {
3332 if (bufs[i].buf == NULL)
3333 continue;
3334 dma_free_coherent(&info->pdev->dev, DMABUFSIZE, bufs[i].buf,
3335 bufs[i].buf_dma_addr);
3336 bufs[i].buf = NULL;
3337 }
3338}
3339
3340static int alloc_dma_bufs(struct slgt_info *info)
3341{
3342 info->rbuf_count = 32;
3343 info->tbuf_count = 32;
3344
3345 if (alloc_desc(info) < 0 ||
3346 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3347 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3348 alloc_tmp_rbuf(info) < 0) {
3349 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3350 return -ENOMEM;
3351 }
3352 reset_rbufs(info);
3353 return 0;
3354}
3355
3356static void free_dma_bufs(struct slgt_info *info)
3357{
3358 if (info->bufs) {
3359 free_bufs(info, info->rbufs, info->rbuf_count);
3360 free_bufs(info, info->tbufs, info->tbuf_count);
3361 free_desc(info);
3362 }
3363 free_tmp_rbuf(info);
3364}
3365
3366static int claim_resources(struct slgt_info *info)
3367{
3368 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3369 DBGERR(("%s reg addr conflict, addr=%08X\n",
3370 info->device_name, info->phys_reg_addr));
3371 info->init_error = DiagStatus_AddressConflict;
3372 goto errout;
3373 }
3374 else
3375 info->reg_addr_requested = true;
3376
3377 info->reg_addr = ioremap(info->phys_reg_addr, SLGT_REG_SIZE);
3378 if (!info->reg_addr) {
3379 DBGERR(("%s can't map device registers, addr=%08X\n",
3380 info->device_name, info->phys_reg_addr));
3381 info->init_error = DiagStatus_CantAssignPciResources;
3382 goto errout;
3383 }
3384 return 0;
3385
3386errout:
3387 release_resources(info);
3388 return -ENODEV;
3389}
3390
3391static void release_resources(struct slgt_info *info)
3392{
3393 if (info->irq_requested) {
3394 free_irq(info->irq_level, info);
3395 info->irq_requested = false;
3396 }
3397
3398 if (info->reg_addr_requested) {
3399 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3400 info->reg_addr_requested = false;
3401 }
3402
3403 if (info->reg_addr) {
3404 iounmap(info->reg_addr);
3405 info->reg_addr = NULL;
3406 }
3407}
3408
3409/* Add the specified device instance data structure to the
3410 * global linked list of devices and increment the device count.
3411 */
3412static void add_device(struct slgt_info *info)
3413{
3414 char *devstr;
3415
3416 info->next_device = NULL;
3417 info->line = slgt_device_count;
3418 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3419
3420 if (info->line < MAX_DEVICES) {
3421 if (maxframe[info->line])
3422 info->max_frame_size = maxframe[info->line];
3423 }
3424
3425 slgt_device_count++;
3426
3427 if (!slgt_device_list)
3428 slgt_device_list = info;
3429 else {
3430 struct slgt_info *current_dev = slgt_device_list;
3431 while(current_dev->next_device)
3432 current_dev = current_dev->next_device;
3433 current_dev->next_device = info;
3434 }
3435
3436 if (info->max_frame_size < 4096)
3437 info->max_frame_size = 4096;
3438 else if (info->max_frame_size > 65535)
3439 info->max_frame_size = 65535;
3440
3441 switch(info->pdev->device) {
3442 case SYNCLINK_GT_DEVICE_ID:
3443 devstr = "GT";
3444 break;
3445 case SYNCLINK_GT2_DEVICE_ID:
3446 devstr = "GT2";
3447 break;
3448 case SYNCLINK_GT4_DEVICE_ID:
3449 devstr = "GT4";
3450 break;
3451 case SYNCLINK_AC_DEVICE_ID:
3452 devstr = "AC";
3453 info->params.mode = MGSL_MODE_ASYNC;
3454 break;
3455 default:
3456 devstr = "(unknown model)";
3457 }
3458 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3459 devstr, info->device_name, info->phys_reg_addr,
3460 info->irq_level, info->max_frame_size);
3461
3462#if SYNCLINK_GENERIC_HDLC
3463 hdlcdev_init(info);
3464#endif
3465}
3466
3467static const struct tty_port_operations slgt_port_ops = {
3468 .carrier_raised = carrier_raised,
3469 .dtr_rts = dtr_rts,
3470};
3471
3472/*
3473 * allocate device instance structure, return NULL on failure
3474 */
3475static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3476{
3477 struct slgt_info *info;
3478
3479 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3480
3481 if (!info) {
3482 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3483 driver_name, adapter_num, port_num));
3484 } else {
3485 tty_port_init(&info->port);
3486 info->port.ops = &slgt_port_ops;
3487 INIT_WORK(&info->task, bh_handler);
3488 info->max_frame_size = 4096;
3489 info->base_clock = 14745600;
3490 info->rbuf_fill_level = DMABUFSIZE;
3491 init_waitqueue_head(&info->status_event_wait_q);
3492 init_waitqueue_head(&info->event_wait_q);
3493 spin_lock_init(&info->netlock);
3494 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3495 info->idle_mode = HDLC_TXIDLE_FLAGS;
3496 info->adapter_num = adapter_num;
3497 info->port_num = port_num;
3498
3499 timer_setup(&info->tx_timer, tx_timeout, 0);
3500 timer_setup(&info->rx_timer, rx_timeout, 0);
3501
3502 /* Copy configuration info to device instance data */
3503 info->pdev = pdev;
3504 info->irq_level = pdev->irq;
3505 info->phys_reg_addr = pci_resource_start(pdev,0);
3506
3507 info->bus_type = MGSL_BUS_TYPE_PCI;
3508 info->irq_flags = IRQF_SHARED;
3509
3510 info->init_error = -1; /* assume error, set to 0 on successful init */
3511 }
3512
3513 return info;
3514}
3515
3516static void device_init(int adapter_num, struct pci_dev *pdev)
3517{
3518 struct slgt_info *port_array[SLGT_MAX_PORTS];
3519 int i;
3520 int port_count = 1;
3521
3522 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3523 port_count = 2;
3524 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3525 port_count = 4;
3526
3527 /* allocate device instances for all ports */
3528 for (i=0; i < port_count; ++i) {
3529 port_array[i] = alloc_dev(adapter_num, i, pdev);
3530 if (port_array[i] == NULL) {
3531 for (--i; i >= 0; --i) {
3532 tty_port_destroy(&port_array[i]->port);
3533 kfree(port_array[i]);
3534 }
3535 return;
3536 }
3537 }
3538
3539 /* give copy of port_array to all ports and add to device list */
3540 for (i=0; i < port_count; ++i) {
3541 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3542 add_device(port_array[i]);
3543 port_array[i]->port_count = port_count;
3544 spin_lock_init(&port_array[i]->lock);
3545 }
3546
3547 /* Allocate and claim adapter resources */
3548 if (!claim_resources(port_array[0])) {
3549
3550 alloc_dma_bufs(port_array[0]);
3551
3552 /* copy resource information from first port to others */
3553 for (i = 1; i < port_count; ++i) {
3554 port_array[i]->irq_level = port_array[0]->irq_level;
3555 port_array[i]->reg_addr = port_array[0]->reg_addr;
3556 alloc_dma_bufs(port_array[i]);
3557 }
3558
3559 if (request_irq(port_array[0]->irq_level,
3560 slgt_interrupt,
3561 port_array[0]->irq_flags,
3562 port_array[0]->device_name,
3563 port_array[0]) < 0) {
3564 DBGERR(("%s request_irq failed IRQ=%d\n",
3565 port_array[0]->device_name,
3566 port_array[0]->irq_level));
3567 } else {
3568 port_array[0]->irq_requested = true;
3569 adapter_test(port_array[0]);
3570 for (i=1 ; i < port_count ; i++) {
3571 port_array[i]->init_error = port_array[0]->init_error;
3572 port_array[i]->gpio_present = port_array[0]->gpio_present;
3573 }
3574 }
3575 }
3576
3577 for (i = 0; i < port_count; ++i) {
3578 struct slgt_info *info = port_array[i];
3579 tty_port_register_device(&info->port, serial_driver, info->line,
3580 &info->pdev->dev);
3581 }
3582}
3583
3584static int init_one(struct pci_dev *dev,
3585 const struct pci_device_id *ent)
3586{
3587 if (pci_enable_device(dev)) {
3588 printk("error enabling pci device %p\n", dev);
3589 return -EIO;
3590 }
3591 pci_set_master(dev);
3592 device_init(slgt_device_count, dev);
3593 return 0;
3594}
3595
3596static void remove_one(struct pci_dev *dev)
3597{
3598}
3599
3600static const struct tty_operations ops = {
3601 .open = open,
3602 .close = close,
3603 .write = write,
3604 .put_char = put_char,
3605 .flush_chars = flush_chars,
3606 .write_room = write_room,
3607 .chars_in_buffer = chars_in_buffer,
3608 .flush_buffer = flush_buffer,
3609 .ioctl = ioctl,
3610 .compat_ioctl = slgt_compat_ioctl,
3611 .throttle = throttle,
3612 .unthrottle = unthrottle,
3613 .send_xchar = send_xchar,
3614 .break_ctl = set_break,
3615 .wait_until_sent = wait_until_sent,
3616 .set_termios = set_termios,
3617 .stop = tx_hold,
3618 .start = tx_release,
3619 .hangup = hangup,
3620 .tiocmget = tiocmget,
3621 .tiocmset = tiocmset,
3622 .get_icount = get_icount,
3623 .proc_show = synclink_gt_proc_show,
3624};
3625
3626static void slgt_cleanup(void)
3627{
3628 struct slgt_info *info;
3629 struct slgt_info *tmp;
3630
3631 if (serial_driver) {
3632 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3633 tty_unregister_device(serial_driver, info->line);
3634 tty_unregister_driver(serial_driver);
3635 tty_driver_kref_put(serial_driver);
3636 }
3637
3638 /* reset devices */
3639 info = slgt_device_list;
3640 while(info) {
3641 reset_port(info);
3642 info = info->next_device;
3643 }
3644
3645 /* release devices */
3646 info = slgt_device_list;
3647 while(info) {
3648#if SYNCLINK_GENERIC_HDLC
3649 hdlcdev_exit(info);
3650#endif
3651 free_dma_bufs(info);
3652 free_tmp_rbuf(info);
3653 if (info->port_num == 0)
3654 release_resources(info);
3655 tmp = info;
3656 info = info->next_device;
3657 tty_port_destroy(&tmp->port);
3658 kfree(tmp);
3659 }
3660
3661 if (pci_registered)
3662 pci_unregister_driver(&pci_driver);
3663}
3664
3665/*
3666 * Driver initialization entry point.
3667 */
3668static int __init slgt_init(void)
3669{
3670 int rc;
3671
3672 serial_driver = tty_alloc_driver(MAX_DEVICES, TTY_DRIVER_REAL_RAW |
3673 TTY_DRIVER_DYNAMIC_DEV);
3674 if (IS_ERR(serial_driver)) {
3675 printk("%s can't allocate tty driver\n", driver_name);
3676 return PTR_ERR(serial_driver);
3677 }
3678
3679 /* Initialize the tty_driver structure */
3680
3681 serial_driver->driver_name = "synclink_gt";
3682 serial_driver->name = tty_dev_prefix;
3683 serial_driver->major = ttymajor;
3684 serial_driver->minor_start = 64;
3685 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3686 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3687 serial_driver->init_termios = tty_std_termios;
3688 serial_driver->init_termios.c_cflag =
3689 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3690 serial_driver->init_termios.c_ispeed = 9600;
3691 serial_driver->init_termios.c_ospeed = 9600;
3692 tty_set_operations(serial_driver, &ops);
3693 if ((rc = tty_register_driver(serial_driver)) < 0) {
3694 DBGERR(("%s can't register serial driver\n", driver_name));
3695 tty_driver_kref_put(serial_driver);
3696 serial_driver = NULL;
3697 goto error;
3698 }
3699
3700 slgt_device_count = 0;
3701 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3702 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3703 goto error;
3704 }
3705 pci_registered = true;
3706
3707 return 0;
3708
3709error:
3710 slgt_cleanup();
3711 return rc;
3712}
3713
3714static void __exit slgt_exit(void)
3715{
3716 slgt_cleanup();
3717}
3718
3719module_init(slgt_init);
3720module_exit(slgt_exit);
3721
3722/*
3723 * register access routines
3724 */
3725
3726static inline void __iomem *calc_regaddr(struct slgt_info *info,
3727 unsigned int addr)
3728{
3729 void __iomem *reg_addr = info->reg_addr + addr;
3730
3731 if (addr >= 0x80)
3732 reg_addr += info->port_num * 32;
3733 else if (addr >= 0x40)
3734 reg_addr += info->port_num * 16;
3735
3736 return reg_addr;
3737}
3738
3739static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3740{
3741 return readb(calc_regaddr(info, addr));
3742}
3743
3744static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3745{
3746 writeb(value, calc_regaddr(info, addr));
3747}
3748
3749static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3750{
3751 return readw(calc_regaddr(info, addr));
3752}
3753
3754static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3755{
3756 writew(value, calc_regaddr(info, addr));
3757}
3758
3759static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3760{
3761 return readl(calc_regaddr(info, addr));
3762}
3763
3764static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3765{
3766 writel(value, calc_regaddr(info, addr));
3767}
3768
3769static void rdma_reset(struct slgt_info *info)
3770{
3771 unsigned int i;
3772
3773 /* set reset bit */
3774 wr_reg32(info, RDCSR, BIT1);
3775
3776 /* wait for enable bit cleared */
3777 for(i=0 ; i < 1000 ; i++)
3778 if (!(rd_reg32(info, RDCSR) & BIT0))
3779 break;
3780}
3781
3782static void tdma_reset(struct slgt_info *info)
3783{
3784 unsigned int i;
3785
3786 /* set reset bit */
3787 wr_reg32(info, TDCSR, BIT1);
3788
3789 /* wait for enable bit cleared */
3790 for(i=0 ; i < 1000 ; i++)
3791 if (!(rd_reg32(info, TDCSR) & BIT0))
3792 break;
3793}
3794
3795/*
3796 * enable internal loopback
3797 * TxCLK and RxCLK are generated from BRG
3798 * and TxD is looped back to RxD internally.
3799 */
3800static void enable_loopback(struct slgt_info *info)
3801{
3802 /* SCR (serial control) BIT2=loopback enable */
3803 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3804
3805 if (info->params.mode != MGSL_MODE_ASYNC) {
3806 /* CCR (clock control)
3807 * 07..05 tx clock source (010 = BRG)
3808 * 04..02 rx clock source (010 = BRG)
3809 * 01 auxclk enable (0 = disable)
3810 * 00 BRG enable (1 = enable)
3811 *
3812 * 0100 1001
3813 */
3814 wr_reg8(info, CCR, 0x49);
3815
3816 /* set speed if available, otherwise use default */
3817 if (info->params.clock_speed)
3818 set_rate(info, info->params.clock_speed);
3819 else
3820 set_rate(info, 3686400);
3821 }
3822}
3823
3824/*
3825 * set baud rate generator to specified rate
3826 */
3827static void set_rate(struct slgt_info *info, u32 rate)
3828{
3829 unsigned int div;
3830 unsigned int osc = info->base_clock;
3831
3832 /* div = osc/rate - 1
3833 *
3834 * Round div up if osc/rate is not integer to
3835 * force to next slowest rate.
3836 */
3837
3838 if (rate) {
3839 div = osc/rate;
3840 if (!(osc % rate) && div)
3841 div--;
3842 wr_reg16(info, BDR, (unsigned short)div);
3843 }
3844}
3845
3846static void rx_stop(struct slgt_info *info)
3847{
3848 unsigned short val;
3849
3850 /* disable and reset receiver */
3851 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3852 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3853 wr_reg16(info, RCR, val); /* clear reset bit */
3854
3855 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3856
3857 /* clear pending rx interrupts */
3858 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3859
3860 rdma_reset(info);
3861
3862 info->rx_enabled = false;
3863 info->rx_restart = false;
3864}
3865
3866static void rx_start(struct slgt_info *info)
3867{
3868 unsigned short val;
3869
3870 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3871
3872 /* clear pending rx overrun IRQ */
3873 wr_reg16(info, SSR, IRQ_RXOVER);
3874
3875 /* reset and disable receiver */
3876 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3877 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3878 wr_reg16(info, RCR, val); /* clear reset bit */
3879
3880 rdma_reset(info);
3881 reset_rbufs(info);
3882
3883 if (info->rx_pio) {
3884 /* rx request when rx FIFO not empty */
3885 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) & ~BIT14));
3886 slgt_irq_on(info, IRQ_RXDATA);
3887 if (info->params.mode == MGSL_MODE_ASYNC) {
3888 /* enable saving of rx status */
3889 wr_reg32(info, RDCSR, BIT6);
3890 }
3891 } else {
3892 /* rx request when rx FIFO half full */
3893 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT14));
3894 /* set 1st descriptor address */
3895 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3896
3897 if (info->params.mode != MGSL_MODE_ASYNC) {
3898 /* enable rx DMA and DMA interrupt */
3899 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3900 } else {
3901 /* enable saving of rx status, rx DMA and DMA interrupt */
3902 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3903 }
3904 }
3905
3906 slgt_irq_on(info, IRQ_RXOVER);
3907
3908 /* enable receiver */
3909 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3910
3911 info->rx_restart = false;
3912 info->rx_enabled = true;
3913}
3914
3915static void tx_start(struct slgt_info *info)
3916{
3917 if (!info->tx_enabled) {
3918 wr_reg16(info, TCR,
3919 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3920 info->tx_enabled = true;
3921 }
3922
3923 if (desc_count(info->tbufs[info->tbuf_start])) {
3924 info->drop_rts_on_tx_done = false;
3925
3926 if (info->params.mode != MGSL_MODE_ASYNC) {
3927 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3928 get_gtsignals(info);
3929 if (!(info->signals & SerialSignal_RTS)) {
3930 info->signals |= SerialSignal_RTS;
3931 set_gtsignals(info);
3932 info->drop_rts_on_tx_done = true;
3933 }
3934 }
3935
3936 slgt_irq_off(info, IRQ_TXDATA);
3937 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3938 /* clear tx idle and underrun status bits */
3939 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3940 } else {
3941 slgt_irq_off(info, IRQ_TXDATA);
3942 slgt_irq_on(info, IRQ_TXIDLE);
3943 /* clear tx idle status bit */
3944 wr_reg16(info, SSR, IRQ_TXIDLE);
3945 }
3946 /* set 1st descriptor address and start DMA */
3947 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3948 wr_reg32(info, TDCSR, BIT2 + BIT0);
3949 info->tx_active = true;
3950 }
3951}
3952
3953static void tx_stop(struct slgt_info *info)
3954{
3955 unsigned short val;
3956
3957 del_timer(&info->tx_timer);
3958
3959 tdma_reset(info);
3960
3961 /* reset and disable transmitter */
3962 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3963 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3964
3965 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3966
3967 /* clear tx idle and underrun status bit */
3968 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3969
3970 reset_tbufs(info);
3971
3972 info->tx_enabled = false;
3973 info->tx_active = false;
3974}
3975
3976static void reset_port(struct slgt_info *info)
3977{
3978 if (!info->reg_addr)
3979 return;
3980
3981 tx_stop(info);
3982 rx_stop(info);
3983
3984 info->signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3985 set_gtsignals(info);
3986
3987 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3988}
3989
3990static void reset_adapter(struct slgt_info *info)
3991{
3992 int i;
3993 for (i=0; i < info->port_count; ++i) {
3994 if (info->port_array[i])
3995 reset_port(info->port_array[i]);
3996 }
3997}
3998
3999static void async_mode(struct slgt_info *info)
4000{
4001 unsigned short val;
4002
4003 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4004 tx_stop(info);
4005 rx_stop(info);
4006
4007 /* TCR (tx control)
4008 *
4009 * 15..13 mode, 010=async
4010 * 12..10 encoding, 000=NRZ
4011 * 09 parity enable
4012 * 08 1=odd parity, 0=even parity
4013 * 07 1=RTS driver control
4014 * 06 1=break enable
4015 * 05..04 character length
4016 * 00=5 bits
4017 * 01=6 bits
4018 * 10=7 bits
4019 * 11=8 bits
4020 * 03 0=1 stop bit, 1=2 stop bits
4021 * 02 reset
4022 * 01 enable
4023 * 00 auto-CTS enable
4024 */
4025 val = 0x4000;
4026
4027 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4028 val |= BIT7;
4029
4030 if (info->params.parity != ASYNC_PARITY_NONE) {
4031 val |= BIT9;
4032 if (info->params.parity == ASYNC_PARITY_ODD)
4033 val |= BIT8;
4034 }
4035
4036 switch (info->params.data_bits)
4037 {
4038 case 6: val |= BIT4; break;
4039 case 7: val |= BIT5; break;
4040 case 8: val |= BIT5 + BIT4; break;
4041 }
4042
4043 if (info->params.stop_bits != 1)
4044 val |= BIT3;
4045
4046 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4047 val |= BIT0;
4048
4049 wr_reg16(info, TCR, val);
4050
4051 /* RCR (rx control)
4052 *
4053 * 15..13 mode, 010=async
4054 * 12..10 encoding, 000=NRZ
4055 * 09 parity enable
4056 * 08 1=odd parity, 0=even parity
4057 * 07..06 reserved, must be 0
4058 * 05..04 character length
4059 * 00=5 bits
4060 * 01=6 bits
4061 * 10=7 bits
4062 * 11=8 bits
4063 * 03 reserved, must be zero
4064 * 02 reset
4065 * 01 enable
4066 * 00 auto-DCD enable
4067 */
4068 val = 0x4000;
4069
4070 if (info->params.parity != ASYNC_PARITY_NONE) {
4071 val |= BIT9;
4072 if (info->params.parity == ASYNC_PARITY_ODD)
4073 val |= BIT8;
4074 }
4075
4076 switch (info->params.data_bits)
4077 {
4078 case 6: val |= BIT4; break;
4079 case 7: val |= BIT5; break;
4080 case 8: val |= BIT5 + BIT4; break;
4081 }
4082
4083 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4084 val |= BIT0;
4085
4086 wr_reg16(info, RCR, val);
4087
4088 /* CCR (clock control)
4089 *
4090 * 07..05 011 = tx clock source is BRG/16
4091 * 04..02 010 = rx clock source is BRG
4092 * 01 0 = auxclk disabled
4093 * 00 1 = BRG enabled
4094 *
4095 * 0110 1001
4096 */
4097 wr_reg8(info, CCR, 0x69);
4098
4099 msc_set_vcr(info);
4100
4101 /* SCR (serial control)
4102 *
4103 * 15 1=tx req on FIFO half empty
4104 * 14 1=rx req on FIFO half full
4105 * 13 tx data IRQ enable
4106 * 12 tx idle IRQ enable
4107 * 11 rx break on IRQ enable
4108 * 10 rx data IRQ enable
4109 * 09 rx break off IRQ enable
4110 * 08 overrun IRQ enable
4111 * 07 DSR IRQ enable
4112 * 06 CTS IRQ enable
4113 * 05 DCD IRQ enable
4114 * 04 RI IRQ enable
4115 * 03 0=16x sampling, 1=8x sampling
4116 * 02 1=txd->rxd internal loopback enable
4117 * 01 reserved, must be zero
4118 * 00 1=master IRQ enable
4119 */
4120 val = BIT15 + BIT14 + BIT0;
4121 /* JCR[8] : 1 = x8 async mode feature available */
4122 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4123 ((info->base_clock < (info->params.data_rate * 16)) ||
4124 (info->base_clock % (info->params.data_rate * 16)))) {
4125 /* use 8x sampling */
4126 val |= BIT3;
4127 set_rate(info, info->params.data_rate * 8);
4128 } else {
4129 /* use 16x sampling */
4130 set_rate(info, info->params.data_rate * 16);
4131 }
4132 wr_reg16(info, SCR, val);
4133
4134 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4135
4136 if (info->params.loopback)
4137 enable_loopback(info);
4138}
4139
4140static void sync_mode(struct slgt_info *info)
4141{
4142 unsigned short val;
4143
4144 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4145 tx_stop(info);
4146 rx_stop(info);
4147
4148 /* TCR (tx control)
4149 *
4150 * 15..13 mode
4151 * 000=HDLC/SDLC
4152 * 001=raw bit synchronous
4153 * 010=asynchronous/isochronous
4154 * 011=monosync byte synchronous
4155 * 100=bisync byte synchronous
4156 * 101=xsync byte synchronous
4157 * 12..10 encoding
4158 * 09 CRC enable
4159 * 08 CRC32
4160 * 07 1=RTS driver control
4161 * 06 preamble enable
4162 * 05..04 preamble length
4163 * 03 share open/close flag
4164 * 02 reset
4165 * 01 enable
4166 * 00 auto-CTS enable
4167 */
4168 val = BIT2;
4169
4170 switch(info->params.mode) {
4171 case MGSL_MODE_XSYNC:
4172 val |= BIT15 + BIT13;
4173 break;
4174 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4175 case MGSL_MODE_BISYNC: val |= BIT15; break;
4176 case MGSL_MODE_RAW: val |= BIT13; break;
4177 }
4178 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4179 val |= BIT7;
4180
4181 switch(info->params.encoding)
4182 {
4183 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4184 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4185 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4186 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4187 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4188 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4189 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4190 }
4191
4192 switch (info->params.crc_type & HDLC_CRC_MASK)
4193 {
4194 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4195 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4196 }
4197
4198 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4199 val |= BIT6;
4200
4201 switch (info->params.preamble_length)
4202 {
4203 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4204 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4205 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4206 }
4207
4208 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4209 val |= BIT0;
4210
4211 wr_reg16(info, TCR, val);
4212
4213 /* TPR (transmit preamble) */
4214
4215 switch (info->params.preamble)
4216 {
4217 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4218 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4219 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4220 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4221 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4222 default: val = 0x7e; break;
4223 }
4224 wr_reg8(info, TPR, (unsigned char)val);
4225
4226 /* RCR (rx control)
4227 *
4228 * 15..13 mode
4229 * 000=HDLC/SDLC
4230 * 001=raw bit synchronous
4231 * 010=asynchronous/isochronous
4232 * 011=monosync byte synchronous
4233 * 100=bisync byte synchronous
4234 * 101=xsync byte synchronous
4235 * 12..10 encoding
4236 * 09 CRC enable
4237 * 08 CRC32
4238 * 07..03 reserved, must be 0
4239 * 02 reset
4240 * 01 enable
4241 * 00 auto-DCD enable
4242 */
4243 val = 0;
4244
4245 switch(info->params.mode) {
4246 case MGSL_MODE_XSYNC:
4247 val |= BIT15 + BIT13;
4248 break;
4249 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4250 case MGSL_MODE_BISYNC: val |= BIT15; break;
4251 case MGSL_MODE_RAW: val |= BIT13; break;
4252 }
4253
4254 switch(info->params.encoding)
4255 {
4256 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4257 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4258 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4259 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4260 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4261 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4262 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4263 }
4264
4265 switch (info->params.crc_type & HDLC_CRC_MASK)
4266 {
4267 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4268 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4269 }
4270
4271 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4272 val |= BIT0;
4273
4274 wr_reg16(info, RCR, val);
4275
4276 /* CCR (clock control)
4277 *
4278 * 07..05 tx clock source
4279 * 04..02 rx clock source
4280 * 01 auxclk enable
4281 * 00 BRG enable
4282 */
4283 val = 0;
4284
4285 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4286 {
4287 // when RxC source is DPLL, BRG generates 16X DPLL
4288 // reference clock, so take TxC from BRG/16 to get
4289 // transmit clock at actual data rate
4290 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4291 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4292 else
4293 val |= BIT6; /* 010, txclk = BRG */
4294 }
4295 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4296 val |= BIT7; /* 100, txclk = DPLL Input */
4297 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4298 val |= BIT5; /* 001, txclk = RXC Input */
4299
4300 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4301 val |= BIT3; /* 010, rxclk = BRG */
4302 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4303 val |= BIT4; /* 100, rxclk = DPLL */
4304 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4305 val |= BIT2; /* 001, rxclk = TXC Input */
4306
4307 if (info->params.clock_speed)
4308 val |= BIT1 + BIT0;
4309
4310 wr_reg8(info, CCR, (unsigned char)val);
4311
4312 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4313 {
4314 // program DPLL mode
4315 switch(info->params.encoding)
4316 {
4317 case HDLC_ENCODING_BIPHASE_MARK:
4318 case HDLC_ENCODING_BIPHASE_SPACE:
4319 val = BIT7; break;
4320 case HDLC_ENCODING_BIPHASE_LEVEL:
4321 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4322 val = BIT7 + BIT6; break;
4323 default: val = BIT6; // NRZ encodings
4324 }
4325 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4326
4327 // DPLL requires a 16X reference clock from BRG
4328 set_rate(info, info->params.clock_speed * 16);
4329 }
4330 else
4331 set_rate(info, info->params.clock_speed);
4332
4333 tx_set_idle(info);
4334
4335 msc_set_vcr(info);
4336
4337 /* SCR (serial control)
4338 *
4339 * 15 1=tx req on FIFO half empty
4340 * 14 1=rx req on FIFO half full
4341 * 13 tx data IRQ enable
4342 * 12 tx idle IRQ enable
4343 * 11 underrun IRQ enable
4344 * 10 rx data IRQ enable
4345 * 09 rx idle IRQ enable
4346 * 08 overrun IRQ enable
4347 * 07 DSR IRQ enable
4348 * 06 CTS IRQ enable
4349 * 05 DCD IRQ enable
4350 * 04 RI IRQ enable
4351 * 03 reserved, must be zero
4352 * 02 1=txd->rxd internal loopback enable
4353 * 01 reserved, must be zero
4354 * 00 1=master IRQ enable
4355 */
4356 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4357
4358 if (info->params.loopback)
4359 enable_loopback(info);
4360}
4361
4362/*
4363 * set transmit idle mode
4364 */
4365static void tx_set_idle(struct slgt_info *info)
4366{
4367 unsigned char val;
4368 unsigned short tcr;
4369
4370 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4371 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4372 */
4373 tcr = rd_reg16(info, TCR);
4374 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4375 /* disable preamble, set idle size to 16 bits */
4376 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4377 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4378 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4379 } else if (!(tcr & BIT6)) {
4380 /* preamble is disabled, set idle size to 8 bits */
4381 tcr &= ~(BIT5 + BIT4);
4382 }
4383 wr_reg16(info, TCR, tcr);
4384
4385 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4386 /* LSB of custom tx idle specified in tx idle register */
4387 val = (unsigned char)(info->idle_mode & 0xff);
4388 } else {
4389 /* standard 8 bit idle patterns */
4390 switch(info->idle_mode)
4391 {
4392 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4393 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4394 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4395 case HDLC_TXIDLE_ZEROS:
4396 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4397 default: val = 0xff;
4398 }
4399 }
4400
4401 wr_reg8(info, TIR, val);
4402}
4403
4404/*
4405 * get state of V24 status (input) signals
4406 */
4407static void get_gtsignals(struct slgt_info *info)
4408{
4409 unsigned short status = rd_reg16(info, SSR);
4410
4411 /* clear all serial signals except RTS and DTR */
4412 info->signals &= SerialSignal_RTS | SerialSignal_DTR;
4413
4414 if (status & BIT3)
4415 info->signals |= SerialSignal_DSR;
4416 if (status & BIT2)
4417 info->signals |= SerialSignal_CTS;
4418 if (status & BIT1)
4419 info->signals |= SerialSignal_DCD;
4420 if (status & BIT0)
4421 info->signals |= SerialSignal_RI;
4422}
4423
4424/*
4425 * set V.24 Control Register based on current configuration
4426 */
4427static void msc_set_vcr(struct slgt_info *info)
4428{
4429 unsigned char val = 0;
4430
4431 /* VCR (V.24 control)
4432 *
4433 * 07..04 serial IF select
4434 * 03 DTR
4435 * 02 RTS
4436 * 01 LL
4437 * 00 RL
4438 */
4439
4440 switch(info->if_mode & MGSL_INTERFACE_MASK)
4441 {
4442 case MGSL_INTERFACE_RS232:
4443 val |= BIT5; /* 0010 */
4444 break;
4445 case MGSL_INTERFACE_V35:
4446 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4447 break;
4448 case MGSL_INTERFACE_RS422:
4449 val |= BIT6; /* 0100 */
4450 break;
4451 }
4452
4453 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4454 val |= BIT4;
4455 if (info->signals & SerialSignal_DTR)
4456 val |= BIT3;
4457 if (info->signals & SerialSignal_RTS)
4458 val |= BIT2;
4459 if (info->if_mode & MGSL_INTERFACE_LL)
4460 val |= BIT1;
4461 if (info->if_mode & MGSL_INTERFACE_RL)
4462 val |= BIT0;
4463 wr_reg8(info, VCR, val);
4464}
4465
4466/*
4467 * set state of V24 control (output) signals
4468 */
4469static void set_gtsignals(struct slgt_info *info)
4470{
4471 unsigned char val = rd_reg8(info, VCR);
4472 if (info->signals & SerialSignal_DTR)
4473 val |= BIT3;
4474 else
4475 val &= ~BIT3;
4476 if (info->signals & SerialSignal_RTS)
4477 val |= BIT2;
4478 else
4479 val &= ~BIT2;
4480 wr_reg8(info, VCR, val);
4481}
4482
4483/*
4484 * free range of receive DMA buffers (i to last)
4485 */
4486static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4487{
4488 int done = 0;
4489
4490 while(!done) {
4491 /* reset current buffer for reuse */
4492 info->rbufs[i].status = 0;
4493 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4494 if (i == last)
4495 done = 1;
4496 if (++i == info->rbuf_count)
4497 i = 0;
4498 }
4499 info->rbuf_current = i;
4500}
4501
4502/*
4503 * mark all receive DMA buffers as free
4504 */
4505static void reset_rbufs(struct slgt_info *info)
4506{
4507 free_rbufs(info, 0, info->rbuf_count - 1);
4508 info->rbuf_fill_index = 0;
4509 info->rbuf_fill_count = 0;
4510}
4511
4512/*
4513 * pass receive HDLC frame to upper layer
4514 *
4515 * return true if frame available, otherwise false
4516 */
4517static bool rx_get_frame(struct slgt_info *info)
4518{
4519 unsigned int start, end;
4520 unsigned short status;
4521 unsigned int framesize = 0;
4522 unsigned long flags;
4523 struct tty_struct *tty = info->port.tty;
4524 unsigned char addr_field = 0xff;
4525 unsigned int crc_size = 0;
4526
4527 switch (info->params.crc_type & HDLC_CRC_MASK) {
4528 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4529 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4530 }
4531
4532check_again:
4533
4534 framesize = 0;
4535 addr_field = 0xff;
4536 start = end = info->rbuf_current;
4537
4538 for (;;) {
4539 if (!desc_complete(info->rbufs[end]))
4540 goto cleanup;
4541
4542 if (framesize == 0 && info->params.addr_filter != 0xff)
4543 addr_field = info->rbufs[end].buf[0];
4544
4545 framesize += desc_count(info->rbufs[end]);
4546
4547 if (desc_eof(info->rbufs[end]))
4548 break;
4549
4550 if (++end == info->rbuf_count)
4551 end = 0;
4552
4553 if (end == info->rbuf_current) {
4554 if (info->rx_enabled){
4555 spin_lock_irqsave(&info->lock,flags);
4556 rx_start(info);
4557 spin_unlock_irqrestore(&info->lock,flags);
4558 }
4559 goto cleanup;
4560 }
4561 }
4562
4563 /* status
4564 *
4565 * 15 buffer complete
4566 * 14..06 reserved
4567 * 05..04 residue
4568 * 02 eof (end of frame)
4569 * 01 CRC error
4570 * 00 abort
4571 */
4572 status = desc_status(info->rbufs[end]);
4573
4574 /* ignore CRC bit if not using CRC (bit is undefined) */
4575 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4576 status &= ~BIT1;
4577
4578 if (framesize == 0 ||
4579 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4580 free_rbufs(info, start, end);
4581 goto check_again;
4582 }
4583
4584 if (framesize < (2 + crc_size) || status & BIT0) {
4585 info->icount.rxshort++;
4586 framesize = 0;
4587 } else if (status & BIT1) {
4588 info->icount.rxcrc++;
4589 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4590 framesize = 0;
4591 }
4592
4593#if SYNCLINK_GENERIC_HDLC
4594 if (framesize == 0) {
4595 info->netdev->stats.rx_errors++;
4596 info->netdev->stats.rx_frame_errors++;
4597 }
4598#endif
4599
4600 DBGBH(("%s rx frame status=%04X size=%d\n",
4601 info->device_name, status, framesize));
4602 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4603
4604 if (framesize) {
4605 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4606 framesize -= crc_size;
4607 crc_size = 0;
4608 }
4609
4610 if (framesize > info->max_frame_size + crc_size)
4611 info->icount.rxlong++;
4612 else {
4613 /* copy dma buffer(s) to contiguous temp buffer */
4614 int copy_count = framesize;
4615 int i = start;
4616 unsigned char *p = info->tmp_rbuf;
4617 info->tmp_rbuf_count = framesize;
4618
4619 info->icount.rxok++;
4620
4621 while(copy_count) {
4622 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4623 memcpy(p, info->rbufs[i].buf, partial_count);
4624 p += partial_count;
4625 copy_count -= partial_count;
4626 if (++i == info->rbuf_count)
4627 i = 0;
4628 }
4629
4630 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4631 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4632 framesize++;
4633 }
4634
4635#if SYNCLINK_GENERIC_HDLC
4636 if (info->netcount)
4637 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4638 else
4639#endif
4640 ldisc_receive_buf(tty, info->tmp_rbuf, NULL,
4641 framesize);
4642 }
4643 }
4644 free_rbufs(info, start, end);
4645 return true;
4646
4647cleanup:
4648 return false;
4649}
4650
4651/*
4652 * pass receive buffer (RAW synchronous mode) to tty layer
4653 * return true if buffer available, otherwise false
4654 */
4655static bool rx_get_buf(struct slgt_info *info)
4656{
4657 unsigned int i = info->rbuf_current;
4658 unsigned int count;
4659
4660 if (!desc_complete(info->rbufs[i]))
4661 return false;
4662 count = desc_count(info->rbufs[i]);
4663 switch(info->params.mode) {
4664 case MGSL_MODE_MONOSYNC:
4665 case MGSL_MODE_BISYNC:
4666 case MGSL_MODE_XSYNC:
4667 /* ignore residue in byte synchronous modes */
4668 if (desc_residue(info->rbufs[i]))
4669 count--;
4670 break;
4671 }
4672 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4673 DBGINFO(("rx_get_buf size=%d\n", count));
4674 if (count)
4675 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf, NULL,
4676 count);
4677 free_rbufs(info, i, i);
4678 return true;
4679}
4680
4681static void reset_tbufs(struct slgt_info *info)
4682{
4683 unsigned int i;
4684 info->tbuf_current = 0;
4685 for (i=0 ; i < info->tbuf_count ; i++) {
4686 info->tbufs[i].status = 0;
4687 info->tbufs[i].count = 0;
4688 }
4689}
4690
4691/*
4692 * return number of free transmit DMA buffers
4693 */
4694static unsigned int free_tbuf_count(struct slgt_info *info)
4695{
4696 unsigned int count = 0;
4697 unsigned int i = info->tbuf_current;
4698
4699 do
4700 {
4701 if (desc_count(info->tbufs[i]))
4702 break; /* buffer in use */
4703 ++count;
4704 if (++i == info->tbuf_count)
4705 i=0;
4706 } while (i != info->tbuf_current);
4707
4708 /* if tx DMA active, last zero count buffer is in use */
4709 if (count && (rd_reg32(info, TDCSR) & BIT0))
4710 --count;
4711
4712 return count;
4713}
4714
4715/*
4716 * return number of bytes in unsent transmit DMA buffers
4717 * and the serial controller tx FIFO
4718 */
4719static unsigned int tbuf_bytes(struct slgt_info *info)
4720{
4721 unsigned int total_count = 0;
4722 unsigned int i = info->tbuf_current;
4723 unsigned int reg_value;
4724 unsigned int count;
4725 unsigned int active_buf_count = 0;
4726
4727 /*
4728 * Add descriptor counts for all tx DMA buffers.
4729 * If count is zero (cleared by DMA controller after read),
4730 * the buffer is complete or is actively being read from.
4731 *
4732 * Record buf_count of last buffer with zero count starting
4733 * from current ring position. buf_count is mirror
4734 * copy of count and is not cleared by serial controller.
4735 * If DMA controller is active, that buffer is actively
4736 * being read so add to total.
4737 */
4738 do {
4739 count = desc_count(info->tbufs[i]);
4740 if (count)
4741 total_count += count;
4742 else if (!total_count)
4743 active_buf_count = info->tbufs[i].buf_count;
4744 if (++i == info->tbuf_count)
4745 i = 0;
4746 } while (i != info->tbuf_current);
4747
4748 /* read tx DMA status register */
4749 reg_value = rd_reg32(info, TDCSR);
4750
4751 /* if tx DMA active, last zero count buffer is in use */
4752 if (reg_value & BIT0)
4753 total_count += active_buf_count;
4754
4755 /* add tx FIFO count = reg_value[15..8] */
4756 total_count += (reg_value >> 8) & 0xff;
4757
4758 /* if transmitter active add one byte for shift register */
4759 if (info->tx_active)
4760 total_count++;
4761
4762 return total_count;
4763}
4764
4765/*
4766 * load data into transmit DMA buffer ring and start transmitter if needed
4767 * return true if data accepted, otherwise false (buffers full)
4768 */
4769static bool tx_load(struct slgt_info *info, const u8 *buf, unsigned int size)
4770{
4771 unsigned short count;
4772 unsigned int i;
4773 struct slgt_desc *d;
4774
4775 /* check required buffer space */
4776 if (DIV_ROUND_UP(size, DMABUFSIZE) > free_tbuf_count(info))
4777 return false;
4778
4779 DBGDATA(info, buf, size, "tx");
4780
4781 /*
4782 * copy data to one or more DMA buffers in circular ring
4783 * tbuf_start = first buffer for this data
4784 * tbuf_current = next free buffer
4785 *
4786 * Copy all data before making data visible to DMA controller by
4787 * setting descriptor count of the first buffer.
4788 * This prevents an active DMA controller from reading the first DMA
4789 * buffers of a frame and stopping before the final buffers are filled.
4790 */
4791
4792 info->tbuf_start = i = info->tbuf_current;
4793
4794 while (size) {
4795 d = &info->tbufs[i];
4796
4797 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4798 memcpy(d->buf, buf, count);
4799
4800 size -= count;
4801 buf += count;
4802
4803 /*
4804 * set EOF bit for last buffer of HDLC frame or
4805 * for every buffer in raw mode
4806 */
4807 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4808 info->params.mode == MGSL_MODE_RAW)
4809 set_desc_eof(*d, 1);
4810 else
4811 set_desc_eof(*d, 0);
4812
4813 /* set descriptor count for all but first buffer */
4814 if (i != info->tbuf_start)
4815 set_desc_count(*d, count);
4816 d->buf_count = count;
4817
4818 if (++i == info->tbuf_count)
4819 i = 0;
4820 }
4821
4822 info->tbuf_current = i;
4823
4824 /* set first buffer count to make new data visible to DMA controller */
4825 d = &info->tbufs[info->tbuf_start];
4826 set_desc_count(*d, d->buf_count);
4827
4828 /* start transmitter if needed and update transmit timeout */
4829 if (!info->tx_active)
4830 tx_start(info);
4831 update_tx_timer(info);
4832
4833 return true;
4834}
4835
4836static int register_test(struct slgt_info *info)
4837{
4838 static unsigned short patterns[] =
4839 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4840 static unsigned int count = ARRAY_SIZE(patterns);
4841 unsigned int i;
4842 int rc = 0;
4843
4844 for (i=0 ; i < count ; i++) {
4845 wr_reg16(info, TIR, patterns[i]);
4846 wr_reg16(info, BDR, patterns[(i+1)%count]);
4847 if ((rd_reg16(info, TIR) != patterns[i]) ||
4848 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4849 rc = -ENODEV;
4850 break;
4851 }
4852 }
4853 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4854 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4855 return rc;
4856}
4857
4858static int irq_test(struct slgt_info *info)
4859{
4860 unsigned long timeout;
4861 unsigned long flags;
4862 struct tty_struct *oldtty = info->port.tty;
4863 u32 speed = info->params.data_rate;
4864
4865 info->params.data_rate = 921600;
4866 info->port.tty = NULL;
4867
4868 spin_lock_irqsave(&info->lock, flags);
4869 async_mode(info);
4870 slgt_irq_on(info, IRQ_TXIDLE);
4871
4872 /* enable transmitter */
4873 wr_reg16(info, TCR,
4874 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4875
4876 /* write one byte and wait for tx idle */
4877 wr_reg16(info, TDR, 0);
4878
4879 /* assume failure */
4880 info->init_error = DiagStatus_IrqFailure;
4881 info->irq_occurred = false;
4882
4883 spin_unlock_irqrestore(&info->lock, flags);
4884
4885 timeout=100;
4886 while(timeout-- && !info->irq_occurred)
4887 msleep_interruptible(10);
4888
4889 spin_lock_irqsave(&info->lock,flags);
4890 reset_port(info);
4891 spin_unlock_irqrestore(&info->lock,flags);
4892
4893 info->params.data_rate = speed;
4894 info->port.tty = oldtty;
4895
4896 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4897 return info->irq_occurred ? 0 : -ENODEV;
4898}
4899
4900static int loopback_test_rx(struct slgt_info *info)
4901{
4902 unsigned char *src, *dest;
4903 int count;
4904
4905 if (desc_complete(info->rbufs[0])) {
4906 count = desc_count(info->rbufs[0]);
4907 src = info->rbufs[0].buf;
4908 dest = info->tmp_rbuf;
4909
4910 for( ; count ; count-=2, src+=2) {
4911 /* src=data byte (src+1)=status byte */
4912 if (!(*(src+1) & (BIT9 + BIT8))) {
4913 *dest = *src;
4914 dest++;
4915 info->tmp_rbuf_count++;
4916 }
4917 }
4918 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4919 return 1;
4920 }
4921 return 0;
4922}
4923
4924static int loopback_test(struct slgt_info *info)
4925{
4926#define TESTFRAMESIZE 20
4927
4928 unsigned long timeout;
4929 u16 count;
4930 unsigned char buf[TESTFRAMESIZE];
4931 int rc = -ENODEV;
4932 unsigned long flags;
4933
4934 struct tty_struct *oldtty = info->port.tty;
4935 MGSL_PARAMS params;
4936
4937 memcpy(¶ms, &info->params, sizeof(params));
4938
4939 info->params.mode = MGSL_MODE_ASYNC;
4940 info->params.data_rate = 921600;
4941 info->params.loopback = 1;
4942 info->port.tty = NULL;
4943
4944 /* build and send transmit frame */
4945 for (count = 0; count < TESTFRAMESIZE; ++count)
4946 buf[count] = (unsigned char)count;
4947
4948 info->tmp_rbuf_count = 0;
4949 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4950
4951 /* program hardware for HDLC and enabled receiver */
4952 spin_lock_irqsave(&info->lock,flags);
4953 async_mode(info);
4954 rx_start(info);
4955 tx_load(info, buf, count);
4956 spin_unlock_irqrestore(&info->lock, flags);
4957
4958 /* wait for receive complete */
4959 for (timeout = 100; timeout; --timeout) {
4960 msleep_interruptible(10);
4961 if (loopback_test_rx(info)) {
4962 rc = 0;
4963 break;
4964 }
4965 }
4966
4967 /* verify received frame length and contents */
4968 if (!rc && (info->tmp_rbuf_count != count ||
4969 memcmp(buf, info->tmp_rbuf, count))) {
4970 rc = -ENODEV;
4971 }
4972
4973 spin_lock_irqsave(&info->lock,flags);
4974 reset_adapter(info);
4975 spin_unlock_irqrestore(&info->lock,flags);
4976
4977 memcpy(&info->params, ¶ms, sizeof(info->params));
4978 info->port.tty = oldtty;
4979
4980 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4981 return rc;
4982}
4983
4984static int adapter_test(struct slgt_info *info)
4985{
4986 DBGINFO(("testing %s\n", info->device_name));
4987 if (register_test(info) < 0) {
4988 printk("register test failure %s addr=%08X\n",
4989 info->device_name, info->phys_reg_addr);
4990 } else if (irq_test(info) < 0) {
4991 printk("IRQ test failure %s IRQ=%d\n",
4992 info->device_name, info->irq_level);
4993 } else if (loopback_test(info) < 0) {
4994 printk("loopback test failure %s\n", info->device_name);
4995 }
4996 return info->init_error;
4997}
4998
4999/*
5000 * transmit timeout handler
5001 */
5002static void tx_timeout(struct timer_list *t)
5003{
5004 struct slgt_info *info = from_timer(info, t, tx_timer);
5005 unsigned long flags;
5006
5007 DBGINFO(("%s tx_timeout\n", info->device_name));
5008 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5009 info->icount.txtimeout++;
5010 }
5011 spin_lock_irqsave(&info->lock,flags);
5012 tx_stop(info);
5013 spin_unlock_irqrestore(&info->lock,flags);
5014
5015#if SYNCLINK_GENERIC_HDLC
5016 if (info->netcount)
5017 hdlcdev_tx_done(info);
5018 else
5019#endif
5020 bh_transmit(info);
5021}
5022
5023/*
5024 * receive buffer polling timer
5025 */
5026static void rx_timeout(struct timer_list *t)
5027{
5028 struct slgt_info *info = from_timer(info, t, rx_timer);
5029 unsigned long flags;
5030
5031 DBGINFO(("%s rx_timeout\n", info->device_name));
5032 spin_lock_irqsave(&info->lock, flags);
5033 info->pending_bh |= BH_RECEIVE;
5034 spin_unlock_irqrestore(&info->lock, flags);
5035 bh_handler(&info->task);
5036}
5037