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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk.h>
7#include <linux/clk-provider.h>
8#include <linux/delay.h>
9#include <linux/err.h>
10#include <linux/io.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/phy/phy.h>
17#include <linux/platform_device.h>
18#include <linux/regulator/consumer.h>
19#include <linux/reset.h>
20#include <linux/slab.h>
21
22#include "phy-qcom-qmp.h"
23#include "phy-qcom-qmp-pcs-misc-v3.h"
24#include "phy-qcom-qmp-pcs-misc-v4.h"
25#include "phy-qcom-qmp-pcs-usb-v4.h"
26#include "phy-qcom-qmp-pcs-usb-v5.h"
27#include "phy-qcom-qmp-pcs-usb-v6.h"
28#include "phy-qcom-qmp-pcs-usb-v7.h"
29
30/* QPHY_SW_RESET bit */
31#define SW_RESET BIT(0)
32/* QPHY_POWER_DOWN_CONTROL */
33#define SW_PWRDN BIT(0)
34/* QPHY_START_CONTROL bits */
35#define SERDES_START BIT(0)
36#define PCS_START BIT(1)
37/* QPHY_PCS_STATUS bit */
38#define PHYSTATUS BIT(6)
39
40/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
41/* DP PHY soft reset */
42#define SW_DPPHY_RESET BIT(0)
43/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
44#define SW_DPPHY_RESET_MUX BIT(1)
45/* USB3 PHY soft reset */
46#define SW_USB3PHY_RESET BIT(2)
47/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
48#define SW_USB3PHY_RESET_MUX BIT(3)
49
50/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
51#define USB3_MODE BIT(0) /* enables USB3 mode */
52#define DP_MODE BIT(1) /* enables DP mode */
53
54/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
55#define ARCVR_DTCT_EN BIT(0)
56#define ALFPS_DTCT_EN BIT(1)
57#define ARCVR_DTCT_EVENT_SEL BIT(4)
58
59/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
60#define IRQ_CLEAR BIT(0)
61
62/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
63#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
64
65#define PHY_INIT_COMPLETE_TIMEOUT 10000
66
67struct qmp_phy_init_tbl {
68 unsigned int offset;
69 unsigned int val;
70 /*
71 * mask of lanes for which this register is written
72 * for cases when second lane needs different values
73 */
74 u8 lane_mask;
75};
76
77#define QMP_PHY_INIT_CFG(o, v) \
78 { \
79 .offset = o, \
80 .val = v, \
81 .lane_mask = 0xff, \
82 }
83
84#define QMP_PHY_INIT_CFG_LANE(o, v, l) \
85 { \
86 .offset = o, \
87 .val = v, \
88 .lane_mask = l, \
89 }
90
91/* set of registers with offsets different per-PHY */
92enum qphy_reg_layout {
93 /* PCS registers */
94 QPHY_SW_RESET,
95 QPHY_START_CTRL,
96 QPHY_PCS_STATUS,
97 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
98 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
99 QPHY_PCS_POWER_DOWN_CONTROL,
100 QPHY_PCS_MISC_CLAMP_ENABLE,
101 /* Keep last to ensure regs_layout arrays are properly initialized */
102 QPHY_LAYOUT_SIZE
103};
104
105static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
106 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
107 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
108 [QPHY_PCS_STATUS] = QPHY_V2_PCS_USB_PCS_STATUS,
109 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL,
110 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR,
111 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL,
112};
113
114static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
115 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
116 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
117 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
118 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
119 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
120 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
121 [QPHY_PCS_MISC_CLAMP_ENABLE] = QPHY_V3_PCS_MISC_CLAMP_ENABLE,
122};
123
124static const unsigned int qmp_v3_usb3phy_regs_layout_qcm2290[QPHY_LAYOUT_SIZE] = {
125 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
126 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
127 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
128 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
129 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
130 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
131};
132
133static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
134 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
135 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
136 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
137 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
138
139 /* In PCS_USB */
140 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
141 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
142 [QPHY_PCS_MISC_CLAMP_ENABLE] = QPHY_V4_PCS_MISC_CLAMP_ENABLE,
143};
144
145static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
146 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
147 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
148 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
149 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
150
151 /* In PCS_USB */
152 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
153 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
154};
155
156static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
157 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET,
158 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL,
159 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1,
160 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL,
161
162 /* In PCS_USB */
163 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,
164 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
165};
166
167static const unsigned int qmp_v7_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
168 [QPHY_SW_RESET] = QPHY_V7_PCS_SW_RESET,
169 [QPHY_START_CTRL] = QPHY_V7_PCS_START_CONTROL,
170 [QPHY_PCS_STATUS] = QPHY_V7_PCS_PCS_STATUS1,
171 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V7_PCS_POWER_DOWN_CONTROL,
172
173 /* In PCS_USB */
174 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V7_PCS_USB3_AUTONOMOUS_MODE_CTRL,
175 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V7_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
176};
177
178static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
179 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
180 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
181 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
182 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
183 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
184 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
185 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
186 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
187 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
188 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
189 /* PLL and Loop filter settings */
190 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
191 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
192 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
193 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
194 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
195 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
196 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
197 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
198 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
199 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
200 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
201 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
202 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
203 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
204 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
205 /* SSC settings */
206 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
207 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
208 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
209 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
210 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
211 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
212 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
213};
214
215static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
216 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
217 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
218 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
219};
220
221static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
222 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
223 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
224 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
225 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
226 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
227 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
228 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
229 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
230 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
231 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
232};
233
234static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
235 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
236 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
237 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
238 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
239 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
240 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
241 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
242 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
243 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
244 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
245 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
246 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
247 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
248 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
249 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
250 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
251 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
252 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
253 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
254 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
255 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
256 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
257 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
258};
259
260static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
261 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
262 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
263 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
264 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
265 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
266 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
267 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
268 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
269 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
270 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
271 /* PLL and Loop filter settings */
272 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
273 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
274 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
275 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
276 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
277 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
278 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
279 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
280 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
281 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
282 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
283 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
284 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
285 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
286 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
287 /* SSC settings */
288 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
289 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
290 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
291 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
292 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
293 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
294 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
295};
296
297static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
298 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
299 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
300 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
301 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
302 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
303 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
304 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
305 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
306 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
307};
308
309static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
310 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
311 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
312 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
313 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
314 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
315 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
316 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
317 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
318 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
319 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
320 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
321 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
322 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
323 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
324 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
325 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
326 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
327 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
328 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
329 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
330 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
331 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
332 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
333};
334
335static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
336 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
337 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
338 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
339 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
340 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
341 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
342 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
343 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
344 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
345 /* PLL and Loop filter settings */
346 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
347 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
348 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
349 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
350 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
351 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
352 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
353 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
354 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
355 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
356 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
357 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
358 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
359 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
360 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
361 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
362 /* SSC settings */
363 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
364 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
365 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
366 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
367 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
368 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
369 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
370};
371
372static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
373 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
374 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
375 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
376};
377
378static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
379 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
380 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
381 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
382 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
383 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
384 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
385 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
386 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
387 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
388 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
389};
390
391static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
392 /* FLL settings */
393 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03),
394 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02),
395 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09),
396 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42),
397 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85),
398
399 /* Lock Det settings */
400 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),
401 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f),
402 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47),
403 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08),
404};
405
406static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
407 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
408 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
409 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
410 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
411 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
412 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
413 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
414 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
424 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
425 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
426 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
427 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
428 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
429 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
430 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
431 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
432 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
433 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
434 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
435 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
436 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
437 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
438 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
439 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
440 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
441 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
442 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
443};
444
445static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
446 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
447 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
448 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
449 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
450 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
451};
452
453static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
454 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
455 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
456 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
457 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
458 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
459 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
460 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
461 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
462 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
463 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
464 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
465};
466
467static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
468 /* FLL settings */
469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
471 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
472 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
473 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
474
475 /* Lock Det settings */
476 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
477 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
478 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
479 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
480
481 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
482 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
483 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
484 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
485 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
486 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
487 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
488 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
489 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
490 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
491 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
492 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
493 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
494 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
495 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
496 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
497 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
498 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
499 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
500
501 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
502 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
503 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
504 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
505 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
506 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
507 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
508 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
509 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
510 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
511 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
512
513 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
514 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
515};
516
517static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
548 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
549 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
550 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
551 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
552 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
553 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
554 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
555 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
556};
557
558static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
559 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
560 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
561 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
562 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
563};
564
565static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
566 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
567 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
568 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
569 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
570 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
571 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
572 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
573 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
574 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
575 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
576 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
577 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
578 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
579 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
580 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
581 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
582 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
583};
584
585static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
586 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
588 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
591 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
609 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
610 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
611 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
612 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
613 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
614 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
615 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
616 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
617 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
618 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
619 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
620 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
621 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
622 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
623 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
624};
625
626static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
627 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
628 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
629 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
630 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
631 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
632 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
633 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
634 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
635 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
636 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
637 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
638 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
639 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
640 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
641 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
642 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
643 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
644 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
645 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
646 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
647 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
648 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
649 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
650 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
651 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
652 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
653 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
654 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
655 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
656 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
657 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
658 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
659 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
660 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
661 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
662 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
663 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
664 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
665 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
666 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
667};
668
669static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
670 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
671 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
672 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
673 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
674};
675
676static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
677 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
678 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
679 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
680 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
681 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
682 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
683 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
684 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
686 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
687 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
688 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
689 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
690 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
691 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
692 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
693 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
694 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
695 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
696 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
697 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
698 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
699 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
700 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
701 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
702 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
703 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
704 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
705 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
706 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
707 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
708 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
709 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
710 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
711 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
712 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
713};
714
715static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
716 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
717 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
718 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
719 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
720 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
721 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
722 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
723 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
724 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
725 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
726 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
727 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
728 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
729 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
730};
731
732static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = {
733 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
734 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
735};
736
737static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
738 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
739 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
740 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
741 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
742 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
743 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
744};
745
746static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
747 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
748 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
749 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
750 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
751 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
752 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
753 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
754 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
755 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
756 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
757 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
758 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
759 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
760 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
761 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
762 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
763 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
764 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
765 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
766 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
767 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
768 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
769 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
770 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
771 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
772 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
773 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
774 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
775 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
776 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
777 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
778 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
779 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
780 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
781 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
782 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
783};
784
785static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
786 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
787 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
788 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
789 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
790 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
791 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
792 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
793 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
794 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
795 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
796 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
797 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
798 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
799 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
800};
801
802static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = {
803 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
804 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
805};
806
807static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
808 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
809 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
810 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
811 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
812 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
813};
814
815static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
816 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
817 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
818 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
819 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
820 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
821 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
822 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
823 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
824 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
825 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
826 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
827 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
828 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
829 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
830 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
831 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
832 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
833 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
834 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
835 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
836 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
837 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
838 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
839 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
840 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
841 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
842 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
843 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
844 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
845 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
846 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
847 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
848 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
849 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
850 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
851 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
852};
853
854static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
855 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
856 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
857 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
858 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
859 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
860 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
861 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
862};
863
864static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
865 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
866 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
867 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
868 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
869 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
870 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
871 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
872 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
873 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
874 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
875 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
876 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
877 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
878 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
879 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
880 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
881 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
882 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
883 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
884 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
885 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
886 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
887 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
888 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
889 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
890 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
891 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
892 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
893 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
894 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
895 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
896};
897
898static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_serdes_tbl[] = {
899 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x9e),
900 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06),
901 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
902 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
903 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
904 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
905 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x2e),
906 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x82),
907 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82),
908 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
909 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xea),
910 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
911 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
912 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25),
913 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02),
914 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb7),
915 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
916 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb7),
917 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
918 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x9e),
919 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06),
920 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
921 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
922 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
923 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x12),
924 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x34),
925 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
926 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
927 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea),
928 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02),
929 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25),
930 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02),
931 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e),
932 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
933 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31),
934 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01),
935 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a),
936 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
937 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14),
938 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
939 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
940 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
941 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
942 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
943 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
944 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c),
945};
946
947static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_tx_tbl[] = {
948 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
949 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
950 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
951 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
952 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
953 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
954 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
955 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
956 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12),
957 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x21),
958};
959
960static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_rx_tbl[] = {
961 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a),
962 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06),
963 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
964 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
965 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
966 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
967 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99),
968 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
969 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
970 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00),
971 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a),
972 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
973 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54),
974 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
975 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13),
976 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
977 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
978 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
979 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
980 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
981 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
982 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04),
983 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
984 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f),
985 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf),
986 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff),
987 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf),
988 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed),
989 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
990 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
991 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
992 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d),
993 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09),
994 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04),
995 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
996 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c),
997 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10),
998 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14),
999 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
1000};
1001
1002static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_pcs_tbl[] = {
1003 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1004 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),
1005 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),
1006 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),
1007 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),
1008 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0xaa),
1009 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1010 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1011 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a),
1012 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1013 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1014 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
1015 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b),
1016 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10),
1017};
1018
1019static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_pcs_usb_tbl[] = {
1020 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1021 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1022 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
1023 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
1024};
1025
1026static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
1027 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
1028 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
1029 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1030 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1031 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1032 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
1033 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1034};
1035
1036static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
1037 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
1038 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1039 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1040 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1041 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1042 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1043 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1044 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1045 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1046 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1047 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1048 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1049 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1050 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1051 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1052 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1053 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1054 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1055 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
1056 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1057 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1058 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1059 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1060 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1061 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1062 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1063 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1064 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1065 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1066 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1067 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1068};
1069
1070static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
1071 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1072 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1073 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1074 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1075 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1076 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1077 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1078 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1079 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1080 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1081 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1082 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1083 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1084 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1085};
1086
1087static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = {
1088 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1089 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1090};
1091
1092static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
1093 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
1094 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
1095 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
1096 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
1097 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
1098 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
1099 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
1100 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
1101 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
1102 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
1103 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
1104 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
1105 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
1106 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
1107 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
1108 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
1109 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
1110 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1111 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
1112 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
1113 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
1114 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
1115 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
1116 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
1117 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
1118 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
1119 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
1120 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
1121 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
1122 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
1123 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
1124 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
1125 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
1126 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
1127 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
1128 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
1129 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
1130 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
1131};
1132
1133static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
1134 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1135 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1136 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
1137 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
1138 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
1139};
1140
1141static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
1142 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1143 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
1144 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1145 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1146 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
1147 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
1148 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1149 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
1150 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1151 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1152 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1153 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1154 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
1155 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1156 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
1157 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1158 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
1159};
1160
1161static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
1162 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1163 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
1164 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
1165 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1166 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1167 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1168 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1169 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
1170 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1171 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1172 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1173 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1174 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1175 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1176 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1177 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1178 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1179 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1180 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1181 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1182 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
1183};
1184
1185static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = {
1186 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
1187 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1188 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
1189 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1190 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab),
1191 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea),
1192 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02),
1193 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1194 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1195 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1196 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1197 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1198 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
1199 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),
1200 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),
1201 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),
1202 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),
1203 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02),
1204 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24),
1205 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
1206 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82),
1207 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
1208 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea),
1209 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
1210 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),
1211 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),
1212 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1213 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1214 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1215 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1216 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1217 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1218 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1219 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1220 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1221 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1222 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1223 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1224 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1225};
1226
1227static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = {
1228 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
1229 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
1230 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1231 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1232 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1233 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
1234 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1235};
1236
1237static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = {
1238 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
1239 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1240 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1241 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1242 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1243 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1244 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1245 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1246 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1247 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1248 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1249 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1250 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1251 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1252 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1253 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1254 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1255 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1256 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x0a),
1257 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1258 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1259 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1260 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1261 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1262 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1263 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1264 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1265 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1266 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1267 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1268 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1269};
1270
1271static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = {
1272 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1273 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),
1274 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1275 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1276 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1277 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1278 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1279 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1280 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1281 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1282 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1283 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1284 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1285 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1286};
1287
1288static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_usb_tbl[] = {
1289 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1290 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1291};
1292
1293static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_tbl[] = {
1294 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1295 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x89),
1296 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1297 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1298 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1299 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1300 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1301 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1302 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1303 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1304 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1305 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1306 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1307 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1308};
1309
1310static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_usb_tbl[] = {
1311 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1312 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1313 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1, 0x6f),
1314};
1315
1316static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_serdes_tbl[] = {
1317 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
1318 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1, 0x01),
1319 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE1, 0x02),
1320 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE1, 0x16),
1321 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE1, 0x36),
1322 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORECLK_DIV_MODE1, 0x04),
1323 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE1, 0x16),
1324 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE1, 0x41),
1325 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE1, 0x41),
1326 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE1, 0x55),
1327 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE1, 0x75),
1328 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE1, 0x01),
1329 QMP_PHY_INIT_CFG(QSERDES_V7_COM_HSCLK_SEL_1, 0x01),
1330 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE1_MODE1, 0x25),
1331 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE2_MODE1, 0x02),
1332 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
1333 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
1334 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
1335 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
1336 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
1337 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1338 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE0, 0x02),
1339 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE0, 0x16),
1340 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE0, 0x36),
1341 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE0, 0x08),
1342 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE0, 0x1a),
1343 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE0, 0x41),
1344 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE0, 0x55),
1345 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE0, 0x75),
1346 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE0, 0x01),
1347 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE1_MODE0, 0x25),
1348 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE2_MODE0, 0x02),
1349 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BG_TIMER, 0x0a),
1350 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_EN_CENTER, 0x01),
1351 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER1, 0x62),
1352 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER2, 0x02),
1353 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_BUF_ENABLE, 0x0a),
1354 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_EN_SEL, 0x1a),
1355 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP_CFG, 0x14),
1356 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE_MAP, 0x04),
1357 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORE_CLK_EN, 0x20),
1358 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CMN_CONFIG_1, 0x16),
1359 QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
1360 QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
1361 QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
1362 QMP_PHY_INIT_CFG(QSERDES_V7_COM_ADDITIONAL_MISC, 0x0c),
1363};
1364
1365static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_tx_tbl[] = {
1366 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_TX, 0x00),
1367 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_RX, 0x00),
1368 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1369 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
1370 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_1, 0xf5),
1371 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_3, 0x3f),
1372 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_4, 0x3f),
1373 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_5, 0x5f),
1374 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RCV_DETECT_LVL_2, 0x12),
1375 QMP_PHY_INIT_CFG(QSERDES_V7_TX_PI_QEC_CTRL, 0x21),
1376};
1377
1378static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_rx_tbl[] = {
1379 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FO_GAIN, 0x0a),
1380 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_GAIN, 0x06),
1381 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1382 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1383 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1384 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1385 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_PI_CONTROLS, 0x99),
1386 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH1, 0x08),
1387 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH2, 0x08),
1388 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_GAIN1, 0x00),
1389 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_GAIN2, 0x0a),
1390 QMP_PHY_INIT_CFG(QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1391 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL1, 0x54),
1392 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL2, 0x0f),
1393 QMP_PHY_INIT_CFG(QSERDES_V7_RX_GM_CAL, 0x13),
1394 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1395 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1396 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1397 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW, 0x07),
1398 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1399 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1400 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CNTRL, 0x04),
1401 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1402 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_LOW, 0x3f),
1403 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH, 0xbf),
1404 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH2, 0xff),
1405 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH3, 0xdf),
1406 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH4, 0xed),
1407 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_LOW, 0xdc),
1408 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH, 0x5c),
1409 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH2, 0x9c),
1410 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH3, 0x1d),
1411 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH4, 0x09),
1412 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_EN_TIMER, 0x04),
1413 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1414 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DCC_CTRL1, 0x0c),
1415 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VTH_CODE, 0x10),
1416 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_CTRL1, 0x14),
1417 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_TRIM, 0x08),
1418};
1419
1420static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_pcs_tbl[] = {
1421 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1422 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG2, 0x89),
1423 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG3, 0x20),
1424 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG6, 0x13),
1425 QMP_PHY_INIT_CFG(QPHY_V7_PCS_REFGEN_REQ_CONFIG1, 0x21),
1426 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RX_SIGDET_LVL, 0xaa),
1427 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1428 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1429 QMP_PHY_INIT_CFG(QPHY_V7_PCS_CDR_RESET_TIME, 0x0a),
1430 QMP_PHY_INIT_CFG(QPHY_V7_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1431 QMP_PHY_INIT_CFG(QPHY_V7_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1432 QMP_PHY_INIT_CFG(QPHY_V7_PCS_PCS_TX_RX_CONFIG, 0x0c),
1433 QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG1, 0x4b),
1434 QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG5, 0x10),
1435};
1436
1437static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_pcs_usb_tbl[] = {
1438 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1439 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1440 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
1441 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
1442};
1443
1444struct qmp_usb_offsets {
1445 u16 serdes;
1446 u16 pcs;
1447 u16 pcs_misc;
1448 u16 pcs_usb;
1449 u16 tx;
1450 u16 rx;
1451 /* for PHYs with >= 2 lanes */
1452 u16 tx2;
1453 u16 rx2;
1454};
1455
1456/* struct qmp_phy_cfg - per-PHY initialization config */
1457struct qmp_phy_cfg {
1458 int lanes;
1459
1460 const struct qmp_usb_offsets *offsets;
1461
1462 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1463 const struct qmp_phy_init_tbl *serdes_tbl;
1464 int serdes_tbl_num;
1465 const struct qmp_phy_init_tbl *tx_tbl;
1466 int tx_tbl_num;
1467 const struct qmp_phy_init_tbl *rx_tbl;
1468 int rx_tbl_num;
1469 const struct qmp_phy_init_tbl *pcs_tbl;
1470 int pcs_tbl_num;
1471 const struct qmp_phy_init_tbl *pcs_usb_tbl;
1472 int pcs_usb_tbl_num;
1473
1474 /* regulators to be requested */
1475 const char * const *vreg_list;
1476 int num_vregs;
1477
1478 /* array of registers with different offsets */
1479 const unsigned int *regs;
1480
1481 /* true, if PHY needs delay after POWER_DOWN */
1482 bool has_pwrdn_delay;
1483
1484 /* Offset from PCS to PCS_USB region */
1485 unsigned int pcs_usb_offset;
1486};
1487
1488struct qmp_usb {
1489 struct device *dev;
1490
1491 const struct qmp_phy_cfg *cfg;
1492
1493 void __iomem *serdes;
1494 void __iomem *pcs;
1495 void __iomem *pcs_misc;
1496 void __iomem *pcs_usb;
1497 void __iomem *tx;
1498 void __iomem *rx;
1499 void __iomem *tx2;
1500 void __iomem *rx2;
1501
1502 struct clk *pipe_clk;
1503 struct clk_bulk_data *clks;
1504 int num_clks;
1505 int num_resets;
1506 struct reset_control_bulk_data *resets;
1507 struct regulator_bulk_data *vregs;
1508
1509 enum phy_mode mode;
1510
1511 struct phy *phy;
1512
1513 struct clk_fixed_rate pipe_clk_fixed;
1514};
1515
1516static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1517{
1518 u32 reg;
1519
1520 reg = readl(base + offset);
1521 reg |= val;
1522 writel(reg, base + offset);
1523
1524 /* ensure that above write is through */
1525 readl(base + offset);
1526}
1527
1528static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1529{
1530 u32 reg;
1531
1532 reg = readl(base + offset);
1533 reg &= ~val;
1534 writel(reg, base + offset);
1535
1536 /* ensure that above write is through */
1537 readl(base + offset);
1538}
1539
1540/* list of clocks required by phy */
1541static const char * const qmp_usb_phy_clk_l[] = {
1542 "aux", "cfg_ahb", "ref", "com_aux",
1543};
1544
1545/* list of resets */
1546static const char * const usb3phy_legacy_reset_l[] = {
1547 "phy", "common",
1548};
1549
1550static const char * const usb3phy_reset_l[] = {
1551 "phy_phy", "phy",
1552};
1553
1554/* list of regulators */
1555static const char * const qmp_phy_vreg_l[] = {
1556 "vdda-phy", "vdda-pll",
1557};
1558
1559static const struct qmp_usb_offsets qmp_usb_offsets_v3 = {
1560 .serdes = 0,
1561 .pcs = 0x800,
1562 .pcs_misc = 0x600,
1563 .tx = 0x200,
1564 .rx = 0x400,
1565};
1566
1567static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
1568 .serdes = 0,
1569 .pcs = 0x800,
1570 .pcs_usb = 0x800,
1571 .tx = 0x200,
1572 .rx = 0x400,
1573};
1574
1575static const struct qmp_usb_offsets qmp_usb_offsets_v3_msm8996 = {
1576 .serdes = 0,
1577 .pcs = 0x600,
1578 .tx = 0x200,
1579 .rx = 0x400,
1580};
1581
1582static const struct qmp_usb_offsets qmp_usb_offsets_v3_qcm2290 = {
1583 .serdes = 0x0,
1584 .pcs = 0xc00,
1585 .pcs_misc = 0xa00,
1586 .tx = 0x200,
1587 .rx = 0x400,
1588 .tx2 = 0x600,
1589 .rx2 = 0x800,
1590};
1591
1592static const struct qmp_usb_offsets qmp_usb_offsets_v4 = {
1593 .serdes = 0,
1594 .pcs = 0x0800,
1595 .pcs_usb = 0x0e00,
1596 .tx = 0x0200,
1597 .rx = 0x0400,
1598};
1599
1600static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
1601 .serdes = 0,
1602 .pcs = 0x0200,
1603 .pcs_usb = 0x1200,
1604 .tx = 0x0e00,
1605 .rx = 0x1000,
1606};
1607
1608static const struct qmp_usb_offsets qmp_usb_offsets_v6 = {
1609 .serdes = 0,
1610 .pcs = 0x0200,
1611 .pcs_usb = 0x1200,
1612 .tx = 0x0e00,
1613 .rx = 0x1000,
1614};
1615
1616static const struct qmp_usb_offsets qmp_usb_offsets_v7 = {
1617 .serdes = 0,
1618 .pcs = 0x0200,
1619 .pcs_usb = 0x1200,
1620 .tx = 0x0e00,
1621 .rx = 0x1000,
1622};
1623
1624static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = {
1625 .lanes = 1,
1626
1627 .offsets = &qmp_usb_offsets_v3,
1628
1629 .serdes_tbl = ipq9574_usb3_serdes_tbl,
1630 .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
1631 .tx_tbl = msm8996_usb3_tx_tbl,
1632 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1633 .rx_tbl = ipq8074_usb3_rx_tbl,
1634 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
1635 .pcs_tbl = ipq8074_usb3_pcs_tbl,
1636 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
1637 .vreg_list = qmp_phy_vreg_l,
1638 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1639 .regs = qmp_v3_usb3phy_regs_layout,
1640};
1641
1642static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
1643 .lanes = 1,
1644
1645 .offsets = &qmp_usb_offsets_v3,
1646
1647 .serdes_tbl = ipq8074_usb3_serdes_tbl,
1648 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
1649 .tx_tbl = msm8996_usb3_tx_tbl,
1650 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1651 .rx_tbl = ipq8074_usb3_rx_tbl,
1652 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
1653 .pcs_tbl = ipq8074_usb3_pcs_tbl,
1654 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
1655 .vreg_list = qmp_phy_vreg_l,
1656 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1657 .regs = qmp_v3_usb3phy_regs_layout,
1658};
1659
1660static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
1661 .lanes = 1,
1662
1663 .offsets = &qmp_usb_offsets_ipq9574,
1664
1665 .serdes_tbl = ipq9574_usb3_serdes_tbl,
1666 .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
1667 .tx_tbl = ipq9574_usb3_tx_tbl,
1668 .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
1669 .rx_tbl = ipq9574_usb3_rx_tbl,
1670 .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
1671 .pcs_tbl = ipq9574_usb3_pcs_tbl,
1672 .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
1673 .vreg_list = qmp_phy_vreg_l,
1674 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1675 .regs = qmp_v3_usb3phy_regs_layout,
1676};
1677
1678static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
1679 .lanes = 1,
1680
1681 .offsets = &qmp_usb_offsets_v3_msm8996,
1682
1683 .serdes_tbl = msm8996_usb3_serdes_tbl,
1684 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1685 .tx_tbl = msm8996_usb3_tx_tbl,
1686 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1687 .rx_tbl = msm8996_usb3_rx_tbl,
1688 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
1689 .pcs_tbl = msm8996_usb3_pcs_tbl,
1690 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
1691 .vreg_list = qmp_phy_vreg_l,
1692 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1693 .regs = qmp_v2_usb3phy_regs_layout,
1694};
1695
1696static const struct qmp_phy_cfg sa8775p_usb3_uniphy_cfg = {
1697 .lanes = 1,
1698
1699 .offsets = &qmp_usb_offsets_v5,
1700
1701 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl,
1702 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1703 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl,
1704 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1705 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl,
1706 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1707 .pcs_tbl = sa8775p_usb3_uniphy_pcs_tbl,
1708 .pcs_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_tbl),
1709 .pcs_usb_tbl = sa8775p_usb3_uniphy_pcs_usb_tbl,
1710 .pcs_usb_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_usb_tbl),
1711 .vreg_list = qmp_phy_vreg_l,
1712 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1713 .regs = qmp_v5_usb3phy_regs_layout,
1714};
1715
1716static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = {
1717 .lanes = 1,
1718
1719 .offsets = &qmp_usb_offsets_v5,
1720
1721 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl,
1722 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1723 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl,
1724 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1725 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl,
1726 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1727 .pcs_tbl = sc8280xp_usb3_uniphy_pcs_tbl,
1728 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl),
1729 .pcs_usb_tbl = sc8280xp_usb3_uniphy_pcs_usb_tbl,
1730 .pcs_usb_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_usb_tbl),
1731 .vreg_list = qmp_phy_vreg_l,
1732 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1733 .regs = qmp_v5_usb3phy_regs_layout,
1734};
1735
1736static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
1737 .lanes = 1,
1738
1739 .offsets = &qmp_usb_offsets_v3,
1740
1741 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
1742 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1743 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
1744 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1745 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
1746 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1747 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
1748 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
1749 .vreg_list = qmp_phy_vreg_l,
1750 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1751 .regs = qmp_v3_usb3phy_regs_layout,
1752
1753 .has_pwrdn_delay = true,
1754};
1755
1756static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
1757 .lanes = 2,
1758
1759 .offsets = &qmp_usb_offsets_v3_qcm2290,
1760
1761 .serdes_tbl = msm8998_usb3_serdes_tbl,
1762 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
1763 .tx_tbl = msm8998_usb3_tx_tbl,
1764 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
1765 .rx_tbl = msm8998_usb3_rx_tbl,
1766 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
1767 .pcs_tbl = msm8998_usb3_pcs_tbl,
1768 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
1769 .vreg_list = qmp_phy_vreg_l,
1770 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1771 .regs = qmp_v3_usb3phy_regs_layout,
1772};
1773
1774static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
1775 .lanes = 1,
1776
1777 .offsets = &qmp_usb_offsets_v4,
1778
1779 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1780 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1781 .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
1782 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
1783 .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
1784 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
1785 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
1786 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
1787 .pcs_usb_tbl = sm8150_usb3_uniphy_pcs_usb_tbl,
1788 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl),
1789 .vreg_list = qmp_phy_vreg_l,
1790 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1791 .regs = qmp_v4_usb3phy_regs_layout,
1792 .pcs_usb_offset = 0x600,
1793
1794 .has_pwrdn_delay = true,
1795};
1796
1797static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
1798 .lanes = 1,
1799
1800 .offsets = &qmp_usb_offsets_v4,
1801
1802 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1803 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1804 .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
1805 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
1806 .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
1807 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
1808 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
1809 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
1810 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,
1811 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
1812 .vreg_list = qmp_phy_vreg_l,
1813 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1814 .regs = qmp_v4_usb3phy_regs_layout,
1815 .pcs_usb_offset = 0x600,
1816
1817 .has_pwrdn_delay = true,
1818};
1819
1820static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
1821 .lanes = 1,
1822
1823 .offsets = &qmp_usb_offsets_v4,
1824
1825 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1826 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1827 .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
1828 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
1829 .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
1830 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
1831 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
1832 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
1833 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,
1834 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
1835 .vreg_list = qmp_phy_vreg_l,
1836 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1837 .regs = qmp_v4_usb3phy_regs_layout,
1838 .pcs_usb_offset = 0x600,
1839
1840 .has_pwrdn_delay = true,
1841};
1842
1843static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
1844 .lanes = 1,
1845
1846 .offsets = &qmp_usb_offsets_v5,
1847
1848 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1849 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1850 .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
1851 .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
1852 .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
1853 .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
1854 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
1855 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
1856 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,
1857 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
1858 .vreg_list = qmp_phy_vreg_l,
1859 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1860 .regs = qmp_v5_usb3phy_regs_layout,
1861 .pcs_usb_offset = 0x1000,
1862
1863 .has_pwrdn_delay = true,
1864};
1865
1866static const struct qmp_phy_cfg sdx75_usb3_uniphy_cfg = {
1867 .lanes = 1,
1868 .offsets = &qmp_usb_offsets_v6,
1869
1870 .serdes_tbl = sdx75_usb3_uniphy_serdes_tbl,
1871 .serdes_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_serdes_tbl),
1872 .tx_tbl = sdx75_usb3_uniphy_tx_tbl,
1873 .tx_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_tx_tbl),
1874 .rx_tbl = sdx75_usb3_uniphy_rx_tbl,
1875 .rx_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_rx_tbl),
1876 .pcs_tbl = sdx75_usb3_uniphy_pcs_tbl,
1877 .pcs_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_tbl),
1878 .pcs_usb_tbl = sdx75_usb3_uniphy_pcs_usb_tbl,
1879 .pcs_usb_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_usb_tbl),
1880 .vreg_list = qmp_phy_vreg_l,
1881 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1882 .regs = qmp_v6_usb3phy_regs_layout,
1883 .pcs_usb_offset = 0x1000,
1884
1885 .has_pwrdn_delay = true,
1886};
1887
1888static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
1889 .lanes = 1,
1890
1891 .offsets = &qmp_usb_offsets_v5,
1892
1893 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1894 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1895 .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
1896 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
1897 .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
1898 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
1899 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
1900 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
1901 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,
1902 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
1903 .vreg_list = qmp_phy_vreg_l,
1904 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1905 .regs = qmp_v5_usb3phy_regs_layout,
1906 .pcs_usb_offset = 0x1000,
1907
1908 .has_pwrdn_delay = true,
1909};
1910
1911static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
1912 .lanes = 2,
1913
1914 .offsets = &qmp_usb_offsets_v3_qcm2290,
1915
1916 .serdes_tbl = qcm2290_usb3_serdes_tbl,
1917 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
1918 .tx_tbl = qcm2290_usb3_tx_tbl,
1919 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
1920 .rx_tbl = qcm2290_usb3_rx_tbl,
1921 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
1922 .pcs_tbl = qcm2290_usb3_pcs_tbl,
1923 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
1924 .vreg_list = qmp_phy_vreg_l,
1925 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1926 .regs = qmp_v3_usb3phy_regs_layout_qcm2290,
1927};
1928
1929static const struct qmp_phy_cfg x1e80100_usb3_uniphy_cfg = {
1930 .lanes = 1,
1931
1932 .offsets = &qmp_usb_offsets_v7,
1933
1934 .serdes_tbl = x1e80100_usb3_uniphy_serdes_tbl,
1935 .serdes_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_serdes_tbl),
1936 .tx_tbl = x1e80100_usb3_uniphy_tx_tbl,
1937 .tx_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_tx_tbl),
1938 .rx_tbl = x1e80100_usb3_uniphy_rx_tbl,
1939 .rx_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_rx_tbl),
1940 .pcs_tbl = x1e80100_usb3_uniphy_pcs_tbl,
1941 .pcs_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_pcs_tbl),
1942 .pcs_usb_tbl = x1e80100_usb3_uniphy_pcs_usb_tbl,
1943 .pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_pcs_usb_tbl),
1944 .vreg_list = qmp_phy_vreg_l,
1945 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1946 .regs = qmp_v7_usb3phy_regs_layout,
1947};
1948
1949static void qmp_usb_configure_lane(void __iomem *base,
1950 const struct qmp_phy_init_tbl tbl[],
1951 int num,
1952 u8 lane_mask)
1953{
1954 int i;
1955 const struct qmp_phy_init_tbl *t = tbl;
1956
1957 if (!t)
1958 return;
1959
1960 for (i = 0; i < num; i++, t++) {
1961 if (!(t->lane_mask & lane_mask))
1962 continue;
1963
1964 writel(t->val, base + t->offset);
1965 }
1966}
1967
1968static void qmp_usb_configure(void __iomem *base,
1969 const struct qmp_phy_init_tbl tbl[],
1970 int num)
1971{
1972 qmp_usb_configure_lane(base, tbl, num, 0xff);
1973}
1974
1975static int qmp_usb_serdes_init(struct qmp_usb *qmp)
1976{
1977 const struct qmp_phy_cfg *cfg = qmp->cfg;
1978 void __iomem *serdes = qmp->serdes;
1979 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
1980 int serdes_tbl_num = cfg->serdes_tbl_num;
1981
1982 qmp_usb_configure(serdes, serdes_tbl, serdes_tbl_num);
1983
1984 return 0;
1985}
1986
1987static int qmp_usb_init(struct phy *phy)
1988{
1989 struct qmp_usb *qmp = phy_get_drvdata(phy);
1990 const struct qmp_phy_cfg *cfg = qmp->cfg;
1991 void __iomem *pcs = qmp->pcs;
1992 int ret;
1993
1994 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1995 if (ret) {
1996 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1997 return ret;
1998 }
1999
2000 ret = reset_control_bulk_assert(qmp->num_resets, qmp->resets);
2001 if (ret) {
2002 dev_err(qmp->dev, "reset assert failed\n");
2003 goto err_disable_regulators;
2004 }
2005
2006 ret = reset_control_bulk_deassert(qmp->num_resets, qmp->resets);
2007 if (ret) {
2008 dev_err(qmp->dev, "reset deassert failed\n");
2009 goto err_disable_regulators;
2010 }
2011
2012 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
2013 if (ret)
2014 goto err_assert_reset;
2015
2016 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
2017
2018 return 0;
2019
2020err_assert_reset:
2021 reset_control_bulk_assert(qmp->num_resets, qmp->resets);
2022err_disable_regulators:
2023 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2024
2025 return ret;
2026}
2027
2028static int qmp_usb_exit(struct phy *phy)
2029{
2030 struct qmp_usb *qmp = phy_get_drvdata(phy);
2031 const struct qmp_phy_cfg *cfg = qmp->cfg;
2032
2033 reset_control_bulk_assert(qmp->num_resets, qmp->resets);
2034
2035 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
2036
2037 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2038
2039 return 0;
2040}
2041
2042static int qmp_usb_power_on(struct phy *phy)
2043{
2044 struct qmp_usb *qmp = phy_get_drvdata(phy);
2045 const struct qmp_phy_cfg *cfg = qmp->cfg;
2046 void __iomem *tx = qmp->tx;
2047 void __iomem *rx = qmp->rx;
2048 void __iomem *pcs = qmp->pcs;
2049 void __iomem *pcs_usb = qmp->pcs_usb;
2050 void __iomem *status;
2051 unsigned int val;
2052 int ret;
2053
2054 qmp_usb_serdes_init(qmp);
2055
2056 ret = clk_prepare_enable(qmp->pipe_clk);
2057 if (ret) {
2058 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
2059 return ret;
2060 }
2061
2062 /* Tx, Rx, and PCS configurations */
2063 qmp_usb_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
2064 qmp_usb_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
2065
2066 if (cfg->lanes >= 2) {
2067 qmp_usb_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
2068 qmp_usb_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
2069 }
2070
2071 qmp_usb_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
2072
2073 if (pcs_usb)
2074 qmp_usb_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num);
2075
2076 if (cfg->has_pwrdn_delay)
2077 usleep_range(10, 20);
2078
2079 /* Pull PHY out of reset state */
2080 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2081
2082 /* start SerDes and Phy-Coding-Sublayer */
2083 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
2084
2085 status = pcs + cfg->regs[QPHY_PCS_STATUS];
2086 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
2087 PHY_INIT_COMPLETE_TIMEOUT);
2088 if (ret) {
2089 dev_err(qmp->dev, "phy initialization timed-out\n");
2090 goto err_disable_pipe_clk;
2091 }
2092
2093 return 0;
2094
2095err_disable_pipe_clk:
2096 clk_disable_unprepare(qmp->pipe_clk);
2097
2098 return ret;
2099}
2100
2101static int qmp_usb_power_off(struct phy *phy)
2102{
2103 struct qmp_usb *qmp = phy_get_drvdata(phy);
2104 const struct qmp_phy_cfg *cfg = qmp->cfg;
2105
2106 clk_disable_unprepare(qmp->pipe_clk);
2107
2108 /* PHY reset */
2109 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2110
2111 /* stop SerDes and Phy-Coding-Sublayer */
2112 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
2113 SERDES_START | PCS_START);
2114
2115 /* Put PHY into POWER DOWN state: active low */
2116 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2117 SW_PWRDN);
2118
2119 return 0;
2120}
2121
2122static int qmp_usb_enable(struct phy *phy)
2123{
2124 int ret;
2125
2126 ret = qmp_usb_init(phy);
2127 if (ret)
2128 return ret;
2129
2130 ret = qmp_usb_power_on(phy);
2131 if (ret)
2132 qmp_usb_exit(phy);
2133
2134 return ret;
2135}
2136
2137static int qmp_usb_disable(struct phy *phy)
2138{
2139 int ret;
2140
2141 ret = qmp_usb_power_off(phy);
2142 if (ret)
2143 return ret;
2144 return qmp_usb_exit(phy);
2145}
2146
2147static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
2148{
2149 struct qmp_usb *qmp = phy_get_drvdata(phy);
2150
2151 qmp->mode = mode;
2152
2153 return 0;
2154}
2155
2156static const struct phy_ops qmp_usb_phy_ops = {
2157 .init = qmp_usb_enable,
2158 .exit = qmp_usb_disable,
2159 .set_mode = qmp_usb_set_mode,
2160 .owner = THIS_MODULE,
2161};
2162
2163static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp)
2164{
2165 const struct qmp_phy_cfg *cfg = qmp->cfg;
2166 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
2167 void __iomem *pcs_misc = qmp->pcs_misc;
2168 u32 intr_mask;
2169
2170 if (qmp->mode == PHY_MODE_USB_HOST_SS ||
2171 qmp->mode == PHY_MODE_USB_DEVICE_SS)
2172 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
2173 else
2174 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
2175
2176 /* Clear any pending interrupts status */
2177 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2178 /* Writing 1 followed by 0 clears the interrupt */
2179 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2180
2181 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2182 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
2183
2184 /* Enable required PHY autonomous mode interrupts */
2185 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
2186
2187 /* Enable i/o clamp_n for autonomous mode */
2188 if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE])
2189 qphy_clrbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN);
2190}
2191
2192static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp)
2193{
2194 const struct qmp_phy_cfg *cfg = qmp->cfg;
2195 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
2196 void __iomem *pcs_misc = qmp->pcs_misc;
2197
2198 /* Disable i/o clamp_n on resume for normal mode */
2199 if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE])
2200 qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN);
2201
2202 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2203 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
2204
2205 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2206 /* Writing 1 followed by 0 clears the interrupt */
2207 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2208}
2209
2210static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev)
2211{
2212 struct qmp_usb *qmp = dev_get_drvdata(dev);
2213
2214 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
2215
2216 if (!qmp->phy->init_count) {
2217 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2218 return 0;
2219 }
2220
2221 qmp_usb_enable_autonomous_mode(qmp);
2222
2223 clk_disable_unprepare(qmp->pipe_clk);
2224 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
2225
2226 return 0;
2227}
2228
2229static int __maybe_unused qmp_usb_runtime_resume(struct device *dev)
2230{
2231 struct qmp_usb *qmp = dev_get_drvdata(dev);
2232 int ret = 0;
2233
2234 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
2235
2236 if (!qmp->phy->init_count) {
2237 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2238 return 0;
2239 }
2240
2241 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
2242 if (ret)
2243 return ret;
2244
2245 ret = clk_prepare_enable(qmp->pipe_clk);
2246 if (ret) {
2247 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
2248 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
2249 return ret;
2250 }
2251
2252 qmp_usb_disable_autonomous_mode(qmp);
2253
2254 return 0;
2255}
2256
2257static const struct dev_pm_ops qmp_usb_pm_ops = {
2258 SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend,
2259 qmp_usb_runtime_resume, NULL)
2260};
2261
2262static int qmp_usb_vreg_init(struct qmp_usb *qmp)
2263{
2264 const struct qmp_phy_cfg *cfg = qmp->cfg;
2265 struct device *dev = qmp->dev;
2266 int num = cfg->num_vregs;
2267 int i;
2268
2269 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
2270 if (!qmp->vregs)
2271 return -ENOMEM;
2272
2273 for (i = 0; i < num; i++)
2274 qmp->vregs[i].supply = cfg->vreg_list[i];
2275
2276 return devm_regulator_bulk_get(dev, num, qmp->vregs);
2277}
2278
2279static int qmp_usb_reset_init(struct qmp_usb *qmp,
2280 const char *const *reset_list,
2281 int num_resets)
2282{
2283 struct device *dev = qmp->dev;
2284 int i;
2285 int ret;
2286
2287 qmp->resets = devm_kcalloc(dev, num_resets,
2288 sizeof(*qmp->resets), GFP_KERNEL);
2289 if (!qmp->resets)
2290 return -ENOMEM;
2291
2292 for (i = 0; i < num_resets; i++)
2293 qmp->resets[i].id = reset_list[i];
2294
2295 qmp->num_resets = num_resets;
2296
2297 ret = devm_reset_control_bulk_get_exclusive(dev, num_resets, qmp->resets);
2298 if (ret)
2299 return dev_err_probe(dev, ret, "failed to get resets\n");
2300
2301 return 0;
2302}
2303
2304static int qmp_usb_clk_init(struct qmp_usb *qmp)
2305{
2306 struct device *dev = qmp->dev;
2307 int num = ARRAY_SIZE(qmp_usb_phy_clk_l);
2308 int i;
2309
2310 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
2311 if (!qmp->clks)
2312 return -ENOMEM;
2313
2314 for (i = 0; i < num; i++)
2315 qmp->clks[i].id = qmp_usb_phy_clk_l[i];
2316
2317 qmp->num_clks = num;
2318
2319 return devm_clk_bulk_get_optional(dev, num, qmp->clks);
2320}
2321
2322static void phy_clk_release_provider(void *res)
2323{
2324 of_clk_del_provider(res);
2325}
2326
2327/*
2328 * Register a fixed rate pipe clock.
2329 *
2330 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
2331 * controls it. The <s>_pipe_clk coming out of the GCC is requested
2332 * by the PHY driver for its operations.
2333 * We register the <s>_pipe_clksrc here. The gcc driver takes care
2334 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
2335 * Below picture shows this relationship.
2336 *
2337 * +---------------+
2338 * | PHY block |<<---------------------------------------+
2339 * | | |
2340 * | +-------+ | +-----+ |
2341 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
2342 * clk | +-------+ | +-----+
2343 * +---------------+
2344 */
2345static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *np)
2346{
2347 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
2348 struct clk_init_data init = { };
2349 int ret;
2350
2351 ret = of_property_read_string(np, "clock-output-names", &init.name);
2352 if (ret) {
2353 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
2354 return ret;
2355 }
2356
2357 init.ops = &clk_fixed_rate_ops;
2358
2359 /* controllers using QMP phys use 125MHz pipe clock interface */
2360 fixed->fixed_rate = 125000000;
2361 fixed->hw.init = &init;
2362
2363 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
2364 if (ret)
2365 return ret;
2366
2367 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
2368 if (ret)
2369 return ret;
2370
2371 /*
2372 * Roll a devm action because the clock provider is the child node, but
2373 * the child node is not actually a device.
2374 */
2375 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
2376}
2377
2378static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np,
2379 int index, bool exclusive)
2380{
2381 struct resource res;
2382
2383 if (!exclusive) {
2384 if (of_address_to_resource(np, index, &res))
2385 return IOMEM_ERR_PTR(-EINVAL);
2386
2387 return devm_ioremap(dev, res.start, resource_size(&res));
2388 }
2389
2390 return devm_of_iomap(dev, np, index, NULL);
2391}
2392
2393static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np)
2394{
2395 struct platform_device *pdev = to_platform_device(qmp->dev);
2396 const struct qmp_phy_cfg *cfg = qmp->cfg;
2397 struct device *dev = qmp->dev;
2398 bool exclusive = true;
2399 int ret;
2400
2401 qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
2402 if (IS_ERR(qmp->serdes))
2403 return PTR_ERR(qmp->serdes);
2404
2405 /*
2406 * FIXME: These bindings should be fixed to not rely on overlapping
2407 * mappings for PCS.
2408 */
2409 if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy"))
2410 exclusive = false;
2411 if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy"))
2412 exclusive = false;
2413
2414 /*
2415 * Get memory resources for the PHY:
2416 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2417 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
2418 * For single lane PHYs: pcs_misc (optional) -> 3.
2419 */
2420 qmp->tx = devm_of_iomap(dev, np, 0, NULL);
2421 if (IS_ERR(qmp->tx))
2422 return PTR_ERR(qmp->tx);
2423
2424 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
2425 if (IS_ERR(qmp->rx))
2426 return PTR_ERR(qmp->rx);
2427
2428 qmp->pcs = qmp_usb_iomap(dev, np, 2, exclusive);
2429 if (IS_ERR(qmp->pcs))
2430 return PTR_ERR(qmp->pcs);
2431
2432 if (cfg->pcs_usb_offset)
2433 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
2434
2435 if (cfg->lanes >= 2) {
2436 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
2437 if (IS_ERR(qmp->tx2))
2438 return PTR_ERR(qmp->tx2);
2439
2440 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
2441 if (IS_ERR(qmp->rx2))
2442 return PTR_ERR(qmp->rx2);
2443
2444 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
2445 } else {
2446 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
2447 }
2448
2449 if (IS_ERR(qmp->pcs_misc)) {
2450 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
2451 qmp->pcs_misc = NULL;
2452 }
2453
2454 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
2455 if (IS_ERR(qmp->pipe_clk)) {
2456 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2457 "failed to get pipe clock\n");
2458 }
2459
2460 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks);
2461 if (ret < 0)
2462 return ret;
2463
2464 qmp->num_clks = ret;
2465
2466 ret = qmp_usb_reset_init(qmp, usb3phy_legacy_reset_l,
2467 ARRAY_SIZE(usb3phy_legacy_reset_l));
2468 if (ret)
2469 return ret;
2470
2471 return 0;
2472}
2473
2474static int qmp_usb_parse_dt(struct qmp_usb *qmp)
2475{
2476 struct platform_device *pdev = to_platform_device(qmp->dev);
2477 const struct qmp_phy_cfg *cfg = qmp->cfg;
2478 const struct qmp_usb_offsets *offs = cfg->offsets;
2479 struct device *dev = qmp->dev;
2480 void __iomem *base;
2481 int ret;
2482
2483 if (!offs)
2484 return -EINVAL;
2485
2486 base = devm_platform_ioremap_resource(pdev, 0);
2487 if (IS_ERR(base))
2488 return PTR_ERR(base);
2489
2490 qmp->serdes = base + offs->serdes;
2491 qmp->pcs = base + offs->pcs;
2492 if (offs->pcs_usb)
2493 qmp->pcs_usb = base + offs->pcs_usb;
2494 if (offs->pcs_misc)
2495 qmp->pcs_misc = base + offs->pcs_misc;
2496 qmp->tx = base + offs->tx;
2497 qmp->rx = base + offs->rx;
2498
2499 if (cfg->lanes >= 2) {
2500 qmp->tx2 = base + offs->tx2;
2501 qmp->rx2 = base + offs->rx2;
2502 }
2503
2504 ret = qmp_usb_clk_init(qmp);
2505 if (ret)
2506 return ret;
2507
2508 qmp->pipe_clk = devm_clk_get(dev, "pipe");
2509 if (IS_ERR(qmp->pipe_clk)) {
2510 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2511 "failed to get pipe clock\n");
2512 }
2513
2514 ret = qmp_usb_reset_init(qmp, usb3phy_reset_l,
2515 ARRAY_SIZE(usb3phy_reset_l));
2516 if (ret)
2517 return ret;
2518
2519 return 0;
2520}
2521
2522static int qmp_usb_probe(struct platform_device *pdev)
2523{
2524 struct device *dev = &pdev->dev;
2525 struct phy_provider *phy_provider;
2526 struct device_node *np;
2527 struct qmp_usb *qmp;
2528 int ret;
2529
2530 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2531 if (!qmp)
2532 return -ENOMEM;
2533
2534 qmp->dev = dev;
2535
2536 qmp->cfg = of_device_get_match_data(dev);
2537 if (!qmp->cfg)
2538 return -EINVAL;
2539
2540 ret = qmp_usb_vreg_init(qmp);
2541 if (ret)
2542 return ret;
2543
2544 /* Check for legacy binding with child node. */
2545 np = of_get_next_available_child(dev->of_node, NULL);
2546 if (np) {
2547 ret = qmp_usb_parse_dt_legacy(qmp, np);
2548 } else {
2549 np = of_node_get(dev->of_node);
2550 ret = qmp_usb_parse_dt(qmp);
2551 }
2552 if (ret)
2553 goto err_node_put;
2554
2555 pm_runtime_set_active(dev);
2556 ret = devm_pm_runtime_enable(dev);
2557 if (ret)
2558 goto err_node_put;
2559 /*
2560 * Prevent runtime pm from being ON by default. Users can enable
2561 * it using power/control in sysfs.
2562 */
2563 pm_runtime_forbid(dev);
2564
2565 ret = phy_pipe_clk_register(qmp, np);
2566 if (ret)
2567 goto err_node_put;
2568
2569 qmp->phy = devm_phy_create(dev, np, &qmp_usb_phy_ops);
2570 if (IS_ERR(qmp->phy)) {
2571 ret = PTR_ERR(qmp->phy);
2572 dev_err(dev, "failed to create PHY: %d\n", ret);
2573 goto err_node_put;
2574 }
2575
2576 phy_set_drvdata(qmp->phy, qmp);
2577
2578 of_node_put(np);
2579
2580 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2581
2582 return PTR_ERR_OR_ZERO(phy_provider);
2583
2584err_node_put:
2585 of_node_put(np);
2586 return ret;
2587}
2588
2589static const struct of_device_id qmp_usb_of_match_table[] = {
2590 {
2591 .compatible = "qcom,ipq6018-qmp-usb3-phy",
2592 .data = &ipq6018_usb3phy_cfg,
2593 }, {
2594 .compatible = "qcom,ipq8074-qmp-usb3-phy",
2595 .data = &ipq8074_usb3phy_cfg,
2596 }, {
2597 .compatible = "qcom,ipq9574-qmp-usb3-phy",
2598 .data = &ipq9574_usb3phy_cfg,
2599 }, {
2600 .compatible = "qcom,msm8996-qmp-usb3-phy",
2601 .data = &msm8996_usb3phy_cfg,
2602 }, {
2603 .compatible = "qcom,msm8998-qmp-usb3-phy",
2604 .data = &msm8998_usb3phy_cfg,
2605 }, {
2606 .compatible = "qcom,qcm2290-qmp-usb3-phy",
2607 .data = &qcm2290_usb3phy_cfg,
2608 }, {
2609 .compatible = "qcom,sa8775p-qmp-usb3-uni-phy",
2610 .data = &sa8775p_usb3_uniphy_cfg,
2611 }, {
2612 .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy",
2613 .data = &sc8280xp_usb3_uniphy_cfg,
2614 }, {
2615 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
2616 .data = &qmp_v3_usb3_uniphy_cfg,
2617 }, {
2618 .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
2619 .data = &sdx55_usb3_uniphy_cfg,
2620 }, {
2621 .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
2622 .data = &sdx65_usb3_uniphy_cfg,
2623 }, {
2624 .compatible = "qcom,sdx75-qmp-usb3-uni-phy",
2625 .data = &sdx75_usb3_uniphy_cfg,
2626 }, {
2627 .compatible = "qcom,sm6115-qmp-usb3-phy",
2628 .data = &qcm2290_usb3phy_cfg,
2629 }, {
2630 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
2631 .data = &sm8150_usb3_uniphy_cfg,
2632 }, {
2633 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
2634 .data = &sm8250_usb3_uniphy_cfg,
2635 }, {
2636 .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
2637 .data = &sm8350_usb3_uniphy_cfg,
2638 }, {
2639 .compatible = "qcom,x1e80100-qmp-usb3-uni-phy",
2640 .data = &x1e80100_usb3_uniphy_cfg,
2641 },
2642 { },
2643};
2644MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table);
2645
2646static struct platform_driver qmp_usb_driver = {
2647 .probe = qmp_usb_probe,
2648 .driver = {
2649 .name = "qcom-qmp-usb-phy",
2650 .pm = &qmp_usb_pm_ops,
2651 .of_match_table = qmp_usb_of_match_table,
2652 },
2653};
2654
2655module_platform_driver(qmp_usb_driver);
2656
2657MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
2658MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");
2659MODULE_LICENSE("GPL v2");