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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Allwinner sun4i USB phy driver
4 *
5 * Copyright (C) 2014-2015 Hans de Goede <hdegoede@redhat.com>
6 *
7 * Based on code from
8 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
9 *
10 * Modelled after: Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY driver
11 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
12 * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
13 */
14
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/err.h>
18#include <linux/extcon-provider.h>
19#include <linux/gpio/consumer.h>
20#include <linux/io.h>
21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/mutex.h>
25#include <linux/of.h>
26#include <linux/of_gpio.h>
27#include <linux/phy/phy.h>
28#include <linux/phy/phy-sun4i-usb.h>
29#include <linux/platform_device.h>
30#include <linux/power_supply.h>
31#include <linux/regulator/consumer.h>
32#include <linux/reset.h>
33#include <linux/spinlock.h>
34#include <linux/usb/of.h>
35#include <linux/workqueue.h>
36
37#define REG_ISCR 0x00
38#define REG_PHYCTL_A10 0x04
39#define REG_PHYBIST 0x08
40#define REG_PHYTUNE 0x0c
41#define REG_PHYCTL_A33 0x10
42#define REG_PHY_OTGCTL 0x20
43
44#define REG_HCI_PHY_CTL 0x10
45
46#define PHYCTL_DATA BIT(7)
47
48#define OTGCTL_ROUTE_MUSB BIT(0)
49
50#define SUNXI_AHB_ICHR8_EN BIT(10)
51#define SUNXI_AHB_INCR4_BURST_EN BIT(9)
52#define SUNXI_AHB_INCRX_ALIGN_EN BIT(8)
53#define SUNXI_ULPI_BYPASS_EN BIT(0)
54
55/* ISCR, Interface Status and Control bits */
56#define ISCR_ID_PULLUP_EN (1 << 17)
57#define ISCR_DPDM_PULLUP_EN (1 << 16)
58/* sunxi has the phy id/vbus pins not connected, so we use the force bits */
59#define ISCR_FORCE_ID_MASK (3 << 14)
60#define ISCR_FORCE_ID_LOW (2 << 14)
61#define ISCR_FORCE_ID_HIGH (3 << 14)
62#define ISCR_FORCE_VBUS_MASK (3 << 12)
63#define ISCR_FORCE_VBUS_LOW (2 << 12)
64#define ISCR_FORCE_VBUS_HIGH (3 << 12)
65
66/* Common Control Bits for Both PHYs */
67#define PHY_PLL_BW 0x03
68#define PHY_RES45_CAL_EN 0x0c
69
70/* Private Control Bits for Each PHY */
71#define PHY_TX_AMPLITUDE_TUNE 0x20
72#define PHY_TX_SLEWRATE_TUNE 0x22
73#define PHY_VBUSVALID_TH_SEL 0x25
74#define PHY_PULLUP_RES_SEL 0x27
75#define PHY_OTG_FUNC_EN 0x28
76#define PHY_VBUS_DET_EN 0x29
77#define PHY_DISCON_TH_SEL 0x2a
78#define PHY_SQUELCH_DETECT 0x3c
79
80/* A83T specific control bits for PHY0 */
81#define PHY_CTL_VBUSVLDEXT BIT(5)
82#define PHY_CTL_SIDDQ BIT(3)
83#define PHY_CTL_H3_SIDDQ BIT(1)
84
85/* A83T specific control bits for PHY2 HSIC */
86#define SUNXI_EHCI_HS_FORCE BIT(20)
87#define SUNXI_HSIC_CONNECT_DET BIT(17)
88#define SUNXI_HSIC_CONNECT_INT BIT(16)
89#define SUNXI_HSIC BIT(1)
90
91#define MAX_PHYS 4
92
93/*
94 * Note do not raise the debounce time, we must report Vusb high within 100ms
95 * otherwise we get Vbus errors
96 */
97#define DEBOUNCE_TIME msecs_to_jiffies(50)
98#define POLL_TIME msecs_to_jiffies(250)
99
100struct sun4i_usb_phy_cfg {
101 int num_phys;
102 int hsic_index;
103 u32 disc_thresh;
104 u32 hci_phy_ctl_clear;
105 u8 phyctl_offset;
106 bool dedicated_clocks;
107 bool phy0_dual_route;
108 bool needs_phy2_siddq;
109 bool siddq_in_base;
110 bool poll_vbusen;
111 int missing_phys;
112};
113
114struct sun4i_usb_phy_data {
115 void __iomem *base;
116 const struct sun4i_usb_phy_cfg *cfg;
117 enum usb_dr_mode dr_mode;
118 spinlock_t reg_lock; /* guard access to phyctl reg */
119 struct sun4i_usb_phy {
120 struct phy *phy;
121 void __iomem *pmu;
122 struct regulator *vbus;
123 struct reset_control *reset;
124 struct clk *clk;
125 struct clk *clk2;
126 bool regulator_on;
127 int index;
128 } phys[MAX_PHYS];
129 /* phy0 / otg related variables */
130 struct extcon_dev *extcon;
131 bool phy0_init;
132 struct gpio_desc *id_det_gpio;
133 struct gpio_desc *vbus_det_gpio;
134 struct power_supply *vbus_power_supply;
135 struct notifier_block vbus_power_nb;
136 bool vbus_power_nb_registered;
137 bool force_session_end;
138 int id_det_irq;
139 int vbus_det_irq;
140 int id_det;
141 int vbus_det;
142 struct delayed_work detect;
143};
144
145#define to_sun4i_usb_phy_data(phy) \
146 container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
147
148static void sun4i_usb_phy0_update_iscr(struct phy *_phy, u32 clr, u32 set)
149{
150 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
151 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
152 u32 iscr;
153
154 iscr = readl(data->base + REG_ISCR);
155 iscr &= ~clr;
156 iscr |= set;
157 writel(iscr, data->base + REG_ISCR);
158}
159
160static void sun4i_usb_phy0_set_id_detect(struct phy *phy, u32 val)
161{
162 if (val)
163 val = ISCR_FORCE_ID_HIGH;
164 else
165 val = ISCR_FORCE_ID_LOW;
166
167 sun4i_usb_phy0_update_iscr(phy, ISCR_FORCE_ID_MASK, val);
168}
169
170static void sun4i_usb_phy0_set_vbus_detect(struct phy *phy, u32 val)
171{
172 if (val)
173 val = ISCR_FORCE_VBUS_HIGH;
174 else
175 val = ISCR_FORCE_VBUS_LOW;
176
177 sun4i_usb_phy0_update_iscr(phy, ISCR_FORCE_VBUS_MASK, val);
178}
179
180static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
181 int len)
182{
183 struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
184 u32 temp, usbc_bit = BIT(phy->index * 2);
185 void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
186 unsigned long flags;
187 int i;
188
189 spin_lock_irqsave(&phy_data->reg_lock, flags);
190
191 if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
192 /* SoCs newer than A33 need us to set phyctl to 0 explicitly */
193 writel(0, phyctl);
194 }
195
196 for (i = 0; i < len; i++) {
197 temp = readl(phyctl);
198
199 /* clear the address portion */
200 temp &= ~(0xff << 8);
201
202 /* set the address */
203 temp |= ((addr + i) << 8);
204 writel(temp, phyctl);
205
206 /* set the data bit and clear usbc bit*/
207 temp = readb(phyctl);
208 if (data & 0x1)
209 temp |= PHYCTL_DATA;
210 else
211 temp &= ~PHYCTL_DATA;
212 temp &= ~usbc_bit;
213 writeb(temp, phyctl);
214
215 /* pulse usbc_bit */
216 temp = readb(phyctl);
217 temp |= usbc_bit;
218 writeb(temp, phyctl);
219
220 temp = readb(phyctl);
221 temp &= ~usbc_bit;
222 writeb(temp, phyctl);
223
224 data >>= 1;
225 }
226
227 spin_unlock_irqrestore(&phy_data->reg_lock, flags);
228}
229
230static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
231{
232 struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
233 u32 bits, reg_value;
234
235 if (!phy->pmu)
236 return;
237
238 bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
239 SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
240
241 /* A83T USB2 is HSIC */
242 if (phy_data->cfg->hsic_index &&
243 phy->index == phy_data->cfg->hsic_index)
244 bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
245 SUNXI_HSIC;
246
247 reg_value = readl(phy->pmu);
248
249 if (enable)
250 reg_value |= bits;
251 else
252 reg_value &= ~bits;
253
254 writel(reg_value, phy->pmu);
255}
256
257static int sun4i_usb_phy_init(struct phy *_phy)
258{
259 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
260 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
261 int ret;
262 u32 val;
263
264 ret = clk_prepare_enable(phy->clk);
265 if (ret)
266 return ret;
267
268 ret = clk_prepare_enable(phy->clk2);
269 if (ret) {
270 clk_disable_unprepare(phy->clk);
271 return ret;
272 }
273
274 ret = reset_control_deassert(phy->reset);
275 if (ret) {
276 clk_disable_unprepare(phy->clk2);
277 clk_disable_unprepare(phy->clk);
278 return ret;
279 }
280
281 /* Some PHYs on some SoCs need the help of PHY2 to work. */
282 if (data->cfg->needs_phy2_siddq && phy->index != 2) {
283 struct sun4i_usb_phy *phy2 = &data->phys[2];
284
285 ret = clk_prepare_enable(phy2->clk);
286 if (ret) {
287 reset_control_assert(phy->reset);
288 clk_disable_unprepare(phy->clk2);
289 clk_disable_unprepare(phy->clk);
290 return ret;
291 }
292
293 ret = reset_control_deassert(phy2->reset);
294 if (ret) {
295 clk_disable_unprepare(phy2->clk);
296 reset_control_assert(phy->reset);
297 clk_disable_unprepare(phy->clk2);
298 clk_disable_unprepare(phy->clk);
299 return ret;
300 }
301
302 /*
303 * This extra clock is just needed to access the
304 * REG_HCI_PHY_CTL PMU register for PHY2.
305 */
306 ret = clk_prepare_enable(phy2->clk2);
307 if (ret) {
308 reset_control_assert(phy2->reset);
309 clk_disable_unprepare(phy2->clk);
310 reset_control_assert(phy->reset);
311 clk_disable_unprepare(phy->clk2);
312 clk_disable_unprepare(phy->clk);
313 return ret;
314 }
315
316 if (phy2->pmu && data->cfg->hci_phy_ctl_clear) {
317 val = readl(phy2->pmu + REG_HCI_PHY_CTL);
318 val &= ~data->cfg->hci_phy_ctl_clear;
319 writel(val, phy2->pmu + REG_HCI_PHY_CTL);
320 }
321
322 clk_disable_unprepare(phy->clk2);
323 }
324
325 if (phy->pmu && data->cfg->hci_phy_ctl_clear) {
326 val = readl(phy->pmu + REG_HCI_PHY_CTL);
327 val &= ~data->cfg->hci_phy_ctl_clear;
328 writel(val, phy->pmu + REG_HCI_PHY_CTL);
329 }
330
331 if (data->cfg->siddq_in_base) {
332 if (phy->index == 0) {
333 val = readl(data->base + data->cfg->phyctl_offset);
334 val |= PHY_CTL_VBUSVLDEXT;
335 val &= ~PHY_CTL_SIDDQ;
336 writel(val, data->base + data->cfg->phyctl_offset);
337 }
338 } else {
339 /* Enable USB 45 Ohm resistor calibration */
340 if (phy->index == 0)
341 sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
342
343 /* Adjust PHY's magnitude and rate */
344 sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
345
346 /* Disconnect threshold adjustment */
347 sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
348 data->cfg->disc_thresh, 2);
349 }
350
351 sun4i_usb_phy_passby(phy, 1);
352
353 if (phy->index == 0) {
354 data->phy0_init = true;
355
356 /* Enable pull-ups */
357 sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_DPDM_PULLUP_EN);
358 sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_ID_PULLUP_EN);
359
360 /* Force ISCR and cable state updates */
361 data->id_det = -1;
362 data->vbus_det = -1;
363 queue_delayed_work(system_wq, &data->detect, 0);
364 }
365
366 return 0;
367}
368
369static int sun4i_usb_phy_exit(struct phy *_phy)
370{
371 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
372 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
373
374 if (phy->index == 0) {
375 if (data->cfg->siddq_in_base) {
376 void __iomem *phyctl = data->base +
377 data->cfg->phyctl_offset;
378
379 writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
380 }
381
382 /* Disable pull-ups */
383 sun4i_usb_phy0_update_iscr(_phy, ISCR_DPDM_PULLUP_EN, 0);
384 sun4i_usb_phy0_update_iscr(_phy, ISCR_ID_PULLUP_EN, 0);
385 data->phy0_init = false;
386 }
387
388 if (data->cfg->needs_phy2_siddq && phy->index != 2) {
389 struct sun4i_usb_phy *phy2 = &data->phys[2];
390
391 clk_disable_unprepare(phy2->clk);
392 reset_control_assert(phy2->reset);
393 }
394
395 sun4i_usb_phy_passby(phy, 0);
396 reset_control_assert(phy->reset);
397 clk_disable_unprepare(phy->clk2);
398 clk_disable_unprepare(phy->clk);
399
400 return 0;
401}
402
403static int sun4i_usb_phy0_get_id_det(struct sun4i_usb_phy_data *data)
404{
405 switch (data->dr_mode) {
406 case USB_DR_MODE_OTG:
407 if (data->id_det_gpio)
408 return gpiod_get_value_cansleep(data->id_det_gpio);
409 else
410 return 1; /* Fallback to peripheral mode */
411 case USB_DR_MODE_HOST:
412 return 0;
413 case USB_DR_MODE_PERIPHERAL:
414 default:
415 return 1;
416 }
417}
418
419static int sun4i_usb_phy0_get_vbus_det(struct sun4i_usb_phy_data *data)
420{
421 if (data->vbus_det_gpio)
422 return gpiod_get_value_cansleep(data->vbus_det_gpio);
423
424 if (data->vbus_power_supply) {
425 union power_supply_propval val;
426 int r;
427
428 r = power_supply_get_property(data->vbus_power_supply,
429 POWER_SUPPLY_PROP_PRESENT, &val);
430 if (r == 0)
431 return val.intval;
432 }
433
434 /* Fallback: report vbus as high */
435 return 1;
436}
437
438static bool sun4i_usb_phy0_have_vbus_det(struct sun4i_usb_phy_data *data)
439{
440 return data->vbus_det_gpio || data->vbus_power_supply;
441}
442
443static bool sun4i_usb_phy0_poll(struct sun4i_usb_phy_data *data)
444{
445 if ((data->id_det_gpio && data->id_det_irq <= 0) ||
446 (data->vbus_det_gpio && data->vbus_det_irq <= 0))
447 return true;
448
449 /*
450 * The A31/A23/A33 companion pmics (AXP221/AXP223) do not
451 * generate vbus change interrupts when the board is driving
452 * vbus using the N_VBUSEN pin on the pmic, so we must poll
453 * when using the pmic for vbus-det _and_ we're driving vbus.
454 */
455 if (data->cfg->poll_vbusen && data->vbus_power_supply &&
456 data->phys[0].regulator_on)
457 return true;
458
459 return false;
460}
461
462static int sun4i_usb_phy_power_on(struct phy *_phy)
463{
464 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
465 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
466 int ret;
467
468 if (!phy->vbus || phy->regulator_on)
469 return 0;
470
471 /* For phy0 only turn on Vbus if we don't have an ext. Vbus */
472 if (phy->index == 0 && sun4i_usb_phy0_have_vbus_det(data) &&
473 data->vbus_det) {
474 dev_warn(&_phy->dev, "External vbus detected, not enabling our own vbus\n");
475 return 0;
476 }
477
478 ret = regulator_enable(phy->vbus);
479 if (ret)
480 return ret;
481
482 phy->regulator_on = true;
483
484 /* We must report Vbus high within OTG_TIME_A_WAIT_VRISE msec. */
485 if (phy->index == 0 && sun4i_usb_phy0_poll(data))
486 mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME);
487
488 return 0;
489}
490
491static int sun4i_usb_phy_power_off(struct phy *_phy)
492{
493 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
494 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
495
496 if (!phy->vbus || !phy->regulator_on)
497 return 0;
498
499 regulator_disable(phy->vbus);
500 phy->regulator_on = false;
501
502 /*
503 * phy0 vbus typically slowly discharges, sometimes this causes the
504 * Vbus gpio to not trigger an edge irq on Vbus off, so force a rescan.
505 */
506 if (phy->index == 0 && !sun4i_usb_phy0_poll(data))
507 mod_delayed_work(system_wq, &data->detect, POLL_TIME);
508
509 return 0;
510}
511
512static int sun4i_usb_phy_set_mode(struct phy *_phy,
513 enum phy_mode mode, int submode)
514{
515 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
516 struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
517 int new_mode;
518
519 if (phy->index != 0) {
520 if (mode == PHY_MODE_USB_HOST)
521 return 0;
522 return -EINVAL;
523 }
524
525 switch (mode) {
526 case PHY_MODE_USB_HOST:
527 new_mode = USB_DR_MODE_HOST;
528 break;
529 case PHY_MODE_USB_DEVICE:
530 new_mode = USB_DR_MODE_PERIPHERAL;
531 break;
532 case PHY_MODE_USB_OTG:
533 new_mode = USB_DR_MODE_OTG;
534 break;
535 default:
536 return -EINVAL;
537 }
538
539 if (new_mode != data->dr_mode) {
540 dev_info(&_phy->dev, "Changing dr_mode to %d\n", new_mode);
541 data->dr_mode = new_mode;
542 }
543
544 data->id_det = -1; /* Force reprocessing of id */
545 data->force_session_end = true;
546 queue_delayed_work(system_wq, &data->detect, 0);
547
548 return 0;
549}
550
551void sun4i_usb_phy_set_squelch_detect(struct phy *_phy, bool enabled)
552{
553 struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
554
555 sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
556}
557EXPORT_SYMBOL_GPL(sun4i_usb_phy_set_squelch_detect);
558
559static const struct phy_ops sun4i_usb_phy_ops = {
560 .init = sun4i_usb_phy_init,
561 .exit = sun4i_usb_phy_exit,
562 .power_on = sun4i_usb_phy_power_on,
563 .power_off = sun4i_usb_phy_power_off,
564 .set_mode = sun4i_usb_phy_set_mode,
565 .owner = THIS_MODULE,
566};
567
568static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, int id_det)
569{
570 u32 regval;
571
572 regval = readl(data->base + REG_PHY_OTGCTL);
573 if (id_det == 0) {
574 /* Host mode. Route phy0 to EHCI/OHCI */
575 regval &= ~OTGCTL_ROUTE_MUSB;
576 } else {
577 /* Peripheral mode. Route phy0 to MUSB */
578 regval |= OTGCTL_ROUTE_MUSB;
579 }
580 writel(regval, data->base + REG_PHY_OTGCTL);
581}
582
583static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
584{
585 struct sun4i_usb_phy_data *data =
586 container_of(work, struct sun4i_usb_phy_data, detect.work);
587 struct phy *phy0 = data->phys[0].phy;
588 struct sun4i_usb_phy *phy;
589 bool force_session_end, id_notify = false, vbus_notify = false;
590 int id_det, vbus_det;
591
592 if (!phy0)
593 return;
594
595 phy = phy_get_drvdata(phy0);
596 id_det = sun4i_usb_phy0_get_id_det(data);
597 vbus_det = sun4i_usb_phy0_get_vbus_det(data);
598
599 mutex_lock(&phy0->mutex);
600
601 if (!data->phy0_init) {
602 mutex_unlock(&phy0->mutex);
603 return;
604 }
605
606 force_session_end = data->force_session_end;
607 data->force_session_end = false;
608
609 if (id_det != data->id_det) {
610 /* id-change, force session end if we've no vbus detection */
611 if (data->dr_mode == USB_DR_MODE_OTG &&
612 !sun4i_usb_phy0_have_vbus_det(data))
613 force_session_end = true;
614
615 /* When entering host mode (id = 0) force end the session now */
616 if (force_session_end && id_det == 0) {
617 sun4i_usb_phy0_set_vbus_detect(phy0, 0);
618 msleep(200);
619 sun4i_usb_phy0_set_vbus_detect(phy0, 1);
620 }
621 sun4i_usb_phy0_set_id_detect(phy0, id_det);
622 data->id_det = id_det;
623 id_notify = true;
624 }
625
626 if (vbus_det != data->vbus_det) {
627 sun4i_usb_phy0_set_vbus_detect(phy0, vbus_det);
628 data->vbus_det = vbus_det;
629 vbus_notify = true;
630 }
631
632 mutex_unlock(&phy0->mutex);
633
634 if (id_notify) {
635 extcon_set_state_sync(data->extcon, EXTCON_USB_HOST,
636 !id_det);
637 /* When leaving host mode force end the session here */
638 if (force_session_end && id_det == 1) {
639 mutex_lock(&phy0->mutex);
640 sun4i_usb_phy0_set_vbus_detect(phy0, 0);
641 msleep(1000);
642 sun4i_usb_phy0_set_vbus_detect(phy0, 1);
643 mutex_unlock(&phy0->mutex);
644 }
645
646 /* Enable PHY0 passby for host mode only. */
647 sun4i_usb_phy_passby(phy, !id_det);
648
649 /* Re-route PHY0 if necessary */
650 if (data->cfg->phy0_dual_route)
651 sun4i_usb_phy0_reroute(data, id_det);
652 }
653
654 if (vbus_notify)
655 extcon_set_state_sync(data->extcon, EXTCON_USB, vbus_det);
656
657 if (sun4i_usb_phy0_poll(data))
658 queue_delayed_work(system_wq, &data->detect, POLL_TIME);
659}
660
661static irqreturn_t sun4i_usb_phy0_id_vbus_det_irq(int irq, void *dev_id)
662{
663 struct sun4i_usb_phy_data *data = dev_id;
664
665 /* vbus or id changed, let the pins settle and then scan them */
666 mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME);
667
668 return IRQ_HANDLED;
669}
670
671static int sun4i_usb_phy0_vbus_notify(struct notifier_block *nb,
672 unsigned long val, void *v)
673{
674 struct sun4i_usb_phy_data *data =
675 container_of(nb, struct sun4i_usb_phy_data, vbus_power_nb);
676 struct power_supply *psy = v;
677
678 /* Properties on the vbus_power_supply changed, scan vbus_det */
679 if (val == PSY_EVENT_PROP_CHANGED && psy == data->vbus_power_supply)
680 mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME);
681
682 return NOTIFY_OK;
683}
684
685static struct phy *sun4i_usb_phy_xlate(struct device *dev,
686 struct of_phandle_args *args)
687{
688 struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
689
690 if (args->args[0] >= data->cfg->num_phys)
691 return ERR_PTR(-ENODEV);
692
693 if (data->cfg->missing_phys & BIT(args->args[0]))
694 return ERR_PTR(-ENODEV);
695
696 return data->phys[args->args[0]].phy;
697}
698
699static void sun4i_usb_phy_remove(struct platform_device *pdev)
700{
701 struct device *dev = &pdev->dev;
702 struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
703
704 if (data->vbus_power_nb_registered)
705 power_supply_unreg_notifier(&data->vbus_power_nb);
706 if (data->id_det_irq > 0)
707 devm_free_irq(dev, data->id_det_irq, data);
708 if (data->vbus_det_irq > 0)
709 devm_free_irq(dev, data->vbus_det_irq, data);
710
711 cancel_delayed_work_sync(&data->detect);
712}
713
714static const unsigned int sun4i_usb_phy0_cable[] = {
715 EXTCON_USB,
716 EXTCON_USB_HOST,
717 EXTCON_NONE,
718};
719
720static int sun4i_usb_phy_probe(struct platform_device *pdev)
721{
722 struct sun4i_usb_phy_data *data;
723 struct device *dev = &pdev->dev;
724 struct device_node *np = dev->of_node;
725 struct phy_provider *phy_provider;
726 int i, ret;
727
728 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
729 if (!data)
730 return -ENOMEM;
731
732 spin_lock_init(&data->reg_lock);
733 INIT_DELAYED_WORK(&data->detect, sun4i_usb_phy0_id_vbus_det_scan);
734 dev_set_drvdata(dev, data);
735 data->cfg = of_device_get_match_data(dev);
736 if (!data->cfg)
737 return -EINVAL;
738
739 data->base = devm_platform_ioremap_resource_byname(pdev, "phy_ctrl");
740 if (IS_ERR(data->base))
741 return PTR_ERR(data->base);
742
743 data->id_det_gpio = devm_gpiod_get_optional(dev, "usb0_id_det",
744 GPIOD_IN);
745 if (IS_ERR(data->id_det_gpio)) {
746 dev_err(dev, "Couldn't request ID GPIO\n");
747 return PTR_ERR(data->id_det_gpio);
748 }
749
750 data->vbus_det_gpio = devm_gpiod_get_optional(dev, "usb0_vbus_det",
751 GPIOD_IN);
752 if (IS_ERR(data->vbus_det_gpio)) {
753 dev_err(dev, "Couldn't request VBUS detect GPIO\n");
754 return PTR_ERR(data->vbus_det_gpio);
755 }
756
757 if (of_property_present(np, "usb0_vbus_power-supply")) {
758 data->vbus_power_supply = devm_power_supply_get_by_phandle(dev,
759 "usb0_vbus_power-supply");
760 if (IS_ERR(data->vbus_power_supply)) {
761 dev_err(dev, "Couldn't get the VBUS power supply\n");
762 return PTR_ERR(data->vbus_power_supply);
763 }
764
765 if (!data->vbus_power_supply)
766 return -EPROBE_DEFER;
767 }
768
769 data->dr_mode = of_usb_get_dr_mode_by_phy(np, 0);
770
771 data->extcon = devm_extcon_dev_allocate(dev, sun4i_usb_phy0_cable);
772 if (IS_ERR(data->extcon)) {
773 dev_err(dev, "Couldn't allocate our extcon device\n");
774 return PTR_ERR(data->extcon);
775 }
776
777 ret = devm_extcon_dev_register(dev, data->extcon);
778 if (ret) {
779 dev_err(dev, "failed to register extcon: %d\n", ret);
780 return ret;
781 }
782
783 for (i = 0; i < data->cfg->num_phys; i++) {
784 struct sun4i_usb_phy *phy = data->phys + i;
785 char name[32];
786
787 if (data->cfg->missing_phys & BIT(i))
788 continue;
789
790 snprintf(name, sizeof(name), "usb%d_vbus", i);
791 phy->vbus = devm_regulator_get_optional(dev, name);
792 if (IS_ERR(phy->vbus)) {
793 if (PTR_ERR(phy->vbus) == -EPROBE_DEFER) {
794 dev_err(dev,
795 "Couldn't get regulator %s... Deferring probe\n",
796 name);
797 return -EPROBE_DEFER;
798 }
799
800 phy->vbus = NULL;
801 }
802
803 if (data->cfg->dedicated_clocks)
804 snprintf(name, sizeof(name), "usb%d_phy", i);
805 else
806 strscpy(name, "usb_phy", sizeof(name));
807
808 phy->clk = devm_clk_get(dev, name);
809 if (IS_ERR(phy->clk)) {
810 dev_err(dev, "failed to get clock %s\n", name);
811 return PTR_ERR(phy->clk);
812 }
813
814 /* The first PHY is always tied to OTG, and never HSIC */
815 if (data->cfg->hsic_index && i == data->cfg->hsic_index) {
816 /* HSIC needs secondary clock */
817 snprintf(name, sizeof(name), "usb%d_hsic_12M", i);
818 phy->clk2 = devm_clk_get(dev, name);
819 if (IS_ERR(phy->clk2)) {
820 dev_err(dev, "failed to get clock %s\n", name);
821 return PTR_ERR(phy->clk2);
822 }
823 } else {
824 snprintf(name, sizeof(name), "pmu%d_clk", i);
825 phy->clk2 = devm_clk_get_optional(dev, name);
826 if (IS_ERR(phy->clk2)) {
827 dev_err(dev, "failed to get clock %s\n", name);
828 return PTR_ERR(phy->clk2);
829 }
830 }
831
832 snprintf(name, sizeof(name), "usb%d_reset", i);
833 phy->reset = devm_reset_control_get(dev, name);
834 if (IS_ERR(phy->reset)) {
835 dev_err(dev, "failed to get reset %s\n", name);
836 return PTR_ERR(phy->reset);
837 }
838
839 if (i || data->cfg->phy0_dual_route) { /* No pmu for musb */
840 snprintf(name, sizeof(name), "pmu%d", i);
841 phy->pmu = devm_platform_ioremap_resource_byname(pdev, name);
842 if (IS_ERR(phy->pmu))
843 return PTR_ERR(phy->pmu);
844 }
845
846 phy->phy = devm_phy_create(dev, NULL, &sun4i_usb_phy_ops);
847 if (IS_ERR(phy->phy)) {
848 dev_err(dev, "failed to create PHY %d\n", i);
849 return PTR_ERR(phy->phy);
850 }
851
852 phy->index = i;
853 phy_set_drvdata(phy->phy, &data->phys[i]);
854 }
855
856 data->id_det_irq = gpiod_to_irq(data->id_det_gpio);
857 if (data->id_det_irq > 0) {
858 ret = devm_request_irq(dev, data->id_det_irq,
859 sun4i_usb_phy0_id_vbus_det_irq,
860 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
861 "usb0-id-det", data);
862 if (ret) {
863 dev_err(dev, "Err requesting id-det-irq: %d\n", ret);
864 return ret;
865 }
866 }
867
868 data->vbus_det_irq = gpiod_to_irq(data->vbus_det_gpio);
869 if (data->vbus_det_irq > 0) {
870 ret = devm_request_irq(dev, data->vbus_det_irq,
871 sun4i_usb_phy0_id_vbus_det_irq,
872 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
873 "usb0-vbus-det", data);
874 if (ret) {
875 dev_err(dev, "Err requesting vbus-det-irq: %d\n", ret);
876 data->vbus_det_irq = -1;
877 sun4i_usb_phy_remove(pdev); /* Stop detect work */
878 return ret;
879 }
880 }
881
882 if (data->vbus_power_supply) {
883 data->vbus_power_nb.notifier_call = sun4i_usb_phy0_vbus_notify;
884 data->vbus_power_nb.priority = 0;
885 ret = power_supply_reg_notifier(&data->vbus_power_nb);
886 if (ret) {
887 sun4i_usb_phy_remove(pdev); /* Stop detect work */
888 return ret;
889 }
890 data->vbus_power_nb_registered = true;
891 }
892
893 phy_provider = devm_of_phy_provider_register(dev, sun4i_usb_phy_xlate);
894 if (IS_ERR(phy_provider)) {
895 sun4i_usb_phy_remove(pdev); /* Stop detect work */
896 return PTR_ERR(phy_provider);
897 }
898
899 dev_dbg(dev, "successfully loaded\n");
900
901 return 0;
902}
903
904static const struct sun4i_usb_phy_cfg suniv_f1c100s_cfg = {
905 .num_phys = 1,
906 .disc_thresh = 3,
907 .phyctl_offset = REG_PHYCTL_A10,
908 .dedicated_clocks = true,
909};
910
911static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
912 .num_phys = 3,
913 .disc_thresh = 3,
914 .phyctl_offset = REG_PHYCTL_A10,
915 .dedicated_clocks = false,
916};
917
918static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
919 .num_phys = 2,
920 .disc_thresh = 2,
921 .phyctl_offset = REG_PHYCTL_A10,
922 .dedicated_clocks = false,
923};
924
925static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
926 .num_phys = 3,
927 .disc_thresh = 3,
928 .phyctl_offset = REG_PHYCTL_A10,
929 .dedicated_clocks = true,
930 .poll_vbusen = true,
931};
932
933static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
934 .num_phys = 3,
935 .disc_thresh = 2,
936 .phyctl_offset = REG_PHYCTL_A10,
937 .dedicated_clocks = false,
938};
939
940static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
941 .num_phys = 2,
942 .disc_thresh = 3,
943 .phyctl_offset = REG_PHYCTL_A10,
944 .dedicated_clocks = true,
945 .poll_vbusen = true,
946};
947
948static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
949 .num_phys = 2,
950 .disc_thresh = 3,
951 .phyctl_offset = REG_PHYCTL_A33,
952 .dedicated_clocks = true,
953 .poll_vbusen = true,
954};
955
956static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
957 .num_phys = 3,
958 .hsic_index = 2,
959 .phyctl_offset = REG_PHYCTL_A33,
960 .dedicated_clocks = true,
961 .siddq_in_base = true,
962};
963
964static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
965 .num_phys = 4,
966 .disc_thresh = 3,
967 .phyctl_offset = REG_PHYCTL_A33,
968 .dedicated_clocks = true,
969 .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
970 .phy0_dual_route = true,
971};
972
973static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
974 .num_phys = 3,
975 .disc_thresh = 3,
976 .phyctl_offset = REG_PHYCTL_A33,
977 .dedicated_clocks = true,
978 .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
979 .phy0_dual_route = true,
980};
981
982static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
983 .num_phys = 1,
984 .disc_thresh = 3,
985 .phyctl_offset = REG_PHYCTL_A33,
986 .dedicated_clocks = true,
987 .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
988 .phy0_dual_route = true,
989};
990
991static const struct sun4i_usb_phy_cfg sun20i_d1_cfg = {
992 .num_phys = 2,
993 .phyctl_offset = REG_PHYCTL_A33,
994 .dedicated_clocks = true,
995 .hci_phy_ctl_clear = PHY_CTL_SIDDQ,
996 .phy0_dual_route = true,
997 .siddq_in_base = true,
998};
999
1000static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
1001 .num_phys = 2,
1002 .disc_thresh = 3,
1003 .phyctl_offset = REG_PHYCTL_A33,
1004 .dedicated_clocks = true,
1005 .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
1006 .phy0_dual_route = true,
1007};
1008
1009static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
1010 .num_phys = 4,
1011 .phyctl_offset = REG_PHYCTL_A33,
1012 .dedicated_clocks = true,
1013 .phy0_dual_route = true,
1014 .missing_phys = BIT(1) | BIT(2),
1015 .siddq_in_base = true,
1016};
1017
1018static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
1019 .num_phys = 4,
1020 .disc_thresh = 3,
1021 .phyctl_offset = REG_PHYCTL_A33,
1022 .dedicated_clocks = true,
1023 .phy0_dual_route = true,
1024 .hci_phy_ctl_clear = PHY_CTL_SIDDQ,
1025 .needs_phy2_siddq = true,
1026 .siddq_in_base = true,
1027};
1028
1029static const struct of_device_id sun4i_usb_phy_of_match[] = {
1030 { .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
1031 { .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
1032 { .compatible = "allwinner,sun6i-a31-usb-phy", .data = &sun6i_a31_cfg },
1033 { .compatible = "allwinner,sun7i-a20-usb-phy", .data = &sun7i_a20_cfg },
1034 { .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
1035 { .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
1036 { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = &sun8i_a83t_cfg },
1037 { .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
1038 { .compatible = "allwinner,sun8i-r40-usb-phy", .data = &sun8i_r40_cfg },
1039 { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg },
1040 { .compatible = "allwinner,sun20i-d1-usb-phy", .data = &sun20i_d1_cfg },
1041 { .compatible = "allwinner,sun50i-a64-usb-phy",
1042 .data = &sun50i_a64_cfg},
1043 { .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
1044 { .compatible = "allwinner,sun50i-h616-usb-phy", .data = &sun50i_h616_cfg },
1045 { .compatible = "allwinner,suniv-f1c100s-usb-phy",
1046 .data = &suniv_f1c100s_cfg },
1047 { },
1048};
1049MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
1050
1051static struct platform_driver sun4i_usb_phy_driver = {
1052 .probe = sun4i_usb_phy_probe,
1053 .remove_new = sun4i_usb_phy_remove,
1054 .driver = {
1055 .of_match_table = sun4i_usb_phy_of_match,
1056 .name = "sun4i-usb-phy",
1057 }
1058};
1059module_platform_driver(sun4i_usb_phy_driver);
1060
1061MODULE_DESCRIPTION("Allwinner sun4i USB phy driver");
1062MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
1063MODULE_LICENSE("GPL v2");