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1/*======================================================================
2
3 Device driver for the PCMCIA control functionality of PXA2xx
4 microprocessors.
5
6 The contents of this file may be used under the
7 terms of the GNU Public License version 2 (the "GPL")
8
9 (c) Ian Molton (spyro@f2s.com) 2003
10 (c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4
11
12 derived from sa11xx_base.c
13
14 Portions created by John G. Dorsey are
15 Copyright (C) 1999 John G. Dorsey.
16
17 ======================================================================*/
18
19#include <linux/module.h>
20#include <linux/slab.h>
21#include <linux/init.h>
22#include <linux/cpufreq.h>
23#include <linux/ioport.h>
24#include <linux/kernel.h>
25#include <linux/spinlock.h>
26#include <linux/platform_device.h>
27
28#include <mach/hardware.h>
29#include <mach/smemc.h>
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <asm/system.h>
33#include <mach/pxa2xx-regs.h>
34#include <asm/mach-types.h>
35
36#include <pcmcia/ss.h>
37#include <pcmcia/cistpl.h>
38
39#include "soc_common.h"
40#include "pxa2xx_base.h"
41
42/*
43 * Personal Computer Memory Card International Association (PCMCIA) sockets
44 */
45
46#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
47#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
48#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
49#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
50#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
51
52#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
53#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
54#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
55#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
56
57#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
58#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
59#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
60#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
61
62#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
63 (0x20000000 + (Nb) * PCMCIASp)
64#define _PCMCIAIO(Nb) _PCMCIA(Nb) /* PCMCIA I/O [0..1] */
65#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
66 (_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
67#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
68 (_PCMCIA(Nb) + 3 * PCMCIAPrtSp)
69
70#define _PCMCIA0 _PCMCIA(0) /* PCMCIA 0 */
71#define _PCMCIA0IO _PCMCIAIO(0) /* PCMCIA 0 I/O */
72#define _PCMCIA0Attr _PCMCIAAttr(0) /* PCMCIA 0 Attribute */
73#define _PCMCIA0Mem _PCMCIAMem(0) /* PCMCIA 0 Memory */
74
75#define _PCMCIA1 _PCMCIA(1) /* PCMCIA 1 */
76#define _PCMCIA1IO _PCMCIAIO(1) /* PCMCIA 1 I/O */
77#define _PCMCIA1Attr _PCMCIAAttr(1) /* PCMCIA 1 Attribute */
78#define _PCMCIA1Mem _PCMCIAMem(1) /* PCMCIA 1 Memory */
79
80
81#define MCXX_SETUP_MASK (0x7f)
82#define MCXX_ASST_MASK (0x1f)
83#define MCXX_HOLD_MASK (0x3f)
84#define MCXX_SETUP_SHIFT (0)
85#define MCXX_ASST_SHIFT (7)
86#define MCXX_HOLD_SHIFT (14)
87
88static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
89 u_int mem_clk_10khz)
90{
91 u_int code = pcmcia_cycle_ns * mem_clk_10khz;
92 return (code / 300000) + ((code % 300000) ? 1 : 0) - 1;
93}
94
95static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns,
96 u_int mem_clk_10khz)
97{
98 u_int code = pcmcia_cycle_ns * mem_clk_10khz;
99 return (code / 300000) + ((code % 300000) ? 1 : 0) + 1;
100}
101
102static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns,
103 u_int mem_clk_10khz)
104{
105 u_int code = pcmcia_cycle_ns * mem_clk_10khz;
106 return (code / 100000) + ((code % 100000) ? 1 : 0) - 1;
107}
108
109/* This function returns the (approximate) command assertion period, in
110 * nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
111 */
112static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
113 u_int pcmcia_mcxx_asst)
114{
115 return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
116}
117
118static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock )
119{
120 uint32_t val;
121
122 val = ((pxa2xx_mcxx_setup(speed, clock)
123 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
124 | ((pxa2xx_mcxx_asst(speed, clock)
125 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
126 | ((pxa2xx_mcxx_hold(speed, clock)
127 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
128
129 __raw_writel(val, MCMEM(sock));
130
131 return 0;
132}
133
134static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock )
135{
136 uint32_t val;
137
138 val = ((pxa2xx_mcxx_setup(speed, clock)
139 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
140 | ((pxa2xx_mcxx_asst(speed, clock)
141 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
142 | ((pxa2xx_mcxx_hold(speed, clock)
143 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
144
145 __raw_writel(val, MCIO(sock));
146
147 return 0;
148}
149
150static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock )
151{
152 uint32_t val;
153
154 val = ((pxa2xx_mcxx_setup(speed, clock)
155 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
156 | ((pxa2xx_mcxx_asst(speed, clock)
157 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
158 | ((pxa2xx_mcxx_hold(speed, clock)
159 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
160
161 __raw_writel(val, MCATT(sock));
162
163 return 0;
164}
165
166static int pxa2xx_pcmcia_set_mcxx(struct soc_pcmcia_socket *skt, unsigned int clk)
167{
168 struct soc_pcmcia_timing timing;
169 int sock = skt->nr;
170
171 soc_common_pcmcia_get_timing(skt, &timing);
172
173 pxa2xx_pcmcia_set_mcmem(sock, timing.mem, clk);
174 pxa2xx_pcmcia_set_mcatt(sock, timing.attr, clk);
175 pxa2xx_pcmcia_set_mcio(sock, timing.io, clk);
176
177 return 0;
178}
179
180static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
181{
182 unsigned long clk = clk_get_rate(skt->clk);
183 return pxa2xx_pcmcia_set_mcxx(skt, clk / 10000);
184}
185
186#ifdef CONFIG_CPU_FREQ
187
188static int
189pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
190 unsigned long val,
191 struct cpufreq_freqs *freqs)
192{
193 switch (val) {
194 case CPUFREQ_PRECHANGE:
195 if (freqs->new > freqs->old) {
196 debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, "
197 "pre-updating\n",
198 freqs->new / 1000, (freqs->new / 100) % 10,
199 freqs->old / 1000, (freqs->old / 100) % 10);
200 pxa2xx_pcmcia_set_timing(skt);
201 }
202 break;
203
204 case CPUFREQ_POSTCHANGE:
205 if (freqs->new < freqs->old) {
206 debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, "
207 "post-updating\n",
208 freqs->new / 1000, (freqs->new / 100) % 10,
209 freqs->old / 1000, (freqs->old / 100) % 10);
210 pxa2xx_pcmcia_set_timing(skt);
211 }
212 break;
213 }
214 return 0;
215}
216#endif
217
218void pxa2xx_configure_sockets(struct device *dev)
219{
220 struct pcmcia_low_level *ops = dev->platform_data;
221 /*
222 * We have at least one socket, so set MECR:CIT
223 * (Card Is There)
224 */
225 uint32_t mecr = MECR_CIT;
226
227 /* Set MECR:NOS (Number Of Sockets) */
228 if ((ops->first + ops->nr) > 1 ||
229 machine_is_viper() || machine_is_arcom_zeus())
230 mecr |= MECR_NOS;
231
232 __raw_writel(mecr, MECR);
233}
234
235static const char *skt_names[] = {
236 "PCMCIA socket 0",
237 "PCMCIA socket 1",
238};
239
240#define SKT_DEV_INFO_SIZE(n) \
241 (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
242
243int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt)
244{
245 skt->res_skt.start = _PCMCIA(skt->nr);
246 skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
247 skt->res_skt.name = skt_names[skt->nr];
248 skt->res_skt.flags = IORESOURCE_MEM;
249
250 skt->res_io.start = _PCMCIAIO(skt->nr);
251 skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
252 skt->res_io.name = "io";
253 skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
254
255 skt->res_mem.start = _PCMCIAMem(skt->nr);
256 skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
257 skt->res_mem.name = "memory";
258 skt->res_mem.flags = IORESOURCE_MEM;
259
260 skt->res_attr.start = _PCMCIAAttr(skt->nr);
261 skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
262 skt->res_attr.name = "attribute";
263 skt->res_attr.flags = IORESOURCE_MEM;
264
265 return soc_pcmcia_add_one(skt);
266}
267EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one);
268
269void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops)
270{
271 /* Provide our PXA2xx specific timing routines. */
272 ops->set_timing = pxa2xx_pcmcia_set_timing;
273#ifdef CONFIG_CPU_FREQ
274 ops->frequency_change = pxa2xx_pcmcia_frequency_change;
275#endif
276}
277EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops);
278
279static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
280{
281 int i, ret = 0;
282 struct pcmcia_low_level *ops;
283 struct skt_dev_info *sinfo;
284 struct soc_pcmcia_socket *skt;
285 struct clk *clk;
286
287 ops = (struct pcmcia_low_level *)dev->dev.platform_data;
288 if (!ops) {
289 ret = -ENODEV;
290 goto err0;
291 }
292
293 if (cpu_is_pxa320() && ops->nr > 1) {
294 dev_err(&dev->dev, "pxa320 supports only one pcmcia slot");
295 ret = -EINVAL;
296 goto err0;
297 }
298
299 clk = clk_get(&dev->dev, NULL);
300 if (!clk)
301 return -ENODEV;
302
303 pxa2xx_drv_pcmcia_ops(ops);
304
305 sinfo = kzalloc(SKT_DEV_INFO_SIZE(ops->nr), GFP_KERNEL);
306 if (!sinfo) {
307 clk_put(clk);
308 return -ENOMEM;
309 }
310
311 sinfo->nskt = ops->nr;
312 sinfo->clk = clk;
313
314 /* Initialize processor specific parameters */
315 for (i = 0; i < ops->nr; i++) {
316 skt = &sinfo->skt[i];
317
318 skt->nr = ops->first + i;
319 skt->clk = clk;
320 skt->ops = ops;
321 skt->socket.owner = ops->owner;
322 skt->socket.dev.parent = &dev->dev;
323 skt->socket.pci_irq = NO_IRQ;
324
325 ret = pxa2xx_drv_pcmcia_add_one(skt);
326 if (ret)
327 goto err1;
328 }
329
330 if (ret) {
331 while (--i >= 0)
332 soc_pcmcia_remove_one(&sinfo->skt[i]);
333 kfree(sinfo);
334 clk_put(clk);
335 } else {
336 pxa2xx_configure_sockets(&dev->dev);
337 dev_set_drvdata(&dev->dev, sinfo);
338 }
339
340 return 0;
341
342err1:
343 while (--i >= 0)
344 soc_pcmcia_remove_one(&sinfo->skt[i]);
345 kfree(sinfo);
346err0:
347 return ret;
348}
349
350static int pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
351{
352 struct skt_dev_info *sinfo = platform_get_drvdata(dev);
353 int i;
354
355 platform_set_drvdata(dev, NULL);
356
357 for (i = 0; i < sinfo->nskt; i++)
358 soc_pcmcia_remove_one(&sinfo->skt[i]);
359
360 clk_put(sinfo->clk);
361 kfree(sinfo);
362 return 0;
363}
364
365static int pxa2xx_drv_pcmcia_resume(struct device *dev)
366{
367 pxa2xx_configure_sockets(dev);
368 return 0;
369}
370
371static const struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops = {
372 .resume = pxa2xx_drv_pcmcia_resume,
373};
374
375static struct platform_driver pxa2xx_pcmcia_driver = {
376 .probe = pxa2xx_drv_pcmcia_probe,
377 .remove = pxa2xx_drv_pcmcia_remove,
378 .driver = {
379 .name = "pxa2xx-pcmcia",
380 .owner = THIS_MODULE,
381 .pm = &pxa2xx_drv_pcmcia_pm_ops,
382 },
383};
384
385static int __init pxa2xx_pcmcia_init(void)
386{
387 return platform_driver_register(&pxa2xx_pcmcia_driver);
388}
389
390static void __exit pxa2xx_pcmcia_exit(void)
391{
392 platform_driver_unregister(&pxa2xx_pcmcia_driver);
393}
394
395fs_initcall(pxa2xx_pcmcia_init);
396module_exit(pxa2xx_pcmcia_exit);
397
398MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>");
399MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
400MODULE_LICENSE("GPL");
401MODULE_ALIAS("platform:pxa2xx-pcmcia");
1// SPDX-License-Identifier: GPL-2.0-only
2/*======================================================================
3
4 Device driver for the PCMCIA control functionality of PXA2xx
5 microprocessors.
6
7
8 (c) Ian Molton (spyro@f2s.com) 2003
9 (c) Stefan Eletzhofer (stefan.eletzhofer@inquant.de) 2003,4
10
11 derived from sa11xx_base.c
12
13 Portions created by John G. Dorsey are
14 Copyright (C) 1999 John G. Dorsey.
15
16 ======================================================================*/
17
18#include <linux/module.h>
19#include <linux/slab.h>
20#include <linux/init.h>
21#include <linux/cpufreq.h>
22#include <linux/ioport.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
25#include <linux/platform_device.h>
26#include <linux/soc/pxa/cpu.h>
27#include <linux/soc/pxa/smemc.h>
28
29#include <asm/io.h>
30#include <asm/irq.h>
31#include <asm/mach-types.h>
32
33#include <pcmcia/ss.h>
34#include <pcmcia/cistpl.h>
35
36#include "soc_common.h"
37#include "pxa2xx_base.h"
38
39/*
40 * Personal Computer Memory Card International Association (PCMCIA) sockets
41 */
42
43#define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
44#define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
45#define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
46#define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
47#define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
48
49#define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
50#define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
51#define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
52#define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
53
54#define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
55#define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
56#define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
57#define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
58
59#define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
60 (0x20000000 + (Nb) * PCMCIASp)
61#define _PCMCIAIO(Nb) _PCMCIA(Nb) /* PCMCIA I/O [0..1] */
62#define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
63 (_PCMCIA(Nb) + 2 * PCMCIAPrtSp)
64#define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
65 (_PCMCIA(Nb) + 3 * PCMCIAPrtSp)
66
67#define _PCMCIA0 _PCMCIA(0) /* PCMCIA 0 */
68#define _PCMCIA0IO _PCMCIAIO(0) /* PCMCIA 0 I/O */
69#define _PCMCIA0Attr _PCMCIAAttr(0) /* PCMCIA 0 Attribute */
70#define _PCMCIA0Mem _PCMCIAMem(0) /* PCMCIA 0 Memory */
71
72#define _PCMCIA1 _PCMCIA(1) /* PCMCIA 1 */
73#define _PCMCIA1IO _PCMCIAIO(1) /* PCMCIA 1 I/O */
74#define _PCMCIA1Attr _PCMCIAAttr(1) /* PCMCIA 1 Attribute */
75#define _PCMCIA1Mem _PCMCIAMem(1) /* PCMCIA 1 Memory */
76
77
78#define MCXX_SETUP_MASK (0x7f)
79#define MCXX_ASST_MASK (0x1f)
80#define MCXX_HOLD_MASK (0x3f)
81#define MCXX_SETUP_SHIFT (0)
82#define MCXX_ASST_SHIFT (7)
83#define MCXX_HOLD_SHIFT (14)
84
85static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
86 u_int mem_clk_10khz)
87{
88 u_int code = pcmcia_cycle_ns * mem_clk_10khz;
89 return (code / 300000) + ((code % 300000) ? 1 : 0) - 1;
90}
91
92static inline u_int pxa2xx_mcxx_asst(u_int pcmcia_cycle_ns,
93 u_int mem_clk_10khz)
94{
95 u_int code = pcmcia_cycle_ns * mem_clk_10khz;
96 return (code / 300000) + ((code % 300000) ? 1 : 0) + 1;
97}
98
99static inline u_int pxa2xx_mcxx_setup(u_int pcmcia_cycle_ns,
100 u_int mem_clk_10khz)
101{
102 u_int code = pcmcia_cycle_ns * mem_clk_10khz;
103 return (code / 100000) + ((code % 100000) ? 1 : 0) - 1;
104}
105
106/* This function returns the (approximate) command assertion period, in
107 * nanoseconds, for a given CPU clock frequency and MCXX_ASST value:
108 */
109static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
110 u_int pcmcia_mcxx_asst)
111{
112 return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
113}
114
115static uint32_t pxa2xx_pcmcia_mcmem(int sock, int speed, int clock)
116{
117 uint32_t val;
118
119 val = ((pxa2xx_mcxx_setup(speed, clock)
120 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
121 | ((pxa2xx_mcxx_asst(speed, clock)
122 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
123 | ((pxa2xx_mcxx_hold(speed, clock)
124 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
125
126 return val;
127}
128
129static int pxa2xx_pcmcia_mcio(int sock, int speed, int clock)
130{
131 uint32_t val;
132
133 val = ((pxa2xx_mcxx_setup(speed, clock)
134 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
135 | ((pxa2xx_mcxx_asst(speed, clock)
136 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
137 | ((pxa2xx_mcxx_hold(speed, clock)
138 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
139
140
141 return val;
142}
143
144static int pxa2xx_pcmcia_mcatt(int sock, int speed, int clock)
145{
146 uint32_t val;
147
148 val = ((pxa2xx_mcxx_setup(speed, clock)
149 & MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
150 | ((pxa2xx_mcxx_asst(speed, clock)
151 & MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
152 | ((pxa2xx_mcxx_hold(speed, clock)
153 & MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
154
155
156 return val;
157}
158
159static int pxa2xx_pcmcia_set_timing(struct soc_pcmcia_socket *skt)
160{
161 unsigned long clk = clk_get_rate(skt->clk) / 10000;
162 struct soc_pcmcia_timing timing;
163 int sock = skt->nr;
164
165 soc_common_pcmcia_get_timing(skt, &timing);
166
167 pxa_smemc_set_pcmcia_timing(sock,
168 pxa2xx_pcmcia_mcmem(sock, timing.mem, clk),
169 pxa2xx_pcmcia_mcatt(sock, timing.attr, clk),
170 pxa2xx_pcmcia_mcio(sock, timing.io, clk));
171
172 return 0;
173}
174
175#ifdef CONFIG_CPU_FREQ
176
177static int
178pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
179 unsigned long val,
180 struct cpufreq_freqs *freqs)
181{
182 switch (val) {
183 case CPUFREQ_PRECHANGE:
184 if (freqs->new > freqs->old) {
185 debug(skt, 2, "new frequency %u.%uMHz > %u.%uMHz, "
186 "pre-updating\n",
187 freqs->new / 1000, (freqs->new / 100) % 10,
188 freqs->old / 1000, (freqs->old / 100) % 10);
189 pxa2xx_pcmcia_set_timing(skt);
190 }
191 break;
192
193 case CPUFREQ_POSTCHANGE:
194 if (freqs->new < freqs->old) {
195 debug(skt, 2, "new frequency %u.%uMHz < %u.%uMHz, "
196 "post-updating\n",
197 freqs->new / 1000, (freqs->new / 100) % 10,
198 freqs->old / 1000, (freqs->old / 100) % 10);
199 pxa2xx_pcmcia_set_timing(skt);
200 }
201 break;
202 }
203 return 0;
204}
205#endif
206
207void pxa2xx_configure_sockets(struct device *dev, struct pcmcia_low_level *ops)
208{
209 pxa_smemc_set_pcmcia_socket(1);
210}
211EXPORT_SYMBOL(pxa2xx_configure_sockets);
212
213static const char *skt_names[] = {
214 "PCMCIA socket 0",
215 "PCMCIA socket 1",
216};
217
218#define SKT_DEV_INFO_SIZE(n) \
219 (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket))
220
221int pxa2xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt)
222{
223 skt->res_skt.start = _PCMCIA(skt->nr);
224 skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1;
225 skt->res_skt.name = skt_names[skt->nr];
226 skt->res_skt.flags = IORESOURCE_MEM;
227
228 skt->res_io.start = _PCMCIAIO(skt->nr);
229 skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1;
230 skt->res_io.name = "io";
231 skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
232
233 skt->res_mem.start = _PCMCIAMem(skt->nr);
234 skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1;
235 skt->res_mem.name = "memory";
236 skt->res_mem.flags = IORESOURCE_MEM;
237
238 skt->res_attr.start = _PCMCIAAttr(skt->nr);
239 skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1;
240 skt->res_attr.name = "attribute";
241 skt->res_attr.flags = IORESOURCE_MEM;
242
243 return soc_pcmcia_add_one(skt);
244}
245EXPORT_SYMBOL(pxa2xx_drv_pcmcia_add_one);
246
247void pxa2xx_drv_pcmcia_ops(struct pcmcia_low_level *ops)
248{
249 /* Provide our PXA2xx specific timing routines. */
250 ops->set_timing = pxa2xx_pcmcia_set_timing;
251#ifdef CONFIG_CPU_FREQ
252 ops->frequency_change = pxa2xx_pcmcia_frequency_change;
253#endif
254}
255EXPORT_SYMBOL(pxa2xx_drv_pcmcia_ops);
256
257static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
258{
259 int i, ret = 0;
260 struct pcmcia_low_level *ops;
261 struct skt_dev_info *sinfo;
262 struct soc_pcmcia_socket *skt;
263 struct clk *clk;
264
265 ops = (struct pcmcia_low_level *)dev->dev.platform_data;
266 if (!ops) {
267 ret = -ENODEV;
268 goto err0;
269 }
270
271 if (cpu_is_pxa320() && ops->nr > 1) {
272 dev_err(&dev->dev, "pxa320 supports only one pcmcia slot");
273 ret = -EINVAL;
274 goto err0;
275 }
276
277 clk = devm_clk_get(&dev->dev, NULL);
278 if (IS_ERR(clk))
279 return -ENODEV;
280
281 pxa2xx_drv_pcmcia_ops(ops);
282
283 sinfo = devm_kzalloc(&dev->dev, SKT_DEV_INFO_SIZE(ops->nr),
284 GFP_KERNEL);
285 if (!sinfo)
286 return -ENOMEM;
287
288 sinfo->nskt = ops->nr;
289
290 /* Initialize processor specific parameters */
291 for (i = 0; i < ops->nr; i++) {
292 skt = &sinfo->skt[i];
293
294 skt->nr = ops->first + i;
295 skt->clk = clk;
296 soc_pcmcia_init_one(skt, ops, &dev->dev);
297
298 ret = pxa2xx_drv_pcmcia_add_one(skt);
299 if (ret)
300 goto err1;
301 }
302
303 pxa2xx_configure_sockets(&dev->dev, ops);
304 dev_set_drvdata(&dev->dev, sinfo);
305
306 return 0;
307
308err1:
309 while (--i >= 0)
310 soc_pcmcia_remove_one(&sinfo->skt[i]);
311
312err0:
313 return ret;
314}
315
316static void pxa2xx_drv_pcmcia_remove(struct platform_device *dev)
317{
318 struct skt_dev_info *sinfo = platform_get_drvdata(dev);
319 int i;
320
321 for (i = 0; i < sinfo->nskt; i++)
322 soc_pcmcia_remove_one(&sinfo->skt[i]);
323}
324
325static int pxa2xx_drv_pcmcia_resume(struct device *dev)
326{
327 struct pcmcia_low_level *ops = (struct pcmcia_low_level *)dev->platform_data;
328
329 pxa2xx_configure_sockets(dev, ops);
330 return 0;
331}
332
333static const struct dev_pm_ops pxa2xx_drv_pcmcia_pm_ops = {
334 .resume = pxa2xx_drv_pcmcia_resume,
335};
336
337static struct platform_driver pxa2xx_pcmcia_driver = {
338 .probe = pxa2xx_drv_pcmcia_probe,
339 .remove_new = pxa2xx_drv_pcmcia_remove,
340 .driver = {
341 .name = "pxa2xx-pcmcia",
342 .pm = &pxa2xx_drv_pcmcia_pm_ops,
343 },
344};
345
346static int __init pxa2xx_pcmcia_init(void)
347{
348 return platform_driver_register(&pxa2xx_pcmcia_driver);
349}
350
351static void __exit pxa2xx_pcmcia_exit(void)
352{
353 platform_driver_unregister(&pxa2xx_pcmcia_driver);
354}
355
356fs_initcall(pxa2xx_pcmcia_init);
357module_exit(pxa2xx_pcmcia_exit);
358
359MODULE_AUTHOR("Stefan Eletzhofer <stefan.eletzhofer@inquant.de> and Ian Molton <spyro@f2s.com>");
360MODULE_DESCRIPTION("Linux PCMCIA Card Services: PXA2xx core socket driver");
361MODULE_LICENSE("GPL");
362MODULE_ALIAS("platform:pxa2xx-pcmcia");