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1/* SPDX-License-Identifier: ISC */
2/*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6#ifndef __MT7996_H
7#define __MT7996_H
8
9#include <linux/interrupt.h>
10#include <linux/ktime.h>
11#include "../mt76_connac.h"
12#include "regs.h"
13
14#define MT7996_MAX_INTERFACES 19 /* per-band */
15#define MT7996_MAX_WMM_SETS 4
16#define MT7996_WTBL_BMC_SIZE (is_mt7992(&dev->mt76) ? 32 : 64)
17#define MT7996_WTBL_RESERVED (mt7996_wtbl_size(dev) - 1)
18#define MT7996_WTBL_STA (MT7996_WTBL_RESERVED - \
19 mt7996_max_interface_num(dev))
20
21#define MT7996_WATCHDOG_TIME (HZ / 10)
22#define MT7996_RESET_TIMEOUT (30 * HZ)
23
24#define MT7996_TX_RING_SIZE 2048
25#define MT7996_TX_MCU_RING_SIZE 256
26#define MT7996_TX_FWDL_RING_SIZE 128
27
28#define MT7996_RX_RING_SIZE 1536
29#define MT7996_RX_MCU_RING_SIZE 512
30#define MT7996_RX_MCU_RING_SIZE_WA 1024
31
32#define MT7996_FIRMWARE_WA "mediatek/mt7996/mt7996_wa.bin"
33#define MT7996_FIRMWARE_WM "mediatek/mt7996/mt7996_wm.bin"
34#define MT7996_FIRMWARE_DSP "mediatek/mt7996/mt7996_dsp.bin"
35#define MT7996_ROM_PATCH "mediatek/mt7996/mt7996_rom_patch.bin"
36
37#define MT7992_FIRMWARE_WA "mediatek/mt7996/mt7992_wa.bin"
38#define MT7992_FIRMWARE_WM "mediatek/mt7996/mt7992_wm.bin"
39#define MT7992_FIRMWARE_DSP "mediatek/mt7996/mt7992_dsp.bin"
40#define MT7992_ROM_PATCH "mediatek/mt7996/mt7992_rom_patch.bin"
41
42#define MT7996_EEPROM_DEFAULT "mediatek/mt7996/mt7996_eeprom.bin"
43#define MT7992_EEPROM_DEFAULT "mediatek/mt7996/mt7992_eeprom.bin"
44#define MT7996_EEPROM_SIZE 7680
45#define MT7996_EEPROM_BLOCK_SIZE 16
46#define MT7996_TOKEN_SIZE 16384
47#define MT7996_HW_TOKEN_SIZE 8192
48
49#define MT7996_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */
50#define MT7996_CFEND_RATE_11B 0x03 /* 11B LP, 11M */
51
52#define MT7996_SKU_RATE_NUM 417
53
54#define MT7996_MAX_TWT_AGRT 16
55#define MT7996_MAX_STA_TWT_AGRT 8
56#define MT7996_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 3)
57
58/* NOTE: used to map mt76_rates. idx may change if firmware expands table */
59#define MT7996_BASIC_RATES_TBL 31
60#define MT7996_BEACON_RATES_TBL 25
61
62#define MT7996_THERMAL_THROTTLE_MAX 100
63#define MT7996_CDEV_THROTTLE_MAX 99
64#define MT7996_CRIT_TEMP_IDX 0
65#define MT7996_MAX_TEMP_IDX 1
66#define MT7996_CRIT_TEMP 110
67#define MT7996_MAX_TEMP 120
68
69#define MT7996_RRO_MAX_SESSION 1024
70#define MT7996_RRO_WINDOW_MAX_LEN 1024
71#define MT7996_RRO_ADDR_ELEM_LEN 128
72#define MT7996_RRO_BA_BITMAP_LEN 2
73#define MT7996_RRO_BA_BITMAP_CR_SIZE ((MT7996_RRO_MAX_SESSION * 128) / \
74 MT7996_RRO_BA_BITMAP_LEN)
75#define MT7996_RRO_BA_BITMAP_SESSION_SIZE (MT7996_RRO_MAX_SESSION / \
76 MT7996_RRO_ADDR_ELEM_LEN)
77#define MT7996_RRO_WINDOW_MAX_SIZE (MT7996_RRO_WINDOW_MAX_LEN * \
78 MT7996_RRO_BA_BITMAP_SESSION_SIZE)
79
80#define MT7996_RX_BUF_SIZE (1800 + \
81 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
82#define MT7996_RX_MSDU_PAGE_SIZE (128 + \
83 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
84
85struct mt7996_vif;
86struct mt7996_sta;
87struct mt7996_dfs_pulse;
88struct mt7996_dfs_pattern;
89
90enum mt7996_ram_type {
91 MT7996_RAM_TYPE_WM,
92 MT7996_RAM_TYPE_WA,
93 MT7996_RAM_TYPE_DSP,
94};
95
96enum mt7996_txq_id {
97 MT7996_TXQ_FWDL = 16,
98 MT7996_TXQ_MCU_WM,
99 MT7996_TXQ_BAND0,
100 MT7996_TXQ_BAND1,
101 MT7996_TXQ_MCU_WA,
102 MT7996_TXQ_BAND2,
103};
104
105enum mt7996_rxq_id {
106 MT7996_RXQ_MCU_WM = 0,
107 MT7996_RXQ_MCU_WA,
108 MT7996_RXQ_MCU_WA_MAIN = 2,
109 MT7996_RXQ_MCU_WA_EXT = 3, /* for mt7992 */
110 MT7996_RXQ_MCU_WA_TRI = 3,
111 MT7996_RXQ_BAND0 = 4,
112 MT7996_RXQ_BAND1 = 5, /* for mt7992 */
113 MT7996_RXQ_BAND2 = 5,
114 MT7996_RXQ_RRO_BAND0 = 8,
115 MT7996_RXQ_RRO_BAND1 = 8,/* unused */
116 MT7996_RXQ_RRO_BAND2 = 6,
117 MT7996_RXQ_MSDU_PG_BAND0 = 10,
118 MT7996_RXQ_MSDU_PG_BAND1 = 11,
119 MT7996_RXQ_MSDU_PG_BAND2 = 12,
120 MT7996_RXQ_TXFREE0 = 9,
121 MT7996_RXQ_TXFREE1 = 9,
122 MT7996_RXQ_TXFREE2 = 7,
123 MT7996_RXQ_RRO_IND = 0,
124};
125
126struct mt7996_twt_flow {
127 struct list_head list;
128 u64 start_tsf;
129 u64 tsf;
130 u32 duration;
131 u16 wcid;
132 __le16 mantissa;
133 u8 exp;
134 u8 table_id;
135 u8 id;
136 u8 protection:1;
137 u8 flowtype:1;
138 u8 trigger:1;
139 u8 sched:1;
140};
141
142DECLARE_EWMA(avg_signal, 10, 8)
143
144struct mt7996_sta {
145 struct mt76_wcid wcid; /* must be first */
146
147 struct mt7996_vif *vif;
148
149 struct list_head rc_list;
150 u32 airtime_ac[8];
151
152 int ack_signal;
153 struct ewma_avg_signal avg_ack_signal;
154
155 unsigned long changed;
156
157 struct mt76_connac_sta_key_conf bip;
158
159 struct {
160 u8 flowid_mask;
161 struct mt7996_twt_flow flow[MT7996_MAX_STA_TWT_AGRT];
162 } twt;
163};
164
165struct mt7996_vif {
166 struct mt76_vif mt76; /* must be first */
167
168 struct mt7996_sta sta;
169 struct mt7996_phy *phy;
170
171 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS];
172 struct cfg80211_bitrate_mask bitrate_mask;
173};
174
175/* crash-dump */
176struct mt7996_crash_data {
177 guid_t guid;
178 struct timespec64 timestamp;
179
180 u8 *memdump_buf;
181 size_t memdump_buf_len;
182};
183
184struct mt7996_hif {
185 struct list_head list;
186
187 struct device *dev;
188 void __iomem *regs;
189 int irq;
190};
191
192struct mt7996_wed_rro_addr {
193 u32 head_low;
194 u32 head_high : 4;
195 u32 count: 11;
196 u32 oor: 1;
197 u32 rsv : 8;
198 u32 signature : 8;
199};
200
201struct mt7996_wed_rro_session_id {
202 struct list_head list;
203 u16 id;
204};
205
206struct mt7996_phy {
207 struct mt76_phy *mt76;
208 struct mt7996_dev *dev;
209
210 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
211
212 struct ieee80211_vif *monitor_vif;
213
214 struct thermal_cooling_device *cdev;
215 u8 cdev_state;
216 u8 throttle_state;
217 u32 throttle_temp[2]; /* 0: critical high, 1: maximum */
218
219 u32 rxfilter;
220 u64 omac_mask;
221
222 u16 noise;
223
224 s16 coverage_class;
225 u8 slottime;
226
227 u8 rdd_state;
228
229 u16 beacon_rate;
230
231 u32 rx_ampdu_ts;
232 u32 ampdu_ref;
233
234 struct mt76_mib_stats mib;
235 struct mt76_channel_state state_ts;
236
237 bool has_aux_rx;
238};
239
240struct mt7996_dev {
241 union { /* must be first */
242 struct mt76_dev mt76;
243 struct mt76_phy mphy;
244 };
245
246 struct mt7996_hif *hif2;
247 struct mt7996_reg_desc reg;
248 u8 q_id[MT7996_MAX_QUEUE];
249 u32 q_int_mask[MT7996_MAX_QUEUE];
250 u32 q_wfdma_mask;
251
252 const struct mt76_bus_ops *bus_ops;
253 struct mt7996_phy phy;
254
255 /* monitor rx chain configured channel */
256 struct cfg80211_chan_def rdd2_chandef;
257 struct mt7996_phy *rdd2_phy;
258
259 u16 chainmask;
260 u8 chainshift[__MT_MAX_BAND];
261 u32 hif_idx;
262
263 struct work_struct init_work;
264 struct work_struct rc_work;
265 struct work_struct dump_work;
266 struct work_struct reset_work;
267 wait_queue_head_t reset_wait;
268 struct {
269 u32 state;
270 u32 wa_reset_count;
271 u32 wm_reset_count;
272 bool hw_full_reset:1;
273 bool hw_init_done:1;
274 bool restart:1;
275 } recovery;
276
277 /* protects coredump data */
278 struct mutex dump_mutex;
279#ifdef CONFIG_DEV_COREDUMP
280 struct {
281 struct mt7996_crash_data *crash_data;
282 } coredump;
283#endif
284
285 struct list_head sta_rc_list;
286 struct list_head twt_list;
287
288 u32 hw_pattern;
289
290 bool flash_mode:1;
291 bool has_eht:1;
292 bool has_rro:1;
293
294 struct {
295 struct {
296 void *ptr;
297 dma_addr_t phy_addr;
298 } ba_bitmap[MT7996_RRO_BA_BITMAP_LEN];
299 struct {
300 void *ptr;
301 dma_addr_t phy_addr;
302 } addr_elem[MT7996_RRO_ADDR_ELEM_LEN];
303 struct {
304 void *ptr;
305 dma_addr_t phy_addr;
306 } session;
307
308 struct work_struct work;
309 struct list_head poll_list;
310 spinlock_t lock;
311 } wed_rro;
312
313 bool ibf;
314 u8 fw_debug_wm;
315 u8 fw_debug_wa;
316 u8 fw_debug_bin;
317 u16 fw_debug_seq;
318
319 struct dentry *debugfs_dir;
320 struct rchan *relay_fwlog;
321
322 struct {
323 u8 table_mask;
324 u8 n_agrt;
325 } twt;
326
327 u32 reg_l1_backup;
328 u32 reg_l2_backup;
329
330 u8 wtbl_size_group;
331};
332
333enum {
334 WFDMA0 = 0x0,
335 WFDMA1,
336 WFDMA_EXT,
337 __MT_WFDMA_MAX,
338};
339
340enum {
341 MT_RX_SEL0,
342 MT_RX_SEL1,
343 MT_RX_SEL2, /* monitor chain */
344};
345
346enum mt7996_rdd_cmd {
347 RDD_STOP,
348 RDD_START,
349 RDD_DET_MODE,
350 RDD_RADAR_EMULATE,
351 RDD_START_TXQ = 20,
352 RDD_CAC_START = 50,
353 RDD_CAC_END,
354 RDD_NORMAL_START,
355 RDD_DISABLE_DFS_CAL,
356 RDD_PULSE_DBG,
357 RDD_READ_PULSE,
358 RDD_RESUME_BF,
359 RDD_IRQ_OFF,
360};
361
362static inline struct mt7996_phy *
363mt7996_hw_phy(struct ieee80211_hw *hw)
364{
365 struct mt76_phy *phy = hw->priv;
366
367 return phy->priv;
368}
369
370static inline struct mt7996_dev *
371mt7996_hw_dev(struct ieee80211_hw *hw)
372{
373 struct mt76_phy *phy = hw->priv;
374
375 return container_of(phy->dev, struct mt7996_dev, mt76);
376}
377
378static inline struct mt7996_phy *
379__mt7996_phy(struct mt7996_dev *dev, enum mt76_band_id band)
380{
381 struct mt76_phy *phy = dev->mt76.phys[band];
382
383 if (!phy)
384 return NULL;
385
386 return phy->priv;
387}
388
389static inline struct mt7996_phy *
390mt7996_phy2(struct mt7996_dev *dev)
391{
392 return __mt7996_phy(dev, MT_BAND1);
393}
394
395static inline struct mt7996_phy *
396mt7996_phy3(struct mt7996_dev *dev)
397{
398 return __mt7996_phy(dev, MT_BAND2);
399}
400
401static inline bool
402mt7996_band_valid(struct mt7996_dev *dev, u8 band)
403{
404 if (is_mt7992(&dev->mt76))
405 return band <= MT_BAND1;
406
407 /* tri-band support */
408 if (band <= MT_BAND2 &&
409 mt76_get_field(dev, MT_PAD_GPIO, MT_PAD_GPIO_ADIE_COMB) <= 1)
410 return true;
411
412 return band == MT_BAND0 || band == MT_BAND2;
413}
414
415extern const struct ieee80211_ops mt7996_ops;
416extern struct pci_driver mt7996_pci_driver;
417extern struct pci_driver mt7996_hif_driver;
418
419struct mt7996_dev *mt7996_mmio_probe(struct device *pdev,
420 void __iomem *mem_base, u32 device_id);
421void mt7996_wfsys_reset(struct mt7996_dev *dev);
422irqreturn_t mt7996_irq_handler(int irq, void *dev_instance);
423u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif *mvif);
424int mt7996_register_device(struct mt7996_dev *dev);
425void mt7996_unregister_device(struct mt7996_dev *dev);
426int mt7996_eeprom_init(struct mt7996_dev *dev);
427int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy);
428int mt7996_eeprom_get_target_power(struct mt7996_dev *dev,
429 struct ieee80211_channel *chan);
430s8 mt7996_eeprom_get_power_delta(struct mt7996_dev *dev, int band);
431int mt7996_dma_init(struct mt7996_dev *dev);
432void mt7996_dma_reset(struct mt7996_dev *dev, bool force);
433void mt7996_dma_prefetch(struct mt7996_dev *dev);
434void mt7996_dma_cleanup(struct mt7996_dev *dev);
435void mt7996_dma_start(struct mt7996_dev *dev, bool reset, bool wed_reset);
436int mt7996_init_tx_queues(struct mt7996_phy *phy, int idx,
437 int n_desc, int ring_base, struct mtk_wed_device *wed);
438void mt7996_init_txpower(struct mt7996_phy *phy);
439int mt7996_txbf_init(struct mt7996_dev *dev);
440void mt7996_reset(struct mt7996_dev *dev);
441int mt7996_run(struct ieee80211_hw *hw);
442int mt7996_mcu_init(struct mt7996_dev *dev);
443int mt7996_mcu_init_firmware(struct mt7996_dev *dev);
444int mt7996_mcu_twt_agrt_update(struct mt7996_dev *dev,
445 struct mt7996_vif *mvif,
446 struct mt7996_twt_flow *flow,
447 int cmd);
448int mt7996_mcu_add_dev_info(struct mt7996_phy *phy,
449 struct ieee80211_vif *vif, bool enable);
450int mt7996_mcu_add_bss_info(struct mt7996_phy *phy,
451 struct ieee80211_vif *vif, int enable);
452int mt7996_mcu_add_sta(struct mt7996_dev *dev, struct ieee80211_vif *vif,
453 struct ieee80211_sta *sta, bool enable);
454int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev,
455 struct ieee80211_ampdu_params *params,
456 bool add);
457int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev,
458 struct ieee80211_ampdu_params *params,
459 bool add);
460int mt7996_mcu_update_bss_color(struct mt7996_dev *dev, struct ieee80211_vif *vif,
461 struct cfg80211_he_bss_color *he_bss_color);
462int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
463 int enable);
464int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev,
465 struct ieee80211_vif *vif, u32 changed);
466int mt7996_mcu_add_obss_spr(struct mt7996_phy *phy, struct ieee80211_vif *vif,
467 struct ieee80211_he_obss_pd *he_obss_pd);
468int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct ieee80211_vif *vif,
469 struct ieee80211_sta *sta, bool changed);
470int mt7996_set_channel(struct mt7996_phy *phy);
471int mt7996_mcu_set_chan_info(struct mt7996_phy *phy, u16 tag);
472int mt7996_mcu_set_tx(struct mt7996_dev *dev, struct ieee80211_vif *vif);
473int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev,
474 void *data, u16 version);
475int mt7996_mcu_set_fixed_field(struct mt7996_dev *dev, struct ieee80211_vif *vif,
476 struct ieee80211_sta *sta, void *data, u32 field);
477int mt7996_mcu_set_eeprom(struct mt7996_dev *dev);
478int mt7996_mcu_get_eeprom(struct mt7996_dev *dev, u32 offset);
479int mt7996_mcu_get_eeprom_free_block(struct mt7996_dev *dev, u8 *block_num);
480int mt7996_mcu_get_chip_config(struct mt7996_dev *dev, u32 *cap);
481int mt7996_mcu_set_ser(struct mt7996_dev *dev, u8 action, u8 set, u8 band);
482int mt7996_mcu_set_txbf(struct mt7996_dev *dev, u8 action);
483int mt7996_mcu_set_fcc5_lpn(struct mt7996_dev *dev, int val);
484int mt7996_mcu_set_pulse_th(struct mt7996_dev *dev,
485 const struct mt7996_dfs_pulse *pulse);
486int mt7996_mcu_set_radar_th(struct mt7996_dev *dev, int index,
487 const struct mt7996_dfs_pattern *pattern);
488int mt7996_mcu_set_radio_en(struct mt7996_phy *phy, bool enable);
489int mt7996_mcu_set_rts_thresh(struct mt7996_phy *phy, u32 val);
490int mt7996_mcu_set_timing(struct mt7996_phy *phy, struct ieee80211_vif *vif);
491int mt7996_mcu_get_chan_mib_info(struct mt7996_phy *phy, bool chan_switch);
492int mt7996_mcu_get_temperature(struct mt7996_phy *phy);
493int mt7996_mcu_set_thermal_throttling(struct mt7996_phy *phy, u8 state);
494int mt7996_mcu_set_thermal_protect(struct mt7996_phy *phy, bool enable);
495int mt7996_mcu_set_txpower_sku(struct mt7996_phy *phy);
496int mt7996_mcu_rdd_cmd(struct mt7996_dev *dev, int cmd, u8 index,
497 u8 rx_sel, u8 val);
498int mt7996_mcu_rdd_background_enable(struct mt7996_phy *phy,
499 struct cfg80211_chan_def *chandef);
500int mt7996_mcu_set_fixed_rate_table(struct mt7996_phy *phy, u8 table_idx,
501 u16 rate_idx, bool beacon);
502int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set);
503int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans);
504int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u16 val);
505int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3);
506int mt7996_mcu_fw_log_2_host(struct mt7996_dev *dev, u8 type, u8 ctrl);
507int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level);
508int mt7996_mcu_trigger_assert(struct mt7996_dev *dev);
509void mt7996_mcu_rx_event(struct mt7996_dev *dev, struct sk_buff *skb);
510void mt7996_mcu_exit(struct mt7996_dev *dev);
511int mt7996_mcu_get_all_sta_info(struct mt7996_phy *phy, u16 tag);
512int mt7996_mcu_wed_rro_reset_sessions(struct mt7996_dev *dev, u16 id);
513
514static inline u8 mt7996_max_interface_num(struct mt7996_dev *dev)
515{
516 return min(MT7996_MAX_INTERFACES * (1 + mt7996_band_valid(dev, MT_BAND1) +
517 mt7996_band_valid(dev, MT_BAND2)),
518 MT7996_WTBL_BMC_SIZE);
519}
520
521static inline u16 mt7996_wtbl_size(struct mt7996_dev *dev)
522{
523 return (dev->wtbl_size_group << 8) + MT7996_WTBL_BMC_SIZE;
524}
525
526void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg,
527 u32 clear, u32 set);
528
529static inline void mt7996_irq_enable(struct mt7996_dev *dev, u32 mask)
530{
531 if (dev->hif2)
532 mt7996_dual_hif_set_irq_mask(dev, false, 0, mask);
533 else
534 mt76_set_irq_mask(&dev->mt76, 0, 0, mask);
535
536 tasklet_schedule(&dev->mt76.irq_tasklet);
537}
538
539static inline void mt7996_irq_disable(struct mt7996_dev *dev, u32 mask)
540{
541 if (dev->hif2)
542 mt7996_dual_hif_set_irq_mask(dev, true, mask, 0);
543 else
544 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
545}
546
547void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset,
548 size_t len);
549
550static inline u16 mt7996_rx_chainmask(struct mt7996_phy *phy)
551{
552 int max_nss = hweight8(phy->mt76->hw->wiphy->available_antennas_tx);
553 int cur_nss = hweight8(phy->mt76->antenna_mask);
554 u16 tx_chainmask = phy->mt76->chainmask;
555
556 if (cur_nss != max_nss)
557 return tx_chainmask;
558
559 return tx_chainmask | (BIT(fls(tx_chainmask)) * phy->has_aux_rx);
560}
561
562void mt7996_mac_init(struct mt7996_dev *dev);
563u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw);
564bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask);
565void mt7996_mac_reset_counters(struct mt7996_phy *phy);
566void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy);
567void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band);
568void mt7996_mac_enable_rtscts(struct mt7996_dev *dev,
569 struct ieee80211_vif *vif, bool enable);
570void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
571 struct sk_buff *skb, struct mt76_wcid *wcid,
572 struct ieee80211_key_conf *key, int pid,
573 enum mt76_txq_id qid, u32 changed);
574void mt7996_mac_set_coverage_class(struct mt7996_phy *phy);
575int mt7996_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif,
576 struct ieee80211_sta *sta);
577void mt7996_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif,
578 struct ieee80211_sta *sta);
579void mt7996_mac_work(struct work_struct *work);
580void mt7996_mac_reset_work(struct work_struct *work);
581void mt7996_mac_dump_work(struct work_struct *work);
582void mt7996_mac_sta_rc_work(struct work_struct *work);
583void mt7996_mac_update_stats(struct mt7996_phy *phy);
584void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev,
585 struct mt7996_sta *msta,
586 u8 flowid);
587void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw,
588 struct ieee80211_sta *sta,
589 struct ieee80211_twt_setup *twt);
590int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
591 enum mt76_txq_id qid, struct mt76_wcid *wcid,
592 struct ieee80211_sta *sta,
593 struct mt76_tx_info *tx_info);
594void mt7996_tx_token_put(struct mt7996_dev *dev);
595void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
596 struct sk_buff *skb, u32 *info);
597bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len);
598void mt7996_stats_work(struct work_struct *work);
599int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force);
600int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy);
601void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy);
602void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy);
603void mt7996_update_channel(struct mt76_phy *mphy);
604int mt7996_init_debugfs(struct mt7996_phy *phy);
605void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len);
606bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len);
607int mt7996_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
608 struct ieee80211_key_conf *key, int mcu_cmd,
609 struct mt76_wcid *wcid, enum set_key_cmd cmd);
610int mt7996_mcu_bcn_prot_enable(struct mt7996_dev *dev, struct ieee80211_vif *vif,
611 struct ieee80211_key_conf *key);
612int mt7996_mcu_wtbl_update_hdr_trans(struct mt7996_dev *dev,
613 struct ieee80211_vif *vif,
614 struct ieee80211_sta *sta);
615#ifdef CONFIG_MAC80211_DEBUGFS
616void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
617 struct ieee80211_sta *sta, struct dentry *dir);
618#endif
619int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,
620 bool hif2, int *irq);
621u32 mt7996_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
622
623#ifdef CONFIG_MTK_DEBUG
624int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir);
625#endif
626
627#ifdef CONFIG_NET_MEDIATEK_SOC_WED
628int mt7996_dma_rro_init(struct mt7996_dev *dev);
629#endif /* CONFIG_NET_MEDIATEK_SOC_WED */
630
631#endif