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1/* SPDX-License-Identifier: ISC */
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#ifndef __MT76_CONNAC_MCU_H
5#define __MT76_CONNAC_MCU_H
6
7#include "mt76_connac.h"
8
9#define FW_FEATURE_SET_ENCRYPT BIT(0)
10#define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1)
11#define FW_FEATURE_ENCRY_MODE BIT(4)
12#define FW_FEATURE_OVERRIDE_ADDR BIT(5)
13#define FW_FEATURE_NON_DL BIT(6)
14
15#define DL_MODE_ENCRYPT BIT(0)
16#define DL_MODE_KEY_IDX GENMASK(2, 1)
17#define DL_MODE_RESET_SEC_IV BIT(3)
18#define DL_MODE_WORKING_PDA_CR4 BIT(4)
19#define DL_MODE_VALID_RAM_ENTRY BIT(5)
20#define DL_CONFIG_ENCRY_MODE_SEL BIT(6)
21#define DL_MODE_NEED_RSP BIT(31)
22
23#define FW_START_OVERRIDE BIT(0)
24#define FW_START_WORKING_PDA_CR4 BIT(2)
25#define FW_START_WORKING_PDA_DSP BIT(3)
26
27#define PATCH_SEC_NOT_SUPPORT GENMASK(31, 0)
28#define PATCH_SEC_TYPE_MASK GENMASK(15, 0)
29#define PATCH_SEC_TYPE_INFO 0x2
30
31#define PATCH_SEC_ENC_TYPE_MASK GENMASK(31, 24)
32#define PATCH_SEC_ENC_TYPE_PLAIN 0x00
33#define PATCH_SEC_ENC_TYPE_AES 0x01
34#define PATCH_SEC_ENC_TYPE_SCRAMBLE 0x02
35#define PATCH_SEC_ENC_SCRAMBLE_INFO_MASK GENMASK(15, 0)
36#define PATCH_SEC_ENC_AES_KEY_MASK GENMASK(7, 0)
37
38enum {
39 FW_TYPE_DEFAULT = 0,
40 FW_TYPE_CLC = 2,
41 FW_TYPE_MAX_NUM = 255
42};
43
44#define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10))
45#define MCU_PKT_ID 0xa0
46
47struct mt76_connac2_mcu_txd {
48 __le32 txd[8];
49
50 __le16 len;
51 __le16 pq_id;
52
53 u8 cid;
54 u8 pkt_type;
55 u8 set_query; /* FW don't care */
56 u8 seq;
57
58 u8 uc_d2b0_rev;
59 u8 ext_cid;
60 u8 s2d_index;
61 u8 ext_cid_ack;
62
63 u32 rsv[5];
64} __packed __aligned(4);
65
66/**
67 * struct mt76_connac2_mcu_uni_txd - mcu command descriptor for connac2 and connac3
68 * @txd: hardware descriptor
69 * @len: total length not including txd
70 * @cid: command identifier
71 * @pkt_type: must be 0xa0 (cmd packet by long format)
72 * @frag_n: fragment number
73 * @seq: sequence number
74 * @checksum: 0 mean there is no checksum
75 * @s2d_index: index for command source and destination
76 * Definition | value | note
77 * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM
78 * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM
79 * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA
80 * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM
81 *
82 * @option: command option
83 * BIT[0]: UNI_CMD_OPT_BIT_ACK
84 * set to 1 to request a fw reply
85 * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY
86 * is set, mcu firmware will send response event EID = 0x01
87 * (UNI_EVENT_ID_CMD_RESULT) to the host.
88 * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD
89 * 0: original command
90 * 1: unified command
91 * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY
92 * 0: QUERY command
93 * 1: SET command
94 */
95struct mt76_connac2_mcu_uni_txd {
96 __le32 txd[8];
97
98 /* DW1 */
99 __le16 len;
100 __le16 cid;
101
102 /* DW2 */
103 u8 rsv;
104 u8 pkt_type;
105 u8 frag_n;
106 u8 seq;
107
108 /* DW3 */
109 __le16 checksum;
110 u8 s2d_index;
111 u8 option;
112
113 /* DW4 */
114 u8 rsv1[4];
115} __packed __aligned(4);
116
117struct mt76_connac2_mcu_rxd {
118 __le32 rxd[6];
119
120 __le16 len;
121 __le16 pkt_type_id;
122
123 u8 eid;
124 u8 seq;
125 u8 option;
126 u8 rsv;
127 u8 ext_eid;
128 u8 rsv1[2];
129 u8 s2d_index;
130
131 u8 tlv[];
132};
133
134struct mt76_connac2_patch_hdr {
135 char build_date[16];
136 char platform[4];
137 __be32 hw_sw_ver;
138 __be32 patch_ver;
139 __be16 checksum;
140 u16 rsv;
141 struct {
142 __be32 patch_ver;
143 __be32 subsys;
144 __be32 feature;
145 __be32 n_region;
146 __be32 crc;
147 u32 rsv[11];
148 } desc;
149} __packed;
150
151struct mt76_connac2_patch_sec {
152 __be32 type;
153 __be32 offs;
154 __be32 size;
155 union {
156 __be32 spec[13];
157 struct {
158 __be32 addr;
159 __be32 len;
160 __be32 sec_key_idx;
161 __be32 align_len;
162 u32 rsv[9];
163 } info;
164 };
165} __packed;
166
167struct mt76_connac2_fw_trailer {
168 u8 chip_id;
169 u8 eco_code;
170 u8 n_region;
171 u8 format_ver;
172 u8 format_flag;
173 u8 rsv[2];
174 char fw_ver[10];
175 char build_date[15];
176 __le32 crc;
177} __packed;
178
179struct mt76_connac2_fw_region {
180 __le32 decomp_crc;
181 __le32 decomp_len;
182 __le32 decomp_blk_sz;
183 u8 rsv[4];
184 __le32 addr;
185 __le32 len;
186 u8 feature_set;
187 u8 type;
188 u8 rsv1[14];
189} __packed;
190
191struct tlv {
192 __le16 tag;
193 __le16 len;
194 u8 data[];
195} __packed;
196
197struct bss_info_omac {
198 __le16 tag;
199 __le16 len;
200 u8 hw_bss_idx;
201 u8 omac_idx;
202 u8 band_idx;
203 u8 rsv0;
204 __le32 conn_type;
205 u32 rsv1;
206} __packed;
207
208struct bss_info_basic {
209 __le16 tag;
210 __le16 len;
211 __le32 network_type;
212 u8 active;
213 u8 rsv0;
214 __le16 bcn_interval;
215 u8 bssid[ETH_ALEN];
216 u8 wmm_idx;
217 u8 dtim_period;
218 u8 bmc_wcid_lo;
219 u8 cipher;
220 u8 phy_mode;
221 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */
222 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */
223 u8 bmc_wcid_hi; /* high Byte and version */
224 u8 rsv[2];
225} __packed;
226
227struct bss_info_rf_ch {
228 __le16 tag;
229 __le16 len;
230 u8 pri_ch;
231 u8 center_ch0;
232 u8 center_ch1;
233 u8 bw;
234 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */
235 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */
236 u8 rsv[2];
237} __packed;
238
239struct bss_info_ext_bss {
240 __le16 tag;
241 __le16 len;
242 __le32 mbss_tsf_offset; /* in unit of us */
243 u8 rsv[8];
244} __packed;
245
246enum {
247 BSS_INFO_OMAC,
248 BSS_INFO_BASIC,
249 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */
250 BSS_INFO_PM, /* sta only */
251 BSS_INFO_UAPSD, /* sta only */
252 BSS_INFO_ROAM_DETECT, /* obsoleted */
253 BSS_INFO_LQ_RM, /* obsoleted */
254 BSS_INFO_EXT_BSS,
255 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */
256 BSS_INFO_SYNC_MODE, /* obsoleted */
257 BSS_INFO_RA,
258 BSS_INFO_HW_AMSDU,
259 BSS_INFO_BSS_COLOR,
260 BSS_INFO_HE_BASIC,
261 BSS_INFO_PROTECT_INFO,
262 BSS_INFO_OFFLOAD,
263 BSS_INFO_11V_MBSSID,
264 BSS_INFO_MAX_NUM
265};
266
267/* sta_rec */
268
269struct sta_ntlv_hdr {
270 u8 rsv[2];
271 __le16 tlv_num;
272} __packed;
273
274struct sta_req_hdr {
275 u8 bss_idx;
276 u8 wlan_idx_lo;
277 __le16 tlv_num;
278 u8 is_tlv_append;
279 u8 muar_idx;
280 u8 wlan_idx_hi;
281 u8 rsv;
282} __packed;
283
284struct sta_rec_basic {
285 __le16 tag;
286 __le16 len;
287 __le32 conn_type;
288 u8 conn_state;
289 u8 qos;
290 __le16 aid;
291 u8 peer_addr[ETH_ALEN];
292#define EXTRA_INFO_VER BIT(0)
293#define EXTRA_INFO_NEW BIT(1)
294 __le16 extra_info;
295} __packed;
296
297struct sta_rec_ht {
298 __le16 tag;
299 __le16 len;
300 __le16 ht_cap;
301 u16 rsv;
302} __packed;
303
304struct sta_rec_vht {
305 __le16 tag;
306 __le16 len;
307 __le32 vht_cap;
308 __le16 vht_rx_mcs_map;
309 __le16 vht_tx_mcs_map;
310 /* mt7915 - mt7921 */
311 u8 rts_bw_sig;
312 u8 rsv[3];
313} __packed;
314
315struct sta_rec_uapsd {
316 __le16 tag;
317 __le16 len;
318 u8 dac_map;
319 u8 tac_map;
320 u8 max_sp;
321 u8 rsv0;
322 __le16 listen_interval;
323 u8 rsv1[2];
324} __packed;
325
326struct sta_rec_ba {
327 __le16 tag;
328 __le16 len;
329 u8 tid;
330 u8 ba_type;
331 u8 amsdu;
332 u8 ba_en;
333 __le16 ssn;
334 __le16 winsize;
335} __packed;
336
337struct sta_rec_he {
338 __le16 tag;
339 __le16 len;
340
341 __le32 he_cap;
342
343 u8 t_frame_dur;
344 u8 max_ampdu_exp;
345 u8 bw_set;
346 u8 device_class;
347 u8 dcm_tx_mode;
348 u8 dcm_tx_max_nss;
349 u8 dcm_rx_mode;
350 u8 dcm_rx_max_nss;
351 u8 dcm_max_ru;
352 u8 punc_pream_rx;
353 u8 pkt_ext;
354 u8 rsv1;
355
356 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
357
358 u8 rsv2[2];
359} __packed;
360
361struct sta_rec_he_v2 {
362 __le16 tag;
363 __le16 len;
364 u8 he_mac_cap[6];
365 u8 he_phy_cap[11];
366 u8 pkt_ext;
367 /* 0: BW80, 1: BW160, 2: BW8080 */
368 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
369} __packed;
370
371struct sta_rec_amsdu {
372 __le16 tag;
373 __le16 len;
374 u8 max_amsdu_num;
375 u8 max_mpdu_size;
376 u8 amsdu_en;
377 u8 rsv;
378} __packed;
379
380struct sta_rec_state {
381 __le16 tag;
382 __le16 len;
383 __le32 flags;
384 u8 state;
385 u8 vht_opmode;
386 u8 action;
387 u8 rsv[1];
388} __packed;
389
390#define RA_LEGACY_OFDM GENMASK(13, 6)
391#define RA_LEGACY_CCK GENMASK(3, 0)
392#define HT_MCS_MASK_NUM 10
393struct sta_rec_ra_info {
394 __le16 tag;
395 __le16 len;
396 __le16 legacy;
397 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM];
398} __packed;
399
400struct sta_rec_phy {
401 __le16 tag;
402 __le16 len;
403 __le16 basic_rate;
404 u8 phy_type;
405 u8 ampdu;
406 u8 rts_policy;
407 u8 rcpi;
408 u8 max_ampdu_len; /* connac3 */
409 u8 rsv[1];
410} __packed;
411
412struct sta_rec_he_6g_capa {
413 __le16 tag;
414 __le16 len;
415 __le16 capa;
416 u8 rsv[2];
417} __packed;
418
419struct sta_rec_pn_info {
420 __le16 tag;
421 __le16 len;
422 u8 pn[6];
423 u8 tsc_type;
424 u8 rsv;
425} __packed;
426
427struct sec_key {
428 u8 cipher_id;
429 u8 cipher_len;
430 u8 key_id;
431 u8 key_len;
432 u8 key[32];
433} __packed;
434
435struct sta_rec_sec {
436 __le16 tag;
437 __le16 len;
438 u8 add;
439 u8 n_cipher;
440 u8 rsv[2];
441
442 struct sec_key key[2];
443} __packed;
444
445struct sta_rec_bf {
446 __le16 tag;
447 __le16 len;
448
449 __le16 pfmu; /* 0xffff: no access right for PFMU */
450 bool su_mu; /* 0: SU, 1: MU */
451 u8 bf_cap; /* 0: iBF, 1: eBF */
452 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */
453 u8 ndpa_rate;
454 u8 ndp_rate;
455 u8 rept_poll_rate;
456 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */
457 u8 ncol;
458 u8 nrow;
459 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */
460
461 u8 mem_total;
462 u8 mem_20m;
463 struct {
464 u8 row;
465 u8 col: 6, row_msb: 2;
466 } mem[4];
467
468 __le16 smart_ant;
469 u8 se_idx;
470 u8 auto_sounding; /* b7: low traffic indicator
471 * b6: Stop sounding for this entry
472 * b5 ~ b0: postpone sounding
473 */
474 u8 ibf_timeout;
475 u8 ibf_dbw;
476 u8 ibf_ncol;
477 u8 ibf_nrow;
478 u8 nrow_gt_bw80;
479 u8 ncol_gt_bw80;
480 u8 ru_start_idx;
481 u8 ru_end_idx;
482
483 bool trigger_su;
484 bool trigger_mu;
485 bool ng16_su;
486 bool ng16_mu;
487 bool codebook42_su;
488 bool codebook75_mu;
489
490 u8 he_ltf;
491 u8 rsv[3];
492} __packed;
493
494struct sta_rec_bfee {
495 __le16 tag;
496 __le16 len;
497 bool fb_identity_matrix; /* 1: feedback identity matrix */
498 bool ignore_feedback; /* 1: ignore */
499 u8 rsv[2];
500} __packed;
501
502struct sta_rec_muru {
503 __le16 tag;
504 __le16 len;
505
506 struct {
507 bool ofdma_dl_en;
508 bool ofdma_ul_en;
509 bool mimo_dl_en;
510 bool mimo_ul_en;
511 u8 rsv[4];
512 } cfg;
513
514 struct {
515 u8 punc_pream_rx;
516 bool he_20m_in_40m_2g;
517 bool he_20m_in_160m;
518 bool he_80m_in_160m;
519 bool lt16_sigb;
520 bool rx_su_comp_sigb;
521 bool rx_su_non_comp_sigb;
522 u8 rsv;
523 } ofdma_dl;
524
525 struct {
526 u8 t_frame_dur;
527 u8 mu_cascading;
528 u8 uo_ra;
529 u8 he_2x996_tone;
530 u8 rx_t_frame_11ac;
531 u8 rx_ctrl_frame_to_mbss;
532 u8 rsv[2];
533 } ofdma_ul;
534
535 struct {
536 bool vht_mu_bfee;
537 bool partial_bw_dl_mimo;
538 u8 rsv[2];
539 } mimo_dl;
540
541 struct {
542 bool full_ul_mimo;
543 bool partial_ul_mimo;
544 u8 rsv[2];
545 } mimo_ul;
546} __packed;
547
548struct sta_phy {
549 u8 type;
550 u8 flag;
551 u8 stbc;
552 u8 sgi;
553 u8 bw;
554 u8 ldpc;
555 u8 mcs;
556 u8 nss;
557 u8 he_ltf;
558};
559
560struct sta_rec_ra {
561 __le16 tag;
562 __le16 len;
563
564 u8 valid;
565 u8 auto_rate;
566 u8 phy_mode;
567 u8 channel;
568 u8 bw;
569 u8 disable_cck;
570 u8 ht_mcs32;
571 u8 ht_gf;
572 u8 ht_mcs[4];
573 u8 mmps_mode;
574 u8 gband_256;
575 u8 af;
576 u8 auth_wapi_mode;
577 u8 rate_len;
578
579 u8 supp_mode;
580 u8 supp_cck_rate;
581 u8 supp_ofdm_rate;
582 __le32 supp_ht_mcs;
583 __le16 supp_vht_mcs[4];
584
585 u8 op_mode;
586 u8 op_vht_chan_width;
587 u8 op_vht_rx_nss;
588 u8 op_vht_rx_nss_type;
589
590 __le32 sta_cap;
591
592 struct sta_phy phy;
593} __packed;
594
595struct sta_rec_ra_fixed {
596 __le16 tag;
597 __le16 len;
598
599 __le32 field;
600 u8 op_mode;
601 u8 op_vht_chan_width;
602 u8 op_vht_rx_nss;
603 u8 op_vht_rx_nss_type;
604
605 struct sta_phy phy;
606
607 u8 spe_idx;
608 u8 short_preamble;
609 u8 is_5g;
610 u8 mmps_mode;
611} __packed;
612
613/* wtbl_rec */
614
615struct wtbl_req_hdr {
616 u8 wlan_idx_lo;
617 u8 operation;
618 __le16 tlv_num;
619 u8 wlan_idx_hi;
620 u8 rsv[3];
621} __packed;
622
623struct wtbl_generic {
624 __le16 tag;
625 __le16 len;
626 u8 peer_addr[ETH_ALEN];
627 u8 muar_idx;
628 u8 skip_tx;
629 u8 cf_ack;
630 u8 qos;
631 u8 mesh;
632 u8 adm;
633 __le16 partial_aid;
634 u8 baf_en;
635 u8 aad_om;
636} __packed;
637
638struct wtbl_rx {
639 __le16 tag;
640 __le16 len;
641 u8 rcid;
642 u8 rca1;
643 u8 rca2;
644 u8 rv;
645 u8 rsv[4];
646} __packed;
647
648struct wtbl_ht {
649 __le16 tag;
650 __le16 len;
651 u8 ht;
652 u8 ldpc;
653 u8 af;
654 u8 mm;
655 u8 rsv[4];
656} __packed;
657
658struct wtbl_vht {
659 __le16 tag;
660 __le16 len;
661 u8 ldpc;
662 u8 dyn_bw;
663 u8 vht;
664 u8 txop_ps;
665 u8 rsv[4];
666} __packed;
667
668struct wtbl_tx_ps {
669 __le16 tag;
670 __le16 len;
671 u8 txps;
672 u8 rsv[3];
673} __packed;
674
675struct wtbl_hdr_trans {
676 __le16 tag;
677 __le16 len;
678 u8 to_ds;
679 u8 from_ds;
680 u8 no_rx_trans;
681 u8 rsv;
682} __packed;
683
684struct wtbl_ba {
685 __le16 tag;
686 __le16 len;
687 /* common */
688 u8 tid;
689 u8 ba_type;
690 u8 rsv0[2];
691 /* originator only */
692 __le16 sn;
693 u8 ba_en;
694 u8 ba_winsize_idx;
695 /* originator & recipient */
696 __le16 ba_winsize;
697 /* recipient only */
698 u8 peer_addr[ETH_ALEN];
699 u8 rst_ba_tid;
700 u8 rst_ba_sel;
701 u8 rst_ba_sb;
702 u8 band_idx;
703 u8 rsv1[4];
704} __packed;
705
706struct wtbl_smps {
707 __le16 tag;
708 __le16 len;
709 u8 smps;
710 u8 rsv[3];
711} __packed;
712
713/* mt7615 only */
714
715struct wtbl_bf {
716 __le16 tag;
717 __le16 len;
718 u8 ibf;
719 u8 ebf;
720 u8 ibf_vht;
721 u8 ebf_vht;
722 u8 gid;
723 u8 pfmu_idx;
724 u8 rsv[2];
725} __packed;
726
727struct wtbl_pn {
728 __le16 tag;
729 __le16 len;
730 u8 pn[6];
731 u8 rsv[2];
732} __packed;
733
734struct wtbl_spe {
735 __le16 tag;
736 __le16 len;
737 u8 spe_idx;
738 u8 rsv[3];
739} __packed;
740
741struct wtbl_raw {
742 __le16 tag;
743 __le16 len;
744 u8 wtbl_idx;
745 u8 dw;
746 u8 rsv[2];
747 __le32 msk;
748 __le32 val;
749} __packed;
750
751#define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \
752 sizeof(struct wtbl_generic) + \
753 sizeof(struct wtbl_rx) + \
754 sizeof(struct wtbl_ht) + \
755 sizeof(struct wtbl_vht) + \
756 sizeof(struct wtbl_tx_ps) + \
757 sizeof(struct wtbl_hdr_trans) +\
758 sizeof(struct wtbl_ba) + \
759 sizeof(struct wtbl_bf) + \
760 sizeof(struct wtbl_smps) + \
761 sizeof(struct wtbl_pn) + \
762 sizeof(struct wtbl_spe))
763
764#define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
765 sizeof(struct sta_rec_basic) + \
766 sizeof(struct sta_rec_bf) + \
767 sizeof(struct sta_rec_ht) + \
768 sizeof(struct sta_rec_he) + \
769 sizeof(struct sta_rec_ba) + \
770 sizeof(struct sta_rec_vht) + \
771 sizeof(struct sta_rec_uapsd) + \
772 sizeof(struct sta_rec_amsdu) + \
773 sizeof(struct sta_rec_muru) + \
774 sizeof(struct sta_rec_bfee) + \
775 sizeof(struct sta_rec_ra) + \
776 sizeof(struct sta_rec_sec) + \
777 sizeof(struct sta_rec_ra_fixed) + \
778 sizeof(struct sta_rec_he_6g_capa) + \
779 sizeof(struct sta_rec_pn_info) + \
780 sizeof(struct tlv) + \
781 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE)
782
783enum {
784 STA_REC_BASIC,
785 STA_REC_RA,
786 STA_REC_RA_CMM_INFO,
787 STA_REC_RA_UPDATE,
788 STA_REC_BF,
789 STA_REC_AMSDU,
790 STA_REC_BA,
791 STA_REC_STATE,
792 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */
793 STA_REC_HT,
794 STA_REC_VHT,
795 STA_REC_APPS,
796 STA_REC_KEY,
797 STA_REC_WTBL,
798 STA_REC_HE,
799 STA_REC_HW_AMSDU,
800 STA_REC_WTBL_AADOM,
801 STA_REC_KEY_V2,
802 STA_REC_MURU,
803 STA_REC_MUEDCA,
804 STA_REC_BFEE,
805 STA_REC_PHY = 0x15,
806 STA_REC_HE_6G = 0x17,
807 STA_REC_HE_V2 = 0x19,
808 STA_REC_MLD = 0x20,
809 STA_REC_EHT = 0x22,
810 STA_REC_PN_INFO = 0x26,
811 STA_REC_HDRT = 0x28,
812 STA_REC_HDR_TRANS = 0x2B,
813 STA_REC_MAX_NUM
814};
815
816enum {
817 WTBL_GENERIC,
818 WTBL_RX,
819 WTBL_HT,
820 WTBL_VHT,
821 WTBL_PEER_PS, /* not used */
822 WTBL_TX_PS,
823 WTBL_HDR_TRANS,
824 WTBL_SEC_KEY,
825 WTBL_BA,
826 WTBL_RDG, /* obsoleted */
827 WTBL_PROTECT, /* not used */
828 WTBL_CLEAR, /* not used */
829 WTBL_BF,
830 WTBL_SMPS,
831 WTBL_RAW_DATA, /* debug only */
832 WTBL_PN,
833 WTBL_SPE,
834 WTBL_MAX_NUM
835};
836
837#define STA_TYPE_STA BIT(0)
838#define STA_TYPE_AP BIT(1)
839#define STA_TYPE_ADHOC BIT(2)
840#define STA_TYPE_WDS BIT(4)
841#define STA_TYPE_BC BIT(5)
842
843#define NETWORK_INFRA BIT(16)
844#define NETWORK_P2P BIT(17)
845#define NETWORK_IBSS BIT(18)
846#define NETWORK_WDS BIT(21)
847
848#define SCAN_FUNC_RANDOM_MAC BIT(0)
849#define SCAN_FUNC_SPLIT_SCAN BIT(5)
850
851#define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA)
852#define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA)
853#define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P)
854#define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P)
855#define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS)
856#define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS)
857#define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA)
858
859#define CONN_STATE_DISCONNECT 0
860#define CONN_STATE_CONNECT 1
861#define CONN_STATE_PORT_SECURE 2
862
863/* HE MAC */
864#define STA_REC_HE_CAP_HTC BIT(0)
865#define STA_REC_HE_CAP_BQR BIT(1)
866#define STA_REC_HE_CAP_BSR BIT(2)
867#define STA_REC_HE_CAP_OM BIT(3)
868#define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4)
869/* HE PHY */
870#define STA_REC_HE_CAP_DUAL_BAND BIT(5)
871#define STA_REC_HE_CAP_LDPC BIT(6)
872#define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7)
873#define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8)
874/* STBC */
875#define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9)
876#define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10)
877#define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11)
878#define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12)
879/* GI */
880#define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13)
881#define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14)
882#define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15)
883#define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16)
884#define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17)
885/* 242 TONE */
886#define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18)
887#define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19)
888#define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20)
889
890#define PHY_MODE_A BIT(0)
891#define PHY_MODE_B BIT(1)
892#define PHY_MODE_G BIT(2)
893#define PHY_MODE_GN BIT(3)
894#define PHY_MODE_AN BIT(4)
895#define PHY_MODE_AC BIT(5)
896#define PHY_MODE_AX_24G BIT(6)
897#define PHY_MODE_AX_5G BIT(7)
898
899#define PHY_MODE_AX_6G BIT(0) /* phymode_ext */
900#define PHY_MODE_BE_24G BIT(1)
901#define PHY_MODE_BE_5G BIT(2)
902#define PHY_MODE_BE_6G BIT(3)
903
904#define MODE_CCK BIT(0)
905#define MODE_OFDM BIT(1)
906#define MODE_HT BIT(2)
907#define MODE_VHT BIT(3)
908#define MODE_HE BIT(4)
909#define MODE_EHT BIT(5)
910
911#define STA_CAP_WMM BIT(0)
912#define STA_CAP_SGI_20 BIT(4)
913#define STA_CAP_SGI_40 BIT(5)
914#define STA_CAP_TX_STBC BIT(6)
915#define STA_CAP_RX_STBC BIT(7)
916#define STA_CAP_VHT_SGI_80 BIT(16)
917#define STA_CAP_VHT_SGI_160 BIT(17)
918#define STA_CAP_VHT_TX_STBC BIT(18)
919#define STA_CAP_VHT_RX_STBC BIT(19)
920#define STA_CAP_VHT_LDPC BIT(23)
921#define STA_CAP_LDPC BIT(24)
922#define STA_CAP_HT BIT(26)
923#define STA_CAP_VHT BIT(27)
924#define STA_CAP_HE BIT(28)
925
926enum {
927 PHY_TYPE_HR_DSSS_INDEX = 0,
928 PHY_TYPE_ERP_INDEX,
929 PHY_TYPE_ERP_P2P_INDEX,
930 PHY_TYPE_OFDM_INDEX,
931 PHY_TYPE_HT_INDEX,
932 PHY_TYPE_VHT_INDEX,
933 PHY_TYPE_HE_INDEX,
934 PHY_TYPE_BE_INDEX,
935 PHY_TYPE_INDEX_NUM
936};
937
938#define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX)
939#define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX)
940#define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX)
941#define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX)
942#define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX)
943#define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX)
944#define PHY_TYPE_BIT_BE BIT(PHY_TYPE_BE_INDEX)
945
946#define MT_WTBL_RATE_TX_MODE GENMASK(9, 6)
947#define MT_WTBL_RATE_MCS GENMASK(5, 0)
948#define MT_WTBL_RATE_NSS GENMASK(12, 10)
949#define MT_WTBL_RATE_HE_GI GENMASK(7, 4)
950#define MT_WTBL_RATE_GI GENMASK(3, 0)
951
952#define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5)
953#define MT_WTBL_W5_SHORT_GI_20 BIT(8)
954#define MT_WTBL_W5_SHORT_GI_40 BIT(9)
955#define MT_WTBL_W5_SHORT_GI_80 BIT(10)
956#define MT_WTBL_W5_SHORT_GI_160 BIT(11)
957#define MT_WTBL_W5_BW_CAP GENMASK(13, 12)
958#define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23)
959#define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26)
960#define MT_WTBL_W5_RATE_IDX GENMASK(31, 29)
961
962enum {
963 WTBL_RESET_AND_SET = 1,
964 WTBL_SET,
965 WTBL_QUERY,
966 WTBL_RESET_ALL
967};
968
969enum {
970 MT_BA_TYPE_INVALID,
971 MT_BA_TYPE_ORIGINATOR,
972 MT_BA_TYPE_RECIPIENT
973};
974
975enum {
976 RST_BA_MAC_TID_MATCH,
977 RST_BA_MAC_MATCH,
978 RST_BA_NO_MATCH
979};
980
981enum {
982 DEV_INFO_ACTIVE,
983 DEV_INFO_MAX_NUM
984};
985
986/* event table */
987enum {
988 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
989 MCU_EVENT_FW_START = 0x01,
990 MCU_EVENT_GENERIC = 0x01,
991 MCU_EVENT_ACCESS_REG = 0x02,
992 MCU_EVENT_MT_PATCH_SEM = 0x04,
993 MCU_EVENT_REG_ACCESS = 0x05,
994 MCU_EVENT_LP_INFO = 0x07,
995 MCU_EVENT_SCAN_DONE = 0x0d,
996 MCU_EVENT_TX_DONE = 0x0f,
997 MCU_EVENT_ROC = 0x10,
998 MCU_EVENT_BSS_ABSENCE = 0x11,
999 MCU_EVENT_BSS_BEACON_LOSS = 0x13,
1000 MCU_EVENT_CH_PRIVILEGE = 0x18,
1001 MCU_EVENT_SCHED_SCAN_DONE = 0x23,
1002 MCU_EVENT_DBG_MSG = 0x27,
1003 MCU_EVENT_TXPWR = 0xd0,
1004 MCU_EVENT_EXT = 0xed,
1005 MCU_EVENT_RESTART_DL = 0xef,
1006 MCU_EVENT_COREDUMP = 0xf0,
1007};
1008
1009/* ext event table */
1010enum {
1011 MCU_EXT_EVENT_PS_SYNC = 0x5,
1012 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
1013 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
1014 MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
1015 MCU_EXT_EVENT_RDD_REPORT = 0x3a,
1016 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
1017 MCU_EXT_EVENT_WA_TX_STAT = 0x74,
1018 MCU_EXT_EVENT_BCC_NOTIFY = 0x75,
1019 MCU_EXT_EVENT_MURU_CTRL = 0x9f,
1020};
1021
1022/* unified event table */
1023enum {
1024 MCU_UNI_EVENT_RESULT = 0x01,
1025 MCU_UNI_EVENT_FW_LOG_2_HOST = 0x04,
1026 MCU_UNI_EVENT_ACCESS_REG = 0x6,
1027 MCU_UNI_EVENT_IE_COUNTDOWN = 0x09,
1028 MCU_UNI_EVENT_COREDUMP = 0x0a,
1029 MCU_UNI_EVENT_BSS_BEACON_LOSS = 0x0c,
1030 MCU_UNI_EVENT_SCAN_DONE = 0x0e,
1031 MCU_UNI_EVENT_RDD_REPORT = 0x11,
1032 MCU_UNI_EVENT_ROC = 0x27,
1033 MCU_UNI_EVENT_TX_DONE = 0x2d,
1034 MCU_UNI_EVENT_THERMAL = 0x35,
1035 MCU_UNI_EVENT_NIC_CAPAB = 0x43,
1036 MCU_UNI_EVENT_WED_RRO = 0x57,
1037 MCU_UNI_EVENT_PER_STA_INFO = 0x6d,
1038 MCU_UNI_EVENT_ALL_STA_INFO = 0x6e,
1039};
1040
1041#define MCU_UNI_CMD_EVENT BIT(1)
1042#define MCU_UNI_CMD_UNSOLICITED_EVENT BIT(2)
1043
1044enum {
1045 MCU_Q_QUERY,
1046 MCU_Q_SET,
1047 MCU_Q_RESERVED,
1048 MCU_Q_NA
1049};
1050
1051enum {
1052 MCU_S2D_H2N,
1053 MCU_S2D_C2N,
1054 MCU_S2D_H2C,
1055 MCU_S2D_H2CN
1056};
1057
1058enum {
1059 PATCH_NOT_DL_SEM_FAIL,
1060 PATCH_IS_DL,
1061 PATCH_NOT_DL_SEM_SUCCESS,
1062 PATCH_REL_SEM_SUCCESS
1063};
1064
1065enum {
1066 FW_STATE_INITIAL,
1067 FW_STATE_FW_DOWNLOAD,
1068 FW_STATE_NORMAL_OPERATION,
1069 FW_STATE_NORMAL_TRX,
1070 FW_STATE_RDY = 7
1071};
1072
1073enum {
1074 CH_SWITCH_NORMAL = 0,
1075 CH_SWITCH_SCAN = 3,
1076 CH_SWITCH_MCC = 4,
1077 CH_SWITCH_DFS = 5,
1078 CH_SWITCH_BACKGROUND_SCAN_START = 6,
1079 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
1080 CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
1081 CH_SWITCH_SCAN_BYPASS_DPD = 9
1082};
1083
1084enum {
1085 THERMAL_SENSOR_TEMP_QUERY,
1086 THERMAL_SENSOR_MANUAL_CTRL,
1087 THERMAL_SENSOR_INFO_QUERY,
1088 THERMAL_SENSOR_TASK_CTRL,
1089};
1090
1091enum mcu_cipher_type {
1092 MCU_CIPHER_NONE = 0,
1093 MCU_CIPHER_WEP40,
1094 MCU_CIPHER_WEP104,
1095 MCU_CIPHER_WEP128,
1096 MCU_CIPHER_TKIP,
1097 MCU_CIPHER_AES_CCMP,
1098 MCU_CIPHER_CCMP_256,
1099 MCU_CIPHER_GCMP,
1100 MCU_CIPHER_GCMP_256,
1101 MCU_CIPHER_WAPI,
1102 MCU_CIPHER_BIP_CMAC_128,
1103 MCU_CIPHER_BIP_CMAC_256,
1104 MCU_CIPHER_BCN_PROT_CMAC_128,
1105 MCU_CIPHER_BCN_PROT_CMAC_256,
1106 MCU_CIPHER_BCN_PROT_GMAC_128,
1107 MCU_CIPHER_BCN_PROT_GMAC_256,
1108 MCU_CIPHER_BIP_GMAC_128,
1109 MCU_CIPHER_BIP_GMAC_256,
1110};
1111
1112enum {
1113 EE_MODE_EFUSE,
1114 EE_MODE_BUFFER,
1115};
1116
1117enum {
1118 EE_FORMAT_BIN,
1119 EE_FORMAT_WHOLE,
1120 EE_FORMAT_MULTIPLE,
1121};
1122
1123enum {
1124 MCU_PHY_STATE_TX_RATE,
1125 MCU_PHY_STATE_RX_RATE,
1126 MCU_PHY_STATE_RSSI,
1127 MCU_PHY_STATE_CONTENTION_RX_RATE,
1128 MCU_PHY_STATE_OFDMLQ_CNINFO,
1129};
1130
1131#define MCU_CMD_ACK BIT(0)
1132#define MCU_CMD_UNI BIT(1)
1133#define MCU_CMD_SET BIT(2)
1134
1135#define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \
1136 MCU_CMD_SET)
1137#define MCU_CMD_UNI_QUERY_ACK (MCU_CMD_ACK | MCU_CMD_UNI)
1138
1139#define __MCU_CMD_FIELD_ID GENMASK(7, 0)
1140#define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8)
1141#define __MCU_CMD_FIELD_QUERY BIT(16)
1142#define __MCU_CMD_FIELD_UNI BIT(17)
1143#define __MCU_CMD_FIELD_CE BIT(18)
1144#define __MCU_CMD_FIELD_WA BIT(19)
1145#define __MCU_CMD_FIELD_WM BIT(20)
1146
1147#define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, \
1148 MCU_CMD_##_t)
1149#define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \
1150 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
1151 MCU_EXT_CMD_##_t))
1152#define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY)
1153#define MCU_UNI_CMD(_t) (__MCU_CMD_FIELD_UNI | \
1154 FIELD_PREP(__MCU_CMD_FIELD_ID, \
1155 MCU_UNI_CMD_##_t))
1156#define MCU_CE_CMD(_t) (__MCU_CMD_FIELD_CE | \
1157 FIELD_PREP(__MCU_CMD_FIELD_ID, \
1158 MCU_CE_CMD_##_t))
1159#define MCU_CE_QUERY(_t) (MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY)
1160
1161#define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA)
1162#define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA)
1163#define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \
1164 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
1165 MCU_WA_PARAM_CMD_##_t))
1166
1167#define MCU_WM_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \
1168 __MCU_CMD_FIELD_WM)
1169#define MCU_WM_UNI_CMD_QUERY(_t) (MCU_UNI_CMD(_t) | \
1170 __MCU_CMD_FIELD_QUERY | \
1171 __MCU_CMD_FIELD_WM)
1172#define MCU_WA_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \
1173 __MCU_CMD_FIELD_WA)
1174#define MCU_WMWA_UNI_CMD(_t) (MCU_WM_UNI_CMD(_t) | \
1175 __MCU_CMD_FIELD_WA)
1176
1177enum {
1178 MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
1179 MCU_EXT_CMD_RF_REG_ACCESS = 0x02,
1180 MCU_EXT_CMD_RF_TEST = 0x04,
1181 MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
1182 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
1183 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
1184 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
1185 MCU_EXT_CMD_TXBF_ACTION = 0x1e,
1186 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
1187 MCU_EXT_CMD_THERMAL_PROT = 0x23,
1188 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
1189 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
1190 MCU_EXT_CMD_EDCA_UPDATE = 0x27,
1191 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
1192 MCU_EXT_CMD_THERMAL_CTRL = 0x2c,
1193 MCU_EXT_CMD_WTBL_UPDATE = 0x32,
1194 MCU_EXT_CMD_SET_DRR_CTRL = 0x36,
1195 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
1196 MCU_EXT_CMD_ATE_CTRL = 0x3d,
1197 MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
1198 MCU_EXT_CMD_DBDC_CTRL = 0x45,
1199 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
1200 MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
1201 MCU_EXT_CMD_MUAR_UPDATE = 0x48,
1202 MCU_EXT_CMD_BCN_OFFLOAD = 0x49,
1203 MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a,
1204 MCU_EXT_CMD_SET_RX_PATH = 0x4e,
1205 MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f,
1206 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
1207 MCU_EXT_CMD_RXDCOC_CAL = 0x59,
1208 MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
1209 MCU_EXT_CMD_TXDPD_CAL = 0x60,
1210 MCU_EXT_CMD_CAL_CACHE = 0x67,
1211 MCU_EXT_CMD_RED_ENABLE = 0x68,
1212 MCU_EXT_CMD_SET_RADAR_TH = 0x7c,
1213 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d,
1214 MCU_EXT_CMD_MWDS_SUPPORT = 0x80,
1215 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81,
1216 MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94,
1217 MCU_EXT_CMD_FW_DBG_CTRL = 0x95,
1218 MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a,
1219 MCU_EXT_CMD_SET_RDD_TH = 0x9d,
1220 MCU_EXT_CMD_MURU_CTRL = 0x9f,
1221 MCU_EXT_CMD_SET_SPR = 0xa8,
1222 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab,
1223 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
1224 MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
1225};
1226
1227enum {
1228 MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01,
1229 MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02,
1230 MCU_UNI_CMD_STA_REC_UPDATE = 0x03,
1231 MCU_UNI_CMD_EDCA_UPDATE = 0x04,
1232 MCU_UNI_CMD_SUSPEND = 0x05,
1233 MCU_UNI_CMD_OFFLOAD = 0x06,
1234 MCU_UNI_CMD_HIF_CTRL = 0x07,
1235 MCU_UNI_CMD_BAND_CONFIG = 0x08,
1236 MCU_UNI_CMD_REPT_MUAR = 0x09,
1237 MCU_UNI_CMD_WSYS_CONFIG = 0x0b,
1238 MCU_UNI_CMD_REG_ACCESS = 0x0d,
1239 MCU_UNI_CMD_CHIP_CONFIG = 0x0e,
1240 MCU_UNI_CMD_POWER_CTRL = 0x0f,
1241 MCU_UNI_CMD_RX_HDR_TRANS = 0x12,
1242 MCU_UNI_CMD_SER = 0x13,
1243 MCU_UNI_CMD_TWT = 0x14,
1244 MCU_UNI_CMD_SET_DOMAIN_INFO = 0x15,
1245 MCU_UNI_CMD_SCAN_REQ = 0x16,
1246 MCU_UNI_CMD_RDD_CTRL = 0x19,
1247 MCU_UNI_CMD_GET_MIB_INFO = 0x22,
1248 MCU_UNI_CMD_GET_STAT_INFO = 0x23,
1249 MCU_UNI_CMD_SNIFFER = 0x24,
1250 MCU_UNI_CMD_SR = 0x25,
1251 MCU_UNI_CMD_ROC = 0x27,
1252 MCU_UNI_CMD_SET_DBDC_PARMS = 0x28,
1253 MCU_UNI_CMD_TXPOWER = 0x2b,
1254 MCU_UNI_CMD_SET_POWER_LIMIT = 0x2c,
1255 MCU_UNI_CMD_EFUSE_CTRL = 0x2d,
1256 MCU_UNI_CMD_RA = 0x2f,
1257 MCU_UNI_CMD_MURU = 0x31,
1258 MCU_UNI_CMD_BF = 0x33,
1259 MCU_UNI_CMD_CHANNEL_SWITCH = 0x34,
1260 MCU_UNI_CMD_THERMAL = 0x35,
1261 MCU_UNI_CMD_VOW = 0x37,
1262 MCU_UNI_CMD_FIXED_RATE_TABLE = 0x40,
1263 MCU_UNI_CMD_RRO = 0x57,
1264 MCU_UNI_CMD_OFFCH_SCAN_CTRL = 0x58,
1265 MCU_UNI_CMD_PER_STA_INFO = 0x6d,
1266 MCU_UNI_CMD_ALL_STA_INFO = 0x6e,
1267 MCU_UNI_CMD_ASSERT_DUMP = 0x6f,
1268};
1269
1270enum {
1271 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01,
1272 MCU_CMD_FW_START_REQ = 0x02,
1273 MCU_CMD_INIT_ACCESS_REG = 0x3,
1274 MCU_CMD_NIC_POWER_CTRL = 0x4,
1275 MCU_CMD_PATCH_START_REQ = 0x05,
1276 MCU_CMD_PATCH_FINISH_REQ = 0x07,
1277 MCU_CMD_PATCH_SEM_CONTROL = 0x10,
1278 MCU_CMD_WA_PARAM = 0xc4,
1279 MCU_CMD_EXT_CID = 0xed,
1280 MCU_CMD_FW_SCATTER = 0xee,
1281 MCU_CMD_RESTART_DL_REQ = 0xef,
1282};
1283
1284/* offload mcu commands */
1285enum {
1286 MCU_CE_CMD_TEST_CTRL = 0x01,
1287 MCU_CE_CMD_START_HW_SCAN = 0x03,
1288 MCU_CE_CMD_SET_PS_PROFILE = 0x05,
1289 MCU_CE_CMD_SET_RX_FILTER = 0x0a,
1290 MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f,
1291 MCU_CE_CMD_SET_BSS_CONNECTED = 0x16,
1292 MCU_CE_CMD_SET_BSS_ABORT = 0x17,
1293 MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b,
1294 MCU_CE_CMD_SET_ROC = 0x1c,
1295 MCU_CE_CMD_SET_EDCA_PARMS = 0x1d,
1296 MCU_CE_CMD_SET_P2P_OPPPS = 0x33,
1297 MCU_CE_CMD_SET_CLC = 0x5c,
1298 MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d,
1299 MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61,
1300 MCU_CE_CMD_SCHED_SCAN_REQ = 0x62,
1301 MCU_CE_CMD_GET_NIC_CAPAB = 0x8a,
1302 MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0,
1303 MCU_CE_CMD_REG_WRITE = 0xc0,
1304 MCU_CE_CMD_REG_READ = 0xc0,
1305 MCU_CE_CMD_CHIP_CONFIG = 0xca,
1306 MCU_CE_CMD_FWLOG_2_HOST = 0xc5,
1307 MCU_CE_CMD_GET_WTBL = 0xcd,
1308 MCU_CE_CMD_GET_TXPWR = 0xd0,
1309};
1310
1311enum {
1312 PATCH_SEM_RELEASE,
1313 PATCH_SEM_GET
1314};
1315
1316enum {
1317 UNI_BSS_INFO_BASIC = 0,
1318 UNI_BSS_INFO_RA = 1,
1319 UNI_BSS_INFO_RLM = 2,
1320 UNI_BSS_INFO_BSS_COLOR = 4,
1321 UNI_BSS_INFO_HE_BASIC = 5,
1322 UNI_BSS_INFO_11V_MBSSID = 6,
1323 UNI_BSS_INFO_BCN_CONTENT = 7,
1324 UNI_BSS_INFO_BCN_CSA = 8,
1325 UNI_BSS_INFO_BCN_BCC = 9,
1326 UNI_BSS_INFO_BCN_MBSSID = 10,
1327 UNI_BSS_INFO_RATE = 11,
1328 UNI_BSS_INFO_QBSS = 15,
1329 UNI_BSS_INFO_SEC = 16,
1330 UNI_BSS_INFO_BCN_PROT = 17,
1331 UNI_BSS_INFO_TXCMD = 18,
1332 UNI_BSS_INFO_UAPSD = 19,
1333 UNI_BSS_INFO_PS = 21,
1334 UNI_BSS_INFO_BCNFT = 22,
1335 UNI_BSS_INFO_IFS_TIME = 23,
1336 UNI_BSS_INFO_OFFLOAD = 25,
1337 UNI_BSS_INFO_MLD = 26,
1338 UNI_BSS_INFO_PM_DISABLE = 27,
1339};
1340
1341enum {
1342 UNI_OFFLOAD_OFFLOAD_ARP,
1343 UNI_OFFLOAD_OFFLOAD_ND,
1344 UNI_OFFLOAD_OFFLOAD_GTK_REKEY,
1345 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT,
1346};
1347
1348enum UNI_ALL_STA_INFO_TAG {
1349 UNI_ALL_STA_TXRX_RATE,
1350 UNI_ALL_STA_TX_STAT,
1351 UNI_ALL_STA_TXRX_ADM_STAT,
1352 UNI_ALL_STA_TXRX_AIR_TIME,
1353 UNI_ALL_STA_DATA_TX_RETRY_COUNT,
1354 UNI_ALL_STA_GI_MODE,
1355 UNI_ALL_STA_TXRX_MSDU_COUNT,
1356 UNI_ALL_STA_MAX_NUM
1357};
1358
1359enum {
1360 MT_NIC_CAP_TX_RESOURCE,
1361 MT_NIC_CAP_TX_EFUSE_ADDR,
1362 MT_NIC_CAP_COEX,
1363 MT_NIC_CAP_SINGLE_SKU,
1364 MT_NIC_CAP_CSUM_OFFLOAD,
1365 MT_NIC_CAP_HW_VER,
1366 MT_NIC_CAP_SW_VER,
1367 MT_NIC_CAP_MAC_ADDR,
1368 MT_NIC_CAP_PHY,
1369 MT_NIC_CAP_MAC,
1370 MT_NIC_CAP_FRAME_BUF,
1371 MT_NIC_CAP_BEAM_FORM,
1372 MT_NIC_CAP_LOCATION,
1373 MT_NIC_CAP_MUMIMO,
1374 MT_NIC_CAP_BUFFER_MODE_INFO,
1375 MT_NIC_CAP_HW_ADIE_VERSION = 0x14,
1376 MT_NIC_CAP_ANTSWP = 0x16,
1377 MT_NIC_CAP_WFDMA_REALLOC,
1378 MT_NIC_CAP_6G,
1379 MT_NIC_CAP_CHIP_CAP = 0x20,
1380};
1381
1382#define UNI_WOW_DETECT_TYPE_MAGIC BIT(0)
1383#define UNI_WOW_DETECT_TYPE_ANY BIT(1)
1384#define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2)
1385#define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3)
1386#define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4)
1387#define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5)
1388#define UNI_WOW_DETECT_TYPE_BITMAP BIT(6)
1389
1390enum {
1391 UNI_SUSPEND_MODE_SETTING,
1392 UNI_SUSPEND_WOW_CTRL,
1393 UNI_SUSPEND_WOW_GPIO_PARAM,
1394 UNI_SUSPEND_WOW_WAKEUP_PORT,
1395 UNI_SUSPEND_WOW_PATTERN,
1396};
1397
1398enum {
1399 WOW_USB = 1,
1400 WOW_PCIE = 2,
1401 WOW_GPIO = 3,
1402};
1403
1404struct mt76_connac_bss_basic_tlv {
1405 __le16 tag;
1406 __le16 len;
1407 u8 active;
1408 u8 omac_idx;
1409 u8 hw_bss_idx;
1410 u8 band_idx;
1411 __le32 conn_type;
1412 u8 conn_state;
1413 u8 wmm_idx;
1414 u8 bssid[ETH_ALEN];
1415 __le16 bmc_tx_wlan_idx;
1416 __le16 bcn_interval;
1417 u8 dtim_period;
1418 u8 phymode; /* bit(0): A
1419 * bit(1): B
1420 * bit(2): G
1421 * bit(3): GN
1422 * bit(4): AN
1423 * bit(5): AC
1424 * bit(6): AX2
1425 * bit(7): AX5
1426 * bit(8): AX6
1427 */
1428 __le16 sta_idx;
1429 __le16 nonht_basic_phy;
1430 u8 phymode_ext; /* bit(0) AX_6G */
1431 u8 pad[1];
1432} __packed;
1433
1434struct mt76_connac_bss_qos_tlv {
1435 __le16 tag;
1436 __le16 len;
1437 u8 qos;
1438 u8 pad[3];
1439} __packed;
1440
1441struct mt76_connac_beacon_loss_event {
1442 u8 bss_idx;
1443 u8 reason;
1444 u8 pad[2];
1445} __packed;
1446
1447struct mt76_connac_mcu_bss_event {
1448 u8 bss_idx;
1449 u8 is_absent;
1450 u8 free_quota;
1451 u8 pad;
1452} __packed;
1453
1454struct mt76_connac_mcu_scan_ssid {
1455 __le32 ssid_len;
1456 u8 ssid[IEEE80211_MAX_SSID_LEN];
1457} __packed;
1458
1459struct mt76_connac_mcu_scan_channel {
1460 u8 band; /* 1: 2.4GHz
1461 * 2: 5.0GHz
1462 * Others: Reserved
1463 */
1464 u8 channel_num;
1465} __packed;
1466
1467struct mt76_connac_mcu_scan_match {
1468 __le32 rssi_th;
1469 u8 ssid[IEEE80211_MAX_SSID_LEN];
1470 u8 ssid_len;
1471 u8 rsv[3];
1472} __packed;
1473
1474struct mt76_connac_hw_scan_req {
1475 u8 seq_num;
1476 u8 bss_idx;
1477 u8 scan_type; /* 0: PASSIVE SCAN
1478 * 1: ACTIVE SCAN
1479 */
1480 u8 ssid_type; /* BIT(0) wildcard SSID
1481 * BIT(1) P2P wildcard SSID
1482 * BIT(2) specified SSID + wildcard SSID
1483 * BIT(2) + ssid_type_ext BIT(0) specified SSID only
1484 */
1485 u8 ssids_num;
1486 u8 probe_req_num; /* Number of probe request for each SSID */
1487 u8 scan_func; /* BIT(0) Enable random MAC scan
1488 * BIT(1) Disable DBDC scan type 1~3.
1489 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan).
1490 */
1491 u8 version; /* 0: Not support fields after ies.
1492 * 1: Support fields after ies.
1493 */
1494 struct mt76_connac_mcu_scan_ssid ssids[4];
1495 __le16 probe_delay_time;
1496 __le16 channel_dwell_time; /* channel Dwell interval */
1497 __le16 timeout_value;
1498 u8 channel_type; /* 0: Full channels
1499 * 1: Only 2.4GHz channels
1500 * 2: Only 5GHz channels
1501 * 3: P2P social channel only (channel #1, #6 and #11)
1502 * 4: Specified channels
1503 * Others: Reserved
1504 */
1505 u8 channels_num; /* valid when channel_type is 4 */
1506 /* valid when channels_num is set */
1507 struct mt76_connac_mcu_scan_channel channels[32];
1508 __le16 ies_len;
1509 u8 ies[MT76_CONNAC_SCAN_IE_LEN];
1510 /* following fields are valid if version > 0 */
1511 u8 ext_channels_num;
1512 u8 ext_ssids_num;
1513 __le16 channel_min_dwell_time;
1514 struct mt76_connac_mcu_scan_channel ext_channels[32];
1515 struct mt76_connac_mcu_scan_ssid ext_ssids[6];
1516 u8 bssid[ETH_ALEN];
1517 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */
1518 u8 pad[63];
1519 u8 ssid_type_ext;
1520} __packed;
1521
1522#define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64
1523
1524struct mt76_connac_hw_scan_done {
1525 u8 seq_num;
1526 u8 sparse_channel_num;
1527 struct mt76_connac_mcu_scan_channel sparse_channel;
1528 u8 complete_channel_num;
1529 u8 current_state;
1530 u8 version;
1531 u8 pad;
1532 __le32 beacon_scan_num;
1533 u8 pno_enabled;
1534 u8 pad2[3];
1535 u8 sparse_channel_valid_num;
1536 u8 pad3[3];
1537 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1538 /* idle format for channel_idle_time
1539 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms)
1540 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms)
1541 * 2: dwell time (16us)
1542 */
1543 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1544 /* beacon and probe response count */
1545 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1546 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1547 __le32 beacon_2g_num;
1548 __le32 beacon_5g_num;
1549} __packed;
1550
1551struct mt76_connac_sched_scan_req {
1552 u8 version;
1553 u8 seq_num;
1554 u8 stop_on_match;
1555 u8 ssids_num;
1556 u8 match_num;
1557 u8 pad;
1558 __le16 ie_len;
1559 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID];
1560 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH];
1561 u8 channel_type;
1562 u8 channels_num;
1563 u8 intervals_num;
1564 u8 scan_func; /* MT7663: BIT(0) eable random mac address */
1565 struct mt76_connac_mcu_scan_channel channels[64];
1566 __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL];
1567 union {
1568 struct {
1569 u8 random_mac[ETH_ALEN];
1570 u8 pad2[58];
1571 } mt7663;
1572 struct {
1573 u8 bss_idx;
1574 u8 pad1[3];
1575 __le32 delay;
1576 u8 pad2[12];
1577 u8 random_mac[ETH_ALEN];
1578 u8 pad3[38];
1579 } mt7921;
1580 };
1581} __packed;
1582
1583struct mt76_connac_sched_scan_done {
1584 u8 seq_num;
1585 u8 status; /* 0: ssid found */
1586 __le16 pad;
1587} __packed;
1588
1589struct bss_info_uni_bss_color {
1590 __le16 tag;
1591 __le16 len;
1592 u8 enable;
1593 u8 bss_color;
1594 u8 rsv[2];
1595} __packed;
1596
1597struct bss_info_uni_he {
1598 __le16 tag;
1599 __le16 len;
1600 __le16 he_rts_thres;
1601 u8 he_pe_duration;
1602 u8 su_disable;
1603 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
1604 u8 rsv[2];
1605} __packed;
1606
1607struct bss_info_uni_mbssid {
1608 __le16 tag;
1609 __le16 len;
1610 u8 max_indicator;
1611 u8 mbss_idx;
1612 u8 tx_bss_omac_idx;
1613 u8 rsv;
1614} __packed;
1615
1616struct mt76_connac_gtk_rekey_tlv {
1617 __le16 tag;
1618 __le16 len;
1619 u8 kek[NL80211_KEK_LEN];
1620 u8 kck[NL80211_KCK_LEN];
1621 u8 replay_ctr[NL80211_REPLAY_CTR_LEN];
1622 u8 rekey_mode; /* 0: rekey offload enable
1623 * 1: rekey offload disable
1624 * 2: rekey update
1625 */
1626 u8 keyid;
1627 u8 option; /* 1: rekey data update without enabling offload */
1628 u8 pad[1];
1629 __le32 proto; /* WPA-RSN-WAPI-OPSN */
1630 __le32 pairwise_cipher;
1631 __le32 group_cipher;
1632 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */
1633 __le32 mgmt_group_cipher;
1634 u8 reserverd[4];
1635} __packed;
1636
1637#define MT76_CONNAC_WOW_MASK_MAX_LEN 16
1638#define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128
1639
1640struct mt76_connac_wow_pattern_tlv {
1641 __le16 tag;
1642 __le16 len;
1643 u8 index; /* pattern index */
1644 u8 enable; /* 0: disable
1645 * 1: enable
1646 */
1647 u8 data_len; /* pattern length */
1648 u8 pad;
1649 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN];
1650 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN];
1651 u8 rsv[4];
1652} __packed;
1653
1654struct mt76_connac_wow_ctrl_tlv {
1655 __le16 tag;
1656 __le16 len;
1657 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START
1658 * 0x2: PM_WOWLAN_REQ_STOP
1659 * 0x3: PM_WOWLAN_PARAM_CLEAR
1660 */
1661 u8 trigger; /* 0: NONE
1662 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT
1663 * BIT(1): NL80211_WOWLAN_TRIG_ANY
1664 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT
1665 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE
1666 * BIT(4): BEACON_LOST
1667 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT
1668 */
1669 u8 wakeup_hif; /* 0x0: HIF_SDIO
1670 * 0x1: HIF_USB
1671 * 0x2: HIF_PCIE
1672 * 0x3: HIF_GPIO
1673 */
1674 u8 pad;
1675 u8 rsv[4];
1676} __packed;
1677
1678struct mt76_connac_wow_gpio_param_tlv {
1679 __le16 tag;
1680 __le16 len;
1681 u8 gpio_pin;
1682 u8 trigger_lvl;
1683 u8 pad[2];
1684 __le32 gpio_interval;
1685 u8 rsv[4];
1686} __packed;
1687
1688struct mt76_connac_arpns_tlv {
1689 __le16 tag;
1690 __le16 len;
1691 u8 mode;
1692 u8 ips_num;
1693 u8 option;
1694 u8 pad[1];
1695} __packed;
1696
1697struct mt76_connac_suspend_tlv {
1698 __le16 tag;
1699 __le16 len;
1700 u8 enable; /* 0: suspend mode disabled
1701 * 1: suspend mode enabled
1702 */
1703 u8 mdtim; /* LP parameter */
1704 u8 wow_suspend; /* 0: update by origin policy
1705 * 1: update by wow dtim
1706 */
1707 u8 pad[5];
1708} __packed;
1709
1710enum mt76_sta_info_state {
1711 MT76_STA_INFO_STATE_NONE,
1712 MT76_STA_INFO_STATE_AUTH,
1713 MT76_STA_INFO_STATE_ASSOC
1714};
1715
1716struct mt76_sta_cmd_info {
1717 struct ieee80211_sta *sta;
1718 struct mt76_wcid *wcid;
1719
1720 struct ieee80211_vif *vif;
1721
1722 bool offload_fw;
1723 bool enable;
1724 bool newly;
1725 int cmd;
1726 u8 rcpi;
1727 u8 state;
1728};
1729
1730#define MT_SKU_POWER_LIMIT 161
1731
1732struct mt76_connac_sku_tlv {
1733 u8 channel;
1734 s8 pwr_limit[MT_SKU_POWER_LIMIT];
1735} __packed;
1736
1737struct mt76_connac_tx_power_limit_tlv {
1738 /* DW0 - common info*/
1739 u8 ver;
1740 u8 pad0;
1741 __le16 len;
1742 /* DW1 - cmd hint */
1743 u8 n_chan; /* # channel */
1744 u8 band; /* 2.4GHz - 5GHz - 6GHz */
1745 u8 last_msg;
1746 u8 pad1;
1747 /* DW3 */
1748 u8 alpha2[4]; /* regulatory_request.alpha2 */
1749 u8 pad2[32];
1750} __packed;
1751
1752struct mt76_connac_config {
1753 __le16 id;
1754 u8 type;
1755 u8 resp_type;
1756 __le16 data_size;
1757 __le16 resv;
1758 u8 data[320];
1759} __packed;
1760
1761struct mt76_connac_mcu_uni_event {
1762 u8 cid;
1763 u8 pad[3];
1764 __le32 status; /* 0: success, others: fail */
1765} __packed;
1766
1767struct mt76_connac_mcu_reg_event {
1768 __le32 reg;
1769 __le32 val;
1770} __packed;
1771
1772static inline enum mcu_cipher_type
1773mt76_connac_mcu_get_cipher(int cipher)
1774{
1775 switch (cipher) {
1776 case WLAN_CIPHER_SUITE_WEP40:
1777 return MCU_CIPHER_WEP40;
1778 case WLAN_CIPHER_SUITE_WEP104:
1779 return MCU_CIPHER_WEP104;
1780 case WLAN_CIPHER_SUITE_TKIP:
1781 return MCU_CIPHER_TKIP;
1782 case WLAN_CIPHER_SUITE_AES_CMAC:
1783 return MCU_CIPHER_BIP_CMAC_128;
1784 case WLAN_CIPHER_SUITE_CCMP:
1785 return MCU_CIPHER_AES_CCMP;
1786 case WLAN_CIPHER_SUITE_CCMP_256:
1787 return MCU_CIPHER_CCMP_256;
1788 case WLAN_CIPHER_SUITE_GCMP:
1789 return MCU_CIPHER_GCMP;
1790 case WLAN_CIPHER_SUITE_GCMP_256:
1791 return MCU_CIPHER_GCMP_256;
1792 case WLAN_CIPHER_SUITE_BIP_GMAC_128:
1793 return MCU_CIPHER_BIP_GMAC_128;
1794 case WLAN_CIPHER_SUITE_BIP_GMAC_256:
1795 return MCU_CIPHER_BIP_GMAC_256;
1796 case WLAN_CIPHER_SUITE_BIP_CMAC_256:
1797 return MCU_CIPHER_BIP_CMAC_256;
1798 case WLAN_CIPHER_SUITE_SMS4:
1799 return MCU_CIPHER_WAPI;
1800 default:
1801 return MCU_CIPHER_NONE;
1802 }
1803}
1804
1805static inline u32
1806mt76_connac_mcu_gen_dl_mode(struct mt76_dev *dev, u8 feature_set, bool is_wa)
1807{
1808 u32 ret = 0;
1809
1810 ret |= feature_set & FW_FEATURE_SET_ENCRYPT ?
1811 DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV : 0;
1812 if (is_mt7921(dev) || is_mt7925(dev))
1813 ret |= feature_set & FW_FEATURE_ENCRY_MODE ?
1814 DL_CONFIG_ENCRY_MODE_SEL : 0;
1815 ret |= FIELD_PREP(DL_MODE_KEY_IDX,
1816 FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set));
1817 ret |= DL_MODE_NEED_RSP;
1818 ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0;
1819
1820 return ret;
1821}
1822
1823#define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id)
1824#define to_wcid_hi(id) FIELD_GET(GENMASK(10, 8), (u16)id)
1825
1826static inline void
1827mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid,
1828 u8 *wlan_idx_lo, u8 *wlan_idx_hi)
1829{
1830 *wlan_idx_hi = 0;
1831
1832 if (!is_connac_v1(dev)) {
1833 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0;
1834 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0;
1835 } else {
1836 *wlan_idx_lo = wcid ? wcid->idx : 0;
1837 }
1838}
1839
1840struct sk_buff *
1841__mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
1842 struct mt76_wcid *wcid, int len);
1843static inline struct sk_buff *
1844mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
1845 struct mt76_wcid *wcid)
1846{
1847 return __mt76_connac_mcu_alloc_sta_req(dev, mvif, wcid,
1848 MT76_CONNAC_STA_UPDATE_MAX_SIZE);
1849}
1850
1851struct wtbl_req_hdr *
1852mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid,
1853 int cmd, void *sta_wtbl, struct sk_buff **skb);
1854struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag,
1855 int len, void *sta_ntlv,
1856 void *sta_wtbl);
1857static inline struct tlv *
1858mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len)
1859{
1860 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL);
1861}
1862
1863int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy);
1864int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif);
1865void mt76_connac_mcu_sta_basic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1866 struct ieee80211_vif *vif,
1867 struct ieee80211_sta *sta, bool enable,
1868 bool newly);
1869void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1870 struct ieee80211_vif *vif,
1871 struct ieee80211_sta *sta, void *sta_wtbl,
1872 void *wtbl_tlv);
1873void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb,
1874 struct ieee80211_vif *vif,
1875 struct mt76_wcid *wcid,
1876 void *sta_wtbl, void *wtbl_tlv);
1877int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev,
1878 struct ieee80211_vif *vif,
1879 struct mt76_wcid *wcid, int cmd);
1880void mt76_connac_mcu_sta_he_tlv_v2(struct sk_buff *skb, struct ieee80211_sta *sta);
1881u8 mt76_connac_get_phy_mode_v2(struct mt76_phy *mphy, struct ieee80211_vif *vif,
1882 enum nl80211_band band, struct ieee80211_sta *sta);
1883int mt76_connac_mcu_wtbl_update_hdr_trans(struct mt76_dev *dev,
1884 struct ieee80211_vif *vif,
1885 struct ieee80211_sta *sta);
1886void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb,
1887 struct ieee80211_sta *sta,
1888 struct ieee80211_vif *vif,
1889 u8 rcpi, u8 state);
1890void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1891 struct ieee80211_sta *sta, void *sta_wtbl,
1892 void *wtbl_tlv, bool ht_ldpc, bool vht_ldpc);
1893void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1894 struct ieee80211_ampdu_params *params,
1895 bool enable, bool tx, void *sta_wtbl,
1896 void *wtbl_tlv);
1897void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb,
1898 struct ieee80211_ampdu_params *params,
1899 bool enable, bool tx);
1900int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy,
1901 struct ieee80211_vif *vif,
1902 struct mt76_wcid *wcid,
1903 bool enable);
1904int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
1905 struct ieee80211_ampdu_params *params,
1906 int cmd, bool enable, bool tx);
1907int mt76_connac_mcu_uni_set_chctx(struct mt76_phy *phy,
1908 struct mt76_vif *vif,
1909 struct ieee80211_chanctx_conf *ctx);
1910int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy,
1911 struct ieee80211_vif *vif,
1912 struct mt76_wcid *wcid,
1913 bool enable,
1914 struct ieee80211_chanctx_conf *ctx);
1915int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy,
1916 struct mt76_sta_cmd_info *info);
1917void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac,
1918 struct ieee80211_vif *vif);
1919int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band);
1920int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable,
1921 bool hdr_trans);
1922int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len,
1923 u32 mode);
1924int mt76_connac_mcu_start_patch(struct mt76_dev *dev);
1925int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get);
1926int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option);
1927
1928int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif,
1929 struct ieee80211_scan_request *scan_req);
1930int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy,
1931 struct ieee80211_vif *vif);
1932int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy,
1933 struct ieee80211_vif *vif,
1934 struct cfg80211_sched_scan_request *sreq);
1935int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy,
1936 struct ieee80211_vif *vif,
1937 bool enable);
1938int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev,
1939 struct mt76_vif *vif,
1940 struct ieee80211_bss_conf *info);
1941int mt76_connac_mcu_set_gtk_rekey(struct mt76_dev *dev, struct ieee80211_vif *vif,
1942 bool suspend);
1943int mt76_connac_mcu_set_wow_ctrl(struct mt76_phy *phy, struct ieee80211_vif *vif,
1944 bool suspend, struct cfg80211_wowlan *wowlan);
1945int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw,
1946 struct ieee80211_vif *vif,
1947 struct cfg80211_gtk_rekey_data *key);
1948int mt76_connac_mcu_set_suspend_mode(struct mt76_dev *dev,
1949 struct ieee80211_vif *vif,
1950 bool enable, u8 mdtim,
1951 bool wow_suspend);
1952int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend);
1953void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac,
1954 struct ieee80211_vif *vif);
1955int mt76_connac_sta_state_dp(struct mt76_dev *dev,
1956 enum ieee80211_sta_state old_state,
1957 enum ieee80211_sta_state new_state);
1958int mt76_connac_mcu_chip_config(struct mt76_dev *dev);
1959int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable);
1960void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb,
1961 struct mt76_connac_coredump *coredump);
1962s8 mt76_connac_get_ch_power(struct mt76_phy *phy,
1963 struct ieee80211_channel *chan,
1964 s8 target_power);
1965int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy);
1966int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw,
1967 struct ieee80211_vif *vif);
1968u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset);
1969void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val);
1970
1971const struct ieee80211_sta_he_cap *
1972mt76_connac_get_he_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif);
1973const struct ieee80211_sta_eht_cap *
1974mt76_connac_get_eht_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif);
1975u8 mt76_connac_get_phy_mode(struct mt76_phy *phy, struct ieee80211_vif *vif,
1976 enum nl80211_band band, struct ieee80211_sta *sta);
1977u8 mt76_connac_get_phy_mode_ext(struct mt76_phy *phy, struct ieee80211_vif *vif,
1978 enum nl80211_band band);
1979
1980int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
1981 struct mt76_connac_sta_key_conf *sta_key_conf,
1982 struct ieee80211_key_conf *key, int mcu_cmd,
1983 struct mt76_wcid *wcid, enum set_key_cmd cmd);
1984
1985void mt76_connac_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt76_vif *mvif);
1986void mt76_connac_mcu_bss_omac_tlv(struct sk_buff *skb,
1987 struct ieee80211_vif *vif);
1988int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb,
1989 struct ieee80211_vif *vif,
1990 struct ieee80211_sta *sta,
1991 struct mt76_phy *phy, u16 wlan_idx,
1992 bool enable);
1993void mt76_connac_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif,
1994 struct ieee80211_sta *sta);
1995void mt76_connac_mcu_wtbl_smps_tlv(struct sk_buff *skb,
1996 struct ieee80211_sta *sta,
1997 void *sta_wtbl, void *wtbl_tlv);
1998int mt76_connac_mcu_set_pm(struct mt76_dev *dev, int band, int enter);
1999int mt76_connac_mcu_restart(struct mt76_dev *dev);
2000int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index,
2001 u8 rx_sel, u8 val);
2002int mt76_connac_mcu_sta_wed_update(struct mt76_dev *dev, struct sk_buff *skb);
2003int mt76_connac2_load_ram(struct mt76_dev *dev, const char *fw_wm,
2004 const char *fw_wa);
2005int mt76_connac2_load_patch(struct mt76_dev *dev, const char *fw_name);
2006int mt76_connac2_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb,
2007 int cmd, int *wait_seq);
2008#endif /* __MT76_CONNAC_MCU_H */