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1/******************************************************************************
2
3 Copyright(c) 2003 - 2006 Intel Corporation. All rights reserved.
4
5 This program is free software; you can redistribute it and/or modify it
6 under the terms of version 2 of the GNU General Public License as
7 published by the Free Software Foundation.
8
9 This program is distributed in the hope that it will be useful, but WITHOUT
10 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 more details.
13
14 You should have received a copy of the GNU General Public License along with
15 this program; if not, write to the Free Software Foundation, Inc., 59
16 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17
18 The full GNU General Public License is included in this distribution in the
19 file called LICENSE.
20
21 Contact Information:
22 Intel Linux Wireless <ilw@linux.intel.com>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24
25******************************************************************************/
26
27#ifndef __ipw2200_h__
28#define __ipw2200_h__
29
30#define WEXT_USECHANNELS 1
31
32#include <linux/module.h>
33#include <linux/moduleparam.h>
34#include <linux/init.h>
35#include <linux/interrupt.h>
36#include <linux/mutex.h>
37
38#include <linux/pci.h>
39#include <linux/netdevice.h>
40#include <linux/ethtool.h>
41#include <linux/skbuff.h>
42#include <linux/etherdevice.h>
43#include <linux/delay.h>
44#include <linux/random.h>
45#include <linux/dma-mapping.h>
46
47#include <linux/firmware.h>
48#include <linux/wireless.h>
49#include <linux/jiffies.h>
50#include <asm/io.h>
51
52#include <net/lib80211.h>
53#include <net/ieee80211_radiotap.h>
54
55#define DRV_NAME "ipw2200"
56
57#include <linux/workqueue.h>
58
59#include "libipw.h"
60
61/* Authentication and Association States */
62enum connection_manager_assoc_states {
63 CMAS_INIT = 0,
64 CMAS_TX_AUTH_SEQ_1,
65 CMAS_RX_AUTH_SEQ_2,
66 CMAS_AUTH_SEQ_1_PASS,
67 CMAS_AUTH_SEQ_1_FAIL,
68 CMAS_TX_AUTH_SEQ_3,
69 CMAS_RX_AUTH_SEQ_4,
70 CMAS_AUTH_SEQ_2_PASS,
71 CMAS_AUTH_SEQ_2_FAIL,
72 CMAS_AUTHENTICATED,
73 CMAS_TX_ASSOC,
74 CMAS_RX_ASSOC_RESP,
75 CMAS_ASSOCIATED,
76 CMAS_LAST
77};
78
79#define IPW_WAIT (1<<0)
80#define IPW_QUIET (1<<1)
81#define IPW_ROAMING (1<<2)
82
83#define IPW_POWER_MODE_CAM 0x00 //(always on)
84#define IPW_POWER_INDEX_1 0x01
85#define IPW_POWER_INDEX_2 0x02
86#define IPW_POWER_INDEX_3 0x03
87#define IPW_POWER_INDEX_4 0x04
88#define IPW_POWER_INDEX_5 0x05
89#define IPW_POWER_AC 0x06
90#define IPW_POWER_BATTERY 0x07
91#define IPW_POWER_LIMIT 0x07
92#define IPW_POWER_MASK 0x0F
93#define IPW_POWER_ENABLED 0x10
94#define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK)
95
96#define IPW_CMD_HOST_COMPLETE 2
97#define IPW_CMD_POWER_DOWN 4
98#define IPW_CMD_SYSTEM_CONFIG 6
99#define IPW_CMD_MULTICAST_ADDRESS 7
100#define IPW_CMD_SSID 8
101#define IPW_CMD_ADAPTER_ADDRESS 11
102#define IPW_CMD_PORT_TYPE 12
103#define IPW_CMD_RTS_THRESHOLD 15
104#define IPW_CMD_FRAG_THRESHOLD 16
105#define IPW_CMD_POWER_MODE 17
106#define IPW_CMD_WEP_KEY 18
107#define IPW_CMD_TGI_TX_KEY 19
108#define IPW_CMD_SCAN_REQUEST 20
109#define IPW_CMD_ASSOCIATE 21
110#define IPW_CMD_SUPPORTED_RATES 22
111#define IPW_CMD_SCAN_ABORT 23
112#define IPW_CMD_TX_FLUSH 24
113#define IPW_CMD_QOS_PARAMETERS 25
114#define IPW_CMD_SCAN_REQUEST_EXT 26
115#define IPW_CMD_DINO_CONFIG 30
116#define IPW_CMD_RSN_CAPABILITIES 31
117#define IPW_CMD_RX_KEY 32
118#define IPW_CMD_CARD_DISABLE 33
119#define IPW_CMD_SEED_NUMBER 34
120#define IPW_CMD_TX_POWER 35
121#define IPW_CMD_COUNTRY_INFO 36
122#define IPW_CMD_AIRONET_INFO 37
123#define IPW_CMD_AP_TX_POWER 38
124#define IPW_CMD_CCKM_INFO 39
125#define IPW_CMD_CCX_VER_INFO 40
126#define IPW_CMD_SET_CALIBRATION 41
127#define IPW_CMD_SENSITIVITY_CALIB 42
128#define IPW_CMD_RETRY_LIMIT 51
129#define IPW_CMD_IPW_PRE_POWER_DOWN 58
130#define IPW_CMD_VAP_BEACON_TEMPLATE 60
131#define IPW_CMD_VAP_DTIM_PERIOD 61
132#define IPW_CMD_EXT_SUPPORTED_RATES 62
133#define IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT 63
134#define IPW_CMD_VAP_QUIET_INTERVALS 64
135#define IPW_CMD_VAP_CHANNEL_SWITCH 65
136#define IPW_CMD_VAP_MANDATORY_CHANNELS 66
137#define IPW_CMD_VAP_CELL_PWR_LIMIT 67
138#define IPW_CMD_VAP_CF_PARAM_SET 68
139#define IPW_CMD_VAP_SET_BEACONING_STATE 69
140#define IPW_CMD_MEASUREMENT 80
141#define IPW_CMD_POWER_CAPABILITY 81
142#define IPW_CMD_SUPPORTED_CHANNELS 82
143#define IPW_CMD_TPC_REPORT 83
144#define IPW_CMD_WME_INFO 84
145#define IPW_CMD_PRODUCTION_COMMAND 85
146#define IPW_CMD_LINKSYS_EOU_INFO 90
147
148#define RFD_SIZE 4
149#define NUM_TFD_CHUNKS 6
150
151#define TX_QUEUE_SIZE 32
152#define RX_QUEUE_SIZE 32
153
154#define DINO_CMD_WEP_KEY 0x08
155#define DINO_CMD_TX 0x0B
156#define DCT_ANTENNA_A 0x01
157#define DCT_ANTENNA_B 0x02
158
159#define IPW_A_MODE 0
160#define IPW_B_MODE 1
161#define IPW_G_MODE 2
162
163/*
164 * TX Queue Flag Definitions
165 */
166
167/* tx wep key definition */
168#define DCT_WEP_KEY_NOT_IMMIDIATE 0x00
169#define DCT_WEP_KEY_64Bit 0x40
170#define DCT_WEP_KEY_128Bit 0x80
171#define DCT_WEP_KEY_128bitIV 0xC0
172#define DCT_WEP_KEY_SIZE_MASK 0xC0
173
174#define DCT_WEP_KEY_INDEX_MASK 0x0F
175#define DCT_WEP_INDEX_USE_IMMEDIATE 0x20
176
177/* abort attempt if mgmt frame is rx'd */
178#define DCT_FLAG_ABORT_MGMT 0x01
179
180/* require CTS */
181#define DCT_FLAG_CTS_REQUIRED 0x02
182
183/* use short preamble */
184#define DCT_FLAG_LONG_PREAMBLE 0x00
185#define DCT_FLAG_SHORT_PREAMBLE 0x04
186
187/* RTS/CTS first */
188#define DCT_FLAG_RTS_REQD 0x08
189
190/* dont calculate duration field */
191#define DCT_FLAG_DUR_SET 0x10
192
193/* even if MAC WEP set (allows pre-encrypt) */
194#define DCT_FLAG_NO_WEP 0x20
195
196/* overwrite TSF field */
197#define DCT_FLAG_TSF_REQD 0x40
198
199/* ACK rx is expected to follow */
200#define DCT_FLAG_ACK_REQD 0x80
201
202/* TX flags extension */
203#define DCT_FLAG_EXT_MODE_CCK 0x01
204#define DCT_FLAG_EXT_MODE_OFDM 0x00
205
206#define DCT_FLAG_EXT_SECURITY_WEP 0x00
207#define DCT_FLAG_EXT_SECURITY_NO DCT_FLAG_EXT_SECURITY_WEP
208#define DCT_FLAG_EXT_SECURITY_CKIP 0x04
209#define DCT_FLAG_EXT_SECURITY_CCM 0x08
210#define DCT_FLAG_EXT_SECURITY_TKIP 0x0C
211#define DCT_FLAG_EXT_SECURITY_MASK 0x0C
212
213#define DCT_FLAG_EXT_QOS_ENABLED 0x10
214
215#define DCT_FLAG_EXT_HC_NO_SIFS_PIFS 0x00
216#define DCT_FLAG_EXT_HC_SIFS 0x20
217#define DCT_FLAG_EXT_HC_PIFS 0x40
218
219#define TX_RX_TYPE_MASK 0xFF
220#define TX_FRAME_TYPE 0x00
221#define TX_HOST_COMMAND_TYPE 0x01
222#define RX_FRAME_TYPE 0x09
223#define RX_HOST_NOTIFICATION_TYPE 0x03
224#define RX_HOST_CMD_RESPONSE_TYPE 0x04
225#define RX_TX_FRAME_RESPONSE_TYPE 0x05
226#define TFD_NEED_IRQ_MASK 0x04
227
228#define HOST_CMD_DINO_CONFIG 30
229
230#define HOST_NOTIFICATION_STATUS_ASSOCIATED 10
231#define HOST_NOTIFICATION_STATUS_AUTHENTICATE 11
232#define HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT 12
233#define HOST_NOTIFICATION_STATUS_SCAN_COMPLETED 13
234#define HOST_NOTIFICATION_STATUS_FRAG_LENGTH 14
235#define HOST_NOTIFICATION_STATUS_LINK_DETERIORATION 15
236#define HOST_NOTIFICATION_DINO_CONFIG_RESPONSE 16
237#define HOST_NOTIFICATION_STATUS_BEACON_STATE 17
238#define HOST_NOTIFICATION_STATUS_TGI_TX_KEY 18
239#define HOST_NOTIFICATION_TX_STATUS 19
240#define HOST_NOTIFICATION_CALIB_KEEP_RESULTS 20
241#define HOST_NOTIFICATION_MEASUREMENT_STARTED 21
242#define HOST_NOTIFICATION_MEASUREMENT_ENDED 22
243#define HOST_NOTIFICATION_CHANNEL_SWITCHED 23
244#define HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD 24
245#define HOST_NOTIFICATION_NOISE_STATS 25
246#define HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED 30
247#define HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED 31
248
249#define HOST_NOTIFICATION_STATUS_BEACON_MISSING 1
250#define IPW_MB_SCAN_CANCEL_THRESHOLD 3
251#define IPW_MB_ROAMING_THRESHOLD_MIN 1
252#define IPW_MB_ROAMING_THRESHOLD_DEFAULT 8
253#define IPW_MB_ROAMING_THRESHOLD_MAX 30
254#define IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT 3*IPW_MB_ROAMING_THRESHOLD_DEFAULT
255#define IPW_REAL_RATE_RX_PACKET_THRESHOLD 300
256
257#define MACADRR_BYTE_LEN 6
258
259#define DCR_TYPE_AP 0x01
260#define DCR_TYPE_WLAP 0x02
261#define DCR_TYPE_MU_ESS 0x03
262#define DCR_TYPE_MU_IBSS 0x04
263#define DCR_TYPE_MU_PIBSS 0x05
264#define DCR_TYPE_SNIFFER 0x06
265#define DCR_TYPE_MU_BSS DCR_TYPE_MU_ESS
266
267/* QoS definitions */
268
269#define CW_MIN_OFDM 15
270#define CW_MAX_OFDM 1023
271#define CW_MIN_CCK 31
272#define CW_MAX_CCK 1023
273
274#define QOS_TX0_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
275#define QOS_TX1_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
276#define QOS_TX2_CW_MIN_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/2 - 1)
277#define QOS_TX3_CW_MIN_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/4 - 1)
278
279#define QOS_TX0_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
280#define QOS_TX1_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
281#define QOS_TX2_CW_MIN_CCK cpu_to_le16((CW_MIN_CCK + 1)/2 - 1)
282#define QOS_TX3_CW_MIN_CCK cpu_to_le16((CW_MIN_CCK + 1)/4 - 1)
283
284#define QOS_TX0_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
285#define QOS_TX1_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
286#define QOS_TX2_CW_MAX_OFDM cpu_to_le16(CW_MIN_OFDM)
287#define QOS_TX3_CW_MAX_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/2 - 1)
288
289#define QOS_TX0_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
290#define QOS_TX1_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
291#define QOS_TX2_CW_MAX_CCK cpu_to_le16(CW_MIN_CCK)
292#define QOS_TX3_CW_MAX_CCK cpu_to_le16((CW_MIN_CCK + 1)/2 - 1)
293
294#define QOS_TX0_AIFS (3 - QOS_AIFSN_MIN_VALUE)
295#define QOS_TX1_AIFS (7 - QOS_AIFSN_MIN_VALUE)
296#define QOS_TX2_AIFS (2 - QOS_AIFSN_MIN_VALUE)
297#define QOS_TX3_AIFS (2 - QOS_AIFSN_MIN_VALUE)
298
299#define QOS_TX0_ACM 0
300#define QOS_TX1_ACM 0
301#define QOS_TX2_ACM 0
302#define QOS_TX3_ACM 0
303
304#define QOS_TX0_TXOP_LIMIT_CCK 0
305#define QOS_TX1_TXOP_LIMIT_CCK 0
306#define QOS_TX2_TXOP_LIMIT_CCK cpu_to_le16(6016)
307#define QOS_TX3_TXOP_LIMIT_CCK cpu_to_le16(3264)
308
309#define QOS_TX0_TXOP_LIMIT_OFDM 0
310#define QOS_TX1_TXOP_LIMIT_OFDM 0
311#define QOS_TX2_TXOP_LIMIT_OFDM cpu_to_le16(3008)
312#define QOS_TX3_TXOP_LIMIT_OFDM cpu_to_le16(1504)
313
314#define DEF_TX0_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
315#define DEF_TX1_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
316#define DEF_TX2_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
317#define DEF_TX3_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
318
319#define DEF_TX0_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
320#define DEF_TX1_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
321#define DEF_TX2_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
322#define DEF_TX3_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
323
324#define DEF_TX0_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
325#define DEF_TX1_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
326#define DEF_TX2_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
327#define DEF_TX3_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
328
329#define DEF_TX0_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
330#define DEF_TX1_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
331#define DEF_TX2_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
332#define DEF_TX3_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
333
334#define DEF_TX0_AIFS 0
335#define DEF_TX1_AIFS 0
336#define DEF_TX2_AIFS 0
337#define DEF_TX3_AIFS 0
338
339#define DEF_TX0_ACM 0
340#define DEF_TX1_ACM 0
341#define DEF_TX2_ACM 0
342#define DEF_TX3_ACM 0
343
344#define DEF_TX0_TXOP_LIMIT_CCK 0
345#define DEF_TX1_TXOP_LIMIT_CCK 0
346#define DEF_TX2_TXOP_LIMIT_CCK 0
347#define DEF_TX3_TXOP_LIMIT_CCK 0
348
349#define DEF_TX0_TXOP_LIMIT_OFDM 0
350#define DEF_TX1_TXOP_LIMIT_OFDM 0
351#define DEF_TX2_TXOP_LIMIT_OFDM 0
352#define DEF_TX3_TXOP_LIMIT_OFDM 0
353
354#define QOS_QOS_SETS 3
355#define QOS_PARAM_SET_ACTIVE 0
356#define QOS_PARAM_SET_DEF_CCK 1
357#define QOS_PARAM_SET_DEF_OFDM 2
358
359#define CTRL_QOS_NO_ACK (0x0020)
360
361#define IPW_TX_QUEUE_1 1
362#define IPW_TX_QUEUE_2 2
363#define IPW_TX_QUEUE_3 3
364#define IPW_TX_QUEUE_4 4
365
366/* QoS sturctures */
367struct ipw_qos_info {
368 int qos_enable;
369 struct libipw_qos_parameters *def_qos_parm_OFDM;
370 struct libipw_qos_parameters *def_qos_parm_CCK;
371 u32 burst_duration_CCK;
372 u32 burst_duration_OFDM;
373 u16 qos_no_ack_mask;
374 int burst_enable;
375};
376
377/**************************************************************/
378/**
379 * Generic queue structure
380 *
381 * Contains common data for Rx and Tx queues
382 */
383struct clx2_queue {
384 int n_bd; /**< number of BDs in this queue */
385 int first_empty; /**< 1-st empty entry (index) */
386 int last_used; /**< last used entry (index) */
387 u32 reg_w; /**< 'write' reg (queue head), addr in domain 1 */
388 u32 reg_r; /**< 'read' reg (queue tail), addr in domain 1 */
389 dma_addr_t dma_addr; /**< physical addr for BD's */
390 int low_mark; /**< low watermark, resume queue if free space more than this */
391 int high_mark; /**< high watermark, stop queue if free space less than this */
392} __packed; /* XXX */
393
394struct machdr32 {
395 __le16 frame_ctl;
396 __le16 duration; // watch out for endians!
397 u8 addr1[MACADRR_BYTE_LEN];
398 u8 addr2[MACADRR_BYTE_LEN];
399 u8 addr3[MACADRR_BYTE_LEN];
400 __le16 seq_ctrl; // more endians!
401 u8 addr4[MACADRR_BYTE_LEN];
402 __le16 qos_ctrl;
403} __packed;
404
405struct machdr30 {
406 __le16 frame_ctl;
407 __le16 duration; // watch out for endians!
408 u8 addr1[MACADRR_BYTE_LEN];
409 u8 addr2[MACADRR_BYTE_LEN];
410 u8 addr3[MACADRR_BYTE_LEN];
411 __le16 seq_ctrl; // more endians!
412 u8 addr4[MACADRR_BYTE_LEN];
413} __packed;
414
415struct machdr26 {
416 __le16 frame_ctl;
417 __le16 duration; // watch out for endians!
418 u8 addr1[MACADRR_BYTE_LEN];
419 u8 addr2[MACADRR_BYTE_LEN];
420 u8 addr3[MACADRR_BYTE_LEN];
421 __le16 seq_ctrl; // more endians!
422 __le16 qos_ctrl;
423} __packed;
424
425struct machdr24 {
426 __le16 frame_ctl;
427 __le16 duration; // watch out for endians!
428 u8 addr1[MACADRR_BYTE_LEN];
429 u8 addr2[MACADRR_BYTE_LEN];
430 u8 addr3[MACADRR_BYTE_LEN];
431 __le16 seq_ctrl; // more endians!
432} __packed;
433
434// TX TFD with 32 byte MAC Header
435struct tx_tfd_32 {
436 struct machdr32 mchdr; // 32
437 __le32 uivplaceholder[2]; // 8
438} __packed;
439
440// TX TFD with 30 byte MAC Header
441struct tx_tfd_30 {
442 struct machdr30 mchdr; // 30
443 u8 reserved[2]; // 2
444 __le32 uivplaceholder[2]; // 8
445} __packed;
446
447// tx tfd with 26 byte mac header
448struct tx_tfd_26 {
449 struct machdr26 mchdr; // 26
450 u8 reserved1[2]; // 2
451 __le32 uivplaceholder[2]; // 8
452 u8 reserved2[4]; // 4
453} __packed;
454
455// tx tfd with 24 byte mac header
456struct tx_tfd_24 {
457 struct machdr24 mchdr; // 24
458 __le32 uivplaceholder[2]; // 8
459 u8 reserved[8]; // 8
460} __packed;
461
462#define DCT_WEP_KEY_FIELD_LENGTH 16
463
464struct tfd_command {
465 u8 index;
466 u8 length;
467 __le16 reserved;
468 u8 payload[0];
469} __packed;
470
471struct tfd_data {
472 /* Header */
473 __le32 work_area_ptr;
474 u8 station_number; /* 0 for BSS */
475 u8 reserved1;
476 __le16 reserved2;
477
478 /* Tx Parameters */
479 u8 cmd_id;
480 u8 seq_num;
481 __le16 len;
482 u8 priority;
483 u8 tx_flags;
484 u8 tx_flags_ext;
485 u8 key_index;
486 u8 wepkey[DCT_WEP_KEY_FIELD_LENGTH];
487 u8 rate;
488 u8 antenna;
489 __le16 next_packet_duration;
490 __le16 next_frag_len;
491 __le16 back_off_counter; //////txop;
492 u8 retrylimit;
493 __le16 cwcurrent;
494 u8 reserved3;
495
496 /* 802.11 MAC Header */
497 union {
498 struct tx_tfd_24 tfd_24;
499 struct tx_tfd_26 tfd_26;
500 struct tx_tfd_30 tfd_30;
501 struct tx_tfd_32 tfd_32;
502 } tfd;
503
504 /* Payload DMA info */
505 __le32 num_chunks;
506 __le32 chunk_ptr[NUM_TFD_CHUNKS];
507 __le16 chunk_len[NUM_TFD_CHUNKS];
508} __packed;
509
510struct txrx_control_flags {
511 u8 message_type;
512 u8 rx_seq_num;
513 u8 control_bits;
514 u8 reserved;
515} __packed;
516
517#define TFD_SIZE 128
518#define TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH (TFD_SIZE - sizeof(struct txrx_control_flags))
519
520struct tfd_frame {
521 struct txrx_control_flags control_flags;
522 union {
523 struct tfd_data data;
524 struct tfd_command cmd;
525 u8 raw[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
526 } u;
527} __packed;
528
529typedef void destructor_func(const void *);
530
531/**
532 * Tx Queue for DMA. Queue consists of circular buffer of
533 * BD's and required locking structures.
534 */
535struct clx2_tx_queue {
536 struct clx2_queue q;
537 struct tfd_frame *bd;
538 struct libipw_txb **txb;
539};
540
541/*
542 * RX related structures and functions
543 */
544#define RX_FREE_BUFFERS 32
545#define RX_LOW_WATERMARK 8
546
547#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
548#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
549#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
550
551// Used for passing to driver number of successes and failures per rate
552struct rate_histogram {
553 union {
554 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
555 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
556 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
557 } success;
558 union {
559 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
560 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
561 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
562 } failed;
563} __packed;
564
565/* statistics command response */
566struct ipw_cmd_stats {
567 u8 cmd_id;
568 u8 seq_num;
569 __le16 good_sfd;
570 __le16 bad_plcp;
571 __le16 wrong_bssid;
572 __le16 valid_mpdu;
573 __le16 bad_mac_header;
574 __le16 reserved_frame_types;
575 __le16 rx_ina;
576 __le16 bad_crc32;
577 __le16 invalid_cts;
578 __le16 invalid_acks;
579 __le16 long_distance_ina_fina;
580 __le16 dsp_silence_unreachable;
581 __le16 accumulated_rssi;
582 __le16 rx_ovfl_frame_tossed;
583 __le16 rssi_silence_threshold;
584 __le16 rx_ovfl_frame_supplied;
585 __le16 last_rx_frame_signal;
586 __le16 last_rx_frame_noise;
587 __le16 rx_autodetec_no_ofdm;
588 __le16 rx_autodetec_no_barker;
589 __le16 reserved;
590} __packed;
591
592struct notif_channel_result {
593 u8 channel_num;
594 struct ipw_cmd_stats stats;
595 u8 uReserved;
596} __packed;
597
598#define SCAN_COMPLETED_STATUS_COMPLETE 1
599#define SCAN_COMPLETED_STATUS_ABORTED 2
600
601struct notif_scan_complete {
602 u8 scan_type;
603 u8 num_channels;
604 u8 status;
605 u8 reserved;
606} __packed;
607
608struct notif_frag_length {
609 __le16 frag_length;
610 __le16 reserved;
611} __packed;
612
613struct notif_beacon_state {
614 __le32 state;
615 __le32 number;
616} __packed;
617
618struct notif_tgi_tx_key {
619 u8 key_state;
620 u8 security_type;
621 u8 station_index;
622 u8 reserved;
623} __packed;
624
625#define SILENCE_OVER_THRESH (1)
626#define SILENCE_UNDER_THRESH (2)
627
628struct notif_link_deterioration {
629 struct ipw_cmd_stats stats;
630 u8 rate;
631 u8 modulation;
632 struct rate_histogram histogram;
633 u8 silence_notification_type; /* SILENCE_OVER/UNDER_THRESH */
634 __le16 silence_count;
635} __packed;
636
637struct notif_association {
638 u8 state;
639} __packed;
640
641struct notif_authenticate {
642 u8 state;
643 struct machdr24 addr;
644 __le16 status;
645} __packed;
646
647struct notif_calibration {
648 u8 data[104];
649} __packed;
650
651struct notif_noise {
652 __le32 value;
653} __packed;
654
655struct ipw_rx_notification {
656 u8 reserved[8];
657 u8 subtype;
658 u8 flags;
659 __le16 size;
660 union {
661 struct notif_association assoc;
662 struct notif_authenticate auth;
663 struct notif_channel_result channel_result;
664 struct notif_scan_complete scan_complete;
665 struct notif_frag_length frag_len;
666 struct notif_beacon_state beacon_state;
667 struct notif_tgi_tx_key tgi_tx_key;
668 struct notif_link_deterioration link_deterioration;
669 struct notif_calibration calibration;
670 struct notif_noise noise;
671 u8 raw[0];
672 } u;
673} __packed;
674
675struct ipw_rx_frame {
676 __le32 reserved1;
677 u8 parent_tsf[4]; // fw_use[0] is boolean for OUR_TSF_IS_GREATER
678 u8 received_channel; // The channel that this frame was received on.
679 // Note that for .11b this does not have to be
680 // the same as the channel that it was sent.
681 // Filled by LMAC
682 u8 frameStatus;
683 u8 rate;
684 u8 rssi;
685 u8 agc;
686 u8 rssi_dbm;
687 __le16 signal;
688 __le16 noise;
689 u8 antennaAndPhy;
690 u8 control; // control bit should be on in bg
691 u8 rtscts_rate; // rate of rts or cts (in rts cts sequence rate
692 // is identical)
693 u8 rtscts_seen; // 0x1 RTS seen ; 0x2 CTS seen
694 __le16 length;
695 u8 data[0];
696} __packed;
697
698struct ipw_rx_header {
699 u8 message_type;
700 u8 rx_seq_num;
701 u8 control_bits;
702 u8 reserved;
703} __packed;
704
705struct ipw_rx_packet {
706 struct ipw_rx_header header;
707 union {
708 struct ipw_rx_frame frame;
709 struct ipw_rx_notification notification;
710 } u;
711} __packed;
712
713#define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12
714#define IPW_RX_FRAME_SIZE (unsigned int)(sizeof(struct ipw_rx_header) + \
715 sizeof(struct ipw_rx_frame))
716
717struct ipw_rx_mem_buffer {
718 dma_addr_t dma_addr;
719 struct sk_buff *skb;
720 struct list_head list;
721}; /* Not transferred over network, so not __packed */
722
723struct ipw_rx_queue {
724 struct ipw_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
725 struct ipw_rx_mem_buffer *queue[RX_QUEUE_SIZE];
726 u32 processed; /* Internal index to last handled Rx packet */
727 u32 read; /* Shared index to newest available Rx buffer */
728 u32 write; /* Shared index to oldest written Rx packet */
729 u32 free_count; /* Number of pre-allocated buffers in rx_free */
730 /* Each of these lists is used as a FIFO for ipw_rx_mem_buffers */
731 struct list_head rx_free; /* Own an SKBs */
732 struct list_head rx_used; /* No SKB allocated */
733 spinlock_t lock;
734}; /* Not transferred over network, so not __packed */
735
736struct alive_command_responce {
737 u8 alive_command;
738 u8 sequence_number;
739 __le16 software_revision;
740 u8 device_identifier;
741 u8 reserved1[5];
742 __le16 reserved2;
743 __le16 reserved3;
744 __le16 clock_settle_time;
745 __le16 powerup_settle_time;
746 __le16 reserved4;
747 u8 time_stamp[5]; /* month, day, year, hours, minutes */
748 u8 ucode_valid;
749} __packed;
750
751#define IPW_MAX_RATES 12
752
753struct ipw_rates {
754 u8 num_rates;
755 u8 rates[IPW_MAX_RATES];
756} __packed;
757
758struct command_block {
759 unsigned int control;
760 u32 source_addr;
761 u32 dest_addr;
762 unsigned int status;
763} __packed;
764
765#define CB_NUMBER_OF_ELEMENTS_SMALL 64
766struct fw_image_desc {
767 unsigned long last_cb_index;
768 unsigned long current_cb_index;
769 struct command_block cb_list[CB_NUMBER_OF_ELEMENTS_SMALL];
770 void *v_addr;
771 unsigned long p_addr;
772 unsigned long len;
773};
774
775struct ipw_sys_config {
776 u8 bt_coexistence;
777 u8 reserved1;
778 u8 answer_broadcast_ssid_probe;
779 u8 accept_all_data_frames;
780 u8 accept_non_directed_frames;
781 u8 exclude_unicast_unencrypted;
782 u8 disable_unicast_decryption;
783 u8 exclude_multicast_unencrypted;
784 u8 disable_multicast_decryption;
785 u8 antenna_diversity;
786 u8 pass_crc_to_host;
787 u8 dot11g_auto_detection;
788 u8 enable_cts_to_self;
789 u8 enable_multicast_filtering;
790 u8 bt_coexist_collision_thr;
791 u8 silence_threshold;
792 u8 accept_all_mgmt_bcpr;
793 u8 accept_all_mgmt_frames;
794 u8 pass_noise_stats_to_host;
795 u8 reserved3;
796} __packed;
797
798struct ipw_multicast_addr {
799 u8 num_of_multicast_addresses;
800 u8 reserved[3];
801 u8 mac1[6];
802 u8 mac2[6];
803 u8 mac3[6];
804 u8 mac4[6];
805} __packed;
806
807#define DCW_WEP_KEY_INDEX_MASK 0x03 /* bits [0:1] */
808#define DCW_WEP_KEY_SEC_TYPE_MASK 0x30 /* bits [4:5] */
809
810#define DCW_WEP_KEY_SEC_TYPE_WEP 0x00
811#define DCW_WEP_KEY_SEC_TYPE_CCM 0x20
812#define DCW_WEP_KEY_SEC_TYPE_TKIP 0x30
813
814#define DCW_WEP_KEY_INVALID_SIZE 0x00 /* 0 = Invalid key */
815#define DCW_WEP_KEY64Bit_SIZE 0x05 /* 64-bit encryption */
816#define DCW_WEP_KEY128Bit_SIZE 0x0D /* 128-bit encryption */
817#define DCW_CCM_KEY128Bit_SIZE 0x10 /* 128-bit key */
818//#define DCW_WEP_KEY128BitIV_SIZE 0x10 /* 128-bit key and 128-bit IV */
819
820struct ipw_wep_key {
821 u8 cmd_id;
822 u8 seq_num;
823 u8 key_index;
824 u8 key_size;
825 u8 key[16];
826} __packed;
827
828struct ipw_tgi_tx_key {
829 u8 key_id;
830 u8 security_type;
831 u8 station_index;
832 u8 flags;
833 u8 key[16];
834 __le32 tx_counter[2];
835} __packed;
836
837#define IPW_SCAN_CHANNELS 54
838
839struct ipw_scan_request {
840 u8 scan_type;
841 __le16 dwell_time;
842 u8 channels_list[IPW_SCAN_CHANNELS];
843 u8 channels_reserved[3];
844} __packed;
845
846enum {
847 IPW_SCAN_PASSIVE_TILL_FIRST_BEACON_SCAN = 0,
848 IPW_SCAN_PASSIVE_FULL_DWELL_SCAN,
849 IPW_SCAN_ACTIVE_DIRECT_SCAN,
850 IPW_SCAN_ACTIVE_BROADCAST_SCAN,
851 IPW_SCAN_ACTIVE_BROADCAST_AND_DIRECT_SCAN,
852 IPW_SCAN_TYPES
853};
854
855struct ipw_scan_request_ext {
856 __le32 full_scan_index;
857 u8 channels_list[IPW_SCAN_CHANNELS];
858 u8 scan_type[IPW_SCAN_CHANNELS / 2];
859 u8 reserved;
860 __le16 dwell_time[IPW_SCAN_TYPES];
861} __packed;
862
863static inline u8 ipw_get_scan_type(struct ipw_scan_request_ext *scan, u8 index)
864{
865 if (index % 2)
866 return scan->scan_type[index / 2] & 0x0F;
867 else
868 return (scan->scan_type[index / 2] & 0xF0) >> 4;
869}
870
871static inline void ipw_set_scan_type(struct ipw_scan_request_ext *scan,
872 u8 index, u8 scan_type)
873{
874 if (index % 2)
875 scan->scan_type[index / 2] =
876 (scan->scan_type[index / 2] & 0xF0) | (scan_type & 0x0F);
877 else
878 scan->scan_type[index / 2] =
879 (scan->scan_type[index / 2] & 0x0F) |
880 ((scan_type & 0x0F) << 4);
881}
882
883struct ipw_associate {
884 u8 channel;
885#ifdef __LITTLE_ENDIAN_BITFIELD
886 u8 auth_type:4, auth_key:4;
887#else
888 u8 auth_key:4, auth_type:4;
889#endif
890 u8 assoc_type;
891 u8 reserved;
892 __le16 policy_support;
893 u8 preamble_length;
894 u8 ieee_mode;
895 u8 bssid[ETH_ALEN];
896 __le32 assoc_tsf_msw;
897 __le32 assoc_tsf_lsw;
898 __le16 capability;
899 __le16 listen_interval;
900 __le16 beacon_interval;
901 u8 dest[ETH_ALEN];
902 __le16 atim_window;
903 u8 smr;
904 u8 reserved1;
905 __le16 reserved2;
906} __packed;
907
908struct ipw_supported_rates {
909 u8 ieee_mode;
910 u8 num_rates;
911 u8 purpose;
912 u8 reserved;
913 u8 supported_rates[IPW_MAX_RATES];
914} __packed;
915
916struct ipw_rts_threshold {
917 __le16 rts_threshold;
918 __le16 reserved;
919} __packed;
920
921struct ipw_frag_threshold {
922 __le16 frag_threshold;
923 __le16 reserved;
924} __packed;
925
926struct ipw_retry_limit {
927 u8 short_retry_limit;
928 u8 long_retry_limit;
929 __le16 reserved;
930} __packed;
931
932struct ipw_dino_config {
933 __le32 dino_config_addr;
934 __le16 dino_config_size;
935 u8 dino_response;
936 u8 reserved;
937} __packed;
938
939struct ipw_aironet_info {
940 u8 id;
941 u8 length;
942 __le16 reserved;
943} __packed;
944
945struct ipw_rx_key {
946 u8 station_index;
947 u8 key_type;
948 u8 key_id;
949 u8 key_flag;
950 u8 key[16];
951 u8 station_address[6];
952 u8 key_index;
953 u8 reserved;
954} __packed;
955
956struct ipw_country_channel_info {
957 u8 first_channel;
958 u8 no_channels;
959 s8 max_tx_power;
960} __packed;
961
962struct ipw_country_info {
963 u8 id;
964 u8 length;
965 u8 country_str[IEEE80211_COUNTRY_STRING_LEN];
966 struct ipw_country_channel_info groups[7];
967} __packed;
968
969struct ipw_channel_tx_power {
970 u8 channel_number;
971 s8 tx_power;
972} __packed;
973
974#define SCAN_ASSOCIATED_INTERVAL (HZ)
975#define SCAN_INTERVAL (HZ / 10)
976#define MAX_A_CHANNELS 37
977#define MAX_B_CHANNELS 14
978
979struct ipw_tx_power {
980 u8 num_channels;
981 u8 ieee_mode;
982 struct ipw_channel_tx_power channels_tx_power[MAX_A_CHANNELS];
983} __packed;
984
985struct ipw_rsn_capabilities {
986 u8 id;
987 u8 length;
988 __le16 version;
989} __packed;
990
991struct ipw_sensitivity_calib {
992 __le16 beacon_rssi_raw;
993 __le16 reserved;
994} __packed;
995
996/**
997 * Host command structure.
998 *
999 * On input, the following fields should be filled:
1000 * - cmd
1001 * - len
1002 * - status_len
1003 * - param (if needed)
1004 *
1005 * On output,
1006 * - \a status contains status;
1007 * - \a param filled with status parameters.
1008 */
1009struct ipw_cmd { /* XXX */
1010 u32 cmd; /**< Host command */
1011 u32 status;/**< Status */
1012 u32 status_len;
1013 /**< How many 32 bit parameters in the status */
1014 u32 len; /**< incoming parameters length, bytes */
1015 /**
1016 * command parameters.
1017 * There should be enough space for incoming and
1018 * outcoming parameters.
1019 * Incoming parameters listed 1-st, followed by outcoming params.
1020 * nParams=(len+3)/4+status_len
1021 */
1022 u32 param[0];
1023} __packed;
1024
1025#define STATUS_HCMD_ACTIVE (1<<0) /**< host command in progress */
1026
1027#define STATUS_INT_ENABLED (1<<1)
1028#define STATUS_RF_KILL_HW (1<<2)
1029#define STATUS_RF_KILL_SW (1<<3)
1030#define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)
1031
1032#define STATUS_INIT (1<<5)
1033#define STATUS_AUTH (1<<6)
1034#define STATUS_ASSOCIATED (1<<7)
1035#define STATUS_STATE_MASK (STATUS_INIT | STATUS_AUTH | STATUS_ASSOCIATED)
1036
1037#define STATUS_ASSOCIATING (1<<8)
1038#define STATUS_DISASSOCIATING (1<<9)
1039#define STATUS_ROAMING (1<<10)
1040#define STATUS_EXIT_PENDING (1<<11)
1041#define STATUS_DISASSOC_PENDING (1<<12)
1042#define STATUS_STATE_PENDING (1<<13)
1043
1044#define STATUS_DIRECT_SCAN_PENDING (1<<19)
1045#define STATUS_SCAN_PENDING (1<<20)
1046#define STATUS_SCANNING (1<<21)
1047#define STATUS_SCAN_ABORTING (1<<22)
1048#define STATUS_SCAN_FORCED (1<<23)
1049
1050#define STATUS_LED_LINK_ON (1<<24)
1051#define STATUS_LED_ACT_ON (1<<25)
1052
1053#define STATUS_INDIRECT_BYTE (1<<28) /* sysfs entry configured for access */
1054#define STATUS_INDIRECT_DWORD (1<<29) /* sysfs entry configured for access */
1055#define STATUS_DIRECT_DWORD (1<<30) /* sysfs entry configured for access */
1056
1057#define STATUS_SECURITY_UPDATED (1<<31) /* Security sync needed */
1058
1059#define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */
1060#define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */
1061#define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */
1062#define CFG_CUSTOM_MAC (1<<3)
1063#define CFG_PREAMBLE_LONG (1<<4)
1064#define CFG_ADHOC_PERSIST (1<<5)
1065#define CFG_ASSOCIATE (1<<6)
1066#define CFG_FIXED_RATE (1<<7)
1067#define CFG_ADHOC_CREATE (1<<8)
1068#define CFG_NO_LED (1<<9)
1069#define CFG_BACKGROUND_SCAN (1<<10)
1070#define CFG_SPEED_SCAN (1<<11)
1071#define CFG_NET_STATS (1<<12)
1072
1073#define CAP_SHARED_KEY (1<<0) /* Off = OPEN */
1074#define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */
1075
1076#define MAX_STATIONS 32
1077#define IPW_INVALID_STATION (0xff)
1078
1079struct ipw_station_entry {
1080 u8 mac_addr[ETH_ALEN];
1081 u8 reserved;
1082 u8 support_mode;
1083};
1084
1085#define AVG_ENTRIES 8
1086struct average {
1087 s16 entries[AVG_ENTRIES];
1088 u8 pos;
1089 u8 init;
1090 s32 sum;
1091};
1092
1093#define MAX_SPEED_SCAN 100
1094#define IPW_IBSS_MAC_HASH_SIZE 31
1095
1096struct ipw_ibss_seq {
1097 u8 mac[ETH_ALEN];
1098 u16 seq_num;
1099 u16 frag_num;
1100 unsigned long packet_time;
1101 struct list_head list;
1102};
1103
1104struct ipw_error_elem { /* XXX */
1105 u32 desc;
1106 u32 time;
1107 u32 blink1;
1108 u32 blink2;
1109 u32 link1;
1110 u32 link2;
1111 u32 data;
1112};
1113
1114struct ipw_event { /* XXX */
1115 u32 event;
1116 u32 time;
1117 u32 data;
1118} __packed;
1119
1120struct ipw_fw_error { /* XXX */
1121 unsigned long jiffies;
1122 u32 status;
1123 u32 config;
1124 u32 elem_len;
1125 u32 log_len;
1126 struct ipw_error_elem *elem;
1127 struct ipw_event *log;
1128 u8 payload[0];
1129} __packed;
1130
1131#ifdef CONFIG_IPW2200_PROMISCUOUS
1132
1133enum ipw_prom_filter {
1134 IPW_PROM_CTL_HEADER_ONLY = (1 << 0),
1135 IPW_PROM_MGMT_HEADER_ONLY = (1 << 1),
1136 IPW_PROM_DATA_HEADER_ONLY = (1 << 2),
1137 IPW_PROM_ALL_HEADER_ONLY = 0xf, /* bits 0..3 */
1138 IPW_PROM_NO_TX = (1 << 4),
1139 IPW_PROM_NO_RX = (1 << 5),
1140 IPW_PROM_NO_CTL = (1 << 6),
1141 IPW_PROM_NO_MGMT = (1 << 7),
1142 IPW_PROM_NO_DATA = (1 << 8),
1143};
1144
1145struct ipw_priv;
1146struct ipw_prom_priv {
1147 struct ipw_priv *priv;
1148 struct libipw_device *ieee;
1149 enum ipw_prom_filter filter;
1150 int tx_packets;
1151 int rx_packets;
1152};
1153#endif
1154
1155#if defined(CONFIG_IPW2200_RADIOTAP) || defined(CONFIG_IPW2200_PROMISCUOUS)
1156/* Magic struct that slots into the radiotap header -- no reason
1157 * to build this manually element by element, we can write it much
1158 * more efficiently than we can parse it. ORDER MATTERS HERE
1159 *
1160 * When sent to us via the simulated Rx interface in sysfs, the entire
1161 * structure is provided regardless of any bits unset.
1162 */
1163struct ipw_rt_hdr {
1164 struct ieee80211_radiotap_header rt_hdr;
1165 u64 rt_tsf; /* TSF */ /* XXX */
1166 u8 rt_flags; /* radiotap packet flags */
1167 u8 rt_rate; /* rate in 500kb/s */
1168 __le16 rt_channel; /* channel in mhz */
1169 __le16 rt_chbitmask; /* channel bitfield */
1170 s8 rt_dbmsignal; /* signal in dbM, kluged to signed */
1171 s8 rt_dbmnoise;
1172 u8 rt_antenna; /* antenna number */
1173 u8 payload[0]; /* payload... */
1174} __packed;
1175#endif
1176
1177struct ipw_priv {
1178 /* ieee device used by generic ieee processing code */
1179 struct libipw_device *ieee;
1180
1181 spinlock_t lock;
1182 spinlock_t irq_lock;
1183 struct mutex mutex;
1184
1185 /* basic pci-network driver stuff */
1186 struct pci_dev *pci_dev;
1187 struct net_device *net_dev;
1188
1189#ifdef CONFIG_IPW2200_PROMISCUOUS
1190 /* Promiscuous mode */
1191 struct ipw_prom_priv *prom_priv;
1192 struct net_device *prom_net_dev;
1193#endif
1194
1195 /* pci hardware address support */
1196 void __iomem *hw_base;
1197 unsigned long hw_len;
1198
1199 struct fw_image_desc sram_desc;
1200
1201 /* result of ucode download */
1202 struct alive_command_responce dino_alive;
1203
1204 wait_queue_head_t wait_command_queue;
1205 wait_queue_head_t wait_state;
1206
1207 /* Rx and Tx DMA processing queues */
1208 struct ipw_rx_queue *rxq;
1209 struct clx2_tx_queue txq_cmd;
1210 struct clx2_tx_queue txq[4];
1211 u32 status;
1212 u32 config;
1213 u32 capability;
1214
1215 struct average average_missed_beacons;
1216 s16 exp_avg_rssi;
1217 s16 exp_avg_noise;
1218 u32 port_type;
1219 int rx_bufs_min; /**< minimum number of bufs in Rx queue */
1220 int rx_pend_max; /**< maximum pending buffers for one IRQ */
1221 u32 hcmd_seq; /**< sequence number for hcmd */
1222 u32 disassociate_threshold;
1223 u32 roaming_threshold;
1224
1225 struct ipw_associate assoc_request;
1226 struct libipw_network *assoc_network;
1227
1228 unsigned long ts_scan_abort;
1229 struct ipw_supported_rates rates;
1230 struct ipw_rates phy[3]; /**< PHY restrictions, per band */
1231 struct ipw_rates supp; /**< software defined */
1232 struct ipw_rates extended; /**< use for corresp. IE, AP only */
1233
1234 struct notif_link_deterioration last_link_deterioration; /** for statistics */
1235 struct ipw_cmd *hcmd; /**< host command currently executed */
1236
1237 wait_queue_head_t hcmd_wq; /**< host command waits for execution */
1238 u32 tsf_bcn[2]; /**< TSF from latest beacon */
1239
1240 struct notif_calibration calib; /**< last calibration */
1241
1242 /* ordinal interface with firmware */
1243 u32 table0_addr;
1244 u32 table0_len;
1245 u32 table1_addr;
1246 u32 table1_len;
1247 u32 table2_addr;
1248 u32 table2_len;
1249
1250 /* context information */
1251 u8 essid[IW_ESSID_MAX_SIZE];
1252 u8 essid_len;
1253 u8 nick[IW_ESSID_MAX_SIZE];
1254 u16 rates_mask;
1255 u8 channel;
1256 struct ipw_sys_config sys_config;
1257 u32 power_mode;
1258 u8 bssid[ETH_ALEN];
1259 u16 rts_threshold;
1260 u8 mac_addr[ETH_ALEN];
1261 u8 num_stations;
1262 u8 stations[MAX_STATIONS][ETH_ALEN];
1263 u8 short_retry_limit;
1264 u8 long_retry_limit;
1265
1266 u32 notif_missed_beacons;
1267
1268 /* Statistics and counters normalized with each association */
1269 u32 last_missed_beacons;
1270 u32 last_tx_packets;
1271 u32 last_rx_packets;
1272 u32 last_tx_failures;
1273 u32 last_rx_err;
1274 u32 last_rate;
1275
1276 u32 missed_adhoc_beacons;
1277 u32 missed_beacons;
1278 u32 rx_packets;
1279 u32 tx_packets;
1280 u32 quality;
1281
1282 u8 speed_scan[MAX_SPEED_SCAN];
1283 u8 speed_scan_pos;
1284
1285 u16 last_seq_num;
1286 u16 last_frag_num;
1287 unsigned long last_packet_time;
1288 struct list_head ibss_mac_hash[IPW_IBSS_MAC_HASH_SIZE];
1289
1290 /* eeprom */
1291 u8 eeprom[0x100]; /* 256 bytes of eeprom */
1292 u8 country[4];
1293 int eeprom_delay;
1294
1295 struct iw_statistics wstats;
1296
1297 struct iw_public_data wireless_data;
1298
1299 int user_requested_scan;
1300 u8 direct_scan_ssid[IW_ESSID_MAX_SIZE];
1301 u8 direct_scan_ssid_len;
1302
1303 struct delayed_work adhoc_check;
1304 struct work_struct associate;
1305 struct work_struct disassociate;
1306 struct work_struct system_config;
1307 struct work_struct rx_replenish;
1308 struct delayed_work request_scan;
1309 struct delayed_work request_direct_scan;
1310 struct delayed_work request_passive_scan;
1311 struct delayed_work scan_event;
1312 struct work_struct adapter_restart;
1313 struct delayed_work rf_kill;
1314 struct work_struct up;
1315 struct work_struct down;
1316 struct delayed_work gather_stats;
1317 struct work_struct abort_scan;
1318 struct work_struct roam;
1319 struct delayed_work scan_check;
1320 struct work_struct link_up;
1321 struct work_struct link_down;
1322
1323 struct tasklet_struct irq_tasklet;
1324
1325 /* LED related variables and work_struct */
1326 u8 nic_type;
1327 u32 led_activity_on;
1328 u32 led_activity_off;
1329 u32 led_association_on;
1330 u32 led_association_off;
1331 u32 led_ofdm_on;
1332 u32 led_ofdm_off;
1333
1334 struct delayed_work led_link_on;
1335 struct delayed_work led_link_off;
1336 struct delayed_work led_act_off;
1337 struct work_struct merge_networks;
1338
1339 struct ipw_cmd_log *cmdlog;
1340 int cmdlog_len;
1341 int cmdlog_pos;
1342
1343#define IPW_2200BG 1
1344#define IPW_2915ABG 2
1345 u8 adapter;
1346
1347 s8 tx_power;
1348
1349 /* Track time in suspend */
1350 unsigned long suspend_at;
1351 unsigned long suspend_time;
1352
1353#ifdef CONFIG_PM
1354 u32 pm_state[16];
1355#endif
1356
1357 struct ipw_fw_error *error;
1358
1359 /* network state */
1360
1361 /* Used to pass the current INTA value from ISR to Tasklet */
1362 u32 isr_inta;
1363
1364 /* QoS */
1365 struct ipw_qos_info qos_data;
1366 struct work_struct qos_activate;
1367 /*********************************/
1368
1369 /* debugging info */
1370 u32 indirect_dword;
1371 u32 direct_dword;
1372 u32 indirect_byte;
1373}; /*ipw_priv */
1374
1375/* debug macros */
1376
1377/* Debug and printf string expansion helpers for printing bitfields */
1378#define BIT_FMT8 "%c%c%c%c-%c%c%c%c"
1379#define BIT_FMT16 BIT_FMT8 ":" BIT_FMT8
1380#define BIT_FMT32 BIT_FMT16 " " BIT_FMT16
1381
1382#define BITC(x,y) (((x>>y)&1)?'1':'0')
1383#define BIT_ARG8(x) \
1384BITC(x,7),BITC(x,6),BITC(x,5),BITC(x,4),\
1385BITC(x,3),BITC(x,2),BITC(x,1),BITC(x,0)
1386
1387#define BIT_ARG16(x) \
1388BITC(x,15),BITC(x,14),BITC(x,13),BITC(x,12),\
1389BITC(x,11),BITC(x,10),BITC(x,9),BITC(x,8),\
1390BIT_ARG8(x)
1391
1392#define BIT_ARG32(x) \
1393BITC(x,31),BITC(x,30),BITC(x,29),BITC(x,28),\
1394BITC(x,27),BITC(x,26),BITC(x,25),BITC(x,24),\
1395BITC(x,23),BITC(x,22),BITC(x,21),BITC(x,20),\
1396BITC(x,19),BITC(x,18),BITC(x,17),BITC(x,16),\
1397BIT_ARG16(x)
1398
1399
1400#define IPW_DEBUG(level, fmt, args...) \
1401do { if (ipw_debug_level & (level)) \
1402 printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \
1403 in_interrupt() ? 'I' : 'U', __func__ , ## args); } while (0)
1404
1405#ifdef CONFIG_IPW2200_DEBUG
1406#define IPW_LL_DEBUG(level, fmt, args...) \
1407do { if (ipw_debug_level & (level)) \
1408 printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \
1409 in_interrupt() ? 'I' : 'U', __func__ , ## args); } while (0)
1410#else
1411#define IPW_LL_DEBUG(level, fmt, args...) do {} while (0)
1412#endif /* CONFIG_IPW2200_DEBUG */
1413
1414/*
1415 * To use the debug system;
1416 *
1417 * If you are defining a new debug classification, simply add it to the #define
1418 * list here in the form of:
1419 *
1420 * #define IPW_DL_xxxx VALUE
1421 *
1422 * shifting value to the left one bit from the previous entry. xxxx should be
1423 * the name of the classification (for example, WEP)
1424 *
1425 * You then need to either add a IPW_xxxx_DEBUG() macro definition for your
1426 * classification, or use IPW_DEBUG(IPW_DL_xxxx, ...) whenever you want
1427 * to send output to that classification.
1428 *
1429 * To add your debug level to the list of levels seen when you perform
1430 *
1431 * % cat /proc/net/ipw/debug_level
1432 *
1433 * you simply need to add your entry to the ipw_debug_levels array.
1434 *
1435 * If you do not see debug_level in /proc/net/ipw then you do not have
1436 * CONFIG_IPW2200_DEBUG defined in your kernel configuration
1437 *
1438 */
1439
1440#define IPW_DL_ERROR (1<<0)
1441#define IPW_DL_WARNING (1<<1)
1442#define IPW_DL_INFO (1<<2)
1443#define IPW_DL_WX (1<<3)
1444#define IPW_DL_HOST_COMMAND (1<<5)
1445#define IPW_DL_STATE (1<<6)
1446
1447#define IPW_DL_NOTIF (1<<10)
1448#define IPW_DL_SCAN (1<<11)
1449#define IPW_DL_ASSOC (1<<12)
1450#define IPW_DL_DROP (1<<13)
1451#define IPW_DL_IOCTL (1<<14)
1452
1453#define IPW_DL_MANAGE (1<<15)
1454#define IPW_DL_FW (1<<16)
1455#define IPW_DL_RF_KILL (1<<17)
1456#define IPW_DL_FW_ERRORS (1<<18)
1457
1458#define IPW_DL_LED (1<<19)
1459
1460#define IPW_DL_ORD (1<<20)
1461
1462#define IPW_DL_FRAG (1<<21)
1463#define IPW_DL_WEP (1<<22)
1464#define IPW_DL_TX (1<<23)
1465#define IPW_DL_RX (1<<24)
1466#define IPW_DL_ISR (1<<25)
1467#define IPW_DL_FW_INFO (1<<26)
1468#define IPW_DL_IO (1<<27)
1469#define IPW_DL_TRACE (1<<28)
1470
1471#define IPW_DL_STATS (1<<29)
1472#define IPW_DL_MERGE (1<<30)
1473#define IPW_DL_QOS (1<<31)
1474
1475#define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
1476#define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
1477#define IPW_DEBUG_INFO(f, a...) IPW_DEBUG(IPW_DL_INFO, f, ## a)
1478
1479#define IPW_DEBUG_WX(f, a...) IPW_DEBUG(IPW_DL_WX, f, ## a)
1480#define IPW_DEBUG_SCAN(f, a...) IPW_DEBUG(IPW_DL_SCAN, f, ## a)
1481#define IPW_DEBUG_TRACE(f, a...) IPW_LL_DEBUG(IPW_DL_TRACE, f, ## a)
1482#define IPW_DEBUG_RX(f, a...) IPW_LL_DEBUG(IPW_DL_RX, f, ## a)
1483#define IPW_DEBUG_TX(f, a...) IPW_LL_DEBUG(IPW_DL_TX, f, ## a)
1484#define IPW_DEBUG_ISR(f, a...) IPW_LL_DEBUG(IPW_DL_ISR, f, ## a)
1485#define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a)
1486#define IPW_DEBUG_LED(f, a...) IPW_LL_DEBUG(IPW_DL_LED, f, ## a)
1487#define IPW_DEBUG_WEP(f, a...) IPW_LL_DEBUG(IPW_DL_WEP, f, ## a)
1488#define IPW_DEBUG_HC(f, a...) IPW_LL_DEBUG(IPW_DL_HOST_COMMAND, f, ## a)
1489#define IPW_DEBUG_FRAG(f, a...) IPW_LL_DEBUG(IPW_DL_FRAG, f, ## a)
1490#define IPW_DEBUG_FW(f, a...) IPW_LL_DEBUG(IPW_DL_FW, f, ## a)
1491#define IPW_DEBUG_RF_KILL(f, a...) IPW_DEBUG(IPW_DL_RF_KILL, f, ## a)
1492#define IPW_DEBUG_DROP(f, a...) IPW_DEBUG(IPW_DL_DROP, f, ## a)
1493#define IPW_DEBUG_IO(f, a...) IPW_LL_DEBUG(IPW_DL_IO, f, ## a)
1494#define IPW_DEBUG_ORD(f, a...) IPW_LL_DEBUG(IPW_DL_ORD, f, ## a)
1495#define IPW_DEBUG_FW_INFO(f, a...) IPW_LL_DEBUG(IPW_DL_FW_INFO, f, ## a)
1496#define IPW_DEBUG_NOTIF(f, a...) IPW_DEBUG(IPW_DL_NOTIF, f, ## a)
1497#define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1498#define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1499#define IPW_DEBUG_STATS(f, a...) IPW_LL_DEBUG(IPW_DL_STATS, f, ## a)
1500#define IPW_DEBUG_MERGE(f, a...) IPW_LL_DEBUG(IPW_DL_MERGE, f, ## a)
1501#define IPW_DEBUG_QOS(f, a...) IPW_LL_DEBUG(IPW_DL_QOS, f, ## a)
1502
1503#include <linux/ctype.h>
1504
1505/*
1506* Register bit definitions
1507*/
1508
1509#define IPW_INTA_RW 0x00000008
1510#define IPW_INTA_MASK_R 0x0000000C
1511#define IPW_INDIRECT_ADDR 0x00000010
1512#define IPW_INDIRECT_DATA 0x00000014
1513#define IPW_AUTOINC_ADDR 0x00000018
1514#define IPW_AUTOINC_DATA 0x0000001C
1515#define IPW_RESET_REG 0x00000020
1516#define IPW_GP_CNTRL_RW 0x00000024
1517
1518#define IPW_READ_INT_REGISTER 0xFF4
1519
1520#define IPW_GP_CNTRL_BIT_INIT_DONE 0x00000004
1521
1522#define IPW_REGISTER_DOMAIN1_END 0x00001000
1523#define IPW_SRAM_READ_INT_REGISTER 0x00000ff4
1524
1525#define IPW_SHARED_LOWER_BOUND 0x00000200
1526#define IPW_INTERRUPT_AREA_LOWER_BOUND 0x00000f80
1527
1528#define IPW_NIC_SRAM_LOWER_BOUND 0x00000000
1529#define IPW_NIC_SRAM_UPPER_BOUND 0x00030000
1530
1531#define IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29)
1532#define IPW_GP_CNTRL_BIT_CLOCK_READY 0x00000001
1533#define IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002
1534
1535/*
1536 * RESET Register Bit Indexes
1537 */
1538#define CBD_RESET_REG_PRINCETON_RESET (1<<0)
1539#define IPW_START_STANDBY (1<<2)
1540#define IPW_ACTIVITY_LED (1<<4)
1541#define IPW_ASSOCIATED_LED (1<<5)
1542#define IPW_OFDM_LED (1<<6)
1543#define IPW_RESET_REG_SW_RESET (1<<7)
1544#define IPW_RESET_REG_MASTER_DISABLED (1<<8)
1545#define IPW_RESET_REG_STOP_MASTER (1<<9)
1546#define IPW_GATE_ODMA (1<<25)
1547#define IPW_GATE_IDMA (1<<26)
1548#define IPW_ARC_KESHET_CONFIG (1<<27)
1549#define IPW_GATE_ADMA (1<<29)
1550
1551#define IPW_CSR_CIS_UPPER_BOUND 0x00000200
1552#define IPW_DOMAIN_0_END 0x1000
1553#define CLX_MEM_BAR_SIZE 0x1000
1554
1555/* Dino/baseband control registers bits */
1556
1557#define DINO_ENABLE_SYSTEM 0x80 /* 1 = baseband processor on, 0 = reset */
1558#define DINO_ENABLE_CS 0x40 /* 1 = enable ucode load */
1559#define DINO_RXFIFO_DATA 0x01 /* 1 = data available */
1560#define IPW_BASEBAND_CONTROL_STATUS 0X00200000
1561#define IPW_BASEBAND_TX_FIFO_WRITE 0X00200004
1562#define IPW_BASEBAND_RX_FIFO_READ 0X00200004
1563#define IPW_BASEBAND_CONTROL_STORE 0X00200010
1564
1565#define IPW_INTERNAL_CMD_EVENT 0X00300004
1566#define IPW_BASEBAND_POWER_DOWN 0x00000001
1567
1568#define IPW_MEM_HALT_AND_RESET 0x003000e0
1569
1570/* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */
1571#define IPW_BIT_HALT_RESET_ON 0x80000000
1572#define IPW_BIT_HALT_RESET_OFF 0x00000000
1573
1574#define CB_LAST_VALID 0x20000000
1575#define CB_INT_ENABLED 0x40000000
1576#define CB_VALID 0x80000000
1577#define CB_SRC_LE 0x08000000
1578#define CB_DEST_LE 0x04000000
1579#define CB_SRC_AUTOINC 0x00800000
1580#define CB_SRC_IO_GATED 0x00400000
1581#define CB_DEST_AUTOINC 0x00080000
1582#define CB_SRC_SIZE_LONG 0x00200000
1583#define CB_DEST_SIZE_LONG 0x00020000
1584
1585/* DMA DEFINES */
1586
1587#define DMA_CONTROL_SMALL_CB_CONST_VALUE 0x00540000
1588#define DMA_CB_STOP_AND_ABORT 0x00000C00
1589#define DMA_CB_START 0x00000100
1590
1591#define IPW_SHARED_SRAM_SIZE 0x00030000
1592#define IPW_SHARED_SRAM_DMA_CONTROL 0x00027000
1593#define CB_MAX_LENGTH 0x1FFF
1594
1595#define IPW_HOST_EEPROM_DATA_SRAM_SIZE 0xA18
1596#define IPW_EEPROM_IMAGE_SIZE 0x100
1597
1598/* DMA defs */
1599#define IPW_DMA_I_CURRENT_CB 0x003000D0
1600#define IPW_DMA_O_CURRENT_CB 0x003000D4
1601#define IPW_DMA_I_DMA_CONTROL 0x003000A4
1602#define IPW_DMA_I_CB_BASE 0x003000A0
1603
1604#define IPW_TX_CMD_QUEUE_BD_BASE 0x00000200
1605#define IPW_TX_CMD_QUEUE_BD_SIZE 0x00000204
1606#define IPW_TX_QUEUE_0_BD_BASE 0x00000208
1607#define IPW_TX_QUEUE_0_BD_SIZE (0x0000020C)
1608#define IPW_TX_QUEUE_1_BD_BASE 0x00000210
1609#define IPW_TX_QUEUE_1_BD_SIZE 0x00000214
1610#define IPW_TX_QUEUE_2_BD_BASE 0x00000218
1611#define IPW_TX_QUEUE_2_BD_SIZE (0x0000021C)
1612#define IPW_TX_QUEUE_3_BD_BASE 0x00000220
1613#define IPW_TX_QUEUE_3_BD_SIZE 0x00000224
1614#define IPW_RX_BD_BASE 0x00000240
1615#define IPW_RX_BD_SIZE 0x00000244
1616#define IPW_RFDS_TABLE_LOWER 0x00000500
1617
1618#define IPW_TX_CMD_QUEUE_READ_INDEX 0x00000280
1619#define IPW_TX_QUEUE_0_READ_INDEX 0x00000284
1620#define IPW_TX_QUEUE_1_READ_INDEX 0x00000288
1621#define IPW_TX_QUEUE_2_READ_INDEX (0x0000028C)
1622#define IPW_TX_QUEUE_3_READ_INDEX 0x00000290
1623#define IPW_RX_READ_INDEX (0x000002A0)
1624
1625#define IPW_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80)
1626#define IPW_TX_QUEUE_0_WRITE_INDEX (0x00000F84)
1627#define IPW_TX_QUEUE_1_WRITE_INDEX (0x00000F88)
1628#define IPW_TX_QUEUE_2_WRITE_INDEX (0x00000F8C)
1629#define IPW_TX_QUEUE_3_WRITE_INDEX (0x00000F90)
1630#define IPW_RX_WRITE_INDEX (0x00000FA0)
1631
1632/*
1633 * EEPROM Related Definitions
1634 */
1635
1636#define IPW_EEPROM_DATA_SRAM_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x814)
1637#define IPW_EEPROM_DATA_SRAM_SIZE (IPW_SHARED_LOWER_BOUND + 0x818)
1638#define IPW_EEPROM_LOAD_DISABLE (IPW_SHARED_LOWER_BOUND + 0x81C)
1639#define IPW_EEPROM_DATA (IPW_SHARED_LOWER_BOUND + 0x820)
1640#define IPW_EEPROM_UPPER_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x9E0)
1641
1642#define IPW_STATION_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0xA0C)
1643#define IPW_STATION_TABLE_UPPER (IPW_SHARED_LOWER_BOUND + 0xB0C)
1644#define IPW_REQUEST_ATIM (IPW_SHARED_LOWER_BOUND + 0xB0C)
1645#define IPW_ATIM_SENT (IPW_SHARED_LOWER_BOUND + 0xB10)
1646#define IPW_WHO_IS_AWAKE (IPW_SHARED_LOWER_BOUND + 0xB14)
1647#define IPW_DURING_ATIM_WINDOW (IPW_SHARED_LOWER_BOUND + 0xB18)
1648
1649#define MSB 1
1650#define LSB 0
1651#define WORD_TO_BYTE(_word) ((_word) * sizeof(u16))
1652
1653#define GET_EEPROM_ADDR(_wordoffset,_byteoffset) \
1654 ( WORD_TO_BYTE(_wordoffset) + (_byteoffset) )
1655
1656/* EEPROM access by BYTE */
1657#define EEPROM_PME_CAPABILITY (GET_EEPROM_ADDR(0x09,MSB)) /* 1 byte */
1658#define EEPROM_MAC_ADDRESS (GET_EEPROM_ADDR(0x21,LSB)) /* 6 byte */
1659#define EEPROM_VERSION (GET_EEPROM_ADDR(0x24,MSB)) /* 1 byte */
1660#define EEPROM_NIC_TYPE (GET_EEPROM_ADDR(0x25,LSB)) /* 1 byte */
1661#define EEPROM_SKU_CAPABILITY (GET_EEPROM_ADDR(0x25,MSB)) /* 1 byte */
1662#define EEPROM_COUNTRY_CODE (GET_EEPROM_ADDR(0x26,LSB)) /* 3 bytes */
1663#define EEPROM_IBSS_CHANNELS_BG (GET_EEPROM_ADDR(0x28,LSB)) /* 2 bytes */
1664#define EEPROM_IBSS_CHANNELS_A (GET_EEPROM_ADDR(0x29,MSB)) /* 5 bytes */
1665#define EEPROM_BSS_CHANNELS_BG (GET_EEPROM_ADDR(0x2c,LSB)) /* 2 bytes */
1666#define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */
1667
1668/* NIC type as found in the one byte EEPROM_NIC_TYPE offset */
1669#define EEPROM_NIC_TYPE_0 0
1670#define EEPROM_NIC_TYPE_1 1
1671#define EEPROM_NIC_TYPE_2 2
1672#define EEPROM_NIC_TYPE_3 3
1673#define EEPROM_NIC_TYPE_4 4
1674
1675/* Bluetooth Coexistence capabilities as found in EEPROM_SKU_CAPABILITY */
1676#define EEPROM_SKU_CAP_BT_CHANNEL_SIG 0x01 /* we can tell BT our channel # */
1677#define EEPROM_SKU_CAP_BT_PRIORITY 0x02 /* BT can take priority over us */
1678#define EEPROM_SKU_CAP_BT_OOB 0x04 /* we can signal BT out-of-band */
1679
1680#define FW_MEM_REG_LOWER_BOUND 0x00300000
1681#define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40)
1682#define IPW_EVENT_REG (FW_MEM_REG_LOWER_BOUND + 0x04)
1683#define EEPROM_BIT_SK (1<<0)
1684#define EEPROM_BIT_CS (1<<1)
1685#define EEPROM_BIT_DI (1<<2)
1686#define EEPROM_BIT_DO (1<<4)
1687
1688#define EEPROM_CMD_READ 0x2
1689
1690/* Interrupts masks */
1691#define IPW_INTA_NONE 0x00000000
1692
1693#define IPW_INTA_BIT_RX_TRANSFER 0x00000002
1694#define IPW_INTA_BIT_STATUS_CHANGE 0x00000010
1695#define IPW_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020
1696
1697//Inta Bits for CF
1698#define IPW_INTA_BIT_TX_CMD_QUEUE 0x00000800
1699#define IPW_INTA_BIT_TX_QUEUE_1 0x00001000
1700#define IPW_INTA_BIT_TX_QUEUE_2 0x00002000
1701#define IPW_INTA_BIT_TX_QUEUE_3 0x00004000
1702#define IPW_INTA_BIT_TX_QUEUE_4 0x00008000
1703
1704#define IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000
1705
1706#define IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000
1707#define IPW_INTA_BIT_POWER_DOWN 0x00200000
1708
1709#define IPW_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000
1710#define IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000
1711#define IPW_INTA_BIT_RF_KILL_DONE 0x04000000
1712#define IPW_INTA_BIT_FATAL_ERROR 0x40000000
1713#define IPW_INTA_BIT_PARITY_ERROR 0x80000000
1714
1715/* Interrupts enabled at init time. */
1716#define IPW_INTA_MASK_ALL \
1717 (IPW_INTA_BIT_TX_QUEUE_1 | \
1718 IPW_INTA_BIT_TX_QUEUE_2 | \
1719 IPW_INTA_BIT_TX_QUEUE_3 | \
1720 IPW_INTA_BIT_TX_QUEUE_4 | \
1721 IPW_INTA_BIT_TX_CMD_QUEUE | \
1722 IPW_INTA_BIT_RX_TRANSFER | \
1723 IPW_INTA_BIT_FATAL_ERROR | \
1724 IPW_INTA_BIT_PARITY_ERROR | \
1725 IPW_INTA_BIT_STATUS_CHANGE | \
1726 IPW_INTA_BIT_FW_INITIALIZATION_DONE | \
1727 IPW_INTA_BIT_BEACON_PERIOD_EXPIRED | \
1728 IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \
1729 IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN | \
1730 IPW_INTA_BIT_POWER_DOWN | \
1731 IPW_INTA_BIT_RF_KILL_DONE )
1732
1733/* FW event log definitions */
1734#define EVENT_ELEM_SIZE (3 * sizeof(u32))
1735#define EVENT_START_OFFSET (1 * sizeof(u32) + 2 * sizeof(u16))
1736
1737/* FW error log definitions */
1738#define ERROR_ELEM_SIZE (7 * sizeof(u32))
1739#define ERROR_START_OFFSET (1 * sizeof(u32))
1740
1741/* TX power level (dbm) */
1742#define IPW_TX_POWER_MIN -12
1743#define IPW_TX_POWER_MAX 20
1744#define IPW_TX_POWER_DEFAULT IPW_TX_POWER_MAX
1745
1746enum {
1747 IPW_FW_ERROR_OK = 0,
1748 IPW_FW_ERROR_FAIL,
1749 IPW_FW_ERROR_MEMORY_UNDERFLOW,
1750 IPW_FW_ERROR_MEMORY_OVERFLOW,
1751 IPW_FW_ERROR_BAD_PARAM,
1752 IPW_FW_ERROR_BAD_CHECKSUM,
1753 IPW_FW_ERROR_NMI_INTERRUPT,
1754 IPW_FW_ERROR_BAD_DATABASE,
1755 IPW_FW_ERROR_ALLOC_FAIL,
1756 IPW_FW_ERROR_DMA_UNDERRUN,
1757 IPW_FW_ERROR_DMA_STATUS,
1758 IPW_FW_ERROR_DINO_ERROR,
1759 IPW_FW_ERROR_EEPROM_ERROR,
1760 IPW_FW_ERROR_SYSASSERT,
1761 IPW_FW_ERROR_FATAL_ERROR
1762};
1763
1764#define AUTH_OPEN 0
1765#define AUTH_SHARED_KEY 1
1766#define AUTH_LEAP 2
1767#define AUTH_IGNORE 3
1768
1769#define HC_ASSOCIATE 0
1770#define HC_REASSOCIATE 1
1771#define HC_DISASSOCIATE 2
1772#define HC_IBSS_START 3
1773#define HC_IBSS_RECONF 4
1774#define HC_DISASSOC_QUIET 5
1775
1776#define HC_QOS_SUPPORT_ASSOC cpu_to_le16(0x01)
1777
1778#define IPW_RATE_CAPABILITIES 1
1779#define IPW_RATE_CONNECT 0
1780
1781/*
1782 * Rate values and masks
1783 */
1784#define IPW_TX_RATE_1MB 0x0A
1785#define IPW_TX_RATE_2MB 0x14
1786#define IPW_TX_RATE_5MB 0x37
1787#define IPW_TX_RATE_6MB 0x0D
1788#define IPW_TX_RATE_9MB 0x0F
1789#define IPW_TX_RATE_11MB 0x6E
1790#define IPW_TX_RATE_12MB 0x05
1791#define IPW_TX_RATE_18MB 0x07
1792#define IPW_TX_RATE_24MB 0x09
1793#define IPW_TX_RATE_36MB 0x0B
1794#define IPW_TX_RATE_48MB 0x01
1795#define IPW_TX_RATE_54MB 0x03
1796
1797#define IPW_ORD_TABLE_ID_MASK 0x0000FF00
1798#define IPW_ORD_TABLE_VALUE_MASK 0x000000FF
1799
1800#define IPW_ORD_TABLE_0_MASK 0x0000F000
1801#define IPW_ORD_TABLE_1_MASK 0x0000F100
1802#define IPW_ORD_TABLE_2_MASK 0x0000F200
1803#define IPW_ORD_TABLE_3_MASK 0x0000F300
1804#define IPW_ORD_TABLE_4_MASK 0x0000F400
1805#define IPW_ORD_TABLE_5_MASK 0x0000F500
1806#define IPW_ORD_TABLE_6_MASK 0x0000F600
1807#define IPW_ORD_TABLE_7_MASK 0x0000F700
1808
1809/*
1810 * Table 0 Entries (all entries are 32 bits)
1811 */
1812enum {
1813 IPW_ORD_STAT_TX_CURR_RATE = IPW_ORD_TABLE_0_MASK + 1,
1814 IPW_ORD_STAT_FRAG_TRESHOLD,
1815 IPW_ORD_STAT_RTS_THRESHOLD,
1816 IPW_ORD_STAT_TX_HOST_REQUESTS,
1817 IPW_ORD_STAT_TX_HOST_COMPLETE,
1818 IPW_ORD_STAT_TX_DIR_DATA,
1819 IPW_ORD_STAT_TX_DIR_DATA_B_1,
1820 IPW_ORD_STAT_TX_DIR_DATA_B_2,
1821 IPW_ORD_STAT_TX_DIR_DATA_B_5_5,
1822 IPW_ORD_STAT_TX_DIR_DATA_B_11,
1823 /* Hole */
1824
1825 IPW_ORD_STAT_TX_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 19,
1826 IPW_ORD_STAT_TX_DIR_DATA_G_2,
1827 IPW_ORD_STAT_TX_DIR_DATA_G_5_5,
1828 IPW_ORD_STAT_TX_DIR_DATA_G_6,
1829 IPW_ORD_STAT_TX_DIR_DATA_G_9,
1830 IPW_ORD_STAT_TX_DIR_DATA_G_11,
1831 IPW_ORD_STAT_TX_DIR_DATA_G_12,
1832 IPW_ORD_STAT_TX_DIR_DATA_G_18,
1833 IPW_ORD_STAT_TX_DIR_DATA_G_24,
1834 IPW_ORD_STAT_TX_DIR_DATA_G_36,
1835 IPW_ORD_STAT_TX_DIR_DATA_G_48,
1836 IPW_ORD_STAT_TX_DIR_DATA_G_54,
1837 IPW_ORD_STAT_TX_NON_DIR_DATA,
1838 IPW_ORD_STAT_TX_NON_DIR_DATA_B_1,
1839 IPW_ORD_STAT_TX_NON_DIR_DATA_B_2,
1840 IPW_ORD_STAT_TX_NON_DIR_DATA_B_5_5,
1841 IPW_ORD_STAT_TX_NON_DIR_DATA_B_11,
1842 /* Hole */
1843
1844 IPW_ORD_STAT_TX_NON_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 44,
1845 IPW_ORD_STAT_TX_NON_DIR_DATA_G_2,
1846 IPW_ORD_STAT_TX_NON_DIR_DATA_G_5_5,
1847 IPW_ORD_STAT_TX_NON_DIR_DATA_G_6,
1848 IPW_ORD_STAT_TX_NON_DIR_DATA_G_9,
1849 IPW_ORD_STAT_TX_NON_DIR_DATA_G_11,
1850 IPW_ORD_STAT_TX_NON_DIR_DATA_G_12,
1851 IPW_ORD_STAT_TX_NON_DIR_DATA_G_18,
1852 IPW_ORD_STAT_TX_NON_DIR_DATA_G_24,
1853 IPW_ORD_STAT_TX_NON_DIR_DATA_G_36,
1854 IPW_ORD_STAT_TX_NON_DIR_DATA_G_48,
1855 IPW_ORD_STAT_TX_NON_DIR_DATA_G_54,
1856 IPW_ORD_STAT_TX_RETRY,
1857 IPW_ORD_STAT_TX_FAILURE,
1858 IPW_ORD_STAT_RX_ERR_CRC,
1859 IPW_ORD_STAT_RX_ERR_ICV,
1860 IPW_ORD_STAT_RX_NO_BUFFER,
1861 IPW_ORD_STAT_FULL_SCANS,
1862 IPW_ORD_STAT_PARTIAL_SCANS,
1863 IPW_ORD_STAT_TGH_ABORTED_SCANS,
1864 IPW_ORD_STAT_TX_TOTAL_BYTES,
1865 IPW_ORD_STAT_CURR_RSSI_RAW,
1866 IPW_ORD_STAT_RX_BEACON,
1867 IPW_ORD_STAT_MISSED_BEACONS,
1868 IPW_ORD_TABLE_0_LAST
1869};
1870
1871#define IPW_RSSI_TO_DBM 112
1872
1873/* Table 1 Entries
1874 */
1875enum {
1876 IPW_ORD_TABLE_1_LAST = IPW_ORD_TABLE_1_MASK | 1,
1877};
1878
1879/*
1880 * Table 2 Entries
1881 *
1882 * FW_VERSION: 16 byte string
1883 * FW_DATE: 16 byte string (only 14 bytes used)
1884 * UCODE_VERSION: 4 byte version code
1885 * UCODE_DATE: 5 bytes code code
1886 * ADDAPTER_MAC: 6 byte MAC address
1887 * RTC: 4 byte clock
1888 */
1889enum {
1890 IPW_ORD_STAT_FW_VERSION = IPW_ORD_TABLE_2_MASK | 1,
1891 IPW_ORD_STAT_FW_DATE,
1892 IPW_ORD_STAT_UCODE_VERSION,
1893 IPW_ORD_STAT_UCODE_DATE,
1894 IPW_ORD_STAT_ADAPTER_MAC,
1895 IPW_ORD_STAT_RTC,
1896 IPW_ORD_TABLE_2_LAST
1897};
1898
1899/* Table 3 */
1900enum {
1901 IPW_ORD_STAT_TX_PACKET = IPW_ORD_TABLE_3_MASK | 0,
1902 IPW_ORD_STAT_TX_PACKET_FAILURE,
1903 IPW_ORD_STAT_TX_PACKET_SUCCESS,
1904 IPW_ORD_STAT_TX_PACKET_ABORTED,
1905 IPW_ORD_TABLE_3_LAST
1906};
1907
1908/* Table 4 */
1909enum {
1910 IPW_ORD_TABLE_4_LAST = IPW_ORD_TABLE_4_MASK
1911};
1912
1913/* Table 5 */
1914enum {
1915 IPW_ORD_STAT_AVAILABLE_AP_COUNT = IPW_ORD_TABLE_5_MASK,
1916 IPW_ORD_STAT_AP_ASSNS,
1917 IPW_ORD_STAT_ROAM,
1918 IPW_ORD_STAT_ROAM_CAUSE_MISSED_BEACONS,
1919 IPW_ORD_STAT_ROAM_CAUSE_UNASSOC,
1920 IPW_ORD_STAT_ROAM_CAUSE_RSSI,
1921 IPW_ORD_STAT_ROAM_CAUSE_LINK_QUALITY,
1922 IPW_ORD_STAT_ROAM_CAUSE_AP_LOAD_BALANCE,
1923 IPW_ORD_STAT_ROAM_CAUSE_AP_NO_TX,
1924 IPW_ORD_STAT_LINK_UP,
1925 IPW_ORD_STAT_LINK_DOWN,
1926 IPW_ORD_ANTENNA_DIVERSITY,
1927 IPW_ORD_CURR_FREQ,
1928 IPW_ORD_TABLE_5_LAST
1929};
1930
1931/* Table 6 */
1932enum {
1933 IPW_ORD_COUNTRY_CODE = IPW_ORD_TABLE_6_MASK,
1934 IPW_ORD_CURR_BSSID,
1935 IPW_ORD_CURR_SSID,
1936 IPW_ORD_TABLE_6_LAST
1937};
1938
1939/* Table 7 */
1940enum {
1941 IPW_ORD_STAT_PERCENT_MISSED_BEACONS = IPW_ORD_TABLE_7_MASK,
1942 IPW_ORD_STAT_PERCENT_TX_RETRIES,
1943 IPW_ORD_STAT_PERCENT_LINK_QUALITY,
1944 IPW_ORD_STAT_CURR_RSSI_DBM,
1945 IPW_ORD_TABLE_7_LAST
1946};
1947
1948#define IPW_ERROR_LOG (IPW_SHARED_LOWER_BOUND + 0x410)
1949#define IPW_EVENT_LOG (IPW_SHARED_LOWER_BOUND + 0x414)
1950#define IPW_ORDINALS_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0x500)
1951#define IPW_ORDINALS_TABLE_0 (IPW_SHARED_LOWER_BOUND + 0x180)
1952#define IPW_ORDINALS_TABLE_1 (IPW_SHARED_LOWER_BOUND + 0x184)
1953#define IPW_ORDINALS_TABLE_2 (IPW_SHARED_LOWER_BOUND + 0x188)
1954#define IPW_MEM_FIXED_OVERRIDE (IPW_SHARED_LOWER_BOUND + 0x41C)
1955
1956struct ipw_fixed_rate {
1957 __le16 tx_rates;
1958 __le16 reserved;
1959} __packed;
1960
1961#define IPW_INDIRECT_ADDR_MASK (~0x3ul)
1962
1963struct host_cmd {
1964 u8 cmd;
1965 u8 len;
1966 u16 reserved;
1967 u32 *param;
1968} __packed; /* XXX */
1969
1970struct cmdlog_host_cmd {
1971 u8 cmd;
1972 u8 len;
1973 __le16 reserved;
1974 char param[124];
1975} __packed;
1976
1977struct ipw_cmd_log {
1978 unsigned long jiffies;
1979 int retcode;
1980 struct cmdlog_host_cmd cmd;
1981};
1982
1983/* SysConfig command parameters ... */
1984/* bt_coexistence param */
1985#define CFG_BT_COEXISTENCE_SIGNAL_CHNL 0x01 /* tell BT our chnl # */
1986#define CFG_BT_COEXISTENCE_DEFER 0x02 /* defer our Tx if BT traffic */
1987#define CFG_BT_COEXISTENCE_KILL 0x04 /* kill our Tx if BT traffic */
1988#define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08 /* multimedia extensions */
1989#define CFG_BT_COEXISTENCE_OOB 0x10 /* signal BT via out-of-band */
1990
1991/* clear-to-send to self param */
1992#define CFG_CTS_TO_ITSELF_ENABLED_MIN 0x00
1993#define CFG_CTS_TO_ITSELF_ENABLED_MAX 0x01
1994#define CFG_CTS_TO_ITSELF_ENABLED_DEF CFG_CTS_TO_ITSELF_ENABLED_MIN
1995
1996/* Antenna diversity param (h/w can select best antenna, based on signal) */
1997#define CFG_SYS_ANTENNA_BOTH 0x00 /* NIC selects best antenna */
1998#define CFG_SYS_ANTENNA_A 0x01 /* force antenna A */
1999#define CFG_SYS_ANTENNA_B 0x03 /* force antenna B */
2000#define CFG_SYS_ANTENNA_SLOW_DIV 0x02 /* consider background noise */
2001
2002/*
2003 * The definitions below were lifted off the ipw2100 driver, which only
2004 * supports 'b' mode, so I'm sure these are not exactly correct.
2005 *
2006 * Somebody fix these!!
2007 */
2008#define REG_MIN_CHANNEL 0
2009#define REG_MAX_CHANNEL 14
2010
2011#define REG_CHANNEL_MASK 0x00003FFF
2012#define IPW_IBSS_11B_DEFAULT_MASK 0x87ff
2013
2014#define IPW_MAX_CONFIG_RETRIES 10
2015
2016#endif /* __ipw2200_h__ */