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1/*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called "COPYING".
23 *
24 */
25
26#ifndef _NETXEN_NIC_H_
27#define _NETXEN_NIC_H_
28
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/types.h>
32#include <linux/ioport.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
35#include <linux/etherdevice.h>
36#include <linux/ip.h>
37#include <linux/in.h>
38#include <linux/tcp.h>
39#include <linux/skbuff.h>
40#include <linux/firmware.h>
41
42#include <linux/ethtool.h>
43#include <linux/mii.h>
44#include <linux/timer.h>
45
46#include <linux/vmalloc.h>
47
48#include <asm/io.h>
49#include <asm/byteorder.h>
50
51#include "netxen_nic_hdr.h"
52#include "netxen_nic_hw.h"
53
54#define _NETXEN_NIC_LINUX_MAJOR 4
55#define _NETXEN_NIC_LINUX_MINOR 0
56#define _NETXEN_NIC_LINUX_SUBVERSION 76
57#define NETXEN_NIC_LINUX_VERSIONID "4.0.76"
58
59#define NETXEN_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
60#define _major(v) (((v) >> 24) & 0xff)
61#define _minor(v) (((v) >> 16) & 0xff)
62#define _build(v) ((v) & 0xffff)
63
64/* version in image has weird encoding:
65 * 7:0 - major
66 * 15:8 - minor
67 * 31:16 - build (little endian)
68 */
69#define NETXEN_DECODE_VERSION(v) \
70 NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
71
72#define NETXEN_NUM_FLASH_SECTORS (64)
73#define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
74#define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
75 * NETXEN_FLASH_SECTOR_SIZE)
76
77#define RCV_DESC_RINGSIZE(rds_ring) \
78 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
79#define RCV_BUFF_RINGSIZE(rds_ring) \
80 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
81#define STATUS_DESC_RINGSIZE(sds_ring) \
82 (sizeof(struct status_desc) * (sds_ring)->num_desc)
83#define TX_BUFF_RINGSIZE(tx_ring) \
84 (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
85#define TX_DESC_RINGSIZE(tx_ring) \
86 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
87
88#define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
89
90#define NETXEN_RCV_PRODUCER_OFFSET 0
91#define NETXEN_RCV_PEG_DB_ID 2
92#define NETXEN_HOST_DUMMY_DMA_SIZE 1024
93#define FLASH_SUCCESS 0
94
95#define ADDR_IN_WINDOW1(off) \
96 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
97
98#define ADDR_IN_RANGE(addr, low, high) \
99 (((addr) < (high)) && ((addr) >= (low)))
100
101/*
102 * normalize a 64MB crb address to 32MB PCI window
103 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
104 */
105#define NETXEN_CRB_NORMAL(reg) \
106 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
107
108#define NETXEN_CRB_NORMALIZE(adapter, reg) \
109 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
110
111#define DB_NORMALIZE(adapter, off) \
112 (adapter->ahw.db_base + (off))
113
114#define NX_P2_C0 0x24
115#define NX_P2_C1 0x25
116#define NX_P3_A0 0x30
117#define NX_P3_A2 0x30
118#define NX_P3_B0 0x40
119#define NX_P3_B1 0x41
120#define NX_P3_B2 0x42
121#define NX_P3P_A0 0x50
122
123#define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
124#define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
125#define NX_IS_REVISION_P3P(REVISION) (REVISION >= NX_P3P_A0)
126
127#define FIRST_PAGE_GROUP_START 0
128#define FIRST_PAGE_GROUP_END 0x100000
129
130#define SECOND_PAGE_GROUP_START 0x6000000
131#define SECOND_PAGE_GROUP_END 0x68BC000
132
133#define THIRD_PAGE_GROUP_START 0x70E4000
134#define THIRD_PAGE_GROUP_END 0x8000000
135
136#define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
137#define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
138#define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
139
140#define P2_MAX_MTU (8000)
141#define P3_MAX_MTU (9600)
142#define NX_ETHERMTU 1500
143#define NX_MAX_ETHERHDR 32 /* This contains some padding */
144
145#define NX_P2_RX_BUF_MAX_LEN 1760
146#define NX_P3_RX_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
147#define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
148#define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
149#define NX_CT_DEFAULT_RX_BUF_LEN 2048
150#define NX_LRO_BUFFER_EXTRA 2048
151
152#define NX_RX_LRO_BUFFER_LENGTH (8060)
153
154/*
155 * Maximum number of ring contexts
156 */
157#define MAX_RING_CTX 1
158
159/* Opcodes to be used with the commands */
160#define TX_ETHER_PKT 0x01
161#define TX_TCP_PKT 0x02
162#define TX_UDP_PKT 0x03
163#define TX_IP_PKT 0x04
164#define TX_TCP_LSO 0x05
165#define TX_TCP_LSO6 0x06
166#define TX_IPSEC 0x07
167#define TX_IPSEC_CMD 0x0a
168#define TX_TCPV6_PKT 0x0b
169#define TX_UDPV6_PKT 0x0c
170
171/* The following opcodes are for internal consumption. */
172#define NETXEN_CONTROL_OP 0x10
173#define PEGNET_REQUEST 0x11
174
175#define MAX_NUM_CARDS 4
176
177#define NETXEN_MAX_FRAGS_PER_TX 14
178#define MAX_TSO_HEADER_DESC 2
179#define MGMT_CMD_DESC_RESV 4
180#define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
181 + MGMT_CMD_DESC_RESV)
182#define NX_MAX_TX_TIMEOUTS 2
183
184/*
185 * Following are the states of the Phantom. Phantom will set them and
186 * Host will read to check if the fields are correct.
187 */
188#define PHAN_INITIALIZE_START 0xff00
189#define PHAN_INITIALIZE_FAILED 0xffff
190#define PHAN_INITIALIZE_COMPLETE 0xff01
191
192/* Host writes the following to notify that it has done the init-handshake */
193#define PHAN_INITIALIZE_ACK 0xf00f
194
195#define NUM_RCV_DESC_RINGS 3
196#define NUM_STS_DESC_RINGS 4
197
198#define RCV_RING_NORMAL 0
199#define RCV_RING_JUMBO 1
200#define RCV_RING_LRO 2
201
202#define MIN_CMD_DESCRIPTORS 64
203#define MIN_RCV_DESCRIPTORS 64
204#define MIN_JUMBO_DESCRIPTORS 32
205
206#define MAX_CMD_DESCRIPTORS 1024
207#define MAX_RCV_DESCRIPTORS_1G 4096
208#define MAX_RCV_DESCRIPTORS_10G 8192
209#define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
210#define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
211#define MAX_LRO_RCV_DESCRIPTORS 8
212
213#define DEFAULT_RCV_DESCRIPTORS_1G 2048
214#define DEFAULT_RCV_DESCRIPTORS_10G 4096
215
216#define NETXEN_CTX_SIGNATURE 0xdee0
217#define NETXEN_CTX_SIGNATURE_V2 0x0002dee0
218#define NETXEN_CTX_RESET 0xbad0
219#define NETXEN_CTX_D3_RESET 0xacc0
220#define NETXEN_RCV_PRODUCER(ringid) (ringid)
221
222#define PHAN_PEG_RCV_INITIALIZED 0xff01
223#define PHAN_PEG_RCV_START_INITIALIZE 0xff00
224
225#define get_next_index(index, length) \
226 (((index) + 1) & ((length) - 1))
227
228#define get_index_range(index,length,count) \
229 (((index) + (count)) & ((length) - 1))
230
231#define MPORT_SINGLE_FUNCTION_MODE 0x1111
232#define MPORT_MULTI_FUNCTION_MODE 0x2222
233
234#define NX_MAX_PCI_FUNC 8
235
236/*
237 * NetXen host-peg signal message structure
238 *
239 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
240 * Bit 2 : priv_id => must be 1
241 * Bit 3-17 : count => for doorbell
242 * Bit 18-27 : ctx_id => Context id
243 * Bit 28-31 : opcode
244 */
245
246typedef u32 netxen_ctx_msg;
247
248#define netxen_set_msg_peg_id(config_word, val) \
249 ((config_word) &= ~3, (config_word) |= val & 3)
250#define netxen_set_msg_privid(config_word) \
251 ((config_word) |= 1 << 2)
252#define netxen_set_msg_count(config_word, val) \
253 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
254#define netxen_set_msg_ctxid(config_word, val) \
255 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
256#define netxen_set_msg_opcode(config_word, val) \
257 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
258
259struct netxen_rcv_ring {
260 __le64 addr;
261 __le32 size;
262 __le32 rsrvd;
263};
264
265struct netxen_sts_ring {
266 __le64 addr;
267 __le32 size;
268 __le16 msi_index;
269 __le16 rsvd;
270} ;
271
272struct netxen_ring_ctx {
273
274 /* one command ring */
275 __le64 cmd_consumer_offset;
276 __le64 cmd_ring_addr;
277 __le32 cmd_ring_size;
278 __le32 rsrvd;
279
280 /* three receive rings */
281 struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS];
282
283 __le64 sts_ring_addr;
284 __le32 sts_ring_size;
285
286 __le32 ctx_id;
287
288 __le64 rsrvd_2[3];
289 __le32 sts_ring_count;
290 __le32 rsrvd_3;
291 struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS];
292
293} __attribute__ ((aligned(64)));
294
295/*
296 * Following data structures describe the descriptors that will be used.
297 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
298 * we are doing LSO (above the 1500 size packet) only.
299 */
300
301/*
302 * The size of reference handle been changed to 16 bits to pass the MSS fields
303 * for the LSO packet
304 */
305
306#define FLAGS_CHECKSUM_ENABLED 0x01
307#define FLAGS_LSO_ENABLED 0x02
308#define FLAGS_IPSEC_SA_ADD 0x04
309#define FLAGS_IPSEC_SA_DELETE 0x08
310#define FLAGS_VLAN_TAGGED 0x10
311#define FLAGS_VLAN_OOB 0x40
312
313#define netxen_set_tx_vlan_tci(cmd_desc, v) \
314 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
315
316#define netxen_set_cmd_desc_port(cmd_desc, var) \
317 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
318#define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
319 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
320
321#define netxen_set_tx_port(_desc, _port) \
322 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
323
324#define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
325 (_desc)->flags_opcode = \
326 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
327
328#define netxen_set_tx_frags_len(_desc, _frags, _len) \
329 (_desc)->nfrags__length = \
330 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
331
332struct cmd_desc_type0 {
333 u8 tcp_hdr_offset; /* For LSO only */
334 u8 ip_hdr_offset; /* For LSO only */
335 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
336 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
337
338 __le64 addr_buffer2;
339
340 __le16 reference_handle;
341 __le16 mss;
342 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
343 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
344 __le16 conn_id; /* IPSec offoad only */
345
346 __le64 addr_buffer3;
347 __le64 addr_buffer1;
348
349 __le16 buffer_length[4];
350
351 __le64 addr_buffer4;
352
353 __le32 reserved2;
354 __le16 reserved;
355 __le16 vlan_TCI;
356
357} __attribute__ ((aligned(64)));
358
359/* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
360struct rcv_desc {
361 __le16 reference_handle;
362 __le16 reserved;
363 __le32 buffer_length; /* allocated buffer length (usually 2K) */
364 __le64 addr_buffer;
365};
366
367/* opcode field in status_desc */
368#define NETXEN_NIC_SYN_OFFLOAD 0x03
369#define NETXEN_NIC_RXPKT_DESC 0x04
370#define NETXEN_OLD_RXPKT_DESC 0x3f
371#define NETXEN_NIC_RESPONSE_DESC 0x05
372#define NETXEN_NIC_LRO_DESC 0x12
373
374/* for status field in status_desc */
375#define STATUS_NEED_CKSUM (1)
376#define STATUS_CKSUM_OK (2)
377
378/* owner bits of status_desc */
379#define STATUS_OWNER_HOST (0x1ULL << 56)
380#define STATUS_OWNER_PHANTOM (0x2ULL << 56)
381
382/* Status descriptor:
383 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
384 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
385 53-55 desc_cnt, 56-57 owner, 58-63 opcode
386 */
387#define netxen_get_sts_port(sts_data) \
388 ((sts_data) & 0x0F)
389#define netxen_get_sts_status(sts_data) \
390 (((sts_data) >> 4) & 0x0F)
391#define netxen_get_sts_type(sts_data) \
392 (((sts_data) >> 8) & 0x0F)
393#define netxen_get_sts_totallength(sts_data) \
394 (((sts_data) >> 12) & 0xFFFF)
395#define netxen_get_sts_refhandle(sts_data) \
396 (((sts_data) >> 28) & 0xFFFF)
397#define netxen_get_sts_prot(sts_data) \
398 (((sts_data) >> 44) & 0x0F)
399#define netxen_get_sts_pkt_offset(sts_data) \
400 (((sts_data) >> 48) & 0x1F)
401#define netxen_get_sts_desc_cnt(sts_data) \
402 (((sts_data) >> 53) & 0x7)
403#define netxen_get_sts_opcode(sts_data) \
404 (((sts_data) >> 58) & 0x03F)
405
406#define netxen_get_lro_sts_refhandle(sts_data) \
407 ((sts_data) & 0x0FFFF)
408#define netxen_get_lro_sts_length(sts_data) \
409 (((sts_data) >> 16) & 0x0FFFF)
410#define netxen_get_lro_sts_l2_hdr_offset(sts_data) \
411 (((sts_data) >> 32) & 0x0FF)
412#define netxen_get_lro_sts_l4_hdr_offset(sts_data) \
413 (((sts_data) >> 40) & 0x0FF)
414#define netxen_get_lro_sts_timestamp(sts_data) \
415 (((sts_data) >> 48) & 0x1)
416#define netxen_get_lro_sts_type(sts_data) \
417 (((sts_data) >> 49) & 0x7)
418#define netxen_get_lro_sts_push_flag(sts_data) \
419 (((sts_data) >> 52) & 0x1)
420#define netxen_get_lro_sts_seq_number(sts_data) \
421 ((sts_data) & 0x0FFFFFFFF)
422
423
424struct status_desc {
425 __le64 status_desc_data[2];
426} __attribute__ ((aligned(16)));
427
428/* UNIFIED ROMIMAGE *************************/
429#define NX_UNI_DIR_SECT_PRODUCT_TBL 0x0
430#define NX_UNI_DIR_SECT_BOOTLD 0x6
431#define NX_UNI_DIR_SECT_FW 0x7
432
433/*Offsets */
434#define NX_UNI_CHIP_REV_OFF 10
435#define NX_UNI_FLAGS_OFF 11
436#define NX_UNI_BIOS_VERSION_OFF 12
437#define NX_UNI_BOOTLD_IDX_OFF 27
438#define NX_UNI_FIRMWARE_IDX_OFF 29
439
440struct uni_table_desc{
441 uint32_t findex;
442 uint32_t num_entries;
443 uint32_t entry_size;
444 uint32_t reserved[5];
445};
446
447struct uni_data_desc{
448 uint32_t findex;
449 uint32_t size;
450 uint32_t reserved[5];
451};
452
453/* UNIFIED ROMIMAGE *************************/
454
455/* The version of the main data structure */
456#define NETXEN_BDINFO_VERSION 1
457
458/* Magic number to let user know flash is programmed */
459#define NETXEN_BDINFO_MAGIC 0x12345678
460
461/* Max number of Gig ports on a Phantom board */
462#define NETXEN_MAX_PORTS 4
463
464#define NETXEN_BRDTYPE_P1_BD 0x0000
465#define NETXEN_BRDTYPE_P1_SB 0x0001
466#define NETXEN_BRDTYPE_P1_SMAX 0x0002
467#define NETXEN_BRDTYPE_P1_SOCK 0x0003
468
469#define NETXEN_BRDTYPE_P2_SOCK_31 0x0008
470#define NETXEN_BRDTYPE_P2_SOCK_35 0x0009
471#define NETXEN_BRDTYPE_P2_SB35_4G 0x000a
472#define NETXEN_BRDTYPE_P2_SB31_10G 0x000b
473#define NETXEN_BRDTYPE_P2_SB31_2G 0x000c
474
475#define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d
476#define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e
477#define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f
478
479#define NETXEN_BRDTYPE_P3_REF_QG 0x0021
480#define NETXEN_BRDTYPE_P3_HMEZ 0x0022
481#define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023
482#define NETXEN_BRDTYPE_P3_4_GB 0x0024
483#define NETXEN_BRDTYPE_P3_IMEZ 0x0025
484#define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026
485#define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027
486#define NETXEN_BRDTYPE_P3_XG_LOM 0x0028
487#define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029
488#define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a
489#define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b
490#define NETXEN_BRDTYPE_P3_10G_CX4 0x0031
491#define NETXEN_BRDTYPE_P3_10G_XFP 0x0032
492#define NETXEN_BRDTYPE_P3_10G_TP 0x0080
493
494/* Flash memory map */
495#define NETXEN_CRBINIT_START 0 /* crbinit section */
496#define NETXEN_BRDCFG_START 0x4000 /* board config */
497#define NETXEN_INITCODE_START 0x6000 /* pegtune code */
498#define NETXEN_BOOTLD_START 0x10000 /* bootld */
499#define NETXEN_IMAGE_START 0x43000 /* compressed image */
500#define NETXEN_SECONDARY_START 0x200000 /* backup images */
501#define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */
502#define NETXEN_USER_START 0x3E8000 /* Firmare info */
503#define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */
504#define NETXEN_USER_START_OLD NETXEN_PXE_START /* very old flash */
505
506#define NX_OLD_MAC_ADDR_OFFSET (NETXEN_USER_START)
507#define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
508#define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
509#define NX_FW_MAC_ADDR_OFFSET (NETXEN_USER_START+0x418)
510#define NX_FW_SERIAL_NUM_OFFSET (NETXEN_USER_START+0x81c)
511#define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
512
513#define NX_HDR_VERSION_OFFSET (NETXEN_BRDCFG_START)
514#define NX_BRDTYPE_OFFSET (NETXEN_BRDCFG_START+0x8)
515#define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
516
517#define NX_FW_MIN_SIZE (0x3fffff)
518#define NX_P2_MN_ROMIMAGE 0
519#define NX_P3_CT_ROMIMAGE 1
520#define NX_P3_MN_ROMIMAGE 2
521#define NX_UNIFIED_ROMIMAGE 3
522#define NX_FLASH_ROMIMAGE 4
523#define NX_UNKNOWN_ROMIMAGE 0xff
524
525#define NX_P2_MN_ROMIMAGE_NAME "nxromimg.bin"
526#define NX_P3_CT_ROMIMAGE_NAME "nx3fwct.bin"
527#define NX_P3_MN_ROMIMAGE_NAME "nx3fwmn.bin"
528#define NX_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
529#define NX_FLASH_ROMIMAGE_NAME "flash"
530
531extern char netxen_nic_driver_name[];
532
533/* Number of status descriptors to handle per interrupt */
534#define MAX_STATUS_HANDLE (64)
535
536/*
537 * netxen_skb_frag{} is to contain mapping info for each SG list. This
538 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
539 */
540struct netxen_skb_frag {
541 u64 dma;
542 u64 length;
543};
544
545struct netxen_recv_crb {
546 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
547 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
548 u32 sw_int_mask[NUM_STS_DESC_RINGS];
549};
550
551/* Following defines are for the state of the buffers */
552#define NETXEN_BUFFER_FREE 0
553#define NETXEN_BUFFER_BUSY 1
554
555/*
556 * There will be one netxen_buffer per skb packet. These will be
557 * used to save the dma info for pci_unmap_page()
558 */
559struct netxen_cmd_buffer {
560 struct sk_buff *skb;
561 struct netxen_skb_frag frag_array[MAX_SKB_FRAGS + 1];
562 u32 frag_count;
563};
564
565/* In rx_buffer, we do not need multiple fragments as is a single buffer */
566struct netxen_rx_buffer {
567 struct list_head list;
568 struct sk_buff *skb;
569 u64 dma;
570 u16 ref_handle;
571 u16 state;
572};
573
574/* Board types */
575#define NETXEN_NIC_GBE 0x01
576#define NETXEN_NIC_XGBE 0x02
577
578/*
579 * One hardware_context{} per adapter
580 * contains interrupt info as well shared hardware info.
581 */
582struct netxen_hardware_context {
583 void __iomem *pci_base0;
584 void __iomem *pci_base1;
585 void __iomem *pci_base2;
586 void __iomem *db_base;
587 void __iomem *ocm_win_crb;
588
589 unsigned long db_len;
590 unsigned long pci_len0;
591
592 u32 ocm_win;
593 u32 crb_win;
594
595 rwlock_t crb_lock;
596 spinlock_t mem_lock;
597
598 u8 cut_through;
599 u8 revision_id;
600 u8 pci_func;
601 u8 linkup;
602 u16 port_type;
603 u16 board_type;
604};
605
606#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
607#define ETHERNET_FCS_SIZE 4
608
609struct netxen_adapter_stats {
610 u64 xmitcalled;
611 u64 xmitfinished;
612 u64 rxdropped;
613 u64 txdropped;
614 u64 csummed;
615 u64 rx_pkts;
616 u64 lro_pkts;
617 u64 rxbytes;
618 u64 txbytes;
619};
620
621/*
622 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
623 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
624 */
625struct nx_host_rds_ring {
626 u32 producer;
627 u32 num_desc;
628 u32 dma_size;
629 u32 skb_size;
630 u32 flags;
631 void __iomem *crb_rcv_producer;
632 struct rcv_desc *desc_head;
633 struct netxen_rx_buffer *rx_buf_arr;
634 struct list_head free_list;
635 spinlock_t lock;
636 dma_addr_t phys_addr;
637};
638
639struct nx_host_sds_ring {
640 u32 consumer;
641 u32 num_desc;
642 void __iomem *crb_sts_consumer;
643 void __iomem *crb_intr_mask;
644
645 struct status_desc *desc_head;
646 struct netxen_adapter *adapter;
647 struct napi_struct napi;
648 struct list_head free_list[NUM_RCV_DESC_RINGS];
649
650 int irq;
651
652 dma_addr_t phys_addr;
653 char name[IFNAMSIZ+4];
654};
655
656struct nx_host_tx_ring {
657 u32 producer;
658 __le32 *hw_consumer;
659 u32 sw_consumer;
660 void __iomem *crb_cmd_producer;
661 void __iomem *crb_cmd_consumer;
662 u32 num_desc;
663
664 struct netdev_queue *txq;
665
666 struct netxen_cmd_buffer *cmd_buf_arr;
667 struct cmd_desc_type0 *desc_head;
668 dma_addr_t phys_addr;
669};
670
671/*
672 * Receive context. There is one such structure per instance of the
673 * receive processing. Any state information that is relevant to
674 * the receive, and is must be in this structure. The global data may be
675 * present elsewhere.
676 */
677struct netxen_recv_context {
678 u32 state;
679 u16 context_id;
680 u16 virt_port;
681
682 struct nx_host_rds_ring *rds_rings;
683 struct nx_host_sds_ring *sds_rings;
684
685 struct netxen_ring_ctx *hwctx;
686 dma_addr_t phys_addr;
687};
688
689/* New HW context creation */
690
691#define NX_OS_CRB_RETRY_COUNT 4000
692#define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
693 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
694
695#define NX_CDRP_CLEAR 0x00000000
696#define NX_CDRP_CMD_BIT 0x80000000
697
698/*
699 * All responses must have the NX_CDRP_CMD_BIT cleared
700 * in the crb NX_CDRP_CRB_OFFSET.
701 */
702#define NX_CDRP_FORM_RSP(rsp) (rsp)
703#define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
704
705#define NX_CDRP_RSP_OK 0x00000001
706#define NX_CDRP_RSP_FAIL 0x00000002
707#define NX_CDRP_RSP_TIMEOUT 0x00000003
708
709/*
710 * All commands must have the NX_CDRP_CMD_BIT set in
711 * the crb NX_CDRP_CRB_OFFSET.
712 */
713#define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
714#define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
715
716#define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
717#define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
718#define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
719#define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
720#define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
721#define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
722#define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
723#define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
724#define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
725#define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
726#define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
727#define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
728#define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
729#define NX_CDRP_CMD_SET_MTU 0x00000012
730#define NX_CDRP_CMD_READ_PHY 0x00000013
731#define NX_CDRP_CMD_WRITE_PHY 0x00000014
732#define NX_CDRP_CMD_READ_HW_REG 0x00000015
733#define NX_CDRP_CMD_GET_FLOW_CTL 0x00000016
734#define NX_CDRP_CMD_SET_FLOW_CTL 0x00000017
735#define NX_CDRP_CMD_READ_MAX_MTU 0x00000018
736#define NX_CDRP_CMD_READ_MAX_LRO 0x00000019
737#define NX_CDRP_CMD_CONFIGURE_TOE 0x0000001a
738#define NX_CDRP_CMD_FUNC_ATTRIB 0x0000001b
739#define NX_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
740#define NX_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
741#define NX_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
742#define NX_CDRP_CMD_CONFIG_GBE_PORT 0x0000001f
743#define NX_CDRP_CMD_MAX 0x00000020
744
745#define NX_RCODE_SUCCESS 0
746#define NX_RCODE_NO_HOST_MEM 1
747#define NX_RCODE_NO_HOST_RESOURCE 2
748#define NX_RCODE_NO_CARD_CRB 3
749#define NX_RCODE_NO_CARD_MEM 4
750#define NX_RCODE_NO_CARD_RESOURCE 5
751#define NX_RCODE_INVALID_ARGS 6
752#define NX_RCODE_INVALID_ACTION 7
753#define NX_RCODE_INVALID_STATE 8
754#define NX_RCODE_NOT_SUPPORTED 9
755#define NX_RCODE_NOT_PERMITTED 10
756#define NX_RCODE_NOT_READY 11
757#define NX_RCODE_DOES_NOT_EXIST 12
758#define NX_RCODE_ALREADY_EXISTS 13
759#define NX_RCODE_BAD_SIGNATURE 14
760#define NX_RCODE_CMD_NOT_IMPL 15
761#define NX_RCODE_CMD_INVALID 16
762#define NX_RCODE_TIMEOUT 17
763#define NX_RCODE_CMD_FAILED 18
764#define NX_RCODE_MAX_EXCEEDED 19
765#define NX_RCODE_MAX 20
766
767#define NX_DESTROY_CTX_RESET 0
768#define NX_DESTROY_CTX_D3_RESET 1
769#define NX_DESTROY_CTX_MAX 2
770
771/*
772 * Capabilities
773 */
774#define NX_CAP_BIT(class, bit) (1 << bit)
775#define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
776#define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
777#define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
778#define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
779#define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
780#define NX_CAP0_LRO NX_CAP_BIT(0, 5)
781#define NX_CAP0_LSO NX_CAP_BIT(0, 6)
782#define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
783#define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
784#define NX_CAP0_HW_LRO NX_CAP_BIT(0, 10)
785
786/*
787 * Context state
788 */
789#define NX_HOST_CTX_STATE_FREED 0
790#define NX_HOST_CTX_STATE_ALLOCATED 1
791#define NX_HOST_CTX_STATE_ACTIVE 2
792#define NX_HOST_CTX_STATE_DISABLED 3
793#define NX_HOST_CTX_STATE_QUIESCED 4
794#define NX_HOST_CTX_STATE_MAX 5
795
796/*
797 * Rx context
798 */
799
800typedef struct {
801 __le64 host_phys_addr; /* Ring base addr */
802 __le32 ring_size; /* Ring entries */
803 __le16 msi_index;
804 __le16 rsvd; /* Padding */
805} nx_hostrq_sds_ring_t;
806
807typedef struct {
808 __le64 host_phys_addr; /* Ring base addr */
809 __le64 buff_size; /* Packet buffer size */
810 __le32 ring_size; /* Ring entries */
811 __le32 ring_kind; /* Class of ring */
812} nx_hostrq_rds_ring_t;
813
814typedef struct {
815 __le64 host_rsp_dma_addr; /* Response dma'd here */
816 __le32 capabilities[4]; /* Flag bit vector */
817 __le32 host_int_crb_mode; /* Interrupt crb usage */
818 __le32 host_rds_crb_mode; /* RDS crb usage */
819 /* These ring offsets are relative to data[0] below */
820 __le32 rds_ring_offset; /* Offset to RDS config */
821 __le32 sds_ring_offset; /* Offset to SDS config */
822 __le16 num_rds_rings; /* Count of RDS rings */
823 __le16 num_sds_rings; /* Count of SDS rings */
824 __le16 rsvd1; /* Padding */
825 __le16 rsvd2; /* Padding */
826 u8 reserved[128]; /* reserve space for future expansion*/
827 /* MUST BE 64-bit aligned.
828 The following is packed:
829 - N hostrq_rds_rings
830 - N hostrq_sds_rings */
831 char data[0];
832} nx_hostrq_rx_ctx_t;
833
834typedef struct {
835 __le32 host_producer_crb; /* Crb to use */
836 __le32 rsvd1; /* Padding */
837} nx_cardrsp_rds_ring_t;
838
839typedef struct {
840 __le32 host_consumer_crb; /* Crb to use */
841 __le32 interrupt_crb; /* Crb to use */
842} nx_cardrsp_sds_ring_t;
843
844typedef struct {
845 /* These ring offsets are relative to data[0] below */
846 __le32 rds_ring_offset; /* Offset to RDS config */
847 __le32 sds_ring_offset; /* Offset to SDS config */
848 __le32 host_ctx_state; /* Starting State */
849 __le32 num_fn_per_port; /* How many PCI fn share the port */
850 __le16 num_rds_rings; /* Count of RDS rings */
851 __le16 num_sds_rings; /* Count of SDS rings */
852 __le16 context_id; /* Handle for context */
853 u8 phys_port; /* Physical id of port */
854 u8 virt_port; /* Virtual/Logical id of port */
855 u8 reserved[128]; /* save space for future expansion */
856 /* MUST BE 64-bit aligned.
857 The following is packed:
858 - N cardrsp_rds_rings
859 - N cardrs_sds_rings */
860 char data[0];
861} nx_cardrsp_rx_ctx_t;
862
863#define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
864 (sizeof(HOSTRQ_RX) + \
865 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
866 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
867
868#define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
869 (sizeof(CARDRSP_RX) + \
870 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
871 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
872
873/*
874 * Tx context
875 */
876
877typedef struct {
878 __le64 host_phys_addr; /* Ring base addr */
879 __le32 ring_size; /* Ring entries */
880 __le32 rsvd; /* Padding */
881} nx_hostrq_cds_ring_t;
882
883typedef struct {
884 __le64 host_rsp_dma_addr; /* Response dma'd here */
885 __le64 cmd_cons_dma_addr; /* */
886 __le64 dummy_dma_addr; /* */
887 __le32 capabilities[4]; /* Flag bit vector */
888 __le32 host_int_crb_mode; /* Interrupt crb usage */
889 __le32 rsvd1; /* Padding */
890 __le16 rsvd2; /* Padding */
891 __le16 interrupt_ctl;
892 __le16 msi_index;
893 __le16 rsvd3; /* Padding */
894 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
895 u8 reserved[128]; /* future expansion */
896} nx_hostrq_tx_ctx_t;
897
898typedef struct {
899 __le32 host_producer_crb; /* Crb to use */
900 __le32 interrupt_crb; /* Crb to use */
901} nx_cardrsp_cds_ring_t;
902
903typedef struct {
904 __le32 host_ctx_state; /* Starting state */
905 __le16 context_id; /* Handle for context */
906 u8 phys_port; /* Physical id of port */
907 u8 virt_port; /* Virtual/Logical id of port */
908 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
909 u8 reserved[128]; /* future expansion */
910} nx_cardrsp_tx_ctx_t;
911
912#define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
913#define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
914
915/* CRB */
916
917#define NX_HOST_RDS_CRB_MODE_UNIQUE 0
918#define NX_HOST_RDS_CRB_MODE_SHARED 1
919#define NX_HOST_RDS_CRB_MODE_CUSTOM 2
920#define NX_HOST_RDS_CRB_MODE_MAX 3
921
922#define NX_HOST_INT_CRB_MODE_UNIQUE 0
923#define NX_HOST_INT_CRB_MODE_SHARED 1
924#define NX_HOST_INT_CRB_MODE_NORX 2
925#define NX_HOST_INT_CRB_MODE_NOTX 3
926#define NX_HOST_INT_CRB_MODE_NORXTX 4
927
928
929/* MAC */
930
931#define MC_COUNT_P2 16
932#define MC_COUNT_P3 38
933
934#define NETXEN_MAC_NOOP 0
935#define NETXEN_MAC_ADD 1
936#define NETXEN_MAC_DEL 2
937
938typedef struct nx_mac_list_s {
939 struct list_head list;
940 uint8_t mac_addr[ETH_ALEN+2];
941} nx_mac_list_t;
942
943/*
944 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
945 * adjusted based on configured MTU.
946 */
947#define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
948#define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
949#define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
950#define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
951
952#define NETXEN_NIC_INTR_DEFAULT 0x04
953
954typedef union {
955 struct {
956 uint16_t rx_packets;
957 uint16_t rx_time_us;
958 uint16_t tx_packets;
959 uint16_t tx_time_us;
960 } data;
961 uint64_t word;
962} nx_nic_intr_coalesce_data_t;
963
964typedef struct {
965 uint16_t stats_time_us;
966 uint16_t rate_sample_time;
967 uint16_t flags;
968 uint16_t rsvd_1;
969 uint32_t low_threshold;
970 uint32_t high_threshold;
971 nx_nic_intr_coalesce_data_t normal;
972 nx_nic_intr_coalesce_data_t low;
973 nx_nic_intr_coalesce_data_t high;
974 nx_nic_intr_coalesce_data_t irq;
975} nx_nic_intr_coalesce_t;
976
977#define NX_HOST_REQUEST 0x13
978#define NX_NIC_REQUEST 0x14
979
980#define NX_MAC_EVENT 0x1
981
982#define NX_IP_UP 2
983#define NX_IP_DOWN 3
984
985/*
986 * Driver --> Firmware
987 */
988#define NX_NIC_H2C_OPCODE_START 0
989#define NX_NIC_H2C_OPCODE_CONFIG_RSS 1
990#define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2
991#define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
992#define NX_NIC_H2C_OPCODE_CONFIG_LED 4
993#define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
994#define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6
995#define NX_NIC_H2C_OPCODE_LRO_REQUEST 7
996#define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8
997#define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9
998#define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
999#define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11
1000#define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
1001#define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
1002#define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
1003#define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
1004#define NX_NIC_H2C_OPCODE_GET_NET_STATS 16
1005#define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
1006#define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18
1007#define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19
1008#define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20
1009#define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21
1010#define NX_NIC_C2C_OPCODE 22
1011#define NX_NIC_H2C_OPCODE_CONFIG_BRIDGING 23
1012#define NX_NIC_H2C_OPCODE_CONFIG_HW_LRO 24
1013#define NX_NIC_H2C_OPCODE_LAST 25
1014
1015/*
1016 * Firmware --> Driver
1017 */
1018
1019#define NX_NIC_C2H_OPCODE_START 128
1020#define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
1021#define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
1022#define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
1023#define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
1024#define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
1025#define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
1026#define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
1027#define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136
1028#define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
1029#define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
1030#define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
1031#define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
1032#define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
1033#define NX_NIC_C2H_OPCODE_LAST 142
1034
1035#define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
1036#define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
1037#define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1038
1039#define NX_NIC_LRO_REQUEST_FIRST 0
1040#define NX_NIC_LRO_REQUEST_ADD_FLOW 1
1041#define NX_NIC_LRO_REQUEST_DELETE_FLOW 2
1042#define NX_NIC_LRO_REQUEST_TIMER 3
1043#define NX_NIC_LRO_REQUEST_CLEANUP 4
1044#define NX_NIC_LRO_REQUEST_ADD_FLOW_SCHEDULED 5
1045#define NX_TOE_LRO_REQUEST_ADD_FLOW 6
1046#define NX_TOE_LRO_REQUEST_ADD_FLOW_RESPONSE 7
1047#define NX_TOE_LRO_REQUEST_DELETE_FLOW 8
1048#define NX_TOE_LRO_REQUEST_DELETE_FLOW_RESPONSE 9
1049#define NX_TOE_LRO_REQUEST_TIMER 10
1050#define NX_NIC_LRO_REQUEST_LAST 11
1051
1052#define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5)
1053#define NX_FW_CAPABILITY_SWITCHING (1 << 6)
1054#define NX_FW_CAPABILITY_PEXQ (1 << 7)
1055#define NX_FW_CAPABILITY_BDG (1 << 8)
1056#define NX_FW_CAPABILITY_FVLANTX (1 << 9)
1057#define NX_FW_CAPABILITY_HW_LRO (1 << 10)
1058#define NX_FW_CAPABILITY_GBE_LINK_CFG (1 << 11)
1059
1060/* module types */
1061#define LINKEVENT_MODULE_NOT_PRESENT 1
1062#define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
1063#define LINKEVENT_MODULE_OPTICAL_SRLR 3
1064#define LINKEVENT_MODULE_OPTICAL_LRM 4
1065#define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
1066#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
1067#define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
1068#define LINKEVENT_MODULE_TWINAX 8
1069
1070#define LINKSPEED_10GBPS 10000
1071#define LINKSPEED_1GBPS 1000
1072#define LINKSPEED_100MBPS 100
1073#define LINKSPEED_10MBPS 10
1074
1075#define LINKSPEED_ENCODED_10MBPS 0
1076#define LINKSPEED_ENCODED_100MBPS 1
1077#define LINKSPEED_ENCODED_1GBPS 2
1078
1079#define LINKEVENT_AUTONEG_DISABLED 0
1080#define LINKEVENT_AUTONEG_ENABLED 1
1081
1082#define LINKEVENT_HALF_DUPLEX 0
1083#define LINKEVENT_FULL_DUPLEX 1
1084
1085#define LINKEVENT_LINKSPEED_MBPS 0
1086#define LINKEVENT_LINKSPEED_ENCODED 1
1087
1088#define AUTO_FW_RESET_ENABLED 0xEF10AF12
1089#define AUTO_FW_RESET_DISABLED 0xDCBAAF12
1090
1091/* firmware response header:
1092 * 63:58 - message type
1093 * 57:56 - owner
1094 * 55:53 - desc count
1095 * 52:48 - reserved
1096 * 47:40 - completion id
1097 * 39:32 - opcode
1098 * 31:16 - error code
1099 * 15:00 - reserved
1100 */
1101#define netxen_get_nic_msgtype(msg_hdr) \
1102 ((msg_hdr >> 58) & 0x3F)
1103#define netxen_get_nic_msg_compid(msg_hdr) \
1104 ((msg_hdr >> 40) & 0xFF)
1105#define netxen_get_nic_msg_opcode(msg_hdr) \
1106 ((msg_hdr >> 32) & 0xFF)
1107#define netxen_get_nic_msg_errcode(msg_hdr) \
1108 ((msg_hdr >> 16) & 0xFFFF)
1109
1110typedef struct {
1111 union {
1112 struct {
1113 u64 hdr;
1114 u64 body[7];
1115 };
1116 u64 words[8];
1117 };
1118} nx_fw_msg_t;
1119
1120typedef struct {
1121 __le64 qhdr;
1122 __le64 req_hdr;
1123 __le64 words[6];
1124} nx_nic_req_t;
1125
1126typedef struct {
1127 u8 op;
1128 u8 tag;
1129 u8 mac_addr[6];
1130} nx_mac_req_t;
1131
1132#define MAX_PENDING_DESC_BLOCK_SIZE 64
1133
1134#define NETXEN_NIC_MSI_ENABLED 0x02
1135#define NETXEN_NIC_MSIX_ENABLED 0x04
1136#define NETXEN_NIC_LRO_ENABLED 0x08
1137#define NETXEN_NIC_LRO_DISABLED 0x00
1138#define NETXEN_NIC_BRIDGE_ENABLED 0X10
1139#define NETXEN_NIC_DIAG_ENABLED 0x20
1140#define NETXEN_IS_MSI_FAMILY(adapter) \
1141 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1142
1143#define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
1144#define NETXEN_MSIX_TBL_SPACE 8192
1145#define NETXEN_PCI_REG_MSIX_TBL 0x44
1146
1147#define NETXEN_DB_MAPSIZE_BYTES 0x1000
1148
1149#define NETXEN_NETDEV_WEIGHT 128
1150#define NETXEN_ADAPTER_UP_MAGIC 777
1151#define NETXEN_NIC_PEG_TUNE 0
1152
1153#define __NX_FW_ATTACHED 0
1154#define __NX_DEV_UP 1
1155#define __NX_RESETTING 2
1156
1157struct netxen_dummy_dma {
1158 void *addr;
1159 dma_addr_t phys_addr;
1160};
1161
1162struct netxen_adapter {
1163 struct netxen_hardware_context ahw;
1164
1165 struct net_device *netdev;
1166 struct pci_dev *pdev;
1167 struct list_head mac_list;
1168
1169 spinlock_t tx_clean_lock;
1170
1171 u16 num_txd;
1172 u16 num_rxd;
1173 u16 num_jumbo_rxd;
1174 u16 num_lro_rxd;
1175
1176 u8 max_rds_rings;
1177 u8 max_sds_rings;
1178 u8 driver_mismatch;
1179 u8 msix_supported;
1180 u8 __pad;
1181 u8 pci_using_dac;
1182 u8 portnum;
1183 u8 physical_port;
1184
1185 u8 mc_enabled;
1186 u8 max_mc_count;
1187 u8 rss_supported;
1188 u8 link_changed;
1189 u8 fw_wait_cnt;
1190 u8 fw_fail_cnt;
1191 u8 tx_timeo_cnt;
1192 u8 need_fw_reset;
1193
1194 u8 has_link_events;
1195 u8 fw_type;
1196 u16 tx_context_id;
1197 u16 mtu;
1198 u16 is_up;
1199
1200 u16 link_speed;
1201 u16 link_duplex;
1202 u16 link_autoneg;
1203 u16 module_type;
1204
1205 u32 capabilities;
1206 u32 flags;
1207 u32 irq;
1208 u32 temp;
1209
1210 u32 int_vec_bit;
1211 u32 heartbit;
1212
1213 u8 mac_addr[ETH_ALEN];
1214
1215 struct netxen_adapter_stats stats;
1216
1217 struct netxen_recv_context recv_ctx;
1218 struct nx_host_tx_ring *tx_ring;
1219
1220 int (*macaddr_set) (struct netxen_adapter *, u8 *);
1221 int (*set_mtu) (struct netxen_adapter *, int);
1222 int (*set_promisc) (struct netxen_adapter *, u32);
1223 void (*set_multi) (struct net_device *);
1224 int (*phy_read) (struct netxen_adapter *, u32 reg, u32 *);
1225 int (*phy_write) (struct netxen_adapter *, u32 reg, u32 val);
1226 int (*init_port) (struct netxen_adapter *, int);
1227 int (*stop_port) (struct netxen_adapter *);
1228
1229 u32 (*crb_read)(struct netxen_adapter *, ulong);
1230 int (*crb_write)(struct netxen_adapter *, ulong, u32);
1231
1232 int (*pci_mem_read)(struct netxen_adapter *, u64, u64 *);
1233 int (*pci_mem_write)(struct netxen_adapter *, u64, u64);
1234
1235 int (*pci_set_window)(struct netxen_adapter *, u64, u32 *);
1236
1237 u32 (*io_read)(struct netxen_adapter *, void __iomem *);
1238 void (*io_write)(struct netxen_adapter *, void __iomem *, u32);
1239
1240 void __iomem *tgt_mask_reg;
1241 void __iomem *pci_int_reg;
1242 void __iomem *tgt_status_reg;
1243 void __iomem *crb_int_state_reg;
1244 void __iomem *isr_int_vec;
1245
1246 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1247
1248 struct netxen_dummy_dma dummy_dma;
1249
1250 struct delayed_work fw_work;
1251
1252 struct work_struct tx_timeout_task;
1253
1254 nx_nic_intr_coalesce_t coal;
1255
1256 unsigned long state;
1257 __le32 file_prd_off; /*File fw product offset*/
1258 u32 fw_version;
1259 const struct firmware *fw;
1260};
1261
1262int nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val);
1263int nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val);
1264
1265#define NXRD32(adapter, off) \
1266 (adapter->crb_read(adapter, off))
1267#define NXWR32(adapter, off, val) \
1268 (adapter->crb_write(adapter, off, val))
1269#define NXRDIO(adapter, addr) \
1270 (adapter->io_read(adapter, addr))
1271#define NXWRIO(adapter, addr, val) \
1272 (adapter->io_write(adapter, addr, val))
1273
1274int netxen_pcie_sem_lock(struct netxen_adapter *, int, u32);
1275void netxen_pcie_sem_unlock(struct netxen_adapter *, int);
1276
1277#define netxen_rom_lock(a) \
1278 netxen_pcie_sem_lock((a), 2, NETXEN_ROM_LOCK_ID)
1279#define netxen_rom_unlock(a) \
1280 netxen_pcie_sem_unlock((a), 2)
1281#define netxen_phy_lock(a) \
1282 netxen_pcie_sem_lock((a), 3, NETXEN_PHY_LOCK_ID)
1283#define netxen_phy_unlock(a) \
1284 netxen_pcie_sem_unlock((a), 3)
1285#define netxen_api_lock(a) \
1286 netxen_pcie_sem_lock((a), 5, 0)
1287#define netxen_api_unlock(a) \
1288 netxen_pcie_sem_unlock((a), 5)
1289#define netxen_sw_lock(a) \
1290 netxen_pcie_sem_lock((a), 6, 0)
1291#define netxen_sw_unlock(a) \
1292 netxen_pcie_sem_unlock((a), 6)
1293#define crb_win_lock(a) \
1294 netxen_pcie_sem_lock((a), 7, NETXEN_CRB_WIN_LOCK_ID)
1295#define crb_win_unlock(a) \
1296 netxen_pcie_sem_unlock((a), 7)
1297
1298int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1299int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1300
1301/* Functions from netxen_nic_init.c */
1302int netxen_init_dummy_dma(struct netxen_adapter *adapter);
1303void netxen_free_dummy_dma(struct netxen_adapter *adapter);
1304
1305int netxen_check_flash_fw_compatibility(struct netxen_adapter *adapter);
1306int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1307int netxen_load_firmware(struct netxen_adapter *adapter);
1308int netxen_need_fw_reset(struct netxen_adapter *adapter);
1309void netxen_request_firmware(struct netxen_adapter *adapter);
1310void netxen_release_firmware(struct netxen_adapter *adapter);
1311int netxen_pinit_from_rom(struct netxen_adapter *adapter);
1312
1313int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1314int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1315 u8 *bytes, size_t size);
1316int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1317 u8 *bytes, size_t size);
1318int netxen_flash_unlock(struct netxen_adapter *adapter);
1319int netxen_backup_crbinit(struct netxen_adapter *adapter);
1320int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1321int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1322void netxen_halt_pegs(struct netxen_adapter *adapter);
1323
1324int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1325
1326int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1327void netxen_free_sw_resources(struct netxen_adapter *adapter);
1328
1329void netxen_setup_hwops(struct netxen_adapter *adapter);
1330void __iomem *netxen_get_ioaddr(struct netxen_adapter *, u32);
1331
1332int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1333void netxen_free_hw_resources(struct netxen_adapter *adapter);
1334
1335void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1336void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1337
1338int netxen_init_firmware(struct netxen_adapter *adapter);
1339void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1340void netxen_watchdog_task(struct work_struct *work);
1341void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1342 struct nx_host_rds_ring *rds_ring);
1343int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1344int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1345
1346void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1347int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1348int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1349int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd);
1350int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
1351void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
1352void netxen_pci_camqm_read_2M(struct netxen_adapter *, u64, u64 *);
1353void netxen_pci_camqm_write_2M(struct netxen_adapter *, u64, u64);
1354
1355int nx_fw_cmd_set_gbe_port(struct netxen_adapter *adapter,
1356 u32 speed, u32 duplex, u32 autoneg);
1357int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1358int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1359int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable);
1360int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable);
1361int netxen_send_lro_cleanup(struct netxen_adapter *adapter);
1362
1363void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1364 struct nx_host_tx_ring *tx_ring);
1365
1366/* Functions from netxen_nic_main.c */
1367int netxen_nic_reset_context(struct netxen_adapter *);
1368
1369/*
1370 * NetXen Board information
1371 */
1372
1373#define NETXEN_MAX_SHORT_NAME 32
1374struct netxen_brdinfo {
1375 int brdtype; /* type of board */
1376 long ports; /* max no of physical ports */
1377 char short_name[NETXEN_MAX_SHORT_NAME];
1378};
1379
1380static const struct netxen_brdinfo netxen_boards[] = {
1381 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1382 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1383 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1384 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1385 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1386 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1387 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1388 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1389 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1390 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1391 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1392 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1393 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1394 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1395 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1396 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1397 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1398 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1399 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1400};
1401
1402#define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1403
1404static inline void get_brd_name_by_type(u32 type, char *name)
1405{
1406 int i, found = 0;
1407 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1408 if (netxen_boards[i].brdtype == type) {
1409 strcpy(name, netxen_boards[i].short_name);
1410 found = 1;
1411 break;
1412 }
1413
1414 }
1415 if (!found)
1416 name = "Unknown";
1417}
1418
1419static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring)
1420{
1421 smp_mb();
1422 return find_diff_among(tx_ring->producer,
1423 tx_ring->sw_consumer, tx_ring->num_desc);
1424
1425}
1426
1427int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac);
1428int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac);
1429extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1430extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1431 int *valp);
1432
1433extern const struct ethtool_ops netxen_nic_ethtool_ops;
1434
1435#endif /* __NETXEN_NIC_H_ */