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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
3
4#ifndef _IONIC_DEV_H_
5#define _IONIC_DEV_H_
6
7#include <linux/atomic.h>
8#include <linux/mutex.h>
9#include <linux/workqueue.h>
10#include <linux/skbuff.h>
11
12#include "ionic_if.h"
13#include "ionic_regs.h"
14
15#define IONIC_MAX_TX_DESC 8192
16#define IONIC_MAX_RX_DESC 16384
17#define IONIC_MIN_TXRX_DESC 64
18#define IONIC_DEF_TXRX_DESC 4096
19#define IONIC_RX_FILL_THRESHOLD 16
20#define IONIC_RX_FILL_DIV 8
21#define IONIC_LIFS_MAX 1024
22#define IONIC_WATCHDOG_SECS 5
23#define IONIC_ITR_COAL_USEC_DEFAULT 64
24
25#define IONIC_DEV_CMD_REG_VERSION 1
26#define IONIC_DEV_INFO_REG_COUNT 32
27#define IONIC_DEV_CMD_REG_COUNT 32
28
29#define IONIC_NAPI_DEADLINE (HZ / 200) /* 5ms */
30#define IONIC_ADMIN_DOORBELL_DEADLINE (HZ / 2) /* 500ms */
31#define IONIC_TX_DOORBELL_DEADLINE (HZ / 100) /* 10ms */
32#define IONIC_RX_MIN_DOORBELL_DEADLINE (HZ / 100) /* 10ms */
33#define IONIC_RX_MAX_DOORBELL_DEADLINE (HZ * 5) /* 5s */
34
35struct ionic_dev_bar {
36 void __iomem *vaddr;
37 phys_addr_t bus_addr;
38 unsigned long len;
39 int res_index;
40};
41
42#ifndef __CHECKER__
43/* Registers */
44static_assert(sizeof(struct ionic_intr) == 32);
45
46static_assert(sizeof(struct ionic_doorbell) == 8);
47static_assert(sizeof(struct ionic_intr_status) == 8);
48static_assert(sizeof(union ionic_dev_regs) == 4096);
49static_assert(sizeof(union ionic_dev_info_regs) == 2048);
50static_assert(sizeof(union ionic_dev_cmd_regs) == 2048);
51static_assert(sizeof(struct ionic_lif_stats) == 1024);
52
53static_assert(sizeof(struct ionic_admin_cmd) == 64);
54static_assert(sizeof(struct ionic_admin_comp) == 16);
55static_assert(sizeof(struct ionic_nop_cmd) == 64);
56static_assert(sizeof(struct ionic_nop_comp) == 16);
57
58/* Device commands */
59static_assert(sizeof(struct ionic_dev_identify_cmd) == 64);
60static_assert(sizeof(struct ionic_dev_identify_comp) == 16);
61static_assert(sizeof(struct ionic_dev_init_cmd) == 64);
62static_assert(sizeof(struct ionic_dev_init_comp) == 16);
63static_assert(sizeof(struct ionic_dev_reset_cmd) == 64);
64static_assert(sizeof(struct ionic_dev_reset_comp) == 16);
65static_assert(sizeof(struct ionic_dev_getattr_cmd) == 64);
66static_assert(sizeof(struct ionic_dev_getattr_comp) == 16);
67static_assert(sizeof(struct ionic_dev_setattr_cmd) == 64);
68static_assert(sizeof(struct ionic_dev_setattr_comp) == 16);
69static_assert(sizeof(struct ionic_lif_setphc_cmd) == 64);
70
71/* Port commands */
72static_assert(sizeof(struct ionic_port_identify_cmd) == 64);
73static_assert(sizeof(struct ionic_port_identify_comp) == 16);
74static_assert(sizeof(struct ionic_port_init_cmd) == 64);
75static_assert(sizeof(struct ionic_port_init_comp) == 16);
76static_assert(sizeof(struct ionic_port_reset_cmd) == 64);
77static_assert(sizeof(struct ionic_port_reset_comp) == 16);
78static_assert(sizeof(struct ionic_port_getattr_cmd) == 64);
79static_assert(sizeof(struct ionic_port_getattr_comp) == 16);
80static_assert(sizeof(struct ionic_port_setattr_cmd) == 64);
81static_assert(sizeof(struct ionic_port_setattr_comp) == 16);
82
83/* LIF commands */
84static_assert(sizeof(struct ionic_lif_init_cmd) == 64);
85static_assert(sizeof(struct ionic_lif_init_comp) == 16);
86static_assert(sizeof(struct ionic_lif_reset_cmd) == 64);
87static_assert(sizeof(ionic_lif_reset_comp) == 16);
88static_assert(sizeof(struct ionic_lif_getattr_cmd) == 64);
89static_assert(sizeof(struct ionic_lif_getattr_comp) == 16);
90static_assert(sizeof(struct ionic_lif_setattr_cmd) == 64);
91static_assert(sizeof(struct ionic_lif_setattr_comp) == 16);
92
93static_assert(sizeof(struct ionic_q_init_cmd) == 64);
94static_assert(sizeof(struct ionic_q_init_comp) == 16);
95static_assert(sizeof(struct ionic_q_control_cmd) == 64);
96static_assert(sizeof(ionic_q_control_comp) == 16);
97static_assert(sizeof(struct ionic_q_identify_cmd) == 64);
98static_assert(sizeof(struct ionic_q_identify_comp) == 16);
99
100static_assert(sizeof(struct ionic_rx_mode_set_cmd) == 64);
101static_assert(sizeof(ionic_rx_mode_set_comp) == 16);
102static_assert(sizeof(struct ionic_rx_filter_add_cmd) == 64);
103static_assert(sizeof(struct ionic_rx_filter_add_comp) == 16);
104static_assert(sizeof(struct ionic_rx_filter_del_cmd) == 64);
105static_assert(sizeof(ionic_rx_filter_del_comp) == 16);
106
107/* RDMA commands */
108static_assert(sizeof(struct ionic_rdma_reset_cmd) == 64);
109static_assert(sizeof(struct ionic_rdma_queue_cmd) == 64);
110
111/* Events */
112static_assert(sizeof(struct ionic_notifyq_cmd) == 4);
113static_assert(sizeof(union ionic_notifyq_comp) == 64);
114static_assert(sizeof(struct ionic_notifyq_event) == 64);
115static_assert(sizeof(struct ionic_link_change_event) == 64);
116static_assert(sizeof(struct ionic_reset_event) == 64);
117static_assert(sizeof(struct ionic_heartbeat_event) == 64);
118static_assert(sizeof(struct ionic_log_event) == 64);
119
120/* I/O */
121static_assert(sizeof(struct ionic_txq_desc) == 16);
122static_assert(sizeof(struct ionic_txq_sg_desc) == 128);
123static_assert(sizeof(struct ionic_txq_comp) == 16);
124
125static_assert(sizeof(struct ionic_rxq_desc) == 16);
126static_assert(sizeof(struct ionic_rxq_sg_desc) == 128);
127static_assert(sizeof(struct ionic_rxq_comp) == 16);
128
129/* SR/IOV */
130static_assert(sizeof(struct ionic_vf_setattr_cmd) == 64);
131static_assert(sizeof(struct ionic_vf_setattr_comp) == 16);
132static_assert(sizeof(struct ionic_vf_getattr_cmd) == 64);
133static_assert(sizeof(struct ionic_vf_getattr_comp) == 16);
134static_assert(sizeof(struct ionic_vf_ctrl_cmd) == 64);
135static_assert(sizeof(struct ionic_vf_ctrl_comp) == 16);
136#endif /* __CHECKER__ */
137
138struct ionic_devinfo {
139 u8 asic_type;
140 u8 asic_rev;
141 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN + 1];
142 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN + 1];
143};
144
145struct ionic_dev {
146 union ionic_dev_info_regs __iomem *dev_info_regs;
147 union ionic_dev_cmd_regs __iomem *dev_cmd_regs;
148 struct ionic_hwstamp_regs __iomem *hwstamp_regs;
149
150 atomic_long_t last_check_time;
151 unsigned long last_hb_time;
152 u32 last_fw_hb;
153 bool fw_hb_ready;
154 bool fw_status_ready;
155 u8 fw_generation;
156 u8 opcode;
157
158 u64 __iomem *db_pages;
159 dma_addr_t phy_db_pages;
160
161 struct ionic_intr __iomem *intr_ctrl;
162 u64 __iomem *intr_status;
163
164 struct mutex cmb_inuse_lock; /* for cmb_inuse */
165 unsigned long *cmb_inuse;
166 dma_addr_t phy_cmb_pages;
167 u32 cmb_npages;
168
169 u32 port_info_sz;
170 struct ionic_port_info *port_info;
171 dma_addr_t port_info_pa;
172
173 struct ionic_devinfo dev_info;
174};
175
176struct ionic_cq_info {
177 union {
178 void *cq_desc;
179 struct ionic_admin_comp *admincq;
180 struct ionic_notifyq_event *notifyq;
181 };
182};
183
184struct ionic_queue;
185struct ionic_qcq;
186struct ionic_desc_info;
187
188typedef void (*ionic_desc_cb)(struct ionic_queue *q,
189 struct ionic_desc_info *desc_info,
190 struct ionic_cq_info *cq_info, void *cb_arg);
191
192#define IONIC_MAX_BUF_LEN ((u16)-1)
193#define IONIC_PAGE_SIZE PAGE_SIZE
194#define IONIC_PAGE_SPLIT_SZ (PAGE_SIZE / 2)
195#define IONIC_PAGE_GFP_MASK (GFP_ATOMIC | __GFP_NOWARN |\
196 __GFP_COMP | __GFP_MEMALLOC)
197
198struct ionic_buf_info {
199 struct page *page;
200 dma_addr_t dma_addr;
201 u32 page_offset;
202 u32 len;
203};
204
205#define IONIC_MAX_FRAGS (1 + IONIC_TX_MAX_SG_ELEMS_V1)
206
207struct ionic_desc_info {
208 union {
209 void *desc;
210 struct ionic_txq_desc *txq_desc;
211 struct ionic_rxq_desc *rxq_desc;
212 struct ionic_admin_cmd *adminq_desc;
213 };
214 void __iomem *cmb_desc;
215 union {
216 void *sg_desc;
217 struct ionic_txq_sg_desc *txq_sg_desc;
218 struct ionic_rxq_sg_desc *rxq_sgl_desc;
219 };
220 unsigned int bytes;
221 unsigned int nbufs;
222 struct ionic_buf_info bufs[MAX_SKB_FRAGS + 1];
223 ionic_desc_cb cb;
224 void *cb_arg;
225};
226
227#define IONIC_QUEUE_NAME_MAX_SZ 16
228
229struct ionic_queue {
230 struct device *dev;
231 struct ionic_lif *lif;
232 struct ionic_desc_info *info;
233 u64 dbval;
234 unsigned long dbell_deadline;
235 unsigned long dbell_jiffies;
236 u16 head_idx;
237 u16 tail_idx;
238 unsigned int index;
239 unsigned int num_descs;
240 unsigned int max_sg_elems;
241 u64 features;
242 u64 drop;
243 struct ionic_dev *idev;
244 unsigned int type;
245 unsigned int hw_index;
246 unsigned int hw_type;
247 union {
248 void *base;
249 struct ionic_txq_desc *txq;
250 struct ionic_rxq_desc *rxq;
251 struct ionic_admin_cmd *adminq;
252 };
253 void __iomem *cmb_base;
254 union {
255 void *sg_base;
256 struct ionic_txq_sg_desc *txq_sgl;
257 struct ionic_rxq_sg_desc *rxq_sgl;
258 };
259 dma_addr_t base_pa;
260 dma_addr_t cmb_base_pa;
261 dma_addr_t sg_base_pa;
262 unsigned int desc_size;
263 unsigned int sg_desc_size;
264 unsigned int pid;
265 char name[IONIC_QUEUE_NAME_MAX_SZ];
266} ____cacheline_aligned_in_smp;
267
268#define IONIC_INTR_INDEX_NOT_ASSIGNED -1
269#define IONIC_INTR_NAME_MAX_SZ 32
270
271struct ionic_intr_info {
272 char name[IONIC_INTR_NAME_MAX_SZ];
273 u64 rearm_count;
274 unsigned int index;
275 unsigned int vector;
276 unsigned int cpu;
277 u32 dim_coal_hw;
278 cpumask_t affinity_mask;
279};
280
281struct ionic_cq {
282 struct ionic_lif *lif;
283 struct ionic_cq_info *info;
284 struct ionic_queue *bound_q;
285 struct ionic_intr_info *bound_intr;
286 u16 tail_idx;
287 bool done_color;
288 unsigned int num_descs;
289 unsigned int desc_size;
290 void *base;
291 dma_addr_t base_pa;
292} ____cacheline_aligned_in_smp;
293
294struct ionic;
295
296static inline void ionic_intr_init(struct ionic_dev *idev,
297 struct ionic_intr_info *intr,
298 unsigned long index)
299{
300 ionic_intr_clean(idev->intr_ctrl, index);
301 intr->index = index;
302}
303
304static inline unsigned int ionic_q_space_avail(struct ionic_queue *q)
305{
306 unsigned int avail = q->tail_idx;
307
308 if (q->head_idx >= avail)
309 avail += q->num_descs - q->head_idx - 1;
310 else
311 avail -= q->head_idx + 1;
312
313 return avail;
314}
315
316static inline bool ionic_q_has_space(struct ionic_queue *q, unsigned int want)
317{
318 return ionic_q_space_avail(q) >= want;
319}
320
321void ionic_init_devinfo(struct ionic *ionic);
322int ionic_dev_setup(struct ionic *ionic);
323void ionic_dev_teardown(struct ionic *ionic);
324
325void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd);
326u8 ionic_dev_cmd_status(struct ionic_dev *idev);
327bool ionic_dev_cmd_done(struct ionic_dev *idev);
328void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp);
329
330void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver);
331void ionic_dev_cmd_init(struct ionic_dev *idev);
332void ionic_dev_cmd_reset(struct ionic_dev *idev);
333
334void ionic_dev_cmd_port_identify(struct ionic_dev *idev);
335void ionic_dev_cmd_port_init(struct ionic_dev *idev);
336void ionic_dev_cmd_port_reset(struct ionic_dev *idev);
337void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state);
338void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed);
339void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable);
340void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type);
341void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type);
342
343int ionic_set_vf_config(struct ionic *ionic, int vf,
344 struct ionic_vf_setattr_cmd *vfc);
345
346void ionic_dev_cmd_queue_identify(struct ionic_dev *idev,
347 u16 lif_type, u8 qtype, u8 qver);
348void ionic_vf_start(struct ionic *ionic);
349void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver);
350void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index,
351 dma_addr_t addr);
352void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index);
353void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq,
354 u16 lif_index, u16 intr_index);
355
356int ionic_db_page_num(struct ionic_lif *lif, int pid);
357
358int ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr, int order);
359void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order);
360
361int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,
362 struct ionic_intr_info *intr,
363 unsigned int num_descs, size_t desc_size);
364void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa);
365void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q);
366typedef bool (*ionic_cq_cb)(struct ionic_cq *cq, struct ionic_cq_info *cq_info);
367typedef void (*ionic_cq_done_cb)(void *done_arg);
368unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do,
369 ionic_cq_cb cb, ionic_cq_done_cb done_cb,
370 void *done_arg);
371
372int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
373 struct ionic_queue *q, unsigned int index, const char *name,
374 unsigned int num_descs, size_t desc_size,
375 size_t sg_desc_size, unsigned int pid);
376void ionic_q_map(struct ionic_queue *q, void *base, dma_addr_t base_pa);
377void ionic_q_cmb_map(struct ionic_queue *q, void __iomem *base, dma_addr_t base_pa);
378void ionic_q_sg_map(struct ionic_queue *q, void *base, dma_addr_t base_pa);
379void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, ionic_desc_cb cb,
380 void *cb_arg);
381void ionic_q_service(struct ionic_queue *q, struct ionic_cq_info *cq_info,
382 unsigned int stop_index);
383int ionic_heartbeat_check(struct ionic *ionic);
384bool ionic_is_fw_running(struct ionic_dev *idev);
385
386bool ionic_adminq_poke_doorbell(struct ionic_queue *q);
387bool ionic_txq_poke_doorbell(struct ionic_queue *q);
388bool ionic_rxq_poke_doorbell(struct ionic_queue *q);
389
390#endif /* _IONIC_DEV_H_ */