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1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/debugfs.h>
22#include <linux/seq_file.h>
23#include <linux/interrupt.h>
24#include <linux/delay.h>
25#include <linux/dma-mapping.h>
26#include <linux/platform_device.h>
27#include <linux/workqueue.h>
28#include <linux/timer.h>
29#include <linux/clk.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/core.h>
32#include <linux/mmc/mmc.h>
33#include <linux/io.h>
34#include <linux/semaphore.h>
35#include <linux/gpio.h>
36#include <linux/regulator/consumer.h>
37#include <linux/pm_runtime.h>
38#include <plat/dma.h>
39#include <mach/hardware.h>
40#include <plat/board.h>
41#include <plat/mmc.h>
42#include <plat/cpu.h>
43
44/* OMAP HSMMC Host Controller Registers */
45#define OMAP_HSMMC_SYSCONFIG 0x0010
46#define OMAP_HSMMC_SYSSTATUS 0x0014
47#define OMAP_HSMMC_CON 0x002C
48#define OMAP_HSMMC_BLK 0x0104
49#define OMAP_HSMMC_ARG 0x0108
50#define OMAP_HSMMC_CMD 0x010C
51#define OMAP_HSMMC_RSP10 0x0110
52#define OMAP_HSMMC_RSP32 0x0114
53#define OMAP_HSMMC_RSP54 0x0118
54#define OMAP_HSMMC_RSP76 0x011C
55#define OMAP_HSMMC_DATA 0x0120
56#define OMAP_HSMMC_HCTL 0x0128
57#define OMAP_HSMMC_SYSCTL 0x012C
58#define OMAP_HSMMC_STAT 0x0130
59#define OMAP_HSMMC_IE 0x0134
60#define OMAP_HSMMC_ISE 0x0138
61#define OMAP_HSMMC_CAPA 0x0140
62
63#define VS18 (1 << 26)
64#define VS30 (1 << 25)
65#define SDVS18 (0x5 << 9)
66#define SDVS30 (0x6 << 9)
67#define SDVS33 (0x7 << 9)
68#define SDVS_MASK 0x00000E00
69#define SDVSCLR 0xFFFFF1FF
70#define SDVSDET 0x00000400
71#define AUTOIDLE 0x1
72#define SDBP (1 << 8)
73#define DTO 0xe
74#define ICE 0x1
75#define ICS 0x2
76#define CEN (1 << 2)
77#define CLKD_MASK 0x0000FFC0
78#define CLKD_SHIFT 6
79#define DTO_MASK 0x000F0000
80#define DTO_SHIFT 16
81#define INT_EN_MASK 0x307F0033
82#define BWR_ENABLE (1 << 4)
83#define BRR_ENABLE (1 << 5)
84#define DTO_ENABLE (1 << 20)
85#define INIT_STREAM (1 << 1)
86#define DP_SELECT (1 << 21)
87#define DDIR (1 << 4)
88#define DMA_EN 0x1
89#define MSBS (1 << 5)
90#define BCE (1 << 1)
91#define FOUR_BIT (1 << 1)
92#define DW8 (1 << 5)
93#define CC 0x1
94#define TC 0x02
95#define OD 0x1
96#define ERR (1 << 15)
97#define CMD_TIMEOUT (1 << 16)
98#define DATA_TIMEOUT (1 << 20)
99#define CMD_CRC (1 << 17)
100#define DATA_CRC (1 << 21)
101#define CARD_ERR (1 << 28)
102#define STAT_CLEAR 0xFFFFFFFF
103#define INIT_STREAM_CMD 0x00000000
104#define DUAL_VOLT_OCR_BIT 7
105#define SRC (1 << 25)
106#define SRD (1 << 26)
107#define SOFTRESET (1 << 1)
108#define RESETDONE (1 << 0)
109
110/*
111 * FIXME: Most likely all the data using these _DEVID defines should come
112 * from the platform_data, or implemented in controller and slot specific
113 * functions.
114 */
115#define OMAP_MMC1_DEVID 0
116#define OMAP_MMC2_DEVID 1
117#define OMAP_MMC3_DEVID 2
118#define OMAP_MMC4_DEVID 3
119#define OMAP_MMC5_DEVID 4
120
121#define MMC_AUTOSUSPEND_DELAY 100
122#define MMC_TIMEOUT_MS 20
123#define OMAP_MMC_MASTER_CLOCK 96000000
124#define OMAP_MMC_MIN_CLOCK 400000
125#define OMAP_MMC_MAX_CLOCK 52000000
126#define DRIVER_NAME "omap_hsmmc"
127
128/*
129 * One controller can have multiple slots, like on some omap boards using
130 * omap.c controller driver. Luckily this is not currently done on any known
131 * omap_hsmmc.c device.
132 */
133#define mmc_slot(host) (host->pdata->slots[host->slot_id])
134
135/*
136 * MMC Host controller read/write API's
137 */
138#define OMAP_HSMMC_READ(base, reg) \
139 __raw_readl((base) + OMAP_HSMMC_##reg)
140
141#define OMAP_HSMMC_WRITE(base, reg, val) \
142 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
143
144struct omap_hsmmc_next {
145 unsigned int dma_len;
146 s32 cookie;
147};
148
149struct omap_hsmmc_host {
150 struct device *dev;
151 struct mmc_host *mmc;
152 struct mmc_request *mrq;
153 struct mmc_command *cmd;
154 struct mmc_data *data;
155 struct clk *fclk;
156 struct clk *dbclk;
157 /*
158 * vcc == configured supply
159 * vcc_aux == optional
160 * - MMC1, supply for DAT4..DAT7
161 * - MMC2/MMC2, external level shifter voltage supply, for
162 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
163 */
164 struct regulator *vcc;
165 struct regulator *vcc_aux;
166 struct work_struct mmc_carddetect_work;
167 void __iomem *base;
168 resource_size_t mapbase;
169 spinlock_t irq_lock; /* Prevent races with irq handler */
170 unsigned int id;
171 unsigned int dma_len;
172 unsigned int dma_sg_idx;
173 unsigned char bus_mode;
174 unsigned char power_mode;
175 u32 *buffer;
176 u32 bytesleft;
177 int suspended;
178 int irq;
179 int use_dma, dma_ch;
180 int dma_line_tx, dma_line_rx;
181 int slot_id;
182 int got_dbclk;
183 int response_busy;
184 int context_loss;
185 int dpm_state;
186 int vdd;
187 int protect_card;
188 int reqs_blocked;
189 int use_reg;
190 int req_in_progress;
191 struct omap_hsmmc_next next_data;
192
193 struct omap_mmc_platform_data *pdata;
194};
195
196static int omap_hsmmc_card_detect(struct device *dev, int slot)
197{
198 struct omap_mmc_platform_data *mmc = dev->platform_data;
199
200 /* NOTE: assumes card detect signal is active-low */
201 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
202}
203
204static int omap_hsmmc_get_wp(struct device *dev, int slot)
205{
206 struct omap_mmc_platform_data *mmc = dev->platform_data;
207
208 /* NOTE: assumes write protect signal is active-high */
209 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
210}
211
212static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
213{
214 struct omap_mmc_platform_data *mmc = dev->platform_data;
215
216 /* NOTE: assumes card detect signal is active-low */
217 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
218}
219
220#ifdef CONFIG_PM
221
222static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
223{
224 struct omap_mmc_platform_data *mmc = dev->platform_data;
225
226 disable_irq(mmc->slots[0].card_detect_irq);
227 return 0;
228}
229
230static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
231{
232 struct omap_mmc_platform_data *mmc = dev->platform_data;
233
234 enable_irq(mmc->slots[0].card_detect_irq);
235 return 0;
236}
237
238#else
239
240#define omap_hsmmc_suspend_cdirq NULL
241#define omap_hsmmc_resume_cdirq NULL
242
243#endif
244
245#ifdef CONFIG_REGULATOR
246
247static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
248 int vdd)
249{
250 struct omap_hsmmc_host *host =
251 platform_get_drvdata(to_platform_device(dev));
252 int ret;
253
254 if (mmc_slot(host).before_set_reg)
255 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
256
257 if (power_on)
258 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
259 else
260 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
261
262 if (mmc_slot(host).after_set_reg)
263 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
264
265 return ret;
266}
267
268static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
269 int vdd)
270{
271 struct omap_hsmmc_host *host =
272 platform_get_drvdata(to_platform_device(dev));
273 int ret = 0;
274
275 /*
276 * If we don't see a Vcc regulator, assume it's a fixed
277 * voltage always-on regulator.
278 */
279 if (!host->vcc)
280 return 0;
281
282 if (mmc_slot(host).before_set_reg)
283 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
284
285 /*
286 * Assume Vcc regulator is used only to power the card ... OMAP
287 * VDDS is used to power the pins, optionally with a transceiver to
288 * support cards using voltages other than VDDS (1.8V nominal). When a
289 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
290 *
291 * In some cases this regulator won't support enable/disable;
292 * e.g. it's a fixed rail for a WLAN chip.
293 *
294 * In other cases vcc_aux switches interface power. Example, for
295 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
296 * chips/cards need an interface voltage rail too.
297 */
298 if (power_on) {
299 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
300 /* Enable interface voltage rail, if needed */
301 if (ret == 0 && host->vcc_aux) {
302 ret = regulator_enable(host->vcc_aux);
303 if (ret < 0)
304 ret = mmc_regulator_set_ocr(host->mmc,
305 host->vcc, 0);
306 }
307 } else {
308 /* Shut down the rail */
309 if (host->vcc_aux)
310 ret = regulator_disable(host->vcc_aux);
311 if (!ret) {
312 /* Then proceed to shut down the local regulator */
313 ret = mmc_regulator_set_ocr(host->mmc,
314 host->vcc, 0);
315 }
316 }
317
318 if (mmc_slot(host).after_set_reg)
319 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
320
321 return ret;
322}
323
324static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
325 int vdd)
326{
327 return 0;
328}
329
330static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
331 int vdd, int cardsleep)
332{
333 struct omap_hsmmc_host *host =
334 platform_get_drvdata(to_platform_device(dev));
335 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
336
337 return regulator_set_mode(host->vcc, mode);
338}
339
340static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
341 int vdd, int cardsleep)
342{
343 struct omap_hsmmc_host *host =
344 platform_get_drvdata(to_platform_device(dev));
345 int err, mode;
346
347 /*
348 * If we don't see a Vcc regulator, assume it's a fixed
349 * voltage always-on regulator.
350 */
351 if (!host->vcc)
352 return 0;
353
354 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
355
356 if (!host->vcc_aux)
357 return regulator_set_mode(host->vcc, mode);
358
359 if (cardsleep) {
360 /* VCC can be turned off if card is asleep */
361 if (sleep)
362 err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
363 else
364 err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
365 } else
366 err = regulator_set_mode(host->vcc, mode);
367 if (err)
368 return err;
369
370 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
371 return regulator_set_mode(host->vcc_aux, mode);
372
373 if (sleep)
374 return regulator_disable(host->vcc_aux);
375 else
376 return regulator_enable(host->vcc_aux);
377}
378
379static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
380 int vdd, int cardsleep)
381{
382 return 0;
383}
384
385static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
386{
387 struct regulator *reg;
388 int ret = 0;
389 int ocr_value = 0;
390
391 switch (host->id) {
392 case OMAP_MMC1_DEVID:
393 /* On-chip level shifting via PBIAS0/PBIAS1 */
394 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
395 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
396 break;
397 case OMAP_MMC2_DEVID:
398 case OMAP_MMC3_DEVID:
399 case OMAP_MMC5_DEVID:
400 /* Off-chip level shifting, or none */
401 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
402 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
403 break;
404 case OMAP_MMC4_DEVID:
405 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
406 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
407 default:
408 pr_err("MMC%d configuration not supported!\n", host->id);
409 return -EINVAL;
410 }
411
412 reg = regulator_get(host->dev, "vmmc");
413 if (IS_ERR(reg)) {
414 dev_dbg(host->dev, "vmmc regulator missing\n");
415 /*
416 * HACK: until fixed.c regulator is usable,
417 * we don't require a main regulator
418 * for MMC2 or MMC3
419 */
420 if (host->id == OMAP_MMC1_DEVID) {
421 ret = PTR_ERR(reg);
422 goto err;
423 }
424 } else {
425 host->vcc = reg;
426 ocr_value = mmc_regulator_get_ocrmask(reg);
427 if (!mmc_slot(host).ocr_mask) {
428 mmc_slot(host).ocr_mask = ocr_value;
429 } else {
430 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
431 pr_err("MMC%d ocrmask %x is not supported\n",
432 host->id, mmc_slot(host).ocr_mask);
433 mmc_slot(host).ocr_mask = 0;
434 return -EINVAL;
435 }
436 }
437
438 /* Allow an aux regulator */
439 reg = regulator_get(host->dev, "vmmc_aux");
440 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
441
442 /* For eMMC do not power off when not in sleep state */
443 if (mmc_slot(host).no_regulator_off_init)
444 return 0;
445 /*
446 * UGLY HACK: workaround regulator framework bugs.
447 * When the bootloader leaves a supply active, it's
448 * initialized with zero usecount ... and we can't
449 * disable it without first enabling it. Until the
450 * framework is fixed, we need a workaround like this
451 * (which is safe for MMC, but not in general).
452 */
453 if (regulator_is_enabled(host->vcc) > 0) {
454 regulator_enable(host->vcc);
455 regulator_disable(host->vcc);
456 }
457 if (host->vcc_aux) {
458 if (regulator_is_enabled(reg) > 0) {
459 regulator_enable(reg);
460 regulator_disable(reg);
461 }
462 }
463 }
464
465 return 0;
466
467err:
468 mmc_slot(host).set_power = NULL;
469 mmc_slot(host).set_sleep = NULL;
470 return ret;
471}
472
473static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
474{
475 regulator_put(host->vcc);
476 regulator_put(host->vcc_aux);
477 mmc_slot(host).set_power = NULL;
478 mmc_slot(host).set_sleep = NULL;
479}
480
481static inline int omap_hsmmc_have_reg(void)
482{
483 return 1;
484}
485
486#else
487
488static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
489{
490 return -EINVAL;
491}
492
493static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
494{
495}
496
497static inline int omap_hsmmc_have_reg(void)
498{
499 return 0;
500}
501
502#endif
503
504static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
505{
506 int ret;
507
508 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
509 if (pdata->slots[0].cover)
510 pdata->slots[0].get_cover_state =
511 omap_hsmmc_get_cover_state;
512 else
513 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
514 pdata->slots[0].card_detect_irq =
515 gpio_to_irq(pdata->slots[0].switch_pin);
516 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
517 if (ret)
518 return ret;
519 ret = gpio_direction_input(pdata->slots[0].switch_pin);
520 if (ret)
521 goto err_free_sp;
522 } else
523 pdata->slots[0].switch_pin = -EINVAL;
524
525 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
526 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
527 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
528 if (ret)
529 goto err_free_cd;
530 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
531 if (ret)
532 goto err_free_wp;
533 } else
534 pdata->slots[0].gpio_wp = -EINVAL;
535
536 return 0;
537
538err_free_wp:
539 gpio_free(pdata->slots[0].gpio_wp);
540err_free_cd:
541 if (gpio_is_valid(pdata->slots[0].switch_pin))
542err_free_sp:
543 gpio_free(pdata->slots[0].switch_pin);
544 return ret;
545}
546
547static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
548{
549 if (gpio_is_valid(pdata->slots[0].gpio_wp))
550 gpio_free(pdata->slots[0].gpio_wp);
551 if (gpio_is_valid(pdata->slots[0].switch_pin))
552 gpio_free(pdata->slots[0].switch_pin);
553}
554
555/*
556 * Start clock to the card
557 */
558static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
559{
560 OMAP_HSMMC_WRITE(host->base, SYSCTL,
561 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
562}
563
564/*
565 * Stop clock to the card
566 */
567static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
568{
569 OMAP_HSMMC_WRITE(host->base, SYSCTL,
570 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
571 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
572 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
573}
574
575static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
576 struct mmc_command *cmd)
577{
578 unsigned int irq_mask;
579
580 if (host->use_dma)
581 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
582 else
583 irq_mask = INT_EN_MASK;
584
585 /* Disable timeout for erases */
586 if (cmd->opcode == MMC_ERASE)
587 irq_mask &= ~DTO_ENABLE;
588
589 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
590 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
591 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
592}
593
594static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
595{
596 OMAP_HSMMC_WRITE(host->base, ISE, 0);
597 OMAP_HSMMC_WRITE(host->base, IE, 0);
598 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
599}
600
601/* Calculate divisor for the given clock frequency */
602static u16 calc_divisor(struct mmc_ios *ios)
603{
604 u16 dsor = 0;
605
606 if (ios->clock) {
607 dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock);
608 if (dsor > 250)
609 dsor = 250;
610 }
611
612 return dsor;
613}
614
615static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
616{
617 struct mmc_ios *ios = &host->mmc->ios;
618 unsigned long regval;
619 unsigned long timeout;
620
621 dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
622
623 omap_hsmmc_stop_clock(host);
624
625 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
626 regval = regval & ~(CLKD_MASK | DTO_MASK);
627 regval = regval | (calc_divisor(ios) << 6) | (DTO << 16);
628 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
629 OMAP_HSMMC_WRITE(host->base, SYSCTL,
630 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
631
632 /* Wait till the ICS bit is set */
633 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
634 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
635 && time_before(jiffies, timeout))
636 cpu_relax();
637
638 omap_hsmmc_start_clock(host);
639}
640
641static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
642{
643 struct mmc_ios *ios = &host->mmc->ios;
644 u32 con;
645
646 con = OMAP_HSMMC_READ(host->base, CON);
647 switch (ios->bus_width) {
648 case MMC_BUS_WIDTH_8:
649 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
650 break;
651 case MMC_BUS_WIDTH_4:
652 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
653 OMAP_HSMMC_WRITE(host->base, HCTL,
654 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
655 break;
656 case MMC_BUS_WIDTH_1:
657 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
658 OMAP_HSMMC_WRITE(host->base, HCTL,
659 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
660 break;
661 }
662}
663
664static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
665{
666 struct mmc_ios *ios = &host->mmc->ios;
667 u32 con;
668
669 con = OMAP_HSMMC_READ(host->base, CON);
670 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
671 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
672 else
673 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
674}
675
676#ifdef CONFIG_PM
677
678/*
679 * Restore the MMC host context, if it was lost as result of a
680 * power state change.
681 */
682static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
683{
684 struct mmc_ios *ios = &host->mmc->ios;
685 struct omap_mmc_platform_data *pdata = host->pdata;
686 int context_loss = 0;
687 u32 hctl, capa;
688 unsigned long timeout;
689
690 if (pdata->get_context_loss_count) {
691 context_loss = pdata->get_context_loss_count(host->dev);
692 if (context_loss < 0)
693 return 1;
694 }
695
696 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
697 context_loss == host->context_loss ? "not " : "");
698 if (host->context_loss == context_loss)
699 return 1;
700
701 /* Wait for hardware reset */
702 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
703 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
704 && time_before(jiffies, timeout))
705 ;
706
707 /* Do software reset */
708 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
709 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
710 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
711 && time_before(jiffies, timeout))
712 ;
713
714 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
715 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
716
717 if (host->id == OMAP_MMC1_DEVID) {
718 if (host->power_mode != MMC_POWER_OFF &&
719 (1 << ios->vdd) <= MMC_VDD_23_24)
720 hctl = SDVS18;
721 else
722 hctl = SDVS30;
723 capa = VS30 | VS18;
724 } else {
725 hctl = SDVS18;
726 capa = VS18;
727 }
728
729 OMAP_HSMMC_WRITE(host->base, HCTL,
730 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
731
732 OMAP_HSMMC_WRITE(host->base, CAPA,
733 OMAP_HSMMC_READ(host->base, CAPA) | capa);
734
735 OMAP_HSMMC_WRITE(host->base, HCTL,
736 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
737
738 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
739 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
740 && time_before(jiffies, timeout))
741 ;
742
743 omap_hsmmc_disable_irq(host);
744
745 /* Do not initialize card-specific things if the power is off */
746 if (host->power_mode == MMC_POWER_OFF)
747 goto out;
748
749 omap_hsmmc_set_bus_width(host);
750
751 omap_hsmmc_set_clock(host);
752
753 omap_hsmmc_set_bus_mode(host);
754
755out:
756 host->context_loss = context_loss;
757
758 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
759 return 0;
760}
761
762/*
763 * Save the MMC host context (store the number of power state changes so far).
764 */
765static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
766{
767 struct omap_mmc_platform_data *pdata = host->pdata;
768 int context_loss;
769
770 if (pdata->get_context_loss_count) {
771 context_loss = pdata->get_context_loss_count(host->dev);
772 if (context_loss < 0)
773 return;
774 host->context_loss = context_loss;
775 }
776}
777
778#else
779
780static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
781{
782 return 0;
783}
784
785static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
786{
787}
788
789#endif
790
791/*
792 * Send init stream sequence to card
793 * before sending IDLE command
794 */
795static void send_init_stream(struct omap_hsmmc_host *host)
796{
797 int reg = 0;
798 unsigned long timeout;
799
800 if (host->protect_card)
801 return;
802
803 disable_irq(host->irq);
804
805 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
806 OMAP_HSMMC_WRITE(host->base, CON,
807 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
808 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
809
810 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
811 while ((reg != CC) && time_before(jiffies, timeout))
812 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
813
814 OMAP_HSMMC_WRITE(host->base, CON,
815 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
816
817 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
818 OMAP_HSMMC_READ(host->base, STAT);
819
820 enable_irq(host->irq);
821}
822
823static inline
824int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
825{
826 int r = 1;
827
828 if (mmc_slot(host).get_cover_state)
829 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
830 return r;
831}
832
833static ssize_t
834omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
835 char *buf)
836{
837 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
838 struct omap_hsmmc_host *host = mmc_priv(mmc);
839
840 return sprintf(buf, "%s\n",
841 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
842}
843
844static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
845
846static ssize_t
847omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
848 char *buf)
849{
850 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
851 struct omap_hsmmc_host *host = mmc_priv(mmc);
852
853 return sprintf(buf, "%s\n", mmc_slot(host).name);
854}
855
856static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
857
858/*
859 * Configure the response type and send the cmd.
860 */
861static void
862omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
863 struct mmc_data *data)
864{
865 int cmdreg = 0, resptype = 0, cmdtype = 0;
866
867 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
868 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
869 host->cmd = cmd;
870
871 omap_hsmmc_enable_irq(host, cmd);
872
873 host->response_busy = 0;
874 if (cmd->flags & MMC_RSP_PRESENT) {
875 if (cmd->flags & MMC_RSP_136)
876 resptype = 1;
877 else if (cmd->flags & MMC_RSP_BUSY) {
878 resptype = 3;
879 host->response_busy = 1;
880 } else
881 resptype = 2;
882 }
883
884 /*
885 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
886 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
887 * a val of 0x3, rest 0x0.
888 */
889 if (cmd == host->mrq->stop)
890 cmdtype = 0x3;
891
892 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
893
894 if (data) {
895 cmdreg |= DP_SELECT | MSBS | BCE;
896 if (data->flags & MMC_DATA_READ)
897 cmdreg |= DDIR;
898 else
899 cmdreg &= ~(DDIR);
900 }
901
902 if (host->use_dma)
903 cmdreg |= DMA_EN;
904
905 host->req_in_progress = 1;
906
907 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
908 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
909}
910
911static int
912omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
913{
914 if (data->flags & MMC_DATA_WRITE)
915 return DMA_TO_DEVICE;
916 else
917 return DMA_FROM_DEVICE;
918}
919
920static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
921{
922 int dma_ch;
923
924 spin_lock(&host->irq_lock);
925 host->req_in_progress = 0;
926 dma_ch = host->dma_ch;
927 spin_unlock(&host->irq_lock);
928
929 omap_hsmmc_disable_irq(host);
930 /* Do not complete the request if DMA is still in progress */
931 if (mrq->data && host->use_dma && dma_ch != -1)
932 return;
933 host->mrq = NULL;
934 mmc_request_done(host->mmc, mrq);
935}
936
937/*
938 * Notify the transfer complete to MMC core
939 */
940static void
941omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
942{
943 if (!data) {
944 struct mmc_request *mrq = host->mrq;
945
946 /* TC before CC from CMD6 - don't know why, but it happens */
947 if (host->cmd && host->cmd->opcode == 6 &&
948 host->response_busy) {
949 host->response_busy = 0;
950 return;
951 }
952
953 omap_hsmmc_request_done(host, mrq);
954 return;
955 }
956
957 host->data = NULL;
958
959 if (!data->error)
960 data->bytes_xfered += data->blocks * (data->blksz);
961 else
962 data->bytes_xfered = 0;
963
964 if (!data->stop) {
965 omap_hsmmc_request_done(host, data->mrq);
966 return;
967 }
968 omap_hsmmc_start_command(host, data->stop, NULL);
969}
970
971/*
972 * Notify the core about command completion
973 */
974static void
975omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
976{
977 host->cmd = NULL;
978
979 if (cmd->flags & MMC_RSP_PRESENT) {
980 if (cmd->flags & MMC_RSP_136) {
981 /* response type 2 */
982 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
983 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
984 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
985 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
986 } else {
987 /* response types 1, 1b, 3, 4, 5, 6 */
988 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
989 }
990 }
991 if ((host->data == NULL && !host->response_busy) || cmd->error)
992 omap_hsmmc_request_done(host, cmd->mrq);
993}
994
995/*
996 * DMA clean up for command errors
997 */
998static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
999{
1000 int dma_ch;
1001
1002 host->data->error = errno;
1003
1004 spin_lock(&host->irq_lock);
1005 dma_ch = host->dma_ch;
1006 host->dma_ch = -1;
1007 spin_unlock(&host->irq_lock);
1008
1009 if (host->use_dma && dma_ch != -1) {
1010 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
1011 host->data->sg_len,
1012 omap_hsmmc_get_dma_dir(host, host->data));
1013 omap_free_dma(dma_ch);
1014 }
1015 host->data = NULL;
1016}
1017
1018/*
1019 * Readable error output
1020 */
1021#ifdef CONFIG_MMC_DEBUG
1022static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1023{
1024 /* --- means reserved bit without definition at documentation */
1025 static const char *omap_hsmmc_status_bits[] = {
1026 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1027 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1028 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1029 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1030 };
1031 char res[256];
1032 char *buf = res;
1033 int len, i;
1034
1035 len = sprintf(buf, "MMC IRQ 0x%x :", status);
1036 buf += len;
1037
1038 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1039 if (status & (1 << i)) {
1040 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1041 buf += len;
1042 }
1043
1044 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1045}
1046#else
1047static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1048 u32 status)
1049{
1050}
1051#endif /* CONFIG_MMC_DEBUG */
1052
1053/*
1054 * MMC controller internal state machines reset
1055 *
1056 * Used to reset command or data internal state machines, using respectively
1057 * SRC or SRD bit of SYSCTL register
1058 * Can be called from interrupt context
1059 */
1060static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1061 unsigned long bit)
1062{
1063 unsigned long i = 0;
1064 unsigned long limit = (loops_per_jiffy *
1065 msecs_to_jiffies(MMC_TIMEOUT_MS));
1066
1067 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1068 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1069
1070 /*
1071 * OMAP4 ES2 and greater has an updated reset logic.
1072 * Monitor a 0->1 transition first
1073 */
1074 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1075 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1076 && (i++ < limit))
1077 cpu_relax();
1078 }
1079 i = 0;
1080
1081 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1082 (i++ < limit))
1083 cpu_relax();
1084
1085 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1086 dev_err(mmc_dev(host->mmc),
1087 "Timeout waiting on controller reset in %s\n",
1088 __func__);
1089}
1090
1091static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1092{
1093 struct mmc_data *data;
1094 int end_cmd = 0, end_trans = 0;
1095
1096 if (!host->req_in_progress) {
1097 do {
1098 OMAP_HSMMC_WRITE(host->base, STAT, status);
1099 /* Flush posted write */
1100 status = OMAP_HSMMC_READ(host->base, STAT);
1101 } while (status & INT_EN_MASK);
1102 return;
1103 }
1104
1105 data = host->data;
1106 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1107
1108 if (status & ERR) {
1109 omap_hsmmc_dbg_report_irq(host, status);
1110 if ((status & CMD_TIMEOUT) ||
1111 (status & CMD_CRC)) {
1112 if (host->cmd) {
1113 if (status & CMD_TIMEOUT) {
1114 omap_hsmmc_reset_controller_fsm(host,
1115 SRC);
1116 host->cmd->error = -ETIMEDOUT;
1117 } else {
1118 host->cmd->error = -EILSEQ;
1119 }
1120 end_cmd = 1;
1121 }
1122 if (host->data || host->response_busy) {
1123 if (host->data)
1124 omap_hsmmc_dma_cleanup(host,
1125 -ETIMEDOUT);
1126 host->response_busy = 0;
1127 omap_hsmmc_reset_controller_fsm(host, SRD);
1128 }
1129 }
1130 if ((status & DATA_TIMEOUT) ||
1131 (status & DATA_CRC)) {
1132 if (host->data || host->response_busy) {
1133 int err = (status & DATA_TIMEOUT) ?
1134 -ETIMEDOUT : -EILSEQ;
1135
1136 if (host->data)
1137 omap_hsmmc_dma_cleanup(host, err);
1138 else
1139 host->mrq->cmd->error = err;
1140 host->response_busy = 0;
1141 omap_hsmmc_reset_controller_fsm(host, SRD);
1142 end_trans = 1;
1143 }
1144 }
1145 if (status & CARD_ERR) {
1146 dev_dbg(mmc_dev(host->mmc),
1147 "Ignoring card err CMD%d\n", host->cmd->opcode);
1148 if (host->cmd)
1149 end_cmd = 1;
1150 if (host->data)
1151 end_trans = 1;
1152 }
1153 }
1154
1155 OMAP_HSMMC_WRITE(host->base, STAT, status);
1156
1157 if (end_cmd || ((status & CC) && host->cmd))
1158 omap_hsmmc_cmd_done(host, host->cmd);
1159 if ((end_trans || (status & TC)) && host->mrq)
1160 omap_hsmmc_xfer_done(host, data);
1161}
1162
1163/*
1164 * MMC controller IRQ handler
1165 */
1166static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1167{
1168 struct omap_hsmmc_host *host = dev_id;
1169 int status;
1170
1171 status = OMAP_HSMMC_READ(host->base, STAT);
1172 do {
1173 omap_hsmmc_do_irq(host, status);
1174 /* Flush posted write */
1175 status = OMAP_HSMMC_READ(host->base, STAT);
1176 } while (status & INT_EN_MASK);
1177
1178 return IRQ_HANDLED;
1179}
1180
1181static void set_sd_bus_power(struct omap_hsmmc_host *host)
1182{
1183 unsigned long i;
1184
1185 OMAP_HSMMC_WRITE(host->base, HCTL,
1186 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1187 for (i = 0; i < loops_per_jiffy; i++) {
1188 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1189 break;
1190 cpu_relax();
1191 }
1192}
1193
1194/*
1195 * Switch MMC interface voltage ... only relevant for MMC1.
1196 *
1197 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1198 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1199 * Some chips, like eMMC ones, use internal transceivers.
1200 */
1201static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1202{
1203 u32 reg_val = 0;
1204 int ret;
1205
1206 /* Disable the clocks */
1207 pm_runtime_put_sync(host->dev);
1208 if (host->got_dbclk)
1209 clk_disable(host->dbclk);
1210
1211 /* Turn the power off */
1212 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1213
1214 /* Turn the power ON with given VDD 1.8 or 3.0v */
1215 if (!ret)
1216 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1217 vdd);
1218 pm_runtime_get_sync(host->dev);
1219 if (host->got_dbclk)
1220 clk_enable(host->dbclk);
1221
1222 if (ret != 0)
1223 goto err;
1224
1225 OMAP_HSMMC_WRITE(host->base, HCTL,
1226 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1227 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1228
1229 /*
1230 * If a MMC dual voltage card is detected, the set_ios fn calls
1231 * this fn with VDD bit set for 1.8V. Upon card removal from the
1232 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1233 *
1234 * Cope with a bit of slop in the range ... per data sheets:
1235 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1236 * but recommended values are 1.71V to 1.89V
1237 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1238 * but recommended values are 2.7V to 3.3V
1239 *
1240 * Board setup code shouldn't permit anything very out-of-range.
1241 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1242 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1243 */
1244 if ((1 << vdd) <= MMC_VDD_23_24)
1245 reg_val |= SDVS18;
1246 else
1247 reg_val |= SDVS30;
1248
1249 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1250 set_sd_bus_power(host);
1251
1252 return 0;
1253err:
1254 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1255 return ret;
1256}
1257
1258/* Protect the card while the cover is open */
1259static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1260{
1261 if (!mmc_slot(host).get_cover_state)
1262 return;
1263
1264 host->reqs_blocked = 0;
1265 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1266 if (host->protect_card) {
1267 printk(KERN_INFO "%s: cover is closed, "
1268 "card is now accessible\n",
1269 mmc_hostname(host->mmc));
1270 host->protect_card = 0;
1271 }
1272 } else {
1273 if (!host->protect_card) {
1274 printk(KERN_INFO "%s: cover is open, "
1275 "card is now inaccessible\n",
1276 mmc_hostname(host->mmc));
1277 host->protect_card = 1;
1278 }
1279 }
1280}
1281
1282/*
1283 * Work Item to notify the core about card insertion/removal
1284 */
1285static void omap_hsmmc_detect(struct work_struct *work)
1286{
1287 struct omap_hsmmc_host *host =
1288 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
1289 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1290 int carddetect;
1291
1292 if (host->suspended)
1293 return;
1294
1295 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1296
1297 if (slot->card_detect)
1298 carddetect = slot->card_detect(host->dev, host->slot_id);
1299 else {
1300 omap_hsmmc_protect_card(host);
1301 carddetect = -ENOSYS;
1302 }
1303
1304 if (carddetect)
1305 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1306 else
1307 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1308}
1309
1310/*
1311 * ISR for handling card insertion and removal
1312 */
1313static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
1314{
1315 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
1316
1317 if (host->suspended)
1318 return IRQ_HANDLED;
1319 schedule_work(&host->mmc_carddetect_work);
1320
1321 return IRQ_HANDLED;
1322}
1323
1324static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1325 struct mmc_data *data)
1326{
1327 int sync_dev;
1328
1329 if (data->flags & MMC_DATA_WRITE)
1330 sync_dev = host->dma_line_tx;
1331 else
1332 sync_dev = host->dma_line_rx;
1333 return sync_dev;
1334}
1335
1336static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1337 struct mmc_data *data,
1338 struct scatterlist *sgl)
1339{
1340 int blksz, nblk, dma_ch;
1341
1342 dma_ch = host->dma_ch;
1343 if (data->flags & MMC_DATA_WRITE) {
1344 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1345 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1346 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1347 sg_dma_address(sgl), 0, 0);
1348 } else {
1349 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1350 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1351 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1352 sg_dma_address(sgl), 0, 0);
1353 }
1354
1355 blksz = host->data->blksz;
1356 nblk = sg_dma_len(sgl) / blksz;
1357
1358 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1359 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1360 omap_hsmmc_get_dma_sync_dev(host, data),
1361 !(data->flags & MMC_DATA_WRITE));
1362
1363 omap_start_dma(dma_ch);
1364}
1365
1366/*
1367 * DMA call back function
1368 */
1369static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1370{
1371 struct omap_hsmmc_host *host = cb_data;
1372 struct mmc_data *data;
1373 int dma_ch, req_in_progress;
1374
1375 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1376 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1377 ch_status);
1378 return;
1379 }
1380
1381 spin_lock(&host->irq_lock);
1382 if (host->dma_ch < 0) {
1383 spin_unlock(&host->irq_lock);
1384 return;
1385 }
1386
1387 data = host->mrq->data;
1388 host->dma_sg_idx++;
1389 if (host->dma_sg_idx < host->dma_len) {
1390 /* Fire up the next transfer. */
1391 omap_hsmmc_config_dma_params(host, data,
1392 data->sg + host->dma_sg_idx);
1393 spin_unlock(&host->irq_lock);
1394 return;
1395 }
1396
1397 if (!data->host_cookie)
1398 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1399 omap_hsmmc_get_dma_dir(host, data));
1400
1401 req_in_progress = host->req_in_progress;
1402 dma_ch = host->dma_ch;
1403 host->dma_ch = -1;
1404 spin_unlock(&host->irq_lock);
1405
1406 omap_free_dma(dma_ch);
1407
1408 /* If DMA has finished after TC, complete the request */
1409 if (!req_in_progress) {
1410 struct mmc_request *mrq = host->mrq;
1411
1412 host->mrq = NULL;
1413 mmc_request_done(host->mmc, mrq);
1414 }
1415}
1416
1417static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1418 struct mmc_data *data,
1419 struct omap_hsmmc_next *next)
1420{
1421 int dma_len;
1422
1423 if (!next && data->host_cookie &&
1424 data->host_cookie != host->next_data.cookie) {
1425 printk(KERN_WARNING "[%s] invalid cookie: data->host_cookie %d"
1426 " host->next_data.cookie %d\n",
1427 __func__, data->host_cookie, host->next_data.cookie);
1428 data->host_cookie = 0;
1429 }
1430
1431 /* Check if next job is already prepared */
1432 if (next ||
1433 (!next && data->host_cookie != host->next_data.cookie)) {
1434 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1435 data->sg_len,
1436 omap_hsmmc_get_dma_dir(host, data));
1437
1438 } else {
1439 dma_len = host->next_data.dma_len;
1440 host->next_data.dma_len = 0;
1441 }
1442
1443
1444 if (dma_len == 0)
1445 return -EINVAL;
1446
1447 if (next) {
1448 next->dma_len = dma_len;
1449 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1450 } else
1451 host->dma_len = dma_len;
1452
1453 return 0;
1454}
1455
1456/*
1457 * Routine to configure and start DMA for the MMC card
1458 */
1459static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1460 struct mmc_request *req)
1461{
1462 int dma_ch = 0, ret = 0, i;
1463 struct mmc_data *data = req->data;
1464
1465 /* Sanity check: all the SG entries must be aligned by block size. */
1466 for (i = 0; i < data->sg_len; i++) {
1467 struct scatterlist *sgl;
1468
1469 sgl = data->sg + i;
1470 if (sgl->length % data->blksz)
1471 return -EINVAL;
1472 }
1473 if ((data->blksz % 4) != 0)
1474 /* REVISIT: The MMC buffer increments only when MSB is written.
1475 * Return error for blksz which is non multiple of four.
1476 */
1477 return -EINVAL;
1478
1479 BUG_ON(host->dma_ch != -1);
1480
1481 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1482 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1483 if (ret != 0) {
1484 dev_err(mmc_dev(host->mmc),
1485 "%s: omap_request_dma() failed with %d\n",
1486 mmc_hostname(host->mmc), ret);
1487 return ret;
1488 }
1489 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1490 if (ret)
1491 return ret;
1492
1493 host->dma_ch = dma_ch;
1494 host->dma_sg_idx = 0;
1495
1496 omap_hsmmc_config_dma_params(host, data, data->sg);
1497
1498 return 0;
1499}
1500
1501static void set_data_timeout(struct omap_hsmmc_host *host,
1502 unsigned int timeout_ns,
1503 unsigned int timeout_clks)
1504{
1505 unsigned int timeout, cycle_ns;
1506 uint32_t reg, clkd, dto = 0;
1507
1508 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1509 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1510 if (clkd == 0)
1511 clkd = 1;
1512
1513 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1514 timeout = timeout_ns / cycle_ns;
1515 timeout += timeout_clks;
1516 if (timeout) {
1517 while ((timeout & 0x80000000) == 0) {
1518 dto += 1;
1519 timeout <<= 1;
1520 }
1521 dto = 31 - dto;
1522 timeout <<= 1;
1523 if (timeout && dto)
1524 dto += 1;
1525 if (dto >= 13)
1526 dto -= 13;
1527 else
1528 dto = 0;
1529 if (dto > 14)
1530 dto = 14;
1531 }
1532
1533 reg &= ~DTO_MASK;
1534 reg |= dto << DTO_SHIFT;
1535 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1536}
1537
1538/*
1539 * Configure block length for MMC/SD cards and initiate the transfer.
1540 */
1541static int
1542omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1543{
1544 int ret;
1545 host->data = req->data;
1546
1547 if (req->data == NULL) {
1548 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1549 /*
1550 * Set an arbitrary 100ms data timeout for commands with
1551 * busy signal.
1552 */
1553 if (req->cmd->flags & MMC_RSP_BUSY)
1554 set_data_timeout(host, 100000000U, 0);
1555 return 0;
1556 }
1557
1558 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1559 | (req->data->blocks << 16));
1560 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1561
1562 if (host->use_dma) {
1563 ret = omap_hsmmc_start_dma_transfer(host, req);
1564 if (ret != 0) {
1565 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1566 return ret;
1567 }
1568 }
1569 return 0;
1570}
1571
1572static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1573 int err)
1574{
1575 struct omap_hsmmc_host *host = mmc_priv(mmc);
1576 struct mmc_data *data = mrq->data;
1577
1578 if (host->use_dma) {
1579 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1580 omap_hsmmc_get_dma_dir(host, data));
1581 data->host_cookie = 0;
1582 }
1583}
1584
1585static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1586 bool is_first_req)
1587{
1588 struct omap_hsmmc_host *host = mmc_priv(mmc);
1589
1590 if (mrq->data->host_cookie) {
1591 mrq->data->host_cookie = 0;
1592 return ;
1593 }
1594
1595 if (host->use_dma)
1596 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1597 &host->next_data))
1598 mrq->data->host_cookie = 0;
1599}
1600
1601/*
1602 * Request function. for read/write operation
1603 */
1604static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1605{
1606 struct omap_hsmmc_host *host = mmc_priv(mmc);
1607 int err;
1608
1609 BUG_ON(host->req_in_progress);
1610 BUG_ON(host->dma_ch != -1);
1611 if (host->protect_card) {
1612 if (host->reqs_blocked < 3) {
1613 /*
1614 * Ensure the controller is left in a consistent
1615 * state by resetting the command and data state
1616 * machines.
1617 */
1618 omap_hsmmc_reset_controller_fsm(host, SRD);
1619 omap_hsmmc_reset_controller_fsm(host, SRC);
1620 host->reqs_blocked += 1;
1621 }
1622 req->cmd->error = -EBADF;
1623 if (req->data)
1624 req->data->error = -EBADF;
1625 req->cmd->retries = 0;
1626 mmc_request_done(mmc, req);
1627 return;
1628 } else if (host->reqs_blocked)
1629 host->reqs_blocked = 0;
1630 WARN_ON(host->mrq != NULL);
1631 host->mrq = req;
1632 err = omap_hsmmc_prepare_data(host, req);
1633 if (err) {
1634 req->cmd->error = err;
1635 if (req->data)
1636 req->data->error = err;
1637 host->mrq = NULL;
1638 mmc_request_done(mmc, req);
1639 return;
1640 }
1641
1642 omap_hsmmc_start_command(host, req->cmd, req->data);
1643}
1644
1645/* Routine to configure clock values. Exposed API to core */
1646static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1647{
1648 struct omap_hsmmc_host *host = mmc_priv(mmc);
1649 int do_send_init_stream = 0;
1650
1651 pm_runtime_get_sync(host->dev);
1652
1653 if (ios->power_mode != host->power_mode) {
1654 switch (ios->power_mode) {
1655 case MMC_POWER_OFF:
1656 mmc_slot(host).set_power(host->dev, host->slot_id,
1657 0, 0);
1658 host->vdd = 0;
1659 break;
1660 case MMC_POWER_UP:
1661 mmc_slot(host).set_power(host->dev, host->slot_id,
1662 1, ios->vdd);
1663 host->vdd = ios->vdd;
1664 break;
1665 case MMC_POWER_ON:
1666 do_send_init_stream = 1;
1667 break;
1668 }
1669 host->power_mode = ios->power_mode;
1670 }
1671
1672 /* FIXME: set registers based only on changes to ios */
1673
1674 omap_hsmmc_set_bus_width(host);
1675
1676 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1677 /* Only MMC1 can interface at 3V without some flavor
1678 * of external transceiver; but they all handle 1.8V.
1679 */
1680 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1681 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1682 /*
1683 * The mmc_select_voltage fn of the core does
1684 * not seem to set the power_mode to
1685 * MMC_POWER_UP upon recalculating the voltage.
1686 * vdd 1.8v.
1687 */
1688 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1689 dev_dbg(mmc_dev(host->mmc),
1690 "Switch operation failed\n");
1691 }
1692 }
1693
1694 omap_hsmmc_set_clock(host);
1695
1696 if (do_send_init_stream)
1697 send_init_stream(host);
1698
1699 omap_hsmmc_set_bus_mode(host);
1700
1701 pm_runtime_put_autosuspend(host->dev);
1702}
1703
1704static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1705{
1706 struct omap_hsmmc_host *host = mmc_priv(mmc);
1707
1708 if (!mmc_slot(host).card_detect)
1709 return -ENOSYS;
1710 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1711}
1712
1713static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1714{
1715 struct omap_hsmmc_host *host = mmc_priv(mmc);
1716
1717 if (!mmc_slot(host).get_ro)
1718 return -ENOSYS;
1719 return mmc_slot(host).get_ro(host->dev, 0);
1720}
1721
1722static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1723{
1724 struct omap_hsmmc_host *host = mmc_priv(mmc);
1725
1726 if (mmc_slot(host).init_card)
1727 mmc_slot(host).init_card(card);
1728}
1729
1730static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1731{
1732 u32 hctl, capa, value;
1733
1734 /* Only MMC1 supports 3.0V */
1735 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1736 hctl = SDVS30;
1737 capa = VS30 | VS18;
1738 } else {
1739 hctl = SDVS18;
1740 capa = VS18;
1741 }
1742
1743 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1744 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1745
1746 value = OMAP_HSMMC_READ(host->base, CAPA);
1747 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1748
1749 /* Set the controller to AUTO IDLE mode */
1750 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1751 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1752
1753 /* Set SD bus power bit */
1754 set_sd_bus_power(host);
1755}
1756
1757static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1758{
1759 struct omap_hsmmc_host *host = mmc_priv(mmc);
1760
1761 pm_runtime_get_sync(host->dev);
1762
1763 return 0;
1764}
1765
1766static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1767{
1768 struct omap_hsmmc_host *host = mmc_priv(mmc);
1769
1770 pm_runtime_mark_last_busy(host->dev);
1771 pm_runtime_put_autosuspend(host->dev);
1772
1773 return 0;
1774}
1775
1776static const struct mmc_host_ops omap_hsmmc_ops = {
1777 .enable = omap_hsmmc_enable_fclk,
1778 .disable = omap_hsmmc_disable_fclk,
1779 .post_req = omap_hsmmc_post_req,
1780 .pre_req = omap_hsmmc_pre_req,
1781 .request = omap_hsmmc_request,
1782 .set_ios = omap_hsmmc_set_ios,
1783 .get_cd = omap_hsmmc_get_cd,
1784 .get_ro = omap_hsmmc_get_ro,
1785 .init_card = omap_hsmmc_init_card,
1786 /* NYET -- enable_sdio_irq */
1787};
1788
1789#ifdef CONFIG_DEBUG_FS
1790
1791static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1792{
1793 struct mmc_host *mmc = s->private;
1794 struct omap_hsmmc_host *host = mmc_priv(mmc);
1795 int context_loss = 0;
1796
1797 if (host->pdata->get_context_loss_count)
1798 context_loss = host->pdata->get_context_loss_count(host->dev);
1799
1800 seq_printf(s, "mmc%d:\n"
1801 " enabled:\t%d\n"
1802 " dpm_state:\t%d\n"
1803 " nesting_cnt:\t%d\n"
1804 " ctx_loss:\t%d:%d\n"
1805 "\nregs:\n",
1806 mmc->index, mmc->enabled ? 1 : 0,
1807 host->dpm_state, mmc->nesting_cnt,
1808 host->context_loss, context_loss);
1809
1810 if (host->suspended) {
1811 seq_printf(s, "host suspended, can't read registers\n");
1812 return 0;
1813 }
1814
1815 pm_runtime_get_sync(host->dev);
1816
1817 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1818 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1819 seq_printf(s, "CON:\t\t0x%08x\n",
1820 OMAP_HSMMC_READ(host->base, CON));
1821 seq_printf(s, "HCTL:\t\t0x%08x\n",
1822 OMAP_HSMMC_READ(host->base, HCTL));
1823 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1824 OMAP_HSMMC_READ(host->base, SYSCTL));
1825 seq_printf(s, "IE:\t\t0x%08x\n",
1826 OMAP_HSMMC_READ(host->base, IE));
1827 seq_printf(s, "ISE:\t\t0x%08x\n",
1828 OMAP_HSMMC_READ(host->base, ISE));
1829 seq_printf(s, "CAPA:\t\t0x%08x\n",
1830 OMAP_HSMMC_READ(host->base, CAPA));
1831
1832 pm_runtime_mark_last_busy(host->dev);
1833 pm_runtime_put_autosuspend(host->dev);
1834
1835 return 0;
1836}
1837
1838static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1839{
1840 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1841}
1842
1843static const struct file_operations mmc_regs_fops = {
1844 .open = omap_hsmmc_regs_open,
1845 .read = seq_read,
1846 .llseek = seq_lseek,
1847 .release = single_release,
1848};
1849
1850static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1851{
1852 if (mmc->debugfs_root)
1853 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1854 mmc, &mmc_regs_fops);
1855}
1856
1857#else
1858
1859static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1860{
1861}
1862
1863#endif
1864
1865static int __init omap_hsmmc_probe(struct platform_device *pdev)
1866{
1867 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1868 struct mmc_host *mmc;
1869 struct omap_hsmmc_host *host = NULL;
1870 struct resource *res;
1871 int ret, irq;
1872
1873 if (pdata == NULL) {
1874 dev_err(&pdev->dev, "Platform Data is missing\n");
1875 return -ENXIO;
1876 }
1877
1878 if (pdata->nr_slots == 0) {
1879 dev_err(&pdev->dev, "No Slots\n");
1880 return -ENXIO;
1881 }
1882
1883 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1884 irq = platform_get_irq(pdev, 0);
1885 if (res == NULL || irq < 0)
1886 return -ENXIO;
1887
1888 res->start += pdata->reg_offset;
1889 res->end += pdata->reg_offset;
1890 res = request_mem_region(res->start, resource_size(res), pdev->name);
1891 if (res == NULL)
1892 return -EBUSY;
1893
1894 ret = omap_hsmmc_gpio_init(pdata);
1895 if (ret)
1896 goto err;
1897
1898 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1899 if (!mmc) {
1900 ret = -ENOMEM;
1901 goto err_alloc;
1902 }
1903
1904 host = mmc_priv(mmc);
1905 host->mmc = mmc;
1906 host->pdata = pdata;
1907 host->dev = &pdev->dev;
1908 host->use_dma = 1;
1909 host->dev->dma_mask = &pdata->dma_mask;
1910 host->dma_ch = -1;
1911 host->irq = irq;
1912 host->id = pdev->id;
1913 host->slot_id = 0;
1914 host->mapbase = res->start;
1915 host->base = ioremap(host->mapbase, SZ_4K);
1916 host->power_mode = MMC_POWER_OFF;
1917 host->next_data.cookie = 1;
1918
1919 platform_set_drvdata(pdev, host);
1920 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
1921
1922 mmc->ops = &omap_hsmmc_ops;
1923
1924 /*
1925 * If regulator_disable can only put vcc_aux to sleep then there is
1926 * no off state.
1927 */
1928 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1929 mmc_slot(host).no_off = 1;
1930
1931 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1932 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1933
1934 spin_lock_init(&host->irq_lock);
1935
1936 host->fclk = clk_get(&pdev->dev, "fck");
1937 if (IS_ERR(host->fclk)) {
1938 ret = PTR_ERR(host->fclk);
1939 host->fclk = NULL;
1940 goto err1;
1941 }
1942
1943 omap_hsmmc_context_save(host);
1944
1945 mmc->caps |= MMC_CAP_DISABLE;
1946
1947 pm_runtime_enable(host->dev);
1948 pm_runtime_get_sync(host->dev);
1949 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1950 pm_runtime_use_autosuspend(host->dev);
1951
1952 if (cpu_is_omap2430()) {
1953 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1954 /*
1955 * MMC can still work without debounce clock.
1956 */
1957 if (IS_ERR(host->dbclk))
1958 dev_warn(mmc_dev(host->mmc),
1959 "Failed to get debounce clock\n");
1960 else
1961 host->got_dbclk = 1;
1962
1963 if (host->got_dbclk)
1964 if (clk_enable(host->dbclk) != 0)
1965 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1966 " clk failed\n");
1967 }
1968
1969 /* Since we do only SG emulation, we can have as many segs
1970 * as we want. */
1971 mmc->max_segs = 1024;
1972
1973 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1974 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1975 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1976 mmc->max_seg_size = mmc->max_req_size;
1977
1978 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1979 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1980
1981 mmc->caps |= mmc_slot(host).caps;
1982 if (mmc->caps & MMC_CAP_8_BIT_DATA)
1983 mmc->caps |= MMC_CAP_4_BIT_DATA;
1984
1985 if (mmc_slot(host).nonremovable)
1986 mmc->caps |= MMC_CAP_NONREMOVABLE;
1987
1988 omap_hsmmc_conf_bus_power(host);
1989
1990 /* Select DMA lines */
1991 switch (host->id) {
1992 case OMAP_MMC1_DEVID:
1993 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1994 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1995 break;
1996 case OMAP_MMC2_DEVID:
1997 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1998 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1999 break;
2000 case OMAP_MMC3_DEVID:
2001 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2002 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2003 break;
2004 case OMAP_MMC4_DEVID:
2005 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2006 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2007 break;
2008 case OMAP_MMC5_DEVID:
2009 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2010 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2011 break;
2012 default:
2013 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2014 goto err_irq;
2015 }
2016
2017 /* Request IRQ for MMC operations */
2018 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
2019 mmc_hostname(mmc), host);
2020 if (ret) {
2021 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2022 goto err_irq;
2023 }
2024
2025 if (pdata->init != NULL) {
2026 if (pdata->init(&pdev->dev) != 0) {
2027 dev_dbg(mmc_dev(host->mmc),
2028 "Unable to configure MMC IRQs\n");
2029 goto err_irq_cd_init;
2030 }
2031 }
2032
2033 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2034 ret = omap_hsmmc_reg_get(host);
2035 if (ret)
2036 goto err_reg;
2037 host->use_reg = 1;
2038 }
2039
2040 mmc->ocr_avail = mmc_slot(host).ocr_mask;
2041
2042 /* Request IRQ for card detect */
2043 if ((mmc_slot(host).card_detect_irq)) {
2044 ret = request_irq(mmc_slot(host).card_detect_irq,
2045 omap_hsmmc_cd_handler,
2046 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2047 | IRQF_DISABLED,
2048 mmc_hostname(mmc), host);
2049 if (ret) {
2050 dev_dbg(mmc_dev(host->mmc),
2051 "Unable to grab MMC CD IRQ\n");
2052 goto err_irq_cd;
2053 }
2054 pdata->suspend = omap_hsmmc_suspend_cdirq;
2055 pdata->resume = omap_hsmmc_resume_cdirq;
2056 }
2057
2058 omap_hsmmc_disable_irq(host);
2059
2060 omap_hsmmc_protect_card(host);
2061
2062 mmc_add_host(mmc);
2063
2064 if (mmc_slot(host).name != NULL) {
2065 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2066 if (ret < 0)
2067 goto err_slot_name;
2068 }
2069 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2070 ret = device_create_file(&mmc->class_dev,
2071 &dev_attr_cover_switch);
2072 if (ret < 0)
2073 goto err_slot_name;
2074 }
2075
2076 omap_hsmmc_debugfs(mmc);
2077 pm_runtime_mark_last_busy(host->dev);
2078 pm_runtime_put_autosuspend(host->dev);
2079
2080 return 0;
2081
2082err_slot_name:
2083 mmc_remove_host(mmc);
2084 free_irq(mmc_slot(host).card_detect_irq, host);
2085err_irq_cd:
2086 if (host->use_reg)
2087 omap_hsmmc_reg_put(host);
2088err_reg:
2089 if (host->pdata->cleanup)
2090 host->pdata->cleanup(&pdev->dev);
2091err_irq_cd_init:
2092 free_irq(host->irq, host);
2093err_irq:
2094 pm_runtime_mark_last_busy(host->dev);
2095 pm_runtime_put_autosuspend(host->dev);
2096 clk_put(host->fclk);
2097 if (host->got_dbclk) {
2098 clk_disable(host->dbclk);
2099 clk_put(host->dbclk);
2100 }
2101err1:
2102 iounmap(host->base);
2103 platform_set_drvdata(pdev, NULL);
2104 mmc_free_host(mmc);
2105err_alloc:
2106 omap_hsmmc_gpio_free(pdata);
2107err:
2108 release_mem_region(res->start, resource_size(res));
2109 return ret;
2110}
2111
2112static int omap_hsmmc_remove(struct platform_device *pdev)
2113{
2114 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2115 struct resource *res;
2116
2117 if (host) {
2118 pm_runtime_get_sync(host->dev);
2119 mmc_remove_host(host->mmc);
2120 if (host->use_reg)
2121 omap_hsmmc_reg_put(host);
2122 if (host->pdata->cleanup)
2123 host->pdata->cleanup(&pdev->dev);
2124 free_irq(host->irq, host);
2125 if (mmc_slot(host).card_detect_irq)
2126 free_irq(mmc_slot(host).card_detect_irq, host);
2127 flush_work_sync(&host->mmc_carddetect_work);
2128
2129 pm_runtime_put_sync(host->dev);
2130 pm_runtime_disable(host->dev);
2131 clk_put(host->fclk);
2132 if (host->got_dbclk) {
2133 clk_disable(host->dbclk);
2134 clk_put(host->dbclk);
2135 }
2136
2137 mmc_free_host(host->mmc);
2138 iounmap(host->base);
2139 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2140 }
2141
2142 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2143 if (res)
2144 release_mem_region(res->start, resource_size(res));
2145 platform_set_drvdata(pdev, NULL);
2146
2147 return 0;
2148}
2149
2150#ifdef CONFIG_PM
2151static int omap_hsmmc_suspend(struct device *dev)
2152{
2153 int ret = 0;
2154 struct platform_device *pdev = to_platform_device(dev);
2155 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2156
2157 if (host && host->suspended)
2158 return 0;
2159
2160 if (host) {
2161 pm_runtime_get_sync(host->dev);
2162 host->suspended = 1;
2163 if (host->pdata->suspend) {
2164 ret = host->pdata->suspend(&pdev->dev,
2165 host->slot_id);
2166 if (ret) {
2167 dev_dbg(mmc_dev(host->mmc),
2168 "Unable to handle MMC board"
2169 " level suspend\n");
2170 host->suspended = 0;
2171 return ret;
2172 }
2173 }
2174 cancel_work_sync(&host->mmc_carddetect_work);
2175 ret = mmc_suspend_host(host->mmc);
2176
2177 if (ret == 0) {
2178 omap_hsmmc_disable_irq(host);
2179 OMAP_HSMMC_WRITE(host->base, HCTL,
2180 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2181 if (host->got_dbclk)
2182 clk_disable(host->dbclk);
2183 } else {
2184 host->suspended = 0;
2185 if (host->pdata->resume) {
2186 ret = host->pdata->resume(&pdev->dev,
2187 host->slot_id);
2188 if (ret)
2189 dev_dbg(mmc_dev(host->mmc),
2190 "Unmask interrupt failed\n");
2191 }
2192 }
2193 pm_runtime_put_sync(host->dev);
2194 }
2195 return ret;
2196}
2197
2198/* Routine to resume the MMC device */
2199static int omap_hsmmc_resume(struct device *dev)
2200{
2201 int ret = 0;
2202 struct platform_device *pdev = to_platform_device(dev);
2203 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2204
2205 if (host && !host->suspended)
2206 return 0;
2207
2208 if (host) {
2209 pm_runtime_get_sync(host->dev);
2210
2211 if (host->got_dbclk)
2212 clk_enable(host->dbclk);
2213
2214 omap_hsmmc_conf_bus_power(host);
2215
2216 if (host->pdata->resume) {
2217 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2218 if (ret)
2219 dev_dbg(mmc_dev(host->mmc),
2220 "Unmask interrupt failed\n");
2221 }
2222
2223 omap_hsmmc_protect_card(host);
2224
2225 /* Notify the core to resume the host */
2226 ret = mmc_resume_host(host->mmc);
2227 if (ret == 0)
2228 host->suspended = 0;
2229
2230 pm_runtime_mark_last_busy(host->dev);
2231 pm_runtime_put_autosuspend(host->dev);
2232 }
2233
2234 return ret;
2235
2236}
2237
2238#else
2239#define omap_hsmmc_suspend NULL
2240#define omap_hsmmc_resume NULL
2241#endif
2242
2243static int omap_hsmmc_runtime_suspend(struct device *dev)
2244{
2245 struct omap_hsmmc_host *host;
2246
2247 host = platform_get_drvdata(to_platform_device(dev));
2248 omap_hsmmc_context_save(host);
2249 dev_dbg(mmc_dev(host->mmc), "disabled\n");
2250
2251 return 0;
2252}
2253
2254static int omap_hsmmc_runtime_resume(struct device *dev)
2255{
2256 struct omap_hsmmc_host *host;
2257
2258 host = platform_get_drvdata(to_platform_device(dev));
2259 omap_hsmmc_context_restore(host);
2260 dev_dbg(mmc_dev(host->mmc), "enabled\n");
2261
2262 return 0;
2263}
2264
2265static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2266 .suspend = omap_hsmmc_suspend,
2267 .resume = omap_hsmmc_resume,
2268 .runtime_suspend = omap_hsmmc_runtime_suspend,
2269 .runtime_resume = omap_hsmmc_runtime_resume,
2270};
2271
2272static struct platform_driver omap_hsmmc_driver = {
2273 .remove = omap_hsmmc_remove,
2274 .driver = {
2275 .name = DRIVER_NAME,
2276 .owner = THIS_MODULE,
2277 .pm = &omap_hsmmc_dev_pm_ops,
2278 },
2279};
2280
2281static int __init omap_hsmmc_init(void)
2282{
2283 /* Register the MMC driver */
2284 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2285}
2286
2287static void __exit omap_hsmmc_cleanup(void)
2288{
2289 /* Unregister MMC driver */
2290 platform_driver_unregister(&omap_hsmmc_driver);
2291}
2292
2293module_init(omap_hsmmc_init);
2294module_exit(omap_hsmmc_cleanup);
2295
2296MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2297MODULE_LICENSE("GPL");
2298MODULE_ALIAS("platform:" DRIVER_NAME);
2299MODULE_AUTHOR("Texas Instruments Inc");
1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/debugfs.h>
22#include <linux/dmaengine.h>
23#include <linux/seq_file.h>
24#include <linux/sizes.h>
25#include <linux/interrupt.h>
26#include <linux/delay.h>
27#include <linux/dma-mapping.h>
28#include <linux/platform_device.h>
29#include <linux/timer.h>
30#include <linux/clk.h>
31#include <linux/of.h>
32#include <linux/of_irq.h>
33#include <linux/of_device.h>
34#include <linux/mmc/host.h>
35#include <linux/mmc/core.h>
36#include <linux/mmc/mmc.h>
37#include <linux/mmc/slot-gpio.h>
38#include <linux/io.h>
39#include <linux/irq.h>
40#include <linux/regulator/consumer.h>
41#include <linux/pinctrl/consumer.h>
42#include <linux/pm_runtime.h>
43#include <linux/pm_wakeirq.h>
44#include <linux/platform_data/hsmmc-omap.h>
45
46/* OMAP HSMMC Host Controller Registers */
47#define OMAP_HSMMC_SYSSTATUS 0x0014
48#define OMAP_HSMMC_CON 0x002C
49#define OMAP_HSMMC_SDMASA 0x0100
50#define OMAP_HSMMC_BLK 0x0104
51#define OMAP_HSMMC_ARG 0x0108
52#define OMAP_HSMMC_CMD 0x010C
53#define OMAP_HSMMC_RSP10 0x0110
54#define OMAP_HSMMC_RSP32 0x0114
55#define OMAP_HSMMC_RSP54 0x0118
56#define OMAP_HSMMC_RSP76 0x011C
57#define OMAP_HSMMC_DATA 0x0120
58#define OMAP_HSMMC_PSTATE 0x0124
59#define OMAP_HSMMC_HCTL 0x0128
60#define OMAP_HSMMC_SYSCTL 0x012C
61#define OMAP_HSMMC_STAT 0x0130
62#define OMAP_HSMMC_IE 0x0134
63#define OMAP_HSMMC_ISE 0x0138
64#define OMAP_HSMMC_AC12 0x013C
65#define OMAP_HSMMC_CAPA 0x0140
66
67#define VS18 (1 << 26)
68#define VS30 (1 << 25)
69#define HSS (1 << 21)
70#define SDVS18 (0x5 << 9)
71#define SDVS30 (0x6 << 9)
72#define SDVS33 (0x7 << 9)
73#define SDVS_MASK 0x00000E00
74#define SDVSCLR 0xFFFFF1FF
75#define SDVSDET 0x00000400
76#define AUTOIDLE 0x1
77#define SDBP (1 << 8)
78#define DTO 0xe
79#define ICE 0x1
80#define ICS 0x2
81#define CEN (1 << 2)
82#define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
83#define CLKD_MASK 0x0000FFC0
84#define CLKD_SHIFT 6
85#define DTO_MASK 0x000F0000
86#define DTO_SHIFT 16
87#define INIT_STREAM (1 << 1)
88#define ACEN_ACMD23 (2 << 2)
89#define DP_SELECT (1 << 21)
90#define DDIR (1 << 4)
91#define DMAE 0x1
92#define MSBS (1 << 5)
93#define BCE (1 << 1)
94#define FOUR_BIT (1 << 1)
95#define HSPE (1 << 2)
96#define IWE (1 << 24)
97#define DDR (1 << 19)
98#define CLKEXTFREE (1 << 16)
99#define CTPL (1 << 11)
100#define DW8 (1 << 5)
101#define OD 0x1
102#define STAT_CLEAR 0xFFFFFFFF
103#define INIT_STREAM_CMD 0x00000000
104#define DUAL_VOLT_OCR_BIT 7
105#define SRC (1 << 25)
106#define SRD (1 << 26)
107#define SOFTRESET (1 << 1)
108
109/* PSTATE */
110#define DLEV_DAT(x) (1 << (20 + (x)))
111
112/* Interrupt masks for IE and ISE register */
113#define CC_EN (1 << 0)
114#define TC_EN (1 << 1)
115#define BWR_EN (1 << 4)
116#define BRR_EN (1 << 5)
117#define CIRQ_EN (1 << 8)
118#define ERR_EN (1 << 15)
119#define CTO_EN (1 << 16)
120#define CCRC_EN (1 << 17)
121#define CEB_EN (1 << 18)
122#define CIE_EN (1 << 19)
123#define DTO_EN (1 << 20)
124#define DCRC_EN (1 << 21)
125#define DEB_EN (1 << 22)
126#define ACE_EN (1 << 24)
127#define CERR_EN (1 << 28)
128#define BADA_EN (1 << 29)
129
130#define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
131 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
132 BRR_EN | BWR_EN | TC_EN | CC_EN)
133
134#define CNI (1 << 7)
135#define ACIE (1 << 4)
136#define ACEB (1 << 3)
137#define ACCE (1 << 2)
138#define ACTO (1 << 1)
139#define ACNE (1 << 0)
140
141#define MMC_AUTOSUSPEND_DELAY 100
142#define MMC_TIMEOUT_MS 20 /* 20 mSec */
143#define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
144#define OMAP_MMC_MIN_CLOCK 400000
145#define OMAP_MMC_MAX_CLOCK 52000000
146#define DRIVER_NAME "omap_hsmmc"
147
148/*
149 * One controller can have multiple slots, like on some omap boards using
150 * omap.c controller driver. Luckily this is not currently done on any known
151 * omap_hsmmc.c device.
152 */
153#define mmc_pdata(host) host->pdata
154
155/*
156 * MMC Host controller read/write API's
157 */
158#define OMAP_HSMMC_READ(base, reg) \
159 __raw_readl((base) + OMAP_HSMMC_##reg)
160
161#define OMAP_HSMMC_WRITE(base, reg, val) \
162 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
163
164struct omap_hsmmc_next {
165 unsigned int dma_len;
166 s32 cookie;
167};
168
169struct omap_hsmmc_host {
170 struct device *dev;
171 struct mmc_host *mmc;
172 struct mmc_request *mrq;
173 struct mmc_command *cmd;
174 struct mmc_data *data;
175 struct clk *fclk;
176 struct clk *dbclk;
177 struct regulator *pbias;
178 bool pbias_enabled;
179 void __iomem *base;
180 bool vqmmc_enabled;
181 resource_size_t mapbase;
182 spinlock_t irq_lock; /* Prevent races with irq handler */
183 unsigned int dma_len;
184 unsigned int dma_sg_idx;
185 unsigned char bus_mode;
186 unsigned char power_mode;
187 int suspended;
188 u32 con;
189 u32 hctl;
190 u32 sysctl;
191 u32 capa;
192 int irq;
193 int wake_irq;
194 int use_dma, dma_ch;
195 struct dma_chan *tx_chan;
196 struct dma_chan *rx_chan;
197 int response_busy;
198 int context_loss;
199 int reqs_blocked;
200 int req_in_progress;
201 unsigned long clk_rate;
202 unsigned int flags;
203#define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
204#define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
205 struct omap_hsmmc_next next_data;
206 struct omap_hsmmc_platform_data *pdata;
207};
208
209struct omap_mmc_of_data {
210 u32 reg_offset;
211 u8 controller_flags;
212};
213
214static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
215
216static int omap_hsmmc_enable_supply(struct mmc_host *mmc)
217{
218 int ret;
219 struct omap_hsmmc_host *host = mmc_priv(mmc);
220 struct mmc_ios *ios = &mmc->ios;
221
222 if (!IS_ERR(mmc->supply.vmmc)) {
223 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
224 if (ret)
225 return ret;
226 }
227
228 /* Enable interface voltage rail, if needed */
229 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
230 ret = regulator_enable(mmc->supply.vqmmc);
231 if (ret) {
232 dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n");
233 goto err_vqmmc;
234 }
235 host->vqmmc_enabled = true;
236 }
237
238 return 0;
239
240err_vqmmc:
241 if (!IS_ERR(mmc->supply.vmmc))
242 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
243
244 return ret;
245}
246
247static int omap_hsmmc_disable_supply(struct mmc_host *mmc)
248{
249 int ret;
250 int status;
251 struct omap_hsmmc_host *host = mmc_priv(mmc);
252
253 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
254 ret = regulator_disable(mmc->supply.vqmmc);
255 if (ret) {
256 dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n");
257 return ret;
258 }
259 host->vqmmc_enabled = false;
260 }
261
262 if (!IS_ERR(mmc->supply.vmmc)) {
263 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
264 if (ret)
265 goto err_set_ocr;
266 }
267
268 return 0;
269
270err_set_ocr:
271 if (!IS_ERR(mmc->supply.vqmmc)) {
272 status = regulator_enable(mmc->supply.vqmmc);
273 if (status)
274 dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n");
275 }
276
277 return ret;
278}
279
280static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on)
281{
282 int ret;
283
284 if (IS_ERR(host->pbias))
285 return 0;
286
287 if (power_on) {
288 if (!host->pbias_enabled) {
289 ret = regulator_enable(host->pbias);
290 if (ret) {
291 dev_err(host->dev, "pbias reg enable fail\n");
292 return ret;
293 }
294 host->pbias_enabled = true;
295 }
296 } else {
297 if (host->pbias_enabled) {
298 ret = regulator_disable(host->pbias);
299 if (ret) {
300 dev_err(host->dev, "pbias reg disable fail\n");
301 return ret;
302 }
303 host->pbias_enabled = false;
304 }
305 }
306
307 return 0;
308}
309
310static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on)
311{
312 struct mmc_host *mmc = host->mmc;
313 int ret = 0;
314
315 /*
316 * If we don't see a Vcc regulator, assume it's a fixed
317 * voltage always-on regulator.
318 */
319 if (IS_ERR(mmc->supply.vmmc))
320 return 0;
321
322 ret = omap_hsmmc_set_pbias(host, false);
323 if (ret)
324 return ret;
325
326 /*
327 * Assume Vcc regulator is used only to power the card ... OMAP
328 * VDDS is used to power the pins, optionally with a transceiver to
329 * support cards using voltages other than VDDS (1.8V nominal). When a
330 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
331 *
332 * In some cases this regulator won't support enable/disable;
333 * e.g. it's a fixed rail for a WLAN chip.
334 *
335 * In other cases vcc_aux switches interface power. Example, for
336 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
337 * chips/cards need an interface voltage rail too.
338 */
339 if (power_on) {
340 ret = omap_hsmmc_enable_supply(mmc);
341 if (ret)
342 return ret;
343
344 ret = omap_hsmmc_set_pbias(host, true);
345 if (ret)
346 goto err_set_voltage;
347 } else {
348 ret = omap_hsmmc_disable_supply(mmc);
349 if (ret)
350 return ret;
351 }
352
353 return 0;
354
355err_set_voltage:
356 omap_hsmmc_disable_supply(mmc);
357
358 return ret;
359}
360
361static int omap_hsmmc_disable_boot_regulator(struct regulator *reg)
362{
363 int ret;
364
365 if (IS_ERR(reg))
366 return 0;
367
368 if (regulator_is_enabled(reg)) {
369 ret = regulator_enable(reg);
370 if (ret)
371 return ret;
372
373 ret = regulator_disable(reg);
374 if (ret)
375 return ret;
376 }
377
378 return 0;
379}
380
381static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
382{
383 struct mmc_host *mmc = host->mmc;
384 int ret;
385
386 /*
387 * disable regulators enabled during boot and get the usecount
388 * right so that regulators can be enabled/disabled by checking
389 * the return value of regulator_is_enabled
390 */
391 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc);
392 if (ret) {
393 dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
394 return ret;
395 }
396
397 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc);
398 if (ret) {
399 dev_err(host->dev,
400 "fail to disable boot enabled vmmc_aux reg\n");
401 return ret;
402 }
403
404 ret = omap_hsmmc_disable_boot_regulator(host->pbias);
405 if (ret) {
406 dev_err(host->dev,
407 "failed to disable boot enabled pbias reg\n");
408 return ret;
409 }
410
411 return 0;
412}
413
414static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
415{
416 int ret;
417 struct mmc_host *mmc = host->mmc;
418
419
420 ret = mmc_regulator_get_supply(mmc);
421 if (ret)
422 return ret;
423
424 /* Allow an aux regulator */
425 if (IS_ERR(mmc->supply.vqmmc)) {
426 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev,
427 "vmmc_aux");
428 if (IS_ERR(mmc->supply.vqmmc)) {
429 ret = PTR_ERR(mmc->supply.vqmmc);
430 if ((ret != -ENODEV) && host->dev->of_node)
431 return ret;
432 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
433 PTR_ERR(mmc->supply.vqmmc));
434 }
435 }
436
437 host->pbias = devm_regulator_get_optional(host->dev, "pbias");
438 if (IS_ERR(host->pbias)) {
439 ret = PTR_ERR(host->pbias);
440 if ((ret != -ENODEV) && host->dev->of_node) {
441 dev_err(host->dev,
442 "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n");
443 return ret;
444 }
445 dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
446 PTR_ERR(host->pbias));
447 }
448
449 /* For eMMC do not power off when not in sleep state */
450 if (mmc_pdata(host)->no_regulator_off_init)
451 return 0;
452
453 ret = omap_hsmmc_disable_boot_regulators(host);
454 if (ret)
455 return ret;
456
457 return 0;
458}
459
460/*
461 * Start clock to the card
462 */
463static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
464{
465 OMAP_HSMMC_WRITE(host->base, SYSCTL,
466 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
467}
468
469/*
470 * Stop clock to the card
471 */
472static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
473{
474 OMAP_HSMMC_WRITE(host->base, SYSCTL,
475 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
476 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
477 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
478}
479
480static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
481 struct mmc_command *cmd)
482{
483 u32 irq_mask = INT_EN_MASK;
484 unsigned long flags;
485
486 if (host->use_dma)
487 irq_mask &= ~(BRR_EN | BWR_EN);
488
489 /* Disable timeout for erases */
490 if (cmd->opcode == MMC_ERASE)
491 irq_mask &= ~DTO_EN;
492
493 spin_lock_irqsave(&host->irq_lock, flags);
494 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
495 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
496
497 /* latch pending CIRQ, but don't signal MMC core */
498 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
499 irq_mask |= CIRQ_EN;
500 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
501 spin_unlock_irqrestore(&host->irq_lock, flags);
502}
503
504static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
505{
506 u32 irq_mask = 0;
507 unsigned long flags;
508
509 spin_lock_irqsave(&host->irq_lock, flags);
510 /* no transfer running but need to keep cirq if enabled */
511 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
512 irq_mask |= CIRQ_EN;
513 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
514 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
515 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
516 spin_unlock_irqrestore(&host->irq_lock, flags);
517}
518
519/* Calculate divisor for the given clock frequency */
520static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
521{
522 u16 dsor = 0;
523
524 if (ios->clock) {
525 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
526 if (dsor > CLKD_MAX)
527 dsor = CLKD_MAX;
528 }
529
530 return dsor;
531}
532
533static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
534{
535 struct mmc_ios *ios = &host->mmc->ios;
536 unsigned long regval;
537 unsigned long timeout;
538 unsigned long clkdiv;
539
540 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
541
542 omap_hsmmc_stop_clock(host);
543
544 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
545 regval = regval & ~(CLKD_MASK | DTO_MASK);
546 clkdiv = calc_divisor(host, ios);
547 regval = regval | (clkdiv << 6) | (DTO << 16);
548 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
549 OMAP_HSMMC_WRITE(host->base, SYSCTL,
550 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
551
552 /* Wait till the ICS bit is set */
553 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
554 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
555 && time_before(jiffies, timeout))
556 cpu_relax();
557
558 /*
559 * Enable High-Speed Support
560 * Pre-Requisites
561 * - Controller should support High-Speed-Enable Bit
562 * - Controller should not be using DDR Mode
563 * - Controller should advertise that it supports High Speed
564 * in capabilities register
565 * - MMC/SD clock coming out of controller > 25MHz
566 */
567 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
568 (ios->timing != MMC_TIMING_MMC_DDR52) &&
569 (ios->timing != MMC_TIMING_UHS_DDR50) &&
570 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
571 regval = OMAP_HSMMC_READ(host->base, HCTL);
572 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
573 regval |= HSPE;
574 else
575 regval &= ~HSPE;
576
577 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
578 }
579
580 omap_hsmmc_start_clock(host);
581}
582
583static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
584{
585 struct mmc_ios *ios = &host->mmc->ios;
586 u32 con;
587
588 con = OMAP_HSMMC_READ(host->base, CON);
589 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
590 ios->timing == MMC_TIMING_UHS_DDR50)
591 con |= DDR; /* configure in DDR mode */
592 else
593 con &= ~DDR;
594 switch (ios->bus_width) {
595 case MMC_BUS_WIDTH_8:
596 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
597 break;
598 case MMC_BUS_WIDTH_4:
599 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
600 OMAP_HSMMC_WRITE(host->base, HCTL,
601 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
602 break;
603 case MMC_BUS_WIDTH_1:
604 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
605 OMAP_HSMMC_WRITE(host->base, HCTL,
606 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
607 break;
608 }
609}
610
611static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
612{
613 struct mmc_ios *ios = &host->mmc->ios;
614 u32 con;
615
616 con = OMAP_HSMMC_READ(host->base, CON);
617 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
618 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
619 else
620 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
621}
622
623#ifdef CONFIG_PM
624
625/*
626 * Restore the MMC host context, if it was lost as result of a
627 * power state change.
628 */
629static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
630{
631 struct mmc_ios *ios = &host->mmc->ios;
632 u32 hctl, capa;
633 unsigned long timeout;
634
635 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
636 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
637 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
638 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
639 return 0;
640
641 host->context_loss++;
642
643 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
644 if (host->power_mode != MMC_POWER_OFF &&
645 (1 << ios->vdd) <= MMC_VDD_23_24)
646 hctl = SDVS18;
647 else
648 hctl = SDVS30;
649 capa = VS30 | VS18;
650 } else {
651 hctl = SDVS18;
652 capa = VS18;
653 }
654
655 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
656 hctl |= IWE;
657
658 OMAP_HSMMC_WRITE(host->base, HCTL,
659 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
660
661 OMAP_HSMMC_WRITE(host->base, CAPA,
662 OMAP_HSMMC_READ(host->base, CAPA) | capa);
663
664 OMAP_HSMMC_WRITE(host->base, HCTL,
665 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
666
667 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
668 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
669 && time_before(jiffies, timeout))
670 ;
671
672 OMAP_HSMMC_WRITE(host->base, ISE, 0);
673 OMAP_HSMMC_WRITE(host->base, IE, 0);
674 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
675
676 /* Do not initialize card-specific things if the power is off */
677 if (host->power_mode == MMC_POWER_OFF)
678 goto out;
679
680 omap_hsmmc_set_bus_width(host);
681
682 omap_hsmmc_set_clock(host);
683
684 omap_hsmmc_set_bus_mode(host);
685
686out:
687 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
688 host->context_loss);
689 return 0;
690}
691
692/*
693 * Save the MMC host context (store the number of power state changes so far).
694 */
695static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
696{
697 host->con = OMAP_HSMMC_READ(host->base, CON);
698 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
699 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
700 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
701}
702
703#else
704
705static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
706{
707}
708
709#endif
710
711/*
712 * Send init stream sequence to card
713 * before sending IDLE command
714 */
715static void send_init_stream(struct omap_hsmmc_host *host)
716{
717 int reg = 0;
718 unsigned long timeout;
719
720 disable_irq(host->irq);
721
722 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
723 OMAP_HSMMC_WRITE(host->base, CON,
724 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
725 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
726
727 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
728 while ((reg != CC_EN) && time_before(jiffies, timeout))
729 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
730
731 OMAP_HSMMC_WRITE(host->base, CON,
732 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
733
734 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
735 OMAP_HSMMC_READ(host->base, STAT);
736
737 enable_irq(host->irq);
738}
739
740static ssize_t
741omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
742 char *buf)
743{
744 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
745 struct omap_hsmmc_host *host = mmc_priv(mmc);
746
747 return sprintf(buf, "%s\n", mmc_pdata(host)->name);
748}
749
750static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
751
752/*
753 * Configure the response type and send the cmd.
754 */
755static void
756omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
757 struct mmc_data *data)
758{
759 int cmdreg = 0, resptype = 0, cmdtype = 0;
760
761 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
762 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
763 host->cmd = cmd;
764
765 omap_hsmmc_enable_irq(host, cmd);
766
767 host->response_busy = 0;
768 if (cmd->flags & MMC_RSP_PRESENT) {
769 if (cmd->flags & MMC_RSP_136)
770 resptype = 1;
771 else if (cmd->flags & MMC_RSP_BUSY) {
772 resptype = 3;
773 host->response_busy = 1;
774 } else
775 resptype = 2;
776 }
777
778 /*
779 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
780 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
781 * a val of 0x3, rest 0x0.
782 */
783 if (cmd == host->mrq->stop)
784 cmdtype = 0x3;
785
786 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
787
788 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
789 host->mrq->sbc) {
790 cmdreg |= ACEN_ACMD23;
791 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
792 }
793 if (data) {
794 cmdreg |= DP_SELECT | MSBS | BCE;
795 if (data->flags & MMC_DATA_READ)
796 cmdreg |= DDIR;
797 else
798 cmdreg &= ~(DDIR);
799 }
800
801 if (host->use_dma)
802 cmdreg |= DMAE;
803
804 host->req_in_progress = 1;
805
806 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
807 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
808}
809
810static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
811 struct mmc_data *data)
812{
813 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
814}
815
816static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
817{
818 int dma_ch;
819 unsigned long flags;
820
821 spin_lock_irqsave(&host->irq_lock, flags);
822 host->req_in_progress = 0;
823 dma_ch = host->dma_ch;
824 spin_unlock_irqrestore(&host->irq_lock, flags);
825
826 omap_hsmmc_disable_irq(host);
827 /* Do not complete the request if DMA is still in progress */
828 if (mrq->data && host->use_dma && dma_ch != -1)
829 return;
830 host->mrq = NULL;
831 mmc_request_done(host->mmc, mrq);
832}
833
834/*
835 * Notify the transfer complete to MMC core
836 */
837static void
838omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
839{
840 if (!data) {
841 struct mmc_request *mrq = host->mrq;
842
843 /* TC before CC from CMD6 - don't know why, but it happens */
844 if (host->cmd && host->cmd->opcode == 6 &&
845 host->response_busy) {
846 host->response_busy = 0;
847 return;
848 }
849
850 omap_hsmmc_request_done(host, mrq);
851 return;
852 }
853
854 host->data = NULL;
855
856 if (!data->error)
857 data->bytes_xfered += data->blocks * (data->blksz);
858 else
859 data->bytes_xfered = 0;
860
861 if (data->stop && (data->error || !host->mrq->sbc))
862 omap_hsmmc_start_command(host, data->stop, NULL);
863 else
864 omap_hsmmc_request_done(host, data->mrq);
865}
866
867/*
868 * Notify the core about command completion
869 */
870static void
871omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
872{
873 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
874 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
875 host->cmd = NULL;
876 omap_hsmmc_start_dma_transfer(host);
877 omap_hsmmc_start_command(host, host->mrq->cmd,
878 host->mrq->data);
879 return;
880 }
881
882 host->cmd = NULL;
883
884 if (cmd->flags & MMC_RSP_PRESENT) {
885 if (cmd->flags & MMC_RSP_136) {
886 /* response type 2 */
887 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
888 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
889 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
890 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
891 } else {
892 /* response types 1, 1b, 3, 4, 5, 6 */
893 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
894 }
895 }
896 if ((host->data == NULL && !host->response_busy) || cmd->error)
897 omap_hsmmc_request_done(host, host->mrq);
898}
899
900/*
901 * DMA clean up for command errors
902 */
903static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
904{
905 int dma_ch;
906 unsigned long flags;
907
908 host->data->error = errno;
909
910 spin_lock_irqsave(&host->irq_lock, flags);
911 dma_ch = host->dma_ch;
912 host->dma_ch = -1;
913 spin_unlock_irqrestore(&host->irq_lock, flags);
914
915 if (host->use_dma && dma_ch != -1) {
916 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
917
918 dmaengine_terminate_all(chan);
919 dma_unmap_sg(chan->device->dev,
920 host->data->sg, host->data->sg_len,
921 mmc_get_dma_dir(host->data));
922
923 host->data->host_cookie = 0;
924 }
925 host->data = NULL;
926}
927
928/*
929 * Readable error output
930 */
931#ifdef CONFIG_MMC_DEBUG
932static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
933{
934 /* --- means reserved bit without definition at documentation */
935 static const char *omap_hsmmc_status_bits[] = {
936 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
937 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
938 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
939 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
940 };
941 char res[256];
942 char *buf = res;
943 int len, i;
944
945 len = sprintf(buf, "MMC IRQ 0x%x :", status);
946 buf += len;
947
948 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
949 if (status & (1 << i)) {
950 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
951 buf += len;
952 }
953
954 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
955}
956#else
957static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
958 u32 status)
959{
960}
961#endif /* CONFIG_MMC_DEBUG */
962
963/*
964 * MMC controller internal state machines reset
965 *
966 * Used to reset command or data internal state machines, using respectively
967 * SRC or SRD bit of SYSCTL register
968 * Can be called from interrupt context
969 */
970static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
971 unsigned long bit)
972{
973 unsigned long i = 0;
974 unsigned long limit = MMC_TIMEOUT_US;
975
976 OMAP_HSMMC_WRITE(host->base, SYSCTL,
977 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
978
979 /*
980 * OMAP4 ES2 and greater has an updated reset logic.
981 * Monitor a 0->1 transition first
982 */
983 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
984 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
985 && (i++ < limit))
986 udelay(1);
987 }
988 i = 0;
989
990 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
991 (i++ < limit))
992 udelay(1);
993
994 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
995 dev_err(mmc_dev(host->mmc),
996 "Timeout waiting on controller reset in %s\n",
997 __func__);
998}
999
1000static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1001 int err, int end_cmd)
1002{
1003 if (end_cmd) {
1004 omap_hsmmc_reset_controller_fsm(host, SRC);
1005 if (host->cmd)
1006 host->cmd->error = err;
1007 }
1008
1009 if (host->data) {
1010 omap_hsmmc_reset_controller_fsm(host, SRD);
1011 omap_hsmmc_dma_cleanup(host, err);
1012 } else if (host->mrq && host->mrq->cmd)
1013 host->mrq->cmd->error = err;
1014}
1015
1016static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1017{
1018 struct mmc_data *data;
1019 int end_cmd = 0, end_trans = 0;
1020 int error = 0;
1021
1022 data = host->data;
1023 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1024
1025 if (status & ERR_EN) {
1026 omap_hsmmc_dbg_report_irq(host, status);
1027
1028 if (status & (CTO_EN | CCRC_EN | CEB_EN))
1029 end_cmd = 1;
1030 if (host->data || host->response_busy) {
1031 end_trans = !end_cmd;
1032 host->response_busy = 0;
1033 }
1034 if (status & (CTO_EN | DTO_EN))
1035 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
1036 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
1037 BADA_EN))
1038 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
1039
1040 if (status & ACE_EN) {
1041 u32 ac12;
1042 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1043 if (!(ac12 & ACNE) && host->mrq->sbc) {
1044 end_cmd = 1;
1045 if (ac12 & ACTO)
1046 error = -ETIMEDOUT;
1047 else if (ac12 & (ACCE | ACEB | ACIE))
1048 error = -EILSEQ;
1049 host->mrq->sbc->error = error;
1050 hsmmc_command_incomplete(host, error, end_cmd);
1051 }
1052 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1053 }
1054 }
1055
1056 OMAP_HSMMC_WRITE(host->base, STAT, status);
1057 if (end_cmd || ((status & CC_EN) && host->cmd))
1058 omap_hsmmc_cmd_done(host, host->cmd);
1059 if ((end_trans || (status & TC_EN)) && host->mrq)
1060 omap_hsmmc_xfer_done(host, data);
1061}
1062
1063/*
1064 * MMC controller IRQ handler
1065 */
1066static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1067{
1068 struct omap_hsmmc_host *host = dev_id;
1069 int status;
1070
1071 status = OMAP_HSMMC_READ(host->base, STAT);
1072 while (status & (INT_EN_MASK | CIRQ_EN)) {
1073 if (host->req_in_progress)
1074 omap_hsmmc_do_irq(host, status);
1075
1076 if (status & CIRQ_EN)
1077 mmc_signal_sdio_irq(host->mmc);
1078
1079 /* Flush posted write */
1080 status = OMAP_HSMMC_READ(host->base, STAT);
1081 }
1082
1083 return IRQ_HANDLED;
1084}
1085
1086static void set_sd_bus_power(struct omap_hsmmc_host *host)
1087{
1088 unsigned long i;
1089
1090 OMAP_HSMMC_WRITE(host->base, HCTL,
1091 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1092 for (i = 0; i < loops_per_jiffy; i++) {
1093 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1094 break;
1095 cpu_relax();
1096 }
1097}
1098
1099/*
1100 * Switch MMC interface voltage ... only relevant for MMC1.
1101 *
1102 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1103 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1104 * Some chips, like eMMC ones, use internal transceivers.
1105 */
1106static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1107{
1108 u32 reg_val = 0;
1109 int ret;
1110
1111 /* Disable the clocks */
1112 clk_disable_unprepare(host->dbclk);
1113
1114 /* Turn the power off */
1115 ret = omap_hsmmc_set_power(host, 0);
1116
1117 /* Turn the power ON with given VDD 1.8 or 3.0v */
1118 if (!ret)
1119 ret = omap_hsmmc_set_power(host, 1);
1120 clk_prepare_enable(host->dbclk);
1121
1122 if (ret != 0)
1123 goto err;
1124
1125 OMAP_HSMMC_WRITE(host->base, HCTL,
1126 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1127 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1128
1129 /*
1130 * If a MMC dual voltage card is detected, the set_ios fn calls
1131 * this fn with VDD bit set for 1.8V. Upon card removal from the
1132 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1133 *
1134 * Cope with a bit of slop in the range ... per data sheets:
1135 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1136 * but recommended values are 1.71V to 1.89V
1137 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1138 * but recommended values are 2.7V to 3.3V
1139 *
1140 * Board setup code shouldn't permit anything very out-of-range.
1141 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1142 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1143 */
1144 if ((1 << vdd) <= MMC_VDD_23_24)
1145 reg_val |= SDVS18;
1146 else
1147 reg_val |= SDVS30;
1148
1149 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1150 set_sd_bus_power(host);
1151
1152 return 0;
1153err:
1154 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1155 return ret;
1156}
1157
1158static void omap_hsmmc_dma_callback(void *param)
1159{
1160 struct omap_hsmmc_host *host = param;
1161 struct dma_chan *chan;
1162 struct mmc_data *data;
1163 int req_in_progress;
1164
1165 spin_lock_irq(&host->irq_lock);
1166 if (host->dma_ch < 0) {
1167 spin_unlock_irq(&host->irq_lock);
1168 return;
1169 }
1170
1171 data = host->mrq->data;
1172 chan = omap_hsmmc_get_dma_chan(host, data);
1173 if (!data->host_cookie)
1174 dma_unmap_sg(chan->device->dev,
1175 data->sg, data->sg_len,
1176 mmc_get_dma_dir(data));
1177
1178 req_in_progress = host->req_in_progress;
1179 host->dma_ch = -1;
1180 spin_unlock_irq(&host->irq_lock);
1181
1182 /* If DMA has finished after TC, complete the request */
1183 if (!req_in_progress) {
1184 struct mmc_request *mrq = host->mrq;
1185
1186 host->mrq = NULL;
1187 mmc_request_done(host->mmc, mrq);
1188 }
1189}
1190
1191static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1192 struct mmc_data *data,
1193 struct omap_hsmmc_next *next,
1194 struct dma_chan *chan)
1195{
1196 int dma_len;
1197
1198 if (!next && data->host_cookie &&
1199 data->host_cookie != host->next_data.cookie) {
1200 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1201 " host->next_data.cookie %d\n",
1202 __func__, data->host_cookie, host->next_data.cookie);
1203 data->host_cookie = 0;
1204 }
1205
1206 /* Check if next job is already prepared */
1207 if (next || data->host_cookie != host->next_data.cookie) {
1208 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1209 mmc_get_dma_dir(data));
1210
1211 } else {
1212 dma_len = host->next_data.dma_len;
1213 host->next_data.dma_len = 0;
1214 }
1215
1216
1217 if (dma_len == 0)
1218 return -EINVAL;
1219
1220 if (next) {
1221 next->dma_len = dma_len;
1222 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1223 } else
1224 host->dma_len = dma_len;
1225
1226 return 0;
1227}
1228
1229/*
1230 * Routine to configure and start DMA for the MMC card
1231 */
1232static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
1233 struct mmc_request *req)
1234{
1235 struct dma_async_tx_descriptor *tx;
1236 int ret = 0, i;
1237 struct mmc_data *data = req->data;
1238 struct dma_chan *chan;
1239 struct dma_slave_config cfg = {
1240 .src_addr = host->mapbase + OMAP_HSMMC_DATA,
1241 .dst_addr = host->mapbase + OMAP_HSMMC_DATA,
1242 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1243 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1244 .src_maxburst = data->blksz / 4,
1245 .dst_maxburst = data->blksz / 4,
1246 };
1247
1248 /* Sanity check: all the SG entries must be aligned by block size. */
1249 for (i = 0; i < data->sg_len; i++) {
1250 struct scatterlist *sgl;
1251
1252 sgl = data->sg + i;
1253 if (sgl->length % data->blksz)
1254 return -EINVAL;
1255 }
1256 if ((data->blksz % 4) != 0)
1257 /* REVISIT: The MMC buffer increments only when MSB is written.
1258 * Return error for blksz which is non multiple of four.
1259 */
1260 return -EINVAL;
1261
1262 BUG_ON(host->dma_ch != -1);
1263
1264 chan = omap_hsmmc_get_dma_chan(host, data);
1265
1266 ret = dmaengine_slave_config(chan, &cfg);
1267 if (ret)
1268 return ret;
1269
1270 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1271 if (ret)
1272 return ret;
1273
1274 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1275 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1276 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1277 if (!tx) {
1278 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1279 /* FIXME: cleanup */
1280 return -1;
1281 }
1282
1283 tx->callback = omap_hsmmc_dma_callback;
1284 tx->callback_param = host;
1285
1286 /* Does not fail */
1287 dmaengine_submit(tx);
1288
1289 host->dma_ch = 1;
1290
1291 return 0;
1292}
1293
1294static void set_data_timeout(struct omap_hsmmc_host *host,
1295 unsigned long long timeout_ns,
1296 unsigned int timeout_clks)
1297{
1298 unsigned long long timeout = timeout_ns;
1299 unsigned int cycle_ns;
1300 uint32_t reg, clkd, dto = 0;
1301
1302 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1303 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1304 if (clkd == 0)
1305 clkd = 1;
1306
1307 cycle_ns = 1000000000 / (host->clk_rate / clkd);
1308 do_div(timeout, cycle_ns);
1309 timeout += timeout_clks;
1310 if (timeout) {
1311 while ((timeout & 0x80000000) == 0) {
1312 dto += 1;
1313 timeout <<= 1;
1314 }
1315 dto = 31 - dto;
1316 timeout <<= 1;
1317 if (timeout && dto)
1318 dto += 1;
1319 if (dto >= 13)
1320 dto -= 13;
1321 else
1322 dto = 0;
1323 if (dto > 14)
1324 dto = 14;
1325 }
1326
1327 reg &= ~DTO_MASK;
1328 reg |= dto << DTO_SHIFT;
1329 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1330}
1331
1332static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1333{
1334 struct mmc_request *req = host->mrq;
1335 struct dma_chan *chan;
1336
1337 if (!req->data)
1338 return;
1339 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1340 | (req->data->blocks << 16));
1341 set_data_timeout(host, req->data->timeout_ns,
1342 req->data->timeout_clks);
1343 chan = omap_hsmmc_get_dma_chan(host, req->data);
1344 dma_async_issue_pending(chan);
1345}
1346
1347/*
1348 * Configure block length for MMC/SD cards and initiate the transfer.
1349 */
1350static int
1351omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1352{
1353 int ret;
1354 unsigned long long timeout;
1355
1356 host->data = req->data;
1357
1358 if (req->data == NULL) {
1359 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1360 if (req->cmd->flags & MMC_RSP_BUSY) {
1361 timeout = req->cmd->busy_timeout * NSEC_PER_MSEC;
1362
1363 /*
1364 * Set an arbitrary 100ms data timeout for commands with
1365 * busy signal and no indication of busy_timeout.
1366 */
1367 if (!timeout)
1368 timeout = 100000000U;
1369
1370 set_data_timeout(host, timeout, 0);
1371 }
1372 return 0;
1373 }
1374
1375 if (host->use_dma) {
1376 ret = omap_hsmmc_setup_dma_transfer(host, req);
1377 if (ret != 0) {
1378 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
1379 return ret;
1380 }
1381 }
1382 return 0;
1383}
1384
1385static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1386 int err)
1387{
1388 struct omap_hsmmc_host *host = mmc_priv(mmc);
1389 struct mmc_data *data = mrq->data;
1390
1391 if (host->use_dma && data->host_cookie) {
1392 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1393
1394 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1395 mmc_get_dma_dir(data));
1396 data->host_cookie = 0;
1397 }
1398}
1399
1400static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1401{
1402 struct omap_hsmmc_host *host = mmc_priv(mmc);
1403
1404 if (mrq->data->host_cookie) {
1405 mrq->data->host_cookie = 0;
1406 return ;
1407 }
1408
1409 if (host->use_dma) {
1410 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1411
1412 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1413 &host->next_data, c))
1414 mrq->data->host_cookie = 0;
1415 }
1416}
1417
1418/*
1419 * Request function. for read/write operation
1420 */
1421static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1422{
1423 struct omap_hsmmc_host *host = mmc_priv(mmc);
1424 int err;
1425
1426 BUG_ON(host->req_in_progress);
1427 BUG_ON(host->dma_ch != -1);
1428 if (host->reqs_blocked)
1429 host->reqs_blocked = 0;
1430 WARN_ON(host->mrq != NULL);
1431 host->mrq = req;
1432 host->clk_rate = clk_get_rate(host->fclk);
1433 err = omap_hsmmc_prepare_data(host, req);
1434 if (err) {
1435 req->cmd->error = err;
1436 if (req->data)
1437 req->data->error = err;
1438 host->mrq = NULL;
1439 mmc_request_done(mmc, req);
1440 return;
1441 }
1442 if (req->sbc && !(host->flags & AUTO_CMD23)) {
1443 omap_hsmmc_start_command(host, req->sbc, NULL);
1444 return;
1445 }
1446
1447 omap_hsmmc_start_dma_transfer(host);
1448 omap_hsmmc_start_command(host, req->cmd, req->data);
1449}
1450
1451/* Routine to configure clock values. Exposed API to core */
1452static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1453{
1454 struct omap_hsmmc_host *host = mmc_priv(mmc);
1455 int do_send_init_stream = 0;
1456
1457 if (ios->power_mode != host->power_mode) {
1458 switch (ios->power_mode) {
1459 case MMC_POWER_OFF:
1460 omap_hsmmc_set_power(host, 0);
1461 break;
1462 case MMC_POWER_UP:
1463 omap_hsmmc_set_power(host, 1);
1464 break;
1465 case MMC_POWER_ON:
1466 do_send_init_stream = 1;
1467 break;
1468 }
1469 host->power_mode = ios->power_mode;
1470 }
1471
1472 /* FIXME: set registers based only on changes to ios */
1473
1474 omap_hsmmc_set_bus_width(host);
1475
1476 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1477 /* Only MMC1 can interface at 3V without some flavor
1478 * of external transceiver; but they all handle 1.8V.
1479 */
1480 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1481 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1482 /*
1483 * The mmc_select_voltage fn of the core does
1484 * not seem to set the power_mode to
1485 * MMC_POWER_UP upon recalculating the voltage.
1486 * vdd 1.8v.
1487 */
1488 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1489 dev_dbg(mmc_dev(host->mmc),
1490 "Switch operation failed\n");
1491 }
1492 }
1493
1494 omap_hsmmc_set_clock(host);
1495
1496 if (do_send_init_stream)
1497 send_init_stream(host);
1498
1499 omap_hsmmc_set_bus_mode(host);
1500}
1501
1502static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1503{
1504 struct omap_hsmmc_host *host = mmc_priv(mmc);
1505 u32 irq_mask, con;
1506 unsigned long flags;
1507
1508 spin_lock_irqsave(&host->irq_lock, flags);
1509
1510 con = OMAP_HSMMC_READ(host->base, CON);
1511 irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1512 if (enable) {
1513 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1514 irq_mask |= CIRQ_EN;
1515 con |= CTPL | CLKEXTFREE;
1516 } else {
1517 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1518 irq_mask &= ~CIRQ_EN;
1519 con &= ~(CTPL | CLKEXTFREE);
1520 }
1521 OMAP_HSMMC_WRITE(host->base, CON, con);
1522 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1523
1524 /*
1525 * if enable, piggy back detection on current request
1526 * but always disable immediately
1527 */
1528 if (!host->req_in_progress || !enable)
1529 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1530
1531 /* flush posted write */
1532 OMAP_HSMMC_READ(host->base, IE);
1533
1534 spin_unlock_irqrestore(&host->irq_lock, flags);
1535}
1536
1537static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1538{
1539 int ret;
1540
1541 /*
1542 * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1543 * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1544 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1545 * with functional clock disabled.
1546 */
1547 if (!host->dev->of_node || !host->wake_irq)
1548 return -ENODEV;
1549
1550 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
1551 if (ret) {
1552 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1553 goto err;
1554 }
1555
1556 /*
1557 * Some omaps don't have wake-up path from deeper idle states
1558 * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1559 */
1560 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
1561 struct pinctrl *p = devm_pinctrl_get(host->dev);
1562 if (IS_ERR(p)) {
1563 ret = PTR_ERR(p);
1564 goto err_free_irq;
1565 }
1566
1567 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1568 dev_info(host->dev, "missing idle pinctrl state\n");
1569 devm_pinctrl_put(p);
1570 ret = -EINVAL;
1571 goto err_free_irq;
1572 }
1573 devm_pinctrl_put(p);
1574 }
1575
1576 OMAP_HSMMC_WRITE(host->base, HCTL,
1577 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
1578 return 0;
1579
1580err_free_irq:
1581 dev_pm_clear_wake_irq(host->dev);
1582err:
1583 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1584 host->wake_irq = 0;
1585 return ret;
1586}
1587
1588static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1589{
1590 u32 hctl, capa, value;
1591
1592 /* Only MMC1 supports 3.0V */
1593 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1594 hctl = SDVS30;
1595 capa = VS30 | VS18;
1596 } else {
1597 hctl = SDVS18;
1598 capa = VS18;
1599 }
1600
1601 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1602 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1603
1604 value = OMAP_HSMMC_READ(host->base, CAPA);
1605 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1606
1607 /* Set SD bus power bit */
1608 set_sd_bus_power(host);
1609}
1610
1611static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1612 unsigned int direction, int blk_size)
1613{
1614 /* This controller can't do multiblock reads due to hw bugs */
1615 if (direction == MMC_DATA_READ)
1616 return 1;
1617
1618 return blk_size;
1619}
1620
1621static struct mmc_host_ops omap_hsmmc_ops = {
1622 .post_req = omap_hsmmc_post_req,
1623 .pre_req = omap_hsmmc_pre_req,
1624 .request = omap_hsmmc_request,
1625 .set_ios = omap_hsmmc_set_ios,
1626 .get_cd = mmc_gpio_get_cd,
1627 .get_ro = mmc_gpio_get_ro,
1628 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
1629};
1630
1631#ifdef CONFIG_DEBUG_FS
1632
1633static int mmc_regs_show(struct seq_file *s, void *data)
1634{
1635 struct mmc_host *mmc = s->private;
1636 struct omap_hsmmc_host *host = mmc_priv(mmc);
1637
1638 seq_printf(s, "mmc%d:\n", mmc->index);
1639 seq_printf(s, "sdio irq mode\t%s\n",
1640 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
1641
1642 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1643 seq_printf(s, "sdio irq \t%s\n",
1644 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
1645 : "disabled");
1646 }
1647 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
1648
1649 pm_runtime_get_sync(host->dev);
1650 seq_puts(s, "\nregs:\n");
1651 seq_printf(s, "CON:\t\t0x%08x\n",
1652 OMAP_HSMMC_READ(host->base, CON));
1653 seq_printf(s, "PSTATE:\t\t0x%08x\n",
1654 OMAP_HSMMC_READ(host->base, PSTATE));
1655 seq_printf(s, "HCTL:\t\t0x%08x\n",
1656 OMAP_HSMMC_READ(host->base, HCTL));
1657 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1658 OMAP_HSMMC_READ(host->base, SYSCTL));
1659 seq_printf(s, "IE:\t\t0x%08x\n",
1660 OMAP_HSMMC_READ(host->base, IE));
1661 seq_printf(s, "ISE:\t\t0x%08x\n",
1662 OMAP_HSMMC_READ(host->base, ISE));
1663 seq_printf(s, "CAPA:\t\t0x%08x\n",
1664 OMAP_HSMMC_READ(host->base, CAPA));
1665
1666 pm_runtime_mark_last_busy(host->dev);
1667 pm_runtime_put_autosuspend(host->dev);
1668
1669 return 0;
1670}
1671
1672DEFINE_SHOW_ATTRIBUTE(mmc_regs);
1673
1674static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1675{
1676 if (mmc->debugfs_root)
1677 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1678 mmc, &mmc_regs_fops);
1679}
1680
1681#else
1682
1683static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1684{
1685}
1686
1687#endif
1688
1689#ifdef CONFIG_OF
1690static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1691 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1692 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1693};
1694
1695static const struct omap_mmc_of_data omap4_mmc_of_data = {
1696 .reg_offset = 0x100,
1697};
1698static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1699 .reg_offset = 0x100,
1700 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1701};
1702
1703static const struct of_device_id omap_mmc_of_match[] = {
1704 {
1705 .compatible = "ti,omap2-hsmmc",
1706 },
1707 {
1708 .compatible = "ti,omap3-pre-es3-hsmmc",
1709 .data = &omap3_pre_es3_mmc_of_data,
1710 },
1711 {
1712 .compatible = "ti,omap3-hsmmc",
1713 },
1714 {
1715 .compatible = "ti,omap4-hsmmc",
1716 .data = &omap4_mmc_of_data,
1717 },
1718 {
1719 .compatible = "ti,am33xx-hsmmc",
1720 .data = &am33xx_mmc_of_data,
1721 },
1722 {},
1723};
1724MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1725
1726static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1727{
1728 struct omap_hsmmc_platform_data *pdata, *legacy;
1729 struct device_node *np = dev->of_node;
1730
1731 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1732 if (!pdata)
1733 return ERR_PTR(-ENOMEM); /* out of memory */
1734
1735 legacy = dev_get_platdata(dev);
1736 if (legacy && legacy->name)
1737 pdata->name = legacy->name;
1738
1739 if (of_property_read_bool(np, "ti,dual-volt"))
1740 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1741
1742 if (of_property_read_bool(np, "ti,non-removable")) {
1743 pdata->nonremovable = true;
1744 pdata->no_regulator_off_init = true;
1745 }
1746
1747 if (of_property_read_bool(np, "ti,needs-special-reset"))
1748 pdata->features |= HSMMC_HAS_UPDATED_RESET;
1749
1750 if (of_property_read_bool(np, "ti,needs-special-hs-handling"))
1751 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
1752
1753 return pdata;
1754}
1755#else
1756static inline struct omap_hsmmc_platform_data
1757 *of_get_hsmmc_pdata(struct device *dev)
1758{
1759 return ERR_PTR(-EINVAL);
1760}
1761#endif
1762
1763static int omap_hsmmc_probe(struct platform_device *pdev)
1764{
1765 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
1766 struct mmc_host *mmc;
1767 struct omap_hsmmc_host *host = NULL;
1768 struct resource *res;
1769 int ret, irq;
1770 const struct of_device_id *match;
1771 const struct omap_mmc_of_data *data;
1772 void __iomem *base;
1773
1774 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1775 if (match) {
1776 pdata = of_get_hsmmc_pdata(&pdev->dev);
1777
1778 if (IS_ERR(pdata))
1779 return PTR_ERR(pdata);
1780
1781 if (match->data) {
1782 data = match->data;
1783 pdata->reg_offset = data->reg_offset;
1784 pdata->controller_flags |= data->controller_flags;
1785 }
1786 }
1787
1788 if (pdata == NULL) {
1789 dev_err(&pdev->dev, "Platform Data is missing\n");
1790 return -ENXIO;
1791 }
1792
1793 irq = platform_get_irq(pdev, 0);
1794 if (irq < 0)
1795 return irq;
1796
1797 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1798 if (IS_ERR(base))
1799 return PTR_ERR(base);
1800
1801 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1802 if (!mmc) {
1803 ret = -ENOMEM;
1804 goto err;
1805 }
1806
1807 ret = mmc_of_parse(mmc);
1808 if (ret)
1809 goto err1;
1810
1811 host = mmc_priv(mmc);
1812 host->mmc = mmc;
1813 host->pdata = pdata;
1814 host->dev = &pdev->dev;
1815 host->use_dma = 1;
1816 host->dma_ch = -1;
1817 host->irq = irq;
1818 host->mapbase = res->start + pdata->reg_offset;
1819 host->base = base + pdata->reg_offset;
1820 host->power_mode = MMC_POWER_OFF;
1821 host->next_data.cookie = 1;
1822 host->pbias_enabled = false;
1823 host->vqmmc_enabled = false;
1824
1825 platform_set_drvdata(pdev, host);
1826
1827 if (pdev->dev.of_node)
1828 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1829
1830 mmc->ops = &omap_hsmmc_ops;
1831
1832 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1833
1834 if (pdata->max_freq > 0)
1835 mmc->f_max = pdata->max_freq;
1836 else if (mmc->f_max == 0)
1837 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1838
1839 spin_lock_init(&host->irq_lock);
1840
1841 host->fclk = devm_clk_get(&pdev->dev, "fck");
1842 if (IS_ERR(host->fclk)) {
1843 ret = PTR_ERR(host->fclk);
1844 host->fclk = NULL;
1845 goto err1;
1846 }
1847
1848 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1849 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1850 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
1851 }
1852
1853 device_init_wakeup(&pdev->dev, true);
1854 pm_runtime_enable(host->dev);
1855 pm_runtime_get_sync(host->dev);
1856 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1857 pm_runtime_use_autosuspend(host->dev);
1858
1859 omap_hsmmc_context_save(host);
1860
1861 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
1862 /*
1863 * MMC can still work without debounce clock.
1864 */
1865 if (IS_ERR(host->dbclk)) {
1866 host->dbclk = NULL;
1867 } else if (clk_prepare_enable(host->dbclk) != 0) {
1868 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1869 host->dbclk = NULL;
1870 }
1871
1872 /* Set this to a value that allows allocating an entire descriptor
1873 * list within a page (zero order allocation). */
1874 mmc->max_segs = 64;
1875
1876 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1877 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1878 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1879
1880 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1881 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_CMD23;
1882
1883 mmc->caps |= mmc_pdata(host)->caps;
1884 if (mmc->caps & MMC_CAP_8_BIT_DATA)
1885 mmc->caps |= MMC_CAP_4_BIT_DATA;
1886
1887 if (mmc_pdata(host)->nonremovable)
1888 mmc->caps |= MMC_CAP_NONREMOVABLE;
1889
1890 mmc->pm_caps |= mmc_pdata(host)->pm_caps;
1891
1892 omap_hsmmc_conf_bus_power(host);
1893
1894 host->rx_chan = dma_request_chan(&pdev->dev, "rx");
1895 if (IS_ERR(host->rx_chan)) {
1896 dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n");
1897 ret = PTR_ERR(host->rx_chan);
1898 goto err_irq;
1899 }
1900
1901 host->tx_chan = dma_request_chan(&pdev->dev, "tx");
1902 if (IS_ERR(host->tx_chan)) {
1903 dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n");
1904 ret = PTR_ERR(host->tx_chan);
1905 goto err_irq;
1906 }
1907
1908 /*
1909 * Limit the maximum segment size to the lower of the request size
1910 * and the DMA engine device segment size limits. In reality, with
1911 * 32-bit transfers, the DMA engine can do longer segments than this
1912 * but there is no way to represent that in the DMA model - if we
1913 * increase this figure here, we get warnings from the DMA API debug.
1914 */
1915 mmc->max_seg_size = min3(mmc->max_req_size,
1916 dma_get_max_seg_size(host->rx_chan->device->dev),
1917 dma_get_max_seg_size(host->tx_chan->device->dev));
1918
1919 /* Request IRQ for MMC operations */
1920 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
1921 mmc_hostname(mmc), host);
1922 if (ret) {
1923 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1924 goto err_irq;
1925 }
1926
1927 ret = omap_hsmmc_reg_get(host);
1928 if (ret)
1929 goto err_irq;
1930
1931 if (!mmc->ocr_avail)
1932 mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
1933
1934 omap_hsmmc_disable_irq(host);
1935
1936 /*
1937 * For now, only support SDIO interrupt if we have a separate
1938 * wake-up interrupt configured from device tree. This is because
1939 * the wake-up interrupt is needed for idle state and some
1940 * platforms need special quirks. And we don't want to add new
1941 * legacy mux platform init code callbacks any longer as we
1942 * are moving to DT based booting anyways.
1943 */
1944 ret = omap_hsmmc_configure_wake_irq(host);
1945 if (!ret)
1946 mmc->caps |= MMC_CAP_SDIO_IRQ;
1947
1948 ret = mmc_add_host(mmc);
1949 if (ret)
1950 goto err_irq;
1951
1952 if (mmc_pdata(host)->name != NULL) {
1953 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1954 if (ret < 0)
1955 goto err_slot_name;
1956 }
1957
1958 omap_hsmmc_debugfs(mmc);
1959 pm_runtime_mark_last_busy(host->dev);
1960 pm_runtime_put_autosuspend(host->dev);
1961
1962 return 0;
1963
1964err_slot_name:
1965 mmc_remove_host(mmc);
1966err_irq:
1967 device_init_wakeup(&pdev->dev, false);
1968 if (!IS_ERR_OR_NULL(host->tx_chan))
1969 dma_release_channel(host->tx_chan);
1970 if (!IS_ERR_OR_NULL(host->rx_chan))
1971 dma_release_channel(host->rx_chan);
1972 pm_runtime_dont_use_autosuspend(host->dev);
1973 pm_runtime_put_sync(host->dev);
1974 pm_runtime_disable(host->dev);
1975 clk_disable_unprepare(host->dbclk);
1976err1:
1977 mmc_free_host(mmc);
1978err:
1979 return ret;
1980}
1981
1982static void omap_hsmmc_remove(struct platform_device *pdev)
1983{
1984 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1985
1986 pm_runtime_get_sync(host->dev);
1987 mmc_remove_host(host->mmc);
1988
1989 dma_release_channel(host->tx_chan);
1990 dma_release_channel(host->rx_chan);
1991
1992 dev_pm_clear_wake_irq(host->dev);
1993 pm_runtime_dont_use_autosuspend(host->dev);
1994 pm_runtime_put_sync(host->dev);
1995 pm_runtime_disable(host->dev);
1996 device_init_wakeup(&pdev->dev, false);
1997 clk_disable_unprepare(host->dbclk);
1998
1999 mmc_free_host(host->mmc);
2000}
2001
2002#ifdef CONFIG_PM_SLEEP
2003static int omap_hsmmc_suspend(struct device *dev)
2004{
2005 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2006
2007 if (!host)
2008 return 0;
2009
2010 pm_runtime_get_sync(host->dev);
2011
2012 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2013 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2014 OMAP_HSMMC_WRITE(host->base, IE, 0);
2015 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2016 OMAP_HSMMC_WRITE(host->base, HCTL,
2017 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2018 }
2019
2020 clk_disable_unprepare(host->dbclk);
2021
2022 pm_runtime_put_sync(host->dev);
2023 return 0;
2024}
2025
2026/* Routine to resume the MMC device */
2027static int omap_hsmmc_resume(struct device *dev)
2028{
2029 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2030
2031 if (!host)
2032 return 0;
2033
2034 pm_runtime_get_sync(host->dev);
2035
2036 clk_prepare_enable(host->dbclk);
2037
2038 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2039 omap_hsmmc_conf_bus_power(host);
2040
2041 pm_runtime_mark_last_busy(host->dev);
2042 pm_runtime_put_autosuspend(host->dev);
2043 return 0;
2044}
2045#endif
2046
2047#ifdef CONFIG_PM
2048static int omap_hsmmc_runtime_suspend(struct device *dev)
2049{
2050 struct omap_hsmmc_host *host;
2051 unsigned long flags;
2052 int ret = 0;
2053
2054 host = dev_get_drvdata(dev);
2055 omap_hsmmc_context_save(host);
2056 dev_dbg(dev, "disabled\n");
2057
2058 spin_lock_irqsave(&host->irq_lock, flags);
2059 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2060 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2061 /* disable sdio irq handling to prevent race */
2062 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2063 OMAP_HSMMC_WRITE(host->base, IE, 0);
2064
2065 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2066 /*
2067 * dat1 line low, pending sdio irq
2068 * race condition: possible irq handler running on
2069 * multi-core, abort
2070 */
2071 dev_dbg(dev, "pending sdio irq, abort suspend\n");
2072 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2073 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2074 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2075 pm_runtime_mark_last_busy(dev);
2076 ret = -EBUSY;
2077 goto abort;
2078 }
2079
2080 pinctrl_pm_select_idle_state(dev);
2081 } else {
2082 pinctrl_pm_select_idle_state(dev);
2083 }
2084
2085abort:
2086 spin_unlock_irqrestore(&host->irq_lock, flags);
2087 return ret;
2088}
2089
2090static int omap_hsmmc_runtime_resume(struct device *dev)
2091{
2092 struct omap_hsmmc_host *host;
2093 unsigned long flags;
2094
2095 host = dev_get_drvdata(dev);
2096 omap_hsmmc_context_restore(host);
2097 dev_dbg(dev, "enabled\n");
2098
2099 spin_lock_irqsave(&host->irq_lock, flags);
2100 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2101 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2102
2103 pinctrl_select_default_state(host->dev);
2104
2105 /* irq lost, if pinmux incorrect */
2106 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2107 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2108 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2109 } else {
2110 pinctrl_select_default_state(host->dev);
2111 }
2112 spin_unlock_irqrestore(&host->irq_lock, flags);
2113 return 0;
2114}
2115#endif
2116
2117static const struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2118 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
2119 SET_RUNTIME_PM_OPS(omap_hsmmc_runtime_suspend, omap_hsmmc_runtime_resume, NULL)
2120};
2121
2122static struct platform_driver omap_hsmmc_driver = {
2123 .probe = omap_hsmmc_probe,
2124 .remove_new = omap_hsmmc_remove,
2125 .driver = {
2126 .name = DRIVER_NAME,
2127 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2128 .pm = &omap_hsmmc_dev_pm_ops,
2129 .of_match_table = of_match_ptr(omap_mmc_of_match),
2130 },
2131};
2132
2133module_platform_driver(omap_hsmmc_driver);
2134MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2135MODULE_LICENSE("GPL");
2136MODULE_ALIAS("platform:" DRIVER_NAME);
2137MODULE_AUTHOR("Texas Instruments Inc");