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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6#include <linux/amba/bus.h>
7#include <linux/bitfield.h>
8#include <linux/bitmap.h>
9#include <linux/coresight.h>
10#include <linux/coresight-pmu.h>
11#include <linux/device.h>
12#include <linux/err.h>
13#include <linux/fs.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/of.h>
18
19#include "coresight-priv.h"
20#include "coresight-tpdm.h"
21
22DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");
23
24/* Read dataset array member with the index number */
25static ssize_t tpdm_simple_dataset_show(struct device *dev,
26 struct device_attribute *attr,
27 char *buf)
28{
29 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
30 struct tpdm_dataset_attribute *tpdm_attr =
31 container_of(attr, struct tpdm_dataset_attribute, attr);
32
33 switch (tpdm_attr->mem) {
34 case DSB_EDGE_CTRL:
35 if (tpdm_attr->idx >= TPDM_DSB_MAX_EDCR)
36 return -EINVAL;
37 return sysfs_emit(buf, "0x%x\n",
38 drvdata->dsb->edge_ctrl[tpdm_attr->idx]);
39 case DSB_EDGE_CTRL_MASK:
40 if (tpdm_attr->idx >= TPDM_DSB_MAX_EDCMR)
41 return -EINVAL;
42 return sysfs_emit(buf, "0x%x\n",
43 drvdata->dsb->edge_ctrl_mask[tpdm_attr->idx]);
44 case DSB_TRIG_PATT:
45 if (tpdm_attr->idx >= TPDM_DSB_MAX_PATT)
46 return -EINVAL;
47 return sysfs_emit(buf, "0x%x\n",
48 drvdata->dsb->trig_patt[tpdm_attr->idx]);
49 case DSB_TRIG_PATT_MASK:
50 if (tpdm_attr->idx >= TPDM_DSB_MAX_PATT)
51 return -EINVAL;
52 return sysfs_emit(buf, "0x%x\n",
53 drvdata->dsb->trig_patt_mask[tpdm_attr->idx]);
54 case DSB_PATT:
55 if (tpdm_attr->idx >= TPDM_DSB_MAX_PATT)
56 return -EINVAL;
57 return sysfs_emit(buf, "0x%x\n",
58 drvdata->dsb->patt_val[tpdm_attr->idx]);
59 case DSB_PATT_MASK:
60 if (tpdm_attr->idx >= TPDM_DSB_MAX_PATT)
61 return -EINVAL;
62 return sysfs_emit(buf, "0x%x\n",
63 drvdata->dsb->patt_mask[tpdm_attr->idx]);
64 case DSB_MSR:
65 if (tpdm_attr->idx >= drvdata->dsb_msr_num)
66 return -EINVAL;
67 return sysfs_emit(buf, "0x%x\n",
68 drvdata->dsb->msr[tpdm_attr->idx]);
69 }
70 return -EINVAL;
71}
72
73/* Write dataset array member with the index number */
74static ssize_t tpdm_simple_dataset_store(struct device *dev,
75 struct device_attribute *attr,
76 const char *buf,
77 size_t size)
78{
79 unsigned long val;
80 ssize_t ret = size;
81
82 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
83 struct tpdm_dataset_attribute *tpdm_attr =
84 container_of(attr, struct tpdm_dataset_attribute, attr);
85
86 if (kstrtoul(buf, 0, &val))
87 return -EINVAL;
88
89 spin_lock(&drvdata->spinlock);
90 switch (tpdm_attr->mem) {
91 case DSB_TRIG_PATT:
92 if (tpdm_attr->idx < TPDM_DSB_MAX_PATT)
93 drvdata->dsb->trig_patt[tpdm_attr->idx] = val;
94 else
95 ret = -EINVAL;
96 break;
97 case DSB_TRIG_PATT_MASK:
98 if (tpdm_attr->idx < TPDM_DSB_MAX_PATT)
99 drvdata->dsb->trig_patt_mask[tpdm_attr->idx] = val;
100 else
101 ret = -EINVAL;
102 break;
103 case DSB_PATT:
104 if (tpdm_attr->idx < TPDM_DSB_MAX_PATT)
105 drvdata->dsb->patt_val[tpdm_attr->idx] = val;
106 else
107 ret = -EINVAL;
108 break;
109 case DSB_PATT_MASK:
110 if (tpdm_attr->idx < TPDM_DSB_MAX_PATT)
111 drvdata->dsb->patt_mask[tpdm_attr->idx] = val;
112 else
113 ret = -EINVAL;
114 break;
115 case DSB_MSR:
116 if (tpdm_attr->idx < drvdata->dsb_msr_num)
117 drvdata->dsb->msr[tpdm_attr->idx] = val;
118 else
119 ret = -EINVAL;
120 break;
121 default:
122 ret = -EINVAL;
123 }
124 spin_unlock(&drvdata->spinlock);
125
126 return ret;
127}
128
129static bool tpdm_has_dsb_dataset(struct tpdm_drvdata *drvdata)
130{
131 return (drvdata->datasets & TPDM_PIDR0_DS_DSB);
132}
133
134static umode_t tpdm_dsb_is_visible(struct kobject *kobj,
135 struct attribute *attr, int n)
136{
137 struct device *dev = kobj_to_dev(kobj);
138 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
139
140 if (drvdata && tpdm_has_dsb_dataset(drvdata))
141 return attr->mode;
142
143 return 0;
144}
145
146static umode_t tpdm_dsb_msr_is_visible(struct kobject *kobj,
147 struct attribute *attr, int n)
148{
149 struct device *dev = kobj_to_dev(kobj);
150 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
151 struct device_attribute *dev_attr =
152 container_of(attr, struct device_attribute, attr);
153 struct tpdm_dataset_attribute *tpdm_attr =
154 container_of(dev_attr, struct tpdm_dataset_attribute, attr);
155
156 if (tpdm_attr->idx < drvdata->dsb_msr_num)
157 return attr->mode;
158
159 return 0;
160}
161
162static void tpdm_reset_datasets(struct tpdm_drvdata *drvdata)
163{
164 if (tpdm_has_dsb_dataset(drvdata)) {
165 memset(drvdata->dsb, 0, sizeof(struct dsb_dataset));
166
167 drvdata->dsb->trig_ts = true;
168 drvdata->dsb->trig_type = false;
169 }
170}
171
172static void set_dsb_mode(struct tpdm_drvdata *drvdata, u32 *val)
173{
174 u32 mode;
175
176 /* Set the test accurate mode */
177 mode = TPDM_DSB_MODE_TEST(drvdata->dsb->mode);
178 *val &= ~TPDM_DSB_CR_TEST_MODE;
179 *val |= FIELD_PREP(TPDM_DSB_CR_TEST_MODE, mode);
180
181 /* Set the byte lane for high-performance mode */
182 mode = TPDM_DSB_MODE_HPBYTESEL(drvdata->dsb->mode);
183 *val &= ~TPDM_DSB_CR_HPSEL;
184 *val |= FIELD_PREP(TPDM_DSB_CR_HPSEL, mode);
185
186 /* Set the performance mode */
187 if (drvdata->dsb->mode & TPDM_DSB_MODE_PERF)
188 *val |= TPDM_DSB_CR_MODE;
189 else
190 *val &= ~TPDM_DSB_CR_MODE;
191}
192
193static void set_dsb_tier(struct tpdm_drvdata *drvdata)
194{
195 u32 val;
196
197 val = readl_relaxed(drvdata->base + TPDM_DSB_TIER);
198
199 /* Clear all relevant fields */
200 val &= ~(TPDM_DSB_TIER_PATT_TSENAB | TPDM_DSB_TIER_PATT_TYPE |
201 TPDM_DSB_TIER_XTRIG_TSENAB);
202
203 /* Set pattern timestamp type and enablement */
204 if (drvdata->dsb->patt_ts) {
205 val |= TPDM_DSB_TIER_PATT_TSENAB;
206 if (drvdata->dsb->patt_type)
207 val |= TPDM_DSB_TIER_PATT_TYPE;
208 else
209 val &= ~TPDM_DSB_TIER_PATT_TYPE;
210 } else {
211 val &= ~TPDM_DSB_TIER_PATT_TSENAB;
212 }
213
214 /* Set trigger timestamp */
215 if (drvdata->dsb->trig_ts)
216 val |= TPDM_DSB_TIER_XTRIG_TSENAB;
217 else
218 val &= ~TPDM_DSB_TIER_XTRIG_TSENAB;
219
220 writel_relaxed(val, drvdata->base + TPDM_DSB_TIER);
221}
222
223static void set_dsb_msr(struct tpdm_drvdata *drvdata)
224{
225 int i;
226
227 for (i = 0; i < drvdata->dsb_msr_num; i++)
228 writel_relaxed(drvdata->dsb->msr[i],
229 drvdata->base + TPDM_DSB_MSR(i));
230}
231
232static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
233{
234 u32 val, i;
235
236 for (i = 0; i < TPDM_DSB_MAX_EDCR; i++)
237 writel_relaxed(drvdata->dsb->edge_ctrl[i],
238 drvdata->base + TPDM_DSB_EDCR(i));
239 for (i = 0; i < TPDM_DSB_MAX_EDCMR; i++)
240 writel_relaxed(drvdata->dsb->edge_ctrl_mask[i],
241 drvdata->base + TPDM_DSB_EDCMR(i));
242 for (i = 0; i < TPDM_DSB_MAX_PATT; i++) {
243 writel_relaxed(drvdata->dsb->patt_val[i],
244 drvdata->base + TPDM_DSB_TPR(i));
245 writel_relaxed(drvdata->dsb->patt_mask[i],
246 drvdata->base + TPDM_DSB_TPMR(i));
247 writel_relaxed(drvdata->dsb->trig_patt[i],
248 drvdata->base + TPDM_DSB_XPR(i));
249 writel_relaxed(drvdata->dsb->trig_patt_mask[i],
250 drvdata->base + TPDM_DSB_XPMR(i));
251 }
252
253 set_dsb_tier(drvdata);
254
255 set_dsb_msr(drvdata);
256
257 val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
258 /* Set the mode of DSB dataset */
259 set_dsb_mode(drvdata, &val);
260 /* Set trigger type */
261 if (drvdata->dsb->trig_type)
262 val |= TPDM_DSB_CR_TRIG_TYPE;
263 else
264 val &= ~TPDM_DSB_CR_TRIG_TYPE;
265 /* Set the enable bit of DSB control register to 1 */
266 val |= TPDM_DSB_CR_ENA;
267 writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
268}
269
270/*
271 * TPDM enable operations
272 * The TPDM or Monitor serves as data collection component for various
273 * dataset types. It covers Basic Counts(BC), Tenure Counts(TC),
274 * Continuous Multi-Bit(CMB), Multi-lane CMB(MCMB) and Discrete Single
275 * Bit(DSB). This function will initialize the configuration according
276 * to the dataset type supported by the TPDM.
277 */
278static void __tpdm_enable(struct tpdm_drvdata *drvdata)
279{
280 CS_UNLOCK(drvdata->base);
281
282 if (tpdm_has_dsb_dataset(drvdata))
283 tpdm_enable_dsb(drvdata);
284
285 CS_LOCK(drvdata->base);
286}
287
288static int tpdm_enable(struct coresight_device *csdev, struct perf_event *event,
289 enum cs_mode mode)
290{
291 struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
292
293 spin_lock(&drvdata->spinlock);
294 if (drvdata->enable) {
295 spin_unlock(&drvdata->spinlock);
296 return -EBUSY;
297 }
298
299 __tpdm_enable(drvdata);
300 drvdata->enable = true;
301 spin_unlock(&drvdata->spinlock);
302
303 dev_dbg(drvdata->dev, "TPDM tracing enabled\n");
304 return 0;
305}
306
307static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata)
308{
309 u32 val;
310
311 /* Set the enable bit of DSB control register to 0 */
312 val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
313 val &= ~TPDM_DSB_CR_ENA;
314 writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
315}
316
317/* TPDM disable operations */
318static void __tpdm_disable(struct tpdm_drvdata *drvdata)
319{
320 CS_UNLOCK(drvdata->base);
321
322 if (tpdm_has_dsb_dataset(drvdata))
323 tpdm_disable_dsb(drvdata);
324
325 CS_LOCK(drvdata->base);
326}
327
328static void tpdm_disable(struct coresight_device *csdev,
329 struct perf_event *event)
330{
331 struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
332
333 spin_lock(&drvdata->spinlock);
334 if (!drvdata->enable) {
335 spin_unlock(&drvdata->spinlock);
336 return;
337 }
338
339 __tpdm_disable(drvdata);
340 drvdata->enable = false;
341 spin_unlock(&drvdata->spinlock);
342
343 dev_dbg(drvdata->dev, "TPDM tracing disabled\n");
344}
345
346static const struct coresight_ops_source tpdm_source_ops = {
347 .enable = tpdm_enable,
348 .disable = tpdm_disable,
349};
350
351static const struct coresight_ops tpdm_cs_ops = {
352 .source_ops = &tpdm_source_ops,
353};
354
355static int tpdm_datasets_setup(struct tpdm_drvdata *drvdata)
356{
357 u32 pidr;
358
359 /* Get the datasets present on the TPDM. */
360 pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0);
361 drvdata->datasets |= pidr & GENMASK(TPDM_DATASETS - 1, 0);
362
363 if (tpdm_has_dsb_dataset(drvdata) && (!drvdata->dsb)) {
364 drvdata->dsb = devm_kzalloc(drvdata->dev,
365 sizeof(*drvdata->dsb), GFP_KERNEL);
366 if (!drvdata->dsb)
367 return -ENOMEM;
368 }
369 tpdm_reset_datasets(drvdata);
370
371 return 0;
372}
373
374static ssize_t reset_dataset_store(struct device *dev,
375 struct device_attribute *attr,
376 const char *buf,
377 size_t size)
378{
379 int ret = 0;
380 unsigned long val;
381 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
382
383 ret = kstrtoul(buf, 0, &val);
384 if (ret || val != 1)
385 return -EINVAL;
386
387 spin_lock(&drvdata->spinlock);
388 tpdm_reset_datasets(drvdata);
389 spin_unlock(&drvdata->spinlock);
390
391 return size;
392}
393static DEVICE_ATTR_WO(reset_dataset);
394
395/*
396 * value 1: 64 bits test data
397 * value 2: 32 bits test data
398 */
399static ssize_t integration_test_store(struct device *dev,
400 struct device_attribute *attr,
401 const char *buf,
402 size_t size)
403{
404 int i, ret = 0;
405 unsigned long val;
406 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
407
408 ret = kstrtoul(buf, 10, &val);
409 if (ret)
410 return ret;
411
412 if (val != 1 && val != 2)
413 return -EINVAL;
414
415 if (!drvdata->enable)
416 return -EINVAL;
417
418 if (val == 1)
419 val = ATBCNTRL_VAL_64;
420 else
421 val = ATBCNTRL_VAL_32;
422 CS_UNLOCK(drvdata->base);
423 writel_relaxed(0x1, drvdata->base + TPDM_ITCNTRL);
424
425 for (i = 0; i < INTEGRATION_TEST_CYCLE; i++)
426 writel_relaxed(val, drvdata->base + TPDM_ITATBCNTRL);
427
428 writel_relaxed(0, drvdata->base + TPDM_ITCNTRL);
429 CS_LOCK(drvdata->base);
430 return size;
431}
432static DEVICE_ATTR_WO(integration_test);
433
434static struct attribute *tpdm_attrs[] = {
435 &dev_attr_reset_dataset.attr,
436 &dev_attr_integration_test.attr,
437 NULL,
438};
439
440static struct attribute_group tpdm_attr_grp = {
441 .attrs = tpdm_attrs,
442};
443
444static ssize_t dsb_mode_show(struct device *dev,
445 struct device_attribute *attr,
446 char *buf)
447{
448 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
449
450 return sysfs_emit(buf, "%x\n", drvdata->dsb->mode);
451}
452
453static ssize_t dsb_mode_store(struct device *dev,
454 struct device_attribute *attr,
455 const char *buf,
456 size_t size)
457{
458 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
459 unsigned long val;
460
461 if ((kstrtoul(buf, 0, &val)) || (val < 0) ||
462 (val & ~TPDM_DSB_MODE_MASK))
463 return -EINVAL;
464
465 spin_lock(&drvdata->spinlock);
466 drvdata->dsb->mode = val & TPDM_DSB_MODE_MASK;
467 spin_unlock(&drvdata->spinlock);
468 return size;
469}
470static DEVICE_ATTR_RW(dsb_mode);
471
472static ssize_t ctrl_idx_show(struct device *dev,
473 struct device_attribute *attr,
474 char *buf)
475{
476 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
477
478 return sysfs_emit(buf, "%u\n",
479 (unsigned int)drvdata->dsb->edge_ctrl_idx);
480}
481
482/*
483 * The EDCR registers can include up to 16 32-bit registers, and each
484 * one can be configured to control up to 16 edge detections(2 bits
485 * control one edge detection). So a total 256 edge detections can be
486 * configured. This function provides a way to set the index number of
487 * the edge detection which needs to be configured.
488 */
489static ssize_t ctrl_idx_store(struct device *dev,
490 struct device_attribute *attr,
491 const char *buf,
492 size_t size)
493{
494 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
495 unsigned long val;
496
497 if ((kstrtoul(buf, 0, &val)) || (val >= TPDM_DSB_MAX_LINES))
498 return -EINVAL;
499
500 spin_lock(&drvdata->spinlock);
501 drvdata->dsb->edge_ctrl_idx = val;
502 spin_unlock(&drvdata->spinlock);
503
504 return size;
505}
506static DEVICE_ATTR_RW(ctrl_idx);
507
508/*
509 * This function is used to control the edge detection according
510 * to the index number that has been set.
511 * "edge_ctrl" should be one of the following values.
512 * 0 - Rising edge detection
513 * 1 - Falling edge detection
514 * 2 - Rising and falling edge detection (toggle detection)
515 */
516static ssize_t ctrl_val_store(struct device *dev,
517 struct device_attribute *attr,
518 const char *buf,
519 size_t size)
520{
521 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
522 unsigned long val, edge_ctrl;
523 int reg;
524
525 if ((kstrtoul(buf, 0, &edge_ctrl)) || (edge_ctrl > 0x2))
526 return -EINVAL;
527
528 spin_lock(&drvdata->spinlock);
529 /*
530 * There are 2 bit per DSB Edge Control line.
531 * Thus we have 16 lines in a 32bit word.
532 */
533 reg = EDCR_TO_WORD_IDX(drvdata->dsb->edge_ctrl_idx);
534 val = drvdata->dsb->edge_ctrl[reg];
535 val &= ~EDCR_TO_WORD_MASK(drvdata->dsb->edge_ctrl_idx);
536 val |= EDCR_TO_WORD_VAL(edge_ctrl, drvdata->dsb->edge_ctrl_idx);
537 drvdata->dsb->edge_ctrl[reg] = val;
538 spin_unlock(&drvdata->spinlock);
539
540 return size;
541}
542static DEVICE_ATTR_WO(ctrl_val);
543
544static ssize_t ctrl_mask_store(struct device *dev,
545 struct device_attribute *attr,
546 const char *buf,
547 size_t size)
548{
549 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
550 unsigned long val;
551 u32 set;
552 int reg;
553
554 if ((kstrtoul(buf, 0, &val)) || (val & ~1UL))
555 return -EINVAL;
556
557 spin_lock(&drvdata->spinlock);
558 /*
559 * There is 1 bit per DSB Edge Control Mark line.
560 * Thus we have 32 lines in a 32bit word.
561 */
562 reg = EDCMR_TO_WORD_IDX(drvdata->dsb->edge_ctrl_idx);
563 set = drvdata->dsb->edge_ctrl_mask[reg];
564 if (val)
565 set |= BIT(EDCMR_TO_WORD_SHIFT(drvdata->dsb->edge_ctrl_idx));
566 else
567 set &= ~BIT(EDCMR_TO_WORD_SHIFT(drvdata->dsb->edge_ctrl_idx));
568 drvdata->dsb->edge_ctrl_mask[reg] = set;
569 spin_unlock(&drvdata->spinlock);
570
571 return size;
572}
573static DEVICE_ATTR_WO(ctrl_mask);
574
575static ssize_t enable_ts_show(struct device *dev,
576 struct device_attribute *attr,
577 char *buf)
578{
579 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
580
581 return sysfs_emit(buf, "%u\n",
582 (unsigned int)drvdata->dsb->patt_ts);
583}
584
585/*
586 * value 1: Enable/Disable DSB pattern timestamp
587 */
588static ssize_t enable_ts_store(struct device *dev,
589 struct device_attribute *attr,
590 const char *buf,
591 size_t size)
592{
593 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
594 unsigned long val;
595
596 if ((kstrtoul(buf, 0, &val)) || (val & ~1UL))
597 return -EINVAL;
598
599 spin_lock(&drvdata->spinlock);
600 drvdata->dsb->patt_ts = !!val;
601 spin_unlock(&drvdata->spinlock);
602 return size;
603}
604static DEVICE_ATTR_RW(enable_ts);
605
606static ssize_t set_type_show(struct device *dev,
607 struct device_attribute *attr,
608 char *buf)
609{
610 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
611
612 return sysfs_emit(buf, "%u\n",
613 (unsigned int)drvdata->dsb->patt_type);
614}
615
616/*
617 * value 1: Set DSB pattern type
618 */
619static ssize_t set_type_store(struct device *dev,
620 struct device_attribute *attr,
621 const char *buf, size_t size)
622{
623 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
624 unsigned long val;
625
626 if ((kstrtoul(buf, 0, &val)) || (val & ~1UL))
627 return -EINVAL;
628
629 spin_lock(&drvdata->spinlock);
630 drvdata->dsb->patt_type = val;
631 spin_unlock(&drvdata->spinlock);
632 return size;
633}
634static DEVICE_ATTR_RW(set_type);
635
636static ssize_t dsb_trig_type_show(struct device *dev,
637 struct device_attribute *attr, char *buf)
638{
639 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
640
641 return sysfs_emit(buf, "%u\n",
642 (unsigned int)drvdata->dsb->trig_type);
643}
644
645/*
646 * Trigger type (boolean):
647 * false - Disable trigger type.
648 * true - Enable trigger type.
649 */
650static ssize_t dsb_trig_type_store(struct device *dev,
651 struct device_attribute *attr,
652 const char *buf,
653 size_t size)
654{
655 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
656 unsigned long val;
657
658 if ((kstrtoul(buf, 0, &val)) || (val & ~1UL))
659 return -EINVAL;
660
661 spin_lock(&drvdata->spinlock);
662 if (val)
663 drvdata->dsb->trig_type = true;
664 else
665 drvdata->dsb->trig_type = false;
666 spin_unlock(&drvdata->spinlock);
667 return size;
668}
669static DEVICE_ATTR_RW(dsb_trig_type);
670
671static ssize_t dsb_trig_ts_show(struct device *dev,
672 struct device_attribute *attr,
673 char *buf)
674{
675 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
676
677 return sysfs_emit(buf, "%u\n",
678 (unsigned int)drvdata->dsb->trig_ts);
679}
680
681/*
682 * Trigger timestamp (boolean):
683 * false - Disable trigger timestamp.
684 * true - Enable trigger timestamp.
685 */
686static ssize_t dsb_trig_ts_store(struct device *dev,
687 struct device_attribute *attr,
688 const char *buf,
689 size_t size)
690{
691 struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
692 unsigned long val;
693
694 if ((kstrtoul(buf, 0, &val)) || (val & ~1UL))
695 return -EINVAL;
696
697 spin_lock(&drvdata->spinlock);
698 if (val)
699 drvdata->dsb->trig_ts = true;
700 else
701 drvdata->dsb->trig_ts = false;
702 spin_unlock(&drvdata->spinlock);
703 return size;
704}
705static DEVICE_ATTR_RW(dsb_trig_ts);
706
707static struct attribute *tpdm_dsb_edge_attrs[] = {
708 &dev_attr_ctrl_idx.attr,
709 &dev_attr_ctrl_val.attr,
710 &dev_attr_ctrl_mask.attr,
711 DSB_EDGE_CTRL_ATTR(0),
712 DSB_EDGE_CTRL_ATTR(1),
713 DSB_EDGE_CTRL_ATTR(2),
714 DSB_EDGE_CTRL_ATTR(3),
715 DSB_EDGE_CTRL_ATTR(4),
716 DSB_EDGE_CTRL_ATTR(5),
717 DSB_EDGE_CTRL_ATTR(6),
718 DSB_EDGE_CTRL_ATTR(7),
719 DSB_EDGE_CTRL_ATTR(8),
720 DSB_EDGE_CTRL_ATTR(9),
721 DSB_EDGE_CTRL_ATTR(10),
722 DSB_EDGE_CTRL_ATTR(11),
723 DSB_EDGE_CTRL_ATTR(12),
724 DSB_EDGE_CTRL_ATTR(13),
725 DSB_EDGE_CTRL_ATTR(14),
726 DSB_EDGE_CTRL_ATTR(15),
727 DSB_EDGE_CTRL_MASK_ATTR(0),
728 DSB_EDGE_CTRL_MASK_ATTR(1),
729 DSB_EDGE_CTRL_MASK_ATTR(2),
730 DSB_EDGE_CTRL_MASK_ATTR(3),
731 DSB_EDGE_CTRL_MASK_ATTR(4),
732 DSB_EDGE_CTRL_MASK_ATTR(5),
733 DSB_EDGE_CTRL_MASK_ATTR(6),
734 DSB_EDGE_CTRL_MASK_ATTR(7),
735 NULL,
736};
737
738static struct attribute *tpdm_dsb_trig_patt_attrs[] = {
739 DSB_TRIG_PATT_ATTR(0),
740 DSB_TRIG_PATT_ATTR(1),
741 DSB_TRIG_PATT_ATTR(2),
742 DSB_TRIG_PATT_ATTR(3),
743 DSB_TRIG_PATT_ATTR(4),
744 DSB_TRIG_PATT_ATTR(5),
745 DSB_TRIG_PATT_ATTR(6),
746 DSB_TRIG_PATT_ATTR(7),
747 DSB_TRIG_PATT_MASK_ATTR(0),
748 DSB_TRIG_PATT_MASK_ATTR(1),
749 DSB_TRIG_PATT_MASK_ATTR(2),
750 DSB_TRIG_PATT_MASK_ATTR(3),
751 DSB_TRIG_PATT_MASK_ATTR(4),
752 DSB_TRIG_PATT_MASK_ATTR(5),
753 DSB_TRIG_PATT_MASK_ATTR(6),
754 DSB_TRIG_PATT_MASK_ATTR(7),
755 NULL,
756};
757
758static struct attribute *tpdm_dsb_patt_attrs[] = {
759 DSB_PATT_ATTR(0),
760 DSB_PATT_ATTR(1),
761 DSB_PATT_ATTR(2),
762 DSB_PATT_ATTR(3),
763 DSB_PATT_ATTR(4),
764 DSB_PATT_ATTR(5),
765 DSB_PATT_ATTR(6),
766 DSB_PATT_ATTR(7),
767 DSB_PATT_MASK_ATTR(0),
768 DSB_PATT_MASK_ATTR(1),
769 DSB_PATT_MASK_ATTR(2),
770 DSB_PATT_MASK_ATTR(3),
771 DSB_PATT_MASK_ATTR(4),
772 DSB_PATT_MASK_ATTR(5),
773 DSB_PATT_MASK_ATTR(6),
774 DSB_PATT_MASK_ATTR(7),
775 &dev_attr_enable_ts.attr,
776 &dev_attr_set_type.attr,
777 NULL,
778};
779
780static struct attribute *tpdm_dsb_msr_attrs[] = {
781 DSB_MSR_ATTR(0),
782 DSB_MSR_ATTR(1),
783 DSB_MSR_ATTR(2),
784 DSB_MSR_ATTR(3),
785 DSB_MSR_ATTR(4),
786 DSB_MSR_ATTR(5),
787 DSB_MSR_ATTR(6),
788 DSB_MSR_ATTR(7),
789 DSB_MSR_ATTR(8),
790 DSB_MSR_ATTR(9),
791 DSB_MSR_ATTR(10),
792 DSB_MSR_ATTR(11),
793 DSB_MSR_ATTR(12),
794 DSB_MSR_ATTR(13),
795 DSB_MSR_ATTR(14),
796 DSB_MSR_ATTR(15),
797 DSB_MSR_ATTR(16),
798 DSB_MSR_ATTR(17),
799 DSB_MSR_ATTR(18),
800 DSB_MSR_ATTR(19),
801 DSB_MSR_ATTR(20),
802 DSB_MSR_ATTR(21),
803 DSB_MSR_ATTR(22),
804 DSB_MSR_ATTR(23),
805 DSB_MSR_ATTR(24),
806 DSB_MSR_ATTR(25),
807 DSB_MSR_ATTR(26),
808 DSB_MSR_ATTR(27),
809 DSB_MSR_ATTR(28),
810 DSB_MSR_ATTR(29),
811 DSB_MSR_ATTR(30),
812 DSB_MSR_ATTR(31),
813 NULL,
814};
815
816static struct attribute *tpdm_dsb_attrs[] = {
817 &dev_attr_dsb_mode.attr,
818 &dev_attr_dsb_trig_ts.attr,
819 &dev_attr_dsb_trig_type.attr,
820 NULL,
821};
822
823static struct attribute_group tpdm_dsb_attr_grp = {
824 .attrs = tpdm_dsb_attrs,
825 .is_visible = tpdm_dsb_is_visible,
826};
827
828static struct attribute_group tpdm_dsb_edge_grp = {
829 .attrs = tpdm_dsb_edge_attrs,
830 .is_visible = tpdm_dsb_is_visible,
831 .name = "dsb_edge",
832};
833
834static struct attribute_group tpdm_dsb_trig_patt_grp = {
835 .attrs = tpdm_dsb_trig_patt_attrs,
836 .is_visible = tpdm_dsb_is_visible,
837 .name = "dsb_trig_patt",
838};
839
840static struct attribute_group tpdm_dsb_patt_grp = {
841 .attrs = tpdm_dsb_patt_attrs,
842 .is_visible = tpdm_dsb_is_visible,
843 .name = "dsb_patt",
844};
845
846static struct attribute_group tpdm_dsb_msr_grp = {
847 .attrs = tpdm_dsb_msr_attrs,
848 .is_visible = tpdm_dsb_msr_is_visible,
849 .name = "dsb_msr",
850};
851
852static const struct attribute_group *tpdm_attr_grps[] = {
853 &tpdm_attr_grp,
854 &tpdm_dsb_attr_grp,
855 &tpdm_dsb_edge_grp,
856 &tpdm_dsb_trig_patt_grp,
857 &tpdm_dsb_patt_grp,
858 &tpdm_dsb_msr_grp,
859 NULL,
860};
861
862static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
863{
864 void __iomem *base;
865 struct device *dev = &adev->dev;
866 struct coresight_platform_data *pdata;
867 struct tpdm_drvdata *drvdata;
868 struct coresight_desc desc = { 0 };
869 int ret;
870
871 pdata = coresight_get_platform_data(dev);
872 if (IS_ERR(pdata))
873 return PTR_ERR(pdata);
874 adev->dev.platform_data = pdata;
875
876 /* driver data*/
877 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
878 if (!drvdata)
879 return -ENOMEM;
880 drvdata->dev = &adev->dev;
881 dev_set_drvdata(dev, drvdata);
882
883 base = devm_ioremap_resource(dev, &adev->res);
884 if (IS_ERR(base))
885 return PTR_ERR(base);
886
887 drvdata->base = base;
888
889 ret = tpdm_datasets_setup(drvdata);
890 if (ret)
891 return ret;
892
893 if (drvdata && tpdm_has_dsb_dataset(drvdata))
894 of_property_read_u32(drvdata->dev->of_node,
895 "qcom,dsb-msrs-num", &drvdata->dsb_msr_num);
896
897 /* Set up coresight component description */
898 desc.name = coresight_alloc_device_name(&tpdm_devs, dev);
899 if (!desc.name)
900 return -ENOMEM;
901 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
902 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM;
903 desc.ops = &tpdm_cs_ops;
904 desc.pdata = adev->dev.platform_data;
905 desc.dev = &adev->dev;
906 desc.access = CSDEV_ACCESS_IOMEM(base);
907 desc.groups = tpdm_attr_grps;
908 drvdata->csdev = coresight_register(&desc);
909 if (IS_ERR(drvdata->csdev))
910 return PTR_ERR(drvdata->csdev);
911
912 spin_lock_init(&drvdata->spinlock);
913
914 /* Decrease pm refcount when probe is done.*/
915 pm_runtime_put(&adev->dev);
916
917 return 0;
918}
919
920static void tpdm_remove(struct amba_device *adev)
921{
922 struct tpdm_drvdata *drvdata = dev_get_drvdata(&adev->dev);
923
924 coresight_unregister(drvdata->csdev);
925}
926
927/*
928 * Different TPDM has different periph id.
929 * The difference is 0-7 bits' value. So ignore 0-7 bits.
930 */
931static struct amba_id tpdm_ids[] = {
932 {
933 .id = 0x000f0e00,
934 .mask = 0x000fff00,
935 },
936 { 0, 0},
937};
938
939static struct amba_driver tpdm_driver = {
940 .drv = {
941 .name = "coresight-tpdm",
942 .owner = THIS_MODULE,
943 .suppress_bind_attrs = true,
944 },
945 .probe = tpdm_probe,
946 .id_table = tpdm_ids,
947 .remove = tpdm_remove,
948};
949
950module_amba_driver(tpdm_driver);
951
952MODULE_LICENSE("GPL");
953MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Monitor driver");