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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/acpi.h>
7#include <linux/bitops.h>
8#include <linux/kernel.h>
9#include <linux/moduleparam.h>
10#include <linux/init.h>
11#include <linux/types.h>
12#include <linux/device.h>
13#include <linux/io.h>
14#include <linux/err.h>
15#include <linux/fs.h>
16#include <linux/slab.h>
17#include <linux/delay.h>
18#include <linux/smp.h>
19#include <linux/sysfs.h>
20#include <linux/stat.h>
21#include <linux/clk.h>
22#include <linux/cpu.h>
23#include <linux/cpu_pm.h>
24#include <linux/coresight.h>
25#include <linux/coresight-pmu.h>
26#include <linux/pm_wakeup.h>
27#include <linux/amba/bus.h>
28#include <linux/seq_file.h>
29#include <linux/uaccess.h>
30#include <linux/perf_event.h>
31#include <linux/platform_device.h>
32#include <linux/pm_runtime.h>
33#include <linux/property.h>
34#include <linux/clk/clk-conf.h>
35
36#include <asm/barrier.h>
37#include <asm/sections.h>
38#include <asm/sysreg.h>
39#include <asm/local.h>
40#include <asm/virt.h>
41
42#include "coresight-etm4x.h"
43#include "coresight-etm-perf.h"
44#include "coresight-etm4x-cfg.h"
45#include "coresight-self-hosted-trace.h"
46#include "coresight-syscfg.h"
47#include "coresight-trace-id.h"
48
49static int boot_enable;
50module_param(boot_enable, int, 0444);
51MODULE_PARM_DESC(boot_enable, "Enable tracing on boot");
52
53#define PARAM_PM_SAVE_FIRMWARE 0 /* save self-hosted state as per firmware */
54#define PARAM_PM_SAVE_NEVER 1 /* never save any state */
55#define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */
56
57static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE;
58module_param(pm_save_enable, int, 0444);
59MODULE_PARM_DESC(pm_save_enable,
60 "Save/restore state on power down: 1 = never, 2 = self-hosted");
61
62static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
63static void etm4_set_default_config(struct etmv4_config *config);
64static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
65 struct perf_event *event);
66static u64 etm4_get_access_type(struct etmv4_config *config);
67
68static enum cpuhp_state hp_online;
69
70struct etm4_init_arg {
71 struct device *dev;
72 struct csdev_access *csa;
73};
74
75static DEFINE_PER_CPU(struct etm4_init_arg *, delayed_probe);
76static int etm4_probe_cpu(unsigned int cpu);
77
78/*
79 * Check if TRCSSPCICRn(i) is implemented for a given instance.
80 *
81 * TRCSSPCICRn is implemented only if :
82 * TRCSSPCICR<n> is present only if all of the following are true:
83 * TRCIDR4.NUMSSCC > n.
84 * TRCIDR4.NUMPC > 0b0000 .
85 * TRCSSCSR<n>.PC == 0b1
86 */
87static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n)
88{
89 return (n < drvdata->nr_ss_cmp) &&
90 drvdata->nr_pe &&
91 (drvdata->config.ss_status[n] & TRCSSCSRn_PC);
92}
93
94u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
95{
96 u64 res = 0;
97
98 switch (offset) {
99 ETM4x_READ_SYSREG_CASES(res)
100 default :
101 pr_warn_ratelimited("etm4x: trying to read unsupported register @%x\n",
102 offset);
103 }
104
105 if (!_relaxed)
106 __io_ar(res); /* Imitate the !relaxed I/O helpers */
107
108 return res;
109}
110
111void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
112{
113 if (!_relaxed)
114 __io_bw(); /* Imitate the !relaxed I/O helpers */
115 if (!_64bit)
116 val &= GENMASK(31, 0);
117
118 switch (offset) {
119 ETM4x_WRITE_SYSREG_CASES(val)
120 default :
121 pr_warn_ratelimited("etm4x: trying to write to unsupported register @%x\n",
122 offset);
123 }
124}
125
126static u64 ete_sysreg_read(u32 offset, bool _relaxed, bool _64bit)
127{
128 u64 res = 0;
129
130 switch (offset) {
131 ETE_READ_CASES(res)
132 default :
133 pr_warn_ratelimited("ete: trying to read unsupported register @%x\n",
134 offset);
135 }
136
137 if (!_relaxed)
138 __io_ar(res); /* Imitate the !relaxed I/O helpers */
139
140 return res;
141}
142
143static void ete_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit)
144{
145 if (!_relaxed)
146 __io_bw(); /* Imitate the !relaxed I/O helpers */
147 if (!_64bit)
148 val &= GENMASK(31, 0);
149
150 switch (offset) {
151 ETE_WRITE_CASES(val)
152 default :
153 pr_warn_ratelimited("ete: trying to write to unsupported register @%x\n",
154 offset);
155 }
156}
157
158static void etm_detect_os_lock(struct etmv4_drvdata *drvdata,
159 struct csdev_access *csa)
160{
161 u32 oslsr = etm4x_relaxed_read32(csa, TRCOSLSR);
162
163 drvdata->os_lock_model = ETM_OSLSR_OSLM(oslsr);
164}
165
166static void etm_write_os_lock(struct etmv4_drvdata *drvdata,
167 struct csdev_access *csa, u32 val)
168{
169 val = !!val;
170
171 switch (drvdata->os_lock_model) {
172 case ETM_OSLOCK_PRESENT:
173 etm4x_relaxed_write32(csa, val, TRCOSLAR);
174 break;
175 case ETM_OSLOCK_PE:
176 write_sysreg_s(val, SYS_OSLAR_EL1);
177 break;
178 default:
179 pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n",
180 smp_processor_id(), drvdata->os_lock_model);
181 fallthrough;
182 case ETM_OSLOCK_NI:
183 return;
184 }
185 isb();
186}
187
188static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata,
189 struct csdev_access *csa)
190{
191 WARN_ON(drvdata->cpu != smp_processor_id());
192
193 /* Writing 0 to OS Lock unlocks the trace unit registers */
194 etm_write_os_lock(drvdata, csa, 0x0);
195 drvdata->os_unlock = true;
196}
197
198static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
199{
200 if (!WARN_ON(!drvdata->csdev))
201 etm4_os_unlock_csa(drvdata, &drvdata->csdev->access);
202}
203
204static void etm4_os_lock(struct etmv4_drvdata *drvdata)
205{
206 if (WARN_ON(!drvdata->csdev))
207 return;
208 /* Writing 0x1 to OS Lock locks the trace registers */
209 etm_write_os_lock(drvdata, &drvdata->csdev->access, 0x1);
210 drvdata->os_unlock = false;
211}
212
213static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
214 struct csdev_access *csa)
215{
216 /* Software Lock is only accessible via memory mapped interface */
217 if (csa->io_mem)
218 CS_LOCK(csa->base);
219}
220
221static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
222 struct csdev_access *csa)
223{
224 if (csa->io_mem)
225 CS_UNLOCK(csa->base);
226}
227
228static int etm4_cpu_id(struct coresight_device *csdev)
229{
230 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
231
232 return drvdata->cpu;
233}
234
235int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata)
236{
237 int trace_id;
238
239 /*
240 * This will allocate a trace ID to the cpu,
241 * or return the one currently allocated.
242 * The trace id function has its own lock
243 */
244 trace_id = coresight_trace_id_get_cpu_id(drvdata->cpu);
245 if (IS_VALID_CS_TRACE_ID(trace_id))
246 drvdata->trcid = (u8)trace_id;
247 else
248 dev_err(&drvdata->csdev->dev,
249 "Failed to allocate trace ID for %s on CPU%d\n",
250 dev_name(&drvdata->csdev->dev), drvdata->cpu);
251 return trace_id;
252}
253
254void etm4_release_trace_id(struct etmv4_drvdata *drvdata)
255{
256 coresight_trace_id_put_cpu_id(drvdata->cpu);
257}
258
259struct etm4_enable_arg {
260 struct etmv4_drvdata *drvdata;
261 int rc;
262};
263
264/*
265 * etm4x_prohibit_trace - Prohibit the CPU from tracing at all ELs.
266 * When the CPU supports FEAT_TRF, we could move the ETM to a trace
267 * prohibited state by filtering the Exception levels via TRFCR_EL1.
268 */
269static void etm4x_prohibit_trace(struct etmv4_drvdata *drvdata)
270{
271 /* If the CPU doesn't support FEAT_TRF, nothing to do */
272 if (!drvdata->trfcr)
273 return;
274 cpu_prohibit_trace();
275}
276
277/*
278 * etm4x_allow_trace - Allow CPU tracing in the respective ELs,
279 * as configured by the drvdata->config.mode for the current
280 * session. Even though we have TRCVICTLR bits to filter the
281 * trace in the ELs, it doesn't prevent the ETM from generating
282 * a packet (e.g, TraceInfo) that might contain the addresses from
283 * the excluded levels. Thus we use the additional controls provided
284 * via the Trace Filtering controls (FEAT_TRF) to make sure no trace
285 * is generated for the excluded ELs.
286 */
287static void etm4x_allow_trace(struct etmv4_drvdata *drvdata)
288{
289 u64 trfcr = drvdata->trfcr;
290
291 /* If the CPU doesn't support FEAT_TRF, nothing to do */
292 if (!trfcr)
293 return;
294
295 if (drvdata->config.mode & ETM_MODE_EXCL_KERN)
296 trfcr &= ~TRFCR_ELx_ExTRE;
297 if (drvdata->config.mode & ETM_MODE_EXCL_USER)
298 trfcr &= ~TRFCR_ELx_E0TRE;
299
300 write_trfcr(trfcr);
301}
302
303#ifdef CONFIG_ETM4X_IMPDEF_FEATURE
304
305#define HISI_HIP08_AMBA_ID 0x000b6d01
306#define ETM4_AMBA_MASK 0xfffff
307#define HISI_HIP08_CORE_COMMIT_MASK 0x3000
308#define HISI_HIP08_CORE_COMMIT_SHIFT 12
309#define HISI_HIP08_CORE_COMMIT_FULL 0b00
310#define HISI_HIP08_CORE_COMMIT_LVL_1 0b01
311#define HISI_HIP08_CORE_COMMIT_REG sys_reg(3, 1, 15, 2, 5)
312
313struct etm4_arch_features {
314 void (*arch_callback)(bool enable);
315};
316
317static bool etm4_hisi_match_pid(unsigned int id)
318{
319 return (id & ETM4_AMBA_MASK) == HISI_HIP08_AMBA_ID;
320}
321
322static void etm4_hisi_config_core_commit(bool enable)
323{
324 u8 commit = enable ? HISI_HIP08_CORE_COMMIT_LVL_1 :
325 HISI_HIP08_CORE_COMMIT_FULL;
326 u64 val;
327
328 /*
329 * bit 12 and 13 of HISI_HIP08_CORE_COMMIT_REG are used together
330 * to set core-commit, 2'b00 means cpu is at full speed, 2'b01,
331 * 2'b10, 2'b11 mean reduce pipeline speed, and 2'b01 means level-1
332 * speed(minimun value). So bit 12 and 13 should be cleared together.
333 */
334 val = read_sysreg_s(HISI_HIP08_CORE_COMMIT_REG);
335 val &= ~HISI_HIP08_CORE_COMMIT_MASK;
336 val |= commit << HISI_HIP08_CORE_COMMIT_SHIFT;
337 write_sysreg_s(val, HISI_HIP08_CORE_COMMIT_REG);
338}
339
340static struct etm4_arch_features etm4_features[] = {
341 [ETM4_IMPDEF_HISI_CORE_COMMIT] = {
342 .arch_callback = etm4_hisi_config_core_commit,
343 },
344 {},
345};
346
347static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
348{
349 struct etm4_arch_features *ftr;
350 int bit;
351
352 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
353 ftr = &etm4_features[bit];
354
355 if (ftr->arch_callback)
356 ftr->arch_callback(true);
357 }
358}
359
360static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
361{
362 struct etm4_arch_features *ftr;
363 int bit;
364
365 for_each_set_bit(bit, drvdata->arch_features, ETM4_IMPDEF_FEATURE_MAX) {
366 ftr = &etm4_features[bit];
367
368 if (ftr->arch_callback)
369 ftr->arch_callback(false);
370 }
371}
372
373static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
374 struct csdev_access *csa)
375{
376 /*
377 * TRCPIDR* registers are not required for ETMs with system
378 * instructions. They must be identified by the MIDR+REVIDRs.
379 * Skip the TRCPID checks for now.
380 */
381 if (!csa->io_mem)
382 return;
383
384 if (etm4_hisi_match_pid(coresight_get_pid(csa)))
385 set_bit(ETM4_IMPDEF_HISI_CORE_COMMIT, drvdata->arch_features);
386}
387#else
388static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata)
389{
390}
391
392static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata)
393{
394}
395
396static void etm4_check_arch_features(struct etmv4_drvdata *drvdata,
397 struct csdev_access *csa)
398{
399}
400#endif /* CONFIG_ETM4X_IMPDEF_FEATURE */
401
402static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
403{
404 int i, rc;
405 struct etmv4_config *config = &drvdata->config;
406 struct coresight_device *csdev = drvdata->csdev;
407 struct device *etm_dev = &csdev->dev;
408 struct csdev_access *csa = &csdev->access;
409
410
411 etm4_cs_unlock(drvdata, csa);
412 etm4_enable_arch_specific(drvdata);
413
414 etm4_os_unlock(drvdata);
415
416 rc = coresight_claim_device_unlocked(csdev);
417 if (rc)
418 goto done;
419
420 /* Disable the trace unit before programming trace registers */
421 etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
422
423 /*
424 * If we use system instructions, we need to synchronize the
425 * write to the TRCPRGCTLR, before accessing the TRCSTATR.
426 * See ARM IHI0064F, section
427 * "4.3.7 Synchronization of register updates"
428 */
429 if (!csa->io_mem)
430 isb();
431
432 /* wait for TRCSTATR.IDLE to go up */
433 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
434 dev_err(etm_dev,
435 "timeout while waiting for Idle Trace Status\n");
436 if (drvdata->nr_pe)
437 etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR);
438 etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR);
439 /* nothing specific implemented */
440 etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR);
441 etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R);
442 etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R);
443 if (drvdata->stallctl)
444 etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR);
445 etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR);
446 etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR);
447 etm4x_relaxed_write32(csa, config->ccctlr, TRCCCCTLR);
448 etm4x_relaxed_write32(csa, config->bb_ctrl, TRCBBCTLR);
449 etm4x_relaxed_write32(csa, drvdata->trcid, TRCTRACEIDR);
450 etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR);
451 etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR);
452 etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR);
453 if (drvdata->nr_pe_cmp)
454 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR);
455 for (i = 0; i < drvdata->nrseqstate - 1; i++)
456 etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i));
457 if (drvdata->nrseqstate) {
458 etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR);
459 etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR);
460 }
461 etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR);
462 for (i = 0; i < drvdata->nr_cntr; i++) {
463 etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i));
464 etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i));
465 etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i));
466 }
467
468 /*
469 * Resource selector pair 0 is always implemented and reserved. As
470 * such start at 2.
471 */
472 for (i = 2; i < drvdata->nr_resource * 2; i++)
473 etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i));
474
475 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
476 /* always clear status bit on restart if using single-shot */
477 if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
478 config->ss_status[i] &= ~TRCSSCSRn_STATUS;
479 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i));
480 etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i));
481 if (etm4x_sspcicrn_present(drvdata, i))
482 etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));
483 }
484 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
485 etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
486 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
487 }
488 for (i = 0; i < drvdata->numcidc; i++)
489 etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i));
490 etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0);
491 if (drvdata->numcidc > 4)
492 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1);
493
494 for (i = 0; i < drvdata->numvmidc; i++)
495 etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i));
496 etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0);
497 if (drvdata->numvmidc > 4)
498 etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1);
499
500 if (!drvdata->skip_power_up) {
501 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR);
502
503 /*
504 * Request to keep the trace unit powered and also
505 * emulation of powerdown
506 */
507 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
508 }
509
510 /*
511 * ETE mandates that the TRCRSR is written to before
512 * enabling it.
513 */
514 if (etm4x_is_ete(drvdata))
515 etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
516
517 etm4x_allow_trace(drvdata);
518 /* Enable the trace unit */
519 etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
520
521 /* Synchronize the register updates for sysreg access */
522 if (!csa->io_mem)
523 isb();
524
525 /* wait for TRCSTATR.IDLE to go back down to '0' */
526 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
527 dev_err(etm_dev,
528 "timeout while waiting for Idle Trace Status\n");
529
530 /*
531 * As recommended by section 4.3.7 ("Synchronization when using the
532 * memory-mapped interface") of ARM IHI 0064D
533 */
534 dsb(sy);
535 isb();
536
537done:
538 etm4_cs_lock(drvdata, csa);
539
540 dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
541 drvdata->cpu, rc);
542 return rc;
543}
544
545static void etm4_enable_hw_smp_call(void *info)
546{
547 struct etm4_enable_arg *arg = info;
548
549 if (WARN_ON(!arg))
550 return;
551 arg->rc = etm4_enable_hw(arg->drvdata);
552}
553
554/*
555 * The goal of function etm4_config_timestamp_event() is to configure a
556 * counter that will tell the tracer to emit a timestamp packet when it
557 * reaches zero. This is done in order to get a more fine grained idea
558 * of when instructions are executed so that they can be correlated
559 * with execution on other CPUs.
560 *
561 * To do this the counter itself is configured to self reload and
562 * TRCRSCTLR1 (always true) used to get the counter to decrement. From
563 * there a resource selector is configured with the counter and the
564 * timestamp control register to use the resource selector to trigger the
565 * event that will insert a timestamp packet in the stream.
566 */
567static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
568{
569 int ctridx, ret = -EINVAL;
570 int counter, rselector;
571 u32 val = 0;
572 struct etmv4_config *config = &drvdata->config;
573
574 /* No point in trying if we don't have at least one counter */
575 if (!drvdata->nr_cntr)
576 goto out;
577
578 /* Find a counter that hasn't been initialised */
579 for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
580 if (config->cntr_val[ctridx] == 0)
581 break;
582
583 /* All the counters have been configured already, bail out */
584 if (ctridx == drvdata->nr_cntr) {
585 pr_debug("%s: no available counter found\n", __func__);
586 ret = -ENOSPC;
587 goto out;
588 }
589
590 /*
591 * Searching for an available resource selector to use, starting at
592 * '2' since every implementation has at least 2 resource selector.
593 * ETMIDR4 gives the number of resource selector _pairs_,
594 * hence multiply by 2.
595 */
596 for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
597 if (!config->res_ctrl[rselector])
598 break;
599
600 if (rselector == drvdata->nr_resource * 2) {
601 pr_debug("%s: no available resource selector found\n",
602 __func__);
603 ret = -ENOSPC;
604 goto out;
605 }
606
607 /* Remember what counter we used */
608 counter = 1 << ctridx;
609
610 /*
611 * Initialise original and reload counter value to the smallest
612 * possible value in order to get as much precision as we can.
613 */
614 config->cntr_val[ctridx] = 1;
615 config->cntrldvr[ctridx] = 1;
616
617 /* Set the trace counter control register */
618 val = 0x1 << 16 | /* Bit 16, reload counter automatically */
619 0x0 << 7 | /* Select single resource selector */
620 0x1; /* Resource selector 1, i.e always true */
621
622 config->cntr_ctrl[ctridx] = val;
623
624 val = 0x2 << 16 | /* Group 0b0010 - Counter and sequencers */
625 counter << 0; /* Counter to use */
626
627 config->res_ctrl[rselector] = val;
628
629 val = 0x0 << 7 | /* Select single resource selector */
630 rselector; /* Resource selector */
631
632 config->ts_ctrl = val;
633
634 ret = 0;
635out:
636 return ret;
637}
638
639static int etm4_parse_event_config(struct coresight_device *csdev,
640 struct perf_event *event)
641{
642 int ret = 0;
643 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
644 struct etmv4_config *config = &drvdata->config;
645 struct perf_event_attr *attr = &event->attr;
646 unsigned long cfg_hash;
647 int preset, cc_threshold;
648
649 /* Clear configuration from previous run */
650 memset(config, 0, sizeof(struct etmv4_config));
651
652 if (attr->exclude_kernel)
653 config->mode = ETM_MODE_EXCL_KERN;
654
655 if (attr->exclude_user)
656 config->mode = ETM_MODE_EXCL_USER;
657
658 /* Always start from the default config */
659 etm4_set_default_config(config);
660
661 /* Configure filters specified on the perf cmd line, if any. */
662 ret = etm4_set_event_filters(drvdata, event);
663 if (ret)
664 goto out;
665
666 /* Go from generic option to ETMv4 specifics */
667 if (attr->config & BIT(ETM_OPT_CYCACC)) {
668 config->cfg |= TRCCONFIGR_CCI;
669 /* TRM: Must program this for cycacc to work */
670 cc_threshold = attr->config3 & ETM_CYC_THRESHOLD_MASK;
671 if (!cc_threshold)
672 cc_threshold = ETM_CYC_THRESHOLD_DEFAULT;
673 if (cc_threshold < drvdata->ccitmin)
674 cc_threshold = drvdata->ccitmin;
675 config->ccctlr = cc_threshold;
676 }
677 if (attr->config & BIT(ETM_OPT_TS)) {
678 /*
679 * Configure timestamps to be emitted at regular intervals in
680 * order to correlate instructions executed on different CPUs
681 * (CPU-wide trace scenarios).
682 */
683 ret = etm4_config_timestamp_event(drvdata);
684
685 /*
686 * No need to go further if timestamp intervals can't
687 * be configured.
688 */
689 if (ret)
690 goto out;
691
692 /* bit[11], Global timestamp tracing bit */
693 config->cfg |= TRCCONFIGR_TS;
694 }
695
696 /* Only trace contextID when runs in root PID namespace */
697 if ((attr->config & BIT(ETM_OPT_CTXTID)) &&
698 task_is_in_init_pid_ns(current))
699 /* bit[6], Context ID tracing bit */
700 config->cfg |= TRCCONFIGR_CID;
701
702 /*
703 * If set bit ETM_OPT_CTXTID2 in perf config, this asks to trace VMID
704 * for recording CONTEXTIDR_EL2. Do not enable VMID tracing if the
705 * kernel is not running in EL2.
706 */
707 if (attr->config & BIT(ETM_OPT_CTXTID2)) {
708 if (!is_kernel_in_hyp_mode()) {
709 ret = -EINVAL;
710 goto out;
711 }
712 /* Only trace virtual contextID when runs in root PID namespace */
713 if (task_is_in_init_pid_ns(current))
714 config->cfg |= TRCCONFIGR_VMID | TRCCONFIGR_VMIDOPT;
715 }
716
717 /* return stack - enable if selected and supported */
718 if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
719 /* bit[12], Return stack enable bit */
720 config->cfg |= TRCCONFIGR_RS;
721
722 /*
723 * Set any selected configuration and preset.
724 *
725 * This extracts the values of PMU_FORMAT_ATTR(configid) and PMU_FORMAT_ATTR(preset)
726 * in the perf attributes defined in coresight-etm-perf.c.
727 * configid uses bits 63:32 of attr->config2, preset uses bits 3:0 of attr->config.
728 * A zero configid means no configuration active, preset = 0 means no preset selected.
729 */
730 if (attr->config2 & GENMASK_ULL(63, 32)) {
731 cfg_hash = (u32)(attr->config2 >> 32);
732 preset = attr->config & 0xF;
733 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
734 }
735
736 /* branch broadcast - enable if selected and supported */
737 if (attr->config & BIT(ETM_OPT_BRANCH_BROADCAST)) {
738 if (!drvdata->trcbb) {
739 /*
740 * Missing BB support could cause silent decode errors
741 * so fail to open if it's not supported.
742 */
743 ret = -EINVAL;
744 goto out;
745 } else {
746 config->cfg |= BIT(ETM4_CFG_BIT_BB);
747 }
748 }
749
750out:
751 return ret;
752}
753
754static int etm4_enable_perf(struct coresight_device *csdev,
755 struct perf_event *event)
756{
757 int ret = 0, trace_id;
758 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
759
760 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
761 ret = -EINVAL;
762 goto out;
763 }
764
765 /* Configure the tracer based on the session's specifics */
766 ret = etm4_parse_event_config(csdev, event);
767 if (ret)
768 goto out;
769
770 /*
771 * perf allocates cpu ids as part of _setup_aux() - device needs to use
772 * the allocated ID. This reads the current version without allocation.
773 *
774 * This does not use the trace id lock to prevent lock_dep issues
775 * with perf locks - we know the ID cannot change until perf shuts down
776 * the session
777 */
778 trace_id = coresight_trace_id_read_cpu_id(drvdata->cpu);
779 if (!IS_VALID_CS_TRACE_ID(trace_id)) {
780 dev_err(&drvdata->csdev->dev, "Failed to set trace ID for %s on CPU%d\n",
781 dev_name(&drvdata->csdev->dev), drvdata->cpu);
782 ret = -EINVAL;
783 goto out;
784 }
785 drvdata->trcid = (u8)trace_id;
786
787 /* And enable it */
788 ret = etm4_enable_hw(drvdata);
789
790out:
791 return ret;
792}
793
794static int etm4_enable_sysfs(struct coresight_device *csdev)
795{
796 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
797 struct etm4_enable_arg arg = { };
798 unsigned long cfg_hash;
799 int ret, preset;
800
801 /* enable any config activated by configfs */
802 cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset);
803 if (cfg_hash) {
804 ret = cscfg_csdev_enable_active_config(csdev, cfg_hash, preset);
805 if (ret)
806 return ret;
807 }
808
809 spin_lock(&drvdata->spinlock);
810
811 /* sysfs needs to read and allocate a trace ID */
812 ret = etm4_read_alloc_trace_id(drvdata);
813 if (ret < 0)
814 goto unlock_sysfs_enable;
815
816 /*
817 * Executing etm4_enable_hw on the cpu whose ETM is being enabled
818 * ensures that register writes occur when cpu is powered.
819 */
820 arg.drvdata = drvdata;
821 ret = smp_call_function_single(drvdata->cpu,
822 etm4_enable_hw_smp_call, &arg, 1);
823 if (!ret)
824 ret = arg.rc;
825 if (!ret)
826 drvdata->sticky_enable = true;
827
828 if (ret)
829 etm4_release_trace_id(drvdata);
830
831unlock_sysfs_enable:
832 spin_unlock(&drvdata->spinlock);
833
834 if (!ret)
835 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
836 return ret;
837}
838
839static int etm4_enable(struct coresight_device *csdev, struct perf_event *event,
840 enum cs_mode mode)
841{
842 int ret;
843 u32 val;
844 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
845
846 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
847
848 /* Someone is already using the tracer */
849 if (val)
850 return -EBUSY;
851
852 switch (mode) {
853 case CS_MODE_SYSFS:
854 ret = etm4_enable_sysfs(csdev);
855 break;
856 case CS_MODE_PERF:
857 ret = etm4_enable_perf(csdev, event);
858 break;
859 default:
860 ret = -EINVAL;
861 }
862
863 /* The tracer didn't start */
864 if (ret)
865 local_set(&drvdata->mode, CS_MODE_DISABLED);
866
867 return ret;
868}
869
870static void etm4_disable_hw(void *info)
871{
872 u32 control;
873 struct etmv4_drvdata *drvdata = info;
874 struct etmv4_config *config = &drvdata->config;
875 struct coresight_device *csdev = drvdata->csdev;
876 struct device *etm_dev = &csdev->dev;
877 struct csdev_access *csa = &csdev->access;
878 int i;
879
880 etm4_cs_unlock(drvdata, csa);
881 etm4_disable_arch_specific(drvdata);
882
883 if (!drvdata->skip_power_up) {
884 /* power can be removed from the trace unit now */
885 control = etm4x_relaxed_read32(csa, TRCPDCR);
886 control &= ~TRCPDCR_PU;
887 etm4x_relaxed_write32(csa, control, TRCPDCR);
888 }
889
890 control = etm4x_relaxed_read32(csa, TRCPRGCTLR);
891
892 /* EN, bit[0] Trace unit enable bit */
893 control &= ~0x1;
894
895 /*
896 * If the CPU supports v8.4 Trace filter Control,
897 * set the ETM to trace prohibited region.
898 */
899 etm4x_prohibit_trace(drvdata);
900 /*
901 * Make sure everything completes before disabling, as recommended
902 * by section 7.3.77 ("TRCVICTLR, ViewInst Main Control Register,
903 * SSTATUS") of ARM IHI 0064D
904 */
905 dsb(sy);
906 isb();
907 /* Trace synchronization barrier, is a nop if not supported */
908 tsb_csync();
909 etm4x_relaxed_write32(csa, control, TRCPRGCTLR);
910
911 /* wait for TRCSTATR.PMSTABLE to go to '1' */
912 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1))
913 dev_err(etm_dev,
914 "timeout while waiting for PM stable Trace Status\n");
915 /* read the status of the single shot comparators */
916 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
917 config->ss_status[i] =
918 etm4x_relaxed_read32(csa, TRCSSCSRn(i));
919 }
920
921 /* read back the current counter values */
922 for (i = 0; i < drvdata->nr_cntr; i++) {
923 config->cntr_val[i] =
924 etm4x_relaxed_read32(csa, TRCCNTVRn(i));
925 }
926
927 coresight_disclaim_device_unlocked(csdev);
928 etm4_cs_lock(drvdata, csa);
929
930 dev_dbg(&drvdata->csdev->dev,
931 "cpu: %d disable smp call done\n", drvdata->cpu);
932}
933
934static int etm4_disable_perf(struct coresight_device *csdev,
935 struct perf_event *event)
936{
937 u32 control;
938 struct etm_filters *filters = event->hw.addr_filters;
939 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
940 struct perf_event_attr *attr = &event->attr;
941
942 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
943 return -EINVAL;
944
945 etm4_disable_hw(drvdata);
946 /*
947 * The config_id occupies bits 63:32 of the config2 perf event attr
948 * field. If this is non-zero then we will have enabled a config.
949 */
950 if (attr->config2 & GENMASK_ULL(63, 32))
951 cscfg_csdev_disable_active_config(csdev);
952
953 /*
954 * Check if the start/stop logic was active when the unit was stopped.
955 * That way we can re-enable the start/stop logic when the process is
956 * scheduled again. Configuration of the start/stop logic happens in
957 * function etm4_set_event_filters().
958 */
959 control = etm4x_relaxed_read32(&csdev->access, TRCVICTLR);
960 /* TRCVICTLR::SSSTATUS, bit[9] */
961 filters->ssstatus = (control & BIT(9));
962
963 /*
964 * perf will release trace ids when _free_aux() is
965 * called at the end of the session.
966 */
967
968 return 0;
969}
970
971static void etm4_disable_sysfs(struct coresight_device *csdev)
972{
973 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
974
975 /*
976 * Taking hotplug lock here protects from clocks getting disabled
977 * with tracing being left on (crash scenario) if user disable occurs
978 * after cpu online mask indicates the cpu is offline but before the
979 * DYING hotplug callback is serviced by the ETM driver.
980 */
981 cpus_read_lock();
982 spin_lock(&drvdata->spinlock);
983
984 /*
985 * Executing etm4_disable_hw on the cpu whose ETM is being disabled
986 * ensures that register writes occur when cpu is powered.
987 */
988 smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
989
990 spin_unlock(&drvdata->spinlock);
991 cpus_read_unlock();
992
993 /*
994 * we only release trace IDs when resetting sysfs.
995 * This permits sysfs users to read the trace ID after the trace
996 * session has completed. This maintains operational behaviour with
997 * prior trace id allocation method
998 */
999
1000 dev_dbg(&csdev->dev, "ETM tracing disabled\n");
1001}
1002
1003static void etm4_disable(struct coresight_device *csdev,
1004 struct perf_event *event)
1005{
1006 enum cs_mode mode;
1007 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
1008
1009 /*
1010 * For as long as the tracer isn't disabled another entity can't
1011 * change its status. As such we can read the status here without
1012 * fearing it will change under us.
1013 */
1014 mode = local_read(&drvdata->mode);
1015
1016 switch (mode) {
1017 case CS_MODE_DISABLED:
1018 break;
1019 case CS_MODE_SYSFS:
1020 etm4_disable_sysfs(csdev);
1021 break;
1022 case CS_MODE_PERF:
1023 etm4_disable_perf(csdev, event);
1024 break;
1025 }
1026
1027 if (mode)
1028 local_set(&drvdata->mode, CS_MODE_DISABLED);
1029}
1030
1031static const struct coresight_ops_source etm4_source_ops = {
1032 .cpu_id = etm4_cpu_id,
1033 .enable = etm4_enable,
1034 .disable = etm4_disable,
1035};
1036
1037static const struct coresight_ops etm4_cs_ops = {
1038 .source_ops = &etm4_source_ops,
1039};
1040
1041static inline bool cpu_supports_sysreg_trace(void)
1042{
1043 u64 dfr0 = read_sysreg_s(SYS_ID_AA64DFR0_EL1);
1044
1045 return ((dfr0 >> ID_AA64DFR0_EL1_TraceVer_SHIFT) & 0xfUL) > 0;
1046}
1047
1048static bool etm4_init_sysreg_access(struct etmv4_drvdata *drvdata,
1049 struct csdev_access *csa)
1050{
1051 u32 devarch;
1052
1053 if (!cpu_supports_sysreg_trace())
1054 return false;
1055
1056 /*
1057 * ETMs implementing sysreg access must implement TRCDEVARCH.
1058 */
1059 devarch = read_etm4x_sysreg_const_offset(TRCDEVARCH);
1060 switch (devarch & ETM_DEVARCH_ID_MASK) {
1061 case ETM_DEVARCH_ETMv4x_ARCH:
1062 *csa = (struct csdev_access) {
1063 .io_mem = false,
1064 .read = etm4x_sysreg_read,
1065 .write = etm4x_sysreg_write,
1066 };
1067 break;
1068 case ETM_DEVARCH_ETE_ARCH:
1069 *csa = (struct csdev_access) {
1070 .io_mem = false,
1071 .read = ete_sysreg_read,
1072 .write = ete_sysreg_write,
1073 };
1074 break;
1075 default:
1076 return false;
1077 }
1078
1079 drvdata->arch = etm_devarch_to_arch(devarch);
1080 return true;
1081}
1082
1083static bool is_devtype_cpu_trace(void __iomem *base)
1084{
1085 u32 devtype = readl(base + TRCDEVTYPE);
1086
1087 return (devtype == CS_DEVTYPE_PE_TRACE);
1088}
1089
1090static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata,
1091 struct csdev_access *csa)
1092{
1093 u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);
1094
1095 if (!is_coresight_device(drvdata->base) || !is_devtype_cpu_trace(drvdata->base))
1096 return false;
1097
1098 /*
1099 * All ETMs must implement TRCDEVARCH to indicate that
1100 * the component is an ETMv4. Even though TRCIDR1 also
1101 * contains the information, it is part of the "Trace"
1102 * register and must be accessed with the OSLK cleared,
1103 * with MMIO. But we cannot touch the OSLK until we are
1104 * sure this is an ETM. So rely only on the TRCDEVARCH.
1105 */
1106 if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) {
1107 pr_warn_once("TRCDEVARCH doesn't match ETMv4 architecture\n");
1108 return false;
1109 }
1110
1111 drvdata->arch = etm_devarch_to_arch(devarch);
1112 *csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1113 return true;
1114}
1115
1116static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
1117 struct csdev_access *csa)
1118{
1119 /*
1120 * Always choose the memory mapped io, if there is
1121 * a memory map to prevent sysreg access on broken
1122 * systems.
1123 */
1124 if (drvdata->base)
1125 return etm4_init_iomem_access(drvdata, csa);
1126
1127 if (etm4_init_sysreg_access(drvdata, csa))
1128 return true;
1129
1130 return false;
1131}
1132
1133static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata)
1134{
1135 u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
1136 u64 trfcr;
1137
1138 drvdata->trfcr = 0;
1139 if (!cpuid_feature_extract_unsigned_field(dfr0, ID_AA64DFR0_EL1_TraceFilt_SHIFT))
1140 return;
1141
1142 /*
1143 * If the CPU supports v8.4 SelfHosted Tracing, enable
1144 * tracing at the kernel EL and EL0, forcing to use the
1145 * virtual time as the timestamp.
1146 */
1147 trfcr = (TRFCR_ELx_TS_VIRTUAL |
1148 TRFCR_ELx_ExTRE |
1149 TRFCR_ELx_E0TRE);
1150
1151 /* If we are running at EL2, allow tracing the CONTEXTIDR_EL2. */
1152 if (is_kernel_in_hyp_mode())
1153 trfcr |= TRFCR_EL2_CX;
1154
1155 drvdata->trfcr = trfcr;
1156}
1157
1158/*
1159 * The following errata on applicable cpu ranges, affect the CCITMIN filed
1160 * in TCRIDR3 register. Software read for the field returns 0x100 limiting
1161 * the cycle threshold granularity, whereas the right value should have
1162 * been 0x4, which is well supported in the hardware.
1163 */
1164static struct midr_range etm_wrong_ccitmin_cpus[] = {
1165 /* Erratum #1490853 - Cortex-A76 */
1166 MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 4, 0),
1167 /* Erratum #1490853 - Neoverse-N1 */
1168 MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 4, 0),
1169 /* Erratum #1491015 - Cortex-A77 */
1170 MIDR_RANGE(MIDR_CORTEX_A77, 0, 0, 1, 0),
1171 /* Erratum #1502854 - Cortex-X1 */
1172 MIDR_REV(MIDR_CORTEX_X1, 0, 0),
1173 /* Erratum #1619801 - Neoverse-V1 */
1174 MIDR_REV(MIDR_NEOVERSE_V1, 0, 0),
1175 {},
1176};
1177
1178static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata)
1179{
1180 /*
1181 * Erratum affected cpus will read 256 as the minimum
1182 * instruction trace cycle counting threshold whereas
1183 * the correct value should be 4 instead. Override the
1184 * recorded value for 'drvdata->ccitmin' to workaround
1185 * this problem.
1186 */
1187 if (is_midr_in_range_list(read_cpuid_id(), etm_wrong_ccitmin_cpus)) {
1188 if (drvdata->ccitmin == 256)
1189 drvdata->ccitmin = 4;
1190 }
1191}
1192
1193static void etm4_init_arch_data(void *info)
1194{
1195 u32 etmidr0;
1196 u32 etmidr2;
1197 u32 etmidr3;
1198 u32 etmidr4;
1199 u32 etmidr5;
1200 struct etm4_init_arg *init_arg = info;
1201 struct etmv4_drvdata *drvdata;
1202 struct csdev_access *csa;
1203 int i;
1204
1205 drvdata = dev_get_drvdata(init_arg->dev);
1206 csa = init_arg->csa;
1207
1208 /*
1209 * If we are unable to detect the access mechanism,
1210 * or unable to detect the trace unit type, fail
1211 * early.
1212 */
1213 if (!etm4_init_csdev_access(drvdata, csa))
1214 return;
1215
1216 /* Detect the support for OS Lock before we actually use it */
1217 etm_detect_os_lock(drvdata, csa);
1218
1219 /* Make sure all registers are accessible */
1220 etm4_os_unlock_csa(drvdata, csa);
1221 etm4_cs_unlock(drvdata, csa);
1222
1223 etm4_check_arch_features(drvdata, csa);
1224
1225 /* find all capabilities of the tracing unit */
1226 etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
1227
1228 /* INSTP0, bits[2:1] P0 tracing support field */
1229 drvdata->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11);
1230 /* TRCBB, bit[5] Branch broadcast tracing support bit */
1231 drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
1232 /* TRCCOND, bit[6] Conditional instruction tracing support bit */
1233 drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
1234 /* TRCCCI, bit[7] Cycle counting instruction bit */
1235 drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
1236 /* RETSTACK, bit[9] Return stack bit */
1237 drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
1238 /* NUMEVENT, bits[11:10] Number of events field */
1239 drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0);
1240 /* QSUPP, bits[16:15] Q element support field */
1241 drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0);
1242 /* TSSIZE, bits[28:24] Global timestamp size field */
1243 drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0);
1244
1245 /* maximum size of resources */
1246 etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
1247 /* CIDSIZE, bits[9:5] Indicates the Context ID size */
1248 drvdata->ctxid_size = FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2);
1249 /* VMIDSIZE, bits[14:10] Indicates the VMID size */
1250 drvdata->vmid_size = FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2);
1251 /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
1252 drvdata->ccsize = FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2);
1253
1254 etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
1255 /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
1256 drvdata->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3);
1257 etm4_fixup_wrong_ccitmin(drvdata);
1258
1259 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
1260 drvdata->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3);
1261 drvdata->config.s_ex_level = drvdata->s_ex_level;
1262 /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
1263 drvdata->ns_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3);
1264 /*
1265 * TRCERR, bit[24] whether a trace unit can trace a
1266 * system error exception.
1267 */
1268 drvdata->trc_error = !!(etmidr3 & TRCIDR3_TRCERR);
1269 /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
1270 drvdata->syncpr = !!(etmidr3 & TRCIDR3_SYNCPR);
1271 /* STALLCTL, bit[26] is stall control implemented? */
1272 drvdata->stallctl = !!(etmidr3 & TRCIDR3_STALLCTL);
1273 /* SYSSTALL, bit[27] implementation can support stall control? */
1274 drvdata->sysstall = !!(etmidr3 & TRCIDR3_SYSSTALL);
1275 /*
1276 * NUMPROC - the number of PEs available for tracing, 5bits
1277 * = TRCIDR3.bits[13:12]bits[30:28]
1278 * bits[4:3] = TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0)
1279 * bits[3:0] = TRCIDR3.bits[30:28]
1280 */
1281 drvdata->nr_pe = (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) |
1282 FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3);
1283 /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
1284 drvdata->nooverflow = !!(etmidr3 & TRCIDR3_NOOVERFLOW);
1285
1286 /* number of resources trace unit supports */
1287 etmidr4 = etm4x_relaxed_read32(csa, TRCIDR4);
1288 /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
1289 drvdata->nr_addr_cmp = FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4);
1290 /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
1291 drvdata->nr_pe_cmp = FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4);
1292 /*
1293 * NUMRSPAIR, bits[19:16]
1294 * The number of resource pairs conveyed by the HW starts at 0, i.e a
1295 * value of 0x0 indicate 1 resource pair, 0x1 indicate two and so on.
1296 * As such add 1 to the value of NUMRSPAIR for a better representation.
1297 *
1298 * For ETM v4.3 and later, 0x0 means 0, and no pairs are available -
1299 * the default TRUE and FALSE resource selectors are omitted.
1300 * Otherwise for values 0x1 and above the number is N + 1 as per v4.2.
1301 */
1302 drvdata->nr_resource = FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4);
1303 if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0))
1304 drvdata->nr_resource += 1;
1305 /*
1306 * NUMSSCC, bits[23:20] the number of single-shot
1307 * comparator control for tracing. Read any status regs as these
1308 * also contain RO capability data.
1309 */
1310 drvdata->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4);
1311 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1312 drvdata->config.ss_status[i] =
1313 etm4x_relaxed_read32(csa, TRCSSCSRn(i));
1314 }
1315 /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
1316 drvdata->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4);
1317 /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
1318 drvdata->numvmidc = FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4);
1319
1320 etmidr5 = etm4x_relaxed_read32(csa, TRCIDR5);
1321 /* NUMEXTIN, bits[8:0] number of external inputs implemented */
1322 drvdata->nr_ext_inp = FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5);
1323 /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
1324 drvdata->trcid_size = FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5);
1325 /* ATBTRIG, bit[22] implementation can support ATB triggers? */
1326 drvdata->atbtrig = !!(etmidr5 & TRCIDR5_ATBTRIG);
1327 /*
1328 * LPOVERRIDE, bit[23] implementation supports
1329 * low-power state override
1330 */
1331 drvdata->lpoverride = (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip_power_up);
1332 /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
1333 drvdata->nrseqstate = FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5);
1334 /* NUMCNTR, bits[30:28] number of counters available for tracing */
1335 drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
1336 etm4_cs_lock(drvdata, csa);
1337 cpu_detect_trace_filtering(drvdata);
1338}
1339
1340static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config)
1341{
1342 return etm4_get_access_type(config) << __bf_shf(TRCVICTLR_EXLEVEL_MASK);
1343}
1344
1345/* Set ELx trace filter access in the TRCVICTLR register */
1346static void etm4_set_victlr_access(struct etmv4_config *config)
1347{
1348 config->vinst_ctrl &= ~TRCVICTLR_EXLEVEL_MASK;
1349 config->vinst_ctrl |= etm4_get_victlr_access_type(config);
1350}
1351
1352static void etm4_set_default_config(struct etmv4_config *config)
1353{
1354 /* disable all events tracing */
1355 config->eventctrl0 = 0x0;
1356 config->eventctrl1 = 0x0;
1357
1358 /* disable stalling */
1359 config->stall_ctrl = 0x0;
1360
1361 /* enable trace synchronization every 4096 bytes, if available */
1362 config->syncfreq = 0xC;
1363
1364 /* disable timestamp event */
1365 config->ts_ctrl = 0x0;
1366
1367 /* TRCVICTLR::EVENT = 0x01, select the always on logic */
1368 config->vinst_ctrl = FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01);
1369
1370 /* TRCVICTLR::EXLEVEL_NS:EXLEVELS: Set kernel / user filtering */
1371 etm4_set_victlr_access(config);
1372}
1373
1374static u64 etm4_get_ns_access_type(struct etmv4_config *config)
1375{
1376 u64 access_type = 0;
1377
1378 /*
1379 * EXLEVEL_NS, for NonSecure Exception levels.
1380 * The mask here is a generic value and must be
1381 * shifted to the corresponding field for the registers
1382 */
1383 if (!is_kernel_in_hyp_mode()) {
1384 /* Stay away from hypervisor mode for non-VHE */
1385 access_type = ETM_EXLEVEL_NS_HYP;
1386 if (config->mode & ETM_MODE_EXCL_KERN)
1387 access_type |= ETM_EXLEVEL_NS_OS;
1388 } else if (config->mode & ETM_MODE_EXCL_KERN) {
1389 access_type = ETM_EXLEVEL_NS_HYP;
1390 }
1391
1392 if (config->mode & ETM_MODE_EXCL_USER)
1393 access_type |= ETM_EXLEVEL_NS_APP;
1394
1395 return access_type;
1396}
1397
1398/*
1399 * Construct the exception level masks for a given config.
1400 * This must be shifted to the corresponding register field
1401 * for usage.
1402 */
1403static u64 etm4_get_access_type(struct etmv4_config *config)
1404{
1405 /* All Secure exception levels are excluded from the trace */
1406 return etm4_get_ns_access_type(config) | (u64)config->s_ex_level;
1407}
1408
1409static u64 etm4_get_comparator_access_type(struct etmv4_config *config)
1410{
1411 return etm4_get_access_type(config) << TRCACATR_EXLEVEL_SHIFT;
1412}
1413
1414static void etm4_set_comparator_filter(struct etmv4_config *config,
1415 u64 start, u64 stop, int comparator)
1416{
1417 u64 access_type = etm4_get_comparator_access_type(config);
1418
1419 /* First half of default address comparator */
1420 config->addr_val[comparator] = start;
1421 config->addr_acc[comparator] = access_type;
1422 config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
1423
1424 /* Second half of default address comparator */
1425 config->addr_val[comparator + 1] = stop;
1426 config->addr_acc[comparator + 1] = access_type;
1427 config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
1428
1429 /*
1430 * Configure the ViewInst function to include this address range
1431 * comparator.
1432 *
1433 * @comparator is divided by two since it is the index in the
1434 * etmv4_config::addr_val array but register TRCVIIECTLR deals with
1435 * address range comparator _pairs_.
1436 *
1437 * Therefore:
1438 * index 0 -> compatator pair 0
1439 * index 2 -> comparator pair 1
1440 * index 4 -> comparator pair 2
1441 * ...
1442 * index 14 -> comparator pair 7
1443 */
1444 config->viiectlr |= BIT(comparator / 2);
1445}
1446
1447static void etm4_set_start_stop_filter(struct etmv4_config *config,
1448 u64 address, int comparator,
1449 enum etm_addr_type type)
1450{
1451 int shift;
1452 u64 access_type = etm4_get_comparator_access_type(config);
1453
1454 /* Configure the comparator */
1455 config->addr_val[comparator] = address;
1456 config->addr_acc[comparator] = access_type;
1457 config->addr_type[comparator] = type;
1458
1459 /*
1460 * Configure ViewInst Start-Stop control register.
1461 * Addresses configured to start tracing go from bit 0 to n-1,
1462 * while those configured to stop tracing from 16 to 16 + n-1.
1463 */
1464 shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
1465 config->vissctlr |= BIT(shift + comparator);
1466}
1467
1468static void etm4_set_default_filter(struct etmv4_config *config)
1469{
1470 /* Trace everything 'default' filter achieved by no filtering */
1471 config->viiectlr = 0x0;
1472
1473 /*
1474 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1475 * in the started state
1476 */
1477 config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1478 config->mode |= ETM_MODE_VIEWINST_STARTSTOP;
1479
1480 /* No start-stop filtering for ViewInst */
1481 config->vissctlr = 0x0;
1482}
1483
1484static void etm4_set_default(struct etmv4_config *config)
1485{
1486 if (WARN_ON_ONCE(!config))
1487 return;
1488
1489 /*
1490 * Make default initialisation trace everything
1491 *
1492 * This is done by a minimum default config sufficient to enable
1493 * full instruction trace - with a default filter for trace all
1494 * achieved by having no filtering.
1495 */
1496 etm4_set_default_config(config);
1497 etm4_set_default_filter(config);
1498}
1499
1500static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
1501{
1502 int nr_comparator, index = 0;
1503 struct etmv4_config *config = &drvdata->config;
1504
1505 /*
1506 * nr_addr_cmp holds the number of comparator _pair_, so time 2
1507 * for the total number of comparators.
1508 */
1509 nr_comparator = drvdata->nr_addr_cmp * 2;
1510
1511 /* Go through the tally of comparators looking for a free one. */
1512 while (index < nr_comparator) {
1513 switch (type) {
1514 case ETM_ADDR_TYPE_RANGE:
1515 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
1516 config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
1517 return index;
1518
1519 /* Address range comparators go in pairs */
1520 index += 2;
1521 break;
1522 case ETM_ADDR_TYPE_START:
1523 case ETM_ADDR_TYPE_STOP:
1524 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
1525 return index;
1526
1527 /* Start/stop address can have odd indexes */
1528 index += 1;
1529 break;
1530 default:
1531 return -EINVAL;
1532 }
1533 }
1534
1535 /* If we are here all the comparators have been used. */
1536 return -ENOSPC;
1537}
1538
1539static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
1540 struct perf_event *event)
1541{
1542 int i, comparator, ret = 0;
1543 u64 address;
1544 struct etmv4_config *config = &drvdata->config;
1545 struct etm_filters *filters = event->hw.addr_filters;
1546
1547 if (!filters)
1548 goto default_filter;
1549
1550 /* Sync events with what Perf got */
1551 perf_event_addr_filters_sync(event);
1552
1553 /*
1554 * If there are no filters to deal with simply go ahead with
1555 * the default filter, i.e the entire address range.
1556 */
1557 if (!filters->nr_filters)
1558 goto default_filter;
1559
1560 for (i = 0; i < filters->nr_filters; i++) {
1561 struct etm_filter *filter = &filters->etm_filter[i];
1562 enum etm_addr_type type = filter->type;
1563
1564 /* See if a comparator is free. */
1565 comparator = etm4_get_next_comparator(drvdata, type);
1566 if (comparator < 0) {
1567 ret = comparator;
1568 goto out;
1569 }
1570
1571 switch (type) {
1572 case ETM_ADDR_TYPE_RANGE:
1573 etm4_set_comparator_filter(config,
1574 filter->start_addr,
1575 filter->stop_addr,
1576 comparator);
1577 /*
1578 * TRCVICTLR::SSSTATUS == 1, the start-stop logic is
1579 * in the started state
1580 */
1581 config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1582
1583 /* No start-stop filtering for ViewInst */
1584 config->vissctlr = 0x0;
1585 break;
1586 case ETM_ADDR_TYPE_START:
1587 case ETM_ADDR_TYPE_STOP:
1588 /* Get the right start or stop address */
1589 address = (type == ETM_ADDR_TYPE_START ?
1590 filter->start_addr :
1591 filter->stop_addr);
1592
1593 /* Configure comparator */
1594 etm4_set_start_stop_filter(config, address,
1595 comparator, type);
1596
1597 /*
1598 * If filters::ssstatus == 1, trace acquisition was
1599 * started but the process was yanked away before the
1600 * stop address was hit. As such the start/stop
1601 * logic needs to be re-started so that tracing can
1602 * resume where it left.
1603 *
1604 * The start/stop logic status when a process is
1605 * scheduled out is checked in function
1606 * etm4_disable_perf().
1607 */
1608 if (filters->ssstatus)
1609 config->vinst_ctrl |= TRCVICTLR_SSSTATUS;
1610
1611 /* No include/exclude filtering for ViewInst */
1612 config->viiectlr = 0x0;
1613 break;
1614 default:
1615 ret = -EINVAL;
1616 goto out;
1617 }
1618 }
1619
1620 goto out;
1621
1622
1623default_filter:
1624 etm4_set_default_filter(config);
1625
1626out:
1627 return ret;
1628}
1629
1630void etm4_config_trace_mode(struct etmv4_config *config)
1631{
1632 u32 mode;
1633
1634 mode = config->mode;
1635 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1636
1637 /* excluding kernel AND user space doesn't make sense */
1638 WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1639
1640 /* nothing to do if neither flags are set */
1641 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1642 return;
1643
1644 etm4_set_victlr_access(config);
1645}
1646
1647static int etm4_online_cpu(unsigned int cpu)
1648{
1649 if (!etmdrvdata[cpu])
1650 return etm4_probe_cpu(cpu);
1651
1652 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1653 coresight_enable(etmdrvdata[cpu]->csdev);
1654 return 0;
1655}
1656
1657static int etm4_starting_cpu(unsigned int cpu)
1658{
1659 if (!etmdrvdata[cpu])
1660 return 0;
1661
1662 spin_lock(&etmdrvdata[cpu]->spinlock);
1663 if (!etmdrvdata[cpu]->os_unlock)
1664 etm4_os_unlock(etmdrvdata[cpu]);
1665
1666 if (local_read(&etmdrvdata[cpu]->mode))
1667 etm4_enable_hw(etmdrvdata[cpu]);
1668 spin_unlock(&etmdrvdata[cpu]->spinlock);
1669 return 0;
1670}
1671
1672static int etm4_dying_cpu(unsigned int cpu)
1673{
1674 if (!etmdrvdata[cpu])
1675 return 0;
1676
1677 spin_lock(&etmdrvdata[cpu]->spinlock);
1678 if (local_read(&etmdrvdata[cpu]->mode))
1679 etm4_disable_hw(etmdrvdata[cpu]);
1680 spin_unlock(&etmdrvdata[cpu]->spinlock);
1681 return 0;
1682}
1683
1684static int __etm4_cpu_save(struct etmv4_drvdata *drvdata)
1685{
1686 int i, ret = 0;
1687 struct etmv4_save_state *state;
1688 struct coresight_device *csdev = drvdata->csdev;
1689 struct csdev_access *csa;
1690 struct device *etm_dev;
1691
1692 if (WARN_ON(!csdev))
1693 return -ENODEV;
1694
1695 etm_dev = &csdev->dev;
1696 csa = &csdev->access;
1697
1698 /*
1699 * As recommended by 3.4.1 ("The procedure when powering down the PE")
1700 * of ARM IHI 0064D
1701 */
1702 dsb(sy);
1703 isb();
1704
1705 etm4_cs_unlock(drvdata, csa);
1706 /* Lock the OS lock to disable trace and external debugger access */
1707 etm4_os_lock(drvdata);
1708
1709 /* wait for TRCSTATR.PMSTABLE to go up */
1710 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_PMSTABLE_BIT, 1)) {
1711 dev_err(etm_dev,
1712 "timeout while waiting for PM Stable Status\n");
1713 etm4_os_unlock(drvdata);
1714 ret = -EBUSY;
1715 goto out;
1716 }
1717
1718 state = drvdata->save_state;
1719
1720 state->trcprgctlr = etm4x_read32(csa, TRCPRGCTLR);
1721 if (drvdata->nr_pe)
1722 state->trcprocselr = etm4x_read32(csa, TRCPROCSELR);
1723 state->trcconfigr = etm4x_read32(csa, TRCCONFIGR);
1724 state->trcauxctlr = etm4x_read32(csa, TRCAUXCTLR);
1725 state->trceventctl0r = etm4x_read32(csa, TRCEVENTCTL0R);
1726 state->trceventctl1r = etm4x_read32(csa, TRCEVENTCTL1R);
1727 if (drvdata->stallctl)
1728 state->trcstallctlr = etm4x_read32(csa, TRCSTALLCTLR);
1729 state->trctsctlr = etm4x_read32(csa, TRCTSCTLR);
1730 state->trcsyncpr = etm4x_read32(csa, TRCSYNCPR);
1731 state->trcccctlr = etm4x_read32(csa, TRCCCCTLR);
1732 state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR);
1733 state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR);
1734 state->trcqctlr = etm4x_read32(csa, TRCQCTLR);
1735
1736 state->trcvictlr = etm4x_read32(csa, TRCVICTLR);
1737 state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR);
1738 state->trcvissctlr = etm4x_read32(csa, TRCVISSCTLR);
1739 if (drvdata->nr_pe_cmp)
1740 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR);
1741 state->trcvdctlr = etm4x_read32(csa, TRCVDCTLR);
1742 state->trcvdsacctlr = etm4x_read32(csa, TRCVDSACCTLR);
1743 state->trcvdarcctlr = etm4x_read32(csa, TRCVDARCCTLR);
1744
1745 for (i = 0; i < drvdata->nrseqstate - 1; i++)
1746 state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i));
1747
1748 if (drvdata->nrseqstate) {
1749 state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR);
1750 state->trcseqstr = etm4x_read32(csa, TRCSEQSTR);
1751 }
1752 state->trcextinselr = etm4x_read32(csa, TRCEXTINSELR);
1753
1754 for (i = 0; i < drvdata->nr_cntr; i++) {
1755 state->trccntrldvr[i] = etm4x_read32(csa, TRCCNTRLDVRn(i));
1756 state->trccntctlr[i] = etm4x_read32(csa, TRCCNTCTLRn(i));
1757 state->trccntvr[i] = etm4x_read32(csa, TRCCNTVRn(i));
1758 }
1759
1760 for (i = 0; i < drvdata->nr_resource * 2; i++)
1761 state->trcrsctlr[i] = etm4x_read32(csa, TRCRSCTLRn(i));
1762
1763 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1764 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i));
1765 state->trcsscsr[i] = etm4x_read32(csa, TRCSSCSRn(i));
1766 if (etm4x_sspcicrn_present(drvdata, i))
1767 state->trcsspcicr[i] = etm4x_read32(csa, TRCSSPCICRn(i));
1768 }
1769
1770 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1771 state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i));
1772 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i));
1773 }
1774
1775 /*
1776 * Data trace stream is architecturally prohibited for A profile cores
1777 * so we don't save (or later restore) trcdvcvr and trcdvcmr - As per
1778 * section 1.3.4 ("Possible functional configurations of an ETMv4 trace
1779 * unit") of ARM IHI 0064D.
1780 */
1781
1782 for (i = 0; i < drvdata->numcidc; i++)
1783 state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i));
1784
1785 for (i = 0; i < drvdata->numvmidc; i++)
1786 state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i));
1787
1788 state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0);
1789 if (drvdata->numcidc > 4)
1790 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1);
1791
1792 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR0);
1793 if (drvdata->numvmidc > 4)
1794 state->trcvmidcctlr0 = etm4x_read32(csa, TRCVMIDCCTLR1);
1795
1796 state->trcclaimset = etm4x_read32(csa, TRCCLAIMCLR);
1797
1798 if (!drvdata->skip_power_up)
1799 state->trcpdcr = etm4x_read32(csa, TRCPDCR);
1800
1801 /* wait for TRCSTATR.IDLE to go up */
1802 if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1)) {
1803 dev_err(etm_dev,
1804 "timeout while waiting for Idle Trace Status\n");
1805 etm4_os_unlock(drvdata);
1806 ret = -EBUSY;
1807 goto out;
1808 }
1809
1810 drvdata->state_needs_restore = true;
1811
1812 /*
1813 * Power can be removed from the trace unit now. We do this to
1814 * potentially save power on systems that respect the TRCPDCR_PU
1815 * despite requesting software to save/restore state.
1816 */
1817 if (!drvdata->skip_power_up)
1818 etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
1819 TRCPDCR);
1820out:
1821 etm4_cs_lock(drvdata, csa);
1822 return ret;
1823}
1824
1825static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
1826{
1827 int ret = 0;
1828
1829 /* Save the TRFCR irrespective of whether the ETM is ON */
1830 if (drvdata->trfcr)
1831 drvdata->save_trfcr = read_trfcr();
1832 /*
1833 * Save and restore the ETM Trace registers only if
1834 * the ETM is active.
1835 */
1836 if (local_read(&drvdata->mode) && drvdata->save_state)
1837 ret = __etm4_cpu_save(drvdata);
1838 return ret;
1839}
1840
1841static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1842{
1843 int i;
1844 struct etmv4_save_state *state = drvdata->save_state;
1845 struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
1846 struct csdev_access *csa = &tmp_csa;
1847
1848 etm4_cs_unlock(drvdata, csa);
1849 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1850
1851 etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
1852 if (drvdata->nr_pe)
1853 etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR);
1854 etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR);
1855 etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR);
1856 etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R);
1857 etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R);
1858 if (drvdata->stallctl)
1859 etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR);
1860 etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR);
1861 etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR);
1862 etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR);
1863 etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR);
1864 etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR);
1865 etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR);
1866
1867 etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR);
1868 etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR);
1869 etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR);
1870 if (drvdata->nr_pe_cmp)
1871 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR);
1872 etm4x_relaxed_write32(csa, state->trcvdctlr, TRCVDCTLR);
1873 etm4x_relaxed_write32(csa, state->trcvdsacctlr, TRCVDSACCTLR);
1874 etm4x_relaxed_write32(csa, state->trcvdarcctlr, TRCVDARCCTLR);
1875
1876 for (i = 0; i < drvdata->nrseqstate - 1; i++)
1877 etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i));
1878
1879 if (drvdata->nrseqstate) {
1880 etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR);
1881 etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR);
1882 }
1883 etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR);
1884
1885 for (i = 0; i < drvdata->nr_cntr; i++) {
1886 etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i));
1887 etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i));
1888 etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i));
1889 }
1890
1891 for (i = 0; i < drvdata->nr_resource * 2; i++)
1892 etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i));
1893
1894 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1895 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i));
1896 etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i));
1897 if (etm4x_sspcicrn_present(drvdata, i))
1898 etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i));
1899 }
1900
1901 for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
1902 etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i));
1903 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i));
1904 }
1905
1906 for (i = 0; i < drvdata->numcidc; i++)
1907 etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i));
1908
1909 for (i = 0; i < drvdata->numvmidc; i++)
1910 etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i));
1911
1912 etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0);
1913 if (drvdata->numcidc > 4)
1914 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1);
1915
1916 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0);
1917 if (drvdata->numvmidc > 4)
1918 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1);
1919
1920 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
1921
1922 if (!drvdata->skip_power_up)
1923 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR);
1924
1925 drvdata->state_needs_restore = false;
1926
1927 /*
1928 * As recommended by section 4.3.7 ("Synchronization when using the
1929 * memory-mapped interface") of ARM IHI 0064D
1930 */
1931 dsb(sy);
1932 isb();
1933
1934 /* Unlock the OS lock to re-enable trace and external debug access */
1935 etm4_os_unlock(drvdata);
1936 etm4_cs_lock(drvdata, csa);
1937}
1938
1939static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
1940{
1941 if (drvdata->trfcr)
1942 write_trfcr(drvdata->save_trfcr);
1943 if (drvdata->state_needs_restore)
1944 __etm4_cpu_restore(drvdata);
1945}
1946
1947static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
1948 void *v)
1949{
1950 struct etmv4_drvdata *drvdata;
1951 unsigned int cpu = smp_processor_id();
1952
1953 if (!etmdrvdata[cpu])
1954 return NOTIFY_OK;
1955
1956 drvdata = etmdrvdata[cpu];
1957
1958 if (WARN_ON_ONCE(drvdata->cpu != cpu))
1959 return NOTIFY_BAD;
1960
1961 switch (cmd) {
1962 case CPU_PM_ENTER:
1963 if (etm4_cpu_save(drvdata))
1964 return NOTIFY_BAD;
1965 break;
1966 case CPU_PM_EXIT:
1967 case CPU_PM_ENTER_FAILED:
1968 etm4_cpu_restore(drvdata);
1969 break;
1970 default:
1971 return NOTIFY_DONE;
1972 }
1973
1974 return NOTIFY_OK;
1975}
1976
1977static struct notifier_block etm4_cpu_pm_nb = {
1978 .notifier_call = etm4_cpu_pm_notify,
1979};
1980
1981/* Setup PM. Deals with error conditions and counts */
1982static int __init etm4_pm_setup(void)
1983{
1984 int ret;
1985
1986 ret = cpu_pm_register_notifier(&etm4_cpu_pm_nb);
1987 if (ret)
1988 return ret;
1989
1990 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING,
1991 "arm/coresight4:starting",
1992 etm4_starting_cpu, etm4_dying_cpu);
1993
1994 if (ret)
1995 goto unregister_notifier;
1996
1997 ret = cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN,
1998 "arm/coresight4:online",
1999 etm4_online_cpu, NULL);
2000
2001 /* HP dyn state ID returned in ret on success */
2002 if (ret > 0) {
2003 hp_online = ret;
2004 return 0;
2005 }
2006
2007 /* failed dyn state - remove others */
2008 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
2009
2010unregister_notifier:
2011 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
2012 return ret;
2013}
2014
2015static void etm4_pm_clear(void)
2016{
2017 cpu_pm_unregister_notifier(&etm4_cpu_pm_nb);
2018 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
2019 if (hp_online) {
2020 cpuhp_remove_state_nocalls(hp_online);
2021 hp_online = 0;
2022 }
2023}
2024
2025static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg)
2026{
2027 int ret;
2028 struct coresight_platform_data *pdata = NULL;
2029 struct device *dev = init_arg->dev;
2030 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2031 struct coresight_desc desc = { 0 };
2032 u8 major, minor;
2033 char *type_name;
2034
2035 if (!drvdata)
2036 return -EINVAL;
2037
2038 desc.access = *init_arg->csa;
2039
2040 if (!drvdata->arch)
2041 return -EINVAL;
2042
2043 /* TRCPDCR is not accessible with system instructions. */
2044 if (!desc.access.io_mem ||
2045 fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
2046 drvdata->skip_power_up = true;
2047
2048 major = ETM_ARCH_MAJOR_VERSION(drvdata->arch);
2049 minor = ETM_ARCH_MINOR_VERSION(drvdata->arch);
2050
2051 if (etm4x_is_ete(drvdata)) {
2052 type_name = "ete";
2053 /* ETE v1 has major version == 0b101. Adjust this for logging.*/
2054 major -= 4;
2055 } else {
2056 type_name = "etm";
2057 }
2058
2059 desc.name = devm_kasprintf(dev, GFP_KERNEL,
2060 "%s%d", type_name, drvdata->cpu);
2061 if (!desc.name)
2062 return -ENOMEM;
2063
2064 etm4_set_default(&drvdata->config);
2065
2066 pdata = coresight_get_platform_data(dev);
2067 if (IS_ERR(pdata))
2068 return PTR_ERR(pdata);
2069
2070 dev->platform_data = pdata;
2071
2072 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
2073 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
2074 desc.ops = &etm4_cs_ops;
2075 desc.pdata = pdata;
2076 desc.dev = dev;
2077 desc.groups = coresight_etmv4_groups;
2078 drvdata->csdev = coresight_register(&desc);
2079 if (IS_ERR(drvdata->csdev))
2080 return PTR_ERR(drvdata->csdev);
2081
2082 ret = etm_perf_symlink(drvdata->csdev, true);
2083 if (ret) {
2084 coresight_unregister(drvdata->csdev);
2085 return ret;
2086 }
2087
2088 /* register with config infrastructure & load any current features */
2089 ret = etm4_cscfg_register(drvdata->csdev);
2090 if (ret) {
2091 coresight_unregister(drvdata->csdev);
2092 return ret;
2093 }
2094
2095 etmdrvdata[drvdata->cpu] = drvdata;
2096
2097 dev_info(&drvdata->csdev->dev, "CPU%d: %s v%d.%d initialized\n",
2098 drvdata->cpu, type_name, major, minor);
2099
2100 if (boot_enable) {
2101 coresight_enable(drvdata->csdev);
2102 drvdata->boot_enable = true;
2103 }
2104
2105 return 0;
2106}
2107
2108static int etm4_probe(struct device *dev)
2109{
2110 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2111 struct csdev_access access = { 0 };
2112 struct etm4_init_arg init_arg = { 0 };
2113 struct etm4_init_arg *delayed;
2114
2115 if (WARN_ON(!drvdata))
2116 return -ENOMEM;
2117
2118 if (pm_save_enable == PARAM_PM_SAVE_FIRMWARE)
2119 pm_save_enable = coresight_loses_context_with_cpu(dev) ?
2120 PARAM_PM_SAVE_SELF_HOSTED : PARAM_PM_SAVE_NEVER;
2121
2122 if (pm_save_enable != PARAM_PM_SAVE_NEVER) {
2123 drvdata->save_state = devm_kmalloc(dev,
2124 sizeof(struct etmv4_save_state), GFP_KERNEL);
2125 if (!drvdata->save_state)
2126 return -ENOMEM;
2127 }
2128
2129 spin_lock_init(&drvdata->spinlock);
2130
2131 drvdata->cpu = coresight_get_cpu(dev);
2132 if (drvdata->cpu < 0)
2133 return drvdata->cpu;
2134
2135 init_arg.dev = dev;
2136 init_arg.csa = &access;
2137
2138 /*
2139 * Serialize against CPUHP callbacks to avoid race condition
2140 * between the smp call and saving the delayed probe.
2141 */
2142 cpus_read_lock();
2143 if (smp_call_function_single(drvdata->cpu,
2144 etm4_init_arch_data, &init_arg, 1)) {
2145 /* The CPU was offline, try again once it comes online. */
2146 delayed = devm_kmalloc(dev, sizeof(*delayed), GFP_KERNEL);
2147 if (!delayed) {
2148 cpus_read_unlock();
2149 return -ENOMEM;
2150 }
2151
2152 *delayed = init_arg;
2153
2154 per_cpu(delayed_probe, drvdata->cpu) = delayed;
2155
2156 cpus_read_unlock();
2157 return 0;
2158 }
2159 cpus_read_unlock();
2160
2161 return etm4_add_coresight_dev(&init_arg);
2162}
2163
2164static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id)
2165{
2166 struct etmv4_drvdata *drvdata;
2167 void __iomem *base;
2168 struct device *dev = &adev->dev;
2169 struct resource *res = &adev->res;
2170 int ret;
2171
2172 /* Validity for the resource is already checked by the AMBA core */
2173 base = devm_ioremap_resource(dev, res);
2174 if (IS_ERR(base))
2175 return PTR_ERR(base);
2176
2177 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
2178 if (!drvdata)
2179 return -ENOMEM;
2180
2181 drvdata->base = base;
2182 dev_set_drvdata(dev, drvdata);
2183 ret = etm4_probe(dev);
2184 if (!ret)
2185 pm_runtime_put(&adev->dev);
2186
2187 return ret;
2188}
2189
2190static int etm4_probe_platform_dev(struct platform_device *pdev)
2191{
2192 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2193 struct etmv4_drvdata *drvdata;
2194 int ret;
2195
2196 drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
2197 if (!drvdata)
2198 return -ENOMEM;
2199
2200 drvdata->pclk = coresight_get_enable_apb_pclk(&pdev->dev);
2201 if (IS_ERR(drvdata->pclk))
2202 return -ENODEV;
2203
2204 if (res) {
2205 drvdata->base = devm_ioremap_resource(&pdev->dev, res);
2206 if (IS_ERR(drvdata->base)) {
2207 clk_put(drvdata->pclk);
2208 return PTR_ERR(drvdata->base);
2209 }
2210 }
2211
2212 dev_set_drvdata(&pdev->dev, drvdata);
2213 pm_runtime_get_noresume(&pdev->dev);
2214 pm_runtime_set_active(&pdev->dev);
2215 pm_runtime_enable(&pdev->dev);
2216
2217 ret = etm4_probe(&pdev->dev);
2218
2219 pm_runtime_put(&pdev->dev);
2220 return ret;
2221}
2222
2223static int etm4_probe_cpu(unsigned int cpu)
2224{
2225 int ret;
2226 struct etm4_init_arg init_arg;
2227 struct csdev_access access = { 0 };
2228 struct etm4_init_arg *iap = *this_cpu_ptr(&delayed_probe);
2229
2230 if (!iap)
2231 return 0;
2232
2233 init_arg = *iap;
2234 devm_kfree(init_arg.dev, iap);
2235 *this_cpu_ptr(&delayed_probe) = NULL;
2236
2237 ret = pm_runtime_resume_and_get(init_arg.dev);
2238 if (ret < 0) {
2239 dev_err(init_arg.dev, "Failed to get PM runtime!\n");
2240 return 0;
2241 }
2242
2243 init_arg.csa = &access;
2244 etm4_init_arch_data(&init_arg);
2245
2246 etm4_add_coresight_dev(&init_arg);
2247
2248 pm_runtime_put(init_arg.dev);
2249 return 0;
2250}
2251
2252static struct amba_cs_uci_id uci_id_etm4[] = {
2253 {
2254 /* ETMv4 UCI data */
2255 .devarch = ETM_DEVARCH_ETMv4x_ARCH,
2256 .devarch_mask = ETM_DEVARCH_ID_MASK,
2257 .devtype = CS_DEVTYPE_PE_TRACE,
2258 }
2259};
2260
2261static void clear_etmdrvdata(void *info)
2262{
2263 int cpu = *(int *)info;
2264
2265 etmdrvdata[cpu] = NULL;
2266 per_cpu(delayed_probe, cpu) = NULL;
2267}
2268
2269static void etm4_remove_dev(struct etmv4_drvdata *drvdata)
2270{
2271 bool had_delayed_probe;
2272 /*
2273 * Taking hotplug lock here to avoid racing between etm4_remove_dev()
2274 * and CPU hotplug call backs.
2275 */
2276 cpus_read_lock();
2277
2278 had_delayed_probe = per_cpu(delayed_probe, drvdata->cpu);
2279
2280 /*
2281 * The readers for etmdrvdata[] are CPU hotplug call backs
2282 * and PM notification call backs. Change etmdrvdata[i] on
2283 * CPU i ensures these call backs has consistent view
2284 * inside one call back function.
2285 */
2286 if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
2287 clear_etmdrvdata(&drvdata->cpu);
2288
2289 cpus_read_unlock();
2290
2291 if (!had_delayed_probe) {
2292 etm_perf_symlink(drvdata->csdev, false);
2293 cscfg_unregister_csdev(drvdata->csdev);
2294 coresight_unregister(drvdata->csdev);
2295 }
2296}
2297
2298static void etm4_remove_amba(struct amba_device *adev)
2299{
2300 struct etmv4_drvdata *drvdata = dev_get_drvdata(&adev->dev);
2301
2302 if (drvdata)
2303 etm4_remove_dev(drvdata);
2304}
2305
2306static void etm4_remove_platform_dev(struct platform_device *pdev)
2307{
2308 struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
2309
2310 if (drvdata)
2311 etm4_remove_dev(drvdata);
2312 pm_runtime_disable(&pdev->dev);
2313
2314 if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk))
2315 clk_put(drvdata->pclk);
2316}
2317
2318static const struct amba_id etm4_ids[] = {
2319 CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */
2320 CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */
2321 CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */
2322 CS_AMBA_ID(0x000bb959), /* Cortex-A73 */
2323 CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
2324 CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
2325 CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
2326 CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
2327 CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */
2328 CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
2329 CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
2330 CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
2331 CS_AMBA_UCI_ID(0x000bb803, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A75 */
2332 CS_AMBA_UCI_ID(0x000bb805, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A55 */
2333 CS_AMBA_UCI_ID(0x000bb804, uci_id_etm4),/* Qualcomm Kryo 4XX Cortex-A76 */
2334 CS_AMBA_UCI_ID(0x000bbd0d, uci_id_etm4),/* Qualcomm Kryo 5XX Cortex-A77 */
2335 CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
2336 CS_AMBA_UCI_ID(0x000b6d01, uci_id_etm4),/* HiSilicon-Hip08 */
2337 CS_AMBA_UCI_ID(0x000b6d02, uci_id_etm4),/* HiSilicon-Hip09 */
2338 /*
2339 * Match all PIDs with ETM4 DEVARCH. No need for adding any of the new
2340 * CPUs to the list here.
2341 */
2342 CS_AMBA_MATCH_ALL_UCI(uci_id_etm4),
2343 {},
2344};
2345
2346MODULE_DEVICE_TABLE(amba, etm4_ids);
2347
2348static struct amba_driver etm4x_amba_driver = {
2349 .drv = {
2350 .name = "coresight-etm4x",
2351 .owner = THIS_MODULE,
2352 .suppress_bind_attrs = true,
2353 },
2354 .probe = etm4_probe_amba,
2355 .remove = etm4_remove_amba,
2356 .id_table = etm4_ids,
2357};
2358
2359#ifdef CONFIG_PM
2360static int etm4_runtime_suspend(struct device *dev)
2361{
2362 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2363
2364 if (drvdata->pclk && !IS_ERR(drvdata->pclk))
2365 clk_disable_unprepare(drvdata->pclk);
2366
2367 return 0;
2368}
2369
2370static int etm4_runtime_resume(struct device *dev)
2371{
2372 struct etmv4_drvdata *drvdata = dev_get_drvdata(dev);
2373
2374 if (drvdata->pclk && !IS_ERR(drvdata->pclk))
2375 clk_prepare_enable(drvdata->pclk);
2376
2377 return 0;
2378}
2379#endif
2380
2381static const struct dev_pm_ops etm4_dev_pm_ops = {
2382 SET_RUNTIME_PM_OPS(etm4_runtime_suspend, etm4_runtime_resume, NULL)
2383};
2384
2385static const struct of_device_id etm4_sysreg_match[] = {
2386 { .compatible = "arm,coresight-etm4x-sysreg" },
2387 { .compatible = "arm,embedded-trace-extension" },
2388 {}
2389};
2390
2391#ifdef CONFIG_ACPI
2392static const struct acpi_device_id etm4x_acpi_ids[] = {
2393 {"ARMHC500", 0}, /* ARM CoreSight ETM4x */
2394 {}
2395};
2396MODULE_DEVICE_TABLE(acpi, etm4x_acpi_ids);
2397#endif
2398
2399static struct platform_driver etm4_platform_driver = {
2400 .probe = etm4_probe_platform_dev,
2401 .remove_new = etm4_remove_platform_dev,
2402 .driver = {
2403 .name = "coresight-etm4x",
2404 .of_match_table = etm4_sysreg_match,
2405 .acpi_match_table = ACPI_PTR(etm4x_acpi_ids),
2406 .suppress_bind_attrs = true,
2407 .pm = &etm4_dev_pm_ops,
2408 },
2409};
2410
2411static int __init etm4x_init(void)
2412{
2413 int ret;
2414
2415 ret = etm4_pm_setup();
2416
2417 /* etm4_pm_setup() does its own cleanup - exit on error */
2418 if (ret)
2419 return ret;
2420
2421 ret = amba_driver_register(&etm4x_amba_driver);
2422 if (ret) {
2423 pr_err("Error registering etm4x AMBA driver\n");
2424 goto clear_pm;
2425 }
2426
2427 ret = platform_driver_register(&etm4_platform_driver);
2428 if (!ret)
2429 return 0;
2430
2431 pr_err("Error registering etm4x platform driver\n");
2432 amba_driver_unregister(&etm4x_amba_driver);
2433
2434clear_pm:
2435 etm4_pm_clear();
2436 return ret;
2437}
2438
2439static void __exit etm4x_exit(void)
2440{
2441 amba_driver_unregister(&etm4x_amba_driver);
2442 platform_driver_unregister(&etm4_platform_driver);
2443 etm4_pm_clear();
2444}
2445
2446module_init(etm4x_init);
2447module_exit(etm4x_exit);
2448
2449MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
2450MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
2451MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace v4.x driver");
2452MODULE_LICENSE("GPL v2");