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1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <ttm/ttm_bo_api.h>
33#include <ttm/ttm_bo_driver.h>
34#include <ttm/ttm_placement.h>
35#include <ttm/ttm_module.h>
36#include <ttm/ttm_page_alloc.h>
37#include <drm/drmP.h>
38#include <drm/radeon_drm.h>
39#include <linux/seq_file.h>
40#include <linux/slab.h>
41#include "radeon_reg.h"
42#include "radeon.h"
43
44#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
45
46static int radeon_ttm_debugfs_init(struct radeon_device *rdev);
47
48static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev)
49{
50 struct radeon_mman *mman;
51 struct radeon_device *rdev;
52
53 mman = container_of(bdev, struct radeon_mman, bdev);
54 rdev = container_of(mman, struct radeon_device, mman);
55 return rdev;
56}
57
58
59/*
60 * Global memory.
61 */
62static int radeon_ttm_mem_global_init(struct drm_global_reference *ref)
63{
64 return ttm_mem_global_init(ref->object);
65}
66
67static void radeon_ttm_mem_global_release(struct drm_global_reference *ref)
68{
69 ttm_mem_global_release(ref->object);
70}
71
72static int radeon_ttm_global_init(struct radeon_device *rdev)
73{
74 struct drm_global_reference *global_ref;
75 int r;
76
77 rdev->mman.mem_global_referenced = false;
78 global_ref = &rdev->mman.mem_global_ref;
79 global_ref->global_type = DRM_GLOBAL_TTM_MEM;
80 global_ref->size = sizeof(struct ttm_mem_global);
81 global_ref->init = &radeon_ttm_mem_global_init;
82 global_ref->release = &radeon_ttm_mem_global_release;
83 r = drm_global_item_ref(global_ref);
84 if (r != 0) {
85 DRM_ERROR("Failed setting up TTM memory accounting "
86 "subsystem.\n");
87 return r;
88 }
89
90 rdev->mman.bo_global_ref.mem_glob =
91 rdev->mman.mem_global_ref.object;
92 global_ref = &rdev->mman.bo_global_ref.ref;
93 global_ref->global_type = DRM_GLOBAL_TTM_BO;
94 global_ref->size = sizeof(struct ttm_bo_global);
95 global_ref->init = &ttm_bo_global_init;
96 global_ref->release = &ttm_bo_global_release;
97 r = drm_global_item_ref(global_ref);
98 if (r != 0) {
99 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
100 drm_global_item_unref(&rdev->mman.mem_global_ref);
101 return r;
102 }
103
104 rdev->mman.mem_global_referenced = true;
105 return 0;
106}
107
108static void radeon_ttm_global_fini(struct radeon_device *rdev)
109{
110 if (rdev->mman.mem_global_referenced) {
111 drm_global_item_unref(&rdev->mman.bo_global_ref.ref);
112 drm_global_item_unref(&rdev->mman.mem_global_ref);
113 rdev->mman.mem_global_referenced = false;
114 }
115}
116
117struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev);
118
119static struct ttm_backend*
120radeon_create_ttm_backend_entry(struct ttm_bo_device *bdev)
121{
122 struct radeon_device *rdev;
123
124 rdev = radeon_get_rdev(bdev);
125#if __OS_HAS_AGP
126 if (rdev->flags & RADEON_IS_AGP) {
127 return ttm_agp_backend_init(bdev, rdev->ddev->agp->bridge);
128 } else
129#endif
130 {
131 return radeon_ttm_backend_create(rdev);
132 }
133}
134
135static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
136{
137 return 0;
138}
139
140static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
141 struct ttm_mem_type_manager *man)
142{
143 struct radeon_device *rdev;
144
145 rdev = radeon_get_rdev(bdev);
146
147 switch (type) {
148 case TTM_PL_SYSTEM:
149 /* System memory */
150 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
151 man->available_caching = TTM_PL_MASK_CACHING;
152 man->default_caching = TTM_PL_FLAG_CACHED;
153 break;
154 case TTM_PL_TT:
155 man->func = &ttm_bo_manager_func;
156 man->gpu_offset = rdev->mc.gtt_start;
157 man->available_caching = TTM_PL_MASK_CACHING;
158 man->default_caching = TTM_PL_FLAG_CACHED;
159 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
160#if __OS_HAS_AGP
161 if (rdev->flags & RADEON_IS_AGP) {
162 if (!(drm_core_has_AGP(rdev->ddev) && rdev->ddev->agp)) {
163 DRM_ERROR("AGP is not enabled for memory type %u\n",
164 (unsigned)type);
165 return -EINVAL;
166 }
167 if (!rdev->ddev->agp->cant_use_aperture)
168 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
169 man->available_caching = TTM_PL_FLAG_UNCACHED |
170 TTM_PL_FLAG_WC;
171 man->default_caching = TTM_PL_FLAG_WC;
172 }
173#endif
174 break;
175 case TTM_PL_VRAM:
176 /* "On-card" video ram */
177 man->func = &ttm_bo_manager_func;
178 man->gpu_offset = rdev->mc.vram_start;
179 man->flags = TTM_MEMTYPE_FLAG_FIXED |
180 TTM_MEMTYPE_FLAG_MAPPABLE;
181 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
182 man->default_caching = TTM_PL_FLAG_WC;
183 break;
184 default:
185 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
186 return -EINVAL;
187 }
188 return 0;
189}
190
191static void radeon_evict_flags(struct ttm_buffer_object *bo,
192 struct ttm_placement *placement)
193{
194 struct radeon_bo *rbo;
195 static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
196
197 if (!radeon_ttm_bo_is_radeon_bo(bo)) {
198 placement->fpfn = 0;
199 placement->lpfn = 0;
200 placement->placement = &placements;
201 placement->busy_placement = &placements;
202 placement->num_placement = 1;
203 placement->num_busy_placement = 1;
204 return;
205 }
206 rbo = container_of(bo, struct radeon_bo, tbo);
207 switch (bo->mem.mem_type) {
208 case TTM_PL_VRAM:
209 if (rbo->rdev->cp.ready == false)
210 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
211 else
212 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
213 break;
214 case TTM_PL_TT:
215 default:
216 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
217 }
218 *placement = rbo->placement;
219}
220
221static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp)
222{
223 return 0;
224}
225
226static void radeon_move_null(struct ttm_buffer_object *bo,
227 struct ttm_mem_reg *new_mem)
228{
229 struct ttm_mem_reg *old_mem = &bo->mem;
230
231 BUG_ON(old_mem->mm_node != NULL);
232 *old_mem = *new_mem;
233 new_mem->mm_node = NULL;
234}
235
236static int radeon_move_blit(struct ttm_buffer_object *bo,
237 bool evict, int no_wait_reserve, bool no_wait_gpu,
238 struct ttm_mem_reg *new_mem,
239 struct ttm_mem_reg *old_mem)
240{
241 struct radeon_device *rdev;
242 uint64_t old_start, new_start;
243 struct radeon_fence *fence;
244 int r;
245
246 rdev = radeon_get_rdev(bo->bdev);
247 r = radeon_fence_create(rdev, &fence);
248 if (unlikely(r)) {
249 return r;
250 }
251 old_start = old_mem->start << PAGE_SHIFT;
252 new_start = new_mem->start << PAGE_SHIFT;
253
254 switch (old_mem->mem_type) {
255 case TTM_PL_VRAM:
256 old_start += rdev->mc.vram_start;
257 break;
258 case TTM_PL_TT:
259 old_start += rdev->mc.gtt_start;
260 break;
261 default:
262 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
263 return -EINVAL;
264 }
265 switch (new_mem->mem_type) {
266 case TTM_PL_VRAM:
267 new_start += rdev->mc.vram_start;
268 break;
269 case TTM_PL_TT:
270 new_start += rdev->mc.gtt_start;
271 break;
272 default:
273 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
274 return -EINVAL;
275 }
276 if (!rdev->cp.ready) {
277 DRM_ERROR("Trying to move memory with CP turned off.\n");
278 return -EINVAL;
279 }
280
281 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
282
283 r = radeon_copy(rdev, old_start, new_start,
284 new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */
285 fence);
286 /* FIXME: handle copy error */
287 r = ttm_bo_move_accel_cleanup(bo, (void *)fence, NULL,
288 evict, no_wait_reserve, no_wait_gpu, new_mem);
289 radeon_fence_unref(&fence);
290 return r;
291}
292
293static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
294 bool evict, bool interruptible,
295 bool no_wait_reserve, bool no_wait_gpu,
296 struct ttm_mem_reg *new_mem)
297{
298 struct radeon_device *rdev;
299 struct ttm_mem_reg *old_mem = &bo->mem;
300 struct ttm_mem_reg tmp_mem;
301 u32 placements;
302 struct ttm_placement placement;
303 int r;
304
305 rdev = radeon_get_rdev(bo->bdev);
306 tmp_mem = *new_mem;
307 tmp_mem.mm_node = NULL;
308 placement.fpfn = 0;
309 placement.lpfn = 0;
310 placement.num_placement = 1;
311 placement.placement = &placements;
312 placement.num_busy_placement = 1;
313 placement.busy_placement = &placements;
314 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
315 r = ttm_bo_mem_space(bo, &placement, &tmp_mem,
316 interruptible, no_wait_reserve, no_wait_gpu);
317 if (unlikely(r)) {
318 return r;
319 }
320
321 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
322 if (unlikely(r)) {
323 goto out_cleanup;
324 }
325
326 r = ttm_tt_bind(bo->ttm, &tmp_mem);
327 if (unlikely(r)) {
328 goto out_cleanup;
329 }
330 r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem, old_mem);
331 if (unlikely(r)) {
332 goto out_cleanup;
333 }
334 r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
335out_cleanup:
336 ttm_bo_mem_put(bo, &tmp_mem);
337 return r;
338}
339
340static int radeon_move_ram_vram(struct ttm_buffer_object *bo,
341 bool evict, bool interruptible,
342 bool no_wait_reserve, bool no_wait_gpu,
343 struct ttm_mem_reg *new_mem)
344{
345 struct radeon_device *rdev;
346 struct ttm_mem_reg *old_mem = &bo->mem;
347 struct ttm_mem_reg tmp_mem;
348 struct ttm_placement placement;
349 u32 placements;
350 int r;
351
352 rdev = radeon_get_rdev(bo->bdev);
353 tmp_mem = *new_mem;
354 tmp_mem.mm_node = NULL;
355 placement.fpfn = 0;
356 placement.lpfn = 0;
357 placement.num_placement = 1;
358 placement.placement = &placements;
359 placement.num_busy_placement = 1;
360 placement.busy_placement = &placements;
361 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
362 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, interruptible, no_wait_reserve, no_wait_gpu);
363 if (unlikely(r)) {
364 return r;
365 }
366 r = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
367 if (unlikely(r)) {
368 goto out_cleanup;
369 }
370 r = radeon_move_blit(bo, true, no_wait_reserve, no_wait_gpu, new_mem, old_mem);
371 if (unlikely(r)) {
372 goto out_cleanup;
373 }
374out_cleanup:
375 ttm_bo_mem_put(bo, &tmp_mem);
376 return r;
377}
378
379static int radeon_bo_move(struct ttm_buffer_object *bo,
380 bool evict, bool interruptible,
381 bool no_wait_reserve, bool no_wait_gpu,
382 struct ttm_mem_reg *new_mem)
383{
384 struct radeon_device *rdev;
385 struct ttm_mem_reg *old_mem = &bo->mem;
386 int r;
387
388 rdev = radeon_get_rdev(bo->bdev);
389 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
390 radeon_move_null(bo, new_mem);
391 return 0;
392 }
393 if ((old_mem->mem_type == TTM_PL_TT &&
394 new_mem->mem_type == TTM_PL_SYSTEM) ||
395 (old_mem->mem_type == TTM_PL_SYSTEM &&
396 new_mem->mem_type == TTM_PL_TT)) {
397 /* bind is enough */
398 radeon_move_null(bo, new_mem);
399 return 0;
400 }
401 if (!rdev->cp.ready || rdev->asic->copy == NULL) {
402 /* use memcpy */
403 goto memcpy;
404 }
405
406 if (old_mem->mem_type == TTM_PL_VRAM &&
407 new_mem->mem_type == TTM_PL_SYSTEM) {
408 r = radeon_move_vram_ram(bo, evict, interruptible,
409 no_wait_reserve, no_wait_gpu, new_mem);
410 } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
411 new_mem->mem_type == TTM_PL_VRAM) {
412 r = radeon_move_ram_vram(bo, evict, interruptible,
413 no_wait_reserve, no_wait_gpu, new_mem);
414 } else {
415 r = radeon_move_blit(bo, evict, no_wait_reserve, no_wait_gpu, new_mem, old_mem);
416 }
417
418 if (r) {
419memcpy:
420 r = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
421 }
422 return r;
423}
424
425static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
426{
427 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
428 struct radeon_device *rdev = radeon_get_rdev(bdev);
429
430 mem->bus.addr = NULL;
431 mem->bus.offset = 0;
432 mem->bus.size = mem->num_pages << PAGE_SHIFT;
433 mem->bus.base = 0;
434 mem->bus.is_iomem = false;
435 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
436 return -EINVAL;
437 switch (mem->mem_type) {
438 case TTM_PL_SYSTEM:
439 /* system memory */
440 return 0;
441 case TTM_PL_TT:
442#if __OS_HAS_AGP
443 if (rdev->flags & RADEON_IS_AGP) {
444 /* RADEON_IS_AGP is set only if AGP is active */
445 mem->bus.offset = mem->start << PAGE_SHIFT;
446 mem->bus.base = rdev->mc.agp_base;
447 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture;
448 }
449#endif
450 break;
451 case TTM_PL_VRAM:
452 mem->bus.offset = mem->start << PAGE_SHIFT;
453 /* check if it's visible */
454 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size)
455 return -EINVAL;
456 mem->bus.base = rdev->mc.aper_base;
457 mem->bus.is_iomem = true;
458#ifdef __alpha__
459 /*
460 * Alpha: use bus.addr to hold the ioremap() return,
461 * so we can modify bus.base below.
462 */
463 if (mem->placement & TTM_PL_FLAG_WC)
464 mem->bus.addr =
465 ioremap_wc(mem->bus.base + mem->bus.offset,
466 mem->bus.size);
467 else
468 mem->bus.addr =
469 ioremap_nocache(mem->bus.base + mem->bus.offset,
470 mem->bus.size);
471
472 /*
473 * Alpha: Use just the bus offset plus
474 * the hose/domain memory base for bus.base.
475 * It then can be used to build PTEs for VRAM
476 * access, as done in ttm_bo_vm_fault().
477 */
478 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) +
479 rdev->ddev->hose->dense_mem_base;
480#endif
481 break;
482 default:
483 return -EINVAL;
484 }
485 return 0;
486}
487
488static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
489{
490}
491
492static int radeon_sync_obj_wait(void *sync_obj, void *sync_arg,
493 bool lazy, bool interruptible)
494{
495 return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible);
496}
497
498static int radeon_sync_obj_flush(void *sync_obj, void *sync_arg)
499{
500 return 0;
501}
502
503static void radeon_sync_obj_unref(void **sync_obj)
504{
505 radeon_fence_unref((struct radeon_fence **)sync_obj);
506}
507
508static void *radeon_sync_obj_ref(void *sync_obj)
509{
510 return radeon_fence_ref((struct radeon_fence *)sync_obj);
511}
512
513static bool radeon_sync_obj_signaled(void *sync_obj, void *sync_arg)
514{
515 return radeon_fence_signaled((struct radeon_fence *)sync_obj);
516}
517
518static struct ttm_bo_driver radeon_bo_driver = {
519 .create_ttm_backend_entry = &radeon_create_ttm_backend_entry,
520 .invalidate_caches = &radeon_invalidate_caches,
521 .init_mem_type = &radeon_init_mem_type,
522 .evict_flags = &radeon_evict_flags,
523 .move = &radeon_bo_move,
524 .verify_access = &radeon_verify_access,
525 .sync_obj_signaled = &radeon_sync_obj_signaled,
526 .sync_obj_wait = &radeon_sync_obj_wait,
527 .sync_obj_flush = &radeon_sync_obj_flush,
528 .sync_obj_unref = &radeon_sync_obj_unref,
529 .sync_obj_ref = &radeon_sync_obj_ref,
530 .move_notify = &radeon_bo_move_notify,
531 .fault_reserve_notify = &radeon_bo_fault_reserve_notify,
532 .io_mem_reserve = &radeon_ttm_io_mem_reserve,
533 .io_mem_free = &radeon_ttm_io_mem_free,
534};
535
536int radeon_ttm_init(struct radeon_device *rdev)
537{
538 int r;
539
540 r = radeon_ttm_global_init(rdev);
541 if (r) {
542 return r;
543 }
544 /* No others user of address space so set it to 0 */
545 r = ttm_bo_device_init(&rdev->mman.bdev,
546 rdev->mman.bo_global_ref.ref.object,
547 &radeon_bo_driver, DRM_FILE_PAGE_OFFSET,
548 rdev->need_dma32);
549 if (r) {
550 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
551 return r;
552 }
553 rdev->mman.initialized = true;
554 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM,
555 rdev->mc.real_vram_size >> PAGE_SHIFT);
556 if (r) {
557 DRM_ERROR("Failed initializing VRAM heap.\n");
558 return r;
559 }
560 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
561 RADEON_GEM_DOMAIN_VRAM,
562 &rdev->stollen_vga_memory);
563 if (r) {
564 return r;
565 }
566 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
567 if (r)
568 return r;
569 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
570 radeon_bo_unreserve(rdev->stollen_vga_memory);
571 if (r) {
572 radeon_bo_unref(&rdev->stollen_vga_memory);
573 return r;
574 }
575 DRM_INFO("radeon: %uM of VRAM memory ready\n",
576 (unsigned)rdev->mc.real_vram_size / (1024 * 1024));
577 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT,
578 rdev->mc.gtt_size >> PAGE_SHIFT);
579 if (r) {
580 DRM_ERROR("Failed initializing GTT heap.\n");
581 return r;
582 }
583 DRM_INFO("radeon: %uM of GTT memory ready.\n",
584 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
585 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
586 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
587 }
588
589 r = radeon_ttm_debugfs_init(rdev);
590 if (r) {
591 DRM_ERROR("Failed to init debugfs\n");
592 return r;
593 }
594 return 0;
595}
596
597void radeon_ttm_fini(struct radeon_device *rdev)
598{
599 int r;
600
601 if (!rdev->mman.initialized)
602 return;
603 if (rdev->stollen_vga_memory) {
604 r = radeon_bo_reserve(rdev->stollen_vga_memory, false);
605 if (r == 0) {
606 radeon_bo_unpin(rdev->stollen_vga_memory);
607 radeon_bo_unreserve(rdev->stollen_vga_memory);
608 }
609 radeon_bo_unref(&rdev->stollen_vga_memory);
610 }
611 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM);
612 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT);
613 ttm_bo_device_release(&rdev->mman.bdev);
614 radeon_gart_fini(rdev);
615 radeon_ttm_global_fini(rdev);
616 rdev->mman.initialized = false;
617 DRM_INFO("radeon: ttm finalized\n");
618}
619
620/* this should only be called at bootup or when userspace
621 * isn't running */
622void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
623{
624 struct ttm_mem_type_manager *man;
625
626 if (!rdev->mman.initialized)
627 return;
628
629 man = &rdev->mman.bdev.man[TTM_PL_VRAM];
630 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
631 man->size = size >> PAGE_SHIFT;
632}
633
634static struct vm_operations_struct radeon_ttm_vm_ops;
635static const struct vm_operations_struct *ttm_vm_ops = NULL;
636
637static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
638{
639 struct ttm_buffer_object *bo;
640 struct radeon_device *rdev;
641 int r;
642
643 bo = (struct ttm_buffer_object *)vma->vm_private_data;
644 if (bo == NULL) {
645 return VM_FAULT_NOPAGE;
646 }
647 rdev = radeon_get_rdev(bo->bdev);
648 mutex_lock(&rdev->vram_mutex);
649 r = ttm_vm_ops->fault(vma, vmf);
650 mutex_unlock(&rdev->vram_mutex);
651 return r;
652}
653
654int radeon_mmap(struct file *filp, struct vm_area_struct *vma)
655{
656 struct drm_file *file_priv;
657 struct radeon_device *rdev;
658 int r;
659
660 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) {
661 return drm_mmap(filp, vma);
662 }
663
664 file_priv = filp->private_data;
665 rdev = file_priv->minor->dev->dev_private;
666 if (rdev == NULL) {
667 return -EINVAL;
668 }
669 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev);
670 if (unlikely(r != 0)) {
671 return r;
672 }
673 if (unlikely(ttm_vm_ops == NULL)) {
674 ttm_vm_ops = vma->vm_ops;
675 radeon_ttm_vm_ops = *ttm_vm_ops;
676 radeon_ttm_vm_ops.fault = &radeon_ttm_fault;
677 }
678 vma->vm_ops = &radeon_ttm_vm_ops;
679 return 0;
680}
681
682
683/*
684 * TTM backend functions.
685 */
686struct radeon_ttm_backend {
687 struct ttm_backend backend;
688 struct radeon_device *rdev;
689 unsigned long num_pages;
690 struct page **pages;
691 struct page *dummy_read_page;
692 dma_addr_t *dma_addrs;
693 bool populated;
694 bool bound;
695 unsigned offset;
696};
697
698static int radeon_ttm_backend_populate(struct ttm_backend *backend,
699 unsigned long num_pages,
700 struct page **pages,
701 struct page *dummy_read_page,
702 dma_addr_t *dma_addrs)
703{
704 struct radeon_ttm_backend *gtt;
705
706 gtt = container_of(backend, struct radeon_ttm_backend, backend);
707 gtt->pages = pages;
708 gtt->dma_addrs = dma_addrs;
709 gtt->num_pages = num_pages;
710 gtt->dummy_read_page = dummy_read_page;
711 gtt->populated = true;
712 return 0;
713}
714
715static void radeon_ttm_backend_clear(struct ttm_backend *backend)
716{
717 struct radeon_ttm_backend *gtt;
718
719 gtt = container_of(backend, struct radeon_ttm_backend, backend);
720 gtt->pages = NULL;
721 gtt->dma_addrs = NULL;
722 gtt->num_pages = 0;
723 gtt->dummy_read_page = NULL;
724 gtt->populated = false;
725 gtt->bound = false;
726}
727
728
729static int radeon_ttm_backend_bind(struct ttm_backend *backend,
730 struct ttm_mem_reg *bo_mem)
731{
732 struct radeon_ttm_backend *gtt;
733 int r;
734
735 gtt = container_of(backend, struct radeon_ttm_backend, backend);
736 gtt->offset = bo_mem->start << PAGE_SHIFT;
737 if (!gtt->num_pages) {
738 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
739 gtt->num_pages, bo_mem, backend);
740 }
741 r = radeon_gart_bind(gtt->rdev, gtt->offset,
742 gtt->num_pages, gtt->pages, gtt->dma_addrs);
743 if (r) {
744 DRM_ERROR("failed to bind %lu pages at 0x%08X\n",
745 gtt->num_pages, gtt->offset);
746 return r;
747 }
748 gtt->bound = true;
749 return 0;
750}
751
752static int radeon_ttm_backend_unbind(struct ttm_backend *backend)
753{
754 struct radeon_ttm_backend *gtt;
755
756 gtt = container_of(backend, struct radeon_ttm_backend, backend);
757 radeon_gart_unbind(gtt->rdev, gtt->offset, gtt->num_pages);
758 gtt->bound = false;
759 return 0;
760}
761
762static void radeon_ttm_backend_destroy(struct ttm_backend *backend)
763{
764 struct radeon_ttm_backend *gtt;
765
766 gtt = container_of(backend, struct radeon_ttm_backend, backend);
767 if (gtt->bound) {
768 radeon_ttm_backend_unbind(backend);
769 }
770 kfree(gtt);
771}
772
773static struct ttm_backend_func radeon_backend_func = {
774 .populate = &radeon_ttm_backend_populate,
775 .clear = &radeon_ttm_backend_clear,
776 .bind = &radeon_ttm_backend_bind,
777 .unbind = &radeon_ttm_backend_unbind,
778 .destroy = &radeon_ttm_backend_destroy,
779};
780
781struct ttm_backend *radeon_ttm_backend_create(struct radeon_device *rdev)
782{
783 struct radeon_ttm_backend *gtt;
784
785 gtt = kzalloc(sizeof(struct radeon_ttm_backend), GFP_KERNEL);
786 if (gtt == NULL) {
787 return NULL;
788 }
789 gtt->backend.bdev = &rdev->mman.bdev;
790 gtt->backend.flags = 0;
791 gtt->backend.func = &radeon_backend_func;
792 gtt->rdev = rdev;
793 gtt->pages = NULL;
794 gtt->num_pages = 0;
795 gtt->dummy_read_page = NULL;
796 gtt->populated = false;
797 gtt->bound = false;
798 return >t->backend;
799}
800
801#define RADEON_DEBUGFS_MEM_TYPES 2
802
803#if defined(CONFIG_DEBUG_FS)
804static int radeon_mm_dump_table(struct seq_file *m, void *data)
805{
806 struct drm_info_node *node = (struct drm_info_node *)m->private;
807 struct drm_mm *mm = (struct drm_mm *)node->info_ent->data;
808 struct drm_device *dev = node->minor->dev;
809 struct radeon_device *rdev = dev->dev_private;
810 int ret;
811 struct ttm_bo_global *glob = rdev->mman.bdev.glob;
812
813 spin_lock(&glob->lru_lock);
814 ret = drm_mm_dump_table(m, mm);
815 spin_unlock(&glob->lru_lock);
816 return ret;
817}
818#endif
819
820static int radeon_ttm_debugfs_init(struct radeon_device *rdev)
821{
822#if defined(CONFIG_DEBUG_FS)
823 static struct drm_info_list radeon_mem_types_list[RADEON_DEBUGFS_MEM_TYPES+1];
824 static char radeon_mem_types_names[RADEON_DEBUGFS_MEM_TYPES+1][32];
825 unsigned i;
826
827 for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) {
828 if (i == 0)
829 sprintf(radeon_mem_types_names[i], "radeon_vram_mm");
830 else
831 sprintf(radeon_mem_types_names[i], "radeon_gtt_mm");
832 radeon_mem_types_list[i].name = radeon_mem_types_names[i];
833 radeon_mem_types_list[i].show = &radeon_mm_dump_table;
834 radeon_mem_types_list[i].driver_features = 0;
835 if (i == 0)
836 radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_VRAM].priv;
837 else
838 radeon_mem_types_list[i].data = rdev->mman.bdev.man[TTM_PL_TT].priv;
839
840 }
841 /* Add ttm page pool to debugfs */
842 sprintf(radeon_mem_types_names[i], "ttm_page_pool");
843 radeon_mem_types_list[i].name = radeon_mem_types_names[i];
844 radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs;
845 radeon_mem_types_list[i].driver_features = 0;
846 radeon_mem_types_list[i].data = NULL;
847 return radeon_debugfs_add_files(rdev, radeon_mem_types_list, RADEON_DEBUGFS_MEM_TYPES+1);
848
849#endif
850 return 0;
851}
1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32
33#include <linux/dma-mapping.h>
34#include <linux/pagemap.h>
35#include <linux/pci.h>
36#include <linux/seq_file.h>
37#include <linux/slab.h>
38#include <linux/swap.h>
39
40#include <drm/drm_device.h>
41#include <drm/drm_file.h>
42#include <drm/drm_prime.h>
43#include <drm/radeon_drm.h>
44#include <drm/ttm/ttm_bo.h>
45#include <drm/ttm/ttm_placement.h>
46#include <drm/ttm/ttm_range_manager.h>
47#include <drm/ttm/ttm_tt.h>
48
49#include "radeon_reg.h"
50#include "radeon.h"
51#include "radeon_ttm.h"
52
53static void radeon_ttm_debugfs_init(struct radeon_device *rdev);
54
55static int radeon_ttm_tt_bind(struct ttm_device *bdev, struct ttm_tt *ttm,
56 struct ttm_resource *bo_mem);
57static void radeon_ttm_tt_unbind(struct ttm_device *bdev, struct ttm_tt *ttm);
58
59struct radeon_device *radeon_get_rdev(struct ttm_device *bdev)
60{
61 struct radeon_mman *mman;
62 struct radeon_device *rdev;
63
64 mman = container_of(bdev, struct radeon_mman, bdev);
65 rdev = container_of(mman, struct radeon_device, mman);
66 return rdev;
67}
68
69static int radeon_ttm_init_vram(struct radeon_device *rdev)
70{
71 return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_VRAM,
72 false, rdev->mc.real_vram_size >> PAGE_SHIFT);
73}
74
75static int radeon_ttm_init_gtt(struct radeon_device *rdev)
76{
77 return ttm_range_man_init(&rdev->mman.bdev, TTM_PL_TT,
78 true, rdev->mc.gtt_size >> PAGE_SHIFT);
79}
80
81static void radeon_evict_flags(struct ttm_buffer_object *bo,
82 struct ttm_placement *placement)
83{
84 static const struct ttm_place placements = {
85 .fpfn = 0,
86 .lpfn = 0,
87 .mem_type = TTM_PL_SYSTEM,
88 .flags = 0
89 };
90
91 struct radeon_bo *rbo;
92
93 if (!radeon_ttm_bo_is_radeon_bo(bo)) {
94 placement->placement = &placements;
95 placement->busy_placement = &placements;
96 placement->num_placement = 1;
97 placement->num_busy_placement = 1;
98 return;
99 }
100 rbo = container_of(bo, struct radeon_bo, tbo);
101 switch (bo->resource->mem_type) {
102 case TTM_PL_VRAM:
103 if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false)
104 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
105 else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size &&
106 bo->resource->start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) {
107 unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
108 int i;
109
110 /* Try evicting to the CPU inaccessible part of VRAM
111 * first, but only set GTT as busy placement, so this
112 * BO will be evicted to GTT rather than causing other
113 * BOs to be evicted from VRAM
114 */
115 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM |
116 RADEON_GEM_DOMAIN_GTT);
117 rbo->placement.num_busy_placement = 0;
118 for (i = 0; i < rbo->placement.num_placement; i++) {
119 if (rbo->placements[i].mem_type == TTM_PL_VRAM) {
120 if (rbo->placements[i].fpfn < fpfn)
121 rbo->placements[i].fpfn = fpfn;
122 } else {
123 rbo->placement.busy_placement =
124 &rbo->placements[i];
125 rbo->placement.num_busy_placement = 1;
126 }
127 }
128 } else
129 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
130 break;
131 case TTM_PL_TT:
132 default:
133 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
134 }
135 *placement = rbo->placement;
136}
137
138static int radeon_move_blit(struct ttm_buffer_object *bo,
139 bool evict,
140 struct ttm_resource *new_mem,
141 struct ttm_resource *old_mem)
142{
143 struct radeon_device *rdev;
144 uint64_t old_start, new_start;
145 struct radeon_fence *fence;
146 unsigned num_pages;
147 int r, ridx;
148
149 rdev = radeon_get_rdev(bo->bdev);
150 ridx = radeon_copy_ring_index(rdev);
151 old_start = (u64)old_mem->start << PAGE_SHIFT;
152 new_start = (u64)new_mem->start << PAGE_SHIFT;
153
154 switch (old_mem->mem_type) {
155 case TTM_PL_VRAM:
156 old_start += rdev->mc.vram_start;
157 break;
158 case TTM_PL_TT:
159 old_start += rdev->mc.gtt_start;
160 break;
161 default:
162 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
163 return -EINVAL;
164 }
165 switch (new_mem->mem_type) {
166 case TTM_PL_VRAM:
167 new_start += rdev->mc.vram_start;
168 break;
169 case TTM_PL_TT:
170 new_start += rdev->mc.gtt_start;
171 break;
172 default:
173 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
174 return -EINVAL;
175 }
176 if (!rdev->ring[ridx].ready) {
177 DRM_ERROR("Trying to move memory with ring turned off.\n");
178 return -EINVAL;
179 }
180
181 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0);
182
183 num_pages = PFN_UP(new_mem->size) * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
184 fence = radeon_copy(rdev, old_start, new_start, num_pages, bo->base.resv);
185 if (IS_ERR(fence))
186 return PTR_ERR(fence);
187
188 r = ttm_bo_move_accel_cleanup(bo, &fence->base, evict, false, new_mem);
189 radeon_fence_unref(&fence);
190 return r;
191}
192
193static int radeon_bo_move(struct ttm_buffer_object *bo, bool evict,
194 struct ttm_operation_ctx *ctx,
195 struct ttm_resource *new_mem,
196 struct ttm_place *hop)
197{
198 struct ttm_resource *old_mem = bo->resource;
199 struct radeon_device *rdev;
200 int r;
201
202 if (new_mem->mem_type == TTM_PL_TT) {
203 r = radeon_ttm_tt_bind(bo->bdev, bo->ttm, new_mem);
204 if (r)
205 return r;
206 }
207
208 r = ttm_bo_wait_ctx(bo, ctx);
209 if (r)
210 return r;
211
212 rdev = radeon_get_rdev(bo->bdev);
213 if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM &&
214 bo->ttm == NULL)) {
215 ttm_bo_move_null(bo, new_mem);
216 goto out;
217 }
218 if (old_mem->mem_type == TTM_PL_SYSTEM &&
219 new_mem->mem_type == TTM_PL_TT) {
220 ttm_bo_move_null(bo, new_mem);
221 goto out;
222 }
223
224 if (old_mem->mem_type == TTM_PL_TT &&
225 new_mem->mem_type == TTM_PL_SYSTEM) {
226 radeon_ttm_tt_unbind(bo->bdev, bo->ttm);
227 ttm_resource_free(bo, &bo->resource);
228 ttm_bo_assign_mem(bo, new_mem);
229 goto out;
230 }
231 if (rdev->ring[radeon_copy_ring_index(rdev)].ready &&
232 rdev->asic->copy.copy != NULL) {
233 if ((old_mem->mem_type == TTM_PL_SYSTEM &&
234 new_mem->mem_type == TTM_PL_VRAM) ||
235 (old_mem->mem_type == TTM_PL_VRAM &&
236 new_mem->mem_type == TTM_PL_SYSTEM)) {
237 hop->fpfn = 0;
238 hop->lpfn = 0;
239 hop->mem_type = TTM_PL_TT;
240 hop->flags = 0;
241 return -EMULTIHOP;
242 }
243
244 r = radeon_move_blit(bo, evict, new_mem, old_mem);
245 } else {
246 r = -ENODEV;
247 }
248
249 if (r) {
250 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
251 if (r)
252 return r;
253 }
254
255out:
256 /* update statistics */
257 atomic64_add(bo->base.size, &rdev->num_bytes_moved);
258 radeon_bo_move_notify(bo);
259 return 0;
260}
261
262static int radeon_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *mem)
263{
264 struct radeon_device *rdev = radeon_get_rdev(bdev);
265 size_t bus_size = (size_t)mem->size;
266
267 switch (mem->mem_type) {
268 case TTM_PL_SYSTEM:
269 /* system memory */
270 return 0;
271 case TTM_PL_TT:
272#if IS_ENABLED(CONFIG_AGP)
273 if (rdev->flags & RADEON_IS_AGP) {
274 /* RADEON_IS_AGP is set only if AGP is active */
275 mem->bus.offset = (mem->start << PAGE_SHIFT) +
276 rdev->mc.agp_base;
277 mem->bus.is_iomem = !rdev->agp->cant_use_aperture;
278 mem->bus.caching = ttm_write_combined;
279 }
280#endif
281 break;
282 case TTM_PL_VRAM:
283 mem->bus.offset = mem->start << PAGE_SHIFT;
284 /* check if it's visible */
285 if ((mem->bus.offset + bus_size) > rdev->mc.visible_vram_size)
286 return -EINVAL;
287 mem->bus.offset += rdev->mc.aper_base;
288 mem->bus.is_iomem = true;
289 mem->bus.caching = ttm_write_combined;
290#ifdef __alpha__
291 /*
292 * Alpha: use bus.addr to hold the ioremap() return,
293 * so we can modify bus.base below.
294 */
295 mem->bus.addr = ioremap_wc(mem->bus.offset, bus_size);
296 if (!mem->bus.addr)
297 return -ENOMEM;
298
299 /*
300 * Alpha: Use just the bus offset plus
301 * the hose/domain memory base for bus.base.
302 * It then can be used to build PTEs for VRAM
303 * access, as done in ttm_bo_vm_fault().
304 */
305 mem->bus.offset = (mem->bus.offset & 0x0ffffffffUL) +
306 rdev->hose->dense_mem_base;
307#endif
308 break;
309 default:
310 return -EINVAL;
311 }
312 return 0;
313}
314
315/*
316 * TTM backend functions.
317 */
318struct radeon_ttm_tt {
319 struct ttm_tt ttm;
320 u64 offset;
321
322 uint64_t userptr;
323 struct mm_struct *usermm;
324 uint32_t userflags;
325 bool bound;
326};
327
328/* prepare the sg table with the user pages */
329static int radeon_ttm_tt_pin_userptr(struct ttm_device *bdev, struct ttm_tt *ttm)
330{
331 struct radeon_device *rdev = radeon_get_rdev(bdev);
332 struct radeon_ttm_tt *gtt = (void *)ttm;
333 unsigned pinned = 0;
334 int r;
335
336 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
337 enum dma_data_direction direction = write ?
338 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
339
340 if (current->mm != gtt->usermm)
341 return -EPERM;
342
343 if (gtt->userflags & RADEON_GEM_USERPTR_ANONONLY) {
344 /* check that we only pin down anonymous memory
345 to prevent problems with writeback */
346 unsigned long end = gtt->userptr + (u64)ttm->num_pages * PAGE_SIZE;
347 struct vm_area_struct *vma;
348 vma = find_vma(gtt->usermm, gtt->userptr);
349 if (!vma || vma->vm_file || vma->vm_end < end)
350 return -EPERM;
351 }
352
353 do {
354 unsigned num_pages = ttm->num_pages - pinned;
355 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
356 struct page **pages = ttm->pages + pinned;
357
358 r = get_user_pages(userptr, num_pages, write ? FOLL_WRITE : 0,
359 pages);
360 if (r < 0)
361 goto release_pages;
362
363 pinned += r;
364
365 } while (pinned < ttm->num_pages);
366
367 r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
368 (u64)ttm->num_pages << PAGE_SHIFT,
369 GFP_KERNEL);
370 if (r)
371 goto release_sg;
372
373 r = dma_map_sgtable(rdev->dev, ttm->sg, direction, 0);
374 if (r)
375 goto release_sg;
376
377 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
378 ttm->num_pages);
379
380 return 0;
381
382release_sg:
383 kfree(ttm->sg);
384
385release_pages:
386 release_pages(ttm->pages, pinned);
387 return r;
388}
389
390static void radeon_ttm_tt_unpin_userptr(struct ttm_device *bdev, struct ttm_tt *ttm)
391{
392 struct radeon_device *rdev = radeon_get_rdev(bdev);
393 struct radeon_ttm_tt *gtt = (void *)ttm;
394 struct sg_page_iter sg_iter;
395
396 int write = !(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
397 enum dma_data_direction direction = write ?
398 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
399
400 /* double check that we don't free the table twice */
401 if (!ttm->sg || !ttm->sg->sgl)
402 return;
403
404 /* free the sg table and pages again */
405 dma_unmap_sgtable(rdev->dev, ttm->sg, direction, 0);
406
407 for_each_sgtable_page(ttm->sg, &sg_iter, 0) {
408 struct page *page = sg_page_iter_page(&sg_iter);
409 if (!(gtt->userflags & RADEON_GEM_USERPTR_READONLY))
410 set_page_dirty(page);
411
412 mark_page_accessed(page);
413 put_page(page);
414 }
415
416 sg_free_table(ttm->sg);
417}
418
419static bool radeon_ttm_backend_is_bound(struct ttm_tt *ttm)
420{
421 struct radeon_ttm_tt *gtt = (void*)ttm;
422
423 return (gtt->bound);
424}
425
426static int radeon_ttm_backend_bind(struct ttm_device *bdev,
427 struct ttm_tt *ttm,
428 struct ttm_resource *bo_mem)
429{
430 struct radeon_ttm_tt *gtt = (void*)ttm;
431 struct radeon_device *rdev = radeon_get_rdev(bdev);
432 uint32_t flags = RADEON_GART_PAGE_VALID | RADEON_GART_PAGE_READ |
433 RADEON_GART_PAGE_WRITE;
434 int r;
435
436 if (gtt->bound)
437 return 0;
438
439 if (gtt->userptr) {
440 radeon_ttm_tt_pin_userptr(bdev, ttm);
441 flags &= ~RADEON_GART_PAGE_WRITE;
442 }
443
444 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT);
445 if (!ttm->num_pages) {
446 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
447 ttm->num_pages, bo_mem, ttm);
448 }
449 if (ttm->caching == ttm_cached)
450 flags |= RADEON_GART_PAGE_SNOOP;
451 r = radeon_gart_bind(rdev, gtt->offset, ttm->num_pages,
452 ttm->pages, gtt->ttm.dma_address, flags);
453 if (r) {
454 DRM_ERROR("failed to bind %u pages at 0x%08X\n",
455 ttm->num_pages, (unsigned)gtt->offset);
456 return r;
457 }
458 gtt->bound = true;
459 return 0;
460}
461
462static void radeon_ttm_backend_unbind(struct ttm_device *bdev, struct ttm_tt *ttm)
463{
464 struct radeon_ttm_tt *gtt = (void *)ttm;
465 struct radeon_device *rdev = radeon_get_rdev(bdev);
466
467 if (gtt->userptr)
468 radeon_ttm_tt_unpin_userptr(bdev, ttm);
469
470 if (!gtt->bound)
471 return;
472
473 radeon_gart_unbind(rdev, gtt->offset, ttm->num_pages);
474
475 gtt->bound = false;
476}
477
478static void radeon_ttm_backend_destroy(struct ttm_device *bdev, struct ttm_tt *ttm)
479{
480 struct radeon_ttm_tt *gtt = (void *)ttm;
481
482 ttm_tt_fini(>t->ttm);
483 kfree(gtt);
484}
485
486static struct ttm_tt *radeon_ttm_tt_create(struct ttm_buffer_object *bo,
487 uint32_t page_flags)
488{
489 struct radeon_ttm_tt *gtt;
490 enum ttm_caching caching;
491 struct radeon_bo *rbo;
492#if IS_ENABLED(CONFIG_AGP)
493 struct radeon_device *rdev = radeon_get_rdev(bo->bdev);
494
495 if (rdev->flags & RADEON_IS_AGP) {
496 return ttm_agp_tt_create(bo, rdev->agp->bridge, page_flags);
497 }
498#endif
499 rbo = container_of(bo, struct radeon_bo, tbo);
500
501 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL);
502 if (gtt == NULL) {
503 return NULL;
504 }
505
506 if (rbo->flags & RADEON_GEM_GTT_UC)
507 caching = ttm_uncached;
508 else if (rbo->flags & RADEON_GEM_GTT_WC)
509 caching = ttm_write_combined;
510 else
511 caching = ttm_cached;
512
513 if (ttm_sg_tt_init(>t->ttm, bo, page_flags, caching)) {
514 kfree(gtt);
515 return NULL;
516 }
517 return >t->ttm;
518}
519
520static struct radeon_ttm_tt *radeon_ttm_tt_to_gtt(struct radeon_device *rdev,
521 struct ttm_tt *ttm)
522{
523#if IS_ENABLED(CONFIG_AGP)
524 if (rdev->flags & RADEON_IS_AGP)
525 return NULL;
526#endif
527
528 if (!ttm)
529 return NULL;
530 return container_of(ttm, struct radeon_ttm_tt, ttm);
531}
532
533static int radeon_ttm_tt_populate(struct ttm_device *bdev,
534 struct ttm_tt *ttm,
535 struct ttm_operation_ctx *ctx)
536{
537 struct radeon_device *rdev = radeon_get_rdev(bdev);
538 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
539 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
540
541 if (gtt && gtt->userptr) {
542 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
543 if (!ttm->sg)
544 return -ENOMEM;
545
546 ttm->page_flags |= TTM_TT_FLAG_EXTERNAL;
547 return 0;
548 }
549
550 if (slave && ttm->sg) {
551 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
552 ttm->num_pages);
553 return 0;
554 }
555
556 return ttm_pool_alloc(&rdev->mman.bdev.pool, ttm, ctx);
557}
558
559static void radeon_ttm_tt_unpopulate(struct ttm_device *bdev, struct ttm_tt *ttm)
560{
561 struct radeon_device *rdev = radeon_get_rdev(bdev);
562 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
563 bool slave = !!(ttm->page_flags & TTM_TT_FLAG_EXTERNAL);
564
565 radeon_ttm_tt_unbind(bdev, ttm);
566
567 if (gtt && gtt->userptr) {
568 kfree(ttm->sg);
569 ttm->page_flags &= ~TTM_TT_FLAG_EXTERNAL;
570 return;
571 }
572
573 if (slave)
574 return;
575
576 return ttm_pool_free(&rdev->mman.bdev.pool, ttm);
577}
578
579int radeon_ttm_tt_set_userptr(struct radeon_device *rdev,
580 struct ttm_tt *ttm, uint64_t addr,
581 uint32_t flags)
582{
583 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
584
585 if (gtt == NULL)
586 return -EINVAL;
587
588 gtt->userptr = addr;
589 gtt->usermm = current->mm;
590 gtt->userflags = flags;
591 return 0;
592}
593
594bool radeon_ttm_tt_is_bound(struct ttm_device *bdev,
595 struct ttm_tt *ttm)
596{
597#if IS_ENABLED(CONFIG_AGP)
598 struct radeon_device *rdev = radeon_get_rdev(bdev);
599 if (rdev->flags & RADEON_IS_AGP)
600 return ttm_agp_is_bound(ttm);
601#endif
602 return radeon_ttm_backend_is_bound(ttm);
603}
604
605static int radeon_ttm_tt_bind(struct ttm_device *bdev,
606 struct ttm_tt *ttm,
607 struct ttm_resource *bo_mem)
608{
609#if IS_ENABLED(CONFIG_AGP)
610 struct radeon_device *rdev = radeon_get_rdev(bdev);
611#endif
612
613 if (!bo_mem)
614 return -EINVAL;
615#if IS_ENABLED(CONFIG_AGP)
616 if (rdev->flags & RADEON_IS_AGP)
617 return ttm_agp_bind(ttm, bo_mem);
618#endif
619
620 return radeon_ttm_backend_bind(bdev, ttm, bo_mem);
621}
622
623static void radeon_ttm_tt_unbind(struct ttm_device *bdev,
624 struct ttm_tt *ttm)
625{
626#if IS_ENABLED(CONFIG_AGP)
627 struct radeon_device *rdev = radeon_get_rdev(bdev);
628
629 if (rdev->flags & RADEON_IS_AGP) {
630 ttm_agp_unbind(ttm);
631 return;
632 }
633#endif
634 radeon_ttm_backend_unbind(bdev, ttm);
635}
636
637static void radeon_ttm_tt_destroy(struct ttm_device *bdev,
638 struct ttm_tt *ttm)
639{
640#if IS_ENABLED(CONFIG_AGP)
641 struct radeon_device *rdev = radeon_get_rdev(bdev);
642
643 if (rdev->flags & RADEON_IS_AGP) {
644 ttm_agp_destroy(ttm);
645 return;
646 }
647#endif
648 radeon_ttm_backend_destroy(bdev, ttm);
649}
650
651bool radeon_ttm_tt_has_userptr(struct radeon_device *rdev,
652 struct ttm_tt *ttm)
653{
654 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
655
656 if (gtt == NULL)
657 return false;
658
659 return !!gtt->userptr;
660}
661
662bool radeon_ttm_tt_is_readonly(struct radeon_device *rdev,
663 struct ttm_tt *ttm)
664{
665 struct radeon_ttm_tt *gtt = radeon_ttm_tt_to_gtt(rdev, ttm);
666
667 if (gtt == NULL)
668 return false;
669
670 return !!(gtt->userflags & RADEON_GEM_USERPTR_READONLY);
671}
672
673static struct ttm_device_funcs radeon_bo_driver = {
674 .ttm_tt_create = &radeon_ttm_tt_create,
675 .ttm_tt_populate = &radeon_ttm_tt_populate,
676 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate,
677 .ttm_tt_destroy = &radeon_ttm_tt_destroy,
678 .eviction_valuable = ttm_bo_eviction_valuable,
679 .evict_flags = &radeon_evict_flags,
680 .move = &radeon_bo_move,
681 .io_mem_reserve = &radeon_ttm_io_mem_reserve,
682};
683
684int radeon_ttm_init(struct radeon_device *rdev)
685{
686 int r;
687
688 /* No others user of address space so set it to 0 */
689 r = ttm_device_init(&rdev->mman.bdev, &radeon_bo_driver, rdev->dev,
690 rdev->ddev->anon_inode->i_mapping,
691 rdev->ddev->vma_offset_manager,
692 rdev->need_swiotlb,
693 dma_addressing_limited(&rdev->pdev->dev));
694 if (r) {
695 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
696 return r;
697 }
698 rdev->mman.initialized = true;
699
700 r = radeon_ttm_init_vram(rdev);
701 if (r) {
702 DRM_ERROR("Failed initializing VRAM heap.\n");
703 return r;
704 }
705 /* Change the size here instead of the init above so only lpfn is affected */
706 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
707
708 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true,
709 RADEON_GEM_DOMAIN_VRAM, 0, NULL,
710 NULL, &rdev->stolen_vga_memory);
711 if (r) {
712 return r;
713 }
714 r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
715 if (r)
716 return r;
717 r = radeon_bo_pin(rdev->stolen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL);
718 radeon_bo_unreserve(rdev->stolen_vga_memory);
719 if (r) {
720 radeon_bo_unref(&rdev->stolen_vga_memory);
721 return r;
722 }
723 DRM_INFO("radeon: %uM of VRAM memory ready\n",
724 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024)));
725
726 r = radeon_ttm_init_gtt(rdev);
727 if (r) {
728 DRM_ERROR("Failed initializing GTT heap.\n");
729 return r;
730 }
731 DRM_INFO("radeon: %uM of GTT memory ready.\n",
732 (unsigned)(rdev->mc.gtt_size / (1024 * 1024)));
733
734 radeon_ttm_debugfs_init(rdev);
735
736 return 0;
737}
738
739void radeon_ttm_fini(struct radeon_device *rdev)
740{
741 int r;
742
743 if (!rdev->mman.initialized)
744 return;
745
746 if (rdev->stolen_vga_memory) {
747 r = radeon_bo_reserve(rdev->stolen_vga_memory, false);
748 if (r == 0) {
749 radeon_bo_unpin(rdev->stolen_vga_memory);
750 radeon_bo_unreserve(rdev->stolen_vga_memory);
751 }
752 radeon_bo_unref(&rdev->stolen_vga_memory);
753 }
754 ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_VRAM);
755 ttm_range_man_fini(&rdev->mman.bdev, TTM_PL_TT);
756 ttm_device_fini(&rdev->mman.bdev);
757 radeon_gart_fini(rdev);
758 rdev->mman.initialized = false;
759 DRM_INFO("radeon: ttm finalized\n");
760}
761
762/* this should only be called at bootup or when userspace
763 * isn't running */
764void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size)
765{
766 struct ttm_resource_manager *man;
767
768 if (!rdev->mman.initialized)
769 return;
770
771 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM);
772 /* this just adjusts TTM size idea, which sets lpfn to the correct value */
773 man->size = size >> PAGE_SHIFT;
774}
775
776#if defined(CONFIG_DEBUG_FS)
777
778static int radeon_ttm_page_pool_show(struct seq_file *m, void *data)
779{
780 struct radeon_device *rdev = m->private;
781
782 return ttm_pool_debugfs(&rdev->mman.bdev.pool, m);
783}
784
785DEFINE_SHOW_ATTRIBUTE(radeon_ttm_page_pool);
786
787static int radeon_ttm_vram_open(struct inode *inode, struct file *filep)
788{
789 struct radeon_device *rdev = inode->i_private;
790 i_size_write(inode, rdev->mc.mc_vram_size);
791 filep->private_data = inode->i_private;
792 return 0;
793}
794
795static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf,
796 size_t size, loff_t *pos)
797{
798 struct radeon_device *rdev = f->private_data;
799 ssize_t result = 0;
800 int r;
801
802 if (size & 0x3 || *pos & 0x3)
803 return -EINVAL;
804
805 while (size) {
806 unsigned long flags;
807 uint32_t value;
808
809 if (*pos >= rdev->mc.mc_vram_size)
810 return result;
811
812 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
813 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000);
814 if (rdev->family >= CHIP_CEDAR)
815 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31);
816 value = RREG32(RADEON_MM_DATA);
817 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
818
819 r = put_user(value, (uint32_t __user *)buf);
820 if (r)
821 return r;
822
823 result += 4;
824 buf += 4;
825 *pos += 4;
826 size -= 4;
827 }
828
829 return result;
830}
831
832static const struct file_operations radeon_ttm_vram_fops = {
833 .owner = THIS_MODULE,
834 .open = radeon_ttm_vram_open,
835 .read = radeon_ttm_vram_read,
836 .llseek = default_llseek
837};
838
839static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep)
840{
841 struct radeon_device *rdev = inode->i_private;
842 i_size_write(inode, rdev->mc.gtt_size);
843 filep->private_data = inode->i_private;
844 return 0;
845}
846
847static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf,
848 size_t size, loff_t *pos)
849{
850 struct radeon_device *rdev = f->private_data;
851 ssize_t result = 0;
852 int r;
853
854 while (size) {
855 loff_t p = *pos / PAGE_SIZE;
856 unsigned off = *pos & ~PAGE_MASK;
857 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
858 struct page *page;
859 void *ptr;
860
861 if (p >= rdev->gart.num_cpu_pages)
862 return result;
863
864 page = rdev->gart.pages[p];
865 if (page) {
866 ptr = kmap_local_page(page);
867 ptr += off;
868
869 r = copy_to_user(buf, ptr, cur_size);
870 kunmap_local(ptr);
871 } else
872 r = clear_user(buf, cur_size);
873
874 if (r)
875 return -EFAULT;
876
877 result += cur_size;
878 buf += cur_size;
879 *pos += cur_size;
880 size -= cur_size;
881 }
882
883 return result;
884}
885
886static const struct file_operations radeon_ttm_gtt_fops = {
887 .owner = THIS_MODULE,
888 .open = radeon_ttm_gtt_open,
889 .read = radeon_ttm_gtt_read,
890 .llseek = default_llseek
891};
892
893#endif
894
895static void radeon_ttm_debugfs_init(struct radeon_device *rdev)
896{
897#if defined(CONFIG_DEBUG_FS)
898 struct drm_minor *minor = rdev->ddev->primary;
899 struct dentry *root = minor->debugfs_root;
900
901 debugfs_create_file("radeon_vram", 0444, root, rdev,
902 &radeon_ttm_vram_fops);
903 debugfs_create_file("radeon_gtt", 0444, root, rdev,
904 &radeon_ttm_gtt_fops);
905 debugfs_create_file("ttm_page_pool", 0444, root, rdev,
906 &radeon_ttm_page_pool_fops);
907 ttm_resource_manager_create_debugfs(ttm_manager_type(&rdev->mman.bdev,
908 TTM_PL_VRAM),
909 root, "radeon_vram_mm");
910 ttm_resource_manager_create_debugfs(ttm_manager_type(&rdev->mman.bdev,
911 TTM_PL_TT),
912 root, "radeon_gtt_mm");
913#endif
914}