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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include <linux/slab.h>
30#include "drmP.h"
31#include "drm.h"
32#include "radeon_drm.h"
33#include "radeon_reg.h"
34#include "radeon.h"
35#include "radeon_asic.h"
36#include "r100d.h"
37#include "rs100d.h"
38#include "rv200d.h"
39#include "rv250d.h"
40#include "atom.h"
41
42#include <linux/firmware.h>
43#include <linux/platform_device.h>
44
45#include "r100_reg_safe.h"
46#include "rn50_reg_safe.h"
47
48/* Firmware Names */
49#define FIRMWARE_R100 "radeon/R100_cp.bin"
50#define FIRMWARE_R200 "radeon/R200_cp.bin"
51#define FIRMWARE_R300 "radeon/R300_cp.bin"
52#define FIRMWARE_R420 "radeon/R420_cp.bin"
53#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
54#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
55#define FIRMWARE_R520 "radeon/R520_cp.bin"
56
57MODULE_FIRMWARE(FIRMWARE_R100);
58MODULE_FIRMWARE(FIRMWARE_R200);
59MODULE_FIRMWARE(FIRMWARE_R300);
60MODULE_FIRMWARE(FIRMWARE_R420);
61MODULE_FIRMWARE(FIRMWARE_RS690);
62MODULE_FIRMWARE(FIRMWARE_RS600);
63MODULE_FIRMWARE(FIRMWARE_R520);
64
65#include "r100_track.h"
66
67/* This files gather functions specifics to:
68 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
69 */
70
71void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
72{
73 /* enable the pflip int */
74 radeon_irq_kms_pflip_irq_get(rdev, crtc);
75}
76
77void r100_post_page_flip(struct radeon_device *rdev, int crtc)
78{
79 /* disable the pflip int */
80 radeon_irq_kms_pflip_irq_put(rdev, crtc);
81}
82
83u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
84{
85 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
86 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
87
88 /* Lock the graphics update lock */
89 /* update the scanout addresses */
90 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
91
92 /* Wait for update_pending to go high. */
93 while (!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET));
94 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
95
96 /* Unlock the lock, so double-buffering can take place inside vblank */
97 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
98 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
99
100 /* Return current update_pending status: */
101 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
102}
103
104void r100_pm_get_dynpm_state(struct radeon_device *rdev)
105{
106 int i;
107 rdev->pm.dynpm_can_upclock = true;
108 rdev->pm.dynpm_can_downclock = true;
109
110 switch (rdev->pm.dynpm_planned_action) {
111 case DYNPM_ACTION_MINIMUM:
112 rdev->pm.requested_power_state_index = 0;
113 rdev->pm.dynpm_can_downclock = false;
114 break;
115 case DYNPM_ACTION_DOWNCLOCK:
116 if (rdev->pm.current_power_state_index == 0) {
117 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
118 rdev->pm.dynpm_can_downclock = false;
119 } else {
120 if (rdev->pm.active_crtc_count > 1) {
121 for (i = 0; i < rdev->pm.num_power_states; i++) {
122 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
123 continue;
124 else if (i >= rdev->pm.current_power_state_index) {
125 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
126 break;
127 } else {
128 rdev->pm.requested_power_state_index = i;
129 break;
130 }
131 }
132 } else
133 rdev->pm.requested_power_state_index =
134 rdev->pm.current_power_state_index - 1;
135 }
136 /* don't use the power state if crtcs are active and no display flag is set */
137 if ((rdev->pm.active_crtc_count > 0) &&
138 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
139 RADEON_PM_MODE_NO_DISPLAY)) {
140 rdev->pm.requested_power_state_index++;
141 }
142 break;
143 case DYNPM_ACTION_UPCLOCK:
144 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
145 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
146 rdev->pm.dynpm_can_upclock = false;
147 } else {
148 if (rdev->pm.active_crtc_count > 1) {
149 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
150 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
151 continue;
152 else if (i <= rdev->pm.current_power_state_index) {
153 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
154 break;
155 } else {
156 rdev->pm.requested_power_state_index = i;
157 break;
158 }
159 }
160 } else
161 rdev->pm.requested_power_state_index =
162 rdev->pm.current_power_state_index + 1;
163 }
164 break;
165 case DYNPM_ACTION_DEFAULT:
166 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
167 rdev->pm.dynpm_can_upclock = false;
168 break;
169 case DYNPM_ACTION_NONE:
170 default:
171 DRM_ERROR("Requested mode for not defined action\n");
172 return;
173 }
174 /* only one clock mode per power state */
175 rdev->pm.requested_clock_mode_index = 0;
176
177 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
178 rdev->pm.power_state[rdev->pm.requested_power_state_index].
179 clock_info[rdev->pm.requested_clock_mode_index].sclk,
180 rdev->pm.power_state[rdev->pm.requested_power_state_index].
181 clock_info[rdev->pm.requested_clock_mode_index].mclk,
182 rdev->pm.power_state[rdev->pm.requested_power_state_index].
183 pcie_lanes);
184}
185
186void r100_pm_init_profile(struct radeon_device *rdev)
187{
188 /* default */
189 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
190 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
191 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
192 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
193 /* low sh */
194 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
195 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
196 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
197 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
198 /* mid sh */
199 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
200 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
201 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
202 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
203 /* high sh */
204 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
205 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
206 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
207 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
208 /* low mh */
209 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
210 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
211 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
212 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
213 /* mid mh */
214 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
215 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
216 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
217 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
218 /* high mh */
219 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
220 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
221 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
222 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
223}
224
225void r100_pm_misc(struct radeon_device *rdev)
226{
227 int requested_index = rdev->pm.requested_power_state_index;
228 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
229 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
230 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
231
232 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
233 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
234 tmp = RREG32(voltage->gpio.reg);
235 if (voltage->active_high)
236 tmp |= voltage->gpio.mask;
237 else
238 tmp &= ~(voltage->gpio.mask);
239 WREG32(voltage->gpio.reg, tmp);
240 if (voltage->delay)
241 udelay(voltage->delay);
242 } else {
243 tmp = RREG32(voltage->gpio.reg);
244 if (voltage->active_high)
245 tmp &= ~voltage->gpio.mask;
246 else
247 tmp |= voltage->gpio.mask;
248 WREG32(voltage->gpio.reg, tmp);
249 if (voltage->delay)
250 udelay(voltage->delay);
251 }
252 }
253
254 sclk_cntl = RREG32_PLL(SCLK_CNTL);
255 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
256 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
257 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
258 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
259 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
260 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
261 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
262 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
263 else
264 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
265 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
266 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
267 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
268 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
269 } else
270 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
271
272 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
273 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
274 if (voltage->delay) {
275 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
276 switch (voltage->delay) {
277 case 33:
278 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
279 break;
280 case 66:
281 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
282 break;
283 case 99:
284 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
285 break;
286 case 132:
287 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
288 break;
289 }
290 } else
291 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
292 } else
293 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
294
295 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
296 sclk_cntl &= ~FORCE_HDP;
297 else
298 sclk_cntl |= FORCE_HDP;
299
300 WREG32_PLL(SCLK_CNTL, sclk_cntl);
301 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
302 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
303
304 /* set pcie lanes */
305 if ((rdev->flags & RADEON_IS_PCIE) &&
306 !(rdev->flags & RADEON_IS_IGP) &&
307 rdev->asic->set_pcie_lanes &&
308 (ps->pcie_lanes !=
309 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
310 radeon_set_pcie_lanes(rdev,
311 ps->pcie_lanes);
312 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
313 }
314}
315
316void r100_pm_prepare(struct radeon_device *rdev)
317{
318 struct drm_device *ddev = rdev->ddev;
319 struct drm_crtc *crtc;
320 struct radeon_crtc *radeon_crtc;
321 u32 tmp;
322
323 /* disable any active CRTCs */
324 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
325 radeon_crtc = to_radeon_crtc(crtc);
326 if (radeon_crtc->enabled) {
327 if (radeon_crtc->crtc_id) {
328 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
329 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
330 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
331 } else {
332 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
333 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
334 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
335 }
336 }
337 }
338}
339
340void r100_pm_finish(struct radeon_device *rdev)
341{
342 struct drm_device *ddev = rdev->ddev;
343 struct drm_crtc *crtc;
344 struct radeon_crtc *radeon_crtc;
345 u32 tmp;
346
347 /* enable any active CRTCs */
348 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
349 radeon_crtc = to_radeon_crtc(crtc);
350 if (radeon_crtc->enabled) {
351 if (radeon_crtc->crtc_id) {
352 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
353 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
354 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
355 } else {
356 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
357 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
358 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
359 }
360 }
361 }
362}
363
364bool r100_gui_idle(struct radeon_device *rdev)
365{
366 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
367 return false;
368 else
369 return true;
370}
371
372/* hpd for digital panel detect/disconnect */
373bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
374{
375 bool connected = false;
376
377 switch (hpd) {
378 case RADEON_HPD_1:
379 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
380 connected = true;
381 break;
382 case RADEON_HPD_2:
383 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
384 connected = true;
385 break;
386 default:
387 break;
388 }
389 return connected;
390}
391
392void r100_hpd_set_polarity(struct radeon_device *rdev,
393 enum radeon_hpd_id hpd)
394{
395 u32 tmp;
396 bool connected = r100_hpd_sense(rdev, hpd);
397
398 switch (hpd) {
399 case RADEON_HPD_1:
400 tmp = RREG32(RADEON_FP_GEN_CNTL);
401 if (connected)
402 tmp &= ~RADEON_FP_DETECT_INT_POL;
403 else
404 tmp |= RADEON_FP_DETECT_INT_POL;
405 WREG32(RADEON_FP_GEN_CNTL, tmp);
406 break;
407 case RADEON_HPD_2:
408 tmp = RREG32(RADEON_FP2_GEN_CNTL);
409 if (connected)
410 tmp &= ~RADEON_FP2_DETECT_INT_POL;
411 else
412 tmp |= RADEON_FP2_DETECT_INT_POL;
413 WREG32(RADEON_FP2_GEN_CNTL, tmp);
414 break;
415 default:
416 break;
417 }
418}
419
420void r100_hpd_init(struct radeon_device *rdev)
421{
422 struct drm_device *dev = rdev->ddev;
423 struct drm_connector *connector;
424
425 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
426 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
427 switch (radeon_connector->hpd.hpd) {
428 case RADEON_HPD_1:
429 rdev->irq.hpd[0] = true;
430 break;
431 case RADEON_HPD_2:
432 rdev->irq.hpd[1] = true;
433 break;
434 default:
435 break;
436 }
437 }
438 if (rdev->irq.installed)
439 r100_irq_set(rdev);
440}
441
442void r100_hpd_fini(struct radeon_device *rdev)
443{
444 struct drm_device *dev = rdev->ddev;
445 struct drm_connector *connector;
446
447 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
448 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
449 switch (radeon_connector->hpd.hpd) {
450 case RADEON_HPD_1:
451 rdev->irq.hpd[0] = false;
452 break;
453 case RADEON_HPD_2:
454 rdev->irq.hpd[1] = false;
455 break;
456 default:
457 break;
458 }
459 }
460}
461
462/*
463 * PCI GART
464 */
465void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
466{
467 /* TODO: can we do somethings here ? */
468 /* It seems hw only cache one entry so we should discard this
469 * entry otherwise if first GPU GART read hit this entry it
470 * could end up in wrong address. */
471}
472
473int r100_pci_gart_init(struct radeon_device *rdev)
474{
475 int r;
476
477 if (rdev->gart.table.ram.ptr) {
478 WARN(1, "R100 PCI GART already initialized\n");
479 return 0;
480 }
481 /* Initialize common gart structure */
482 r = radeon_gart_init(rdev);
483 if (r)
484 return r;
485 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
486 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
487 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
488 return radeon_gart_table_ram_alloc(rdev);
489}
490
491/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
492void r100_enable_bm(struct radeon_device *rdev)
493{
494 uint32_t tmp;
495 /* Enable bus mastering */
496 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
497 WREG32(RADEON_BUS_CNTL, tmp);
498}
499
500int r100_pci_gart_enable(struct radeon_device *rdev)
501{
502 uint32_t tmp;
503
504 radeon_gart_restore(rdev);
505 /* discard memory request outside of configured range */
506 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
507 WREG32(RADEON_AIC_CNTL, tmp);
508 /* set address range for PCI address translate */
509 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
510 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
511 /* set PCI GART page-table base address */
512 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
513 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
514 WREG32(RADEON_AIC_CNTL, tmp);
515 r100_pci_gart_tlb_flush(rdev);
516 rdev->gart.ready = true;
517 return 0;
518}
519
520void r100_pci_gart_disable(struct radeon_device *rdev)
521{
522 uint32_t tmp;
523
524 /* discard memory request outside of configured range */
525 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
526 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
527 WREG32(RADEON_AIC_LO_ADDR, 0);
528 WREG32(RADEON_AIC_HI_ADDR, 0);
529}
530
531int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
532{
533 if (i < 0 || i > rdev->gart.num_gpu_pages) {
534 return -EINVAL;
535 }
536 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
537 return 0;
538}
539
540void r100_pci_gart_fini(struct radeon_device *rdev)
541{
542 radeon_gart_fini(rdev);
543 r100_pci_gart_disable(rdev);
544 radeon_gart_table_ram_free(rdev);
545}
546
547int r100_irq_set(struct radeon_device *rdev)
548{
549 uint32_t tmp = 0;
550
551 if (!rdev->irq.installed) {
552 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
553 WREG32(R_000040_GEN_INT_CNTL, 0);
554 return -EINVAL;
555 }
556 if (rdev->irq.sw_int) {
557 tmp |= RADEON_SW_INT_ENABLE;
558 }
559 if (rdev->irq.gui_idle) {
560 tmp |= RADEON_GUI_IDLE_MASK;
561 }
562 if (rdev->irq.crtc_vblank_int[0] ||
563 rdev->irq.pflip[0]) {
564 tmp |= RADEON_CRTC_VBLANK_MASK;
565 }
566 if (rdev->irq.crtc_vblank_int[1] ||
567 rdev->irq.pflip[1]) {
568 tmp |= RADEON_CRTC2_VBLANK_MASK;
569 }
570 if (rdev->irq.hpd[0]) {
571 tmp |= RADEON_FP_DETECT_MASK;
572 }
573 if (rdev->irq.hpd[1]) {
574 tmp |= RADEON_FP2_DETECT_MASK;
575 }
576 WREG32(RADEON_GEN_INT_CNTL, tmp);
577 return 0;
578}
579
580void r100_irq_disable(struct radeon_device *rdev)
581{
582 u32 tmp;
583
584 WREG32(R_000040_GEN_INT_CNTL, 0);
585 /* Wait and acknowledge irq */
586 mdelay(1);
587 tmp = RREG32(R_000044_GEN_INT_STATUS);
588 WREG32(R_000044_GEN_INT_STATUS, tmp);
589}
590
591static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
592{
593 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
594 uint32_t irq_mask = RADEON_SW_INT_TEST |
595 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
596 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
597
598 /* the interrupt works, but the status bit is permanently asserted */
599 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
600 if (!rdev->irq.gui_idle_acked)
601 irq_mask |= RADEON_GUI_IDLE_STAT;
602 }
603
604 if (irqs) {
605 WREG32(RADEON_GEN_INT_STATUS, irqs);
606 }
607 return irqs & irq_mask;
608}
609
610int r100_irq_process(struct radeon_device *rdev)
611{
612 uint32_t status, msi_rearm;
613 bool queue_hotplug = false;
614
615 /* reset gui idle ack. the status bit is broken */
616 rdev->irq.gui_idle_acked = false;
617
618 status = r100_irq_ack(rdev);
619 if (!status) {
620 return IRQ_NONE;
621 }
622 if (rdev->shutdown) {
623 return IRQ_NONE;
624 }
625 while (status) {
626 /* SW interrupt */
627 if (status & RADEON_SW_INT_TEST) {
628 radeon_fence_process(rdev);
629 }
630 /* gui idle interrupt */
631 if (status & RADEON_GUI_IDLE_STAT) {
632 rdev->irq.gui_idle_acked = true;
633 rdev->pm.gui_idle = true;
634 wake_up(&rdev->irq.idle_queue);
635 }
636 /* Vertical blank interrupts */
637 if (status & RADEON_CRTC_VBLANK_STAT) {
638 if (rdev->irq.crtc_vblank_int[0]) {
639 drm_handle_vblank(rdev->ddev, 0);
640 rdev->pm.vblank_sync = true;
641 wake_up(&rdev->irq.vblank_queue);
642 }
643 if (rdev->irq.pflip[0])
644 radeon_crtc_handle_flip(rdev, 0);
645 }
646 if (status & RADEON_CRTC2_VBLANK_STAT) {
647 if (rdev->irq.crtc_vblank_int[1]) {
648 drm_handle_vblank(rdev->ddev, 1);
649 rdev->pm.vblank_sync = true;
650 wake_up(&rdev->irq.vblank_queue);
651 }
652 if (rdev->irq.pflip[1])
653 radeon_crtc_handle_flip(rdev, 1);
654 }
655 if (status & RADEON_FP_DETECT_STAT) {
656 queue_hotplug = true;
657 DRM_DEBUG("HPD1\n");
658 }
659 if (status & RADEON_FP2_DETECT_STAT) {
660 queue_hotplug = true;
661 DRM_DEBUG("HPD2\n");
662 }
663 status = r100_irq_ack(rdev);
664 }
665 /* reset gui idle ack. the status bit is broken */
666 rdev->irq.gui_idle_acked = false;
667 if (queue_hotplug)
668 schedule_work(&rdev->hotplug_work);
669 if (rdev->msi_enabled) {
670 switch (rdev->family) {
671 case CHIP_RS400:
672 case CHIP_RS480:
673 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
674 WREG32(RADEON_AIC_CNTL, msi_rearm);
675 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
676 break;
677 default:
678 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
679 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
680 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
681 break;
682 }
683 }
684 return IRQ_HANDLED;
685}
686
687u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
688{
689 if (crtc == 0)
690 return RREG32(RADEON_CRTC_CRNT_FRAME);
691 else
692 return RREG32(RADEON_CRTC2_CRNT_FRAME);
693}
694
695/* Who ever call radeon_fence_emit should call ring_lock and ask
696 * for enough space (today caller are ib schedule and buffer move) */
697void r100_fence_ring_emit(struct radeon_device *rdev,
698 struct radeon_fence *fence)
699{
700 /* We have to make sure that caches are flushed before
701 * CPU might read something from VRAM. */
702 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
703 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
704 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
705 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
706 /* Wait until IDLE & CLEAN */
707 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
708 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
709 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
710 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
711 RADEON_HDP_READ_BUFFER_INVALIDATE);
712 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
713 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
714 /* Emit fence sequence & fire IRQ */
715 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
716 radeon_ring_write(rdev, fence->seq);
717 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
718 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
719}
720
721int r100_copy_blit(struct radeon_device *rdev,
722 uint64_t src_offset,
723 uint64_t dst_offset,
724 unsigned num_gpu_pages,
725 struct radeon_fence *fence)
726{
727 uint32_t cur_pages;
728 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
729 uint32_t pitch;
730 uint32_t stride_pixels;
731 unsigned ndw;
732 int num_loops;
733 int r = 0;
734
735 /* radeon limited to 16k stride */
736 stride_bytes &= 0x3fff;
737 /* radeon pitch is /64 */
738 pitch = stride_bytes / 64;
739 stride_pixels = stride_bytes / 4;
740 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
741
742 /* Ask for enough room for blit + flush + fence */
743 ndw = 64 + (10 * num_loops);
744 r = radeon_ring_lock(rdev, ndw);
745 if (r) {
746 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
747 return -EINVAL;
748 }
749 while (num_gpu_pages > 0) {
750 cur_pages = num_gpu_pages;
751 if (cur_pages > 8191) {
752 cur_pages = 8191;
753 }
754 num_gpu_pages -= cur_pages;
755
756 /* pages are in Y direction - height
757 page width in X direction - width */
758 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
759 radeon_ring_write(rdev,
760 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
761 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
762 RADEON_GMC_SRC_CLIPPING |
763 RADEON_GMC_DST_CLIPPING |
764 RADEON_GMC_BRUSH_NONE |
765 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
766 RADEON_GMC_SRC_DATATYPE_COLOR |
767 RADEON_ROP3_S |
768 RADEON_DP_SRC_SOURCE_MEMORY |
769 RADEON_GMC_CLR_CMP_CNTL_DIS |
770 RADEON_GMC_WR_MSK_DIS);
771 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
772 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
773 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
774 radeon_ring_write(rdev, 0);
775 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
776 radeon_ring_write(rdev, num_gpu_pages);
777 radeon_ring_write(rdev, num_gpu_pages);
778 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
779 }
780 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
781 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
782 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
783 radeon_ring_write(rdev,
784 RADEON_WAIT_2D_IDLECLEAN |
785 RADEON_WAIT_HOST_IDLECLEAN |
786 RADEON_WAIT_DMA_GUI_IDLE);
787 if (fence) {
788 r = radeon_fence_emit(rdev, fence);
789 }
790 radeon_ring_unlock_commit(rdev);
791 return r;
792}
793
794static int r100_cp_wait_for_idle(struct radeon_device *rdev)
795{
796 unsigned i;
797 u32 tmp;
798
799 for (i = 0; i < rdev->usec_timeout; i++) {
800 tmp = RREG32(R_000E40_RBBM_STATUS);
801 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
802 return 0;
803 }
804 udelay(1);
805 }
806 return -1;
807}
808
809void r100_ring_start(struct radeon_device *rdev)
810{
811 int r;
812
813 r = radeon_ring_lock(rdev, 2);
814 if (r) {
815 return;
816 }
817 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
818 radeon_ring_write(rdev,
819 RADEON_ISYNC_ANY2D_IDLE3D |
820 RADEON_ISYNC_ANY3D_IDLE2D |
821 RADEON_ISYNC_WAIT_IDLEGUI |
822 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
823 radeon_ring_unlock_commit(rdev);
824}
825
826
827/* Load the microcode for the CP */
828static int r100_cp_init_microcode(struct radeon_device *rdev)
829{
830 struct platform_device *pdev;
831 const char *fw_name = NULL;
832 int err;
833
834 DRM_DEBUG_KMS("\n");
835
836 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
837 err = IS_ERR(pdev);
838 if (err) {
839 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
840 return -EINVAL;
841 }
842 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
843 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
844 (rdev->family == CHIP_RS200)) {
845 DRM_INFO("Loading R100 Microcode\n");
846 fw_name = FIRMWARE_R100;
847 } else if ((rdev->family == CHIP_R200) ||
848 (rdev->family == CHIP_RV250) ||
849 (rdev->family == CHIP_RV280) ||
850 (rdev->family == CHIP_RS300)) {
851 DRM_INFO("Loading R200 Microcode\n");
852 fw_name = FIRMWARE_R200;
853 } else if ((rdev->family == CHIP_R300) ||
854 (rdev->family == CHIP_R350) ||
855 (rdev->family == CHIP_RV350) ||
856 (rdev->family == CHIP_RV380) ||
857 (rdev->family == CHIP_RS400) ||
858 (rdev->family == CHIP_RS480)) {
859 DRM_INFO("Loading R300 Microcode\n");
860 fw_name = FIRMWARE_R300;
861 } else if ((rdev->family == CHIP_R420) ||
862 (rdev->family == CHIP_R423) ||
863 (rdev->family == CHIP_RV410)) {
864 DRM_INFO("Loading R400 Microcode\n");
865 fw_name = FIRMWARE_R420;
866 } else if ((rdev->family == CHIP_RS690) ||
867 (rdev->family == CHIP_RS740)) {
868 DRM_INFO("Loading RS690/RS740 Microcode\n");
869 fw_name = FIRMWARE_RS690;
870 } else if (rdev->family == CHIP_RS600) {
871 DRM_INFO("Loading RS600 Microcode\n");
872 fw_name = FIRMWARE_RS600;
873 } else if ((rdev->family == CHIP_RV515) ||
874 (rdev->family == CHIP_R520) ||
875 (rdev->family == CHIP_RV530) ||
876 (rdev->family == CHIP_R580) ||
877 (rdev->family == CHIP_RV560) ||
878 (rdev->family == CHIP_RV570)) {
879 DRM_INFO("Loading R500 Microcode\n");
880 fw_name = FIRMWARE_R520;
881 }
882
883 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
884 platform_device_unregister(pdev);
885 if (err) {
886 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
887 fw_name);
888 } else if (rdev->me_fw->size % 8) {
889 printk(KERN_ERR
890 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
891 rdev->me_fw->size, fw_name);
892 err = -EINVAL;
893 release_firmware(rdev->me_fw);
894 rdev->me_fw = NULL;
895 }
896 return err;
897}
898
899static void r100_cp_load_microcode(struct radeon_device *rdev)
900{
901 const __be32 *fw_data;
902 int i, size;
903
904 if (r100_gui_wait_for_idle(rdev)) {
905 printk(KERN_WARNING "Failed to wait GUI idle while "
906 "programming pipes. Bad things might happen.\n");
907 }
908
909 if (rdev->me_fw) {
910 size = rdev->me_fw->size / 4;
911 fw_data = (const __be32 *)&rdev->me_fw->data[0];
912 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
913 for (i = 0; i < size; i += 2) {
914 WREG32(RADEON_CP_ME_RAM_DATAH,
915 be32_to_cpup(&fw_data[i]));
916 WREG32(RADEON_CP_ME_RAM_DATAL,
917 be32_to_cpup(&fw_data[i + 1]));
918 }
919 }
920}
921
922int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
923{
924 unsigned rb_bufsz;
925 unsigned rb_blksz;
926 unsigned max_fetch;
927 unsigned pre_write_timer;
928 unsigned pre_write_limit;
929 unsigned indirect2_start;
930 unsigned indirect1_start;
931 uint32_t tmp;
932 int r;
933
934 if (r100_debugfs_cp_init(rdev)) {
935 DRM_ERROR("Failed to register debugfs file for CP !\n");
936 }
937 if (!rdev->me_fw) {
938 r = r100_cp_init_microcode(rdev);
939 if (r) {
940 DRM_ERROR("Failed to load firmware!\n");
941 return r;
942 }
943 }
944
945 /* Align ring size */
946 rb_bufsz = drm_order(ring_size / 8);
947 ring_size = (1 << (rb_bufsz + 1)) * 4;
948 r100_cp_load_microcode(rdev);
949 r = radeon_ring_init(rdev, ring_size);
950 if (r) {
951 return r;
952 }
953 /* Each time the cp read 1024 bytes (16 dword/quadword) update
954 * the rptr copy in system ram */
955 rb_blksz = 9;
956 /* cp will read 128bytes at a time (4 dwords) */
957 max_fetch = 1;
958 rdev->cp.align_mask = 16 - 1;
959 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
960 pre_write_timer = 64;
961 /* Force CP_RB_WPTR write if written more than one time before the
962 * delay expire
963 */
964 pre_write_limit = 0;
965 /* Setup the cp cache like this (cache size is 96 dwords) :
966 * RING 0 to 15
967 * INDIRECT1 16 to 79
968 * INDIRECT2 80 to 95
969 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
970 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
971 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
972 * Idea being that most of the gpu cmd will be through indirect1 buffer
973 * so it gets the bigger cache.
974 */
975 indirect2_start = 80;
976 indirect1_start = 16;
977 /* cp setup */
978 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
979 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
980 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
981 REG_SET(RADEON_MAX_FETCH, max_fetch));
982#ifdef __BIG_ENDIAN
983 tmp |= RADEON_BUF_SWAP_32BIT;
984#endif
985 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
986
987 /* Set ring address */
988 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
989 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
990 /* Force read & write ptr to 0 */
991 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
992 WREG32(RADEON_CP_RB_RPTR_WR, 0);
993 rdev->cp.wptr = 0;
994 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
995
996 /* set the wb address whether it's enabled or not */
997 WREG32(R_00070C_CP_RB_RPTR_ADDR,
998 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
999 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1000
1001 if (rdev->wb.enabled)
1002 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1003 else {
1004 tmp |= RADEON_RB_NO_UPDATE;
1005 WREG32(R_000770_SCRATCH_UMSK, 0);
1006 }
1007
1008 WREG32(RADEON_CP_RB_CNTL, tmp);
1009 udelay(10);
1010 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1011 /* Set cp mode to bus mastering & enable cp*/
1012 WREG32(RADEON_CP_CSQ_MODE,
1013 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1014 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1015 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1016 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1017 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1018 radeon_ring_start(rdev);
1019 r = radeon_ring_test(rdev);
1020 if (r) {
1021 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1022 return r;
1023 }
1024 rdev->cp.ready = true;
1025 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1026 return 0;
1027}
1028
1029void r100_cp_fini(struct radeon_device *rdev)
1030{
1031 if (r100_cp_wait_for_idle(rdev)) {
1032 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1033 }
1034 /* Disable ring */
1035 r100_cp_disable(rdev);
1036 radeon_ring_fini(rdev);
1037 DRM_INFO("radeon: cp finalized\n");
1038}
1039
1040void r100_cp_disable(struct radeon_device *rdev)
1041{
1042 /* Disable ring */
1043 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1044 rdev->cp.ready = false;
1045 WREG32(RADEON_CP_CSQ_MODE, 0);
1046 WREG32(RADEON_CP_CSQ_CNTL, 0);
1047 WREG32(R_000770_SCRATCH_UMSK, 0);
1048 if (r100_gui_wait_for_idle(rdev)) {
1049 printk(KERN_WARNING "Failed to wait GUI idle while "
1050 "programming pipes. Bad things might happen.\n");
1051 }
1052}
1053
1054void r100_cp_commit(struct radeon_device *rdev)
1055{
1056 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1057 (void)RREG32(RADEON_CP_RB_WPTR);
1058}
1059
1060
1061/*
1062 * CS functions
1063 */
1064int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1065 struct radeon_cs_packet *pkt,
1066 const unsigned *auth, unsigned n,
1067 radeon_packet0_check_t check)
1068{
1069 unsigned reg;
1070 unsigned i, j, m;
1071 unsigned idx;
1072 int r;
1073
1074 idx = pkt->idx + 1;
1075 reg = pkt->reg;
1076 /* Check that register fall into register range
1077 * determined by the number of entry (n) in the
1078 * safe register bitmap.
1079 */
1080 if (pkt->one_reg_wr) {
1081 if ((reg >> 7) > n) {
1082 return -EINVAL;
1083 }
1084 } else {
1085 if (((reg + (pkt->count << 2)) >> 7) > n) {
1086 return -EINVAL;
1087 }
1088 }
1089 for (i = 0; i <= pkt->count; i++, idx++) {
1090 j = (reg >> 7);
1091 m = 1 << ((reg >> 2) & 31);
1092 if (auth[j] & m) {
1093 r = check(p, pkt, idx, reg);
1094 if (r) {
1095 return r;
1096 }
1097 }
1098 if (pkt->one_reg_wr) {
1099 if (!(auth[j] & m)) {
1100 break;
1101 }
1102 } else {
1103 reg += 4;
1104 }
1105 }
1106 return 0;
1107}
1108
1109void r100_cs_dump_packet(struct radeon_cs_parser *p,
1110 struct radeon_cs_packet *pkt)
1111{
1112 volatile uint32_t *ib;
1113 unsigned i;
1114 unsigned idx;
1115
1116 ib = p->ib->ptr;
1117 idx = pkt->idx;
1118 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1119 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1120 }
1121}
1122
1123/**
1124 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1125 * @parser: parser structure holding parsing context.
1126 * @pkt: where to store packet informations
1127 *
1128 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1129 * if packet is bigger than remaining ib size. or if packets is unknown.
1130 **/
1131int r100_cs_packet_parse(struct radeon_cs_parser *p,
1132 struct radeon_cs_packet *pkt,
1133 unsigned idx)
1134{
1135 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1136 uint32_t header;
1137
1138 if (idx >= ib_chunk->length_dw) {
1139 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1140 idx, ib_chunk->length_dw);
1141 return -EINVAL;
1142 }
1143 header = radeon_get_ib_value(p, idx);
1144 pkt->idx = idx;
1145 pkt->type = CP_PACKET_GET_TYPE(header);
1146 pkt->count = CP_PACKET_GET_COUNT(header);
1147 switch (pkt->type) {
1148 case PACKET_TYPE0:
1149 pkt->reg = CP_PACKET0_GET_REG(header);
1150 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1151 break;
1152 case PACKET_TYPE3:
1153 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1154 break;
1155 case PACKET_TYPE2:
1156 pkt->count = -1;
1157 break;
1158 default:
1159 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1160 return -EINVAL;
1161 }
1162 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1163 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1164 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1165 return -EINVAL;
1166 }
1167 return 0;
1168}
1169
1170/**
1171 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1172 * @parser: parser structure holding parsing context.
1173 *
1174 * Userspace sends a special sequence for VLINE waits.
1175 * PACKET0 - VLINE_START_END + value
1176 * PACKET0 - WAIT_UNTIL +_value
1177 * RELOC (P3) - crtc_id in reloc.
1178 *
1179 * This function parses this and relocates the VLINE START END
1180 * and WAIT UNTIL packets to the correct crtc.
1181 * It also detects a switched off crtc and nulls out the
1182 * wait in that case.
1183 */
1184int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1185{
1186 struct drm_mode_object *obj;
1187 struct drm_crtc *crtc;
1188 struct radeon_crtc *radeon_crtc;
1189 struct radeon_cs_packet p3reloc, waitreloc;
1190 int crtc_id;
1191 int r;
1192 uint32_t header, h_idx, reg;
1193 volatile uint32_t *ib;
1194
1195 ib = p->ib->ptr;
1196
1197 /* parse the wait until */
1198 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1199 if (r)
1200 return r;
1201
1202 /* check its a wait until and only 1 count */
1203 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1204 waitreloc.count != 0) {
1205 DRM_ERROR("vline wait had illegal wait until segment\n");
1206 return -EINVAL;
1207 }
1208
1209 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1210 DRM_ERROR("vline wait had illegal wait until\n");
1211 return -EINVAL;
1212 }
1213
1214 /* jump over the NOP */
1215 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1216 if (r)
1217 return r;
1218
1219 h_idx = p->idx - 2;
1220 p->idx += waitreloc.count + 2;
1221 p->idx += p3reloc.count + 2;
1222
1223 header = radeon_get_ib_value(p, h_idx);
1224 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1225 reg = CP_PACKET0_GET_REG(header);
1226 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1227 if (!obj) {
1228 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1229 return -EINVAL;
1230 }
1231 crtc = obj_to_crtc(obj);
1232 radeon_crtc = to_radeon_crtc(crtc);
1233 crtc_id = radeon_crtc->crtc_id;
1234
1235 if (!crtc->enabled) {
1236 /* if the CRTC isn't enabled - we need to nop out the wait until */
1237 ib[h_idx + 2] = PACKET2(0);
1238 ib[h_idx + 3] = PACKET2(0);
1239 } else if (crtc_id == 1) {
1240 switch (reg) {
1241 case AVIVO_D1MODE_VLINE_START_END:
1242 header &= ~R300_CP_PACKET0_REG_MASK;
1243 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1244 break;
1245 case RADEON_CRTC_GUI_TRIG_VLINE:
1246 header &= ~R300_CP_PACKET0_REG_MASK;
1247 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1248 break;
1249 default:
1250 DRM_ERROR("unknown crtc reloc\n");
1251 return -EINVAL;
1252 }
1253 ib[h_idx] = header;
1254 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1255 }
1256
1257 return 0;
1258}
1259
1260/**
1261 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1262 * @parser: parser structure holding parsing context.
1263 * @data: pointer to relocation data
1264 * @offset_start: starting offset
1265 * @offset_mask: offset mask (to align start offset on)
1266 * @reloc: reloc informations
1267 *
1268 * Check next packet is relocation packet3, do bo validation and compute
1269 * GPU offset using the provided start.
1270 **/
1271int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1272 struct radeon_cs_reloc **cs_reloc)
1273{
1274 struct radeon_cs_chunk *relocs_chunk;
1275 struct radeon_cs_packet p3reloc;
1276 unsigned idx;
1277 int r;
1278
1279 if (p->chunk_relocs_idx == -1) {
1280 DRM_ERROR("No relocation chunk !\n");
1281 return -EINVAL;
1282 }
1283 *cs_reloc = NULL;
1284 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1285 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1286 if (r) {
1287 return r;
1288 }
1289 p->idx += p3reloc.count + 2;
1290 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1291 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1292 p3reloc.idx);
1293 r100_cs_dump_packet(p, &p3reloc);
1294 return -EINVAL;
1295 }
1296 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1297 if (idx >= relocs_chunk->length_dw) {
1298 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1299 idx, relocs_chunk->length_dw);
1300 r100_cs_dump_packet(p, &p3reloc);
1301 return -EINVAL;
1302 }
1303 /* FIXME: we assume reloc size is 4 dwords */
1304 *cs_reloc = p->relocs_ptr[(idx / 4)];
1305 return 0;
1306}
1307
1308static int r100_get_vtx_size(uint32_t vtx_fmt)
1309{
1310 int vtx_size;
1311 vtx_size = 2;
1312 /* ordered according to bits in spec */
1313 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1314 vtx_size++;
1315 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1316 vtx_size += 3;
1317 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1318 vtx_size++;
1319 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1320 vtx_size++;
1321 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1322 vtx_size += 3;
1323 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1324 vtx_size++;
1325 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1326 vtx_size++;
1327 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1328 vtx_size += 2;
1329 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1330 vtx_size += 2;
1331 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1332 vtx_size++;
1333 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1334 vtx_size += 2;
1335 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1336 vtx_size++;
1337 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1338 vtx_size += 2;
1339 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1340 vtx_size++;
1341 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1342 vtx_size++;
1343 /* blend weight */
1344 if (vtx_fmt & (0x7 << 15))
1345 vtx_size += (vtx_fmt >> 15) & 0x7;
1346 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1347 vtx_size += 3;
1348 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1349 vtx_size += 2;
1350 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1351 vtx_size++;
1352 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1353 vtx_size++;
1354 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1355 vtx_size++;
1356 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1357 vtx_size++;
1358 return vtx_size;
1359}
1360
1361static int r100_packet0_check(struct radeon_cs_parser *p,
1362 struct radeon_cs_packet *pkt,
1363 unsigned idx, unsigned reg)
1364{
1365 struct radeon_cs_reloc *reloc;
1366 struct r100_cs_track *track;
1367 volatile uint32_t *ib;
1368 uint32_t tmp;
1369 int r;
1370 int i, face;
1371 u32 tile_flags = 0;
1372 u32 idx_value;
1373
1374 ib = p->ib->ptr;
1375 track = (struct r100_cs_track *)p->track;
1376
1377 idx_value = radeon_get_ib_value(p, idx);
1378
1379 switch (reg) {
1380 case RADEON_CRTC_GUI_TRIG_VLINE:
1381 r = r100_cs_packet_parse_vline(p);
1382 if (r) {
1383 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1384 idx, reg);
1385 r100_cs_dump_packet(p, pkt);
1386 return r;
1387 }
1388 break;
1389 /* FIXME: only allow PACKET3 blit? easier to check for out of
1390 * range access */
1391 case RADEON_DST_PITCH_OFFSET:
1392 case RADEON_SRC_PITCH_OFFSET:
1393 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1394 if (r)
1395 return r;
1396 break;
1397 case RADEON_RB3D_DEPTHOFFSET:
1398 r = r100_cs_packet_next_reloc(p, &reloc);
1399 if (r) {
1400 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1401 idx, reg);
1402 r100_cs_dump_packet(p, pkt);
1403 return r;
1404 }
1405 track->zb.robj = reloc->robj;
1406 track->zb.offset = idx_value;
1407 track->zb_dirty = true;
1408 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1409 break;
1410 case RADEON_RB3D_COLOROFFSET:
1411 r = r100_cs_packet_next_reloc(p, &reloc);
1412 if (r) {
1413 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1414 idx, reg);
1415 r100_cs_dump_packet(p, pkt);
1416 return r;
1417 }
1418 track->cb[0].robj = reloc->robj;
1419 track->cb[0].offset = idx_value;
1420 track->cb_dirty = true;
1421 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1422 break;
1423 case RADEON_PP_TXOFFSET_0:
1424 case RADEON_PP_TXOFFSET_1:
1425 case RADEON_PP_TXOFFSET_2:
1426 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1427 r = r100_cs_packet_next_reloc(p, &reloc);
1428 if (r) {
1429 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1430 idx, reg);
1431 r100_cs_dump_packet(p, pkt);
1432 return r;
1433 }
1434 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1435 track->textures[i].robj = reloc->robj;
1436 track->tex_dirty = true;
1437 break;
1438 case RADEON_PP_CUBIC_OFFSET_T0_0:
1439 case RADEON_PP_CUBIC_OFFSET_T0_1:
1440 case RADEON_PP_CUBIC_OFFSET_T0_2:
1441 case RADEON_PP_CUBIC_OFFSET_T0_3:
1442 case RADEON_PP_CUBIC_OFFSET_T0_4:
1443 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1444 r = r100_cs_packet_next_reloc(p, &reloc);
1445 if (r) {
1446 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1447 idx, reg);
1448 r100_cs_dump_packet(p, pkt);
1449 return r;
1450 }
1451 track->textures[0].cube_info[i].offset = idx_value;
1452 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1453 track->textures[0].cube_info[i].robj = reloc->robj;
1454 track->tex_dirty = true;
1455 break;
1456 case RADEON_PP_CUBIC_OFFSET_T1_0:
1457 case RADEON_PP_CUBIC_OFFSET_T1_1:
1458 case RADEON_PP_CUBIC_OFFSET_T1_2:
1459 case RADEON_PP_CUBIC_OFFSET_T1_3:
1460 case RADEON_PP_CUBIC_OFFSET_T1_4:
1461 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1462 r = r100_cs_packet_next_reloc(p, &reloc);
1463 if (r) {
1464 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1465 idx, reg);
1466 r100_cs_dump_packet(p, pkt);
1467 return r;
1468 }
1469 track->textures[1].cube_info[i].offset = idx_value;
1470 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1471 track->textures[1].cube_info[i].robj = reloc->robj;
1472 track->tex_dirty = true;
1473 break;
1474 case RADEON_PP_CUBIC_OFFSET_T2_0:
1475 case RADEON_PP_CUBIC_OFFSET_T2_1:
1476 case RADEON_PP_CUBIC_OFFSET_T2_2:
1477 case RADEON_PP_CUBIC_OFFSET_T2_3:
1478 case RADEON_PP_CUBIC_OFFSET_T2_4:
1479 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1480 r = r100_cs_packet_next_reloc(p, &reloc);
1481 if (r) {
1482 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1483 idx, reg);
1484 r100_cs_dump_packet(p, pkt);
1485 return r;
1486 }
1487 track->textures[2].cube_info[i].offset = idx_value;
1488 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1489 track->textures[2].cube_info[i].robj = reloc->robj;
1490 track->tex_dirty = true;
1491 break;
1492 case RADEON_RE_WIDTH_HEIGHT:
1493 track->maxy = ((idx_value >> 16) & 0x7FF);
1494 track->cb_dirty = true;
1495 track->zb_dirty = true;
1496 break;
1497 case RADEON_RB3D_COLORPITCH:
1498 r = r100_cs_packet_next_reloc(p, &reloc);
1499 if (r) {
1500 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1501 idx, reg);
1502 r100_cs_dump_packet(p, pkt);
1503 return r;
1504 }
1505
1506 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1507 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1508 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1509 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1510
1511 tmp = idx_value & ~(0x7 << 16);
1512 tmp |= tile_flags;
1513 ib[idx] = tmp;
1514
1515 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1516 track->cb_dirty = true;
1517 break;
1518 case RADEON_RB3D_DEPTHPITCH:
1519 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1520 track->zb_dirty = true;
1521 break;
1522 case RADEON_RB3D_CNTL:
1523 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1524 case 7:
1525 case 8:
1526 case 9:
1527 case 11:
1528 case 12:
1529 track->cb[0].cpp = 1;
1530 break;
1531 case 3:
1532 case 4:
1533 case 15:
1534 track->cb[0].cpp = 2;
1535 break;
1536 case 6:
1537 track->cb[0].cpp = 4;
1538 break;
1539 default:
1540 DRM_ERROR("Invalid color buffer format (%d) !\n",
1541 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1542 return -EINVAL;
1543 }
1544 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1545 track->cb_dirty = true;
1546 track->zb_dirty = true;
1547 break;
1548 case RADEON_RB3D_ZSTENCILCNTL:
1549 switch (idx_value & 0xf) {
1550 case 0:
1551 track->zb.cpp = 2;
1552 break;
1553 case 2:
1554 case 3:
1555 case 4:
1556 case 5:
1557 case 9:
1558 case 11:
1559 track->zb.cpp = 4;
1560 break;
1561 default:
1562 break;
1563 }
1564 track->zb_dirty = true;
1565 break;
1566 case RADEON_RB3D_ZPASS_ADDR:
1567 r = r100_cs_packet_next_reloc(p, &reloc);
1568 if (r) {
1569 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1570 idx, reg);
1571 r100_cs_dump_packet(p, pkt);
1572 return r;
1573 }
1574 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1575 break;
1576 case RADEON_PP_CNTL:
1577 {
1578 uint32_t temp = idx_value >> 4;
1579 for (i = 0; i < track->num_texture; i++)
1580 track->textures[i].enabled = !!(temp & (1 << i));
1581 track->tex_dirty = true;
1582 }
1583 break;
1584 case RADEON_SE_VF_CNTL:
1585 track->vap_vf_cntl = idx_value;
1586 break;
1587 case RADEON_SE_VTX_FMT:
1588 track->vtx_size = r100_get_vtx_size(idx_value);
1589 break;
1590 case RADEON_PP_TEX_SIZE_0:
1591 case RADEON_PP_TEX_SIZE_1:
1592 case RADEON_PP_TEX_SIZE_2:
1593 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1594 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1595 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1596 track->tex_dirty = true;
1597 break;
1598 case RADEON_PP_TEX_PITCH_0:
1599 case RADEON_PP_TEX_PITCH_1:
1600 case RADEON_PP_TEX_PITCH_2:
1601 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1602 track->textures[i].pitch = idx_value + 32;
1603 track->tex_dirty = true;
1604 break;
1605 case RADEON_PP_TXFILTER_0:
1606 case RADEON_PP_TXFILTER_1:
1607 case RADEON_PP_TXFILTER_2:
1608 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1609 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1610 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1611 tmp = (idx_value >> 23) & 0x7;
1612 if (tmp == 2 || tmp == 6)
1613 track->textures[i].roundup_w = false;
1614 tmp = (idx_value >> 27) & 0x7;
1615 if (tmp == 2 || tmp == 6)
1616 track->textures[i].roundup_h = false;
1617 track->tex_dirty = true;
1618 break;
1619 case RADEON_PP_TXFORMAT_0:
1620 case RADEON_PP_TXFORMAT_1:
1621 case RADEON_PP_TXFORMAT_2:
1622 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1623 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1624 track->textures[i].use_pitch = 1;
1625 } else {
1626 track->textures[i].use_pitch = 0;
1627 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1628 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1629 }
1630 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1631 track->textures[i].tex_coord_type = 2;
1632 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1633 case RADEON_TXFORMAT_I8:
1634 case RADEON_TXFORMAT_RGB332:
1635 case RADEON_TXFORMAT_Y8:
1636 track->textures[i].cpp = 1;
1637 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1638 break;
1639 case RADEON_TXFORMAT_AI88:
1640 case RADEON_TXFORMAT_ARGB1555:
1641 case RADEON_TXFORMAT_RGB565:
1642 case RADEON_TXFORMAT_ARGB4444:
1643 case RADEON_TXFORMAT_VYUY422:
1644 case RADEON_TXFORMAT_YVYU422:
1645 case RADEON_TXFORMAT_SHADOW16:
1646 case RADEON_TXFORMAT_LDUDV655:
1647 case RADEON_TXFORMAT_DUDV88:
1648 track->textures[i].cpp = 2;
1649 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1650 break;
1651 case RADEON_TXFORMAT_ARGB8888:
1652 case RADEON_TXFORMAT_RGBA8888:
1653 case RADEON_TXFORMAT_SHADOW32:
1654 case RADEON_TXFORMAT_LDUDUV8888:
1655 track->textures[i].cpp = 4;
1656 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1657 break;
1658 case RADEON_TXFORMAT_DXT1:
1659 track->textures[i].cpp = 1;
1660 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1661 break;
1662 case RADEON_TXFORMAT_DXT23:
1663 case RADEON_TXFORMAT_DXT45:
1664 track->textures[i].cpp = 1;
1665 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1666 break;
1667 }
1668 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1669 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1670 track->tex_dirty = true;
1671 break;
1672 case RADEON_PP_CUBIC_FACES_0:
1673 case RADEON_PP_CUBIC_FACES_1:
1674 case RADEON_PP_CUBIC_FACES_2:
1675 tmp = idx_value;
1676 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1677 for (face = 0; face < 4; face++) {
1678 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1679 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1680 }
1681 track->tex_dirty = true;
1682 break;
1683 default:
1684 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1685 reg, idx);
1686 return -EINVAL;
1687 }
1688 return 0;
1689}
1690
1691int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1692 struct radeon_cs_packet *pkt,
1693 struct radeon_bo *robj)
1694{
1695 unsigned idx;
1696 u32 value;
1697 idx = pkt->idx + 1;
1698 value = radeon_get_ib_value(p, idx + 2);
1699 if ((value + 1) > radeon_bo_size(robj)) {
1700 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1701 "(need %u have %lu) !\n",
1702 value + 1,
1703 radeon_bo_size(robj));
1704 return -EINVAL;
1705 }
1706 return 0;
1707}
1708
1709static int r100_packet3_check(struct radeon_cs_parser *p,
1710 struct radeon_cs_packet *pkt)
1711{
1712 struct radeon_cs_reloc *reloc;
1713 struct r100_cs_track *track;
1714 unsigned idx;
1715 volatile uint32_t *ib;
1716 int r;
1717
1718 ib = p->ib->ptr;
1719 idx = pkt->idx + 1;
1720 track = (struct r100_cs_track *)p->track;
1721 switch (pkt->opcode) {
1722 case PACKET3_3D_LOAD_VBPNTR:
1723 r = r100_packet3_load_vbpntr(p, pkt, idx);
1724 if (r)
1725 return r;
1726 break;
1727 case PACKET3_INDX_BUFFER:
1728 r = r100_cs_packet_next_reloc(p, &reloc);
1729 if (r) {
1730 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1731 r100_cs_dump_packet(p, pkt);
1732 return r;
1733 }
1734 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1735 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1736 if (r) {
1737 return r;
1738 }
1739 break;
1740 case 0x23:
1741 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1742 r = r100_cs_packet_next_reloc(p, &reloc);
1743 if (r) {
1744 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1745 r100_cs_dump_packet(p, pkt);
1746 return r;
1747 }
1748 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1749 track->num_arrays = 1;
1750 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1751
1752 track->arrays[0].robj = reloc->robj;
1753 track->arrays[0].esize = track->vtx_size;
1754
1755 track->max_indx = radeon_get_ib_value(p, idx+1);
1756
1757 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1758 track->immd_dwords = pkt->count - 1;
1759 r = r100_cs_track_check(p->rdev, track);
1760 if (r)
1761 return r;
1762 break;
1763 case PACKET3_3D_DRAW_IMMD:
1764 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1765 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1766 return -EINVAL;
1767 }
1768 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1769 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1770 track->immd_dwords = pkt->count - 1;
1771 r = r100_cs_track_check(p->rdev, track);
1772 if (r)
1773 return r;
1774 break;
1775 /* triggers drawing using in-packet vertex data */
1776 case PACKET3_3D_DRAW_IMMD_2:
1777 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1778 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1779 return -EINVAL;
1780 }
1781 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1782 track->immd_dwords = pkt->count;
1783 r = r100_cs_track_check(p->rdev, track);
1784 if (r)
1785 return r;
1786 break;
1787 /* triggers drawing using in-packet vertex data */
1788 case PACKET3_3D_DRAW_VBUF_2:
1789 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1790 r = r100_cs_track_check(p->rdev, track);
1791 if (r)
1792 return r;
1793 break;
1794 /* triggers drawing of vertex buffers setup elsewhere */
1795 case PACKET3_3D_DRAW_INDX_2:
1796 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1797 r = r100_cs_track_check(p->rdev, track);
1798 if (r)
1799 return r;
1800 break;
1801 /* triggers drawing using indices to vertex buffer */
1802 case PACKET3_3D_DRAW_VBUF:
1803 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1804 r = r100_cs_track_check(p->rdev, track);
1805 if (r)
1806 return r;
1807 break;
1808 /* triggers drawing of vertex buffers setup elsewhere */
1809 case PACKET3_3D_DRAW_INDX:
1810 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1811 r = r100_cs_track_check(p->rdev, track);
1812 if (r)
1813 return r;
1814 break;
1815 /* triggers drawing using indices to vertex buffer */
1816 case PACKET3_3D_CLEAR_HIZ:
1817 case PACKET3_3D_CLEAR_ZMASK:
1818 if (p->rdev->hyperz_filp != p->filp)
1819 return -EINVAL;
1820 break;
1821 case PACKET3_NOP:
1822 break;
1823 default:
1824 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1825 return -EINVAL;
1826 }
1827 return 0;
1828}
1829
1830int r100_cs_parse(struct radeon_cs_parser *p)
1831{
1832 struct radeon_cs_packet pkt;
1833 struct r100_cs_track *track;
1834 int r;
1835
1836 track = kzalloc(sizeof(*track), GFP_KERNEL);
1837 r100_cs_track_clear(p->rdev, track);
1838 p->track = track;
1839 do {
1840 r = r100_cs_packet_parse(p, &pkt, p->idx);
1841 if (r) {
1842 return r;
1843 }
1844 p->idx += pkt.count + 2;
1845 switch (pkt.type) {
1846 case PACKET_TYPE0:
1847 if (p->rdev->family >= CHIP_R200)
1848 r = r100_cs_parse_packet0(p, &pkt,
1849 p->rdev->config.r100.reg_safe_bm,
1850 p->rdev->config.r100.reg_safe_bm_size,
1851 &r200_packet0_check);
1852 else
1853 r = r100_cs_parse_packet0(p, &pkt,
1854 p->rdev->config.r100.reg_safe_bm,
1855 p->rdev->config.r100.reg_safe_bm_size,
1856 &r100_packet0_check);
1857 break;
1858 case PACKET_TYPE2:
1859 break;
1860 case PACKET_TYPE3:
1861 r = r100_packet3_check(p, &pkt);
1862 break;
1863 default:
1864 DRM_ERROR("Unknown packet type %d !\n",
1865 pkt.type);
1866 return -EINVAL;
1867 }
1868 if (r) {
1869 return r;
1870 }
1871 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1872 return 0;
1873}
1874
1875
1876/*
1877 * Global GPU functions
1878 */
1879void r100_errata(struct radeon_device *rdev)
1880{
1881 rdev->pll_errata = 0;
1882
1883 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1884 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1885 }
1886
1887 if (rdev->family == CHIP_RV100 ||
1888 rdev->family == CHIP_RS100 ||
1889 rdev->family == CHIP_RS200) {
1890 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1891 }
1892}
1893
1894/* Wait for vertical sync on primary CRTC */
1895void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1896{
1897 uint32_t crtc_gen_cntl, tmp;
1898 int i;
1899
1900 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1901 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1902 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1903 return;
1904 }
1905 /* Clear the CRTC_VBLANK_SAVE bit */
1906 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1907 for (i = 0; i < rdev->usec_timeout; i++) {
1908 tmp = RREG32(RADEON_CRTC_STATUS);
1909 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1910 return;
1911 }
1912 DRM_UDELAY(1);
1913 }
1914}
1915
1916/* Wait for vertical sync on secondary CRTC */
1917void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1918{
1919 uint32_t crtc2_gen_cntl, tmp;
1920 int i;
1921
1922 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1923 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1924 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1925 return;
1926
1927 /* Clear the CRTC_VBLANK_SAVE bit */
1928 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1929 for (i = 0; i < rdev->usec_timeout; i++) {
1930 tmp = RREG32(RADEON_CRTC2_STATUS);
1931 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1932 return;
1933 }
1934 DRM_UDELAY(1);
1935 }
1936}
1937
1938int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1939{
1940 unsigned i;
1941 uint32_t tmp;
1942
1943 for (i = 0; i < rdev->usec_timeout; i++) {
1944 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1945 if (tmp >= n) {
1946 return 0;
1947 }
1948 DRM_UDELAY(1);
1949 }
1950 return -1;
1951}
1952
1953int r100_gui_wait_for_idle(struct radeon_device *rdev)
1954{
1955 unsigned i;
1956 uint32_t tmp;
1957
1958 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1959 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1960 " Bad things might happen.\n");
1961 }
1962 for (i = 0; i < rdev->usec_timeout; i++) {
1963 tmp = RREG32(RADEON_RBBM_STATUS);
1964 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1965 return 0;
1966 }
1967 DRM_UDELAY(1);
1968 }
1969 return -1;
1970}
1971
1972int r100_mc_wait_for_idle(struct radeon_device *rdev)
1973{
1974 unsigned i;
1975 uint32_t tmp;
1976
1977 for (i = 0; i < rdev->usec_timeout; i++) {
1978 /* read MC_STATUS */
1979 tmp = RREG32(RADEON_MC_STATUS);
1980 if (tmp & RADEON_MC_IDLE) {
1981 return 0;
1982 }
1983 DRM_UDELAY(1);
1984 }
1985 return -1;
1986}
1987
1988void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
1989{
1990 lockup->last_cp_rptr = cp->rptr;
1991 lockup->last_jiffies = jiffies;
1992}
1993
1994/**
1995 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
1996 * @rdev: radeon device structure
1997 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
1998 * @cp: radeon_cp structure holding CP information
1999 *
2000 * We don't need to initialize the lockup tracking information as we will either
2001 * have CP rptr to a different value of jiffies wrap around which will force
2002 * initialization of the lockup tracking informations.
2003 *
2004 * A possible false positivie is if we get call after while and last_cp_rptr ==
2005 * the current CP rptr, even if it's unlikely it might happen. To avoid this
2006 * if the elapsed time since last call is bigger than 2 second than we return
2007 * false and update the tracking information. Due to this the caller must call
2008 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2009 * the fencing code should be cautious about that.
2010 *
2011 * Caller should write to the ring to force CP to do something so we don't get
2012 * false positive when CP is just gived nothing to do.
2013 *
2014 **/
2015bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2016{
2017 unsigned long cjiffies, elapsed;
2018
2019 cjiffies = jiffies;
2020 if (!time_after(cjiffies, lockup->last_jiffies)) {
2021 /* likely a wrap around */
2022 lockup->last_cp_rptr = cp->rptr;
2023 lockup->last_jiffies = jiffies;
2024 return false;
2025 }
2026 if (cp->rptr != lockup->last_cp_rptr) {
2027 /* CP is still working no lockup */
2028 lockup->last_cp_rptr = cp->rptr;
2029 lockup->last_jiffies = jiffies;
2030 return false;
2031 }
2032 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2033 if (elapsed >= 10000) {
2034 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2035 return true;
2036 }
2037 /* give a chance to the GPU ... */
2038 return false;
2039}
2040
2041bool r100_gpu_is_lockup(struct radeon_device *rdev)
2042{
2043 u32 rbbm_status;
2044 int r;
2045
2046 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2047 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2048 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2049 return false;
2050 }
2051 /* force CP activities */
2052 r = radeon_ring_lock(rdev, 2);
2053 if (!r) {
2054 /* PACKET2 NOP */
2055 radeon_ring_write(rdev, 0x80000000);
2056 radeon_ring_write(rdev, 0x80000000);
2057 radeon_ring_unlock_commit(rdev);
2058 }
2059 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2060 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2061}
2062
2063void r100_bm_disable(struct radeon_device *rdev)
2064{
2065 u32 tmp;
2066
2067 /* disable bus mastering */
2068 tmp = RREG32(R_000030_BUS_CNTL);
2069 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2070 mdelay(1);
2071 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2072 mdelay(1);
2073 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2074 tmp = RREG32(RADEON_BUS_CNTL);
2075 mdelay(1);
2076 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2077 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
2078 mdelay(1);
2079}
2080
2081int r100_asic_reset(struct radeon_device *rdev)
2082{
2083 struct r100_mc_save save;
2084 u32 status, tmp;
2085 int ret = 0;
2086
2087 status = RREG32(R_000E40_RBBM_STATUS);
2088 if (!G_000E40_GUI_ACTIVE(status)) {
2089 return 0;
2090 }
2091 r100_mc_stop(rdev, &save);
2092 status = RREG32(R_000E40_RBBM_STATUS);
2093 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2094 /* stop CP */
2095 WREG32(RADEON_CP_CSQ_CNTL, 0);
2096 tmp = RREG32(RADEON_CP_RB_CNTL);
2097 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2098 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2099 WREG32(RADEON_CP_RB_WPTR, 0);
2100 WREG32(RADEON_CP_RB_CNTL, tmp);
2101 /* save PCI state */
2102 pci_save_state(rdev->pdev);
2103 /* disable bus mastering */
2104 r100_bm_disable(rdev);
2105 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2106 S_0000F0_SOFT_RESET_RE(1) |
2107 S_0000F0_SOFT_RESET_PP(1) |
2108 S_0000F0_SOFT_RESET_RB(1));
2109 RREG32(R_0000F0_RBBM_SOFT_RESET);
2110 mdelay(500);
2111 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2112 mdelay(1);
2113 status = RREG32(R_000E40_RBBM_STATUS);
2114 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2115 /* reset CP */
2116 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2117 RREG32(R_0000F0_RBBM_SOFT_RESET);
2118 mdelay(500);
2119 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2120 mdelay(1);
2121 status = RREG32(R_000E40_RBBM_STATUS);
2122 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2123 /* restore PCI & busmastering */
2124 pci_restore_state(rdev->pdev);
2125 r100_enable_bm(rdev);
2126 /* Check if GPU is idle */
2127 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2128 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2129 dev_err(rdev->dev, "failed to reset GPU\n");
2130 rdev->gpu_lockup = true;
2131 ret = -1;
2132 } else
2133 dev_info(rdev->dev, "GPU reset succeed\n");
2134 r100_mc_resume(rdev, &save);
2135 return ret;
2136}
2137
2138void r100_set_common_regs(struct radeon_device *rdev)
2139{
2140 struct drm_device *dev = rdev->ddev;
2141 bool force_dac2 = false;
2142 u32 tmp;
2143
2144 /* set these so they don't interfere with anything */
2145 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2146 WREG32(RADEON_SUBPIC_CNTL, 0);
2147 WREG32(RADEON_VIPH_CONTROL, 0);
2148 WREG32(RADEON_I2C_CNTL_1, 0);
2149 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2150 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2151 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2152
2153 /* always set up dac2 on rn50 and some rv100 as lots
2154 * of servers seem to wire it up to a VGA port but
2155 * don't report it in the bios connector
2156 * table.
2157 */
2158 switch (dev->pdev->device) {
2159 /* RN50 */
2160 case 0x515e:
2161 case 0x5969:
2162 force_dac2 = true;
2163 break;
2164 /* RV100*/
2165 case 0x5159:
2166 case 0x515a:
2167 /* DELL triple head servers */
2168 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2169 ((dev->pdev->subsystem_device == 0x016c) ||
2170 (dev->pdev->subsystem_device == 0x016d) ||
2171 (dev->pdev->subsystem_device == 0x016e) ||
2172 (dev->pdev->subsystem_device == 0x016f) ||
2173 (dev->pdev->subsystem_device == 0x0170) ||
2174 (dev->pdev->subsystem_device == 0x017d) ||
2175 (dev->pdev->subsystem_device == 0x017e) ||
2176 (dev->pdev->subsystem_device == 0x0183) ||
2177 (dev->pdev->subsystem_device == 0x018a) ||
2178 (dev->pdev->subsystem_device == 0x019a)))
2179 force_dac2 = true;
2180 break;
2181 }
2182
2183 if (force_dac2) {
2184 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2185 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2186 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2187
2188 /* For CRT on DAC2, don't turn it on if BIOS didn't
2189 enable it, even it's detected.
2190 */
2191
2192 /* force it to crtc0 */
2193 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2194 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2195 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2196
2197 /* set up the TV DAC */
2198 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2199 RADEON_TV_DAC_STD_MASK |
2200 RADEON_TV_DAC_RDACPD |
2201 RADEON_TV_DAC_GDACPD |
2202 RADEON_TV_DAC_BDACPD |
2203 RADEON_TV_DAC_BGADJ_MASK |
2204 RADEON_TV_DAC_DACADJ_MASK);
2205 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2206 RADEON_TV_DAC_NHOLD |
2207 RADEON_TV_DAC_STD_PS2 |
2208 (0x58 << 16));
2209
2210 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2211 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2212 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2213 }
2214
2215 /* switch PM block to ACPI mode */
2216 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2217 tmp &= ~RADEON_PM_MODE_SEL;
2218 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2219
2220}
2221
2222/*
2223 * VRAM info
2224 */
2225static void r100_vram_get_type(struct radeon_device *rdev)
2226{
2227 uint32_t tmp;
2228
2229 rdev->mc.vram_is_ddr = false;
2230 if (rdev->flags & RADEON_IS_IGP)
2231 rdev->mc.vram_is_ddr = true;
2232 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2233 rdev->mc.vram_is_ddr = true;
2234 if ((rdev->family == CHIP_RV100) ||
2235 (rdev->family == CHIP_RS100) ||
2236 (rdev->family == CHIP_RS200)) {
2237 tmp = RREG32(RADEON_MEM_CNTL);
2238 if (tmp & RV100_HALF_MODE) {
2239 rdev->mc.vram_width = 32;
2240 } else {
2241 rdev->mc.vram_width = 64;
2242 }
2243 if (rdev->flags & RADEON_SINGLE_CRTC) {
2244 rdev->mc.vram_width /= 4;
2245 rdev->mc.vram_is_ddr = true;
2246 }
2247 } else if (rdev->family <= CHIP_RV280) {
2248 tmp = RREG32(RADEON_MEM_CNTL);
2249 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2250 rdev->mc.vram_width = 128;
2251 } else {
2252 rdev->mc.vram_width = 64;
2253 }
2254 } else {
2255 /* newer IGPs */
2256 rdev->mc.vram_width = 128;
2257 }
2258}
2259
2260static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2261{
2262 u32 aper_size;
2263 u8 byte;
2264
2265 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2266
2267 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2268 * that is has the 2nd generation multifunction PCI interface
2269 */
2270 if (rdev->family == CHIP_RV280 ||
2271 rdev->family >= CHIP_RV350) {
2272 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2273 ~RADEON_HDP_APER_CNTL);
2274 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2275 return aper_size * 2;
2276 }
2277
2278 /* Older cards have all sorts of funny issues to deal with. First
2279 * check if it's a multifunction card by reading the PCI config
2280 * header type... Limit those to one aperture size
2281 */
2282 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2283 if (byte & 0x80) {
2284 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2285 DRM_INFO("Limiting VRAM to one aperture\n");
2286 return aper_size;
2287 }
2288
2289 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2290 * have set it up. We don't write this as it's broken on some ASICs but
2291 * we expect the BIOS to have done the right thing (might be too optimistic...)
2292 */
2293 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2294 return aper_size * 2;
2295 return aper_size;
2296}
2297
2298void r100_vram_init_sizes(struct radeon_device *rdev)
2299{
2300 u64 config_aper_size;
2301
2302 /* work out accessible VRAM */
2303 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2304 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2305 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2306 /* FIXME we don't use the second aperture yet when we could use it */
2307 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2308 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2309 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2310 if (rdev->flags & RADEON_IS_IGP) {
2311 uint32_t tom;
2312 /* read NB_TOM to get the amount of ram stolen for the GPU */
2313 tom = RREG32(RADEON_NB_TOM);
2314 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2315 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2316 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2317 } else {
2318 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2319 /* Some production boards of m6 will report 0
2320 * if it's 8 MB
2321 */
2322 if (rdev->mc.real_vram_size == 0) {
2323 rdev->mc.real_vram_size = 8192 * 1024;
2324 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2325 }
2326 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2327 * Novell bug 204882 + along with lots of ubuntu ones
2328 */
2329 if (rdev->mc.aper_size > config_aper_size)
2330 config_aper_size = rdev->mc.aper_size;
2331
2332 if (config_aper_size > rdev->mc.real_vram_size)
2333 rdev->mc.mc_vram_size = config_aper_size;
2334 else
2335 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2336 }
2337}
2338
2339void r100_vga_set_state(struct radeon_device *rdev, bool state)
2340{
2341 uint32_t temp;
2342
2343 temp = RREG32(RADEON_CONFIG_CNTL);
2344 if (state == false) {
2345 temp &= ~RADEON_CFG_VGA_RAM_EN;
2346 temp |= RADEON_CFG_VGA_IO_DIS;
2347 } else {
2348 temp &= ~RADEON_CFG_VGA_IO_DIS;
2349 }
2350 WREG32(RADEON_CONFIG_CNTL, temp);
2351}
2352
2353void r100_mc_init(struct radeon_device *rdev)
2354{
2355 u64 base;
2356
2357 r100_vram_get_type(rdev);
2358 r100_vram_init_sizes(rdev);
2359 base = rdev->mc.aper_base;
2360 if (rdev->flags & RADEON_IS_IGP)
2361 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2362 radeon_vram_location(rdev, &rdev->mc, base);
2363 rdev->mc.gtt_base_align = 0;
2364 if (!(rdev->flags & RADEON_IS_AGP))
2365 radeon_gtt_location(rdev, &rdev->mc);
2366 radeon_update_bandwidth_info(rdev);
2367}
2368
2369
2370/*
2371 * Indirect registers accessor
2372 */
2373void r100_pll_errata_after_index(struct radeon_device *rdev)
2374{
2375 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2376 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2377 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2378 }
2379}
2380
2381static void r100_pll_errata_after_data(struct radeon_device *rdev)
2382{
2383 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2384 * or the chip could hang on a subsequent access
2385 */
2386 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2387 udelay(5000);
2388 }
2389
2390 /* This function is required to workaround a hardware bug in some (all?)
2391 * revisions of the R300. This workaround should be called after every
2392 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2393 * may not be correct.
2394 */
2395 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2396 uint32_t save, tmp;
2397
2398 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2399 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2400 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2401 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2402 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2403 }
2404}
2405
2406uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2407{
2408 uint32_t data;
2409
2410 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2411 r100_pll_errata_after_index(rdev);
2412 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2413 r100_pll_errata_after_data(rdev);
2414 return data;
2415}
2416
2417void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2418{
2419 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2420 r100_pll_errata_after_index(rdev);
2421 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2422 r100_pll_errata_after_data(rdev);
2423}
2424
2425void r100_set_safe_registers(struct radeon_device *rdev)
2426{
2427 if (ASIC_IS_RN50(rdev)) {
2428 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2429 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2430 } else if (rdev->family < CHIP_R200) {
2431 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2432 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2433 } else {
2434 r200_set_safe_registers(rdev);
2435 }
2436}
2437
2438/*
2439 * Debugfs info
2440 */
2441#if defined(CONFIG_DEBUG_FS)
2442static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2443{
2444 struct drm_info_node *node = (struct drm_info_node *) m->private;
2445 struct drm_device *dev = node->minor->dev;
2446 struct radeon_device *rdev = dev->dev_private;
2447 uint32_t reg, value;
2448 unsigned i;
2449
2450 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2451 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2452 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2453 for (i = 0; i < 64; i++) {
2454 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2455 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2456 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2457 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2458 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2459 }
2460 return 0;
2461}
2462
2463static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2464{
2465 struct drm_info_node *node = (struct drm_info_node *) m->private;
2466 struct drm_device *dev = node->minor->dev;
2467 struct radeon_device *rdev = dev->dev_private;
2468 uint32_t rdp, wdp;
2469 unsigned count, i, j;
2470
2471 radeon_ring_free_size(rdev);
2472 rdp = RREG32(RADEON_CP_RB_RPTR);
2473 wdp = RREG32(RADEON_CP_RB_WPTR);
2474 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2475 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2476 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2477 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2478 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2479 seq_printf(m, "%u dwords in ring\n", count);
2480 for (j = 0; j <= count; j++) {
2481 i = (rdp + j) & rdev->cp.ptr_mask;
2482 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2483 }
2484 return 0;
2485}
2486
2487
2488static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2489{
2490 struct drm_info_node *node = (struct drm_info_node *) m->private;
2491 struct drm_device *dev = node->minor->dev;
2492 struct radeon_device *rdev = dev->dev_private;
2493 uint32_t csq_stat, csq2_stat, tmp;
2494 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2495 unsigned i;
2496
2497 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2498 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2499 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2500 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2501 r_rptr = (csq_stat >> 0) & 0x3ff;
2502 r_wptr = (csq_stat >> 10) & 0x3ff;
2503 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2504 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2505 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2506 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2507 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2508 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2509 seq_printf(m, "Ring rptr %u\n", r_rptr);
2510 seq_printf(m, "Ring wptr %u\n", r_wptr);
2511 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2512 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2513 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2514 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2515 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2516 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2517 seq_printf(m, "Ring fifo:\n");
2518 for (i = 0; i < 256; i++) {
2519 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2520 tmp = RREG32(RADEON_CP_CSQ_DATA);
2521 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2522 }
2523 seq_printf(m, "Indirect1 fifo:\n");
2524 for (i = 256; i <= 512; i++) {
2525 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2526 tmp = RREG32(RADEON_CP_CSQ_DATA);
2527 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2528 }
2529 seq_printf(m, "Indirect2 fifo:\n");
2530 for (i = 640; i < ib1_wptr; i++) {
2531 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2532 tmp = RREG32(RADEON_CP_CSQ_DATA);
2533 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2534 }
2535 return 0;
2536}
2537
2538static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2539{
2540 struct drm_info_node *node = (struct drm_info_node *) m->private;
2541 struct drm_device *dev = node->minor->dev;
2542 struct radeon_device *rdev = dev->dev_private;
2543 uint32_t tmp;
2544
2545 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2546 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2547 tmp = RREG32(RADEON_MC_FB_LOCATION);
2548 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2549 tmp = RREG32(RADEON_BUS_CNTL);
2550 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2551 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2552 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2553 tmp = RREG32(RADEON_AGP_BASE);
2554 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2555 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2556 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2557 tmp = RREG32(0x01D0);
2558 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2559 tmp = RREG32(RADEON_AIC_LO_ADDR);
2560 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2561 tmp = RREG32(RADEON_AIC_HI_ADDR);
2562 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2563 tmp = RREG32(0x01E4);
2564 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2565 return 0;
2566}
2567
2568static struct drm_info_list r100_debugfs_rbbm_list[] = {
2569 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2570};
2571
2572static struct drm_info_list r100_debugfs_cp_list[] = {
2573 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2574 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2575};
2576
2577static struct drm_info_list r100_debugfs_mc_info_list[] = {
2578 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2579};
2580#endif
2581
2582int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2583{
2584#if defined(CONFIG_DEBUG_FS)
2585 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2586#else
2587 return 0;
2588#endif
2589}
2590
2591int r100_debugfs_cp_init(struct radeon_device *rdev)
2592{
2593#if defined(CONFIG_DEBUG_FS)
2594 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2595#else
2596 return 0;
2597#endif
2598}
2599
2600int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2601{
2602#if defined(CONFIG_DEBUG_FS)
2603 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2604#else
2605 return 0;
2606#endif
2607}
2608
2609int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2610 uint32_t tiling_flags, uint32_t pitch,
2611 uint32_t offset, uint32_t obj_size)
2612{
2613 int surf_index = reg * 16;
2614 int flags = 0;
2615
2616 if (rdev->family <= CHIP_RS200) {
2617 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2618 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2619 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2620 if (tiling_flags & RADEON_TILING_MACRO)
2621 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2622 } else if (rdev->family <= CHIP_RV280) {
2623 if (tiling_flags & (RADEON_TILING_MACRO))
2624 flags |= R200_SURF_TILE_COLOR_MACRO;
2625 if (tiling_flags & RADEON_TILING_MICRO)
2626 flags |= R200_SURF_TILE_COLOR_MICRO;
2627 } else {
2628 if (tiling_flags & RADEON_TILING_MACRO)
2629 flags |= R300_SURF_TILE_MACRO;
2630 if (tiling_flags & RADEON_TILING_MICRO)
2631 flags |= R300_SURF_TILE_MICRO;
2632 }
2633
2634 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2635 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2636 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2637 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2638
2639 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2640 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2641 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2642 if (ASIC_IS_RN50(rdev))
2643 pitch /= 16;
2644 }
2645
2646 /* r100/r200 divide by 16 */
2647 if (rdev->family < CHIP_R300)
2648 flags |= pitch / 16;
2649 else
2650 flags |= pitch / 8;
2651
2652
2653 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2654 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2655 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2656 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2657 return 0;
2658}
2659
2660void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2661{
2662 int surf_index = reg * 16;
2663 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2664}
2665
2666void r100_bandwidth_update(struct radeon_device *rdev)
2667{
2668 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2669 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2670 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2671 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2672 fixed20_12 memtcas_ff[8] = {
2673 dfixed_init(1),
2674 dfixed_init(2),
2675 dfixed_init(3),
2676 dfixed_init(0),
2677 dfixed_init_half(1),
2678 dfixed_init_half(2),
2679 dfixed_init(0),
2680 };
2681 fixed20_12 memtcas_rs480_ff[8] = {
2682 dfixed_init(0),
2683 dfixed_init(1),
2684 dfixed_init(2),
2685 dfixed_init(3),
2686 dfixed_init(0),
2687 dfixed_init_half(1),
2688 dfixed_init_half(2),
2689 dfixed_init_half(3),
2690 };
2691 fixed20_12 memtcas2_ff[8] = {
2692 dfixed_init(0),
2693 dfixed_init(1),
2694 dfixed_init(2),
2695 dfixed_init(3),
2696 dfixed_init(4),
2697 dfixed_init(5),
2698 dfixed_init(6),
2699 dfixed_init(7),
2700 };
2701 fixed20_12 memtrbs[8] = {
2702 dfixed_init(1),
2703 dfixed_init_half(1),
2704 dfixed_init(2),
2705 dfixed_init_half(2),
2706 dfixed_init(3),
2707 dfixed_init_half(3),
2708 dfixed_init(4),
2709 dfixed_init_half(4)
2710 };
2711 fixed20_12 memtrbs_r4xx[8] = {
2712 dfixed_init(4),
2713 dfixed_init(5),
2714 dfixed_init(6),
2715 dfixed_init(7),
2716 dfixed_init(8),
2717 dfixed_init(9),
2718 dfixed_init(10),
2719 dfixed_init(11)
2720 };
2721 fixed20_12 min_mem_eff;
2722 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2723 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2724 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2725 disp_drain_rate2, read_return_rate;
2726 fixed20_12 time_disp1_drop_priority;
2727 int c;
2728 int cur_size = 16; /* in octawords */
2729 int critical_point = 0, critical_point2;
2730/* uint32_t read_return_rate, time_disp1_drop_priority; */
2731 int stop_req, max_stop_req;
2732 struct drm_display_mode *mode1 = NULL;
2733 struct drm_display_mode *mode2 = NULL;
2734 uint32_t pixel_bytes1 = 0;
2735 uint32_t pixel_bytes2 = 0;
2736
2737 radeon_update_display_priority(rdev);
2738
2739 if (rdev->mode_info.crtcs[0]->base.enabled) {
2740 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2741 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2742 }
2743 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2744 if (rdev->mode_info.crtcs[1]->base.enabled) {
2745 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2746 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2747 }
2748 }
2749
2750 min_mem_eff.full = dfixed_const_8(0);
2751 /* get modes */
2752 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2753 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2754 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2755 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2756 /* check crtc enables */
2757 if (mode2)
2758 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2759 if (mode1)
2760 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2761 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2762 }
2763
2764 /*
2765 * determine is there is enough bw for current mode
2766 */
2767 sclk_ff = rdev->pm.sclk;
2768 mclk_ff = rdev->pm.mclk;
2769
2770 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2771 temp_ff.full = dfixed_const(temp);
2772 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2773
2774 pix_clk.full = 0;
2775 pix_clk2.full = 0;
2776 peak_disp_bw.full = 0;
2777 if (mode1) {
2778 temp_ff.full = dfixed_const(1000);
2779 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2780 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2781 temp_ff.full = dfixed_const(pixel_bytes1);
2782 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2783 }
2784 if (mode2) {
2785 temp_ff.full = dfixed_const(1000);
2786 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2787 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2788 temp_ff.full = dfixed_const(pixel_bytes2);
2789 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2790 }
2791
2792 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2793 if (peak_disp_bw.full >= mem_bw.full) {
2794 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2795 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2796 }
2797
2798 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2799 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2800 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2801 mem_trcd = ((temp >> 2) & 0x3) + 1;
2802 mem_trp = ((temp & 0x3)) + 1;
2803 mem_tras = ((temp & 0x70) >> 4) + 1;
2804 } else if (rdev->family == CHIP_R300 ||
2805 rdev->family == CHIP_R350) { /* r300, r350 */
2806 mem_trcd = (temp & 0x7) + 1;
2807 mem_trp = ((temp >> 8) & 0x7) + 1;
2808 mem_tras = ((temp >> 11) & 0xf) + 4;
2809 } else if (rdev->family == CHIP_RV350 ||
2810 rdev->family <= CHIP_RV380) {
2811 /* rv3x0 */
2812 mem_trcd = (temp & 0x7) + 3;
2813 mem_trp = ((temp >> 8) & 0x7) + 3;
2814 mem_tras = ((temp >> 11) & 0xf) + 6;
2815 } else if (rdev->family == CHIP_R420 ||
2816 rdev->family == CHIP_R423 ||
2817 rdev->family == CHIP_RV410) {
2818 /* r4xx */
2819 mem_trcd = (temp & 0xf) + 3;
2820 if (mem_trcd > 15)
2821 mem_trcd = 15;
2822 mem_trp = ((temp >> 8) & 0xf) + 3;
2823 if (mem_trp > 15)
2824 mem_trp = 15;
2825 mem_tras = ((temp >> 12) & 0x1f) + 6;
2826 if (mem_tras > 31)
2827 mem_tras = 31;
2828 } else { /* RV200, R200 */
2829 mem_trcd = (temp & 0x7) + 1;
2830 mem_trp = ((temp >> 8) & 0x7) + 1;
2831 mem_tras = ((temp >> 12) & 0xf) + 4;
2832 }
2833 /* convert to FF */
2834 trcd_ff.full = dfixed_const(mem_trcd);
2835 trp_ff.full = dfixed_const(mem_trp);
2836 tras_ff.full = dfixed_const(mem_tras);
2837
2838 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2839 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2840 data = (temp & (7 << 20)) >> 20;
2841 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2842 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2843 tcas_ff = memtcas_rs480_ff[data];
2844 else
2845 tcas_ff = memtcas_ff[data];
2846 } else
2847 tcas_ff = memtcas2_ff[data];
2848
2849 if (rdev->family == CHIP_RS400 ||
2850 rdev->family == CHIP_RS480) {
2851 /* extra cas latency stored in bits 23-25 0-4 clocks */
2852 data = (temp >> 23) & 0x7;
2853 if (data < 5)
2854 tcas_ff.full += dfixed_const(data);
2855 }
2856
2857 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2858 /* on the R300, Tcas is included in Trbs.
2859 */
2860 temp = RREG32(RADEON_MEM_CNTL);
2861 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2862 if (data == 1) {
2863 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2864 temp = RREG32(R300_MC_IND_INDEX);
2865 temp &= ~R300_MC_IND_ADDR_MASK;
2866 temp |= R300_MC_READ_CNTL_CD_mcind;
2867 WREG32(R300_MC_IND_INDEX, temp);
2868 temp = RREG32(R300_MC_IND_DATA);
2869 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2870 } else {
2871 temp = RREG32(R300_MC_READ_CNTL_AB);
2872 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2873 }
2874 } else {
2875 temp = RREG32(R300_MC_READ_CNTL_AB);
2876 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2877 }
2878 if (rdev->family == CHIP_RV410 ||
2879 rdev->family == CHIP_R420 ||
2880 rdev->family == CHIP_R423)
2881 trbs_ff = memtrbs_r4xx[data];
2882 else
2883 trbs_ff = memtrbs[data];
2884 tcas_ff.full += trbs_ff.full;
2885 }
2886
2887 sclk_eff_ff.full = sclk_ff.full;
2888
2889 if (rdev->flags & RADEON_IS_AGP) {
2890 fixed20_12 agpmode_ff;
2891 agpmode_ff.full = dfixed_const(radeon_agpmode);
2892 temp_ff.full = dfixed_const_666(16);
2893 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
2894 }
2895 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2896
2897 if (ASIC_IS_R300(rdev)) {
2898 sclk_delay_ff.full = dfixed_const(250);
2899 } else {
2900 if ((rdev->family == CHIP_RV100) ||
2901 rdev->flags & RADEON_IS_IGP) {
2902 if (rdev->mc.vram_is_ddr)
2903 sclk_delay_ff.full = dfixed_const(41);
2904 else
2905 sclk_delay_ff.full = dfixed_const(33);
2906 } else {
2907 if (rdev->mc.vram_width == 128)
2908 sclk_delay_ff.full = dfixed_const(57);
2909 else
2910 sclk_delay_ff.full = dfixed_const(41);
2911 }
2912 }
2913
2914 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
2915
2916 if (rdev->mc.vram_is_ddr) {
2917 if (rdev->mc.vram_width == 32) {
2918 k1.full = dfixed_const(40);
2919 c = 3;
2920 } else {
2921 k1.full = dfixed_const(20);
2922 c = 1;
2923 }
2924 } else {
2925 k1.full = dfixed_const(40);
2926 c = 3;
2927 }
2928
2929 temp_ff.full = dfixed_const(2);
2930 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
2931 temp_ff.full = dfixed_const(c);
2932 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
2933 temp_ff.full = dfixed_const(4);
2934 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
2935 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
2936 mc_latency_mclk.full += k1.full;
2937
2938 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
2939 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
2940
2941 /*
2942 HW cursor time assuming worst case of full size colour cursor.
2943 */
2944 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2945 temp_ff.full += trcd_ff.full;
2946 if (temp_ff.full < tras_ff.full)
2947 temp_ff.full = tras_ff.full;
2948 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
2949
2950 temp_ff.full = dfixed_const(cur_size);
2951 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
2952 /*
2953 Find the total latency for the display data.
2954 */
2955 disp_latency_overhead.full = dfixed_const(8);
2956 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
2957 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2958 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2959
2960 if (mc_latency_mclk.full > mc_latency_sclk.full)
2961 disp_latency.full = mc_latency_mclk.full;
2962 else
2963 disp_latency.full = mc_latency_sclk.full;
2964
2965 /* setup Max GRPH_STOP_REQ default value */
2966 if (ASIC_IS_RV100(rdev))
2967 max_stop_req = 0x5c;
2968 else
2969 max_stop_req = 0x7c;
2970
2971 if (mode1) {
2972 /* CRTC1
2973 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2974 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2975 */
2976 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2977
2978 if (stop_req > max_stop_req)
2979 stop_req = max_stop_req;
2980
2981 /*
2982 Find the drain rate of the display buffer.
2983 */
2984 temp_ff.full = dfixed_const((16/pixel_bytes1));
2985 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
2986
2987 /*
2988 Find the critical point of the display buffer.
2989 */
2990 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
2991 crit_point_ff.full += dfixed_const_half(0);
2992
2993 critical_point = dfixed_trunc(crit_point_ff);
2994
2995 if (rdev->disp_priority == 2) {
2996 critical_point = 0;
2997 }
2998
2999 /*
3000 The critical point should never be above max_stop_req-4. Setting
3001 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3002 */
3003 if (max_stop_req - critical_point < 4)
3004 critical_point = 0;
3005
3006 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3007 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3008 critical_point = 0x10;
3009 }
3010
3011 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3012 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3013 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3014 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3015 if ((rdev->family == CHIP_R350) &&
3016 (stop_req > 0x15)) {
3017 stop_req -= 0x10;
3018 }
3019 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3020 temp |= RADEON_GRPH_BUFFER_SIZE;
3021 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3022 RADEON_GRPH_CRITICAL_AT_SOF |
3023 RADEON_GRPH_STOP_CNTL);
3024 /*
3025 Write the result into the register.
3026 */
3027 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3028 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3029
3030#if 0
3031 if ((rdev->family == CHIP_RS400) ||
3032 (rdev->family == CHIP_RS480)) {
3033 /* attempt to program RS400 disp regs correctly ??? */
3034 temp = RREG32(RS400_DISP1_REG_CNTL);
3035 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3036 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3037 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3038 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3039 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3040 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3041 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3042 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3043 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3044 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3045 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3046 }
3047#endif
3048
3049 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3050 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3051 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3052 }
3053
3054 if (mode2) {
3055 u32 grph2_cntl;
3056 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3057
3058 if (stop_req > max_stop_req)
3059 stop_req = max_stop_req;
3060
3061 /*
3062 Find the drain rate of the display buffer.
3063 */
3064 temp_ff.full = dfixed_const((16/pixel_bytes2));
3065 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3066
3067 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3068 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3069 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3070 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3071 if ((rdev->family == CHIP_R350) &&
3072 (stop_req > 0x15)) {
3073 stop_req -= 0x10;
3074 }
3075 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3076 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3077 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3078 RADEON_GRPH_CRITICAL_AT_SOF |
3079 RADEON_GRPH_STOP_CNTL);
3080
3081 if ((rdev->family == CHIP_RS100) ||
3082 (rdev->family == CHIP_RS200))
3083 critical_point2 = 0;
3084 else {
3085 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3086 temp_ff.full = dfixed_const(temp);
3087 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3088 if (sclk_ff.full < temp_ff.full)
3089 temp_ff.full = sclk_ff.full;
3090
3091 read_return_rate.full = temp_ff.full;
3092
3093 if (mode1) {
3094 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3095 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3096 } else {
3097 time_disp1_drop_priority.full = 0;
3098 }
3099 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3100 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3101 crit_point_ff.full += dfixed_const_half(0);
3102
3103 critical_point2 = dfixed_trunc(crit_point_ff);
3104
3105 if (rdev->disp_priority == 2) {
3106 critical_point2 = 0;
3107 }
3108
3109 if (max_stop_req - critical_point2 < 4)
3110 critical_point2 = 0;
3111
3112 }
3113
3114 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3115 /* some R300 cards have problem with this set to 0 */
3116 critical_point2 = 0x10;
3117 }
3118
3119 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3120 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3121
3122 if ((rdev->family == CHIP_RS400) ||
3123 (rdev->family == CHIP_RS480)) {
3124#if 0
3125 /* attempt to program RS400 disp2 regs correctly ??? */
3126 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3127 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3128 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3129 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3130 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3131 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3132 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3133 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3134 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3135 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3136 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3137 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3138#endif
3139 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3140 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3141 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3142 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3143 }
3144
3145 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3146 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3147 }
3148}
3149
3150static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3151{
3152 DRM_ERROR("pitch %d\n", t->pitch);
3153 DRM_ERROR("use_pitch %d\n", t->use_pitch);
3154 DRM_ERROR("width %d\n", t->width);
3155 DRM_ERROR("width_11 %d\n", t->width_11);
3156 DRM_ERROR("height %d\n", t->height);
3157 DRM_ERROR("height_11 %d\n", t->height_11);
3158 DRM_ERROR("num levels %d\n", t->num_levels);
3159 DRM_ERROR("depth %d\n", t->txdepth);
3160 DRM_ERROR("bpp %d\n", t->cpp);
3161 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
3162 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
3163 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3164 DRM_ERROR("compress format %d\n", t->compress_format);
3165}
3166
3167static int r100_track_compress_size(int compress_format, int w, int h)
3168{
3169 int block_width, block_height, block_bytes;
3170 int wblocks, hblocks;
3171 int min_wblocks;
3172 int sz;
3173
3174 block_width = 4;
3175 block_height = 4;
3176
3177 switch (compress_format) {
3178 case R100_TRACK_COMP_DXT1:
3179 block_bytes = 8;
3180 min_wblocks = 4;
3181 break;
3182 default:
3183 case R100_TRACK_COMP_DXT35:
3184 block_bytes = 16;
3185 min_wblocks = 2;
3186 break;
3187 }
3188
3189 hblocks = (h + block_height - 1) / block_height;
3190 wblocks = (w + block_width - 1) / block_width;
3191 if (wblocks < min_wblocks)
3192 wblocks = min_wblocks;
3193 sz = wblocks * hblocks * block_bytes;
3194 return sz;
3195}
3196
3197static int r100_cs_track_cube(struct radeon_device *rdev,
3198 struct r100_cs_track *track, unsigned idx)
3199{
3200 unsigned face, w, h;
3201 struct radeon_bo *cube_robj;
3202 unsigned long size;
3203 unsigned compress_format = track->textures[idx].compress_format;
3204
3205 for (face = 0; face < 5; face++) {
3206 cube_robj = track->textures[idx].cube_info[face].robj;
3207 w = track->textures[idx].cube_info[face].width;
3208 h = track->textures[idx].cube_info[face].height;
3209
3210 if (compress_format) {
3211 size = r100_track_compress_size(compress_format, w, h);
3212 } else
3213 size = w * h;
3214 size *= track->textures[idx].cpp;
3215
3216 size += track->textures[idx].cube_info[face].offset;
3217
3218 if (size > radeon_bo_size(cube_robj)) {
3219 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3220 size, radeon_bo_size(cube_robj));
3221 r100_cs_track_texture_print(&track->textures[idx]);
3222 return -1;
3223 }
3224 }
3225 return 0;
3226}
3227
3228static int r100_cs_track_texture_check(struct radeon_device *rdev,
3229 struct r100_cs_track *track)
3230{
3231 struct radeon_bo *robj;
3232 unsigned long size;
3233 unsigned u, i, w, h, d;
3234 int ret;
3235
3236 for (u = 0; u < track->num_texture; u++) {
3237 if (!track->textures[u].enabled)
3238 continue;
3239 if (track->textures[u].lookup_disable)
3240 continue;
3241 robj = track->textures[u].robj;
3242 if (robj == NULL) {
3243 DRM_ERROR("No texture bound to unit %u\n", u);
3244 return -EINVAL;
3245 }
3246 size = 0;
3247 for (i = 0; i <= track->textures[u].num_levels; i++) {
3248 if (track->textures[u].use_pitch) {
3249 if (rdev->family < CHIP_R300)
3250 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3251 else
3252 w = track->textures[u].pitch / (1 << i);
3253 } else {
3254 w = track->textures[u].width;
3255 if (rdev->family >= CHIP_RV515)
3256 w |= track->textures[u].width_11;
3257 w = w / (1 << i);
3258 if (track->textures[u].roundup_w)
3259 w = roundup_pow_of_two(w);
3260 }
3261 h = track->textures[u].height;
3262 if (rdev->family >= CHIP_RV515)
3263 h |= track->textures[u].height_11;
3264 h = h / (1 << i);
3265 if (track->textures[u].roundup_h)
3266 h = roundup_pow_of_two(h);
3267 if (track->textures[u].tex_coord_type == 1) {
3268 d = (1 << track->textures[u].txdepth) / (1 << i);
3269 if (!d)
3270 d = 1;
3271 } else {
3272 d = 1;
3273 }
3274 if (track->textures[u].compress_format) {
3275
3276 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3277 /* compressed textures are block based */
3278 } else
3279 size += w * h * d;
3280 }
3281 size *= track->textures[u].cpp;
3282
3283 switch (track->textures[u].tex_coord_type) {
3284 case 0:
3285 case 1:
3286 break;
3287 case 2:
3288 if (track->separate_cube) {
3289 ret = r100_cs_track_cube(rdev, track, u);
3290 if (ret)
3291 return ret;
3292 } else
3293 size *= 6;
3294 break;
3295 default:
3296 DRM_ERROR("Invalid texture coordinate type %u for unit "
3297 "%u\n", track->textures[u].tex_coord_type, u);
3298 return -EINVAL;
3299 }
3300 if (size > radeon_bo_size(robj)) {
3301 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3302 "%lu\n", u, size, radeon_bo_size(robj));
3303 r100_cs_track_texture_print(&track->textures[u]);
3304 return -EINVAL;
3305 }
3306 }
3307 return 0;
3308}
3309
3310int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3311{
3312 unsigned i;
3313 unsigned long size;
3314 unsigned prim_walk;
3315 unsigned nverts;
3316 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
3317
3318 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
3319 !track->blend_read_enable)
3320 num_cb = 0;
3321
3322 for (i = 0; i < num_cb; i++) {
3323 if (track->cb[i].robj == NULL) {
3324 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3325 return -EINVAL;
3326 }
3327 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3328 size += track->cb[i].offset;
3329 if (size > radeon_bo_size(track->cb[i].robj)) {
3330 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3331 "(need %lu have %lu) !\n", i, size,
3332 radeon_bo_size(track->cb[i].robj));
3333 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3334 i, track->cb[i].pitch, track->cb[i].cpp,
3335 track->cb[i].offset, track->maxy);
3336 return -EINVAL;
3337 }
3338 }
3339 track->cb_dirty = false;
3340
3341 if (track->zb_dirty && track->z_enabled) {
3342 if (track->zb.robj == NULL) {
3343 DRM_ERROR("[drm] No buffer for z buffer !\n");
3344 return -EINVAL;
3345 }
3346 size = track->zb.pitch * track->zb.cpp * track->maxy;
3347 size += track->zb.offset;
3348 if (size > radeon_bo_size(track->zb.robj)) {
3349 DRM_ERROR("[drm] Buffer too small for z buffer "
3350 "(need %lu have %lu) !\n", size,
3351 radeon_bo_size(track->zb.robj));
3352 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3353 track->zb.pitch, track->zb.cpp,
3354 track->zb.offset, track->maxy);
3355 return -EINVAL;
3356 }
3357 }
3358 track->zb_dirty = false;
3359
3360 if (track->aa_dirty && track->aaresolve) {
3361 if (track->aa.robj == NULL) {
3362 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3363 return -EINVAL;
3364 }
3365 /* I believe the format comes from colorbuffer0. */
3366 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3367 size += track->aa.offset;
3368 if (size > radeon_bo_size(track->aa.robj)) {
3369 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3370 "(need %lu have %lu) !\n", i, size,
3371 radeon_bo_size(track->aa.robj));
3372 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3373 i, track->aa.pitch, track->cb[0].cpp,
3374 track->aa.offset, track->maxy);
3375 return -EINVAL;
3376 }
3377 }
3378 track->aa_dirty = false;
3379
3380 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3381 if (track->vap_vf_cntl & (1 << 14)) {
3382 nverts = track->vap_alt_nverts;
3383 } else {
3384 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3385 }
3386 switch (prim_walk) {
3387 case 1:
3388 for (i = 0; i < track->num_arrays; i++) {
3389 size = track->arrays[i].esize * track->max_indx * 4;
3390 if (track->arrays[i].robj == NULL) {
3391 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3392 "bound\n", prim_walk, i);
3393 return -EINVAL;
3394 }
3395 if (size > radeon_bo_size(track->arrays[i].robj)) {
3396 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3397 "need %lu dwords have %lu dwords\n",
3398 prim_walk, i, size >> 2,
3399 radeon_bo_size(track->arrays[i].robj)
3400 >> 2);
3401 DRM_ERROR("Max indices %u\n", track->max_indx);
3402 return -EINVAL;
3403 }
3404 }
3405 break;
3406 case 2:
3407 for (i = 0; i < track->num_arrays; i++) {
3408 size = track->arrays[i].esize * (nverts - 1) * 4;
3409 if (track->arrays[i].robj == NULL) {
3410 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3411 "bound\n", prim_walk, i);
3412 return -EINVAL;
3413 }
3414 if (size > radeon_bo_size(track->arrays[i].robj)) {
3415 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3416 "need %lu dwords have %lu dwords\n",
3417 prim_walk, i, size >> 2,
3418 radeon_bo_size(track->arrays[i].robj)
3419 >> 2);
3420 return -EINVAL;
3421 }
3422 }
3423 break;
3424 case 3:
3425 size = track->vtx_size * nverts;
3426 if (size != track->immd_dwords) {
3427 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3428 track->immd_dwords, size);
3429 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3430 nverts, track->vtx_size);
3431 return -EINVAL;
3432 }
3433 break;
3434 default:
3435 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3436 prim_walk);
3437 return -EINVAL;
3438 }
3439
3440 if (track->tex_dirty) {
3441 track->tex_dirty = false;
3442 return r100_cs_track_texture_check(rdev, track);
3443 }
3444 return 0;
3445}
3446
3447void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3448{
3449 unsigned i, face;
3450
3451 track->cb_dirty = true;
3452 track->zb_dirty = true;
3453 track->tex_dirty = true;
3454 track->aa_dirty = true;
3455
3456 if (rdev->family < CHIP_R300) {
3457 track->num_cb = 1;
3458 if (rdev->family <= CHIP_RS200)
3459 track->num_texture = 3;
3460 else
3461 track->num_texture = 6;
3462 track->maxy = 2048;
3463 track->separate_cube = 1;
3464 } else {
3465 track->num_cb = 4;
3466 track->num_texture = 16;
3467 track->maxy = 4096;
3468 track->separate_cube = 0;
3469 track->aaresolve = false;
3470 track->aa.robj = NULL;
3471 }
3472
3473 for (i = 0; i < track->num_cb; i++) {
3474 track->cb[i].robj = NULL;
3475 track->cb[i].pitch = 8192;
3476 track->cb[i].cpp = 16;
3477 track->cb[i].offset = 0;
3478 }
3479 track->z_enabled = true;
3480 track->zb.robj = NULL;
3481 track->zb.pitch = 8192;
3482 track->zb.cpp = 4;
3483 track->zb.offset = 0;
3484 track->vtx_size = 0x7F;
3485 track->immd_dwords = 0xFFFFFFFFUL;
3486 track->num_arrays = 11;
3487 track->max_indx = 0x00FFFFFFUL;
3488 for (i = 0; i < track->num_arrays; i++) {
3489 track->arrays[i].robj = NULL;
3490 track->arrays[i].esize = 0x7F;
3491 }
3492 for (i = 0; i < track->num_texture; i++) {
3493 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3494 track->textures[i].pitch = 16536;
3495 track->textures[i].width = 16536;
3496 track->textures[i].height = 16536;
3497 track->textures[i].width_11 = 1 << 11;
3498 track->textures[i].height_11 = 1 << 11;
3499 track->textures[i].num_levels = 12;
3500 if (rdev->family <= CHIP_RS200) {
3501 track->textures[i].tex_coord_type = 0;
3502 track->textures[i].txdepth = 0;
3503 } else {
3504 track->textures[i].txdepth = 16;
3505 track->textures[i].tex_coord_type = 1;
3506 }
3507 track->textures[i].cpp = 64;
3508 track->textures[i].robj = NULL;
3509 /* CS IB emission code makes sure texture unit are disabled */
3510 track->textures[i].enabled = false;
3511 track->textures[i].lookup_disable = false;
3512 track->textures[i].roundup_w = true;
3513 track->textures[i].roundup_h = true;
3514 if (track->separate_cube)
3515 for (face = 0; face < 5; face++) {
3516 track->textures[i].cube_info[face].robj = NULL;
3517 track->textures[i].cube_info[face].width = 16536;
3518 track->textures[i].cube_info[face].height = 16536;
3519 track->textures[i].cube_info[face].offset = 0;
3520 }
3521 }
3522}
3523
3524int r100_ring_test(struct radeon_device *rdev)
3525{
3526 uint32_t scratch;
3527 uint32_t tmp = 0;
3528 unsigned i;
3529 int r;
3530
3531 r = radeon_scratch_get(rdev, &scratch);
3532 if (r) {
3533 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3534 return r;
3535 }
3536 WREG32(scratch, 0xCAFEDEAD);
3537 r = radeon_ring_lock(rdev, 2);
3538 if (r) {
3539 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3540 radeon_scratch_free(rdev, scratch);
3541 return r;
3542 }
3543 radeon_ring_write(rdev, PACKET0(scratch, 0));
3544 radeon_ring_write(rdev, 0xDEADBEEF);
3545 radeon_ring_unlock_commit(rdev);
3546 for (i = 0; i < rdev->usec_timeout; i++) {
3547 tmp = RREG32(scratch);
3548 if (tmp == 0xDEADBEEF) {
3549 break;
3550 }
3551 DRM_UDELAY(1);
3552 }
3553 if (i < rdev->usec_timeout) {
3554 DRM_INFO("ring test succeeded in %d usecs\n", i);
3555 } else {
3556 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3557 scratch, tmp);
3558 r = -EINVAL;
3559 }
3560 radeon_scratch_free(rdev, scratch);
3561 return r;
3562}
3563
3564void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3565{
3566 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3567 radeon_ring_write(rdev, ib->gpu_addr);
3568 radeon_ring_write(rdev, ib->length_dw);
3569}
3570
3571int r100_ib_test(struct radeon_device *rdev)
3572{
3573 struct radeon_ib *ib;
3574 uint32_t scratch;
3575 uint32_t tmp = 0;
3576 unsigned i;
3577 int r;
3578
3579 r = radeon_scratch_get(rdev, &scratch);
3580 if (r) {
3581 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3582 return r;
3583 }
3584 WREG32(scratch, 0xCAFEDEAD);
3585 r = radeon_ib_get(rdev, &ib);
3586 if (r) {
3587 return r;
3588 }
3589 ib->ptr[0] = PACKET0(scratch, 0);
3590 ib->ptr[1] = 0xDEADBEEF;
3591 ib->ptr[2] = PACKET2(0);
3592 ib->ptr[3] = PACKET2(0);
3593 ib->ptr[4] = PACKET2(0);
3594 ib->ptr[5] = PACKET2(0);
3595 ib->ptr[6] = PACKET2(0);
3596 ib->ptr[7] = PACKET2(0);
3597 ib->length_dw = 8;
3598 r = radeon_ib_schedule(rdev, ib);
3599 if (r) {
3600 radeon_scratch_free(rdev, scratch);
3601 radeon_ib_free(rdev, &ib);
3602 return r;
3603 }
3604 r = radeon_fence_wait(ib->fence, false);
3605 if (r) {
3606 return r;
3607 }
3608 for (i = 0; i < rdev->usec_timeout; i++) {
3609 tmp = RREG32(scratch);
3610 if (tmp == 0xDEADBEEF) {
3611 break;
3612 }
3613 DRM_UDELAY(1);
3614 }
3615 if (i < rdev->usec_timeout) {
3616 DRM_INFO("ib test succeeded in %u usecs\n", i);
3617 } else {
3618 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3619 scratch, tmp);
3620 r = -EINVAL;
3621 }
3622 radeon_scratch_free(rdev, scratch);
3623 radeon_ib_free(rdev, &ib);
3624 return r;
3625}
3626
3627void r100_ib_fini(struct radeon_device *rdev)
3628{
3629 radeon_ib_pool_fini(rdev);
3630}
3631
3632int r100_ib_init(struct radeon_device *rdev)
3633{
3634 int r;
3635
3636 r = radeon_ib_pool_init(rdev);
3637 if (r) {
3638 dev_err(rdev->dev, "failed initializing IB pool (%d).\n", r);
3639 r100_ib_fini(rdev);
3640 return r;
3641 }
3642 r = r100_ib_test(rdev);
3643 if (r) {
3644 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
3645 r100_ib_fini(rdev);
3646 return r;
3647 }
3648 return 0;
3649}
3650
3651void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3652{
3653 /* Shutdown CP we shouldn't need to do that but better be safe than
3654 * sorry
3655 */
3656 rdev->cp.ready = false;
3657 WREG32(R_000740_CP_CSQ_CNTL, 0);
3658
3659 /* Save few CRTC registers */
3660 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3661 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3662 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3663 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3664 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3665 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3666 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3667 }
3668
3669 /* Disable VGA aperture access */
3670 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3671 /* Disable cursor, overlay, crtc */
3672 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3673 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3674 S_000054_CRTC_DISPLAY_DIS(1));
3675 WREG32(R_000050_CRTC_GEN_CNTL,
3676 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3677 S_000050_CRTC_DISP_REQ_EN_B(1));
3678 WREG32(R_000420_OV0_SCALE_CNTL,
3679 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3680 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3681 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3682 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3683 S_000360_CUR2_LOCK(1));
3684 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3685 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3686 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3687 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3688 WREG32(R_000360_CUR2_OFFSET,
3689 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3690 }
3691}
3692
3693void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3694{
3695 /* Update base address for crtc */
3696 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3697 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3698 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3699 }
3700 /* Restore CRTC registers */
3701 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3702 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3703 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3704 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3705 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3706 }
3707}
3708
3709void r100_vga_render_disable(struct radeon_device *rdev)
3710{
3711 u32 tmp;
3712
3713 tmp = RREG8(R_0003C2_GENMO_WT);
3714 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3715}
3716
3717static void r100_debugfs(struct radeon_device *rdev)
3718{
3719 int r;
3720
3721 r = r100_debugfs_mc_info_init(rdev);
3722 if (r)
3723 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3724}
3725
3726static void r100_mc_program(struct radeon_device *rdev)
3727{
3728 struct r100_mc_save save;
3729
3730 /* Stops all mc clients */
3731 r100_mc_stop(rdev, &save);
3732 if (rdev->flags & RADEON_IS_AGP) {
3733 WREG32(R_00014C_MC_AGP_LOCATION,
3734 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3735 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3736 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3737 if (rdev->family > CHIP_RV200)
3738 WREG32(R_00015C_AGP_BASE_2,
3739 upper_32_bits(rdev->mc.agp_base) & 0xff);
3740 } else {
3741 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3742 WREG32(R_000170_AGP_BASE, 0);
3743 if (rdev->family > CHIP_RV200)
3744 WREG32(R_00015C_AGP_BASE_2, 0);
3745 }
3746 /* Wait for mc idle */
3747 if (r100_mc_wait_for_idle(rdev))
3748 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3749 /* Program MC, should be a 32bits limited address space */
3750 WREG32(R_000148_MC_FB_LOCATION,
3751 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3752 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3753 r100_mc_resume(rdev, &save);
3754}
3755
3756void r100_clock_startup(struct radeon_device *rdev)
3757{
3758 u32 tmp;
3759
3760 if (radeon_dynclks != -1 && radeon_dynclks)
3761 radeon_legacy_set_clock_gating(rdev, 1);
3762 /* We need to force on some of the block */
3763 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3764 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3765 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3766 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3767 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3768}
3769
3770static int r100_startup(struct radeon_device *rdev)
3771{
3772 int r;
3773
3774 /* set common regs */
3775 r100_set_common_regs(rdev);
3776 /* program mc */
3777 r100_mc_program(rdev);
3778 /* Resume clock */
3779 r100_clock_startup(rdev);
3780 /* Initialize GART (initialize after TTM so we can allocate
3781 * memory through TTM but finalize after TTM) */
3782 r100_enable_bm(rdev);
3783 if (rdev->flags & RADEON_IS_PCI) {
3784 r = r100_pci_gart_enable(rdev);
3785 if (r)
3786 return r;
3787 }
3788
3789 /* allocate wb buffer */
3790 r = radeon_wb_init(rdev);
3791 if (r)
3792 return r;
3793
3794 /* Enable IRQ */
3795 r100_irq_set(rdev);
3796 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3797 /* 1M ring buffer */
3798 r = r100_cp_init(rdev, 1024 * 1024);
3799 if (r) {
3800 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3801 return r;
3802 }
3803 r = r100_ib_init(rdev);
3804 if (r) {
3805 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
3806 return r;
3807 }
3808 return 0;
3809}
3810
3811int r100_resume(struct radeon_device *rdev)
3812{
3813 /* Make sur GART are not working */
3814 if (rdev->flags & RADEON_IS_PCI)
3815 r100_pci_gart_disable(rdev);
3816 /* Resume clock before doing reset */
3817 r100_clock_startup(rdev);
3818 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3819 if (radeon_asic_reset(rdev)) {
3820 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3821 RREG32(R_000E40_RBBM_STATUS),
3822 RREG32(R_0007C0_CP_STAT));
3823 }
3824 /* post */
3825 radeon_combios_asic_init(rdev->ddev);
3826 /* Resume clock after posting */
3827 r100_clock_startup(rdev);
3828 /* Initialize surface registers */
3829 radeon_surface_init(rdev);
3830 return r100_startup(rdev);
3831}
3832
3833int r100_suspend(struct radeon_device *rdev)
3834{
3835 r100_cp_disable(rdev);
3836 radeon_wb_disable(rdev);
3837 r100_irq_disable(rdev);
3838 if (rdev->flags & RADEON_IS_PCI)
3839 r100_pci_gart_disable(rdev);
3840 return 0;
3841}
3842
3843void r100_fini(struct radeon_device *rdev)
3844{
3845 r100_cp_fini(rdev);
3846 radeon_wb_fini(rdev);
3847 r100_ib_fini(rdev);
3848 radeon_gem_fini(rdev);
3849 if (rdev->flags & RADEON_IS_PCI)
3850 r100_pci_gart_fini(rdev);
3851 radeon_agp_fini(rdev);
3852 radeon_irq_kms_fini(rdev);
3853 radeon_fence_driver_fini(rdev);
3854 radeon_bo_fini(rdev);
3855 radeon_atombios_fini(rdev);
3856 kfree(rdev->bios);
3857 rdev->bios = NULL;
3858}
3859
3860/*
3861 * Due to how kexec works, it can leave the hw fully initialised when it
3862 * boots the new kernel. However doing our init sequence with the CP and
3863 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3864 * do some quick sanity checks and restore sane values to avoid this
3865 * problem.
3866 */
3867void r100_restore_sanity(struct radeon_device *rdev)
3868{
3869 u32 tmp;
3870
3871 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3872 if (tmp) {
3873 WREG32(RADEON_CP_CSQ_CNTL, 0);
3874 }
3875 tmp = RREG32(RADEON_CP_RB_CNTL);
3876 if (tmp) {
3877 WREG32(RADEON_CP_RB_CNTL, 0);
3878 }
3879 tmp = RREG32(RADEON_SCRATCH_UMSK);
3880 if (tmp) {
3881 WREG32(RADEON_SCRATCH_UMSK, 0);
3882 }
3883}
3884
3885int r100_init(struct radeon_device *rdev)
3886{
3887 int r;
3888
3889 /* Register debugfs file specific to this group of asics */
3890 r100_debugfs(rdev);
3891 /* Disable VGA */
3892 r100_vga_render_disable(rdev);
3893 /* Initialize scratch registers */
3894 radeon_scratch_init(rdev);
3895 /* Initialize surface registers */
3896 radeon_surface_init(rdev);
3897 /* sanity check some register to avoid hangs like after kexec */
3898 r100_restore_sanity(rdev);
3899 /* TODO: disable VGA need to use VGA request */
3900 /* BIOS*/
3901 if (!radeon_get_bios(rdev)) {
3902 if (ASIC_IS_AVIVO(rdev))
3903 return -EINVAL;
3904 }
3905 if (rdev->is_atom_bios) {
3906 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3907 return -EINVAL;
3908 } else {
3909 r = radeon_combios_init(rdev);
3910 if (r)
3911 return r;
3912 }
3913 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3914 if (radeon_asic_reset(rdev)) {
3915 dev_warn(rdev->dev,
3916 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3917 RREG32(R_000E40_RBBM_STATUS),
3918 RREG32(R_0007C0_CP_STAT));
3919 }
3920 /* check if cards are posted or not */
3921 if (radeon_boot_test_post_card(rdev) == false)
3922 return -EINVAL;
3923 /* Set asic errata */
3924 r100_errata(rdev);
3925 /* Initialize clocks */
3926 radeon_get_clock_info(rdev->ddev);
3927 /* initialize AGP */
3928 if (rdev->flags & RADEON_IS_AGP) {
3929 r = radeon_agp_init(rdev);
3930 if (r) {
3931 radeon_agp_disable(rdev);
3932 }
3933 }
3934 /* initialize VRAM */
3935 r100_mc_init(rdev);
3936 /* Fence driver */
3937 r = radeon_fence_driver_init(rdev);
3938 if (r)
3939 return r;
3940 r = radeon_irq_kms_init(rdev);
3941 if (r)
3942 return r;
3943 /* Memory manager */
3944 r = radeon_bo_init(rdev);
3945 if (r)
3946 return r;
3947 if (rdev->flags & RADEON_IS_PCI) {
3948 r = r100_pci_gart_init(rdev);
3949 if (r)
3950 return r;
3951 }
3952 r100_set_safe_registers(rdev);
3953 rdev->accel_working = true;
3954 r = r100_startup(rdev);
3955 if (r) {
3956 /* Somethings want wront with the accel init stop accel */
3957 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3958 r100_cp_fini(rdev);
3959 radeon_wb_fini(rdev);
3960 r100_ib_fini(rdev);
3961 radeon_irq_kms_fini(rdev);
3962 if (rdev->flags & RADEON_IS_PCI)
3963 r100_pci_gart_fini(rdev);
3964 rdev->accel_working = false;
3965 }
3966 return 0;
3967}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/firmware.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/seq_file.h>
33#include <linux/slab.h>
34
35#include <drm/drm_device.h>
36#include <drm/drm_file.h>
37#include <drm/drm_fourcc.h>
38#include <drm/drm_framebuffer.h>
39#include <drm/drm_vblank.h>
40#include <drm/radeon_drm.h>
41
42#include "atom.h"
43#include "r100_reg_safe.h"
44#include "r100d.h"
45#include "radeon.h"
46#include "radeon_asic.h"
47#include "radeon_reg.h"
48#include "rn50_reg_safe.h"
49#include "rs100d.h"
50#include "rv200d.h"
51#include "rv250d.h"
52
53/* Firmware Names */
54#define FIRMWARE_R100 "radeon/R100_cp.bin"
55#define FIRMWARE_R200 "radeon/R200_cp.bin"
56#define FIRMWARE_R300 "radeon/R300_cp.bin"
57#define FIRMWARE_R420 "radeon/R420_cp.bin"
58#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
59#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
60#define FIRMWARE_R520 "radeon/R520_cp.bin"
61
62MODULE_FIRMWARE(FIRMWARE_R100);
63MODULE_FIRMWARE(FIRMWARE_R200);
64MODULE_FIRMWARE(FIRMWARE_R300);
65MODULE_FIRMWARE(FIRMWARE_R420);
66MODULE_FIRMWARE(FIRMWARE_RS690);
67MODULE_FIRMWARE(FIRMWARE_RS600);
68MODULE_FIRMWARE(FIRMWARE_R520);
69
70#include "r100_track.h"
71
72/* This files gather functions specifics to:
73 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
74 * and others in some cases.
75 */
76
77static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
78{
79 if (crtc == 0) {
80 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
81 return true;
82 else
83 return false;
84 } else {
85 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
86 return true;
87 else
88 return false;
89 }
90}
91
92static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
93{
94 u32 vline1, vline2;
95
96 if (crtc == 0) {
97 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
98 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
99 } else {
100 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
101 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
102 }
103 if (vline1 != vline2)
104 return true;
105 else
106 return false;
107}
108
109/**
110 * r100_wait_for_vblank - vblank wait asic callback.
111 *
112 * @rdev: radeon_device pointer
113 * @crtc: crtc to wait for vblank on
114 *
115 * Wait for vblank on the requested crtc (r1xx-r4xx).
116 */
117void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
118{
119 unsigned i = 0;
120
121 if (crtc >= rdev->num_crtc)
122 return;
123
124 if (crtc == 0) {
125 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
126 return;
127 } else {
128 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
129 return;
130 }
131
132 /* depending on when we hit vblank, we may be close to active; if so,
133 * wait for another frame.
134 */
135 while (r100_is_in_vblank(rdev, crtc)) {
136 if (i++ % 100 == 0) {
137 if (!r100_is_counter_moving(rdev, crtc))
138 break;
139 }
140 }
141
142 while (!r100_is_in_vblank(rdev, crtc)) {
143 if (i++ % 100 == 0) {
144 if (!r100_is_counter_moving(rdev, crtc))
145 break;
146 }
147 }
148}
149
150/**
151 * r100_page_flip - pageflip callback.
152 *
153 * @rdev: radeon_device pointer
154 * @crtc_id: crtc to cleanup pageflip on
155 * @crtc_base: new address of the crtc (GPU MC address)
156 * @async: asynchronous flip
157 *
158 * Does the actual pageflip (r1xx-r4xx).
159 * During vblank we take the crtc lock and wait for the update_pending
160 * bit to go high, when it does, we release the lock, and allow the
161 * double buffered update to take place.
162 */
163void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
164{
165 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
166 uint32_t crtc_pitch, pitch_pixels;
167 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;
168 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
169 int i;
170
171 /* Lock the graphics update lock */
172 /* update the scanout addresses */
173 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
174
175 /* update pitch */
176 pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
177 crtc_pitch = DIV_ROUND_UP(pitch_pixels * fb->format->cpp[0] * 8,
178 fb->format->cpp[0] * 8 * 8);
179 crtc_pitch |= crtc_pitch << 16;
180 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
181
182 /* Wait for update_pending to go high. */
183 for (i = 0; i < rdev->usec_timeout; i++) {
184 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
185 break;
186 udelay(1);
187 }
188 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
189
190 /* Unlock the lock, so double-buffering can take place inside vblank */
191 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
192 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
193
194}
195
196/**
197 * r100_page_flip_pending - check if page flip is still pending
198 *
199 * @rdev: radeon_device pointer
200 * @crtc_id: crtc to check
201 *
202 * Check if the last pagefilp is still pending (r1xx-r4xx).
203 * Returns the current update pending status.
204 */
205bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
206{
207 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
208
209 /* Return current update_pending status: */
210 return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
211 RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET);
212}
213
214/**
215 * r100_pm_get_dynpm_state - look up dynpm power state callback.
216 *
217 * @rdev: radeon_device pointer
218 *
219 * Look up the optimal power state based on the
220 * current state of the GPU (r1xx-r5xx).
221 * Used for dynpm only.
222 */
223void r100_pm_get_dynpm_state(struct radeon_device *rdev)
224{
225 int i;
226 rdev->pm.dynpm_can_upclock = true;
227 rdev->pm.dynpm_can_downclock = true;
228
229 switch (rdev->pm.dynpm_planned_action) {
230 case DYNPM_ACTION_MINIMUM:
231 rdev->pm.requested_power_state_index = 0;
232 rdev->pm.dynpm_can_downclock = false;
233 break;
234 case DYNPM_ACTION_DOWNCLOCK:
235 if (rdev->pm.current_power_state_index == 0) {
236 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
237 rdev->pm.dynpm_can_downclock = false;
238 } else {
239 if (rdev->pm.active_crtc_count > 1) {
240 for (i = 0; i < rdev->pm.num_power_states; i++) {
241 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
242 continue;
243 else if (i >= rdev->pm.current_power_state_index) {
244 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
245 break;
246 } else {
247 rdev->pm.requested_power_state_index = i;
248 break;
249 }
250 }
251 } else
252 rdev->pm.requested_power_state_index =
253 rdev->pm.current_power_state_index - 1;
254 }
255 /* don't use the power state if crtcs are active and no display flag is set */
256 if ((rdev->pm.active_crtc_count > 0) &&
257 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
258 RADEON_PM_MODE_NO_DISPLAY)) {
259 rdev->pm.requested_power_state_index++;
260 }
261 break;
262 case DYNPM_ACTION_UPCLOCK:
263 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
264 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
265 rdev->pm.dynpm_can_upclock = false;
266 } else {
267 if (rdev->pm.active_crtc_count > 1) {
268 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
269 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
270 continue;
271 else if (i <= rdev->pm.current_power_state_index) {
272 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
273 break;
274 } else {
275 rdev->pm.requested_power_state_index = i;
276 break;
277 }
278 }
279 } else
280 rdev->pm.requested_power_state_index =
281 rdev->pm.current_power_state_index + 1;
282 }
283 break;
284 case DYNPM_ACTION_DEFAULT:
285 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
286 rdev->pm.dynpm_can_upclock = false;
287 break;
288 case DYNPM_ACTION_NONE:
289 default:
290 DRM_ERROR("Requested mode for not defined action\n");
291 return;
292 }
293 /* only one clock mode per power state */
294 rdev->pm.requested_clock_mode_index = 0;
295
296 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
297 rdev->pm.power_state[rdev->pm.requested_power_state_index].
298 clock_info[rdev->pm.requested_clock_mode_index].sclk,
299 rdev->pm.power_state[rdev->pm.requested_power_state_index].
300 clock_info[rdev->pm.requested_clock_mode_index].mclk,
301 rdev->pm.power_state[rdev->pm.requested_power_state_index].
302 pcie_lanes);
303}
304
305/**
306 * r100_pm_init_profile - Initialize power profiles callback.
307 *
308 * @rdev: radeon_device pointer
309 *
310 * Initialize the power states used in profile mode
311 * (r1xx-r3xx).
312 * Used for profile mode only.
313 */
314void r100_pm_init_profile(struct radeon_device *rdev)
315{
316 /* default */
317 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
318 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
319 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
321 /* low sh */
322 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
326 /* mid sh */
327 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
331 /* high sh */
332 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
333 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
334 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
336 /* low mh */
337 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
339 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
341 /* mid mh */
342 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
344 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
346 /* high mh */
347 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
348 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
349 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
350 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
351}
352
353/**
354 * r100_pm_misc - set additional pm hw parameters callback.
355 *
356 * @rdev: radeon_device pointer
357 *
358 * Set non-clock parameters associated with a power state
359 * (voltage, pcie lanes, etc.) (r1xx-r4xx).
360 */
361void r100_pm_misc(struct radeon_device *rdev)
362{
363 int requested_index = rdev->pm.requested_power_state_index;
364 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
365 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
366 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
367
368 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
369 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
370 tmp = RREG32(voltage->gpio.reg);
371 if (voltage->active_high)
372 tmp |= voltage->gpio.mask;
373 else
374 tmp &= ~(voltage->gpio.mask);
375 WREG32(voltage->gpio.reg, tmp);
376 if (voltage->delay)
377 udelay(voltage->delay);
378 } else {
379 tmp = RREG32(voltage->gpio.reg);
380 if (voltage->active_high)
381 tmp &= ~voltage->gpio.mask;
382 else
383 tmp |= voltage->gpio.mask;
384 WREG32(voltage->gpio.reg, tmp);
385 if (voltage->delay)
386 udelay(voltage->delay);
387 }
388 }
389
390 sclk_cntl = RREG32_PLL(SCLK_CNTL);
391 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
392 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
393 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
394 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
395 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
396 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
397 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
398 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
399 else
400 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
401 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
402 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
403 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
404 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
405 } else
406 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
407
408 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
409 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
410 if (voltage->delay) {
411 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
412 switch (voltage->delay) {
413 case 33:
414 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
415 break;
416 case 66:
417 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
418 break;
419 case 99:
420 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
421 break;
422 case 132:
423 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
424 break;
425 }
426 } else
427 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
428 } else
429 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
430
431 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
432 sclk_cntl &= ~FORCE_HDP;
433 else
434 sclk_cntl |= FORCE_HDP;
435
436 WREG32_PLL(SCLK_CNTL, sclk_cntl);
437 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
438 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
439
440 /* set pcie lanes */
441 if ((rdev->flags & RADEON_IS_PCIE) &&
442 !(rdev->flags & RADEON_IS_IGP) &&
443 rdev->asic->pm.set_pcie_lanes &&
444 (ps->pcie_lanes !=
445 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
446 radeon_set_pcie_lanes(rdev,
447 ps->pcie_lanes);
448 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
449 }
450}
451
452/**
453 * r100_pm_prepare - pre-power state change callback.
454 *
455 * @rdev: radeon_device pointer
456 *
457 * Prepare for a power state change (r1xx-r4xx).
458 */
459void r100_pm_prepare(struct radeon_device *rdev)
460{
461 struct drm_device *ddev = rdev->ddev;
462 struct drm_crtc *crtc;
463 struct radeon_crtc *radeon_crtc;
464 u32 tmp;
465
466 /* disable any active CRTCs */
467 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
468 radeon_crtc = to_radeon_crtc(crtc);
469 if (radeon_crtc->enabled) {
470 if (radeon_crtc->crtc_id) {
471 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
472 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
473 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
474 } else {
475 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
476 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
477 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
478 }
479 }
480 }
481}
482
483/**
484 * r100_pm_finish - post-power state change callback.
485 *
486 * @rdev: radeon_device pointer
487 *
488 * Clean up after a power state change (r1xx-r4xx).
489 */
490void r100_pm_finish(struct radeon_device *rdev)
491{
492 struct drm_device *ddev = rdev->ddev;
493 struct drm_crtc *crtc;
494 struct radeon_crtc *radeon_crtc;
495 u32 tmp;
496
497 /* enable any active CRTCs */
498 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
499 radeon_crtc = to_radeon_crtc(crtc);
500 if (radeon_crtc->enabled) {
501 if (radeon_crtc->crtc_id) {
502 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
503 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
504 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
505 } else {
506 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
507 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
508 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
509 }
510 }
511 }
512}
513
514/**
515 * r100_gui_idle - gui idle callback.
516 *
517 * @rdev: radeon_device pointer
518 *
519 * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
520 * Returns true if idle, false if not.
521 */
522bool r100_gui_idle(struct radeon_device *rdev)
523{
524 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
525 return false;
526 else
527 return true;
528}
529
530/* hpd for digital panel detect/disconnect */
531/**
532 * r100_hpd_sense - hpd sense callback.
533 *
534 * @rdev: radeon_device pointer
535 * @hpd: hpd (hotplug detect) pin
536 *
537 * Checks if a digital monitor is connected (r1xx-r4xx).
538 * Returns true if connected, false if not connected.
539 */
540bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
541{
542 bool connected = false;
543
544 switch (hpd) {
545 case RADEON_HPD_1:
546 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
547 connected = true;
548 break;
549 case RADEON_HPD_2:
550 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
551 connected = true;
552 break;
553 default:
554 break;
555 }
556 return connected;
557}
558
559/**
560 * r100_hpd_set_polarity - hpd set polarity callback.
561 *
562 * @rdev: radeon_device pointer
563 * @hpd: hpd (hotplug detect) pin
564 *
565 * Set the polarity of the hpd pin (r1xx-r4xx).
566 */
567void r100_hpd_set_polarity(struct radeon_device *rdev,
568 enum radeon_hpd_id hpd)
569{
570 u32 tmp;
571 bool connected = r100_hpd_sense(rdev, hpd);
572
573 switch (hpd) {
574 case RADEON_HPD_1:
575 tmp = RREG32(RADEON_FP_GEN_CNTL);
576 if (connected)
577 tmp &= ~RADEON_FP_DETECT_INT_POL;
578 else
579 tmp |= RADEON_FP_DETECT_INT_POL;
580 WREG32(RADEON_FP_GEN_CNTL, tmp);
581 break;
582 case RADEON_HPD_2:
583 tmp = RREG32(RADEON_FP2_GEN_CNTL);
584 if (connected)
585 tmp &= ~RADEON_FP2_DETECT_INT_POL;
586 else
587 tmp |= RADEON_FP2_DETECT_INT_POL;
588 WREG32(RADEON_FP2_GEN_CNTL, tmp);
589 break;
590 default:
591 break;
592 }
593}
594
595/**
596 * r100_hpd_init - hpd setup callback.
597 *
598 * @rdev: radeon_device pointer
599 *
600 * Setup the hpd pins used by the card (r1xx-r4xx).
601 * Set the polarity, and enable the hpd interrupts.
602 */
603void r100_hpd_init(struct radeon_device *rdev)
604{
605 struct drm_device *dev = rdev->ddev;
606 struct drm_connector *connector;
607 unsigned enable = 0;
608
609 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
610 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
611 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
612 enable |= 1 << radeon_connector->hpd.hpd;
613 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
614 }
615 radeon_irq_kms_enable_hpd(rdev, enable);
616}
617
618/**
619 * r100_hpd_fini - hpd tear down callback.
620 *
621 * @rdev: radeon_device pointer
622 *
623 * Tear down the hpd pins used by the card (r1xx-r4xx).
624 * Disable the hpd interrupts.
625 */
626void r100_hpd_fini(struct radeon_device *rdev)
627{
628 struct drm_device *dev = rdev->ddev;
629 struct drm_connector *connector;
630 unsigned disable = 0;
631
632 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
633 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
634 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
635 disable |= 1 << radeon_connector->hpd.hpd;
636 }
637 radeon_irq_kms_disable_hpd(rdev, disable);
638}
639
640/*
641 * PCI GART
642 */
643void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
644{
645 /* TODO: can we do somethings here ? */
646 /* It seems hw only cache one entry so we should discard this
647 * entry otherwise if first GPU GART read hit this entry it
648 * could end up in wrong address. */
649}
650
651int r100_pci_gart_init(struct radeon_device *rdev)
652{
653 int r;
654
655 if (rdev->gart.ptr) {
656 WARN(1, "R100 PCI GART already initialized\n");
657 return 0;
658 }
659 /* Initialize common gart structure */
660 r = radeon_gart_init(rdev);
661 if (r)
662 return r;
663 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
664 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
665 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
666 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
667 return radeon_gart_table_ram_alloc(rdev);
668}
669
670int r100_pci_gart_enable(struct radeon_device *rdev)
671{
672 uint32_t tmp;
673
674 /* discard memory request outside of configured range */
675 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
676 WREG32(RADEON_AIC_CNTL, tmp);
677 /* set address range for PCI address translate */
678 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
679 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
680 /* set PCI GART page-table base address */
681 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
682 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
683 WREG32(RADEON_AIC_CNTL, tmp);
684 r100_pci_gart_tlb_flush(rdev);
685 DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
686 (unsigned)(rdev->mc.gtt_size >> 20),
687 (unsigned long long)rdev->gart.table_addr);
688 rdev->gart.ready = true;
689 return 0;
690}
691
692void r100_pci_gart_disable(struct radeon_device *rdev)
693{
694 uint32_t tmp;
695
696 /* discard memory request outside of configured range */
697 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
698 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
699 WREG32(RADEON_AIC_LO_ADDR, 0);
700 WREG32(RADEON_AIC_HI_ADDR, 0);
701}
702
703uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags)
704{
705 return addr;
706}
707
708void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
709 uint64_t entry)
710{
711 u32 *gtt = rdev->gart.ptr;
712 gtt[i] = cpu_to_le32(lower_32_bits(entry));
713}
714
715void r100_pci_gart_fini(struct radeon_device *rdev)
716{
717 radeon_gart_fini(rdev);
718 r100_pci_gart_disable(rdev);
719 radeon_gart_table_ram_free(rdev);
720}
721
722int r100_irq_set(struct radeon_device *rdev)
723{
724 uint32_t tmp = 0;
725
726 if (!rdev->irq.installed) {
727 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
728 WREG32(R_000040_GEN_INT_CNTL, 0);
729 return -EINVAL;
730 }
731 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
732 tmp |= RADEON_SW_INT_ENABLE;
733 }
734 if (rdev->irq.crtc_vblank_int[0] ||
735 atomic_read(&rdev->irq.pflip[0])) {
736 tmp |= RADEON_CRTC_VBLANK_MASK;
737 }
738 if (rdev->irq.crtc_vblank_int[1] ||
739 atomic_read(&rdev->irq.pflip[1])) {
740 tmp |= RADEON_CRTC2_VBLANK_MASK;
741 }
742 if (rdev->irq.hpd[0]) {
743 tmp |= RADEON_FP_DETECT_MASK;
744 }
745 if (rdev->irq.hpd[1]) {
746 tmp |= RADEON_FP2_DETECT_MASK;
747 }
748 WREG32(RADEON_GEN_INT_CNTL, tmp);
749
750 /* read back to post the write */
751 RREG32(RADEON_GEN_INT_CNTL);
752
753 return 0;
754}
755
756void r100_irq_disable(struct radeon_device *rdev)
757{
758 u32 tmp;
759
760 WREG32(R_000040_GEN_INT_CNTL, 0);
761 /* Wait and acknowledge irq */
762 mdelay(1);
763 tmp = RREG32(R_000044_GEN_INT_STATUS);
764 WREG32(R_000044_GEN_INT_STATUS, tmp);
765}
766
767static uint32_t r100_irq_ack(struct radeon_device *rdev)
768{
769 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
770 uint32_t irq_mask = RADEON_SW_INT_TEST |
771 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
772 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
773
774 if (irqs) {
775 WREG32(RADEON_GEN_INT_STATUS, irqs);
776 }
777 return irqs & irq_mask;
778}
779
780int r100_irq_process(struct radeon_device *rdev)
781{
782 uint32_t status, msi_rearm;
783 bool queue_hotplug = false;
784
785 status = r100_irq_ack(rdev);
786 if (!status) {
787 return IRQ_NONE;
788 }
789 if (rdev->shutdown) {
790 return IRQ_NONE;
791 }
792 while (status) {
793 /* SW interrupt */
794 if (status & RADEON_SW_INT_TEST) {
795 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
796 }
797 /* Vertical blank interrupts */
798 if (status & RADEON_CRTC_VBLANK_STAT) {
799 if (rdev->irq.crtc_vblank_int[0]) {
800 drm_handle_vblank(rdev->ddev, 0);
801 rdev->pm.vblank_sync = true;
802 wake_up(&rdev->irq.vblank_queue);
803 }
804 if (atomic_read(&rdev->irq.pflip[0]))
805 radeon_crtc_handle_vblank(rdev, 0);
806 }
807 if (status & RADEON_CRTC2_VBLANK_STAT) {
808 if (rdev->irq.crtc_vblank_int[1]) {
809 drm_handle_vblank(rdev->ddev, 1);
810 rdev->pm.vblank_sync = true;
811 wake_up(&rdev->irq.vblank_queue);
812 }
813 if (atomic_read(&rdev->irq.pflip[1]))
814 radeon_crtc_handle_vblank(rdev, 1);
815 }
816 if (status & RADEON_FP_DETECT_STAT) {
817 queue_hotplug = true;
818 DRM_DEBUG("HPD1\n");
819 }
820 if (status & RADEON_FP2_DETECT_STAT) {
821 queue_hotplug = true;
822 DRM_DEBUG("HPD2\n");
823 }
824 status = r100_irq_ack(rdev);
825 }
826 if (queue_hotplug)
827 schedule_delayed_work(&rdev->hotplug_work, 0);
828 if (rdev->msi_enabled) {
829 switch (rdev->family) {
830 case CHIP_RS400:
831 case CHIP_RS480:
832 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
833 WREG32(RADEON_AIC_CNTL, msi_rearm);
834 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
835 break;
836 default:
837 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
838 break;
839 }
840 }
841 return IRQ_HANDLED;
842}
843
844u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
845{
846 if (crtc == 0)
847 return RREG32(RADEON_CRTC_CRNT_FRAME);
848 else
849 return RREG32(RADEON_CRTC2_CRNT_FRAME);
850}
851
852/**
853 * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
854 * @rdev: radeon device structure
855 * @ring: ring buffer struct for emitting packets
856 */
857static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
858{
859 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
860 radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
861 RADEON_HDP_READ_BUFFER_INVALIDATE);
862 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
863 radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
864}
865
866/* Who ever call radeon_fence_emit should call ring_lock and ask
867 * for enough space (today caller are ib schedule and buffer move) */
868void r100_fence_ring_emit(struct radeon_device *rdev,
869 struct radeon_fence *fence)
870{
871 struct radeon_ring *ring = &rdev->ring[fence->ring];
872
873 /* We have to make sure that caches are flushed before
874 * CPU might read something from VRAM. */
875 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
876 radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
877 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
878 radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
879 /* Wait until IDLE & CLEAN */
880 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
881 radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
882 r100_ring_hdp_flush(rdev, ring);
883 /* Emit fence sequence & fire IRQ */
884 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
885 radeon_ring_write(ring, fence->seq);
886 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
887 radeon_ring_write(ring, RADEON_SW_INT_FIRE);
888}
889
890bool r100_semaphore_ring_emit(struct radeon_device *rdev,
891 struct radeon_ring *ring,
892 struct radeon_semaphore *semaphore,
893 bool emit_wait)
894{
895 /* Unused on older asics, since we don't have semaphores or multiple rings */
896 BUG();
897 return false;
898}
899
900struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
901 uint64_t src_offset,
902 uint64_t dst_offset,
903 unsigned num_gpu_pages,
904 struct dma_resv *resv)
905{
906 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
907 struct radeon_fence *fence;
908 uint32_t cur_pages;
909 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
910 uint32_t pitch;
911 uint32_t stride_pixels;
912 unsigned ndw;
913 int num_loops;
914 int r = 0;
915
916 /* radeon limited to 16k stride */
917 stride_bytes &= 0x3fff;
918 /* radeon pitch is /64 */
919 pitch = stride_bytes / 64;
920 stride_pixels = stride_bytes / 4;
921 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
922
923 /* Ask for enough room for blit + flush + fence */
924 ndw = 64 + (10 * num_loops);
925 r = radeon_ring_lock(rdev, ring, ndw);
926 if (r) {
927 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
928 return ERR_PTR(-EINVAL);
929 }
930 while (num_gpu_pages > 0) {
931 cur_pages = num_gpu_pages;
932 if (cur_pages > 8191) {
933 cur_pages = 8191;
934 }
935 num_gpu_pages -= cur_pages;
936
937 /* pages are in Y direction - height
938 page width in X direction - width */
939 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
940 radeon_ring_write(ring,
941 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
942 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
943 RADEON_GMC_SRC_CLIPPING |
944 RADEON_GMC_DST_CLIPPING |
945 RADEON_GMC_BRUSH_NONE |
946 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
947 RADEON_GMC_SRC_DATATYPE_COLOR |
948 RADEON_ROP3_S |
949 RADEON_DP_SRC_SOURCE_MEMORY |
950 RADEON_GMC_CLR_CMP_CNTL_DIS |
951 RADEON_GMC_WR_MSK_DIS);
952 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
953 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
954 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
955 radeon_ring_write(ring, 0);
956 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
957 radeon_ring_write(ring, num_gpu_pages);
958 radeon_ring_write(ring, num_gpu_pages);
959 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
960 }
961 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
962 radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
963 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
964 radeon_ring_write(ring,
965 RADEON_WAIT_2D_IDLECLEAN |
966 RADEON_WAIT_HOST_IDLECLEAN |
967 RADEON_WAIT_DMA_GUI_IDLE);
968 r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
969 if (r) {
970 radeon_ring_unlock_undo(rdev, ring);
971 return ERR_PTR(r);
972 }
973 radeon_ring_unlock_commit(rdev, ring, false);
974 return fence;
975}
976
977static int r100_cp_wait_for_idle(struct radeon_device *rdev)
978{
979 unsigned i;
980 u32 tmp;
981
982 for (i = 0; i < rdev->usec_timeout; i++) {
983 tmp = RREG32(R_000E40_RBBM_STATUS);
984 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
985 return 0;
986 }
987 udelay(1);
988 }
989 return -1;
990}
991
992void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
993{
994 int r;
995
996 r = radeon_ring_lock(rdev, ring, 2);
997 if (r) {
998 return;
999 }
1000 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
1001 radeon_ring_write(ring,
1002 RADEON_ISYNC_ANY2D_IDLE3D |
1003 RADEON_ISYNC_ANY3D_IDLE2D |
1004 RADEON_ISYNC_WAIT_IDLEGUI |
1005 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
1006 radeon_ring_unlock_commit(rdev, ring, false);
1007}
1008
1009
1010/* Load the microcode for the CP */
1011static int r100_cp_init_microcode(struct radeon_device *rdev)
1012{
1013 const char *fw_name = NULL;
1014 int err;
1015
1016 DRM_DEBUG_KMS("\n");
1017
1018 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
1019 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
1020 (rdev->family == CHIP_RS200)) {
1021 DRM_INFO("Loading R100 Microcode\n");
1022 fw_name = FIRMWARE_R100;
1023 } else if ((rdev->family == CHIP_R200) ||
1024 (rdev->family == CHIP_RV250) ||
1025 (rdev->family == CHIP_RV280) ||
1026 (rdev->family == CHIP_RS300)) {
1027 DRM_INFO("Loading R200 Microcode\n");
1028 fw_name = FIRMWARE_R200;
1029 } else if ((rdev->family == CHIP_R300) ||
1030 (rdev->family == CHIP_R350) ||
1031 (rdev->family == CHIP_RV350) ||
1032 (rdev->family == CHIP_RV380) ||
1033 (rdev->family == CHIP_RS400) ||
1034 (rdev->family == CHIP_RS480)) {
1035 DRM_INFO("Loading R300 Microcode\n");
1036 fw_name = FIRMWARE_R300;
1037 } else if ((rdev->family == CHIP_R420) ||
1038 (rdev->family == CHIP_R423) ||
1039 (rdev->family == CHIP_RV410)) {
1040 DRM_INFO("Loading R400 Microcode\n");
1041 fw_name = FIRMWARE_R420;
1042 } else if ((rdev->family == CHIP_RS690) ||
1043 (rdev->family == CHIP_RS740)) {
1044 DRM_INFO("Loading RS690/RS740 Microcode\n");
1045 fw_name = FIRMWARE_RS690;
1046 } else if (rdev->family == CHIP_RS600) {
1047 DRM_INFO("Loading RS600 Microcode\n");
1048 fw_name = FIRMWARE_RS600;
1049 } else if ((rdev->family == CHIP_RV515) ||
1050 (rdev->family == CHIP_R520) ||
1051 (rdev->family == CHIP_RV530) ||
1052 (rdev->family == CHIP_R580) ||
1053 (rdev->family == CHIP_RV560) ||
1054 (rdev->family == CHIP_RV570)) {
1055 DRM_INFO("Loading R500 Microcode\n");
1056 fw_name = FIRMWARE_R520;
1057 }
1058
1059 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1060 if (err) {
1061 pr_err("radeon_cp: Failed to load firmware \"%s\"\n", fw_name);
1062 } else if (rdev->me_fw->size % 8) {
1063 pr_err("radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1064 rdev->me_fw->size, fw_name);
1065 err = -EINVAL;
1066 release_firmware(rdev->me_fw);
1067 rdev->me_fw = NULL;
1068 }
1069 return err;
1070}
1071
1072u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1073 struct radeon_ring *ring)
1074{
1075 u32 rptr;
1076
1077 if (rdev->wb.enabled)
1078 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1079 else
1080 rptr = RREG32(RADEON_CP_RB_RPTR);
1081
1082 return rptr;
1083}
1084
1085u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1086 struct radeon_ring *ring)
1087{
1088 return RREG32(RADEON_CP_RB_WPTR);
1089}
1090
1091void r100_gfx_set_wptr(struct radeon_device *rdev,
1092 struct radeon_ring *ring)
1093{
1094 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1095 (void)RREG32(RADEON_CP_RB_WPTR);
1096}
1097
1098static void r100_cp_load_microcode(struct radeon_device *rdev)
1099{
1100 const __be32 *fw_data;
1101 int i, size;
1102
1103 if (r100_gui_wait_for_idle(rdev)) {
1104 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
1105 }
1106
1107 if (rdev->me_fw) {
1108 size = rdev->me_fw->size / 4;
1109 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1110 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1111 for (i = 0; i < size; i += 2) {
1112 WREG32(RADEON_CP_ME_RAM_DATAH,
1113 be32_to_cpup(&fw_data[i]));
1114 WREG32(RADEON_CP_ME_RAM_DATAL,
1115 be32_to_cpup(&fw_data[i + 1]));
1116 }
1117 }
1118}
1119
1120int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1121{
1122 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1123 unsigned rb_bufsz;
1124 unsigned rb_blksz;
1125 unsigned max_fetch;
1126 unsigned pre_write_timer;
1127 unsigned pre_write_limit;
1128 unsigned indirect2_start;
1129 unsigned indirect1_start;
1130 uint32_t tmp;
1131 int r;
1132
1133 r100_debugfs_cp_init(rdev);
1134 if (!rdev->me_fw) {
1135 r = r100_cp_init_microcode(rdev);
1136 if (r) {
1137 DRM_ERROR("Failed to load firmware!\n");
1138 return r;
1139 }
1140 }
1141
1142 /* Align ring size */
1143 rb_bufsz = order_base_2(ring_size / 8);
1144 ring_size = (1 << (rb_bufsz + 1)) * 4;
1145 r100_cp_load_microcode(rdev);
1146 r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1147 RADEON_CP_PACKET2);
1148 if (r) {
1149 return r;
1150 }
1151 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1152 * the rptr copy in system ram */
1153 rb_blksz = 9;
1154 /* cp will read 128bytes at a time (4 dwords) */
1155 max_fetch = 1;
1156 ring->align_mask = 16 - 1;
1157 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1158 pre_write_timer = 64;
1159 /* Force CP_RB_WPTR write if written more than one time before the
1160 * delay expire
1161 */
1162 pre_write_limit = 0;
1163 /* Setup the cp cache like this (cache size is 96 dwords) :
1164 * RING 0 to 15
1165 * INDIRECT1 16 to 79
1166 * INDIRECT2 80 to 95
1167 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1168 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1169 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1170 * Idea being that most of the gpu cmd will be through indirect1 buffer
1171 * so it gets the bigger cache.
1172 */
1173 indirect2_start = 80;
1174 indirect1_start = 16;
1175 /* cp setup */
1176 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1177 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1178 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1179 REG_SET(RADEON_MAX_FETCH, max_fetch));
1180#ifdef __BIG_ENDIAN
1181 tmp |= RADEON_BUF_SWAP_32BIT;
1182#endif
1183 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1184
1185 /* Set ring address */
1186 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1187 WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1188 /* Force read & write ptr to 0 */
1189 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1190 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1191 ring->wptr = 0;
1192 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1193
1194 /* set the wb address whether it's enabled or not */
1195 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1196 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1197 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1198
1199 if (rdev->wb.enabled)
1200 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1201 else {
1202 tmp |= RADEON_RB_NO_UPDATE;
1203 WREG32(R_000770_SCRATCH_UMSK, 0);
1204 }
1205
1206 WREG32(RADEON_CP_RB_CNTL, tmp);
1207 udelay(10);
1208 /* Set cp mode to bus mastering & enable cp*/
1209 WREG32(RADEON_CP_CSQ_MODE,
1210 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1211 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1212 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1213 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1214 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1215
1216 /* at this point everything should be setup correctly to enable master */
1217 pci_set_master(rdev->pdev);
1218
1219 radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1220 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1221 if (r) {
1222 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1223 return r;
1224 }
1225 ring->ready = true;
1226 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1227
1228 if (!ring->rptr_save_reg /* not resuming from suspend */
1229 && radeon_ring_supports_scratch_reg(rdev, ring)) {
1230 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1231 if (r) {
1232 DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1233 ring->rptr_save_reg = 0;
1234 }
1235 }
1236 return 0;
1237}
1238
1239void r100_cp_fini(struct radeon_device *rdev)
1240{
1241 if (r100_cp_wait_for_idle(rdev)) {
1242 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1243 }
1244 /* Disable ring */
1245 r100_cp_disable(rdev);
1246 radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1247 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1248 DRM_INFO("radeon: cp finalized\n");
1249}
1250
1251void r100_cp_disable(struct radeon_device *rdev)
1252{
1253 /* Disable ring */
1254 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1255 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1256 WREG32(RADEON_CP_CSQ_MODE, 0);
1257 WREG32(RADEON_CP_CSQ_CNTL, 0);
1258 WREG32(R_000770_SCRATCH_UMSK, 0);
1259 if (r100_gui_wait_for_idle(rdev)) {
1260 pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
1261 }
1262}
1263
1264/*
1265 * CS functions
1266 */
1267int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1268 struct radeon_cs_packet *pkt,
1269 unsigned idx,
1270 unsigned reg)
1271{
1272 int r;
1273 u32 tile_flags = 0;
1274 u32 tmp;
1275 struct radeon_bo_list *reloc;
1276 u32 value;
1277
1278 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1279 if (r) {
1280 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1281 idx, reg);
1282 radeon_cs_dump_packet(p, pkt);
1283 return r;
1284 }
1285
1286 value = radeon_get_ib_value(p, idx);
1287 tmp = value & 0x003fffff;
1288 tmp += (((u32)reloc->gpu_offset) >> 10);
1289
1290 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1291 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1292 tile_flags |= RADEON_DST_TILE_MACRO;
1293 if (reloc->tiling_flags & RADEON_TILING_MICRO) {
1294 if (reg == RADEON_SRC_PITCH_OFFSET) {
1295 DRM_ERROR("Cannot src blit from microtiled surface\n");
1296 radeon_cs_dump_packet(p, pkt);
1297 return -EINVAL;
1298 }
1299 tile_flags |= RADEON_DST_TILE_MICRO;
1300 }
1301
1302 tmp |= tile_flags;
1303 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1304 } else
1305 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1306 return 0;
1307}
1308
1309int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1310 struct radeon_cs_packet *pkt,
1311 int idx)
1312{
1313 unsigned c, i;
1314 struct radeon_bo_list *reloc;
1315 struct r100_cs_track *track;
1316 int r = 0;
1317 volatile uint32_t *ib;
1318 u32 idx_value;
1319
1320 ib = p->ib.ptr;
1321 track = (struct r100_cs_track *)p->track;
1322 c = radeon_get_ib_value(p, idx++) & 0x1F;
1323 if (c > 16) {
1324 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1325 pkt->opcode);
1326 radeon_cs_dump_packet(p, pkt);
1327 return -EINVAL;
1328 }
1329 track->num_arrays = c;
1330 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1331 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1332 if (r) {
1333 DRM_ERROR("No reloc for packet3 %d\n",
1334 pkt->opcode);
1335 radeon_cs_dump_packet(p, pkt);
1336 return r;
1337 }
1338 idx_value = radeon_get_ib_value(p, idx);
1339 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1340
1341 track->arrays[i + 0].esize = idx_value >> 8;
1342 track->arrays[i + 0].robj = reloc->robj;
1343 track->arrays[i + 0].esize &= 0x7F;
1344 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1345 if (r) {
1346 DRM_ERROR("No reloc for packet3 %d\n",
1347 pkt->opcode);
1348 radeon_cs_dump_packet(p, pkt);
1349 return r;
1350 }
1351 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
1352 track->arrays[i + 1].robj = reloc->robj;
1353 track->arrays[i + 1].esize = idx_value >> 24;
1354 track->arrays[i + 1].esize &= 0x7F;
1355 }
1356 if (c & 1) {
1357 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1358 if (r) {
1359 DRM_ERROR("No reloc for packet3 %d\n",
1360 pkt->opcode);
1361 radeon_cs_dump_packet(p, pkt);
1362 return r;
1363 }
1364 idx_value = radeon_get_ib_value(p, idx);
1365 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1366 track->arrays[i + 0].robj = reloc->robj;
1367 track->arrays[i + 0].esize = idx_value >> 8;
1368 track->arrays[i + 0].esize &= 0x7F;
1369 }
1370 return r;
1371}
1372
1373int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1374 struct radeon_cs_packet *pkt,
1375 const unsigned *auth, unsigned n,
1376 radeon_packet0_check_t check)
1377{
1378 unsigned reg;
1379 unsigned i, j, m;
1380 unsigned idx;
1381 int r;
1382
1383 idx = pkt->idx + 1;
1384 reg = pkt->reg;
1385 /* Check that register fall into register range
1386 * determined by the number of entry (n) in the
1387 * safe register bitmap.
1388 */
1389 if (pkt->one_reg_wr) {
1390 if ((reg >> 7) > n) {
1391 return -EINVAL;
1392 }
1393 } else {
1394 if (((reg + (pkt->count << 2)) >> 7) > n) {
1395 return -EINVAL;
1396 }
1397 }
1398 for (i = 0; i <= pkt->count; i++, idx++) {
1399 j = (reg >> 7);
1400 m = 1 << ((reg >> 2) & 31);
1401 if (auth[j] & m) {
1402 r = check(p, pkt, idx, reg);
1403 if (r) {
1404 return r;
1405 }
1406 }
1407 if (pkt->one_reg_wr) {
1408 if (!(auth[j] & m)) {
1409 break;
1410 }
1411 } else {
1412 reg += 4;
1413 }
1414 }
1415 return 0;
1416}
1417
1418/**
1419 * r100_cs_packet_parse_vline() - parse userspace VLINE packet
1420 * @p: parser structure holding parsing context.
1421 *
1422 * Userspace sends a special sequence for VLINE waits.
1423 * PACKET0 - VLINE_START_END + value
1424 * PACKET0 - WAIT_UNTIL +_value
1425 * RELOC (P3) - crtc_id in reloc.
1426 *
1427 * This function parses this and relocates the VLINE START END
1428 * and WAIT UNTIL packets to the correct crtc.
1429 * It also detects a switched off crtc and nulls out the
1430 * wait in that case.
1431 */
1432int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1433{
1434 struct drm_crtc *crtc;
1435 struct radeon_crtc *radeon_crtc;
1436 struct radeon_cs_packet p3reloc, waitreloc;
1437 int crtc_id;
1438 int r;
1439 uint32_t header, h_idx, reg;
1440 volatile uint32_t *ib;
1441
1442 ib = p->ib.ptr;
1443
1444 /* parse the wait until */
1445 r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1446 if (r)
1447 return r;
1448
1449 /* check its a wait until and only 1 count */
1450 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1451 waitreloc.count != 0) {
1452 DRM_ERROR("vline wait had illegal wait until segment\n");
1453 return -EINVAL;
1454 }
1455
1456 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1457 DRM_ERROR("vline wait had illegal wait until\n");
1458 return -EINVAL;
1459 }
1460
1461 /* jump over the NOP */
1462 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1463 if (r)
1464 return r;
1465
1466 h_idx = p->idx - 2;
1467 p->idx += waitreloc.count + 2;
1468 p->idx += p3reloc.count + 2;
1469
1470 header = radeon_get_ib_value(p, h_idx);
1471 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1472 reg = R100_CP_PACKET0_GET_REG(header);
1473 crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id);
1474 if (!crtc) {
1475 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1476 return -ENOENT;
1477 }
1478 radeon_crtc = to_radeon_crtc(crtc);
1479 crtc_id = radeon_crtc->crtc_id;
1480
1481 if (!crtc->enabled) {
1482 /* if the CRTC isn't enabled - we need to nop out the wait until */
1483 ib[h_idx + 2] = PACKET2(0);
1484 ib[h_idx + 3] = PACKET2(0);
1485 } else if (crtc_id == 1) {
1486 switch (reg) {
1487 case AVIVO_D1MODE_VLINE_START_END:
1488 header &= ~R300_CP_PACKET0_REG_MASK;
1489 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1490 break;
1491 case RADEON_CRTC_GUI_TRIG_VLINE:
1492 header &= ~R300_CP_PACKET0_REG_MASK;
1493 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1494 break;
1495 default:
1496 DRM_ERROR("unknown crtc reloc\n");
1497 return -EINVAL;
1498 }
1499 ib[h_idx] = header;
1500 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1501 }
1502
1503 return 0;
1504}
1505
1506static int r100_get_vtx_size(uint32_t vtx_fmt)
1507{
1508 int vtx_size;
1509 vtx_size = 2;
1510 /* ordered according to bits in spec */
1511 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1512 vtx_size++;
1513 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1514 vtx_size += 3;
1515 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1516 vtx_size++;
1517 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1518 vtx_size++;
1519 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1520 vtx_size += 3;
1521 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1522 vtx_size++;
1523 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1524 vtx_size++;
1525 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1526 vtx_size += 2;
1527 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1528 vtx_size += 2;
1529 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1530 vtx_size++;
1531 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1532 vtx_size += 2;
1533 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1534 vtx_size++;
1535 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1536 vtx_size += 2;
1537 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1538 vtx_size++;
1539 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1540 vtx_size++;
1541 /* blend weight */
1542 if (vtx_fmt & (0x7 << 15))
1543 vtx_size += (vtx_fmt >> 15) & 0x7;
1544 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1545 vtx_size += 3;
1546 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1547 vtx_size += 2;
1548 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1549 vtx_size++;
1550 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1551 vtx_size++;
1552 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1553 vtx_size++;
1554 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1555 vtx_size++;
1556 return vtx_size;
1557}
1558
1559static int r100_packet0_check(struct radeon_cs_parser *p,
1560 struct radeon_cs_packet *pkt,
1561 unsigned idx, unsigned reg)
1562{
1563 struct radeon_bo_list *reloc;
1564 struct r100_cs_track *track;
1565 volatile uint32_t *ib;
1566 uint32_t tmp;
1567 int r;
1568 int i, face;
1569 u32 tile_flags = 0;
1570 u32 idx_value;
1571
1572 ib = p->ib.ptr;
1573 track = (struct r100_cs_track *)p->track;
1574
1575 idx_value = radeon_get_ib_value(p, idx);
1576
1577 switch (reg) {
1578 case RADEON_CRTC_GUI_TRIG_VLINE:
1579 r = r100_cs_packet_parse_vline(p);
1580 if (r) {
1581 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1582 idx, reg);
1583 radeon_cs_dump_packet(p, pkt);
1584 return r;
1585 }
1586 break;
1587 /* FIXME: only allow PACKET3 blit? easier to check for out of
1588 * range access */
1589 case RADEON_DST_PITCH_OFFSET:
1590 case RADEON_SRC_PITCH_OFFSET:
1591 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1592 if (r)
1593 return r;
1594 break;
1595 case RADEON_RB3D_DEPTHOFFSET:
1596 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1597 if (r) {
1598 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1599 idx, reg);
1600 radeon_cs_dump_packet(p, pkt);
1601 return r;
1602 }
1603 track->zb.robj = reloc->robj;
1604 track->zb.offset = idx_value;
1605 track->zb_dirty = true;
1606 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1607 break;
1608 case RADEON_RB3D_COLOROFFSET:
1609 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1610 if (r) {
1611 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1612 idx, reg);
1613 radeon_cs_dump_packet(p, pkt);
1614 return r;
1615 }
1616 track->cb[0].robj = reloc->robj;
1617 track->cb[0].offset = idx_value;
1618 track->cb_dirty = true;
1619 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1620 break;
1621 case RADEON_PP_TXOFFSET_0:
1622 case RADEON_PP_TXOFFSET_1:
1623 case RADEON_PP_TXOFFSET_2:
1624 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1625 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1626 if (r) {
1627 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1628 idx, reg);
1629 radeon_cs_dump_packet(p, pkt);
1630 return r;
1631 }
1632 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1633 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1634 tile_flags |= RADEON_TXO_MACRO_TILE;
1635 if (reloc->tiling_flags & RADEON_TILING_MICRO)
1636 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1637
1638 tmp = idx_value & ~(0x7 << 2);
1639 tmp |= tile_flags;
1640 ib[idx] = tmp + ((u32)reloc->gpu_offset);
1641 } else
1642 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1643 track->textures[i].robj = reloc->robj;
1644 track->tex_dirty = true;
1645 break;
1646 case RADEON_PP_CUBIC_OFFSET_T0_0:
1647 case RADEON_PP_CUBIC_OFFSET_T0_1:
1648 case RADEON_PP_CUBIC_OFFSET_T0_2:
1649 case RADEON_PP_CUBIC_OFFSET_T0_3:
1650 case RADEON_PP_CUBIC_OFFSET_T0_4:
1651 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1652 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1653 if (r) {
1654 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1655 idx, reg);
1656 radeon_cs_dump_packet(p, pkt);
1657 return r;
1658 }
1659 track->textures[0].cube_info[i].offset = idx_value;
1660 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1661 track->textures[0].cube_info[i].robj = reloc->robj;
1662 track->tex_dirty = true;
1663 break;
1664 case RADEON_PP_CUBIC_OFFSET_T1_0:
1665 case RADEON_PP_CUBIC_OFFSET_T1_1:
1666 case RADEON_PP_CUBIC_OFFSET_T1_2:
1667 case RADEON_PP_CUBIC_OFFSET_T1_3:
1668 case RADEON_PP_CUBIC_OFFSET_T1_4:
1669 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1670 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1671 if (r) {
1672 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1673 idx, reg);
1674 radeon_cs_dump_packet(p, pkt);
1675 return r;
1676 }
1677 track->textures[1].cube_info[i].offset = idx_value;
1678 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1679 track->textures[1].cube_info[i].robj = reloc->robj;
1680 track->tex_dirty = true;
1681 break;
1682 case RADEON_PP_CUBIC_OFFSET_T2_0:
1683 case RADEON_PP_CUBIC_OFFSET_T2_1:
1684 case RADEON_PP_CUBIC_OFFSET_T2_2:
1685 case RADEON_PP_CUBIC_OFFSET_T2_3:
1686 case RADEON_PP_CUBIC_OFFSET_T2_4:
1687 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1688 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1689 if (r) {
1690 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1691 idx, reg);
1692 radeon_cs_dump_packet(p, pkt);
1693 return r;
1694 }
1695 track->textures[2].cube_info[i].offset = idx_value;
1696 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1697 track->textures[2].cube_info[i].robj = reloc->robj;
1698 track->tex_dirty = true;
1699 break;
1700 case RADEON_RE_WIDTH_HEIGHT:
1701 track->maxy = ((idx_value >> 16) & 0x7FF);
1702 track->cb_dirty = true;
1703 track->zb_dirty = true;
1704 break;
1705 case RADEON_RB3D_COLORPITCH:
1706 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1707 if (r) {
1708 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1709 idx, reg);
1710 radeon_cs_dump_packet(p, pkt);
1711 return r;
1712 }
1713 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1714 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1715 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1716 if (reloc->tiling_flags & RADEON_TILING_MICRO)
1717 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1718
1719 tmp = idx_value & ~(0x7 << 16);
1720 tmp |= tile_flags;
1721 ib[idx] = tmp;
1722 } else
1723 ib[idx] = idx_value;
1724
1725 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1726 track->cb_dirty = true;
1727 break;
1728 case RADEON_RB3D_DEPTHPITCH:
1729 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1730 track->zb_dirty = true;
1731 break;
1732 case RADEON_RB3D_CNTL:
1733 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1734 case 7:
1735 case 8:
1736 case 9:
1737 case 11:
1738 case 12:
1739 track->cb[0].cpp = 1;
1740 break;
1741 case 3:
1742 case 4:
1743 case 15:
1744 track->cb[0].cpp = 2;
1745 break;
1746 case 6:
1747 track->cb[0].cpp = 4;
1748 break;
1749 default:
1750 DRM_ERROR("Invalid color buffer format (%d) !\n",
1751 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1752 return -EINVAL;
1753 }
1754 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1755 track->cb_dirty = true;
1756 track->zb_dirty = true;
1757 break;
1758 case RADEON_RB3D_ZSTENCILCNTL:
1759 switch (idx_value & 0xf) {
1760 case 0:
1761 track->zb.cpp = 2;
1762 break;
1763 case 2:
1764 case 3:
1765 case 4:
1766 case 5:
1767 case 9:
1768 case 11:
1769 track->zb.cpp = 4;
1770 break;
1771 default:
1772 break;
1773 }
1774 track->zb_dirty = true;
1775 break;
1776 case RADEON_RB3D_ZPASS_ADDR:
1777 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1778 if (r) {
1779 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1780 idx, reg);
1781 radeon_cs_dump_packet(p, pkt);
1782 return r;
1783 }
1784 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1785 break;
1786 case RADEON_PP_CNTL:
1787 {
1788 uint32_t temp = idx_value >> 4;
1789 for (i = 0; i < track->num_texture; i++)
1790 track->textures[i].enabled = !!(temp & (1 << i));
1791 track->tex_dirty = true;
1792 }
1793 break;
1794 case RADEON_SE_VF_CNTL:
1795 track->vap_vf_cntl = idx_value;
1796 break;
1797 case RADEON_SE_VTX_FMT:
1798 track->vtx_size = r100_get_vtx_size(idx_value);
1799 break;
1800 case RADEON_PP_TEX_SIZE_0:
1801 case RADEON_PP_TEX_SIZE_1:
1802 case RADEON_PP_TEX_SIZE_2:
1803 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1804 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1805 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1806 track->tex_dirty = true;
1807 break;
1808 case RADEON_PP_TEX_PITCH_0:
1809 case RADEON_PP_TEX_PITCH_1:
1810 case RADEON_PP_TEX_PITCH_2:
1811 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1812 track->textures[i].pitch = idx_value + 32;
1813 track->tex_dirty = true;
1814 break;
1815 case RADEON_PP_TXFILTER_0:
1816 case RADEON_PP_TXFILTER_1:
1817 case RADEON_PP_TXFILTER_2:
1818 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1819 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1820 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1821 tmp = (idx_value >> 23) & 0x7;
1822 if (tmp == 2 || tmp == 6)
1823 track->textures[i].roundup_w = false;
1824 tmp = (idx_value >> 27) & 0x7;
1825 if (tmp == 2 || tmp == 6)
1826 track->textures[i].roundup_h = false;
1827 track->tex_dirty = true;
1828 break;
1829 case RADEON_PP_TXFORMAT_0:
1830 case RADEON_PP_TXFORMAT_1:
1831 case RADEON_PP_TXFORMAT_2:
1832 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1833 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1834 track->textures[i].use_pitch = true;
1835 } else {
1836 track->textures[i].use_pitch = false;
1837 track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT);
1838 track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT);
1839 }
1840 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1841 track->textures[i].tex_coord_type = 2;
1842 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1843 case RADEON_TXFORMAT_I8:
1844 case RADEON_TXFORMAT_RGB332:
1845 case RADEON_TXFORMAT_Y8:
1846 track->textures[i].cpp = 1;
1847 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1848 break;
1849 case RADEON_TXFORMAT_AI88:
1850 case RADEON_TXFORMAT_ARGB1555:
1851 case RADEON_TXFORMAT_RGB565:
1852 case RADEON_TXFORMAT_ARGB4444:
1853 case RADEON_TXFORMAT_VYUY422:
1854 case RADEON_TXFORMAT_YVYU422:
1855 case RADEON_TXFORMAT_SHADOW16:
1856 case RADEON_TXFORMAT_LDUDV655:
1857 case RADEON_TXFORMAT_DUDV88:
1858 track->textures[i].cpp = 2;
1859 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1860 break;
1861 case RADEON_TXFORMAT_ARGB8888:
1862 case RADEON_TXFORMAT_RGBA8888:
1863 case RADEON_TXFORMAT_SHADOW32:
1864 case RADEON_TXFORMAT_LDUDUV8888:
1865 track->textures[i].cpp = 4;
1866 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1867 break;
1868 case RADEON_TXFORMAT_DXT1:
1869 track->textures[i].cpp = 1;
1870 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1871 break;
1872 case RADEON_TXFORMAT_DXT23:
1873 case RADEON_TXFORMAT_DXT45:
1874 track->textures[i].cpp = 1;
1875 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1876 break;
1877 }
1878 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1879 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1880 track->tex_dirty = true;
1881 break;
1882 case RADEON_PP_CUBIC_FACES_0:
1883 case RADEON_PP_CUBIC_FACES_1:
1884 case RADEON_PP_CUBIC_FACES_2:
1885 tmp = idx_value;
1886 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1887 for (face = 0; face < 4; face++) {
1888 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1889 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1890 }
1891 track->tex_dirty = true;
1892 break;
1893 default:
1894 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);
1895 return -EINVAL;
1896 }
1897 return 0;
1898}
1899
1900int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1901 struct radeon_cs_packet *pkt,
1902 struct radeon_bo *robj)
1903{
1904 unsigned idx;
1905 u32 value;
1906 idx = pkt->idx + 1;
1907 value = radeon_get_ib_value(p, idx + 2);
1908 if ((value + 1) > radeon_bo_size(robj)) {
1909 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1910 "(need %u have %lu) !\n",
1911 value + 1,
1912 radeon_bo_size(robj));
1913 return -EINVAL;
1914 }
1915 return 0;
1916}
1917
1918static int r100_packet3_check(struct radeon_cs_parser *p,
1919 struct radeon_cs_packet *pkt)
1920{
1921 struct radeon_bo_list *reloc;
1922 struct r100_cs_track *track;
1923 unsigned idx;
1924 volatile uint32_t *ib;
1925 int r;
1926
1927 ib = p->ib.ptr;
1928 idx = pkt->idx + 1;
1929 track = (struct r100_cs_track *)p->track;
1930 switch (pkt->opcode) {
1931 case PACKET3_3D_LOAD_VBPNTR:
1932 r = r100_packet3_load_vbpntr(p, pkt, idx);
1933 if (r)
1934 return r;
1935 break;
1936 case PACKET3_INDX_BUFFER:
1937 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1938 if (r) {
1939 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1940 radeon_cs_dump_packet(p, pkt);
1941 return r;
1942 }
1943 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
1944 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1945 if (r) {
1946 return r;
1947 }
1948 break;
1949 case 0x23:
1950 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1951 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1952 if (r) {
1953 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1954 radeon_cs_dump_packet(p, pkt);
1955 return r;
1956 }
1957 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
1958 track->num_arrays = 1;
1959 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1960
1961 track->arrays[0].robj = reloc->robj;
1962 track->arrays[0].esize = track->vtx_size;
1963
1964 track->max_indx = radeon_get_ib_value(p, idx+1);
1965
1966 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1967 track->immd_dwords = pkt->count - 1;
1968 r = r100_cs_track_check(p->rdev, track);
1969 if (r)
1970 return r;
1971 break;
1972 case PACKET3_3D_DRAW_IMMD:
1973 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1974 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1975 return -EINVAL;
1976 }
1977 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1978 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1979 track->immd_dwords = pkt->count - 1;
1980 r = r100_cs_track_check(p->rdev, track);
1981 if (r)
1982 return r;
1983 break;
1984 /* triggers drawing using in-packet vertex data */
1985 case PACKET3_3D_DRAW_IMMD_2:
1986 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1987 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1988 return -EINVAL;
1989 }
1990 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1991 track->immd_dwords = pkt->count;
1992 r = r100_cs_track_check(p->rdev, track);
1993 if (r)
1994 return r;
1995 break;
1996 /* triggers drawing using in-packet vertex data */
1997 case PACKET3_3D_DRAW_VBUF_2:
1998 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1999 r = r100_cs_track_check(p->rdev, track);
2000 if (r)
2001 return r;
2002 break;
2003 /* triggers drawing of vertex buffers setup elsewhere */
2004 case PACKET3_3D_DRAW_INDX_2:
2005 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2006 r = r100_cs_track_check(p->rdev, track);
2007 if (r)
2008 return r;
2009 break;
2010 /* triggers drawing using indices to vertex buffer */
2011 case PACKET3_3D_DRAW_VBUF:
2012 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2013 r = r100_cs_track_check(p->rdev, track);
2014 if (r)
2015 return r;
2016 break;
2017 /* triggers drawing of vertex buffers setup elsewhere */
2018 case PACKET3_3D_DRAW_INDX:
2019 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2020 r = r100_cs_track_check(p->rdev, track);
2021 if (r)
2022 return r;
2023 break;
2024 /* triggers drawing using indices to vertex buffer */
2025 case PACKET3_3D_CLEAR_HIZ:
2026 case PACKET3_3D_CLEAR_ZMASK:
2027 if (p->rdev->hyperz_filp != p->filp)
2028 return -EINVAL;
2029 break;
2030 case PACKET3_NOP:
2031 break;
2032 default:
2033 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2034 return -EINVAL;
2035 }
2036 return 0;
2037}
2038
2039int r100_cs_parse(struct radeon_cs_parser *p)
2040{
2041 struct radeon_cs_packet pkt;
2042 struct r100_cs_track *track;
2043 int r;
2044
2045 track = kzalloc(sizeof(*track), GFP_KERNEL);
2046 if (!track)
2047 return -ENOMEM;
2048 r100_cs_track_clear(p->rdev, track);
2049 p->track = track;
2050 do {
2051 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2052 if (r) {
2053 return r;
2054 }
2055 p->idx += pkt.count + 2;
2056 switch (pkt.type) {
2057 case RADEON_PACKET_TYPE0:
2058 if (p->rdev->family >= CHIP_R200)
2059 r = r100_cs_parse_packet0(p, &pkt,
2060 p->rdev->config.r100.reg_safe_bm,
2061 p->rdev->config.r100.reg_safe_bm_size,
2062 &r200_packet0_check);
2063 else
2064 r = r100_cs_parse_packet0(p, &pkt,
2065 p->rdev->config.r100.reg_safe_bm,
2066 p->rdev->config.r100.reg_safe_bm_size,
2067 &r100_packet0_check);
2068 break;
2069 case RADEON_PACKET_TYPE2:
2070 break;
2071 case RADEON_PACKET_TYPE3:
2072 r = r100_packet3_check(p, &pkt);
2073 break;
2074 default:
2075 DRM_ERROR("Unknown packet type %d !\n",
2076 pkt.type);
2077 return -EINVAL;
2078 }
2079 if (r)
2080 return r;
2081 } while (p->idx < p->chunk_ib->length_dw);
2082 return 0;
2083}
2084
2085static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2086{
2087 DRM_ERROR("pitch %d\n", t->pitch);
2088 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2089 DRM_ERROR("width %d\n", t->width);
2090 DRM_ERROR("width_11 %d\n", t->width_11);
2091 DRM_ERROR("height %d\n", t->height);
2092 DRM_ERROR("height_11 %d\n", t->height_11);
2093 DRM_ERROR("num levels %d\n", t->num_levels);
2094 DRM_ERROR("depth %d\n", t->txdepth);
2095 DRM_ERROR("bpp %d\n", t->cpp);
2096 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2097 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2098 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2099 DRM_ERROR("compress format %d\n", t->compress_format);
2100}
2101
2102static int r100_track_compress_size(int compress_format, int w, int h)
2103{
2104 int block_width, block_height, block_bytes;
2105 int wblocks, hblocks;
2106 int min_wblocks;
2107 int sz;
2108
2109 block_width = 4;
2110 block_height = 4;
2111
2112 switch (compress_format) {
2113 case R100_TRACK_COMP_DXT1:
2114 block_bytes = 8;
2115 min_wblocks = 4;
2116 break;
2117 default:
2118 case R100_TRACK_COMP_DXT35:
2119 block_bytes = 16;
2120 min_wblocks = 2;
2121 break;
2122 }
2123
2124 hblocks = (h + block_height - 1) / block_height;
2125 wblocks = (w + block_width - 1) / block_width;
2126 if (wblocks < min_wblocks)
2127 wblocks = min_wblocks;
2128 sz = wblocks * hblocks * block_bytes;
2129 return sz;
2130}
2131
2132static int r100_cs_track_cube(struct radeon_device *rdev,
2133 struct r100_cs_track *track, unsigned idx)
2134{
2135 unsigned face, w, h;
2136 struct radeon_bo *cube_robj;
2137 unsigned long size;
2138 unsigned compress_format = track->textures[idx].compress_format;
2139
2140 for (face = 0; face < 5; face++) {
2141 cube_robj = track->textures[idx].cube_info[face].robj;
2142 w = track->textures[idx].cube_info[face].width;
2143 h = track->textures[idx].cube_info[face].height;
2144
2145 if (compress_format) {
2146 size = r100_track_compress_size(compress_format, w, h);
2147 } else
2148 size = w * h;
2149 size *= track->textures[idx].cpp;
2150
2151 size += track->textures[idx].cube_info[face].offset;
2152
2153 if (size > radeon_bo_size(cube_robj)) {
2154 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2155 size, radeon_bo_size(cube_robj));
2156 r100_cs_track_texture_print(&track->textures[idx]);
2157 return -1;
2158 }
2159 }
2160 return 0;
2161}
2162
2163static int r100_cs_track_texture_check(struct radeon_device *rdev,
2164 struct r100_cs_track *track)
2165{
2166 struct radeon_bo *robj;
2167 unsigned long size;
2168 unsigned u, i, w, h, d;
2169 int ret;
2170
2171 for (u = 0; u < track->num_texture; u++) {
2172 if (!track->textures[u].enabled)
2173 continue;
2174 if (track->textures[u].lookup_disable)
2175 continue;
2176 robj = track->textures[u].robj;
2177 if (robj == NULL) {
2178 DRM_ERROR("No texture bound to unit %u\n", u);
2179 return -EINVAL;
2180 }
2181 size = 0;
2182 for (i = 0; i <= track->textures[u].num_levels; i++) {
2183 if (track->textures[u].use_pitch) {
2184 if (rdev->family < CHIP_R300)
2185 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2186 else
2187 w = track->textures[u].pitch / (1 << i);
2188 } else {
2189 w = track->textures[u].width;
2190 if (rdev->family >= CHIP_RV515)
2191 w |= track->textures[u].width_11;
2192 w = w / (1 << i);
2193 if (track->textures[u].roundup_w)
2194 w = roundup_pow_of_two(w);
2195 }
2196 h = track->textures[u].height;
2197 if (rdev->family >= CHIP_RV515)
2198 h |= track->textures[u].height_11;
2199 h = h / (1 << i);
2200 if (track->textures[u].roundup_h)
2201 h = roundup_pow_of_two(h);
2202 if (track->textures[u].tex_coord_type == 1) {
2203 d = (1 << track->textures[u].txdepth) / (1 << i);
2204 if (!d)
2205 d = 1;
2206 } else {
2207 d = 1;
2208 }
2209 if (track->textures[u].compress_format) {
2210
2211 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2212 /* compressed textures are block based */
2213 } else
2214 size += w * h * d;
2215 }
2216 size *= track->textures[u].cpp;
2217
2218 switch (track->textures[u].tex_coord_type) {
2219 case 0:
2220 case 1:
2221 break;
2222 case 2:
2223 if (track->separate_cube) {
2224 ret = r100_cs_track_cube(rdev, track, u);
2225 if (ret)
2226 return ret;
2227 } else
2228 size *= 6;
2229 break;
2230 default:
2231 DRM_ERROR("Invalid texture coordinate type %u for unit "
2232 "%u\n", track->textures[u].tex_coord_type, u);
2233 return -EINVAL;
2234 }
2235 if (size > radeon_bo_size(robj)) {
2236 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2237 "%lu\n", u, size, radeon_bo_size(robj));
2238 r100_cs_track_texture_print(&track->textures[u]);
2239 return -EINVAL;
2240 }
2241 }
2242 return 0;
2243}
2244
2245int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2246{
2247 unsigned i;
2248 unsigned long size;
2249 unsigned prim_walk;
2250 unsigned nverts;
2251 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2252
2253 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2254 !track->blend_read_enable)
2255 num_cb = 0;
2256
2257 for (i = 0; i < num_cb; i++) {
2258 if (track->cb[i].robj == NULL) {
2259 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2260 return -EINVAL;
2261 }
2262 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2263 size += track->cb[i].offset;
2264 if (size > radeon_bo_size(track->cb[i].robj)) {
2265 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2266 "(need %lu have %lu) !\n", i, size,
2267 radeon_bo_size(track->cb[i].robj));
2268 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2269 i, track->cb[i].pitch, track->cb[i].cpp,
2270 track->cb[i].offset, track->maxy);
2271 return -EINVAL;
2272 }
2273 }
2274 track->cb_dirty = false;
2275
2276 if (track->zb_dirty && track->z_enabled) {
2277 if (track->zb.robj == NULL) {
2278 DRM_ERROR("[drm] No buffer for z buffer !\n");
2279 return -EINVAL;
2280 }
2281 size = track->zb.pitch * track->zb.cpp * track->maxy;
2282 size += track->zb.offset;
2283 if (size > radeon_bo_size(track->zb.robj)) {
2284 DRM_ERROR("[drm] Buffer too small for z buffer "
2285 "(need %lu have %lu) !\n", size,
2286 radeon_bo_size(track->zb.robj));
2287 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2288 track->zb.pitch, track->zb.cpp,
2289 track->zb.offset, track->maxy);
2290 return -EINVAL;
2291 }
2292 }
2293 track->zb_dirty = false;
2294
2295 if (track->aa_dirty && track->aaresolve) {
2296 if (track->aa.robj == NULL) {
2297 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2298 return -EINVAL;
2299 }
2300 /* I believe the format comes from colorbuffer0. */
2301 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2302 size += track->aa.offset;
2303 if (size > radeon_bo_size(track->aa.robj)) {
2304 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2305 "(need %lu have %lu) !\n", i, size,
2306 radeon_bo_size(track->aa.robj));
2307 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2308 i, track->aa.pitch, track->cb[0].cpp,
2309 track->aa.offset, track->maxy);
2310 return -EINVAL;
2311 }
2312 }
2313 track->aa_dirty = false;
2314
2315 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2316 if (track->vap_vf_cntl & (1 << 14)) {
2317 nverts = track->vap_alt_nverts;
2318 } else {
2319 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2320 }
2321 switch (prim_walk) {
2322 case 1:
2323 for (i = 0; i < track->num_arrays; i++) {
2324 size = track->arrays[i].esize * track->max_indx * 4UL;
2325 if (track->arrays[i].robj == NULL) {
2326 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2327 "bound\n", prim_walk, i);
2328 return -EINVAL;
2329 }
2330 if (size > radeon_bo_size(track->arrays[i].robj)) {
2331 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2332 "need %lu dwords have %lu dwords\n",
2333 prim_walk, i, size >> 2,
2334 radeon_bo_size(track->arrays[i].robj)
2335 >> 2);
2336 DRM_ERROR("Max indices %u\n", track->max_indx);
2337 return -EINVAL;
2338 }
2339 }
2340 break;
2341 case 2:
2342 for (i = 0; i < track->num_arrays; i++) {
2343 size = track->arrays[i].esize * (nverts - 1) * 4UL;
2344 if (track->arrays[i].robj == NULL) {
2345 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2346 "bound\n", prim_walk, i);
2347 return -EINVAL;
2348 }
2349 if (size > radeon_bo_size(track->arrays[i].robj)) {
2350 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2351 "need %lu dwords have %lu dwords\n",
2352 prim_walk, i, size >> 2,
2353 radeon_bo_size(track->arrays[i].robj)
2354 >> 2);
2355 return -EINVAL;
2356 }
2357 }
2358 break;
2359 case 3:
2360 size = track->vtx_size * nverts;
2361 if (size != track->immd_dwords) {
2362 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2363 track->immd_dwords, size);
2364 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2365 nverts, track->vtx_size);
2366 return -EINVAL;
2367 }
2368 break;
2369 default:
2370 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2371 prim_walk);
2372 return -EINVAL;
2373 }
2374
2375 if (track->tex_dirty) {
2376 track->tex_dirty = false;
2377 return r100_cs_track_texture_check(rdev, track);
2378 }
2379 return 0;
2380}
2381
2382void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2383{
2384 unsigned i, face;
2385
2386 track->cb_dirty = true;
2387 track->zb_dirty = true;
2388 track->tex_dirty = true;
2389 track->aa_dirty = true;
2390
2391 if (rdev->family < CHIP_R300) {
2392 track->num_cb = 1;
2393 if (rdev->family <= CHIP_RS200)
2394 track->num_texture = 3;
2395 else
2396 track->num_texture = 6;
2397 track->maxy = 2048;
2398 track->separate_cube = true;
2399 } else {
2400 track->num_cb = 4;
2401 track->num_texture = 16;
2402 track->maxy = 4096;
2403 track->separate_cube = false;
2404 track->aaresolve = false;
2405 track->aa.robj = NULL;
2406 }
2407
2408 for (i = 0; i < track->num_cb; i++) {
2409 track->cb[i].robj = NULL;
2410 track->cb[i].pitch = 8192;
2411 track->cb[i].cpp = 16;
2412 track->cb[i].offset = 0;
2413 }
2414 track->z_enabled = true;
2415 track->zb.robj = NULL;
2416 track->zb.pitch = 8192;
2417 track->zb.cpp = 4;
2418 track->zb.offset = 0;
2419 track->vtx_size = 0x7F;
2420 track->immd_dwords = 0xFFFFFFFFUL;
2421 track->num_arrays = 11;
2422 track->max_indx = 0x00FFFFFFUL;
2423 for (i = 0; i < track->num_arrays; i++) {
2424 track->arrays[i].robj = NULL;
2425 track->arrays[i].esize = 0x7F;
2426 }
2427 for (i = 0; i < track->num_texture; i++) {
2428 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2429 track->textures[i].pitch = 16536;
2430 track->textures[i].width = 16536;
2431 track->textures[i].height = 16536;
2432 track->textures[i].width_11 = 1 << 11;
2433 track->textures[i].height_11 = 1 << 11;
2434 track->textures[i].num_levels = 12;
2435 if (rdev->family <= CHIP_RS200) {
2436 track->textures[i].tex_coord_type = 0;
2437 track->textures[i].txdepth = 0;
2438 } else {
2439 track->textures[i].txdepth = 16;
2440 track->textures[i].tex_coord_type = 1;
2441 }
2442 track->textures[i].cpp = 64;
2443 track->textures[i].robj = NULL;
2444 /* CS IB emission code makes sure texture unit are disabled */
2445 track->textures[i].enabled = false;
2446 track->textures[i].lookup_disable = false;
2447 track->textures[i].roundup_w = true;
2448 track->textures[i].roundup_h = true;
2449 if (track->separate_cube)
2450 for (face = 0; face < 5; face++) {
2451 track->textures[i].cube_info[face].robj = NULL;
2452 track->textures[i].cube_info[face].width = 16536;
2453 track->textures[i].cube_info[face].height = 16536;
2454 track->textures[i].cube_info[face].offset = 0;
2455 }
2456 }
2457}
2458
2459/*
2460 * Global GPU functions
2461 */
2462static void r100_errata(struct radeon_device *rdev)
2463{
2464 rdev->pll_errata = 0;
2465
2466 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2467 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2468 }
2469
2470 if (rdev->family == CHIP_RV100 ||
2471 rdev->family == CHIP_RS100 ||
2472 rdev->family == CHIP_RS200) {
2473 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2474 }
2475}
2476
2477static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2478{
2479 unsigned i;
2480 uint32_t tmp;
2481
2482 for (i = 0; i < rdev->usec_timeout; i++) {
2483 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2484 if (tmp >= n) {
2485 return 0;
2486 }
2487 udelay(1);
2488 }
2489 return -1;
2490}
2491
2492int r100_gui_wait_for_idle(struct radeon_device *rdev)
2493{
2494 unsigned i;
2495 uint32_t tmp;
2496
2497 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2498 pr_warn("radeon: wait for empty RBBM fifo failed! Bad things might happen.\n");
2499 }
2500 for (i = 0; i < rdev->usec_timeout; i++) {
2501 tmp = RREG32(RADEON_RBBM_STATUS);
2502 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2503 return 0;
2504 }
2505 udelay(1);
2506 }
2507 return -1;
2508}
2509
2510int r100_mc_wait_for_idle(struct radeon_device *rdev)
2511{
2512 unsigned i;
2513 uint32_t tmp;
2514
2515 for (i = 0; i < rdev->usec_timeout; i++) {
2516 /* read MC_STATUS */
2517 tmp = RREG32(RADEON_MC_STATUS);
2518 if (tmp & RADEON_MC_IDLE) {
2519 return 0;
2520 }
2521 udelay(1);
2522 }
2523 return -1;
2524}
2525
2526bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2527{
2528 u32 rbbm_status;
2529
2530 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2531 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2532 radeon_ring_lockup_update(rdev, ring);
2533 return false;
2534 }
2535 return radeon_ring_test_lockup(rdev, ring);
2536}
2537
2538/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2539void r100_enable_bm(struct radeon_device *rdev)
2540{
2541 uint32_t tmp;
2542 /* Enable bus mastering */
2543 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2544 WREG32(RADEON_BUS_CNTL, tmp);
2545}
2546
2547void r100_bm_disable(struct radeon_device *rdev)
2548{
2549 u32 tmp;
2550
2551 /* disable bus mastering */
2552 tmp = RREG32(R_000030_BUS_CNTL);
2553 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2554 mdelay(1);
2555 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2556 mdelay(1);
2557 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2558 tmp = RREG32(RADEON_BUS_CNTL);
2559 mdelay(1);
2560 pci_clear_master(rdev->pdev);
2561 mdelay(1);
2562}
2563
2564int r100_asic_reset(struct radeon_device *rdev, bool hard)
2565{
2566 struct r100_mc_save save;
2567 u32 status, tmp;
2568 int ret = 0;
2569
2570 status = RREG32(R_000E40_RBBM_STATUS);
2571 if (!G_000E40_GUI_ACTIVE(status)) {
2572 return 0;
2573 }
2574 r100_mc_stop(rdev, &save);
2575 status = RREG32(R_000E40_RBBM_STATUS);
2576 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2577 /* stop CP */
2578 WREG32(RADEON_CP_CSQ_CNTL, 0);
2579 tmp = RREG32(RADEON_CP_RB_CNTL);
2580 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2581 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2582 WREG32(RADEON_CP_RB_WPTR, 0);
2583 WREG32(RADEON_CP_RB_CNTL, tmp);
2584 /* save PCI state */
2585 pci_save_state(rdev->pdev);
2586 /* disable bus mastering */
2587 r100_bm_disable(rdev);
2588 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2589 S_0000F0_SOFT_RESET_RE(1) |
2590 S_0000F0_SOFT_RESET_PP(1) |
2591 S_0000F0_SOFT_RESET_RB(1));
2592 RREG32(R_0000F0_RBBM_SOFT_RESET);
2593 mdelay(500);
2594 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2595 mdelay(1);
2596 status = RREG32(R_000E40_RBBM_STATUS);
2597 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2598 /* reset CP */
2599 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2600 RREG32(R_0000F0_RBBM_SOFT_RESET);
2601 mdelay(500);
2602 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2603 mdelay(1);
2604 status = RREG32(R_000E40_RBBM_STATUS);
2605 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2606 /* restore PCI & busmastering */
2607 pci_restore_state(rdev->pdev);
2608 r100_enable_bm(rdev);
2609 /* Check if GPU is idle */
2610 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2611 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2612 dev_err(rdev->dev, "failed to reset GPU\n");
2613 ret = -1;
2614 } else
2615 dev_info(rdev->dev, "GPU reset succeed\n");
2616 r100_mc_resume(rdev, &save);
2617 return ret;
2618}
2619
2620void r100_set_common_regs(struct radeon_device *rdev)
2621{
2622 bool force_dac2 = false;
2623 u32 tmp;
2624
2625 /* set these so they don't interfere with anything */
2626 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2627 WREG32(RADEON_SUBPIC_CNTL, 0);
2628 WREG32(RADEON_VIPH_CONTROL, 0);
2629 WREG32(RADEON_I2C_CNTL_1, 0);
2630 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2631 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2632 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2633
2634 /* always set up dac2 on rn50 and some rv100 as lots
2635 * of servers seem to wire it up to a VGA port but
2636 * don't report it in the bios connector
2637 * table.
2638 */
2639 switch (rdev->pdev->device) {
2640 /* RN50 */
2641 case 0x515e:
2642 case 0x5969:
2643 force_dac2 = true;
2644 break;
2645 /* RV100*/
2646 case 0x5159:
2647 case 0x515a:
2648 /* DELL triple head servers */
2649 if ((rdev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2650 ((rdev->pdev->subsystem_device == 0x016c) ||
2651 (rdev->pdev->subsystem_device == 0x016d) ||
2652 (rdev->pdev->subsystem_device == 0x016e) ||
2653 (rdev->pdev->subsystem_device == 0x016f) ||
2654 (rdev->pdev->subsystem_device == 0x0170) ||
2655 (rdev->pdev->subsystem_device == 0x017d) ||
2656 (rdev->pdev->subsystem_device == 0x017e) ||
2657 (rdev->pdev->subsystem_device == 0x0183) ||
2658 (rdev->pdev->subsystem_device == 0x018a) ||
2659 (rdev->pdev->subsystem_device == 0x019a)))
2660 force_dac2 = true;
2661 break;
2662 }
2663
2664 if (force_dac2) {
2665 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2666 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2667 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2668
2669 /* For CRT on DAC2, don't turn it on if BIOS didn't
2670 enable it, even it's detected.
2671 */
2672
2673 /* force it to crtc0 */
2674 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2675 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2676 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2677
2678 /* set up the TV DAC */
2679 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2680 RADEON_TV_DAC_STD_MASK |
2681 RADEON_TV_DAC_RDACPD |
2682 RADEON_TV_DAC_GDACPD |
2683 RADEON_TV_DAC_BDACPD |
2684 RADEON_TV_DAC_BGADJ_MASK |
2685 RADEON_TV_DAC_DACADJ_MASK);
2686 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2687 RADEON_TV_DAC_NHOLD |
2688 RADEON_TV_DAC_STD_PS2 |
2689 (0x58 << 16));
2690
2691 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2692 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2693 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2694 }
2695
2696 /* switch PM block to ACPI mode */
2697 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2698 tmp &= ~RADEON_PM_MODE_SEL;
2699 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2700
2701}
2702
2703/*
2704 * VRAM info
2705 */
2706static void r100_vram_get_type(struct radeon_device *rdev)
2707{
2708 uint32_t tmp;
2709
2710 rdev->mc.vram_is_ddr = false;
2711 if (rdev->flags & RADEON_IS_IGP)
2712 rdev->mc.vram_is_ddr = true;
2713 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2714 rdev->mc.vram_is_ddr = true;
2715 if ((rdev->family == CHIP_RV100) ||
2716 (rdev->family == CHIP_RS100) ||
2717 (rdev->family == CHIP_RS200)) {
2718 tmp = RREG32(RADEON_MEM_CNTL);
2719 if (tmp & RV100_HALF_MODE) {
2720 rdev->mc.vram_width = 32;
2721 } else {
2722 rdev->mc.vram_width = 64;
2723 }
2724 if (rdev->flags & RADEON_SINGLE_CRTC) {
2725 rdev->mc.vram_width /= 4;
2726 rdev->mc.vram_is_ddr = true;
2727 }
2728 } else if (rdev->family <= CHIP_RV280) {
2729 tmp = RREG32(RADEON_MEM_CNTL);
2730 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2731 rdev->mc.vram_width = 128;
2732 } else {
2733 rdev->mc.vram_width = 64;
2734 }
2735 } else {
2736 /* newer IGPs */
2737 rdev->mc.vram_width = 128;
2738 }
2739}
2740
2741static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2742{
2743 u32 aper_size;
2744 u8 byte;
2745
2746 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2747
2748 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2749 * that is has the 2nd generation multifunction PCI interface
2750 */
2751 if (rdev->family == CHIP_RV280 ||
2752 rdev->family >= CHIP_RV350) {
2753 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2754 ~RADEON_HDP_APER_CNTL);
2755 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2756 return aper_size * 2;
2757 }
2758
2759 /* Older cards have all sorts of funny issues to deal with. First
2760 * check if it's a multifunction card by reading the PCI config
2761 * header type... Limit those to one aperture size
2762 */
2763 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2764 if (byte & 0x80) {
2765 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2766 DRM_INFO("Limiting VRAM to one aperture\n");
2767 return aper_size;
2768 }
2769
2770 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2771 * have set it up. We don't write this as it's broken on some ASICs but
2772 * we expect the BIOS to have done the right thing (might be too optimistic...)
2773 */
2774 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2775 return aper_size * 2;
2776 return aper_size;
2777}
2778
2779void r100_vram_init_sizes(struct radeon_device *rdev)
2780{
2781 u64 config_aper_size;
2782
2783 /* work out accessible VRAM */
2784 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2785 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2786 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2787 /* FIXME we don't use the second aperture yet when we could use it */
2788 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2789 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2790 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2791 if (rdev->flags & RADEON_IS_IGP) {
2792 uint32_t tom;
2793 /* read NB_TOM to get the amount of ram stolen for the GPU */
2794 tom = RREG32(RADEON_NB_TOM);
2795 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2796 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2797 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2798 } else {
2799 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2800 /* Some production boards of m6 will report 0
2801 * if it's 8 MB
2802 */
2803 if (rdev->mc.real_vram_size == 0) {
2804 rdev->mc.real_vram_size = 8192 * 1024;
2805 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2806 }
2807 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2808 * Novell bug 204882 + along with lots of ubuntu ones
2809 */
2810 if (rdev->mc.aper_size > config_aper_size)
2811 config_aper_size = rdev->mc.aper_size;
2812
2813 if (config_aper_size > rdev->mc.real_vram_size)
2814 rdev->mc.mc_vram_size = config_aper_size;
2815 else
2816 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2817 }
2818}
2819
2820void r100_vga_set_state(struct radeon_device *rdev, bool state)
2821{
2822 uint32_t temp;
2823
2824 temp = RREG32(RADEON_CONFIG_CNTL);
2825 if (!state) {
2826 temp &= ~RADEON_CFG_VGA_RAM_EN;
2827 temp |= RADEON_CFG_VGA_IO_DIS;
2828 } else {
2829 temp &= ~RADEON_CFG_VGA_IO_DIS;
2830 }
2831 WREG32(RADEON_CONFIG_CNTL, temp);
2832}
2833
2834static void r100_mc_init(struct radeon_device *rdev)
2835{
2836 u64 base;
2837
2838 r100_vram_get_type(rdev);
2839 r100_vram_init_sizes(rdev);
2840 base = rdev->mc.aper_base;
2841 if (rdev->flags & RADEON_IS_IGP)
2842 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2843 radeon_vram_location(rdev, &rdev->mc, base);
2844 rdev->mc.gtt_base_align = 0;
2845 if (!(rdev->flags & RADEON_IS_AGP))
2846 radeon_gtt_location(rdev, &rdev->mc);
2847 radeon_update_bandwidth_info(rdev);
2848}
2849
2850
2851/*
2852 * Indirect registers accessor
2853 */
2854void r100_pll_errata_after_index(struct radeon_device *rdev)
2855{
2856 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2857 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2858 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2859 }
2860}
2861
2862static void r100_pll_errata_after_data(struct radeon_device *rdev)
2863{
2864 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2865 * or the chip could hang on a subsequent access
2866 */
2867 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2868 mdelay(5);
2869 }
2870
2871 /* This function is required to workaround a hardware bug in some (all?)
2872 * revisions of the R300. This workaround should be called after every
2873 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2874 * may not be correct.
2875 */
2876 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2877 uint32_t save, tmp;
2878
2879 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2880 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2881 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2882 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2883 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2884 }
2885}
2886
2887uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2888{
2889 unsigned long flags;
2890 uint32_t data;
2891
2892 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2893 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2894 r100_pll_errata_after_index(rdev);
2895 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2896 r100_pll_errata_after_data(rdev);
2897 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2898 return data;
2899}
2900
2901void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2902{
2903 unsigned long flags;
2904
2905 spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2906 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2907 r100_pll_errata_after_index(rdev);
2908 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2909 r100_pll_errata_after_data(rdev);
2910 spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2911}
2912
2913static void r100_set_safe_registers(struct radeon_device *rdev)
2914{
2915 if (ASIC_IS_RN50(rdev)) {
2916 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2917 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2918 } else if (rdev->family < CHIP_R200) {
2919 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2920 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2921 } else {
2922 r200_set_safe_registers(rdev);
2923 }
2924}
2925
2926/*
2927 * Debugfs info
2928 */
2929#if defined(CONFIG_DEBUG_FS)
2930static int r100_debugfs_rbbm_info_show(struct seq_file *m, void *unused)
2931{
2932 struct radeon_device *rdev = m->private;
2933 uint32_t reg, value;
2934 unsigned i;
2935
2936 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2937 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2938 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2939 for (i = 0; i < 64; i++) {
2940 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2941 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2942 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2943 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2944 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2945 }
2946 return 0;
2947}
2948
2949static int r100_debugfs_cp_ring_info_show(struct seq_file *m, void *unused)
2950{
2951 struct radeon_device *rdev = m->private;
2952 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2953 uint32_t rdp, wdp;
2954 unsigned count, i, j;
2955
2956 radeon_ring_free_size(rdev, ring);
2957 rdp = RREG32(RADEON_CP_RB_RPTR);
2958 wdp = RREG32(RADEON_CP_RB_WPTR);
2959 count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2960 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2961 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2962 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2963 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2964 seq_printf(m, "%u dwords in ring\n", count);
2965 if (ring->ready) {
2966 for (j = 0; j <= count; j++) {
2967 i = (rdp + j) & ring->ptr_mask;
2968 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2969 }
2970 }
2971 return 0;
2972}
2973
2974
2975static int r100_debugfs_cp_csq_fifo_show(struct seq_file *m, void *unused)
2976{
2977 struct radeon_device *rdev = m->private;
2978 uint32_t csq_stat, csq2_stat, tmp;
2979 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2980 unsigned i;
2981
2982 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2983 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2984 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2985 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2986 r_rptr = (csq_stat >> 0) & 0x3ff;
2987 r_wptr = (csq_stat >> 10) & 0x3ff;
2988 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2989 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2990 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2991 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2992 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2993 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2994 seq_printf(m, "Ring rptr %u\n", r_rptr);
2995 seq_printf(m, "Ring wptr %u\n", r_wptr);
2996 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2997 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2998 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2999 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
3000 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
3001 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
3002 seq_printf(m, "Ring fifo:\n");
3003 for (i = 0; i < 256; i++) {
3004 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3005 tmp = RREG32(RADEON_CP_CSQ_DATA);
3006 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3007 }
3008 seq_printf(m, "Indirect1 fifo:\n");
3009 for (i = 256; i <= 512; i++) {
3010 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3011 tmp = RREG32(RADEON_CP_CSQ_DATA);
3012 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3013 }
3014 seq_printf(m, "Indirect2 fifo:\n");
3015 for (i = 640; i < ib1_wptr; i++) {
3016 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3017 tmp = RREG32(RADEON_CP_CSQ_DATA);
3018 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3019 }
3020 return 0;
3021}
3022
3023static int r100_debugfs_mc_info_show(struct seq_file *m, void *unused)
3024{
3025 struct radeon_device *rdev = m->private;
3026 uint32_t tmp;
3027
3028 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3029 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3030 tmp = RREG32(RADEON_MC_FB_LOCATION);
3031 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3032 tmp = RREG32(RADEON_BUS_CNTL);
3033 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3034 tmp = RREG32(RADEON_MC_AGP_LOCATION);
3035 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3036 tmp = RREG32(RADEON_AGP_BASE);
3037 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3038 tmp = RREG32(RADEON_HOST_PATH_CNTL);
3039 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3040 tmp = RREG32(0x01D0);
3041 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3042 tmp = RREG32(RADEON_AIC_LO_ADDR);
3043 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3044 tmp = RREG32(RADEON_AIC_HI_ADDR);
3045 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3046 tmp = RREG32(0x01E4);
3047 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3048 return 0;
3049}
3050
3051DEFINE_SHOW_ATTRIBUTE(r100_debugfs_rbbm_info);
3052DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_ring_info);
3053DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_csq_fifo);
3054DEFINE_SHOW_ATTRIBUTE(r100_debugfs_mc_info);
3055
3056#endif
3057
3058void r100_debugfs_rbbm_init(struct radeon_device *rdev)
3059{
3060#if defined(CONFIG_DEBUG_FS)
3061 struct dentry *root = rdev->ddev->primary->debugfs_root;
3062
3063 debugfs_create_file("r100_rbbm_info", 0444, root, rdev,
3064 &r100_debugfs_rbbm_info_fops);
3065#endif
3066}
3067
3068void r100_debugfs_cp_init(struct radeon_device *rdev)
3069{
3070#if defined(CONFIG_DEBUG_FS)
3071 struct dentry *root = rdev->ddev->primary->debugfs_root;
3072
3073 debugfs_create_file("r100_cp_ring_info", 0444, root, rdev,
3074 &r100_debugfs_cp_ring_info_fops);
3075 debugfs_create_file("r100_cp_csq_fifo", 0444, root, rdev,
3076 &r100_debugfs_cp_csq_fifo_fops);
3077#endif
3078}
3079
3080void r100_debugfs_mc_info_init(struct radeon_device *rdev)
3081{
3082#if defined(CONFIG_DEBUG_FS)
3083 struct dentry *root = rdev->ddev->primary->debugfs_root;
3084
3085 debugfs_create_file("r100_mc_info", 0444, root, rdev,
3086 &r100_debugfs_mc_info_fops);
3087#endif
3088}
3089
3090int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3091 uint32_t tiling_flags, uint32_t pitch,
3092 uint32_t offset, uint32_t obj_size)
3093{
3094 int surf_index = reg * 16;
3095 int flags = 0;
3096
3097 if (rdev->family <= CHIP_RS200) {
3098 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3099 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3100 flags |= RADEON_SURF_TILE_COLOR_BOTH;
3101 if (tiling_flags & RADEON_TILING_MACRO)
3102 flags |= RADEON_SURF_TILE_COLOR_MACRO;
3103 /* setting pitch to 0 disables tiling */
3104 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3105 == 0)
3106 pitch = 0;
3107 } else if (rdev->family <= CHIP_RV280) {
3108 if (tiling_flags & (RADEON_TILING_MACRO))
3109 flags |= R200_SURF_TILE_COLOR_MACRO;
3110 if (tiling_flags & RADEON_TILING_MICRO)
3111 flags |= R200_SURF_TILE_COLOR_MICRO;
3112 } else {
3113 if (tiling_flags & RADEON_TILING_MACRO)
3114 flags |= R300_SURF_TILE_MACRO;
3115 if (tiling_flags & RADEON_TILING_MICRO)
3116 flags |= R300_SURF_TILE_MICRO;
3117 }
3118
3119 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3120 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3121 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3122 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3123
3124 /* r100/r200 divide by 16 */
3125 if (rdev->family < CHIP_R300)
3126 flags |= pitch / 16;
3127 else
3128 flags |= pitch / 8;
3129
3130
3131 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3132 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3133 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3134 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3135 return 0;
3136}
3137
3138void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3139{
3140 int surf_index = reg * 16;
3141 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3142}
3143
3144void r100_bandwidth_update(struct radeon_device *rdev)
3145{
3146 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3147 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3148 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff;
3149 fixed20_12 crit_point_ff = {0};
3150 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3151 fixed20_12 memtcas_ff[8] = {
3152 dfixed_init(1),
3153 dfixed_init(2),
3154 dfixed_init(3),
3155 dfixed_init(0),
3156 dfixed_init_half(1),
3157 dfixed_init_half(2),
3158 dfixed_init(0),
3159 };
3160 fixed20_12 memtcas_rs480_ff[8] = {
3161 dfixed_init(0),
3162 dfixed_init(1),
3163 dfixed_init(2),
3164 dfixed_init(3),
3165 dfixed_init(0),
3166 dfixed_init_half(1),
3167 dfixed_init_half(2),
3168 dfixed_init_half(3),
3169 };
3170 fixed20_12 memtcas2_ff[8] = {
3171 dfixed_init(0),
3172 dfixed_init(1),
3173 dfixed_init(2),
3174 dfixed_init(3),
3175 dfixed_init(4),
3176 dfixed_init(5),
3177 dfixed_init(6),
3178 dfixed_init(7),
3179 };
3180 fixed20_12 memtrbs[8] = {
3181 dfixed_init(1),
3182 dfixed_init_half(1),
3183 dfixed_init(2),
3184 dfixed_init_half(2),
3185 dfixed_init(3),
3186 dfixed_init_half(3),
3187 dfixed_init(4),
3188 dfixed_init_half(4)
3189 };
3190 fixed20_12 memtrbs_r4xx[8] = {
3191 dfixed_init(4),
3192 dfixed_init(5),
3193 dfixed_init(6),
3194 dfixed_init(7),
3195 dfixed_init(8),
3196 dfixed_init(9),
3197 dfixed_init(10),
3198 dfixed_init(11)
3199 };
3200 fixed20_12 min_mem_eff;
3201 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3202 fixed20_12 cur_latency_mclk, cur_latency_sclk;
3203 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate = {0},
3204 disp_drain_rate2, read_return_rate;
3205 fixed20_12 time_disp1_drop_priority;
3206 int c;
3207 int cur_size = 16; /* in octawords */
3208 int critical_point = 0, critical_point2;
3209/* uint32_t read_return_rate, time_disp1_drop_priority; */
3210 int stop_req, max_stop_req;
3211 struct drm_display_mode *mode1 = NULL;
3212 struct drm_display_mode *mode2 = NULL;
3213 uint32_t pixel_bytes1 = 0;
3214 uint32_t pixel_bytes2 = 0;
3215
3216 /* Guess line buffer size to be 8192 pixels */
3217 u32 lb_size = 8192;
3218
3219 if (!rdev->mode_info.mode_config_initialized)
3220 return;
3221
3222 radeon_update_display_priority(rdev);
3223
3224 if (rdev->mode_info.crtcs[0]->base.enabled) {
3225 const struct drm_framebuffer *fb =
3226 rdev->mode_info.crtcs[0]->base.primary->fb;
3227
3228 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3229 pixel_bytes1 = fb->format->cpp[0];
3230 }
3231 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3232 if (rdev->mode_info.crtcs[1]->base.enabled) {
3233 const struct drm_framebuffer *fb =
3234 rdev->mode_info.crtcs[1]->base.primary->fb;
3235
3236 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3237 pixel_bytes2 = fb->format->cpp[0];
3238 }
3239 }
3240
3241 min_mem_eff.full = dfixed_const_8(0);
3242 /* get modes */
3243 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3244 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3245 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3246 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3247 /* check crtc enables */
3248 if (mode2)
3249 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3250 if (mode1)
3251 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3252 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3253 }
3254
3255 /*
3256 * determine is there is enough bw for current mode
3257 */
3258 sclk_ff = rdev->pm.sclk;
3259 mclk_ff = rdev->pm.mclk;
3260
3261 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3262 temp_ff.full = dfixed_const(temp);
3263 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3264
3265 pix_clk.full = 0;
3266 pix_clk2.full = 0;
3267 peak_disp_bw.full = 0;
3268 if (mode1) {
3269 temp_ff.full = dfixed_const(1000);
3270 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3271 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3272 temp_ff.full = dfixed_const(pixel_bytes1);
3273 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3274 }
3275 if (mode2) {
3276 temp_ff.full = dfixed_const(1000);
3277 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3278 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3279 temp_ff.full = dfixed_const(pixel_bytes2);
3280 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3281 }
3282
3283 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3284 if (peak_disp_bw.full >= mem_bw.full) {
3285 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3286 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3287 }
3288
3289 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
3290 temp = RREG32(RADEON_MEM_TIMING_CNTL);
3291 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3292 mem_trcd = ((temp >> 2) & 0x3) + 1;
3293 mem_trp = ((temp & 0x3)) + 1;
3294 mem_tras = ((temp & 0x70) >> 4) + 1;
3295 } else if (rdev->family == CHIP_R300 ||
3296 rdev->family == CHIP_R350) { /* r300, r350 */
3297 mem_trcd = (temp & 0x7) + 1;
3298 mem_trp = ((temp >> 8) & 0x7) + 1;
3299 mem_tras = ((temp >> 11) & 0xf) + 4;
3300 } else if (rdev->family == CHIP_RV350 ||
3301 rdev->family == CHIP_RV380) {
3302 /* rv3x0 */
3303 mem_trcd = (temp & 0x7) + 3;
3304 mem_trp = ((temp >> 8) & 0x7) + 3;
3305 mem_tras = ((temp >> 11) & 0xf) + 6;
3306 } else if (rdev->family == CHIP_R420 ||
3307 rdev->family == CHIP_R423 ||
3308 rdev->family == CHIP_RV410) {
3309 /* r4xx */
3310 mem_trcd = (temp & 0xf) + 3;
3311 if (mem_trcd > 15)
3312 mem_trcd = 15;
3313 mem_trp = ((temp >> 8) & 0xf) + 3;
3314 if (mem_trp > 15)
3315 mem_trp = 15;
3316 mem_tras = ((temp >> 12) & 0x1f) + 6;
3317 if (mem_tras > 31)
3318 mem_tras = 31;
3319 } else { /* RV200, R200 */
3320 mem_trcd = (temp & 0x7) + 1;
3321 mem_trp = ((temp >> 8) & 0x7) + 1;
3322 mem_tras = ((temp >> 12) & 0xf) + 4;
3323 }
3324 /* convert to FF */
3325 trcd_ff.full = dfixed_const(mem_trcd);
3326 trp_ff.full = dfixed_const(mem_trp);
3327 tras_ff.full = dfixed_const(mem_tras);
3328
3329 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3330 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3331 data = (temp & (7 << 20)) >> 20;
3332 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3333 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3334 tcas_ff = memtcas_rs480_ff[data];
3335 else
3336 tcas_ff = memtcas_ff[data];
3337 } else
3338 tcas_ff = memtcas2_ff[data];
3339
3340 if (rdev->family == CHIP_RS400 ||
3341 rdev->family == CHIP_RS480) {
3342 /* extra cas latency stored in bits 23-25 0-4 clocks */
3343 data = (temp >> 23) & 0x7;
3344 if (data < 5)
3345 tcas_ff.full += dfixed_const(data);
3346 }
3347
3348 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3349 /* on the R300, Tcas is included in Trbs.
3350 */
3351 temp = RREG32(RADEON_MEM_CNTL);
3352 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3353 if (data == 1) {
3354 if (R300_MEM_USE_CD_CH_ONLY & temp) {
3355 temp = RREG32(R300_MC_IND_INDEX);
3356 temp &= ~R300_MC_IND_ADDR_MASK;
3357 temp |= R300_MC_READ_CNTL_CD_mcind;
3358 WREG32(R300_MC_IND_INDEX, temp);
3359 temp = RREG32(R300_MC_IND_DATA);
3360 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3361 } else {
3362 temp = RREG32(R300_MC_READ_CNTL_AB);
3363 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3364 }
3365 } else {
3366 temp = RREG32(R300_MC_READ_CNTL_AB);
3367 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3368 }
3369 if (rdev->family == CHIP_RV410 ||
3370 rdev->family == CHIP_R420 ||
3371 rdev->family == CHIP_R423)
3372 trbs_ff = memtrbs_r4xx[data];
3373 else
3374 trbs_ff = memtrbs[data];
3375 tcas_ff.full += trbs_ff.full;
3376 }
3377
3378 sclk_eff_ff.full = sclk_ff.full;
3379
3380 if (rdev->flags & RADEON_IS_AGP) {
3381 fixed20_12 agpmode_ff;
3382 agpmode_ff.full = dfixed_const(radeon_agpmode);
3383 temp_ff.full = dfixed_const_666(16);
3384 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3385 }
3386 /* TODO PCIE lanes may affect this - agpmode == 16?? */
3387
3388 if (ASIC_IS_R300(rdev)) {
3389 sclk_delay_ff.full = dfixed_const(250);
3390 } else {
3391 if ((rdev->family == CHIP_RV100) ||
3392 rdev->flags & RADEON_IS_IGP) {
3393 if (rdev->mc.vram_is_ddr)
3394 sclk_delay_ff.full = dfixed_const(41);
3395 else
3396 sclk_delay_ff.full = dfixed_const(33);
3397 } else {
3398 if (rdev->mc.vram_width == 128)
3399 sclk_delay_ff.full = dfixed_const(57);
3400 else
3401 sclk_delay_ff.full = dfixed_const(41);
3402 }
3403 }
3404
3405 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3406
3407 if (rdev->mc.vram_is_ddr) {
3408 if (rdev->mc.vram_width == 32) {
3409 k1.full = dfixed_const(40);
3410 c = 3;
3411 } else {
3412 k1.full = dfixed_const(20);
3413 c = 1;
3414 }
3415 } else {
3416 k1.full = dfixed_const(40);
3417 c = 3;
3418 }
3419
3420 temp_ff.full = dfixed_const(2);
3421 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3422 temp_ff.full = dfixed_const(c);
3423 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3424 temp_ff.full = dfixed_const(4);
3425 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3426 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3427 mc_latency_mclk.full += k1.full;
3428
3429 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3430 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3431
3432 /*
3433 HW cursor time assuming worst case of full size colour cursor.
3434 */
3435 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3436 temp_ff.full += trcd_ff.full;
3437 if (temp_ff.full < tras_ff.full)
3438 temp_ff.full = tras_ff.full;
3439 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3440
3441 temp_ff.full = dfixed_const(cur_size);
3442 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3443 /*
3444 Find the total latency for the display data.
3445 */
3446 disp_latency_overhead.full = dfixed_const(8);
3447 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3448 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3449 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3450
3451 if (mc_latency_mclk.full > mc_latency_sclk.full)
3452 disp_latency.full = mc_latency_mclk.full;
3453 else
3454 disp_latency.full = mc_latency_sclk.full;
3455
3456 /* setup Max GRPH_STOP_REQ default value */
3457 if (ASIC_IS_RV100(rdev))
3458 max_stop_req = 0x5c;
3459 else
3460 max_stop_req = 0x7c;
3461
3462 if (mode1) {
3463 /* CRTC1
3464 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3465 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3466 */
3467 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3468
3469 if (stop_req > max_stop_req)
3470 stop_req = max_stop_req;
3471
3472 /*
3473 Find the drain rate of the display buffer.
3474 */
3475 temp_ff.full = dfixed_const((16/pixel_bytes1));
3476 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3477
3478 /*
3479 Find the critical point of the display buffer.
3480 */
3481 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3482 crit_point_ff.full += dfixed_const_half(0);
3483
3484 critical_point = dfixed_trunc(crit_point_ff);
3485
3486 if (rdev->disp_priority == 2) {
3487 critical_point = 0;
3488 }
3489
3490 /*
3491 The critical point should never be above max_stop_req-4. Setting
3492 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3493 */
3494 if (max_stop_req - critical_point < 4)
3495 critical_point = 0;
3496
3497 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3498 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3499 critical_point = 0x10;
3500 }
3501
3502 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3503 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3504 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3505 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3506 if ((rdev->family == CHIP_R350) &&
3507 (stop_req > 0x15)) {
3508 stop_req -= 0x10;
3509 }
3510 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3511 temp |= RADEON_GRPH_BUFFER_SIZE;
3512 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3513 RADEON_GRPH_CRITICAL_AT_SOF |
3514 RADEON_GRPH_STOP_CNTL);
3515 /*
3516 Write the result into the register.
3517 */
3518 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3519 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3520
3521#if 0
3522 if ((rdev->family == CHIP_RS400) ||
3523 (rdev->family == CHIP_RS480)) {
3524 /* attempt to program RS400 disp regs correctly ??? */
3525 temp = RREG32(RS400_DISP1_REG_CNTL);
3526 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3527 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3528 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3529 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3530 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3531 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3532 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3533 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3534 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3535 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3536 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3537 }
3538#endif
3539
3540 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3541 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3542 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3543 }
3544
3545 if (mode2) {
3546 u32 grph2_cntl;
3547 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3548
3549 if (stop_req > max_stop_req)
3550 stop_req = max_stop_req;
3551
3552 /*
3553 Find the drain rate of the display buffer.
3554 */
3555 temp_ff.full = dfixed_const((16/pixel_bytes2));
3556 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3557
3558 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3559 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3560 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3561 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3562 if ((rdev->family == CHIP_R350) &&
3563 (stop_req > 0x15)) {
3564 stop_req -= 0x10;
3565 }
3566 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3567 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3568 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3569 RADEON_GRPH_CRITICAL_AT_SOF |
3570 RADEON_GRPH_STOP_CNTL);
3571
3572 if ((rdev->family == CHIP_RS100) ||
3573 (rdev->family == CHIP_RS200))
3574 critical_point2 = 0;
3575 else {
3576 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3577 temp_ff.full = dfixed_const(temp);
3578 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3579 if (sclk_ff.full < temp_ff.full)
3580 temp_ff.full = sclk_ff.full;
3581
3582 read_return_rate.full = temp_ff.full;
3583
3584 if (mode1) {
3585 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3586 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3587 } else {
3588 time_disp1_drop_priority.full = 0;
3589 }
3590 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3591 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3592 crit_point_ff.full += dfixed_const_half(0);
3593
3594 critical_point2 = dfixed_trunc(crit_point_ff);
3595
3596 if (rdev->disp_priority == 2) {
3597 critical_point2 = 0;
3598 }
3599
3600 if (max_stop_req - critical_point2 < 4)
3601 critical_point2 = 0;
3602
3603 }
3604
3605 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3606 /* some R300 cards have problem with this set to 0 */
3607 critical_point2 = 0x10;
3608 }
3609
3610 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3611 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3612
3613 if ((rdev->family == CHIP_RS400) ||
3614 (rdev->family == CHIP_RS480)) {
3615#if 0
3616 /* attempt to program RS400 disp2 regs correctly ??? */
3617 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3618 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3619 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3620 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3621 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3622 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3623 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3624 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3625 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3626 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3627 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3628 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3629#endif
3630 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3631 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3632 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3633 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3634 }
3635
3636 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3637 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3638 }
3639
3640 /* Save number of lines the linebuffer leads before the scanout */
3641 if (mode1)
3642 rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
3643
3644 if (mode2)
3645 rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
3646}
3647
3648int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3649{
3650 uint32_t scratch;
3651 uint32_t tmp = 0;
3652 unsigned i;
3653 int r;
3654
3655 r = radeon_scratch_get(rdev, &scratch);
3656 if (r) {
3657 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3658 return r;
3659 }
3660 WREG32(scratch, 0xCAFEDEAD);
3661 r = radeon_ring_lock(rdev, ring, 2);
3662 if (r) {
3663 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3664 radeon_scratch_free(rdev, scratch);
3665 return r;
3666 }
3667 radeon_ring_write(ring, PACKET0(scratch, 0));
3668 radeon_ring_write(ring, 0xDEADBEEF);
3669 radeon_ring_unlock_commit(rdev, ring, false);
3670 for (i = 0; i < rdev->usec_timeout; i++) {
3671 tmp = RREG32(scratch);
3672 if (tmp == 0xDEADBEEF) {
3673 break;
3674 }
3675 udelay(1);
3676 }
3677 if (i < rdev->usec_timeout) {
3678 DRM_INFO("ring test succeeded in %d usecs\n", i);
3679 } else {
3680 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3681 scratch, tmp);
3682 r = -EINVAL;
3683 }
3684 radeon_scratch_free(rdev, scratch);
3685 return r;
3686}
3687
3688void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3689{
3690 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3691
3692 if (ring->rptr_save_reg) {
3693 u32 next_rptr = ring->wptr + 2 + 3;
3694 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3695 radeon_ring_write(ring, next_rptr);
3696 }
3697
3698 radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3699 radeon_ring_write(ring, ib->gpu_addr);
3700 radeon_ring_write(ring, ib->length_dw);
3701}
3702
3703int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3704{
3705 struct radeon_ib ib;
3706 uint32_t scratch;
3707 uint32_t tmp = 0;
3708 unsigned i;
3709 int r;
3710
3711 r = radeon_scratch_get(rdev, &scratch);
3712 if (r) {
3713 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3714 return r;
3715 }
3716 WREG32(scratch, 0xCAFEDEAD);
3717 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3718 if (r) {
3719 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3720 goto free_scratch;
3721 }
3722 ib.ptr[0] = PACKET0(scratch, 0);
3723 ib.ptr[1] = 0xDEADBEEF;
3724 ib.ptr[2] = PACKET2(0);
3725 ib.ptr[3] = PACKET2(0);
3726 ib.ptr[4] = PACKET2(0);
3727 ib.ptr[5] = PACKET2(0);
3728 ib.ptr[6] = PACKET2(0);
3729 ib.ptr[7] = PACKET2(0);
3730 ib.length_dw = 8;
3731 r = radeon_ib_schedule(rdev, &ib, NULL, false);
3732 if (r) {
3733 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3734 goto free_ib;
3735 }
3736 r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
3737 RADEON_USEC_IB_TEST_TIMEOUT));
3738 if (r < 0) {
3739 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3740 goto free_ib;
3741 } else if (r == 0) {
3742 DRM_ERROR("radeon: fence wait timed out.\n");
3743 r = -ETIMEDOUT;
3744 goto free_ib;
3745 }
3746 r = 0;
3747 for (i = 0; i < rdev->usec_timeout; i++) {
3748 tmp = RREG32(scratch);
3749 if (tmp == 0xDEADBEEF) {
3750 break;
3751 }
3752 udelay(1);
3753 }
3754 if (i < rdev->usec_timeout) {
3755 DRM_INFO("ib test succeeded in %u usecs\n", i);
3756 } else {
3757 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3758 scratch, tmp);
3759 r = -EINVAL;
3760 }
3761free_ib:
3762 radeon_ib_free(rdev, &ib);
3763free_scratch:
3764 radeon_scratch_free(rdev, scratch);
3765 return r;
3766}
3767
3768void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3769{
3770 /* Shutdown CP we shouldn't need to do that but better be safe than
3771 * sorry
3772 */
3773 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3774 WREG32(R_000740_CP_CSQ_CNTL, 0);
3775
3776 /* Save few CRTC registers */
3777 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3778 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3779 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3780 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3781 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3782 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3783 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3784 }
3785
3786 /* Disable VGA aperture access */
3787 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3788 /* Disable cursor, overlay, crtc */
3789 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3790 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3791 S_000054_CRTC_DISPLAY_DIS(1));
3792 WREG32(R_000050_CRTC_GEN_CNTL,
3793 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3794 S_000050_CRTC_DISP_REQ_EN_B(1));
3795 WREG32(R_000420_OV0_SCALE_CNTL,
3796 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3797 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3798 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3799 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3800 S_000360_CUR2_LOCK(1));
3801 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3802 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3803 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3804 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3805 WREG32(R_000360_CUR2_OFFSET,
3806 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3807 }
3808}
3809
3810void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3811{
3812 /* Update base address for crtc */
3813 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3814 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3815 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3816 }
3817 /* Restore CRTC registers */
3818 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3819 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3820 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3821 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3822 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3823 }
3824}
3825
3826void r100_vga_render_disable(struct radeon_device *rdev)
3827{
3828 u32 tmp;
3829
3830 tmp = RREG8(R_0003C2_GENMO_WT);
3831 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3832}
3833
3834static void r100_mc_program(struct radeon_device *rdev)
3835{
3836 struct r100_mc_save save;
3837
3838 /* Stops all mc clients */
3839 r100_mc_stop(rdev, &save);
3840 if (rdev->flags & RADEON_IS_AGP) {
3841 WREG32(R_00014C_MC_AGP_LOCATION,
3842 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3843 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3844 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3845 if (rdev->family > CHIP_RV200)
3846 WREG32(R_00015C_AGP_BASE_2,
3847 upper_32_bits(rdev->mc.agp_base) & 0xff);
3848 } else {
3849 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3850 WREG32(R_000170_AGP_BASE, 0);
3851 if (rdev->family > CHIP_RV200)
3852 WREG32(R_00015C_AGP_BASE_2, 0);
3853 }
3854 /* Wait for mc idle */
3855 if (r100_mc_wait_for_idle(rdev))
3856 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3857 /* Program MC, should be a 32bits limited address space */
3858 WREG32(R_000148_MC_FB_LOCATION,
3859 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3860 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3861 r100_mc_resume(rdev, &save);
3862}
3863
3864static void r100_clock_startup(struct radeon_device *rdev)
3865{
3866 u32 tmp;
3867
3868 if (radeon_dynclks != -1 && radeon_dynclks)
3869 radeon_legacy_set_clock_gating(rdev, 1);
3870 /* We need to force on some of the block */
3871 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3872 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3873 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3874 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3875 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3876}
3877
3878static int r100_startup(struct radeon_device *rdev)
3879{
3880 int r;
3881
3882 /* set common regs */
3883 r100_set_common_regs(rdev);
3884 /* program mc */
3885 r100_mc_program(rdev);
3886 /* Resume clock */
3887 r100_clock_startup(rdev);
3888 /* Initialize GART (initialize after TTM so we can allocate
3889 * memory through TTM but finalize after TTM) */
3890 r100_enable_bm(rdev);
3891 if (rdev->flags & RADEON_IS_PCI) {
3892 r = r100_pci_gart_enable(rdev);
3893 if (r)
3894 return r;
3895 }
3896
3897 /* allocate wb buffer */
3898 r = radeon_wb_init(rdev);
3899 if (r)
3900 return r;
3901
3902 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3903 if (r) {
3904 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3905 return r;
3906 }
3907
3908 /* Enable IRQ */
3909 if (!rdev->irq.installed) {
3910 r = radeon_irq_kms_init(rdev);
3911 if (r)
3912 return r;
3913 }
3914
3915 r100_irq_set(rdev);
3916 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3917 /* 1M ring buffer */
3918 r = r100_cp_init(rdev, 1024 * 1024);
3919 if (r) {
3920 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3921 return r;
3922 }
3923
3924 r = radeon_ib_pool_init(rdev);
3925 if (r) {
3926 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3927 return r;
3928 }
3929
3930 return 0;
3931}
3932
3933int r100_resume(struct radeon_device *rdev)
3934{
3935 int r;
3936
3937 /* Make sur GART are not working */
3938 if (rdev->flags & RADEON_IS_PCI)
3939 r100_pci_gart_disable(rdev);
3940 /* Resume clock before doing reset */
3941 r100_clock_startup(rdev);
3942 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3943 if (radeon_asic_reset(rdev)) {
3944 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3945 RREG32(R_000E40_RBBM_STATUS),
3946 RREG32(R_0007C0_CP_STAT));
3947 }
3948 /* post */
3949 radeon_combios_asic_init(rdev->ddev);
3950 /* Resume clock after posting */
3951 r100_clock_startup(rdev);
3952 /* Initialize surface registers */
3953 radeon_surface_init(rdev);
3954
3955 rdev->accel_working = true;
3956 r = r100_startup(rdev);
3957 if (r) {
3958 rdev->accel_working = false;
3959 }
3960 return r;
3961}
3962
3963int r100_suspend(struct radeon_device *rdev)
3964{
3965 radeon_pm_suspend(rdev);
3966 r100_cp_disable(rdev);
3967 radeon_wb_disable(rdev);
3968 r100_irq_disable(rdev);
3969 if (rdev->flags & RADEON_IS_PCI)
3970 r100_pci_gart_disable(rdev);
3971 return 0;
3972}
3973
3974void r100_fini(struct radeon_device *rdev)
3975{
3976 radeon_pm_fini(rdev);
3977 r100_cp_fini(rdev);
3978 radeon_wb_fini(rdev);
3979 radeon_ib_pool_fini(rdev);
3980 radeon_gem_fini(rdev);
3981 if (rdev->flags & RADEON_IS_PCI)
3982 r100_pci_gart_fini(rdev);
3983 radeon_agp_fini(rdev);
3984 radeon_irq_kms_fini(rdev);
3985 radeon_fence_driver_fini(rdev);
3986 radeon_bo_fini(rdev);
3987 radeon_atombios_fini(rdev);
3988 kfree(rdev->bios);
3989 rdev->bios = NULL;
3990}
3991
3992/*
3993 * Due to how kexec works, it can leave the hw fully initialised when it
3994 * boots the new kernel. However doing our init sequence with the CP and
3995 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3996 * do some quick sanity checks and restore sane values to avoid this
3997 * problem.
3998 */
3999void r100_restore_sanity(struct radeon_device *rdev)
4000{
4001 u32 tmp;
4002
4003 tmp = RREG32(RADEON_CP_CSQ_CNTL);
4004 if (tmp) {
4005 WREG32(RADEON_CP_CSQ_CNTL, 0);
4006 }
4007 tmp = RREG32(RADEON_CP_RB_CNTL);
4008 if (tmp) {
4009 WREG32(RADEON_CP_RB_CNTL, 0);
4010 }
4011 tmp = RREG32(RADEON_SCRATCH_UMSK);
4012 if (tmp) {
4013 WREG32(RADEON_SCRATCH_UMSK, 0);
4014 }
4015}
4016
4017int r100_init(struct radeon_device *rdev)
4018{
4019 int r;
4020
4021 /* Register debugfs file specific to this group of asics */
4022 r100_debugfs_mc_info_init(rdev);
4023 /* Disable VGA */
4024 r100_vga_render_disable(rdev);
4025 /* Initialize scratch registers */
4026 radeon_scratch_init(rdev);
4027 /* Initialize surface registers */
4028 radeon_surface_init(rdev);
4029 /* sanity check some register to avoid hangs like after kexec */
4030 r100_restore_sanity(rdev);
4031 /* TODO: disable VGA need to use VGA request */
4032 /* BIOS*/
4033 if (!radeon_get_bios(rdev)) {
4034 if (ASIC_IS_AVIVO(rdev))
4035 return -EINVAL;
4036 }
4037 if (rdev->is_atom_bios) {
4038 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4039 return -EINVAL;
4040 } else {
4041 r = radeon_combios_init(rdev);
4042 if (r)
4043 return r;
4044 }
4045 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4046 if (radeon_asic_reset(rdev)) {
4047 dev_warn(rdev->dev,
4048 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4049 RREG32(R_000E40_RBBM_STATUS),
4050 RREG32(R_0007C0_CP_STAT));
4051 }
4052 /* check if cards are posted or not */
4053 if (radeon_boot_test_post_card(rdev) == false)
4054 return -EINVAL;
4055 /* Set asic errata */
4056 r100_errata(rdev);
4057 /* Initialize clocks */
4058 radeon_get_clock_info(rdev->ddev);
4059 /* initialize AGP */
4060 if (rdev->flags & RADEON_IS_AGP) {
4061 r = radeon_agp_init(rdev);
4062 if (r) {
4063 radeon_agp_disable(rdev);
4064 }
4065 }
4066 /* initialize VRAM */
4067 r100_mc_init(rdev);
4068 /* Fence driver */
4069 radeon_fence_driver_init(rdev);
4070 /* Memory manager */
4071 r = radeon_bo_init(rdev);
4072 if (r)
4073 return r;
4074 if (rdev->flags & RADEON_IS_PCI) {
4075 r = r100_pci_gart_init(rdev);
4076 if (r)
4077 return r;
4078 }
4079 r100_set_safe_registers(rdev);
4080
4081 /* Initialize power management */
4082 radeon_pm_init(rdev);
4083
4084 rdev->accel_working = true;
4085 r = r100_startup(rdev);
4086 if (r) {
4087 /* Somethings want wront with the accel init stop accel */
4088 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4089 r100_cp_fini(rdev);
4090 radeon_wb_fini(rdev);
4091 radeon_ib_pool_fini(rdev);
4092 radeon_irq_kms_fini(rdev);
4093 if (rdev->flags & RADEON_IS_PCI)
4094 r100_pci_gart_fini(rdev);
4095 rdev->accel_working = false;
4096 }
4097 return 0;
4098}
4099
4100uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
4101{
4102 unsigned long flags;
4103 uint32_t ret;
4104
4105 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4106 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4107 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4108 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4109 return ret;
4110}
4111
4112void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4113{
4114 unsigned long flags;
4115
4116 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4117 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4118 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4119 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4120}
4121
4122u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4123{
4124 if (reg < rdev->rio_mem_size)
4125 return ioread32(rdev->rio_mem + reg);
4126 else {
4127 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4128 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4129 }
4130}
4131
4132void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4133{
4134 if (reg < rdev->rio_mem_size)
4135 iowrite32(v, rdev->rio_mem + reg);
4136 else {
4137 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4138 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4139 }
4140}