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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
7
8#include <linux/debugfs.h>
9
10#include <drm/drm_framebuffer.h>
11#include <drm/drm_managed.h>
12
13#include "dpu_encoder_phys.h"
14#include "dpu_formats.h"
15#include "dpu_hw_top.h"
16#include "dpu_hw_wb.h"
17#include "dpu_hw_lm.h"
18#include "dpu_hw_merge3d.h"
19#include "dpu_hw_interrupts.h"
20#include "dpu_core_irq.h"
21#include "dpu_vbif.h"
22#include "dpu_crtc.h"
23#include "disp/msm_disp_snapshot.h"
24
25#define to_dpu_encoder_phys_wb(x) \
26 container_of(x, struct dpu_encoder_phys_wb, base)
27
28/**
29 * dpu_encoder_phys_wb_is_master - report wb always as master encoder
30 * @phys_enc: Pointer to physical encoder
31 */
32static bool dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys *phys_enc)
33{
34 /* there is only one physical enc for dpu_writeback */
35 return true;
36}
37
38static bool _dpu_encoder_phys_wb_clk_force_ctrl(struct dpu_hw_wb *wb,
39 struct dpu_hw_mdp *mdp,
40 bool enable, bool *forced_on)
41{
42 if (wb->ops.setup_clk_force_ctrl) {
43 *forced_on = wb->ops.setup_clk_force_ctrl(wb, enable);
44 return true;
45 }
46
47 if (mdp->ops.setup_clk_force_ctrl) {
48 *forced_on = mdp->ops.setup_clk_force_ctrl(mdp, wb->caps->clk_ctrl, enable);
49 return true;
50 }
51
52 return false;
53}
54
55/**
56 * dpu_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface
57 * @phys_enc: Pointer to physical encoder
58 */
59static void dpu_encoder_phys_wb_set_ot_limit(
60 struct dpu_encoder_phys *phys_enc)
61{
62 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
63 struct dpu_vbif_set_ot_params ot_params;
64 bool forced_on = false;
65
66 memset(&ot_params, 0, sizeof(ot_params));
67 ot_params.xin_id = hw_wb->caps->xin_id;
68 ot_params.num = hw_wb->idx - WB_0;
69 ot_params.width = phys_enc->cached_mode.hdisplay;
70 ot_params.height = phys_enc->cached_mode.vdisplay;
71 ot_params.is_wfd = true;
72 ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode);
73 ot_params.vbif_idx = hw_wb->caps->vbif_idx;
74 ot_params.rd = false;
75
76 if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
77 true, &forced_on))
78 return;
79
80 dpu_vbif_set_ot_limit(phys_enc->dpu_kms, &ot_params);
81
82 if (forced_on)
83 _dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
84 false, &forced_on);
85}
86
87/**
88 * dpu_encoder_phys_wb_set_qos_remap - set QoS remapper for writeback
89 * @phys_enc: Pointer to physical encoder
90 */
91static void dpu_encoder_phys_wb_set_qos_remap(
92 struct dpu_encoder_phys *phys_enc)
93{
94 struct dpu_hw_wb *hw_wb;
95 struct dpu_vbif_set_qos_params qos_params;
96 bool forced_on = false;
97
98 if (!phys_enc || !phys_enc->parent || !phys_enc->parent->crtc) {
99 DPU_ERROR("invalid arguments\n");
100 return;
101 }
102
103 if (!phys_enc->hw_wb || !phys_enc->hw_wb->caps) {
104 DPU_ERROR("invalid writeback hardware\n");
105 return;
106 }
107
108 hw_wb = phys_enc->hw_wb;
109
110 memset(&qos_params, 0, sizeof(qos_params));
111 qos_params.vbif_idx = hw_wb->caps->vbif_idx;
112 qos_params.xin_id = hw_wb->caps->xin_id;
113 qos_params.num = hw_wb->idx - WB_0;
114 qos_params.is_rt = false;
115
116 DPU_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d is_rt:%d\n",
117 qos_params.num,
118 qos_params.vbif_idx,
119 qos_params.xin_id, qos_params.is_rt);
120
121 if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
122 true, &forced_on))
123 return;
124
125 dpu_vbif_set_qos_remap(phys_enc->dpu_kms, &qos_params);
126
127 if (forced_on)
128 _dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
129 false, &forced_on);
130}
131
132/**
133 * dpu_encoder_phys_wb_set_qos - set QoS/danger/safe LUTs for writeback
134 * @phys_enc: Pointer to physical encoder
135 */
136static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc)
137{
138 struct dpu_hw_wb *hw_wb;
139 struct dpu_hw_qos_cfg qos_cfg;
140 const struct dpu_mdss_cfg *catalog;
141 const struct dpu_qos_lut_tbl *qos_lut_tb;
142
143 if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
144 DPU_ERROR("invalid parameter(s)\n");
145 return;
146 }
147
148 catalog = phys_enc->dpu_kms->catalog;
149
150 hw_wb = phys_enc->hw_wb;
151
152 memset(&qos_cfg, 0, sizeof(struct dpu_hw_qos_cfg));
153 qos_cfg.danger_safe_en = true;
154 qos_cfg.danger_lut =
155 catalog->perf->danger_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
156
157 qos_cfg.safe_lut = catalog->perf->safe_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
158
159 qos_lut_tb = &catalog->perf->qos_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
160 qos_cfg.creq_lut = _dpu_hw_get_qos_lut(qos_lut_tb, 0);
161
162 if (hw_wb->ops.setup_qos_lut)
163 hw_wb->ops.setup_qos_lut(hw_wb, &qos_cfg);
164}
165
166/**
167 * dpu_encoder_phys_wb_setup_fb - setup output framebuffer
168 * @phys_enc: Pointer to physical encoder
169 * @fb: Pointer to output framebuffer
170 */
171static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc,
172 struct drm_framebuffer *fb)
173{
174 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
175 struct dpu_hw_wb *hw_wb;
176 struct dpu_hw_wb_cfg *wb_cfg;
177
178 if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
179 DPU_ERROR("invalid encoder\n");
180 return;
181 }
182
183 hw_wb = phys_enc->hw_wb;
184 wb_cfg = &wb_enc->wb_cfg;
185
186 wb_cfg->intf_mode = phys_enc->intf_mode;
187 wb_cfg->roi.x1 = 0;
188 wb_cfg->roi.x2 = phys_enc->cached_mode.hdisplay;
189 wb_cfg->roi.y1 = 0;
190 wb_cfg->roi.y2 = phys_enc->cached_mode.vdisplay;
191
192 if (hw_wb->ops.setup_roi)
193 hw_wb->ops.setup_roi(hw_wb, wb_cfg);
194
195 if (hw_wb->ops.setup_outformat)
196 hw_wb->ops.setup_outformat(hw_wb, wb_cfg);
197
198 if (hw_wb->ops.setup_cdp) {
199 const struct dpu_perf_cfg *perf = phys_enc->dpu_kms->catalog->perf;
200
201 hw_wb->ops.setup_cdp(hw_wb, wb_cfg->dest.format,
202 perf->cdp_cfg[DPU_PERF_CDP_USAGE_NRT].wr_enable);
203 }
204
205 if (hw_wb->ops.setup_outaddress)
206 hw_wb->ops.setup_outaddress(hw_wb, wb_cfg);
207}
208
209/**
210 * dpu_encoder_phys_wb_setup_ctl - setup wb pipeline for ctl path
211 * @phys_enc:Pointer to physical encoder
212 */
213static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc)
214{
215 struct dpu_hw_wb *hw_wb;
216 struct dpu_hw_ctl *ctl;
217 struct dpu_hw_cdm *hw_cdm;
218
219 if (!phys_enc) {
220 DPU_ERROR("invalid encoder\n");
221 return;
222 }
223
224 hw_wb = phys_enc->hw_wb;
225 ctl = phys_enc->hw_ctl;
226 hw_cdm = phys_enc->hw_cdm;
227
228 if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) &&
229 (phys_enc->hw_ctl &&
230 phys_enc->hw_ctl->ops.setup_intf_cfg)) {
231 struct dpu_hw_intf_cfg intf_cfg = {0};
232 struct dpu_hw_pingpong *hw_pp = phys_enc->hw_pp;
233 enum dpu_3d_blend_mode mode_3d;
234
235 mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
236
237 intf_cfg.intf = DPU_NONE;
238 intf_cfg.wb = hw_wb->idx;
239
240 if (mode_3d && hw_pp && hw_pp->merge_3d)
241 intf_cfg.merge_3d = hw_pp->merge_3d->idx;
242
243 if (hw_cdm)
244 intf_cfg.cdm = hw_cdm->idx;
245
246 if (phys_enc->hw_pp->merge_3d && phys_enc->hw_pp->merge_3d->ops.setup_3d_mode)
247 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,
248 mode_3d);
249
250 /* setup which pp blk will connect to this wb */
251 if (hw_pp && phys_enc->hw_wb->ops.bind_pingpong_blk)
252 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb,
253 phys_enc->hw_pp->idx);
254
255 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
256 } else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) {
257 struct dpu_hw_intf_cfg intf_cfg = {0};
258
259 intf_cfg.intf = DPU_NONE;
260 intf_cfg.wb = hw_wb->idx;
261 intf_cfg.mode_3d =
262 dpu_encoder_helper_get_3d_blend_mode(phys_enc);
263 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
264 }
265}
266
267/**
268 * dpu_encoder_helper_phys_setup_cdm - setup chroma down sampling block
269 * This API does not handle DPU_CHROMA_H1V2.
270 * @phys_enc:Pointer to physical encoder
271 */
272static void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc)
273{
274 struct dpu_hw_cdm *hw_cdm;
275 struct dpu_hw_cdm_cfg *cdm_cfg;
276 struct dpu_hw_pingpong *hw_pp;
277 struct dpu_encoder_phys_wb *wb_enc;
278 const struct msm_format *format;
279 const struct dpu_format *dpu_fmt;
280 struct drm_writeback_job *wb_job;
281 int ret;
282
283 if (!phys_enc)
284 return;
285
286 wb_enc = to_dpu_encoder_phys_wb(phys_enc);
287 cdm_cfg = &wb_enc->cdm_cfg;
288 hw_pp = phys_enc->hw_pp;
289 hw_cdm = phys_enc->hw_cdm;
290 wb_job = wb_enc->wb_job;
291
292 format = msm_framebuffer_format(wb_enc->wb_job->fb);
293 dpu_fmt = dpu_get_dpu_format_ext(format->pixel_format, wb_job->fb->modifier);
294
295 if (!hw_cdm)
296 return;
297
298 if (!DPU_FORMAT_IS_YUV(dpu_fmt)) {
299 DPU_DEBUG("[enc:%d] cdm_disable fmt:%x\n", DRMID(phys_enc->parent),
300 dpu_fmt->base.pixel_format);
301 if (hw_cdm->ops.bind_pingpong_blk)
302 hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE);
303
304 return;
305 }
306
307 memset(cdm_cfg, 0, sizeof(struct dpu_hw_cdm_cfg));
308
309 cdm_cfg->output_width = wb_job->fb->width;
310 cdm_cfg->output_height = wb_job->fb->height;
311 cdm_cfg->output_fmt = dpu_fmt;
312 cdm_cfg->output_type = CDM_CDWN_OUTPUT_WB;
313 cdm_cfg->output_bit_depth = DPU_FORMAT_IS_DX(dpu_fmt) ?
314 CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT;
315 cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l;
316
317 /* enable 10 bit logic */
318 switch (cdm_cfg->output_fmt->chroma_sample) {
319 case DPU_CHROMA_RGB:
320 cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
321 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
322 break;
323 case DPU_CHROMA_H2V1:
324 cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
325 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
326 break;
327 case DPU_CHROMA_420:
328 cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE;
329 cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE;
330 break;
331 case DPU_CHROMA_H1V2:
332 default:
333 DPU_ERROR("[enc:%d] unsupported chroma sampling type\n",
334 DRMID(phys_enc->parent));
335 cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE;
336 cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE;
337 break;
338 }
339
340 DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n",
341 DRMID(phys_enc->parent), cdm_cfg->output_width,
342 cdm_cfg->output_height, cdm_cfg->output_fmt->base.pixel_format,
343 cdm_cfg->output_type, cdm_cfg->output_bit_depth,
344 cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type);
345
346 if (hw_cdm->ops.enable) {
347 cdm_cfg->pp_id = hw_pp->idx;
348 ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg);
349 if (ret < 0) {
350 DPU_ERROR("[enc:%d] failed to enable CDM; ret:%d\n",
351 DRMID(phys_enc->parent), ret);
352 return;
353 }
354 }
355}
356
357/**
358 * dpu_encoder_phys_wb_atomic_check - verify and fixup given atomic states
359 * @phys_enc: Pointer to physical encoder
360 * @crtc_state: Pointer to CRTC atomic state
361 * @conn_state: Pointer to connector atomic state
362 */
363static int dpu_encoder_phys_wb_atomic_check(
364 struct dpu_encoder_phys *phys_enc,
365 struct drm_crtc_state *crtc_state,
366 struct drm_connector_state *conn_state)
367{
368 struct drm_framebuffer *fb;
369 const struct drm_display_mode *mode = &crtc_state->mode;
370
371 DPU_DEBUG("[atomic_check:%d, \"%s\",%d,%d]\n",
372 phys_enc->hw_wb->idx, mode->name, mode->hdisplay, mode->vdisplay);
373
374 if (!conn_state || !conn_state->connector) {
375 DPU_ERROR("invalid connector state\n");
376 return -EINVAL;
377 } else if (conn_state->connector->status !=
378 connector_status_connected) {
379 DPU_ERROR("connector not connected %d\n",
380 conn_state->connector->status);
381 return -EINVAL;
382 }
383
384 if (!conn_state->writeback_job || !conn_state->writeback_job->fb)
385 return 0;
386
387 fb = conn_state->writeback_job->fb;
388
389 DPU_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
390 fb->width, fb->height);
391
392 if (fb->width != mode->hdisplay) {
393 DPU_ERROR("invalid fb w=%d, mode w=%d\n", fb->width,
394 mode->hdisplay);
395 return -EINVAL;
396 } else if (fb->height != mode->vdisplay) {
397 DPU_ERROR("invalid fb h=%d, mode h=%d\n", fb->height,
398 mode->vdisplay);
399 return -EINVAL;
400 } else if (fb->width > phys_enc->hw_wb->caps->maxlinewidth) {
401 DPU_ERROR("invalid fb w=%d, maxlinewidth=%u\n",
402 fb->width, phys_enc->hw_wb->caps->maxlinewidth);
403 return -EINVAL;
404 }
405
406 return drm_atomic_helper_check_wb_connector_state(conn_state->connector, conn_state->state);
407}
408
409
410/**
411 * _dpu_encoder_phys_wb_update_flush - flush hardware update
412 * @phys_enc: Pointer to physical encoder
413 */
414static void _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc)
415{
416 struct dpu_hw_wb *hw_wb;
417 struct dpu_hw_ctl *hw_ctl;
418 struct dpu_hw_pingpong *hw_pp;
419 struct dpu_hw_cdm *hw_cdm;
420 u32 pending_flush = 0;
421
422 if (!phys_enc)
423 return;
424
425 hw_wb = phys_enc->hw_wb;
426 hw_pp = phys_enc->hw_pp;
427 hw_ctl = phys_enc->hw_ctl;
428 hw_cdm = phys_enc->hw_cdm;
429
430 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
431
432 if (!hw_ctl) {
433 DPU_DEBUG("[wb:%d] no ctl assigned\n", hw_wb->idx - WB_0);
434 return;
435 }
436
437 if (hw_ctl->ops.update_pending_flush_wb)
438 hw_ctl->ops.update_pending_flush_wb(hw_ctl, hw_wb->idx);
439
440 if (hw_ctl->ops.update_pending_flush_merge_3d && hw_pp && hw_pp->merge_3d)
441 hw_ctl->ops.update_pending_flush_merge_3d(hw_ctl,
442 hw_pp->merge_3d->idx);
443
444 if (hw_cdm && hw_ctl->ops.update_pending_flush_cdm)
445 hw_ctl->ops.update_pending_flush_cdm(hw_ctl, hw_cdm->idx);
446
447 if (hw_ctl->ops.get_pending_flush)
448 pending_flush = hw_ctl->ops.get_pending_flush(hw_ctl);
449
450 DPU_DEBUG("Pending flush mask for CTL_%d is 0x%x, WB %d\n",
451 hw_ctl->idx - CTL_0, pending_flush,
452 hw_wb->idx - WB_0);
453}
454
455/**
456 * dpu_encoder_phys_wb_setup - setup writeback encoder
457 * @phys_enc: Pointer to physical encoder
458 */
459static void dpu_encoder_phys_wb_setup(
460 struct dpu_encoder_phys *phys_enc)
461{
462 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
463 struct drm_display_mode mode = phys_enc->cached_mode;
464 struct drm_framebuffer *fb = NULL;
465
466 DPU_DEBUG("[mode_set:%d, \"%s\",%d,%d]\n",
467 hw_wb->idx - WB_0, mode.name,
468 mode.hdisplay, mode.vdisplay);
469
470 dpu_encoder_phys_wb_set_ot_limit(phys_enc);
471
472 dpu_encoder_phys_wb_set_qos_remap(phys_enc);
473
474 dpu_encoder_phys_wb_set_qos(phys_enc);
475
476 dpu_encoder_phys_wb_setup_fb(phys_enc, fb);
477
478 dpu_encoder_helper_phys_setup_cdm(phys_enc);
479
480 dpu_encoder_phys_wb_setup_ctl(phys_enc);
481}
482
483/**
484 * dpu_encoder_phys_wb_done_irq - writeback interrupt handler
485 * @arg: Pointer to writeback encoder
486 */
487static void dpu_encoder_phys_wb_done_irq(void *arg)
488{
489 struct dpu_encoder_phys *phys_enc = arg;
490 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
491
492 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
493 unsigned long lock_flags;
494 u32 event = DPU_ENCODER_FRAME_EVENT_DONE;
495
496 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
497
498 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, event);
499
500 dpu_encoder_vblank_callback(phys_enc->parent, phys_enc);
501
502 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
503 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
504 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
505
506 if (wb_enc->wb_conn)
507 drm_writeback_signal_completion(wb_enc->wb_conn, 0);
508
509 /* Signal any waiting atomic commit thread */
510 wake_up_all(&phys_enc->pending_kickoff_wq);
511}
512
513/**
514 * dpu_encoder_phys_wb_irq_ctrl - irq control of WB
515 * @phys: Pointer to physical encoder
516 * @enable: indicates enable or disable interrupts
517 */
518static void dpu_encoder_phys_wb_irq_ctrl(
519 struct dpu_encoder_phys *phys, bool enable)
520{
521
522 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys);
523
524 if (enable && atomic_inc_return(&wb_enc->wbirq_refcount) == 1)
525 dpu_core_irq_register_callback(phys->dpu_kms,
526 phys->irq[INTR_IDX_WB_DONE], dpu_encoder_phys_wb_done_irq, phys);
527 else if (!enable &&
528 atomic_dec_return(&wb_enc->wbirq_refcount) == 0)
529 dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]);
530}
531
532static void dpu_encoder_phys_wb_atomic_mode_set(
533 struct dpu_encoder_phys *phys_enc,
534 struct drm_crtc_state *crtc_state,
535 struct drm_connector_state *conn_state)
536{
537
538 phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done;
539}
540
541static void _dpu_encoder_phys_wb_handle_wbdone_timeout(
542 struct dpu_encoder_phys *phys_enc)
543{
544 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
545 u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR;
546
547 wb_enc->wb_done_timeout_cnt++;
548
549 if (wb_enc->wb_done_timeout_cnt == 1)
550 msm_disp_snapshot_state(phys_enc->parent->dev);
551
552 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
553
554 /* request a ctl reset before the next kickoff */
555 phys_enc->enable_state = DPU_ENC_ERR_NEEDS_HW_RESET;
556
557 if (wb_enc->wb_conn)
558 drm_writeback_signal_completion(wb_enc->wb_conn, 0);
559
560 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, frame_event);
561}
562
563/**
564 * dpu_encoder_phys_wb_wait_for_commit_done - wait until request is committed
565 * @phys_enc: Pointer to physical encoder
566 */
567static int dpu_encoder_phys_wb_wait_for_commit_done(
568 struct dpu_encoder_phys *phys_enc)
569{
570 unsigned long ret;
571 struct dpu_encoder_wait_info wait_info;
572 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
573
574 wait_info.wq = &phys_enc->pending_kickoff_wq;
575 wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
576 wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
577
578 ret = dpu_encoder_helper_wait_for_irq(phys_enc,
579 phys_enc->irq[INTR_IDX_WB_DONE],
580 dpu_encoder_phys_wb_done_irq, &wait_info);
581 if (ret == -ETIMEDOUT)
582 _dpu_encoder_phys_wb_handle_wbdone_timeout(phys_enc);
583 else if (!ret)
584 wb_enc->wb_done_timeout_cnt = 0;
585
586 return ret;
587}
588
589/**
590 * dpu_encoder_phys_wb_prepare_for_kickoff - pre-kickoff processing
591 * @phys_enc: Pointer to physical encoder
592 * Returns: Zero on success
593 */
594static void dpu_encoder_phys_wb_prepare_for_kickoff(
595 struct dpu_encoder_phys *phys_enc)
596{
597 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
598 struct drm_connector *drm_conn;
599 struct drm_connector_state *state;
600
601 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
602
603 if (!wb_enc->wb_conn || !wb_enc->wb_job) {
604 DPU_ERROR("invalid wb_conn or wb_job\n");
605 return;
606 }
607
608 drm_conn = &wb_enc->wb_conn->base;
609 state = drm_conn->state;
610
611 if (wb_enc->wb_conn && wb_enc->wb_job)
612 drm_writeback_queue_job(wb_enc->wb_conn, state);
613
614 dpu_encoder_phys_wb_setup(phys_enc);
615
616 _dpu_encoder_phys_wb_update_flush(phys_enc);
617}
618
619/**
620 * dpu_encoder_phys_wb_needs_single_flush - trigger flush processing
621 * @phys_enc: Pointer to physical encoder
622 */
623static bool dpu_encoder_phys_wb_needs_single_flush(struct dpu_encoder_phys *phys_enc)
624{
625 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
626 return false;
627}
628
629/**
630 * dpu_encoder_phys_wb_handle_post_kickoff - post-kickoff processing
631 * @phys_enc: Pointer to physical encoder
632 */
633static void dpu_encoder_phys_wb_handle_post_kickoff(
634 struct dpu_encoder_phys *phys_enc)
635{
636 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
637
638}
639
640/**
641 * dpu_encoder_phys_wb_enable - enable writeback encoder
642 * @phys_enc: Pointer to physical encoder
643 */
644static void dpu_encoder_phys_wb_enable(struct dpu_encoder_phys *phys_enc)
645{
646 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
647 phys_enc->enable_state = DPU_ENC_ENABLED;
648}
649/**
650 * dpu_encoder_phys_wb_disable - disable writeback encoder
651 * @phys_enc: Pointer to physical encoder
652 */
653static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc)
654{
655 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
656 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
657
658 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
659
660 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
661 DPU_ERROR("encoder is already disabled\n");
662 return;
663 }
664
665 /* reset h/w before final flush */
666 if (phys_enc->hw_ctl->ops.clear_pending_flush)
667 phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl);
668
669 /*
670 * New CTL reset sequence from 5.0 MDP onwards.
671 * If has_3d_merge_reset is not set, legacy reset
672 * sequence is executed.
673 *
674 * Legacy reset sequence has not been implemented yet.
675 * Any target earlier than SM8150 will need it and when
676 * WB support is added to those targets will need to add
677 * the legacy teardown sequence as well.
678 */
679 if (hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG))
680 dpu_encoder_helper_phys_cleanup(phys_enc);
681
682 phys_enc->enable_state = DPU_ENC_DISABLED;
683}
684
685static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc,
686 struct drm_writeback_job *job)
687{
688 const struct msm_format *format;
689 struct msm_gem_address_space *aspace;
690 struct dpu_hw_wb_cfg *wb_cfg;
691 int ret;
692 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
693
694 if (!job->fb)
695 return;
696
697 wb_enc->wb_job = job;
698 wb_enc->wb_conn = job->connector;
699 aspace = phys_enc->dpu_kms->base.aspace;
700
701 wb_cfg = &wb_enc->wb_cfg;
702
703 memset(wb_cfg, 0, sizeof(struct dpu_hw_wb_cfg));
704
705 ret = msm_framebuffer_prepare(job->fb, aspace, false);
706 if (ret) {
707 DPU_ERROR("prep fb failed, %d\n", ret);
708 return;
709 }
710
711 format = msm_framebuffer_format(job->fb);
712
713 wb_cfg->dest.format = dpu_get_dpu_format_ext(
714 format->pixel_format, job->fb->modifier);
715 if (!wb_cfg->dest.format) {
716 /* this error should be detected during atomic_check */
717 DPU_ERROR("failed to get format %x\n", format->pixel_format);
718 return;
719 }
720
721 ret = dpu_format_populate_layout(aspace, job->fb, &wb_cfg->dest);
722 if (ret) {
723 DPU_DEBUG("failed to populate layout %d\n", ret);
724 return;
725 }
726
727 wb_cfg->dest.width = job->fb->width;
728 wb_cfg->dest.height = job->fb->height;
729 wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
730
731 if ((wb_cfg->dest.format->fetch_planes == DPU_PLANE_PLANAR) &&
732 (wb_cfg->dest.format->element[0] == C1_B_Cb))
733 swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
734
735 DPU_DEBUG("[fb_offset:%8.8x,%8.8x,%8.8x,%8.8x]\n",
736 wb_cfg->dest.plane_addr[0], wb_cfg->dest.plane_addr[1],
737 wb_cfg->dest.plane_addr[2], wb_cfg->dest.plane_addr[3]);
738
739 DPU_DEBUG("[fb_stride:%8.8x,%8.8x,%8.8x,%8.8x]\n",
740 wb_cfg->dest.plane_pitch[0], wb_cfg->dest.plane_pitch[1],
741 wb_cfg->dest.plane_pitch[2], wb_cfg->dest.plane_pitch[3]);
742}
743
744static void dpu_encoder_phys_wb_cleanup_wb_job(struct dpu_encoder_phys *phys_enc,
745 struct drm_writeback_job *job)
746{
747 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
748 struct msm_gem_address_space *aspace;
749
750 if (!job->fb)
751 return;
752
753 aspace = phys_enc->dpu_kms->base.aspace;
754
755 msm_framebuffer_cleanup(job->fb, aspace, false);
756 wb_enc->wb_job = NULL;
757 wb_enc->wb_conn = NULL;
758}
759
760static bool dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys *phys_enc)
761{
762 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
763
764 if (wb_enc->wb_job)
765 return true;
766 else
767 return false;
768}
769
770/**
771 * dpu_encoder_phys_wb_init_ops - initialize writeback operations
772 * @ops: Pointer to encoder operation table
773 */
774static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops)
775{
776 ops->is_master = dpu_encoder_phys_wb_is_master;
777 ops->atomic_mode_set = dpu_encoder_phys_wb_atomic_mode_set;
778 ops->enable = dpu_encoder_phys_wb_enable;
779 ops->disable = dpu_encoder_phys_wb_disable;
780 ops->atomic_check = dpu_encoder_phys_wb_atomic_check;
781 ops->wait_for_commit_done = dpu_encoder_phys_wb_wait_for_commit_done;
782 ops->prepare_for_kickoff = dpu_encoder_phys_wb_prepare_for_kickoff;
783 ops->handle_post_kickoff = dpu_encoder_phys_wb_handle_post_kickoff;
784 ops->needs_single_flush = dpu_encoder_phys_wb_needs_single_flush;
785 ops->trigger_start = dpu_encoder_helper_trigger_start;
786 ops->prepare_wb_job = dpu_encoder_phys_wb_prepare_wb_job;
787 ops->cleanup_wb_job = dpu_encoder_phys_wb_cleanup_wb_job;
788 ops->irq_control = dpu_encoder_phys_wb_irq_ctrl;
789 ops->is_valid_for_commit = dpu_encoder_phys_wb_is_valid_for_commit;
790
791}
792
793/**
794 * dpu_encoder_phys_wb_init - initialize writeback encoder
795 * @dev: Corresponding device for devres management
796 * @p: Pointer to init info structure with initialization params
797 */
798struct dpu_encoder_phys *dpu_encoder_phys_wb_init(struct drm_device *dev,
799 struct dpu_enc_phys_init_params *p)
800{
801 struct dpu_encoder_phys *phys_enc = NULL;
802 struct dpu_encoder_phys_wb *wb_enc = NULL;
803
804 DPU_DEBUG("\n");
805
806 if (!p || !p->parent) {
807 DPU_ERROR("invalid params\n");
808 return ERR_PTR(-EINVAL);
809 }
810
811 wb_enc = drmm_kzalloc(dev, sizeof(*wb_enc), GFP_KERNEL);
812 if (!wb_enc) {
813 DPU_ERROR("failed to allocate wb phys_enc enc\n");
814 return ERR_PTR(-ENOMEM);
815 }
816
817 phys_enc = &wb_enc->base;
818
819 dpu_encoder_phys_init(phys_enc, p);
820
821 dpu_encoder_phys_wb_init_ops(&phys_enc->ops);
822 phys_enc->intf_mode = INTF_MODE_WB_LINE;
823
824 atomic_set(&wb_enc->wbirq_refcount, 0);
825
826 wb_enc->wb_done_timeout_cnt = 0;
827
828 DPU_DEBUG("Created dpu_encoder_phys for wb %d\n", phys_enc->hw_wb->idx);
829
830 return phys_enc;
831}