1// SPDX-License-Identifier: GPL-2.0-only OR MIT
  2/* Copyright (c) 2023 Imagination Technologies Ltd. */
  3
  4#include "pvr_device.h"
  5#include "pvr_fw_mips.h"
  6#include "pvr_gem.h"
  7#include "pvr_mmu.h"
  8#include "pvr_rogue_mips.h"
  9#include "pvr_vm.h"
 10#include "pvr_vm_mips.h"
 11
 12#include <drm/drm_managed.h>
 13#include <linux/dma-mapping.h>
 14#include <linux/err.h>
 15#include <linux/slab.h>
 16#include <linux/types.h>
 17
 18/**
 19 * pvr_vm_mips_init() - Initialise MIPS FW pagetable
 20 * @pvr_dev: Target PowerVR device.
 21 *
 22 * Returns:
 23 *  * 0 on success,
 24 *  * -%EINVAL,
 25 *  * Any error returned by pvr_gem_object_create(), or
 26 *  * And error returned by pvr_gem_object_vmap().
 27 */
 28int
 29pvr_vm_mips_init(struct pvr_device *pvr_dev)
 30{
 31	u32 pt_size = 1 << ROGUE_MIPSFW_LOG2_PAGETABLE_SIZE_4K(pvr_dev);
 32	struct device *dev = from_pvr_device(pvr_dev)->dev;
 33	struct pvr_fw_mips_data *mips_data;
 34	u32 phys_bus_width;
 35	int page_nr;
 36	int err;
 37
 38	/* Page table size must be at most ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES * 4k pages. */
 39	if (pt_size > ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES * SZ_4K)
 40		return -EINVAL;
 41
 42	if (PVR_FEATURE_VALUE(pvr_dev, phys_bus_width, &phys_bus_width))
 43		return -EINVAL;
 44
 45	mips_data = drmm_kzalloc(from_pvr_device(pvr_dev), sizeof(*mips_data), GFP_KERNEL);
 46	if (!mips_data)
 47		return -ENOMEM;
 48
 49	for (page_nr = 0; page_nr < ARRAY_SIZE(mips_data->pt_pages); page_nr++) {
 50		mips_data->pt_pages[page_nr] = alloc_page(GFP_KERNEL | __GFP_ZERO);
 51		if (!mips_data->pt_pages[page_nr]) {
 52			err = -ENOMEM;
 53			goto err_free_pages;
 54		}
 55
 56		mips_data->pt_dma_addr[page_nr] = dma_map_page(dev, mips_data->pt_pages[page_nr], 0,
 57							       PAGE_SIZE, DMA_TO_DEVICE);
 58		if (dma_mapping_error(dev, mips_data->pt_dma_addr[page_nr])) {
 59			err = -ENOMEM;
 60			__free_page(mips_data->pt_pages[page_nr]);
 61			goto err_free_pages;
 62		}
 63	}
 64
 65	mips_data->pt = vmap(mips_data->pt_pages, pt_size >> PAGE_SHIFT, VM_MAP,
 66			     pgprot_writecombine(PAGE_KERNEL));
 67	if (!mips_data->pt) {
 68		err = -ENOMEM;
 69		goto err_free_pages;
 70	}
 71
 72	mips_data->pfn_mask = (phys_bus_width > 32) ? ROGUE_MIPSFW_ENTRYLO_PFN_MASK_ABOVE_32BIT :
 73						      ROGUE_MIPSFW_ENTRYLO_PFN_MASK;
 74
 75	mips_data->cache_policy = (phys_bus_width > 32) ? ROGUE_MIPSFW_CACHED_POLICY_ABOVE_32BIT :
 76							  ROGUE_MIPSFW_CACHED_POLICY;
 77
 78	pvr_dev->fw_dev.processor_data.mips_data = mips_data;
 79
 80	return 0;
 81
 82err_free_pages:
 83	while (--page_nr >= 0) {
 84		dma_unmap_page(from_pvr_device(pvr_dev)->dev,
 85			       mips_data->pt_dma_addr[page_nr], PAGE_SIZE, DMA_TO_DEVICE);
 86
 87		__free_page(mips_data->pt_pages[page_nr]);
 88	}
 89
 90	return err;
 91}
 92
 93/**
 94 * pvr_vm_mips_fini() - Release MIPS FW pagetable
 95 * @pvr_dev: Target PowerVR device.
 96 */
 97void
 98pvr_vm_mips_fini(struct pvr_device *pvr_dev)
 99{
100	struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev;
101	struct pvr_fw_mips_data *mips_data = fw_dev->processor_data.mips_data;
102	int page_nr;
103
104	vunmap(mips_data->pt);
105	for (page_nr = ARRAY_SIZE(mips_data->pt_pages) - 1; page_nr >= 0; page_nr--) {
106		dma_unmap_page(from_pvr_device(pvr_dev)->dev,
107			       mips_data->pt_dma_addr[page_nr], PAGE_SIZE, DMA_TO_DEVICE);
108
109		__free_page(mips_data->pt_pages[page_nr]);
110	}
111
112	fw_dev->processor_data.mips_data = NULL;
113}
114
115static u32
116get_mips_pte_flags(bool read, bool write, u32 cache_policy)
117{
118	u32 flags = 0;
119
120	if (read && write) /* Read/write. */
121		flags |= ROGUE_MIPSFW_ENTRYLO_DIRTY_EN;
122	else if (write)    /* Write only. */
123		flags |= ROGUE_MIPSFW_ENTRYLO_READ_INHIBIT_EN;
124	else
125		WARN_ON(!read);
126
127	flags |= cache_policy << ROGUE_MIPSFW_ENTRYLO_CACHE_POLICY_SHIFT;
128
129	flags |= ROGUE_MIPSFW_ENTRYLO_VALID_EN | ROGUE_MIPSFW_ENTRYLO_GLOBAL_EN;
130
131	return flags;
132}
133
134/**
135 * pvr_vm_mips_map() - Map a FW object into MIPS address space
136 * @pvr_dev: Target PowerVR device.
137 * @fw_obj: FW object to map.
138 *
139 * Returns:
140 *  * 0 on success,
141 *  * -%EINVAL if object does not reside within FW address space, or
142 *  * Any error returned by pvr_fw_object_get_dma_addr().
143 */
144int
145pvr_vm_mips_map(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj)
146{
147	struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev;
148	struct pvr_fw_mips_data *mips_data = fw_dev->processor_data.mips_data;
149	struct pvr_gem_object *pvr_obj = fw_obj->gem;
150	const u64 start = fw_obj->fw_mm_node.start;
151	const u64 size = fw_obj->fw_mm_node.size;
152	u64 end;
153	u32 cache_policy;
154	u32 pte_flags;
155	s32 start_pfn;
156	s32 end_pfn;
157	s32 pfn;
158	int err;
159
160	if (check_add_overflow(start, size - 1, &end))
161		return -EINVAL;
162
163	if (start < ROGUE_FW_HEAP_BASE ||
164	    start >= ROGUE_FW_HEAP_BASE + fw_dev->fw_heap_info.raw_size ||
165	    end < ROGUE_FW_HEAP_BASE ||
166	    end >= ROGUE_FW_HEAP_BASE + fw_dev->fw_heap_info.raw_size ||
167	    (start & ROGUE_MIPSFW_PAGE_MASK_4K) ||
168	    ((end + 1) & ROGUE_MIPSFW_PAGE_MASK_4K))
169		return -EINVAL;
170
171	start_pfn = (start & fw_dev->fw_heap_info.offset_mask) >> ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K;
172	end_pfn = (end & fw_dev->fw_heap_info.offset_mask) >> ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K;
173
174	if (pvr_obj->flags & PVR_BO_FW_FLAGS_DEVICE_UNCACHED)
175		cache_policy = ROGUE_MIPSFW_UNCACHED_CACHE_POLICY;
176	else
177		cache_policy = mips_data->cache_policy;
178
179	pte_flags = get_mips_pte_flags(true, true, cache_policy);
180
181	for (pfn = start_pfn; pfn <= end_pfn; pfn++) {
182		dma_addr_t dma_addr;
183		u32 pte;
184
185		err = pvr_fw_object_get_dma_addr(fw_obj,
186						 (pfn - start_pfn) <<
187						 ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K,
188						 &dma_addr);
189		if (err)
190			goto err_unmap_pages;
191
192		pte = ((dma_addr >> ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K)
193		       << ROGUE_MIPSFW_ENTRYLO_PFN_SHIFT) & mips_data->pfn_mask;
194		pte |= pte_flags;
195
196		WRITE_ONCE(mips_data->pt[pfn], pte);
197	}
198
199	pvr_mmu_flush_request_all(pvr_dev);
200
201	return 0;
202
203err_unmap_pages:
204	while (--pfn >= start_pfn)
205		WRITE_ONCE(mips_data->pt[pfn], 0);
206
207	pvr_mmu_flush_request_all(pvr_dev);
208	WARN_ON(pvr_mmu_flush_exec(pvr_dev, true));
209
210	return err;
211}
212
213/**
214 * pvr_vm_mips_unmap() - Unmap a FW object into MIPS address space
215 * @pvr_dev: Target PowerVR device.
216 * @fw_obj: FW object to unmap.
217 */
218void
219pvr_vm_mips_unmap(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj)
220{
221	struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev;
222	struct pvr_fw_mips_data *mips_data = fw_dev->processor_data.mips_data;
223	const u64 start = fw_obj->fw_mm_node.start;
224	const u64 size = fw_obj->fw_mm_node.size;
225	const u64 end = start + size;
226
227	const u32 start_pfn = (start & fw_dev->fw_heap_info.offset_mask) >>
228			      ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K;
229	const u32 end_pfn = (end & fw_dev->fw_heap_info.offset_mask) >>
230			    ROGUE_MIPSFW_LOG2_PAGE_SIZE_4K;
231
232	for (u32 pfn = start_pfn; pfn < end_pfn; pfn++)
233		WRITE_ONCE(mips_data->pt[pfn], 0);
234
235	pvr_mmu_flush_request_all(pvr_dev);
236	WARN_ON(pvr_mmu_flush_exec(pvr_dev, true));
237}