1/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
 2/* Copyright (c) 2023 Imagination Technologies Ltd. */
 3
 4#ifndef PVR_FW_MIPS_H
 5#define PVR_FW_MIPS_H
 6
 7#include "pvr_rogue_mips.h"
 8
 9#include <asm/page.h>
10#include <linux/types.h>
11
12/* Forward declaration from pvr_gem.h. */
13struct pvr_gem_object;
14
15#define PVR_MIPS_PT_PAGE_COUNT ((ROGUE_MIPSFW_MAX_NUM_PAGETABLE_PAGES * ROGUE_MIPSFW_PAGE_SIZE_4K) \
16				>> PAGE_SHIFT)
17/**
18 * struct pvr_fw_mips_data - MIPS-specific data
19 */
20struct pvr_fw_mips_data {
21	/**
22	 * @pt_pages: Pages containing MIPS pagetable.
23	 */
24	struct page *pt_pages[PVR_MIPS_PT_PAGE_COUNT];
25
26	/** @pt: Pointer to CPU mapping of MIPS pagetable. */
27	u32 *pt;
28
29	/** @pt_dma_addr: DMA mappings of MIPS pagetable. */
30	dma_addr_t pt_dma_addr[PVR_MIPS_PT_PAGE_COUNT];
31
32	/** @boot_code_dma_addr: DMA address of MIPS boot code. */
33	dma_addr_t boot_code_dma_addr;
34
35	/** @boot_data_dma_addr: DMA address of MIPS boot data. */
36	dma_addr_t boot_data_dma_addr;
37
38	/** @exception_code_dma_addr: DMA address of MIPS exception code. */
39	dma_addr_t exception_code_dma_addr;
40
41	/** @cache_policy: Cache policy for this processor. */
42	u32 cache_policy;
43
44	/** @pfn_mask: PFN mask for MIPS pagetable. */
45	u32 pfn_mask;
46};
47
48#endif /* PVR_FW_MIPS_H */