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1/*
2 * Copyright © 2014-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include "i915_reg.h"
25#include "intel_ddi.h"
26#include "intel_ddi_buf_trans.h"
27#include "intel_de.h"
28#include "intel_display_power_well.h"
29#include "intel_display_types.h"
30#include "intel_dp.h"
31#include "intel_dpio_phy.h"
32#include "vlv_sideband.h"
33
34/**
35 * DOC: DPIO
36 *
37 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
38 * ports. DPIO is the name given to such a display PHY. These PHYs
39 * don't follow the standard programming model using direct MMIO
40 * registers, and instead their registers must be accessed trough IOSF
41 * sideband. VLV has one such PHY for driving ports B and C, and CHV
42 * adds another PHY for driving port D. Each PHY responds to specific
43 * IOSF-SB port.
44 *
45 * Each display PHY is made up of one or two channels. Each channel
46 * houses a common lane part which contains the PLL and other common
47 * logic. CH0 common lane also contains the IOSF-SB logic for the
48 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
49 * must be running when any DPIO registers are accessed.
50 *
51 * In addition to having their own registers, the PHYs are also
52 * controlled through some dedicated signals from the display
53 * controller. These include PLL reference clock enable, PLL enable,
54 * and CRI clock selection, for example.
55 *
56 * Eeach channel also has two splines (also called data lanes), and
57 * each spline is made up of one Physical Access Coding Sub-Layer
58 * (PCS) block and two TX lanes. So each channel has two PCS blocks
59 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
60 * data/clock pairs depending on the output type.
61 *
62 * Additionally the PHY also contains an AUX lane with AUX blocks
63 * for each channel. This is used for DP AUX communication, but
64 * this fact isn't really relevant for the driver since AUX is
65 * controlled from the display controller side. No DPIO registers
66 * need to be accessed during AUX communication,
67 *
68 * Generally on VLV/CHV the common lane corresponds to the pipe and
69 * the spline (PCS/TX) corresponds to the port.
70 *
71 * For dual channel PHY (VLV/CHV):
72 *
73 * pipe A == CMN/PLL/REF CH0
74 *
75 * pipe B == CMN/PLL/REF CH1
76 *
77 * port B == PCS/TX CH0
78 *
79 * port C == PCS/TX CH1
80 *
81 * This is especially important when we cross the streams
82 * ie. drive port B with pipe B, or port C with pipe A.
83 *
84 * For single channel PHY (CHV):
85 *
86 * pipe C == CMN/PLL/REF CH0
87 *
88 * port D == PCS/TX CH0
89 *
90 * On BXT the entire PHY channel corresponds to the port. That means
91 * the PLL is also now associated with the port rather than the pipe,
92 * and so the clock needs to be routed to the appropriate transcoder.
93 * Port A PLL is directly connected to transcoder EDP and port B/C
94 * PLLs can be routed to any transcoder A/B/C.
95 *
96 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
97 * digital port D (CHV) or port A (BXT). ::
98 *
99 *
100 * Dual channel PHY (VLV/CHV/BXT)
101 * ---------------------------------
102 * | CH0 | CH1 |
103 * | CMN/PLL/REF | CMN/PLL/REF |
104 * |---------------|---------------| Display PHY
105 * | PCS01 | PCS23 | PCS01 | PCS23 |
106 * |-------|-------|-------|-------|
107 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
108 * ---------------------------------
109 * | DDI0 | DDI1 | DP/HDMI ports
110 * ---------------------------------
111 *
112 * Single channel PHY (CHV/BXT)
113 * -----------------
114 * | CH0 |
115 * | CMN/PLL/REF |
116 * |---------------| Display PHY
117 * | PCS01 | PCS23 |
118 * |-------|-------|
119 * |TX0|TX1|TX2|TX3|
120 * -----------------
121 * | DDI2 | DP/HDMI port
122 * -----------------
123 */
124
125/**
126 * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
127 */
128struct bxt_ddi_phy_info {
129 /**
130 * @dual_channel: true if this phy has a second channel.
131 */
132 bool dual_channel;
133
134 /**
135 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
136 * Otherwise the GRC value will be copied from the phy indicated by
137 * this field.
138 */
139 enum dpio_phy rcomp_phy;
140
141 /**
142 * @reset_delay: delay in us to wait before setting the common reset
143 * bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy.
144 */
145 int reset_delay;
146
147 /**
148 * @pwron_mask: Mask with the appropriate bit set that would cause the
149 * punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON.
150 */
151 u32 pwron_mask;
152
153 /**
154 * @channel: struct containing per channel information.
155 */
156 struct {
157 /**
158 * @channel.port: which port maps to this channel.
159 */
160 enum port port;
161 } channel[2];
162};
163
164static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
165 [DPIO_PHY0] = {
166 .dual_channel = true,
167 .rcomp_phy = DPIO_PHY1,
168 .pwron_mask = BIT(0),
169
170 .channel = {
171 [DPIO_CH0] = { .port = PORT_B },
172 [DPIO_CH1] = { .port = PORT_C },
173 }
174 },
175 [DPIO_PHY1] = {
176 .dual_channel = false,
177 .rcomp_phy = -1,
178 .pwron_mask = BIT(1),
179
180 .channel = {
181 [DPIO_CH0] = { .port = PORT_A },
182 }
183 },
184};
185
186static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = {
187 [DPIO_PHY0] = {
188 .dual_channel = false,
189 .rcomp_phy = DPIO_PHY1,
190 .pwron_mask = BIT(0),
191 .reset_delay = 20,
192
193 .channel = {
194 [DPIO_CH0] = { .port = PORT_B },
195 }
196 },
197 [DPIO_PHY1] = {
198 .dual_channel = false,
199 .rcomp_phy = -1,
200 .pwron_mask = BIT(3),
201 .reset_delay = 20,
202
203 .channel = {
204 [DPIO_CH0] = { .port = PORT_A },
205 }
206 },
207 [DPIO_PHY2] = {
208 .dual_channel = false,
209 .rcomp_phy = DPIO_PHY1,
210 .pwron_mask = BIT(1),
211 .reset_delay = 20,
212
213 .channel = {
214 [DPIO_CH0] = { .port = PORT_C },
215 }
216 },
217};
218
219static const struct bxt_ddi_phy_info *
220bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
221{
222 if (IS_GEMINILAKE(dev_priv)) {
223 *count = ARRAY_SIZE(glk_ddi_phy_info);
224 return glk_ddi_phy_info;
225 } else {
226 *count = ARRAY_SIZE(bxt_ddi_phy_info);
227 return bxt_ddi_phy_info;
228 }
229}
230
231static const struct bxt_ddi_phy_info *
232bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)
233{
234 int count;
235 const struct bxt_ddi_phy_info *phy_list =
236 bxt_get_phy_list(dev_priv, &count);
237
238 return &phy_list[phy];
239}
240
241void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
242 enum dpio_phy *phy, enum dpio_channel *ch)
243{
244 const struct bxt_ddi_phy_info *phy_info, *phys;
245 int i, count;
246
247 phys = bxt_get_phy_list(dev_priv, &count);
248
249 for (i = 0; i < count; i++) {
250 phy_info = &phys[i];
251
252 if (port == phy_info->channel[DPIO_CH0].port) {
253 *phy = i;
254 *ch = DPIO_CH0;
255 return;
256 }
257
258 if (phy_info->dual_channel &&
259 port == phy_info->channel[DPIO_CH1].port) {
260 *phy = i;
261 *ch = DPIO_CH1;
262 return;
263 }
264 }
265
266 drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c",
267 port_name(port));
268 *phy = DPIO_PHY0;
269 *ch = DPIO_CH0;
270}
271
272void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
273 const struct intel_crtc_state *crtc_state)
274{
275 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
276 int level = intel_ddi_level(encoder, crtc_state, 0);
277 const struct intel_ddi_buf_trans *trans;
278 enum dpio_channel ch;
279 enum dpio_phy phy;
280 int n_entries;
281 u32 val;
282
283 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
284 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
285 return;
286
287 bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch);
288
289 /*
290 * While we write to the group register to program all lanes at once we
291 * can read only lane registers and we pick lanes 0/1 for that.
292 */
293 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch));
294 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
295 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val);
296
297 val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch));
298 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
299 val |= trans->entries[level].bxt.margin << MARGIN_000_SHIFT |
300 trans->entries[level].bxt.scale << UNIQ_TRANS_SCALE_SHIFT;
301 intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val);
302
303 val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch));
304 val &= ~SCALE_DCOMP_METHOD;
305 if (trans->entries[level].bxt.enable)
306 val |= SCALE_DCOMP_METHOD;
307
308 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
309 drm_err(&dev_priv->drm,
310 "Disabled scaling while ouniqetrangenmethod was set");
311
312 intel_de_write(dev_priv, BXT_PORT_TX_DW3_GRP(phy, ch), val);
313
314 val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch));
315 val &= ~DE_EMPHASIS;
316 val |= trans->entries[level].bxt.deemphasis << DEEMPH_SHIFT;
317 intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val);
318
319 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch));
320 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
321 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val);
322}
323
324bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
325 enum dpio_phy phy)
326{
327 const struct bxt_ddi_phy_info *phy_info;
328
329 phy_info = bxt_get_phy_info(dev_priv, phy);
330
331 if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
332 return false;
333
334 if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) &
335 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
336 drm_dbg(&dev_priv->drm,
337 "DDI PHY %d powered, but power hasn't settled\n", phy);
338
339 return false;
340 }
341
342 if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
343 drm_dbg(&dev_priv->drm,
344 "DDI PHY %d powered, but still in reset\n", phy);
345
346 return false;
347 }
348
349 return true;
350}
351
352static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
353{
354 u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy));
355
356 return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
357}
358
359static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
360 enum dpio_phy phy)
361{
362 if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy),
363 GRC_DONE, 10))
364 drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n",
365 phy);
366}
367
368static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
369 enum dpio_phy phy)
370{
371 const struct bxt_ddi_phy_info *phy_info;
372 u32 val;
373
374 phy_info = bxt_get_phy_info(dev_priv, phy);
375
376 if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
377 /* Still read out the GRC value for state verification */
378 if (phy_info->rcomp_phy != -1)
379 dev_priv->display.state.bxt_phy_grc = bxt_get_grc(dev_priv, phy);
380
381 if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
382 drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, "
383 "won't reprogram it\n", phy);
384 return;
385 }
386
387 drm_dbg(&dev_priv->drm,
388 "DDI PHY %d enabled with invalid state, "
389 "force reprogramming it\n", phy);
390 }
391
392 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask);
393
394 /*
395 * The PHY registers start out inaccessible and respond to reads with
396 * all 1s. Eventually they become accessible as they power up, then
397 * the reserved bit will give the default 0. Poll on the reserved bit
398 * becoming 0 to find when the PHY is accessible.
399 * The flag should get set in 100us according to the HW team, but
400 * use 1ms due to occasional timeouts observed with that.
401 */
402 if (intel_wait_for_register_fw(&dev_priv->uncore,
403 BXT_PORT_CL1CM_DW0(phy),
404 PHY_RESERVED | PHY_POWER_GOOD,
405 PHY_POWER_GOOD,
406 1))
407 drm_err(&dev_priv->drm, "timeout during PHY%d power on\n",
408 phy);
409
410 /* Program PLL Rcomp code offset */
411 intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW9(phy), IREF0RC_OFFSET_MASK,
412 0xE4 << IREF0RC_OFFSET_SHIFT);
413
414 intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW10(phy), IREF1RC_OFFSET_MASK,
415 0xE4 << IREF1RC_OFFSET_SHIFT);
416
417 /* Program power gating */
418 intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW28(phy), 0,
419 OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG);
420
421 if (phy_info->dual_channel)
422 intel_de_rmw(dev_priv, BXT_PORT_CL2CM_DW6(phy), 0,
423 DW6_OLDO_DYN_PWR_DOWN_EN);
424
425 if (phy_info->rcomp_phy != -1) {
426 u32 grc_code;
427
428 bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
429
430 /*
431 * PHY0 isn't connected to an RCOMP resistor so copy over
432 * the corresponding calibrated value from PHY1, and disable
433 * the automatic calibration on PHY0.
434 */
435 val = bxt_get_grc(dev_priv, phy_info->rcomp_phy);
436 dev_priv->display.state.bxt_phy_grc = val;
437
438 grc_code = val << GRC_CODE_FAST_SHIFT |
439 val << GRC_CODE_SLOW_SHIFT |
440 val;
441 intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code);
442 intel_de_rmw(dev_priv, BXT_PORT_REF_DW8(phy),
443 0, GRC_DIS | GRC_RDY_OVRD);
444 }
445
446 if (phy_info->reset_delay)
447 udelay(phy_info->reset_delay);
448
449 intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS);
450}
451
452void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
453{
454 const struct bxt_ddi_phy_info *phy_info;
455
456 phy_info = bxt_get_phy_info(dev_priv, phy);
457
458 intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0);
459
460 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0);
461}
462
463void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
464{
465 const struct bxt_ddi_phy_info *phy_info =
466 bxt_get_phy_info(dev_priv, phy);
467 enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
468 bool was_enabled;
469
470 lockdep_assert_held(&dev_priv->display.power.domains.lock);
471
472 was_enabled = true;
473 if (rcomp_phy != -1)
474 was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy);
475
476 /*
477 * We need to copy the GRC calibration value from rcomp_phy,
478 * so make sure it's powered up.
479 */
480 if (!was_enabled)
481 _bxt_ddi_phy_init(dev_priv, rcomp_phy);
482
483 _bxt_ddi_phy_init(dev_priv, phy);
484
485 if (!was_enabled)
486 bxt_ddi_phy_uninit(dev_priv, rcomp_phy);
487}
488
489static bool __printf(6, 7)
490__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
491 i915_reg_t reg, u32 mask, u32 expected,
492 const char *reg_fmt, ...)
493{
494 struct va_format vaf;
495 va_list args;
496 u32 val;
497
498 val = intel_de_read(dev_priv, reg);
499 if ((val & mask) == expected)
500 return true;
501
502 va_start(args, reg_fmt);
503 vaf.fmt = reg_fmt;
504 vaf.va = &args;
505
506 drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: "
507 "current %08x, expected %08x (mask %08x)\n",
508 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
509 mask);
510
511 va_end(args);
512
513 return false;
514}
515
516bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
517 enum dpio_phy phy)
518{
519 const struct bxt_ddi_phy_info *phy_info;
520 u32 mask;
521 bool ok;
522
523 phy_info = bxt_get_phy_info(dev_priv, phy);
524
525#define _CHK(reg, mask, exp, fmt, ...) \
526 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
527 ## __VA_ARGS__)
528
529 if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
530 return false;
531
532 ok = true;
533
534 /* PLL Rcomp code offset */
535 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
536 IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
537 "BXT_PORT_CL1CM_DW9(%d)", phy);
538 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
539 IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
540 "BXT_PORT_CL1CM_DW10(%d)", phy);
541
542 /* Power gating */
543 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
544 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
545 "BXT_PORT_CL1CM_DW28(%d)", phy);
546
547 if (phy_info->dual_channel)
548 ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
549 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
550 "BXT_PORT_CL2CM_DW6(%d)", phy);
551
552 if (phy_info->rcomp_phy != -1) {
553 u32 grc_code = dev_priv->display.state.bxt_phy_grc;
554
555 grc_code = grc_code << GRC_CODE_FAST_SHIFT |
556 grc_code << GRC_CODE_SLOW_SHIFT |
557 grc_code;
558 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
559 GRC_CODE_NOM_MASK;
560 ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
561 "BXT_PORT_REF_DW6(%d)", phy);
562
563 mask = GRC_DIS | GRC_RDY_OVRD;
564 ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
565 "BXT_PORT_REF_DW8(%d)", phy);
566 }
567
568 return ok;
569#undef _CHK
570}
571
572u8
573bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count)
574{
575 switch (lane_count) {
576 case 1:
577 return 0;
578 case 2:
579 return BIT(2) | BIT(0);
580 case 4:
581 return BIT(3) | BIT(2) | BIT(0);
582 default:
583 MISSING_CASE(lane_count);
584
585 return 0;
586 }
587}
588
589void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
590 u8 lane_lat_optim_mask)
591{
592 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
593 enum port port = encoder->port;
594 enum dpio_phy phy;
595 enum dpio_channel ch;
596 int lane;
597
598 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
599
600 for (lane = 0; lane < 4; lane++) {
601 u32 val = intel_de_read(dev_priv,
602 BXT_PORT_TX_DW14_LN(phy, ch, lane));
603
604 /*
605 * Note that on CHV this flag is called UPAR, but has
606 * the same function.
607 */
608 val &= ~LATENCY_OPTIM;
609 if (lane_lat_optim_mask & BIT(lane))
610 val |= LATENCY_OPTIM;
611
612 intel_de_write(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane),
613 val);
614 }
615}
616
617u8
618bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
619{
620 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
621 enum port port = encoder->port;
622 enum dpio_phy phy;
623 enum dpio_channel ch;
624 int lane;
625 u8 mask;
626
627 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
628
629 mask = 0;
630 for (lane = 0; lane < 4; lane++) {
631 u32 val = intel_de_read(dev_priv,
632 BXT_PORT_TX_DW14_LN(phy, ch, lane));
633
634 if (val & LATENCY_OPTIM)
635 mask |= BIT(lane);
636 }
637
638 return mask;
639}
640
641enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
642{
643 switch (dig_port->base.port) {
644 default:
645 MISSING_CASE(dig_port->base.port);
646 fallthrough;
647 case PORT_B:
648 case PORT_D:
649 return DPIO_CH0;
650 case PORT_C:
651 return DPIO_CH1;
652 }
653}
654
655enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
656{
657 switch (dig_port->base.port) {
658 default:
659 MISSING_CASE(dig_port->base.port);
660 fallthrough;
661 case PORT_B:
662 case PORT_C:
663 return DPIO_PHY0;
664 case PORT_D:
665 return DPIO_PHY1;
666 }
667}
668
669enum dpio_phy vlv_pipe_to_phy(enum pipe pipe)
670{
671 switch (pipe) {
672 default:
673 MISSING_CASE(pipe);
674 fallthrough;
675 case PIPE_A:
676 case PIPE_B:
677 return DPIO_PHY0;
678 case PIPE_C:
679 return DPIO_PHY1;
680 }
681}
682
683enum dpio_channel vlv_pipe_to_channel(enum pipe pipe)
684{
685 switch (pipe) {
686 default:
687 MISSING_CASE(pipe);
688 fallthrough;
689 case PIPE_A:
690 case PIPE_C:
691 return DPIO_CH0;
692 case PIPE_B:
693 return DPIO_CH1;
694 }
695}
696
697void chv_set_phy_signal_level(struct intel_encoder *encoder,
698 const struct intel_crtc_state *crtc_state,
699 u32 deemph_reg_value, u32 margin_reg_value,
700 bool uniq_trans_scale)
701{
702 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
703 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
704 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
705 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
706 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
707 u32 val;
708 int i;
709
710 vlv_dpio_get(dev_priv);
711
712 /* Clear calc init */
713 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW10(ch));
714 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
715 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
716 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
717 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW10(ch), val);
718
719 if (crtc_state->lane_count > 2) {
720 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW10(ch));
721 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
722 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
723 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
724 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW10(ch), val);
725 }
726
727 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW9(ch));
728 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
729 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
730 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW9(ch), val);
731
732 if (crtc_state->lane_count > 2) {
733 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW9(ch));
734 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
735 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
736 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW9(ch), val);
737 }
738
739 /* Program swing deemph */
740 for (i = 0; i < crtc_state->lane_count; i++) {
741 val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW4(ch, i));
742 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
743 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
744 vlv_dpio_write(dev_priv, phy, CHV_TX_DW4(ch, i), val);
745 }
746
747 /* Program swing margin */
748 for (i = 0; i < crtc_state->lane_count; i++) {
749 val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW2(ch, i));
750
751 val &= ~DPIO_SWING_MARGIN000_MASK;
752 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
753
754 /*
755 * Supposedly this value shouldn't matter when unique transition
756 * scale is disabled, but in fact it does matter. Let's just
757 * always program the same value and hope it's OK.
758 */
759 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
760 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
761
762 vlv_dpio_write(dev_priv, phy, CHV_TX_DW2(ch, i), val);
763 }
764
765 /*
766 * The document said it needs to set bit 27 for ch0 and bit 26
767 * for ch1. Might be a typo in the doc.
768 * For now, for this unique transition scale selection, set bit
769 * 27 for ch0 and ch1.
770 */
771 for (i = 0; i < crtc_state->lane_count; i++) {
772 val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW3(ch, i));
773 if (uniq_trans_scale)
774 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
775 else
776 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
777 vlv_dpio_write(dev_priv, phy, CHV_TX_DW3(ch, i), val);
778 }
779
780 /* Start swing calculation */
781 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW10(ch));
782 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
783 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW10(ch), val);
784
785 if (crtc_state->lane_count > 2) {
786 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW10(ch));
787 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
788 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW10(ch), val);
789 }
790
791 vlv_dpio_put(dev_priv);
792}
793
794void chv_data_lane_soft_reset(struct intel_encoder *encoder,
795 const struct intel_crtc_state *crtc_state,
796 bool reset)
797{
798 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
799 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
800 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
801 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
802 u32 val;
803
804 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW0(ch));
805 if (reset)
806 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
807 else
808 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
809 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW0(ch), val);
810
811 if (crtc_state->lane_count > 2) {
812 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW0(ch));
813 if (reset)
814 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
815 else
816 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
817 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW0(ch), val);
818 }
819
820 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW1(ch));
821 val |= CHV_PCS_REQ_SOFTRESET_EN;
822 if (reset)
823 val &= ~DPIO_PCS_CLK_SOFT_RESET;
824 else
825 val |= DPIO_PCS_CLK_SOFT_RESET;
826 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW1(ch), val);
827
828 if (crtc_state->lane_count > 2) {
829 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW1(ch));
830 val |= CHV_PCS_REQ_SOFTRESET_EN;
831 if (reset)
832 val &= ~DPIO_PCS_CLK_SOFT_RESET;
833 else
834 val |= DPIO_PCS_CLK_SOFT_RESET;
835 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW1(ch), val);
836 }
837}
838
839void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
840 const struct intel_crtc_state *crtc_state)
841{
842 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
843 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
844 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
845 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
846 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
847 enum pipe pipe = crtc->pipe;
848 unsigned int lane_mask =
849 intel_dp_unused_lane_mask(crtc_state->lane_count);
850 u32 val;
851
852 /*
853 * Must trick the second common lane into life.
854 * Otherwise we can't even access the PLL.
855 */
856 if (ch == DPIO_CH0 && pipe == PIPE_B)
857 dig_port->release_cl2_override =
858 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
859
860 chv_phy_powergate_lanes(encoder, true, lane_mask);
861
862 vlv_dpio_get(dev_priv);
863
864 /* Assert data lane reset */
865 chv_data_lane_soft_reset(encoder, crtc_state, true);
866
867 /* program left/right clock distribution */
868 if (pipe != PIPE_B) {
869 val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW5_CH0);
870 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
871 if (ch == DPIO_CH0)
872 val |= CHV_BUFLEFTENA1_FORCE;
873 if (ch == DPIO_CH1)
874 val |= CHV_BUFRIGHTENA1_FORCE;
875 vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW5_CH0, val);
876 } else {
877 val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW1_CH1);
878 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
879 if (ch == DPIO_CH0)
880 val |= CHV_BUFLEFTENA2_FORCE;
881 if (ch == DPIO_CH1)
882 val |= CHV_BUFRIGHTENA2_FORCE;
883 vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW1_CH1, val);
884 }
885
886 /* program clock channel usage */
887 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(ch));
888 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
889 if (pipe != PIPE_B)
890 val &= ~CHV_PCS_USEDCLKCHANNEL;
891 else
892 val |= CHV_PCS_USEDCLKCHANNEL;
893 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW8(ch), val);
894
895 if (crtc_state->lane_count > 2) {
896 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW8(ch));
897 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
898 if (pipe != PIPE_B)
899 val &= ~CHV_PCS_USEDCLKCHANNEL;
900 else
901 val |= CHV_PCS_USEDCLKCHANNEL;
902 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW8(ch), val);
903 }
904
905 /*
906 * This a a bit weird since generally CL
907 * matches the pipe, but here we need to
908 * pick the CL based on the port.
909 */
910 val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW19(ch));
911 if (pipe != PIPE_B)
912 val &= ~CHV_CMN_USEDCLKCHANNEL;
913 else
914 val |= CHV_CMN_USEDCLKCHANNEL;
915 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW19(ch), val);
916
917 vlv_dpio_put(dev_priv);
918}
919
920void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
921 const struct intel_crtc_state *crtc_state)
922{
923 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
924 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
925 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
926 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
927 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
928 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
929 int data, i, stagger;
930 u32 val;
931
932 vlv_dpio_get(dev_priv);
933
934 /* allow hardware to manage TX FIFO reset source */
935 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW11(ch));
936 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
937 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW11(ch), val);
938
939 if (crtc_state->lane_count > 2) {
940 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW11(ch));
941 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
942 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW11(ch), val);
943 }
944
945 /* Program Tx lane latency optimal setting*/
946 for (i = 0; i < crtc_state->lane_count; i++) {
947 /* Set the upar bit */
948 if (crtc_state->lane_count == 1)
949 data = 0x0;
950 else
951 data = (i == 1) ? 0x0 : 0x1;
952 vlv_dpio_write(dev_priv, phy, CHV_TX_DW14(ch, i),
953 data << DPIO_UPAR_SHIFT);
954 }
955
956 /* Data lane stagger programming */
957 if (crtc_state->port_clock > 270000)
958 stagger = 0x18;
959 else if (crtc_state->port_clock > 135000)
960 stagger = 0xd;
961 else if (crtc_state->port_clock > 67500)
962 stagger = 0x7;
963 else if (crtc_state->port_clock > 33750)
964 stagger = 0x4;
965 else
966 stagger = 0x2;
967
968 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW11(ch));
969 val |= DPIO_TX2_STAGGER_MASK(0x1f);
970 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW11(ch), val);
971
972 if (crtc_state->lane_count > 2) {
973 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW11(ch));
974 val |= DPIO_TX2_STAGGER_MASK(0x1f);
975 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW11(ch), val);
976 }
977
978 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW12(ch),
979 DPIO_LANESTAGGER_STRAP(stagger) |
980 DPIO_LANESTAGGER_STRAP_OVRD |
981 DPIO_TX1_STAGGER_MASK(0x1f) |
982 DPIO_TX1_STAGGER_MULT(6) |
983 DPIO_TX2_STAGGER_MULT(0));
984
985 if (crtc_state->lane_count > 2) {
986 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW12(ch),
987 DPIO_LANESTAGGER_STRAP(stagger) |
988 DPIO_LANESTAGGER_STRAP_OVRD |
989 DPIO_TX1_STAGGER_MASK(0x1f) |
990 DPIO_TX1_STAGGER_MULT(7) |
991 DPIO_TX2_STAGGER_MULT(5));
992 }
993
994 /* Deassert data lane reset */
995 chv_data_lane_soft_reset(encoder, crtc_state, false);
996
997 vlv_dpio_put(dev_priv);
998}
999
1000void chv_phy_release_cl2_override(struct intel_encoder *encoder)
1001{
1002 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1003 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1004
1005 if (dig_port->release_cl2_override) {
1006 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
1007 dig_port->release_cl2_override = false;
1008 }
1009}
1010
1011void chv_phy_post_pll_disable(struct intel_encoder *encoder,
1012 const struct intel_crtc_state *old_crtc_state)
1013{
1014 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1015 enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe;
1016 enum dpio_phy phy = vlv_pipe_to_phy(pipe);
1017 u32 val;
1018
1019 vlv_dpio_get(dev_priv);
1020
1021 /* disable left/right clock distribution */
1022 if (pipe != PIPE_B) {
1023 val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW5_CH0);
1024 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1025 vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW5_CH0, val);
1026 } else {
1027 val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW1_CH1);
1028 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1029 vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW1_CH1, val);
1030 }
1031
1032 vlv_dpio_put(dev_priv);
1033
1034 /*
1035 * Leave the power down bit cleared for at least one
1036 * lane so that chv_powergate_phy_ch() will power
1037 * on something when the channel is otherwise unused.
1038 * When the port is off and the override is removed
1039 * the lanes power down anyway, so otherwise it doesn't
1040 * really matter what the state of power down bits is
1041 * after this.
1042 */
1043 chv_phy_powergate_lanes(encoder, false, 0x0);
1044}
1045
1046void vlv_set_phy_signal_level(struct intel_encoder *encoder,
1047 const struct intel_crtc_state *crtc_state,
1048 u32 demph_reg_value, u32 preemph_reg_value,
1049 u32 uniqtranscale_reg_value, u32 tx3_demph)
1050{
1051 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1052 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1053 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1054 enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1055 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
1056
1057 vlv_dpio_get(dev_priv);
1058
1059 vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), 0x00000000);
1060 vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(port), demph_reg_value);
1061 vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(port),
1062 uniqtranscale_reg_value);
1063 vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(port), 0x0C782040);
1064
1065 if (tx3_demph)
1066 vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(port), tx3_demph);
1067
1068 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(port), 0x00030000);
1069 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(port), preemph_reg_value);
1070 vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1071
1072 vlv_dpio_put(dev_priv);
1073}
1074
1075void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
1076 const struct intel_crtc_state *crtc_state)
1077{
1078 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1079 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1080 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1081 enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1082 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
1083
1084 /* Program Tx lane resets to default */
1085 vlv_dpio_get(dev_priv);
1086
1087 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port),
1088 DPIO_PCS_TX_LANE2_RESET |
1089 DPIO_PCS_TX_LANE1_RESET);
1090 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port),
1091 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1092 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1093 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1094 DPIO_PCS_CLK_SOFT_RESET);
1095
1096 /* Fix up inter-pair skew failure */
1097 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12(port), 0x00750f00);
1098 vlv_dpio_write(dev_priv, phy, VLV_TX_DW11(port), 0x00001500);
1099 vlv_dpio_write(dev_priv, phy, VLV_TX_DW14(port), 0x40400000);
1100
1101 vlv_dpio_put(dev_priv);
1102}
1103
1104void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
1105 const struct intel_crtc_state *crtc_state)
1106{
1107 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1108 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1109 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1110 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1111 enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1112 enum pipe pipe = crtc->pipe;
1113 enum dpio_phy phy = vlv_pipe_to_phy(pipe);
1114 u32 val;
1115
1116 vlv_dpio_get(dev_priv);
1117
1118 /* Enable clock channels for this port */
1119 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(port));
1120 val = 0;
1121 if (pipe)
1122 val |= (1<<21);
1123 else
1124 val &= ~(1<<21);
1125 val |= 0x001000c4;
1126 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(port), val);
1127
1128 /* Program lane clock */
1129 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(port), 0x00760018);
1130 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(port), 0x00400888);
1131
1132 vlv_dpio_put(dev_priv);
1133}
1134
1135void vlv_phy_reset_lanes(struct intel_encoder *encoder,
1136 const struct intel_crtc_state *old_crtc_state)
1137{
1138 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1139 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1140 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1141 enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1142 enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe);
1143
1144 vlv_dpio_get(dev_priv);
1145 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port), 0x00000000);
1146 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port), 0x00e00060);
1147 vlv_dpio_put(dev_priv);
1148}