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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * DesignWare High-Definition Multimedia Interface (HDMI) driver
4 *
5 * Copyright (C) 2013-2015 Mentor Graphics Inc.
6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
8 */
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/err.h>
12#include <linux/hdmi.h>
13#include <linux/i2c.h>
14#include <linux/irq.h>
15#include <linux/module.h>
16#include <linux/mutex.h>
17#include <linux/of.h>
18#include <linux/pinctrl/consumer.h>
19#include <linux/regmap.h>
20#include <linux/dma-mapping.h>
21#include <linux/spinlock.h>
22
23#include <media/cec-notifier.h>
24
25#include <uapi/linux/media-bus-format.h>
26#include <uapi/linux/videodev2.h>
27
28#include <drm/bridge/dw_hdmi.h>
29#include <drm/display/drm_hdmi_helper.h>
30#include <drm/display/drm_scdc_helper.h>
31#include <drm/drm_atomic.h>
32#include <drm/drm_atomic_helper.h>
33#include <drm/drm_bridge.h>
34#include <drm/drm_of.h>
35#include <drm/drm_print.h>
36#include <drm/drm_probe_helper.h>
37
38#include "dw-hdmi-audio.h"
39#include "dw-hdmi-cec.h"
40#include "dw-hdmi.h"
41
42#define DDC_CI_ADDR 0x37
43#define DDC_SEGMENT_ADDR 0x30
44
45#define HDMI_EDID_LEN 512
46
47/* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */
48#define SCDC_MIN_SOURCE_VERSION 0x1
49
50#define HDMI14_MAX_TMDSCLK 340000000
51
52static const u16 csc_coeff_default[3][4] = {
53 { 0x2000, 0x0000, 0x0000, 0x0000 },
54 { 0x0000, 0x2000, 0x0000, 0x0000 },
55 { 0x0000, 0x0000, 0x2000, 0x0000 }
56};
57
58static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
59 { 0x2000, 0x6926, 0x74fd, 0x010e },
60 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
61 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
62};
63
64static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
65 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
66 { 0x2000, 0x3264, 0x0000, 0x7e6d },
67 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
68};
69
70static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
71 { 0x2591, 0x1322, 0x074b, 0x0000 },
72 { 0x6535, 0x2000, 0x7acc, 0x0200 },
73 { 0x6acd, 0x7534, 0x2000, 0x0200 }
74};
75
76static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
77 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
78 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
79 { 0x6756, 0x78ab, 0x2000, 0x0200 }
80};
81
82static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = {
83 { 0x1b7c, 0x0000, 0x0000, 0x0020 },
84 { 0x0000, 0x1b7c, 0x0000, 0x0020 },
85 { 0x0000, 0x0000, 0x1b7c, 0x0020 }
86};
87
88struct hdmi_vmode {
89 bool mdataenablepolarity;
90
91 unsigned int mpixelclock;
92 unsigned int mpixelrepetitioninput;
93 unsigned int mpixelrepetitionoutput;
94 unsigned int mtmdsclock;
95};
96
97struct hdmi_data_info {
98 unsigned int enc_in_bus_format;
99 unsigned int enc_out_bus_format;
100 unsigned int enc_in_encoding;
101 unsigned int enc_out_encoding;
102 unsigned int pix_repet_factor;
103 unsigned int hdcp_enable;
104 struct hdmi_vmode video_mode;
105 bool rgb_limited_range;
106};
107
108struct dw_hdmi_i2c {
109 struct i2c_adapter adap;
110
111 struct mutex lock; /* used to serialize data transfers */
112 struct completion cmp;
113 u8 stat;
114
115 u8 slave_reg;
116 bool is_regaddr;
117 bool is_segment;
118};
119
120struct dw_hdmi_phy_data {
121 enum dw_hdmi_phy_type type;
122 const char *name;
123 unsigned int gen;
124 bool has_svsret;
125 int (*configure)(struct dw_hdmi *hdmi,
126 const struct dw_hdmi_plat_data *pdata,
127 unsigned long mpixelclock);
128};
129
130struct dw_hdmi {
131 struct drm_connector connector;
132 struct drm_bridge bridge;
133 struct drm_bridge *next_bridge;
134
135 unsigned int version;
136
137 struct platform_device *audio;
138 struct platform_device *cec;
139 struct device *dev;
140 struct clk *isfr_clk;
141 struct clk *iahb_clk;
142 struct clk *cec_clk;
143 struct dw_hdmi_i2c *i2c;
144
145 struct hdmi_data_info hdmi_data;
146 const struct dw_hdmi_plat_data *plat_data;
147
148 int vic;
149
150 u8 edid[HDMI_EDID_LEN];
151
152 struct {
153 const struct dw_hdmi_phy_ops *ops;
154 const char *name;
155 void *data;
156 bool enabled;
157 } phy;
158
159 struct drm_display_mode previous_mode;
160
161 struct i2c_adapter *ddc;
162 void __iomem *regs;
163 bool sink_is_hdmi;
164 bool sink_has_audio;
165
166 struct pinctrl *pinctrl;
167 struct pinctrl_state *default_state;
168 struct pinctrl_state *unwedge_state;
169
170 struct mutex mutex; /* for state below and previous_mode */
171 enum drm_connector_force force; /* mutex-protected force state */
172 struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */
173 bool disabled; /* DRM has disabled our bridge */
174 bool bridge_is_on; /* indicates the bridge is on */
175 bool rxsense; /* rxsense state */
176 u8 phy_mask; /* desired phy int mask settings */
177 u8 mc_clkdis; /* clock disable register */
178
179 spinlock_t audio_lock;
180 struct mutex audio_mutex;
181 unsigned int sample_non_pcm;
182 unsigned int sample_width;
183 unsigned int sample_rate;
184 unsigned int channels;
185 unsigned int audio_cts;
186 unsigned int audio_n;
187 bool audio_enable;
188
189 unsigned int reg_shift;
190 struct regmap *regm;
191 void (*enable_audio)(struct dw_hdmi *hdmi);
192 void (*disable_audio)(struct dw_hdmi *hdmi);
193
194 struct mutex cec_notifier_mutex;
195 struct cec_notifier *cec_notifier;
196
197 hdmi_codec_plugged_cb plugged_cb;
198 struct device *codec_dev;
199 enum drm_connector_status last_connector_result;
200};
201
202#define HDMI_IH_PHY_STAT0_RX_SENSE \
203 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
204 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
205
206#define HDMI_PHY_RX_SENSE \
207 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
208 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
209
210static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
211{
212 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val);
213}
214
215static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
216{
217 unsigned int val = 0;
218
219 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val);
220
221 return val;
222}
223
224static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged)
225{
226 if (hdmi->plugged_cb && hdmi->codec_dev)
227 hdmi->plugged_cb(hdmi->codec_dev, plugged);
228}
229
230int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
231 struct device *codec_dev)
232{
233 bool plugged;
234
235 mutex_lock(&hdmi->mutex);
236 hdmi->plugged_cb = fn;
237 hdmi->codec_dev = codec_dev;
238 plugged = hdmi->last_connector_result == connector_status_connected;
239 handle_plugged_change(hdmi, plugged);
240 mutex_unlock(&hdmi->mutex);
241
242 return 0;
243}
244EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb);
245
246static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
247{
248 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data);
249}
250
251static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
252 u8 shift, u8 mask)
253{
254 hdmi_modb(hdmi, data << shift, mask, reg);
255}
256
257static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
258{
259 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
260 HDMI_PHY_I2CM_INT_ADDR);
261
262 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
263 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
264 HDMI_PHY_I2CM_CTLINT_ADDR);
265
266 /* Software reset */
267 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
268
269 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */
270 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
271
272 /* Set done, not acknowledged and arbitration interrupt polarities */
273 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
274 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
275 HDMI_I2CM_CTLINT);
276
277 /* Clear DONE and ERROR interrupts */
278 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
279 HDMI_IH_I2CM_STAT0);
280
281 /* Mute DONE and ERROR interrupts */
282 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
283 HDMI_IH_MUTE_I2CM_STAT0);
284}
285
286static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi)
287{
288 /* If no unwedge state then give up */
289 if (!hdmi->unwedge_state)
290 return false;
291
292 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n");
293
294 /*
295 * This is a huge hack to workaround a problem where the dw_hdmi i2c
296 * bus could sometimes get wedged. Once wedged there doesn't appear
297 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ)
298 * other than pulsing the SDA line.
299 *
300 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi)
301 * by:
302 * 1. Remux the pin as a GPIO output, driven low.
303 * 2. Wait a little while. 1 ms seems to work, but we'll do 10.
304 * 3. Immediately jump to remux the pin as dw_hdmi i2c again.
305 *
306 * At the moment of remuxing, the line will still be low due to its
307 * recent stint as an output, but then it will be pulled high by the
308 * (presumed) external pullup. dw_hdmi seems to see this as a rising
309 * edge and that seems to get it out of its jam.
310 *
311 * This wedging was only ever seen on one TV, and only on one of
312 * its HDMI ports. It happened when the TV was powered on while the
313 * device was plugged in. A scope trace shows the TV bringing both SDA
314 * and SCL low, then bringing them both back up at roughly the same
315 * time. Presumably this confuses dw_hdmi because it saw activity but
316 * no real STOP (maybe it thinks there's another master on the bus?).
317 * Giving it a clean rising edge of SDA while SCL is already high
318 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out
319 * of its stupor.
320 *
321 * Note that after coming back alive, transfers seem to immediately
322 * resume, so if we unwedge due to a timeout we should wait a little
323 * longer for our transfer to finish, since it might have just started
324 * now.
325 */
326 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state);
327 msleep(10);
328 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state);
329
330 return true;
331}
332
333static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi)
334{
335 struct dw_hdmi_i2c *i2c = hdmi->i2c;
336 int stat;
337
338 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
339 if (!stat) {
340 /* If we can't unwedge, return timeout */
341 if (!dw_hdmi_i2c_unwedge(hdmi))
342 return -EAGAIN;
343
344 /* We tried to unwedge; give it another chance */
345 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
346 if (!stat)
347 return -EAGAIN;
348 }
349
350 /* Check for error condition on the bus */
351 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
352 return -EIO;
353
354 return 0;
355}
356
357static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
358 unsigned char *buf, unsigned int length)
359{
360 struct dw_hdmi_i2c *i2c = hdmi->i2c;
361 int ret;
362
363 if (!i2c->is_regaddr) {
364 dev_dbg(hdmi->dev, "set read register address to 0\n");
365 i2c->slave_reg = 0x00;
366 i2c->is_regaddr = true;
367 }
368
369 while (length--) {
370 reinit_completion(&i2c->cmp);
371
372 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
373 if (i2c->is_segment)
374 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
375 HDMI_I2CM_OPERATION);
376 else
377 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
378 HDMI_I2CM_OPERATION);
379
380 ret = dw_hdmi_i2c_wait(hdmi);
381 if (ret)
382 return ret;
383
384 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
385 }
386 i2c->is_segment = false;
387
388 return 0;
389}
390
391static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
392 unsigned char *buf, unsigned int length)
393{
394 struct dw_hdmi_i2c *i2c = hdmi->i2c;
395 int ret;
396
397 if (!i2c->is_regaddr) {
398 /* Use the first write byte as register address */
399 i2c->slave_reg = buf[0];
400 length--;
401 buf++;
402 i2c->is_regaddr = true;
403 }
404
405 while (length--) {
406 reinit_completion(&i2c->cmp);
407
408 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
409 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
410 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
411 HDMI_I2CM_OPERATION);
412
413 ret = dw_hdmi_i2c_wait(hdmi);
414 if (ret)
415 return ret;
416 }
417
418 return 0;
419}
420
421static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
422 struct i2c_msg *msgs, int num)
423{
424 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
425 struct dw_hdmi_i2c *i2c = hdmi->i2c;
426 u8 addr = msgs[0].addr;
427 int i, ret = 0;
428
429 if (addr == DDC_CI_ADDR)
430 /*
431 * The internal I2C controller does not support the multi-byte
432 * read and write operations needed for DDC/CI.
433 * TOFIX: Blacklist the DDC/CI address until we filter out
434 * unsupported I2C operations.
435 */
436 return -EOPNOTSUPP;
437
438 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
439
440 for (i = 0; i < num; i++) {
441 if (msgs[i].len == 0) {
442 dev_dbg(hdmi->dev,
443 "unsupported transfer %d/%d, no data\n",
444 i + 1, num);
445 return -EOPNOTSUPP;
446 }
447 }
448
449 mutex_lock(&i2c->lock);
450
451 /* Unmute DONE and ERROR interrupts */
452 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
453
454 /* Set slave device address taken from the first I2C message */
455 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
456
457 /* Set slave device register address on transfer */
458 i2c->is_regaddr = false;
459
460 /* Set segment pointer for I2C extended read mode operation */
461 i2c->is_segment = false;
462
463 for (i = 0; i < num; i++) {
464 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
465 i + 1, num, msgs[i].len, msgs[i].flags);
466 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
467 i2c->is_segment = true;
468 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
469 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
470 } else {
471 if (msgs[i].flags & I2C_M_RD)
472 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
473 msgs[i].len);
474 else
475 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
476 msgs[i].len);
477 }
478 if (ret < 0)
479 break;
480 }
481
482 if (!ret)
483 ret = num;
484
485 /* Mute DONE and ERROR interrupts */
486 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
487 HDMI_IH_MUTE_I2CM_STAT0);
488
489 mutex_unlock(&i2c->lock);
490
491 return ret;
492}
493
494static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
495{
496 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
497}
498
499static const struct i2c_algorithm dw_hdmi_algorithm = {
500 .master_xfer = dw_hdmi_i2c_xfer,
501 .functionality = dw_hdmi_i2c_func,
502};
503
504static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
505{
506 struct i2c_adapter *adap;
507 struct dw_hdmi_i2c *i2c;
508 int ret;
509
510 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
511 if (!i2c)
512 return ERR_PTR(-ENOMEM);
513
514 mutex_init(&i2c->lock);
515 init_completion(&i2c->cmp);
516
517 adap = &i2c->adap;
518 adap->owner = THIS_MODULE;
519 adap->dev.parent = hdmi->dev;
520 adap->algo = &dw_hdmi_algorithm;
521 strscpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
522 i2c_set_adapdata(adap, hdmi);
523
524 ret = i2c_add_adapter(adap);
525 if (ret) {
526 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
527 devm_kfree(hdmi->dev, i2c);
528 return ERR_PTR(ret);
529 }
530
531 hdmi->i2c = i2c;
532
533 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
534
535 return adap;
536}
537
538static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
539 unsigned int n)
540{
541 /* Must be set/cleared first */
542 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
543
544 /* nshift factor = 0 */
545 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
546
547 /* Use automatic CTS generation mode when CTS is not set */
548 if (cts)
549 hdmi_writeb(hdmi, ((cts >> 16) &
550 HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
551 HDMI_AUD_CTS3_CTS_MANUAL,
552 HDMI_AUD_CTS3);
553 else
554 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3);
555 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
556 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
557
558 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
559 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
560 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
561}
562
563static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
564{
565 unsigned int n = (128 * freq) / 1000;
566 unsigned int mult = 1;
567
568 while (freq > 48000) {
569 mult *= 2;
570 freq /= 2;
571 }
572
573 switch (freq) {
574 case 32000:
575 if (pixel_clk == 25175000)
576 n = 4576;
577 else if (pixel_clk == 27027000)
578 n = 4096;
579 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
580 n = 11648;
581 else if (pixel_clk == 297000000)
582 n = 3072;
583 else
584 n = 4096;
585 n *= mult;
586 break;
587
588 case 44100:
589 if (pixel_clk == 25175000)
590 n = 7007;
591 else if (pixel_clk == 74176000)
592 n = 17836;
593 else if (pixel_clk == 148352000)
594 n = 8918;
595 else if (pixel_clk == 297000000)
596 n = 4704;
597 else
598 n = 6272;
599 n *= mult;
600 break;
601
602 case 48000:
603 if (pixel_clk == 25175000)
604 n = 6864;
605 else if (pixel_clk == 27027000)
606 n = 6144;
607 else if (pixel_clk == 74176000)
608 n = 11648;
609 else if (pixel_clk == 148352000)
610 n = 5824;
611 else if (pixel_clk == 297000000)
612 n = 5120;
613 else
614 n = 6144;
615 n *= mult;
616 break;
617
618 default:
619 break;
620 }
621
622 return n;
623}
624
625/*
626 * When transmitting IEC60958 linear PCM audio, these registers allow to
627 * configure the channel status information of all the channel status
628 * bits in the IEC60958 frame. For the moment this configuration is only
629 * used when the I2S audio interface, General Purpose Audio (GPA),
630 * or AHB audio DMA (AHBAUDDMA) interface is active
631 * (for S/PDIF interface this information comes from the stream).
632 */
633void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi,
634 u8 *channel_status)
635{
636 /*
637 * Set channel status register for frequency and word length.
638 * Use default values for other registers.
639 */
640 hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7);
641 hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8);
642}
643EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status);
644
645static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
646 unsigned long pixel_clk, unsigned int sample_rate)
647{
648 unsigned long ftdms = pixel_clk;
649 unsigned int n, cts;
650 u8 config3;
651 u64 tmp;
652
653 n = hdmi_compute_n(sample_rate, pixel_clk);
654
655 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
656
657 /* Compute CTS when using internal AHB audio or General Parallel audio*/
658 if ((config3 & HDMI_CONFIG3_AHBAUDDMA) || (config3 & HDMI_CONFIG3_GPAUD)) {
659 /*
660 * Compute the CTS value from the N value. Note that CTS and N
661 * can be up to 20 bits in total, so we need 64-bit math. Also
662 * note that our TDMS clock is not fully accurate; it is
663 * accurate to kHz. This can introduce an unnecessary remainder
664 * in the calculation below, so we don't try to warn about that.
665 */
666 tmp = (u64)ftdms * n;
667 do_div(tmp, 128 * sample_rate);
668 cts = tmp;
669
670 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
671 __func__, sample_rate,
672 ftdms / 1000000, (ftdms / 1000) % 1000,
673 n, cts);
674 } else {
675 cts = 0;
676 }
677
678 spin_lock_irq(&hdmi->audio_lock);
679 hdmi->audio_n = n;
680 hdmi->audio_cts = cts;
681 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
682 spin_unlock_irq(&hdmi->audio_lock);
683}
684
685static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
686{
687 mutex_lock(&hdmi->audio_mutex);
688 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
689 mutex_unlock(&hdmi->audio_mutex);
690}
691
692static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
693{
694 mutex_lock(&hdmi->audio_mutex);
695 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
696 hdmi->sample_rate);
697 mutex_unlock(&hdmi->audio_mutex);
698}
699
700void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width)
701{
702 mutex_lock(&hdmi->audio_mutex);
703 hdmi->sample_width = width;
704 mutex_unlock(&hdmi->audio_mutex);
705}
706EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_width);
707
708void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm)
709{
710 mutex_lock(&hdmi->audio_mutex);
711 hdmi->sample_non_pcm = non_pcm;
712 mutex_unlock(&hdmi->audio_mutex);
713}
714EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_non_pcm);
715
716void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
717{
718 mutex_lock(&hdmi->audio_mutex);
719 hdmi->sample_rate = rate;
720 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock,
721 hdmi->sample_rate);
722 mutex_unlock(&hdmi->audio_mutex);
723}
724EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
725
726void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt)
727{
728 u8 layout;
729
730 mutex_lock(&hdmi->audio_mutex);
731 hdmi->channels = cnt;
732
733 /*
734 * For >2 channel PCM audio, we need to select layout 1
735 * and set an appropriate channel map.
736 */
737 if (cnt > 2)
738 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1;
739 else
740 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0;
741
742 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK,
743 HDMI_FC_AUDSCONF);
744
745 /* Set the audio infoframes channel count */
746 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET,
747 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0);
748
749 mutex_unlock(&hdmi->audio_mutex);
750}
751EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count);
752
753void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca)
754{
755 mutex_lock(&hdmi->audio_mutex);
756
757 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2);
758
759 mutex_unlock(&hdmi->audio_mutex);
760}
761EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation);
762
763static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable)
764{
765 if (enable)
766 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE;
767 else
768 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE;
769 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
770}
771
772static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi)
773{
774 if (!hdmi->curr_conn)
775 return NULL;
776
777 return hdmi->curr_conn->eld;
778}
779
780static void dw_hdmi_gp_audio_enable(struct dw_hdmi *hdmi)
781{
782 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
783 int sample_freq = 0x2, org_sample_freq = 0xD;
784 int ch_mask = BIT(hdmi->channels) - 1;
785
786 switch (hdmi->sample_rate) {
787 case 32000:
788 sample_freq = 0x03;
789 org_sample_freq = 0x0C;
790 break;
791 case 44100:
792 sample_freq = 0x00;
793 org_sample_freq = 0x0F;
794 break;
795 case 48000:
796 sample_freq = 0x02;
797 org_sample_freq = 0x0D;
798 break;
799 case 88200:
800 sample_freq = 0x08;
801 org_sample_freq = 0x07;
802 break;
803 case 96000:
804 sample_freq = 0x0A;
805 org_sample_freq = 0x05;
806 break;
807 case 176400:
808 sample_freq = 0x0C;
809 org_sample_freq = 0x03;
810 break;
811 case 192000:
812 sample_freq = 0x0E;
813 org_sample_freq = 0x01;
814 break;
815 default:
816 break;
817 }
818
819 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
820 hdmi_enable_audio_clk(hdmi, true);
821
822 hdmi_writeb(hdmi, 0x1, HDMI_FC_AUDSCHNLS0);
823 hdmi_writeb(hdmi, hdmi->channels, HDMI_FC_AUDSCHNLS2);
824 hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS3);
825 hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS4);
826 hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS5);
827 hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS6);
828 hdmi_writeb(hdmi, (0x3 << 4) | sample_freq, HDMI_FC_AUDSCHNLS7);
829 hdmi_writeb(hdmi, (org_sample_freq << 4) | 0xb, HDMI_FC_AUDSCHNLS8);
830
831 hdmi_writeb(hdmi, ch_mask, HDMI_GP_CONF1);
832 hdmi_writeb(hdmi, 0x02, HDMI_GP_CONF2);
833 hdmi_writeb(hdmi, 0x01, HDMI_GP_CONF0);
834
835 hdmi_modb(hdmi, 0x3, 0x3, HDMI_FC_DATAUTO3);
836
837 /* hbr */
838 if (hdmi->sample_rate == 192000 && hdmi->channels == 8 &&
839 hdmi->sample_width == 32 && hdmi->sample_non_pcm)
840 hdmi_modb(hdmi, 0x01, 0x01, HDMI_GP_CONF2);
841
842 if (pdata->enable_audio)
843 pdata->enable_audio(hdmi,
844 hdmi->channels,
845 hdmi->sample_width,
846 hdmi->sample_rate,
847 hdmi->sample_non_pcm);
848}
849
850static void dw_hdmi_gp_audio_disable(struct dw_hdmi *hdmi)
851{
852 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
853
854 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
855
856 hdmi_modb(hdmi, 0, 0x3, HDMI_FC_DATAUTO3);
857 if (pdata->disable_audio)
858 pdata->disable_audio(hdmi);
859
860 hdmi_enable_audio_clk(hdmi, false);
861}
862
863static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi)
864{
865 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
866}
867
868static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi)
869{
870 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
871}
872
873static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi)
874{
875 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
876 hdmi_enable_audio_clk(hdmi, true);
877}
878
879static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi)
880{
881 hdmi_enable_audio_clk(hdmi, false);
882}
883
884void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
885{
886 unsigned long flags;
887
888 spin_lock_irqsave(&hdmi->audio_lock, flags);
889 hdmi->audio_enable = true;
890 if (hdmi->enable_audio)
891 hdmi->enable_audio(hdmi);
892 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
893}
894EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
895
896void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
897{
898 unsigned long flags;
899
900 spin_lock_irqsave(&hdmi->audio_lock, flags);
901 hdmi->audio_enable = false;
902 if (hdmi->disable_audio)
903 hdmi->disable_audio(hdmi);
904 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
905}
906EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
907
908static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
909{
910 switch (bus_format) {
911 case MEDIA_BUS_FMT_RGB888_1X24:
912 case MEDIA_BUS_FMT_RGB101010_1X30:
913 case MEDIA_BUS_FMT_RGB121212_1X36:
914 case MEDIA_BUS_FMT_RGB161616_1X48:
915 return true;
916
917 default:
918 return false;
919 }
920}
921
922static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
923{
924 switch (bus_format) {
925 case MEDIA_BUS_FMT_YUV8_1X24:
926 case MEDIA_BUS_FMT_YUV10_1X30:
927 case MEDIA_BUS_FMT_YUV12_1X36:
928 case MEDIA_BUS_FMT_YUV16_1X48:
929 return true;
930
931 default:
932 return false;
933 }
934}
935
936static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
937{
938 switch (bus_format) {
939 case MEDIA_BUS_FMT_UYVY8_1X16:
940 case MEDIA_BUS_FMT_UYVY10_1X20:
941 case MEDIA_BUS_FMT_UYVY12_1X24:
942 return true;
943
944 default:
945 return false;
946 }
947}
948
949static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
950{
951 switch (bus_format) {
952 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
953 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
954 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
955 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
956 return true;
957
958 default:
959 return false;
960 }
961}
962
963static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
964{
965 switch (bus_format) {
966 case MEDIA_BUS_FMT_RGB888_1X24:
967 case MEDIA_BUS_FMT_YUV8_1X24:
968 case MEDIA_BUS_FMT_UYVY8_1X16:
969 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
970 return 8;
971
972 case MEDIA_BUS_FMT_RGB101010_1X30:
973 case MEDIA_BUS_FMT_YUV10_1X30:
974 case MEDIA_BUS_FMT_UYVY10_1X20:
975 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
976 return 10;
977
978 case MEDIA_BUS_FMT_RGB121212_1X36:
979 case MEDIA_BUS_FMT_YUV12_1X36:
980 case MEDIA_BUS_FMT_UYVY12_1X24:
981 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
982 return 12;
983
984 case MEDIA_BUS_FMT_RGB161616_1X48:
985 case MEDIA_BUS_FMT_YUV16_1X48:
986 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
987 return 16;
988
989 default:
990 return 0;
991 }
992}
993
994/*
995 * this submodule is responsible for the video data synchronization.
996 * for example, for RGB 4:4:4 input, the data map is defined as
997 * pin{47~40} <==> R[7:0]
998 * pin{31~24} <==> G[7:0]
999 * pin{15~8} <==> B[7:0]
1000 */
1001static void hdmi_video_sample(struct dw_hdmi *hdmi)
1002{
1003 int color_format = 0;
1004 u8 val;
1005
1006 switch (hdmi->hdmi_data.enc_in_bus_format) {
1007 case MEDIA_BUS_FMT_RGB888_1X24:
1008 color_format = 0x01;
1009 break;
1010 case MEDIA_BUS_FMT_RGB101010_1X30:
1011 color_format = 0x03;
1012 break;
1013 case MEDIA_BUS_FMT_RGB121212_1X36:
1014 color_format = 0x05;
1015 break;
1016 case MEDIA_BUS_FMT_RGB161616_1X48:
1017 color_format = 0x07;
1018 break;
1019
1020 case MEDIA_BUS_FMT_YUV8_1X24:
1021 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1022 color_format = 0x09;
1023 break;
1024 case MEDIA_BUS_FMT_YUV10_1X30:
1025 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
1026 color_format = 0x0B;
1027 break;
1028 case MEDIA_BUS_FMT_YUV12_1X36:
1029 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
1030 color_format = 0x0D;
1031 break;
1032 case MEDIA_BUS_FMT_YUV16_1X48:
1033 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
1034 color_format = 0x0F;
1035 break;
1036
1037 case MEDIA_BUS_FMT_UYVY8_1X16:
1038 color_format = 0x16;
1039 break;
1040 case MEDIA_BUS_FMT_UYVY10_1X20:
1041 color_format = 0x14;
1042 break;
1043 case MEDIA_BUS_FMT_UYVY12_1X24:
1044 color_format = 0x12;
1045 break;
1046
1047 default:
1048 return;
1049 }
1050
1051 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
1052 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
1053 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
1054 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
1055
1056 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
1057 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
1058 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
1059 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
1060 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
1061 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
1062 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
1063 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
1064 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
1065 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
1066 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
1067}
1068
1069static int is_color_space_conversion(struct dw_hdmi *hdmi)
1070{
1071 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1072 bool is_input_rgb, is_output_rgb;
1073
1074 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format);
1075 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format);
1076
1077 return (is_input_rgb != is_output_rgb) ||
1078 (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range);
1079}
1080
1081static int is_color_space_decimation(struct dw_hdmi *hdmi)
1082{
1083 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1084 return 0;
1085
1086 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
1087 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
1088 return 1;
1089
1090 return 0;
1091}
1092
1093static int is_color_space_interpolation(struct dw_hdmi *hdmi)
1094{
1095 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
1096 return 0;
1097
1098 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1099 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1100 return 1;
1101
1102 return 0;
1103}
1104
1105static bool is_csc_needed(struct dw_hdmi *hdmi)
1106{
1107 return is_color_space_conversion(hdmi) ||
1108 is_color_space_decimation(hdmi) ||
1109 is_color_space_interpolation(hdmi);
1110}
1111
1112static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
1113{
1114 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
1115 bool is_input_rgb, is_output_rgb;
1116 unsigned i;
1117 u32 csc_scale = 1;
1118
1119 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format);
1120 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format);
1121
1122 if (!is_input_rgb && is_output_rgb) {
1123 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
1124 csc_coeff = &csc_coeff_rgb_out_eitu601;
1125 else
1126 csc_coeff = &csc_coeff_rgb_out_eitu709;
1127 } else if (is_input_rgb && !is_output_rgb) {
1128 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601)
1129 csc_coeff = &csc_coeff_rgb_in_eitu601;
1130 else
1131 csc_coeff = &csc_coeff_rgb_in_eitu709;
1132 csc_scale = 0;
1133 } else if (is_input_rgb && is_output_rgb &&
1134 hdmi->hdmi_data.rgb_limited_range) {
1135 csc_coeff = &csc_coeff_rgb_full_to_rgb_limited;
1136 }
1137
1138 /* The CSC registers are sequential, alternating MSB then LSB */
1139 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
1140 u16 coeff_a = (*csc_coeff)[0][i];
1141 u16 coeff_b = (*csc_coeff)[1][i];
1142 u16 coeff_c = (*csc_coeff)[2][i];
1143
1144 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
1145 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
1146 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
1147 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
1148 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
1149 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
1150 }
1151
1152 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
1153 HDMI_CSC_SCALE);
1154}
1155
1156static void hdmi_video_csc(struct dw_hdmi *hdmi)
1157{
1158 int color_depth = 0;
1159 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
1160 int decimation = 0;
1161
1162 /* YCC422 interpolation to 444 mode */
1163 if (is_color_space_interpolation(hdmi))
1164 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
1165 else if (is_color_space_decimation(hdmi))
1166 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
1167
1168 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
1169 case 8:
1170 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
1171 break;
1172 case 10:
1173 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
1174 break;
1175 case 12:
1176 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
1177 break;
1178 case 16:
1179 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
1180 break;
1181
1182 default:
1183 return;
1184 }
1185
1186 /* Configure the CSC registers */
1187 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
1188 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
1189 HDMI_CSC_SCALE);
1190
1191 dw_hdmi_update_csc_coeffs(hdmi);
1192}
1193
1194/*
1195 * HDMI video packetizer is used to packetize the data.
1196 * for example, if input is YCC422 mode or repeater is used,
1197 * data should be repacked this module can be bypassed.
1198 */
1199static void hdmi_video_packetize(struct dw_hdmi *hdmi)
1200{
1201 unsigned int color_depth = 0;
1202 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
1203 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
1204 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1205 u8 val, vp_conf;
1206 u8 clear_gcp_auto = 0;
1207
1208
1209 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1210 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
1211 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1212 switch (hdmi_bus_fmt_color_depth(
1213 hdmi->hdmi_data.enc_out_bus_format)) {
1214 case 8:
1215 color_depth = 4;
1216 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1217 clear_gcp_auto = 1;
1218 break;
1219 case 10:
1220 color_depth = 5;
1221 break;
1222 case 12:
1223 color_depth = 6;
1224 break;
1225 case 16:
1226 color_depth = 7;
1227 break;
1228 default:
1229 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1230 }
1231 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1232 switch (hdmi_bus_fmt_color_depth(
1233 hdmi->hdmi_data.enc_out_bus_format)) {
1234 case 0:
1235 case 8:
1236 remap_size = HDMI_VP_REMAP_YCC422_16bit;
1237 clear_gcp_auto = 1;
1238 break;
1239 case 10:
1240 remap_size = HDMI_VP_REMAP_YCC422_20bit;
1241 break;
1242 case 12:
1243 remap_size = HDMI_VP_REMAP_YCC422_24bit;
1244 break;
1245
1246 default:
1247 return;
1248 }
1249 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
1250 } else {
1251 return;
1252 }
1253
1254 /* set the packetizer registers */
1255 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
1256 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
1257 ((hdmi_data->pix_repet_factor <<
1258 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
1259 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
1260 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
1261
1262 /* HDMI1.4b specification section 6.5.3:
1263 * Source shall only send GCPs with non-zero CD to sinks
1264 * that indicate support for Deep Color.
1265 * GCP only transmit CD and do not handle AVMUTE, PP norDefault_Phase (yet).
1266 * Disable Auto GCP when 24-bit color for sinks that not support Deep Color.
1267 */
1268 val = hdmi_readb(hdmi, HDMI_FC_DATAUTO3);
1269 if (clear_gcp_auto == 1)
1270 val &= ~HDMI_FC_DATAUTO3_GCP_AUTO;
1271 else
1272 val |= HDMI_FC_DATAUTO3_GCP_AUTO;
1273 hdmi_writeb(hdmi, val, HDMI_FC_DATAUTO3);
1274
1275 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
1276 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
1277
1278 /* Data from pixel repeater block */
1279 if (hdmi_data->pix_repet_factor > 1) {
1280 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
1281 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
1282 } else { /* data from packetizer block */
1283 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
1284 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
1285 }
1286
1287 hdmi_modb(hdmi, vp_conf,
1288 HDMI_VP_CONF_PR_EN_MASK |
1289 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
1290
1291 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
1292 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
1293
1294 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1295
1296 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
1297 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1298 HDMI_VP_CONF_PP_EN_ENABLE |
1299 HDMI_VP_CONF_YCC422_EN_DISABLE;
1300 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
1301 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1302 HDMI_VP_CONF_PP_EN_DISABLE |
1303 HDMI_VP_CONF_YCC422_EN_ENABLE;
1304 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
1305 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
1306 HDMI_VP_CONF_PP_EN_DISABLE |
1307 HDMI_VP_CONF_YCC422_EN_DISABLE;
1308 } else {
1309 return;
1310 }
1311
1312 hdmi_modb(hdmi, vp_conf,
1313 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
1314 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
1315
1316 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1317 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
1318 HDMI_VP_STUFF_PP_STUFFING_MASK |
1319 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
1320
1321 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1322 HDMI_VP_CONF);
1323}
1324
1325/* -----------------------------------------------------------------------------
1326 * Synopsys PHY Handling
1327 */
1328
1329static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
1330 unsigned char bit)
1331{
1332 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1333 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
1334}
1335
1336static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1337{
1338 u32 val;
1339
1340 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1341 if (msec-- == 0)
1342 return false;
1343 udelay(1000);
1344 }
1345 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1346
1347 return true;
1348}
1349
1350void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1351 unsigned char addr)
1352{
1353 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1354 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1355 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1356 HDMI_PHY_I2CM_DATAO_1_ADDR);
1357 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1358 HDMI_PHY_I2CM_DATAO_0_ADDR);
1359 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1360 HDMI_PHY_I2CM_OPERATION_ADDR);
1361 hdmi_phy_wait_i2c_done(hdmi, 1000);
1362}
1363EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1364
1365/* Filter out invalid setups to avoid configuring SCDC and scrambling */
1366static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi,
1367 const struct drm_display_info *display)
1368{
1369 /* Completely disable SCDC support for older controllers */
1370 if (hdmi->version < 0x200a)
1371 return false;
1372
1373 /* Disable if no DDC bus */
1374 if (!hdmi->ddc)
1375 return false;
1376
1377 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */
1378 if (!display->hdmi.scdc.supported ||
1379 !display->hdmi.scdc.scrambling.supported)
1380 return false;
1381
1382 /*
1383 * Disable if display only support low TMDS rates and scrambling
1384 * for low rates is not supported either
1385 */
1386 if (!display->hdmi.scdc.scrambling.low_rates &&
1387 display->max_tmds_clock <= 340000)
1388 return false;
1389
1390 return true;
1391}
1392
1393/*
1394 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
1395 * - The Source shall suspend transmission of the TMDS clock and data
1396 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it
1397 * from a 0 to a 1 or from a 1 to a 0
1398 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from
1399 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming
1400 * transmission of TMDS clock and data
1401 *
1402 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio()
1403 * helper should called right before enabling the TMDS Clock and Data in
1404 * the PHY configuration callback.
1405 */
1406void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi,
1407 const struct drm_display_info *display)
1408{
1409 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1410
1411 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1412 if (dw_hdmi_support_scdc(hdmi, display)) {
1413 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1414 drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, 1);
1415 else
1416 drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, 0);
1417 }
1418}
1419EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio);
1420
1421static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1422{
1423 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1424 HDMI_PHY_CONF0_PDZ_OFFSET,
1425 HDMI_PHY_CONF0_PDZ_MASK);
1426}
1427
1428static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1429{
1430 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1431 HDMI_PHY_CONF0_ENTMDS_OFFSET,
1432 HDMI_PHY_CONF0_ENTMDS_MASK);
1433}
1434
1435static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1436{
1437 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1438 HDMI_PHY_CONF0_SVSRET_OFFSET,
1439 HDMI_PHY_CONF0_SVSRET_MASK);
1440}
1441
1442void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1443{
1444 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1445 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1446 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1447}
1448EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq);
1449
1450void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1451{
1452 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1453 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1454 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1455}
1456EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron);
1457
1458static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1459{
1460 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1461 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1462 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1463}
1464
1465static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1466{
1467 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1468 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1469 HDMI_PHY_CONF0_SELDIPIF_MASK);
1470}
1471
1472void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi)
1473{
1474 /* PHY reset. The reset signal is active low on Gen1 PHYs. */
1475 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1476 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1477}
1478EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen1_reset);
1479
1480void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi)
1481{
1482 /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1483 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1484 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1485}
1486EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_reset);
1487
1488void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address)
1489{
1490 hdmi_phy_test_clear(hdmi, 1);
1491 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR);
1492 hdmi_phy_test_clear(hdmi, 0);
1493}
1494EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr);
1495
1496static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1497{
1498 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1499 unsigned int i;
1500 u16 val;
1501
1502 if (phy->gen == 1) {
1503 dw_hdmi_phy_enable_tmds(hdmi, 0);
1504 dw_hdmi_phy_enable_powerdown(hdmi, true);
1505 return;
1506 }
1507
1508 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1509
1510 /*
1511 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1512 * to low power mode.
1513 */
1514 for (i = 0; i < 5; ++i) {
1515 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1516 if (!(val & HDMI_PHY_TX_PHY_LOCK))
1517 break;
1518
1519 usleep_range(1000, 2000);
1520 }
1521
1522 if (val & HDMI_PHY_TX_PHY_LOCK)
1523 dev_warn(hdmi->dev, "PHY failed to power down\n");
1524 else
1525 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1526
1527 dw_hdmi_phy_gen2_pddq(hdmi, 1);
1528}
1529
1530static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1531{
1532 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1533 unsigned int i;
1534 u8 val;
1535
1536 if (phy->gen == 1) {
1537 dw_hdmi_phy_enable_powerdown(hdmi, false);
1538
1539 /* Toggle TMDS enable. */
1540 dw_hdmi_phy_enable_tmds(hdmi, 0);
1541 dw_hdmi_phy_enable_tmds(hdmi, 1);
1542 return 0;
1543 }
1544
1545 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1546 dw_hdmi_phy_gen2_pddq(hdmi, 0);
1547
1548 /* Wait for PHY PLL lock */
1549 for (i = 0; i < 5; ++i) {
1550 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1551 if (val)
1552 break;
1553
1554 usleep_range(1000, 2000);
1555 }
1556
1557 if (!val) {
1558 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1559 return -ETIMEDOUT;
1560 }
1561
1562 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1563 return 0;
1564}
1565
1566/*
1567 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1568 * information the DWC MHL PHY has the same register layout and is thus also
1569 * supported by this function.
1570 */
1571static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1572 const struct dw_hdmi_plat_data *pdata,
1573 unsigned long mpixelclock)
1574{
1575 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1576 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1577 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1578
1579 /* TOFIX Will need 420 specific PHY configuration tables */
1580
1581 /* PLL/MPLL Cfg - always match on final entry */
1582 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1583 if (mpixelclock <= mpll_config->mpixelclock)
1584 break;
1585
1586 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1587 if (mpixelclock <= curr_ctrl->mpixelclock)
1588 break;
1589
1590 for (; phy_config->mpixelclock != ~0UL; phy_config++)
1591 if (mpixelclock <= phy_config->mpixelclock)
1592 break;
1593
1594 if (mpll_config->mpixelclock == ~0UL ||
1595 curr_ctrl->mpixelclock == ~0UL ||
1596 phy_config->mpixelclock == ~0UL)
1597 return -EINVAL;
1598
1599 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1600 HDMI_3D_TX_PHY_CPCE_CTRL);
1601 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1602 HDMI_3D_TX_PHY_GMPCTRL);
1603 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1604 HDMI_3D_TX_PHY_CURRCTRL);
1605
1606 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1607 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1608 HDMI_3D_TX_PHY_MSM_CTRL);
1609
1610 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1611 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1612 HDMI_3D_TX_PHY_CKSYMTXCTRL);
1613 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1614 HDMI_3D_TX_PHY_VLEVCTRL);
1615
1616 /* Override and disable clock termination. */
1617 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1618 HDMI_3D_TX_PHY_CKCALCTRL);
1619
1620 return 0;
1621}
1622
1623static int hdmi_phy_configure(struct dw_hdmi *hdmi,
1624 const struct drm_display_info *display)
1625{
1626 const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1627 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1628 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1629 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock;
1630 int ret;
1631
1632 dw_hdmi_phy_power_off(hdmi);
1633
1634 dw_hdmi_set_high_tmds_clock_ratio(hdmi, display);
1635
1636 /* Leave low power consumption mode by asserting SVSRET. */
1637 if (phy->has_svsret)
1638 dw_hdmi_phy_enable_svsret(hdmi, 1);
1639
1640 dw_hdmi_phy_gen2_reset(hdmi);
1641
1642 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1643
1644 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
1645
1646 /* Write to the PHY as configured by the platform */
1647 if (pdata->configure_phy)
1648 ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock);
1649 else
1650 ret = phy->configure(hdmi, pdata, mpixelclock);
1651 if (ret) {
1652 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1653 mpixelclock);
1654 return ret;
1655 }
1656
1657 /* Wait for resuming transmission of TMDS clock and data */
1658 if (mtmdsclock > HDMI14_MAX_TMDSCLK)
1659 msleep(100);
1660
1661 return dw_hdmi_phy_power_on(hdmi);
1662}
1663
1664static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1665 const struct drm_display_info *display,
1666 const struct drm_display_mode *mode)
1667{
1668 int i, ret;
1669
1670 /* HDMI Phy spec says to do the phy initialization sequence twice */
1671 for (i = 0; i < 2; i++) {
1672 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1673 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1674
1675 ret = hdmi_phy_configure(hdmi, display);
1676 if (ret)
1677 return ret;
1678 }
1679
1680 return 0;
1681}
1682
1683static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1684{
1685 dw_hdmi_phy_power_off(hdmi);
1686}
1687
1688enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1689 void *data)
1690{
1691 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1692 connector_status_connected : connector_status_disconnected;
1693}
1694EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);
1695
1696void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
1697 bool force, bool disabled, bool rxsense)
1698{
1699 u8 old_mask = hdmi->phy_mask;
1700
1701 if (force || disabled || !rxsense)
1702 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1703 else
1704 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1705
1706 if (old_mask != hdmi->phy_mask)
1707 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1708}
1709EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd);
1710
1711void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
1712{
1713 /*
1714 * Configure the PHY RX SENSE and HPD interrupts polarities and clear
1715 * any pending interrupt.
1716 */
1717 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1718 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1719 HDMI_IH_PHY_STAT0);
1720
1721 /* Enable cable hot plug irq. */
1722 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1723
1724 /* Clear and unmute interrupts. */
1725 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1726 HDMI_IH_PHY_STAT0);
1727 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1728 HDMI_IH_MUTE_PHY_STAT0);
1729}
1730EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd);
1731
1732static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1733 .init = dw_hdmi_phy_init,
1734 .disable = dw_hdmi_phy_disable,
1735 .read_hpd = dw_hdmi_phy_read_hpd,
1736 .update_hpd = dw_hdmi_phy_update_hpd,
1737 .setup_hpd = dw_hdmi_phy_setup_hpd,
1738};
1739
1740/* -----------------------------------------------------------------------------
1741 * HDMI TX Setup
1742 */
1743
1744static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1745{
1746 u8 de;
1747
1748 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1749 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1750 else
1751 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1752
1753 /* disable rx detect */
1754 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1755 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1756
1757 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1758
1759 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1760 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1761}
1762
1763static void hdmi_config_AVI(struct dw_hdmi *hdmi,
1764 const struct drm_connector *connector,
1765 const struct drm_display_mode *mode)
1766{
1767 struct hdmi_avi_infoframe frame;
1768 u8 val;
1769
1770 /* Initialise info frame from DRM mode */
1771 drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1772
1773 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1774 drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode,
1775 hdmi->hdmi_data.rgb_limited_range ?
1776 HDMI_QUANTIZATION_RANGE_LIMITED :
1777 HDMI_QUANTIZATION_RANGE_FULL);
1778 } else {
1779 frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
1780 frame.ycc_quantization_range =
1781 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
1782 }
1783
1784 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1785 frame.colorspace = HDMI_COLORSPACE_YUV444;
1786 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1787 frame.colorspace = HDMI_COLORSPACE_YUV422;
1788 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1789 frame.colorspace = HDMI_COLORSPACE_YUV420;
1790 else
1791 frame.colorspace = HDMI_COLORSPACE_RGB;
1792
1793 /* Set up colorimetry */
1794 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1795 switch (hdmi->hdmi_data.enc_out_encoding) {
1796 case V4L2_YCBCR_ENC_601:
1797 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1798 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1799 else
1800 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1801 frame.extended_colorimetry =
1802 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1803 break;
1804 case V4L2_YCBCR_ENC_709:
1805 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1806 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1807 else
1808 frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1809 frame.extended_colorimetry =
1810 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1811 break;
1812 default: /* Carries no data */
1813 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1814 frame.extended_colorimetry =
1815 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1816 break;
1817 }
1818 } else {
1819 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1820 frame.extended_colorimetry =
1821 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1822 }
1823
1824 /*
1825 * The Designware IP uses a different byte format from standard
1826 * AVI info frames, though generally the bits are in the correct
1827 * bytes.
1828 */
1829
1830 /*
1831 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
1832 * scan info in bits 4,5 rather than 0,1 and active aspect present in
1833 * bit 6 rather than 4.
1834 */
1835 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
1836 if (frame.active_aspect & 15)
1837 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1838 if (frame.top_bar || frame.bottom_bar)
1839 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1840 if (frame.left_bar || frame.right_bar)
1841 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1842 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1843
1844 /* AVI data byte 2 differences: none */
1845 val = ((frame.colorimetry & 0x3) << 6) |
1846 ((frame.picture_aspect & 0x3) << 4) |
1847 (frame.active_aspect & 0xf);
1848 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1849
1850 /* AVI data byte 3 differences: none */
1851 val = ((frame.extended_colorimetry & 0x7) << 4) |
1852 ((frame.quantization_range & 0x3) << 2) |
1853 (frame.nups & 0x3);
1854 if (frame.itc)
1855 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1856 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1857
1858 /* AVI data byte 4 differences: none */
1859 val = frame.video_code & 0x7f;
1860 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1861
1862 /* AVI Data Byte 5- set up input and output pixel repetition */
1863 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1864 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1865 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1866 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1867 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1868 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1869 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1870
1871 /*
1872 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1873 * ycc range in bits 2,3 rather than 6,7
1874 */
1875 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1876 (frame.content_type & 0x3);
1877 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1878
1879 /* AVI Data Bytes 6-13 */
1880 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1881 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1882 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1883 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1884 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1885 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1886 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1887 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1888}
1889
1890static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1891 const struct drm_connector *connector,
1892 const struct drm_display_mode *mode)
1893{
1894 struct hdmi_vendor_infoframe frame;
1895 u8 buffer[10];
1896 ssize_t err;
1897
1898 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, connector,
1899 mode);
1900 if (err < 0)
1901 /*
1902 * Going into that statement does not means vendor infoframe
1903 * fails. It just informed us that vendor infoframe is not
1904 * needed for the selected mode. Only 4k or stereoscopic 3D
1905 * mode requires vendor infoframe. So just simply return.
1906 */
1907 return;
1908
1909 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1910 if (err < 0) {
1911 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1912 err);
1913 return;
1914 }
1915 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1916 HDMI_FC_DATAUTO0_VSD_MASK);
1917
1918 /* Set the length of HDMI vendor specific InfoFrame payload */
1919 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1920
1921 /* Set 24bit IEEE Registration Identifier */
1922 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1923 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1924 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1925
1926 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1927 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1928 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1929
1930 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1931 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1932
1933 /* Packet frame interpolation */
1934 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1935
1936 /* Auto packets per frame and line spacing */
1937 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1938
1939 /* Configures the Frame Composer On RDRB mode */
1940 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1941 HDMI_FC_DATAUTO0_VSD_MASK);
1942}
1943
1944static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi,
1945 const struct drm_connector *connector)
1946{
1947 const struct drm_connector_state *conn_state = connector->state;
1948 struct hdmi_drm_infoframe frame;
1949 u8 buffer[30];
1950 ssize_t err;
1951 int i;
1952
1953 if (!hdmi->plat_data->use_drm_infoframe)
1954 return;
1955
1956 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE,
1957 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
1958
1959 err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
1960 if (err < 0)
1961 return;
1962
1963 err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer));
1964 if (err < 0) {
1965 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err);
1966 return;
1967 }
1968
1969 hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0);
1970 hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1);
1971
1972 for (i = 0; i < frame.length; i++)
1973 hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i);
1974
1975 hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP);
1976 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE,
1977 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN);
1978}
1979
1980static void hdmi_av_composer(struct dw_hdmi *hdmi,
1981 const struct drm_display_info *display,
1982 const struct drm_display_mode *mode)
1983{
1984 u8 inv_val, bytes;
1985 const struct drm_hdmi_info *hdmi_info = &display->hdmi;
1986 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1987 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1988 unsigned int vdisplay, hdisplay;
1989
1990 vmode->mpixelclock = mode->clock * 1000;
1991
1992 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1993
1994 vmode->mtmdsclock = vmode->mpixelclock;
1995
1996 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1997 switch (hdmi_bus_fmt_color_depth(
1998 hdmi->hdmi_data.enc_out_bus_format)) {
1999 case 16:
2000 vmode->mtmdsclock = vmode->mpixelclock * 2;
2001 break;
2002 case 12:
2003 vmode->mtmdsclock = vmode->mpixelclock * 3 / 2;
2004 break;
2005 case 10:
2006 vmode->mtmdsclock = vmode->mpixelclock * 5 / 4;
2007 break;
2008 }
2009 }
2010
2011 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
2012 vmode->mtmdsclock /= 2;
2013
2014 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock);
2015
2016 /* Set up HDMI_FC_INVIDCONF */
2017 inv_val = (hdmi->hdmi_data.hdcp_enable ||
2018 (dw_hdmi_support_scdc(hdmi, display) &&
2019 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
2020 hdmi_info->scdc.scrambling.low_rates)) ?
2021 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
2022 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
2023
2024 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
2025 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
2026 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
2027
2028 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
2029 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
2030 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
2031
2032 inv_val |= (vmode->mdataenablepolarity ?
2033 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
2034 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
2035
2036 if (hdmi->vic == 39)
2037 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
2038 else
2039 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
2040 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
2041 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
2042
2043 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
2044 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
2045 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
2046
2047 inv_val |= hdmi->sink_is_hdmi ?
2048 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
2049 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
2050
2051 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
2052
2053 hdisplay = mode->hdisplay;
2054 hblank = mode->htotal - mode->hdisplay;
2055 h_de_hs = mode->hsync_start - mode->hdisplay;
2056 hsync_len = mode->hsync_end - mode->hsync_start;
2057
2058 /*
2059 * When we're setting a YCbCr420 mode, we need
2060 * to adjust the horizontal timing to suit.
2061 */
2062 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
2063 hdisplay /= 2;
2064 hblank /= 2;
2065 h_de_hs /= 2;
2066 hsync_len /= 2;
2067 }
2068
2069 vdisplay = mode->vdisplay;
2070 vblank = mode->vtotal - mode->vdisplay;
2071 v_de_vs = mode->vsync_start - mode->vdisplay;
2072 vsync_len = mode->vsync_end - mode->vsync_start;
2073
2074 /*
2075 * When we're setting an interlaced mode, we need
2076 * to adjust the vertical timing to suit.
2077 */
2078 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2079 vdisplay /= 2;
2080 vblank /= 2;
2081 v_de_vs /= 2;
2082 vsync_len /= 2;
2083 }
2084
2085 /* Scrambling Control */
2086 if (dw_hdmi_support_scdc(hdmi, display)) {
2087 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK ||
2088 hdmi_info->scdc.scrambling.low_rates) {
2089 /*
2090 * HDMI2.0 Specifies the following procedure:
2091 * After the Source Device has determined that
2092 * SCDC_Present is set (=1), the Source Device should
2093 * write the accurate Version of the Source Device
2094 * to the Source Version field in the SCDCS.
2095 * Source Devices compliant shall set the
2096 * Source Version = 1.
2097 */
2098 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION,
2099 &bytes);
2100 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION,
2101 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION));
2102
2103 /* Enabled Scrambling in the Sink */
2104 drm_scdc_set_scrambling(hdmi->curr_conn, 1);
2105
2106 /*
2107 * To activate the scrambler feature, you must ensure
2108 * that the quasi-static configuration bit
2109 * fc_invidconf.HDCP_keepout is set at configuration
2110 * time, before the required mc_swrstzreq.tmdsswrst_req
2111 * reset request is issued.
2112 */
2113 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
2114 HDMI_MC_SWRSTZ);
2115 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
2116 } else {
2117 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
2118 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
2119 HDMI_MC_SWRSTZ);
2120 drm_scdc_set_scrambling(hdmi->curr_conn, 0);
2121 }
2122 }
2123
2124 /* Set up horizontal active pixel width */
2125 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
2126 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
2127
2128 /* Set up vertical active lines */
2129 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
2130 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
2131
2132 /* Set up horizontal blanking pixel region width */
2133 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
2134 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
2135
2136 /* Set up vertical blanking pixel region width */
2137 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
2138
2139 /* Set up HSYNC active edge delay width (in pixel clks) */
2140 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
2141 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
2142
2143 /* Set up VSYNC active edge delay (in lines) */
2144 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
2145
2146 /* Set up HSYNC active pulse width (in pixel clks) */
2147 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
2148 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
2149
2150 /* Set up VSYNC active edge delay (in lines) */
2151 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
2152}
2153
2154/* HDMI Initialization Step B.4 */
2155static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
2156{
2157 /* control period minimum duration */
2158 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
2159 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
2160 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
2161
2162 /* Set to fill TMDS data channels */
2163 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
2164 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
2165 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
2166
2167 /* Enable pixel clock and tmds data path */
2168 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE |
2169 HDMI_MC_CLKDIS_CSCCLK_DISABLE |
2170 HDMI_MC_CLKDIS_AUDCLK_DISABLE |
2171 HDMI_MC_CLKDIS_PREPCLK_DISABLE |
2172 HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2173 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
2174 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2175
2176 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
2177 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2178
2179 /* Enable csc path */
2180 if (is_csc_needed(hdmi)) {
2181 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2182 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2183
2184 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
2185 HDMI_MC_FLOWCTRL);
2186 } else {
2187 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE;
2188 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
2189
2190 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
2191 HDMI_MC_FLOWCTRL);
2192 }
2193}
2194
2195/* Workaround to clear the overflow condition */
2196static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
2197{
2198 unsigned int count;
2199 unsigned int i;
2200 u8 val;
2201
2202 /*
2203 * Under some circumstances the Frame Composer arithmetic unit can miss
2204 * an FC register write due to being busy processing the previous one.
2205 * The issue can be worked around by issuing a TMDS software reset and
2206 * then write one of the FC registers several times.
2207 *
2208 * The number of iterations matters and depends on the HDMI TX revision
2209 * (and possibly on the platform).
2210 * 4 iterations for i.MX6Q(v1.30a) and 1 iteration for others.
2211 * i.MX6DL (v1.31a), Allwinner SoCs (v1.32a), Rockchip RK3288 SoC (v2.00a),
2212 * Amlogic Meson GX SoCs (v2.01a), RK3328/RK3399 SoCs (v2.11a)
2213 * and i.MX8MPlus (v2.13a) have been identified as needing the workaround
2214 * with a single iteration.
2215 */
2216
2217 switch (hdmi->version) {
2218 case 0x130a:
2219 count = 4;
2220 break;
2221 default:
2222 count = 1;
2223 break;
2224 }
2225
2226 /* TMDS software reset */
2227 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
2228
2229 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
2230 for (i = 0; i < count; i++)
2231 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
2232}
2233
2234static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
2235{
2236 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
2237 HDMI_IH_MUTE_FC_STAT2);
2238}
2239
2240static int dw_hdmi_setup(struct dw_hdmi *hdmi,
2241 const struct drm_connector *connector,
2242 const struct drm_display_mode *mode)
2243{
2244 int ret;
2245
2246 hdmi_disable_overflow_interrupts(hdmi);
2247
2248 hdmi->vic = drm_match_cea_mode(mode);
2249
2250 if (!hdmi->vic) {
2251 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
2252 } else {
2253 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
2254 }
2255
2256 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
2257 (hdmi->vic == 21) || (hdmi->vic == 22) ||
2258 (hdmi->vic == 2) || (hdmi->vic == 3) ||
2259 (hdmi->vic == 17) || (hdmi->vic == 18))
2260 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
2261 else
2262 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
2263
2264 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
2265 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
2266
2267 if (hdmi->hdmi_data.enc_in_bus_format == MEDIA_BUS_FMT_FIXED)
2268 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2269
2270 /* TOFIX: Get input encoding from plat data or fallback to none */
2271 if (hdmi->plat_data->input_bus_encoding)
2272 hdmi->hdmi_data.enc_in_encoding =
2273 hdmi->plat_data->input_bus_encoding;
2274 else
2275 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
2276
2277 if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED)
2278 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2279
2280 hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi &&
2281 drm_default_rgb_quant_range(mode) ==
2282 HDMI_QUANTIZATION_RANGE_LIMITED;
2283
2284 hdmi->hdmi_data.pix_repet_factor = 0;
2285 hdmi->hdmi_data.hdcp_enable = 0;
2286 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
2287
2288 /* HDMI Initialization Step B.1 */
2289 hdmi_av_composer(hdmi, &connector->display_info, mode);
2290
2291 /* HDMI Initializateion Step B.2 */
2292 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data,
2293 &connector->display_info,
2294 &hdmi->previous_mode);
2295 if (ret)
2296 return ret;
2297 hdmi->phy.enabled = true;
2298
2299 /* HDMI Initialization Step B.3 */
2300 dw_hdmi_enable_video_path(hdmi);
2301
2302 if (hdmi->sink_has_audio) {
2303 dev_dbg(hdmi->dev, "sink has audio support\n");
2304
2305 /* HDMI Initialization Step E - Configure audio */
2306 hdmi_clk_regenerator_update_pixel_clock(hdmi);
2307 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable);
2308 }
2309
2310 /* not for DVI mode */
2311 if (hdmi->sink_is_hdmi) {
2312 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
2313
2314 /* HDMI Initialization Step F - Configure AVI InfoFrame */
2315 hdmi_config_AVI(hdmi, connector, mode);
2316 hdmi_config_vendor_specific_infoframe(hdmi, connector, mode);
2317 hdmi_config_drm_infoframe(hdmi, connector);
2318 } else {
2319 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
2320 }
2321
2322 hdmi_video_packetize(hdmi);
2323 hdmi_video_csc(hdmi);
2324 hdmi_video_sample(hdmi);
2325 hdmi_tx_hdcp_config(hdmi);
2326
2327 dw_hdmi_clear_overflow(hdmi);
2328
2329 return 0;
2330}
2331
2332static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
2333{
2334 u8 ih_mute;
2335
2336 /*
2337 * Boot up defaults are:
2338 * HDMI_IH_MUTE = 0x03 (disabled)
2339 * HDMI_IH_MUTE_* = 0x00 (enabled)
2340 *
2341 * Disable top level interrupt bits in HDMI block
2342 */
2343 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
2344 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2345 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
2346
2347 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2348
2349 /* by default mask all interrupts */
2350 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
2351 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
2352 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
2353 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
2354 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
2355 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
2356 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
2357 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
2358 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
2359 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
2360 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
2361 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
2362 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
2363 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
2364
2365 /* Disable interrupts in the IH_MUTE_* registers */
2366 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
2367 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
2368 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
2369 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
2370 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
2371 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
2372 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
2373 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
2374 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
2375 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
2376
2377 /* Enable top level interrupt bits in HDMI block */
2378 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2379 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
2380 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2381}
2382
2383static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
2384{
2385 hdmi->bridge_is_on = true;
2386
2387 /*
2388 * The curr_conn field is guaranteed to be valid here, as this function
2389 * is only be called when !hdmi->disabled.
2390 */
2391 dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode);
2392}
2393
2394static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
2395{
2396 if (hdmi->phy.enabled) {
2397 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
2398 hdmi->phy.enabled = false;
2399 }
2400
2401 hdmi->bridge_is_on = false;
2402}
2403
2404static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
2405{
2406 int force = hdmi->force;
2407
2408 if (hdmi->disabled) {
2409 force = DRM_FORCE_OFF;
2410 } else if (force == DRM_FORCE_UNSPECIFIED) {
2411 if (hdmi->rxsense)
2412 force = DRM_FORCE_ON;
2413 else
2414 force = DRM_FORCE_OFF;
2415 }
2416
2417 if (force == DRM_FORCE_OFF) {
2418 if (hdmi->bridge_is_on)
2419 dw_hdmi_poweroff(hdmi);
2420 } else {
2421 if (!hdmi->bridge_is_on)
2422 dw_hdmi_poweron(hdmi);
2423 }
2424}
2425
2426/*
2427 * Adjust the detection of RXSENSE according to whether we have a forced
2428 * connection mode enabled, or whether we have been disabled. There is
2429 * no point processing RXSENSE interrupts if we have a forced connection
2430 * state, or DRM has us disabled.
2431 *
2432 * We also disable rxsense interrupts when we think we're disconnected
2433 * to avoid floating TDMS signals giving false rxsense interrupts.
2434 *
2435 * Note: we still need to listen for HPD interrupts even when DRM has us
2436 * disabled so that we can detect a connect event.
2437 */
2438static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
2439{
2440 if (hdmi->phy.ops->update_hpd)
2441 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data,
2442 hdmi->force, hdmi->disabled,
2443 hdmi->rxsense);
2444}
2445
2446static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi)
2447{
2448 enum drm_connector_status result;
2449
2450 result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
2451 hdmi->last_connector_result = result;
2452
2453 return result;
2454}
2455
2456static struct edid *dw_hdmi_get_edid(struct dw_hdmi *hdmi,
2457 struct drm_connector *connector)
2458{
2459 struct edid *edid;
2460
2461 if (!hdmi->ddc)
2462 return NULL;
2463
2464 edid = drm_get_edid(connector, hdmi->ddc);
2465 if (!edid) {
2466 dev_dbg(hdmi->dev, "failed to get edid\n");
2467 return NULL;
2468 }
2469
2470 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2471 edid->width_cm, edid->height_cm);
2472
2473 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
2474 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2475
2476 return edid;
2477}
2478
2479/* -----------------------------------------------------------------------------
2480 * DRM Connector Operations
2481 */
2482
2483static enum drm_connector_status
2484dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
2485{
2486 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2487 connector);
2488 return dw_hdmi_detect(hdmi);
2489}
2490
2491static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
2492{
2493 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2494 connector);
2495 struct edid *edid;
2496 int ret;
2497
2498 edid = dw_hdmi_get_edid(hdmi, connector);
2499 if (!edid)
2500 return 0;
2501
2502 drm_connector_update_edid_property(connector, edid);
2503 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid);
2504 ret = drm_add_edid_modes(connector, edid);
2505 kfree(edid);
2506
2507 return ret;
2508}
2509
2510static int dw_hdmi_connector_atomic_check(struct drm_connector *connector,
2511 struct drm_atomic_state *state)
2512{
2513 struct drm_connector_state *old_state =
2514 drm_atomic_get_old_connector_state(state, connector);
2515 struct drm_connector_state *new_state =
2516 drm_atomic_get_new_connector_state(state, connector);
2517 struct drm_crtc *crtc = new_state->crtc;
2518 struct drm_crtc_state *crtc_state;
2519
2520 if (!crtc)
2521 return 0;
2522
2523 if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
2524 crtc_state = drm_atomic_get_crtc_state(state, crtc);
2525 if (IS_ERR(crtc_state))
2526 return PTR_ERR(crtc_state);
2527
2528 crtc_state->mode_changed = true;
2529 }
2530
2531 return 0;
2532}
2533
2534static void dw_hdmi_connector_force(struct drm_connector *connector)
2535{
2536 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2537 connector);
2538
2539 mutex_lock(&hdmi->mutex);
2540 hdmi->force = connector->force;
2541 dw_hdmi_update_power(hdmi);
2542 dw_hdmi_update_phy_mask(hdmi);
2543 mutex_unlock(&hdmi->mutex);
2544}
2545
2546static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
2547 .fill_modes = drm_helper_probe_single_connector_modes,
2548 .detect = dw_hdmi_connector_detect,
2549 .destroy = drm_connector_cleanup,
2550 .force = dw_hdmi_connector_force,
2551 .reset = drm_atomic_helper_connector_reset,
2552 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2553 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2554};
2555
2556static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
2557 .get_modes = dw_hdmi_connector_get_modes,
2558 .atomic_check = dw_hdmi_connector_atomic_check,
2559};
2560
2561static int dw_hdmi_connector_create(struct dw_hdmi *hdmi)
2562{
2563 struct drm_connector *connector = &hdmi->connector;
2564 struct cec_connector_info conn_info;
2565 struct cec_notifier *notifier;
2566
2567 if (hdmi->version >= 0x200a)
2568 connector->ycbcr_420_allowed =
2569 hdmi->plat_data->ycbcr_420_allowed;
2570 else
2571 connector->ycbcr_420_allowed = false;
2572
2573 connector->interlace_allowed = 1;
2574 connector->polled = DRM_CONNECTOR_POLL_HPD;
2575
2576 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs);
2577
2578 drm_connector_init_with_ddc(hdmi->bridge.dev, connector,
2579 &dw_hdmi_connector_funcs,
2580 DRM_MODE_CONNECTOR_HDMIA,
2581 hdmi->ddc);
2582
2583 /*
2584 * drm_connector_attach_max_bpc_property() requires the
2585 * connector to have a state.
2586 */
2587 drm_atomic_helper_connector_reset(connector);
2588
2589 drm_connector_attach_max_bpc_property(connector, 8, 16);
2590
2591 if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe)
2592 drm_connector_attach_hdr_output_metadata_property(connector);
2593
2594 drm_connector_attach_encoder(connector, hdmi->bridge.encoder);
2595
2596 cec_fill_conn_info_from_drm(&conn_info, connector);
2597
2598 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info);
2599 if (!notifier)
2600 return -ENOMEM;
2601
2602 mutex_lock(&hdmi->cec_notifier_mutex);
2603 hdmi->cec_notifier = notifier;
2604 mutex_unlock(&hdmi->cec_notifier_mutex);
2605
2606 return 0;
2607}
2608
2609/* -----------------------------------------------------------------------------
2610 * DRM Bridge Operations
2611 */
2612
2613/*
2614 * Possible output formats :
2615 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48,
2616 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36,
2617 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30,
2618 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24,
2619 * - MEDIA_BUS_FMT_YUV16_1X48,
2620 * - MEDIA_BUS_FMT_RGB161616_1X48,
2621 * - MEDIA_BUS_FMT_UYVY12_1X24,
2622 * - MEDIA_BUS_FMT_YUV12_1X36,
2623 * - MEDIA_BUS_FMT_RGB121212_1X36,
2624 * - MEDIA_BUS_FMT_UYVY10_1X20,
2625 * - MEDIA_BUS_FMT_YUV10_1X30,
2626 * - MEDIA_BUS_FMT_RGB101010_1X30,
2627 * - MEDIA_BUS_FMT_UYVY8_1X16,
2628 * - MEDIA_BUS_FMT_YUV8_1X24,
2629 * - MEDIA_BUS_FMT_RGB888_1X24,
2630 */
2631
2632/* Can return a maximum of 11 possible output formats for a mode/connector */
2633#define MAX_OUTPUT_SEL_FORMATS 11
2634
2635static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
2636 struct drm_bridge_state *bridge_state,
2637 struct drm_crtc_state *crtc_state,
2638 struct drm_connector_state *conn_state,
2639 unsigned int *num_output_fmts)
2640{
2641 struct drm_connector *conn = conn_state->connector;
2642 struct drm_display_info *info = &conn->display_info;
2643 struct drm_display_mode *mode = &crtc_state->mode;
2644 u8 max_bpc = conn_state->max_requested_bpc;
2645 bool is_hdmi2_sink = info->hdmi.scdc.supported ||
2646 (info->color_formats & DRM_COLOR_FORMAT_YCBCR420);
2647 u32 *output_fmts;
2648 unsigned int i = 0;
2649
2650 *num_output_fmts = 0;
2651
2652 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts),
2653 GFP_KERNEL);
2654 if (!output_fmts)
2655 return NULL;
2656
2657 /* If dw-hdmi is the first or only bridge, avoid negociating with ourselves */
2658 if (list_is_singular(&bridge->encoder->bridge_chain) ||
2659 list_is_first(&bridge->chain_node, &bridge->encoder->bridge_chain)) {
2660 *num_output_fmts = 1;
2661 output_fmts[0] = MEDIA_BUS_FMT_FIXED;
2662
2663 return output_fmts;
2664 }
2665
2666 /*
2667 * If the current mode enforces 4:2:0, force the output but format
2668 * to 4:2:0 and do not add the YUV422/444/RGB formats
2669 */
2670 if (conn->ycbcr_420_allowed &&
2671 (drm_mode_is_420_only(info, mode) ||
2672 (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) {
2673
2674 /* Order bus formats from 16bit to 8bit if supported */
2675 if (max_bpc >= 16 && info->bpc == 16 &&
2676 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48))
2677 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48;
2678
2679 if (max_bpc >= 12 && info->bpc >= 12 &&
2680 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
2681 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36;
2682
2683 if (max_bpc >= 10 && info->bpc >= 10 &&
2684 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30))
2685 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30;
2686
2687 /* Default 8bit fallback */
2688 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
2689
2690 if (drm_mode_is_420_only(info, mode)) {
2691 *num_output_fmts = i;
2692 return output_fmts;
2693 }
2694 }
2695
2696 /*
2697 * Order bus formats from 16bit to 8bit and from YUV422 to RGB
2698 * if supported. In any case the default RGB888 format is added
2699 */
2700
2701 /* Default 8bit RGB fallback */
2702 output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2703
2704 if (max_bpc >= 16 && info->bpc == 16) {
2705 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
2706 output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
2707
2708 output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
2709 }
2710
2711 if (max_bpc >= 12 && info->bpc >= 12) {
2712 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
2713 output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2714
2715 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
2716 output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2717
2718 output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2719 }
2720
2721 if (max_bpc >= 10 && info->bpc >= 10) {
2722 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
2723 output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2724
2725 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
2726 output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2727
2728 output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2729 }
2730
2731 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422)
2732 output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2733
2734 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
2735 output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2736
2737 *num_output_fmts = i;
2738
2739 return output_fmts;
2740}
2741
2742/*
2743 * Possible input formats :
2744 * - MEDIA_BUS_FMT_RGB888_1X24
2745 * - MEDIA_BUS_FMT_YUV8_1X24
2746 * - MEDIA_BUS_FMT_UYVY8_1X16
2747 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24
2748 * - MEDIA_BUS_FMT_RGB101010_1X30
2749 * - MEDIA_BUS_FMT_YUV10_1X30
2750 * - MEDIA_BUS_FMT_UYVY10_1X20
2751 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30
2752 * - MEDIA_BUS_FMT_RGB121212_1X36
2753 * - MEDIA_BUS_FMT_YUV12_1X36
2754 * - MEDIA_BUS_FMT_UYVY12_1X24
2755 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36
2756 * - MEDIA_BUS_FMT_RGB161616_1X48
2757 * - MEDIA_BUS_FMT_YUV16_1X48
2758 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48
2759 */
2760
2761/* Can return a maximum of 3 possible input formats for an output format */
2762#define MAX_INPUT_SEL_FORMATS 3
2763
2764static u32 *dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
2765 struct drm_bridge_state *bridge_state,
2766 struct drm_crtc_state *crtc_state,
2767 struct drm_connector_state *conn_state,
2768 u32 output_fmt,
2769 unsigned int *num_input_fmts)
2770{
2771 u32 *input_fmts;
2772 unsigned int i = 0;
2773
2774 *num_input_fmts = 0;
2775
2776 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
2777 GFP_KERNEL);
2778 if (!input_fmts)
2779 return NULL;
2780
2781 switch (output_fmt) {
2782 /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */
2783 case MEDIA_BUS_FMT_FIXED:
2784 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2785 break;
2786 /* 8bit */
2787 case MEDIA_BUS_FMT_RGB888_1X24:
2788 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2789 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2790 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2791 break;
2792 case MEDIA_BUS_FMT_YUV8_1X24:
2793 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2794 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2795 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2796 break;
2797 case MEDIA_BUS_FMT_UYVY8_1X16:
2798 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16;
2799 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
2800 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
2801 break;
2802
2803 /* 10bit */
2804 case MEDIA_BUS_FMT_RGB101010_1X30:
2805 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2806 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2807 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2808 break;
2809 case MEDIA_BUS_FMT_YUV10_1X30:
2810 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2811 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2812 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2813 break;
2814 case MEDIA_BUS_FMT_UYVY10_1X20:
2815 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20;
2816 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30;
2817 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30;
2818 break;
2819
2820 /* 12bit */
2821 case MEDIA_BUS_FMT_RGB121212_1X36:
2822 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2823 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2824 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2825 break;
2826 case MEDIA_BUS_FMT_YUV12_1X36:
2827 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2828 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2829 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2830 break;
2831 case MEDIA_BUS_FMT_UYVY12_1X24:
2832 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24;
2833 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36;
2834 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36;
2835 break;
2836
2837 /* 16bit */
2838 case MEDIA_BUS_FMT_RGB161616_1X48:
2839 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
2840 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
2841 break;
2842 case MEDIA_BUS_FMT_YUV16_1X48:
2843 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
2844 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48;
2845 break;
2846
2847 /*YUV 4:2:0 */
2848 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
2849 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
2850 case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
2851 case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
2852 input_fmts[i++] = output_fmt;
2853 break;
2854 }
2855
2856 *num_input_fmts = i;
2857
2858 if (*num_input_fmts == 0) {
2859 kfree(input_fmts);
2860 input_fmts = NULL;
2861 }
2862
2863 return input_fmts;
2864}
2865
2866static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge,
2867 struct drm_bridge_state *bridge_state,
2868 struct drm_crtc_state *crtc_state,
2869 struct drm_connector_state *conn_state)
2870{
2871 struct dw_hdmi *hdmi = bridge->driver_private;
2872
2873 hdmi->hdmi_data.enc_out_bus_format =
2874 bridge_state->output_bus_cfg.format;
2875
2876 hdmi->hdmi_data.enc_in_bus_format =
2877 bridge_state->input_bus_cfg.format;
2878
2879 dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n",
2880 bridge_state->input_bus_cfg.format,
2881 bridge_state->output_bus_cfg.format);
2882
2883 return 0;
2884}
2885
2886static int dw_hdmi_bridge_attach(struct drm_bridge *bridge,
2887 enum drm_bridge_attach_flags flags)
2888{
2889 struct dw_hdmi *hdmi = bridge->driver_private;
2890
2891 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
2892 return drm_bridge_attach(bridge->encoder, hdmi->next_bridge,
2893 bridge, flags);
2894
2895 return dw_hdmi_connector_create(hdmi);
2896}
2897
2898static void dw_hdmi_bridge_detach(struct drm_bridge *bridge)
2899{
2900 struct dw_hdmi *hdmi = bridge->driver_private;
2901
2902 mutex_lock(&hdmi->cec_notifier_mutex);
2903 cec_notifier_conn_unregister(hdmi->cec_notifier);
2904 hdmi->cec_notifier = NULL;
2905 mutex_unlock(&hdmi->cec_notifier_mutex);
2906}
2907
2908static enum drm_mode_status
2909dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
2910 const struct drm_display_info *info,
2911 const struct drm_display_mode *mode)
2912{
2913 struct dw_hdmi *hdmi = bridge->driver_private;
2914 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
2915 enum drm_mode_status mode_status = MODE_OK;
2916
2917 /* We don't support double-clocked modes */
2918 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
2919 return MODE_BAD;
2920
2921 if (pdata->mode_valid)
2922 mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info,
2923 mode);
2924
2925 return mode_status;
2926}
2927
2928static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
2929 const struct drm_display_mode *orig_mode,
2930 const struct drm_display_mode *mode)
2931{
2932 struct dw_hdmi *hdmi = bridge->driver_private;
2933
2934 mutex_lock(&hdmi->mutex);
2935
2936 /* Store the display mode for plugin/DKMS poweron events */
2937 drm_mode_copy(&hdmi->previous_mode, mode);
2938
2939 mutex_unlock(&hdmi->mutex);
2940}
2941
2942static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
2943 struct drm_bridge_state *old_state)
2944{
2945 struct dw_hdmi *hdmi = bridge->driver_private;
2946
2947 mutex_lock(&hdmi->mutex);
2948 hdmi->disabled = true;
2949 hdmi->curr_conn = NULL;
2950 dw_hdmi_update_power(hdmi);
2951 dw_hdmi_update_phy_mask(hdmi);
2952 handle_plugged_change(hdmi, false);
2953 mutex_unlock(&hdmi->mutex);
2954}
2955
2956static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
2957 struct drm_bridge_state *old_state)
2958{
2959 struct dw_hdmi *hdmi = bridge->driver_private;
2960 struct drm_atomic_state *state = old_state->base.state;
2961 struct drm_connector *connector;
2962
2963 connector = drm_atomic_get_new_connector_for_encoder(state,
2964 bridge->encoder);
2965
2966 mutex_lock(&hdmi->mutex);
2967 hdmi->disabled = false;
2968 hdmi->curr_conn = connector;
2969 dw_hdmi_update_power(hdmi);
2970 dw_hdmi_update_phy_mask(hdmi);
2971 handle_plugged_change(hdmi, true);
2972 mutex_unlock(&hdmi->mutex);
2973}
2974
2975static enum drm_connector_status dw_hdmi_bridge_detect(struct drm_bridge *bridge)
2976{
2977 struct dw_hdmi *hdmi = bridge->driver_private;
2978
2979 return dw_hdmi_detect(hdmi);
2980}
2981
2982static struct edid *dw_hdmi_bridge_get_edid(struct drm_bridge *bridge,
2983 struct drm_connector *connector)
2984{
2985 struct dw_hdmi *hdmi = bridge->driver_private;
2986
2987 return dw_hdmi_get_edid(hdmi, connector);
2988}
2989
2990static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2991 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
2992 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
2993 .atomic_reset = drm_atomic_helper_bridge_reset,
2994 .attach = dw_hdmi_bridge_attach,
2995 .detach = dw_hdmi_bridge_detach,
2996 .atomic_check = dw_hdmi_bridge_atomic_check,
2997 .atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts,
2998 .atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts,
2999 .atomic_enable = dw_hdmi_bridge_atomic_enable,
3000 .atomic_disable = dw_hdmi_bridge_atomic_disable,
3001 .mode_set = dw_hdmi_bridge_mode_set,
3002 .mode_valid = dw_hdmi_bridge_mode_valid,
3003 .detect = dw_hdmi_bridge_detect,
3004 .get_edid = dw_hdmi_bridge_get_edid,
3005};
3006
3007/* -----------------------------------------------------------------------------
3008 * IRQ Handling
3009 */
3010
3011static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
3012{
3013 struct dw_hdmi_i2c *i2c = hdmi->i2c;
3014 unsigned int stat;
3015
3016 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
3017 if (!stat)
3018 return IRQ_NONE;
3019
3020 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
3021
3022 i2c->stat = stat;
3023
3024 complete(&i2c->cmp);
3025
3026 return IRQ_HANDLED;
3027}
3028
3029static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
3030{
3031 struct dw_hdmi *hdmi = dev_id;
3032 u8 intr_stat;
3033 irqreturn_t ret = IRQ_NONE;
3034
3035 if (hdmi->i2c)
3036 ret = dw_hdmi_i2c_irq(hdmi);
3037
3038 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
3039 if (intr_stat) {
3040 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
3041 return IRQ_WAKE_THREAD;
3042 }
3043
3044 return ret;
3045}
3046
3047void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense)
3048{
3049 mutex_lock(&hdmi->mutex);
3050
3051 if (!hdmi->force) {
3052 /*
3053 * If the RX sense status indicates we're disconnected,
3054 * clear the software rxsense status.
3055 */
3056 if (!rx_sense)
3057 hdmi->rxsense = false;
3058
3059 /*
3060 * Only set the software rxsense status when both
3061 * rxsense and hpd indicates we're connected.
3062 * This avoids what seems to be bad behaviour in
3063 * at least iMX6S versions of the phy.
3064 */
3065 if (hpd)
3066 hdmi->rxsense = true;
3067
3068 dw_hdmi_update_power(hdmi);
3069 dw_hdmi_update_phy_mask(hdmi);
3070 }
3071 mutex_unlock(&hdmi->mutex);
3072}
3073EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense);
3074
3075static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
3076{
3077 struct dw_hdmi *hdmi = dev_id;
3078 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
3079 enum drm_connector_status status = connector_status_unknown;
3080
3081 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
3082 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
3083 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
3084
3085 phy_pol_mask = 0;
3086 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
3087 phy_pol_mask |= HDMI_PHY_HPD;
3088 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
3089 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
3090 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
3091 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
3092 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
3093 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
3094 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
3095 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
3096
3097 if (phy_pol_mask)
3098 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
3099
3100 /*
3101 * RX sense tells us whether the TDMS transmitters are detecting
3102 * load - in other words, there's something listening on the
3103 * other end of the link. Use this to decide whether we should
3104 * power on the phy as HPD may be toggled by the sink to merely
3105 * ask the source to re-read the EDID.
3106 */
3107 if (intr_stat &
3108 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
3109 dw_hdmi_setup_rx_sense(hdmi,
3110 phy_stat & HDMI_PHY_HPD,
3111 phy_stat & HDMI_PHY_RX_SENSE);
3112
3113 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) {
3114 mutex_lock(&hdmi->cec_notifier_mutex);
3115 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier);
3116 mutex_unlock(&hdmi->cec_notifier_mutex);
3117 }
3118
3119 if (phy_stat & HDMI_PHY_HPD)
3120 status = connector_status_connected;
3121
3122 if (!(phy_stat & (HDMI_PHY_HPD | HDMI_PHY_RX_SENSE)))
3123 status = connector_status_disconnected;
3124 }
3125
3126 if (status != connector_status_unknown) {
3127 dev_dbg(hdmi->dev, "EVENT=%s\n",
3128 status == connector_status_connected ?
3129 "plugin" : "plugout");
3130
3131 if (hdmi->bridge.dev) {
3132 drm_helper_hpd_irq_event(hdmi->bridge.dev);
3133 drm_bridge_hpd_notify(&hdmi->bridge, status);
3134 }
3135 }
3136
3137 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
3138 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
3139 HDMI_IH_MUTE_PHY_STAT0);
3140
3141 return IRQ_HANDLED;
3142}
3143
3144static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
3145 {
3146 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
3147 .name = "DWC HDMI TX PHY",
3148 .gen = 1,
3149 }, {
3150 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
3151 .name = "DWC MHL PHY + HEAC PHY",
3152 .gen = 2,
3153 .has_svsret = true,
3154 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3155 }, {
3156 .type = DW_HDMI_PHY_DWC_MHL_PHY,
3157 .name = "DWC MHL PHY",
3158 .gen = 2,
3159 .has_svsret = true,
3160 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3161 }, {
3162 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
3163 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
3164 .gen = 2,
3165 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3166 }, {
3167 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
3168 .name = "DWC HDMI 3D TX PHY",
3169 .gen = 2,
3170 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3171 }, {
3172 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
3173 .name = "DWC HDMI 2.0 TX PHY",
3174 .gen = 2,
3175 .has_svsret = true,
3176 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
3177 }, {
3178 .type = DW_HDMI_PHY_VENDOR_PHY,
3179 .name = "Vendor PHY",
3180 }
3181};
3182
3183static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
3184{
3185 unsigned int i;
3186 u8 phy_type;
3187
3188 phy_type = hdmi->plat_data->phy_force_vendor ?
3189 DW_HDMI_PHY_VENDOR_PHY :
3190 hdmi_readb(hdmi, HDMI_CONFIG2_ID);
3191
3192 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) {
3193 /* Vendor PHYs require support from the glue layer. */
3194 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
3195 dev_err(hdmi->dev,
3196 "Vendor HDMI PHY not supported by glue layer\n");
3197 return -ENODEV;
3198 }
3199
3200 hdmi->phy.ops = hdmi->plat_data->phy_ops;
3201 hdmi->phy.data = hdmi->plat_data->phy_data;
3202 hdmi->phy.name = hdmi->plat_data->phy_name;
3203 return 0;
3204 }
3205
3206 /* Synopsys PHYs are handled internally. */
3207 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
3208 if (dw_hdmi_phys[i].type == phy_type) {
3209 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
3210 hdmi->phy.name = dw_hdmi_phys[i].name;
3211 hdmi->phy.data = (void *)&dw_hdmi_phys[i];
3212
3213 if (!dw_hdmi_phys[i].configure &&
3214 !hdmi->plat_data->configure_phy) {
3215 dev_err(hdmi->dev, "%s requires platform support\n",
3216 hdmi->phy.name);
3217 return -ENODEV;
3218 }
3219
3220 return 0;
3221 }
3222 }
3223
3224 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
3225 return -ENODEV;
3226}
3227
3228static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi)
3229{
3230 mutex_lock(&hdmi->mutex);
3231 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE;
3232 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
3233 mutex_unlock(&hdmi->mutex);
3234}
3235
3236static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi)
3237{
3238 mutex_lock(&hdmi->mutex);
3239 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE;
3240 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS);
3241 mutex_unlock(&hdmi->mutex);
3242}
3243
3244static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = {
3245 .write = hdmi_writeb,
3246 .read = hdmi_readb,
3247 .enable = dw_hdmi_cec_enable,
3248 .disable = dw_hdmi_cec_disable,
3249};
3250
3251static const struct regmap_config hdmi_regmap_8bit_config = {
3252 .reg_bits = 32,
3253 .val_bits = 8,
3254 .reg_stride = 1,
3255 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR,
3256};
3257
3258static const struct regmap_config hdmi_regmap_32bit_config = {
3259 .reg_bits = 32,
3260 .val_bits = 32,
3261 .reg_stride = 4,
3262 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2,
3263};
3264
3265static void dw_hdmi_init_hw(struct dw_hdmi *hdmi)
3266{
3267 initialize_hdmi_ih_mutes(hdmi);
3268
3269 /*
3270 * Reset HDMI DDC I2C master controller and mute I2CM interrupts.
3271 * Even if we are using a separate i2c adapter doing this doesn't
3272 * hurt.
3273 */
3274 dw_hdmi_i2c_init(hdmi);
3275
3276 if (hdmi->phy.ops->setup_hpd)
3277 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
3278}
3279
3280/* -----------------------------------------------------------------------------
3281 * Probe/remove API, used from platforms based on the DRM bridge API.
3282 */
3283
3284static int dw_hdmi_parse_dt(struct dw_hdmi *hdmi)
3285{
3286 struct device_node *endpoint;
3287 struct device_node *remote;
3288
3289 if (!hdmi->plat_data->output_port)
3290 return 0;
3291
3292 endpoint = of_graph_get_endpoint_by_regs(hdmi->dev->of_node,
3293 hdmi->plat_data->output_port,
3294 -1);
3295 if (!endpoint) {
3296 /*
3297 * On platforms whose bindings don't make the output port
3298 * mandatory (such as Rockchip) the plat_data->output_port
3299 * field isn't set, so it's safe to make this a fatal error.
3300 */
3301 dev_err(hdmi->dev, "Missing endpoint in port@%u\n",
3302 hdmi->plat_data->output_port);
3303 return -ENODEV;
3304 }
3305
3306 remote = of_graph_get_remote_port_parent(endpoint);
3307 of_node_put(endpoint);
3308 if (!remote) {
3309 dev_err(hdmi->dev, "Endpoint in port@%u unconnected\n",
3310 hdmi->plat_data->output_port);
3311 return -ENODEV;
3312 }
3313
3314 if (!of_device_is_available(remote)) {
3315 dev_err(hdmi->dev, "port@%u remote device is disabled\n",
3316 hdmi->plat_data->output_port);
3317 of_node_put(remote);
3318 return -ENODEV;
3319 }
3320
3321 hdmi->next_bridge = of_drm_find_bridge(remote);
3322 of_node_put(remote);
3323 if (!hdmi->next_bridge)
3324 return -EPROBE_DEFER;
3325
3326 return 0;
3327}
3328
3329bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi)
3330{
3331 return hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format);
3332}
3333EXPORT_SYMBOL_GPL(dw_hdmi_bus_fmt_is_420);
3334
3335struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
3336 const struct dw_hdmi_plat_data *plat_data)
3337{
3338 struct device *dev = &pdev->dev;
3339 struct device_node *np = dev->of_node;
3340 struct platform_device_info pdevinfo;
3341 struct device_node *ddc_node;
3342 struct dw_hdmi_cec_data cec;
3343 struct dw_hdmi *hdmi;
3344 struct resource *iores = NULL;
3345 int irq;
3346 int ret;
3347 u32 val = 1;
3348 u8 prod_id0;
3349 u8 prod_id1;
3350 u8 config0;
3351 u8 config3;
3352
3353 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
3354 if (!hdmi)
3355 return ERR_PTR(-ENOMEM);
3356
3357 hdmi->plat_data = plat_data;
3358 hdmi->dev = dev;
3359 hdmi->sample_rate = 48000;
3360 hdmi->channels = 2;
3361 hdmi->disabled = true;
3362 hdmi->rxsense = true;
3363 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
3364 hdmi->mc_clkdis = 0x7f;
3365 hdmi->last_connector_result = connector_status_disconnected;
3366
3367 mutex_init(&hdmi->mutex);
3368 mutex_init(&hdmi->audio_mutex);
3369 mutex_init(&hdmi->cec_notifier_mutex);
3370 spin_lock_init(&hdmi->audio_lock);
3371
3372 ret = dw_hdmi_parse_dt(hdmi);
3373 if (ret < 0)
3374 return ERR_PTR(ret);
3375
3376 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
3377 if (ddc_node) {
3378 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
3379 of_node_put(ddc_node);
3380 if (!hdmi->ddc) {
3381 dev_dbg(hdmi->dev, "failed to read ddc node\n");
3382 return ERR_PTR(-EPROBE_DEFER);
3383 }
3384
3385 } else {
3386 dev_dbg(hdmi->dev, "no ddc property found\n");
3387 }
3388
3389 if (!plat_data->regm) {
3390 const struct regmap_config *reg_config;
3391
3392 of_property_read_u32(np, "reg-io-width", &val);
3393 switch (val) {
3394 case 4:
3395 reg_config = &hdmi_regmap_32bit_config;
3396 hdmi->reg_shift = 2;
3397 break;
3398 case 1:
3399 reg_config = &hdmi_regmap_8bit_config;
3400 break;
3401 default:
3402 dev_err(dev, "reg-io-width must be 1 or 4\n");
3403 return ERR_PTR(-EINVAL);
3404 }
3405
3406 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3407 hdmi->regs = devm_ioremap_resource(dev, iores);
3408 if (IS_ERR(hdmi->regs)) {
3409 ret = PTR_ERR(hdmi->regs);
3410 goto err_res;
3411 }
3412
3413 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config);
3414 if (IS_ERR(hdmi->regm)) {
3415 dev_err(dev, "Failed to configure regmap\n");
3416 ret = PTR_ERR(hdmi->regm);
3417 goto err_res;
3418 }
3419 } else {
3420 hdmi->regm = plat_data->regm;
3421 }
3422
3423 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
3424 if (IS_ERR(hdmi->isfr_clk)) {
3425 ret = PTR_ERR(hdmi->isfr_clk);
3426 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
3427 goto err_res;
3428 }
3429
3430 ret = clk_prepare_enable(hdmi->isfr_clk);
3431 if (ret) {
3432 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
3433 goto err_res;
3434 }
3435
3436 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
3437 if (IS_ERR(hdmi->iahb_clk)) {
3438 ret = PTR_ERR(hdmi->iahb_clk);
3439 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
3440 goto err_isfr;
3441 }
3442
3443 ret = clk_prepare_enable(hdmi->iahb_clk);
3444 if (ret) {
3445 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
3446 goto err_isfr;
3447 }
3448
3449 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec");
3450 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) {
3451 hdmi->cec_clk = NULL;
3452 } else if (IS_ERR(hdmi->cec_clk)) {
3453 ret = PTR_ERR(hdmi->cec_clk);
3454 if (ret != -EPROBE_DEFER)
3455 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n",
3456 ret);
3457
3458 hdmi->cec_clk = NULL;
3459 goto err_iahb;
3460 } else {
3461 ret = clk_prepare_enable(hdmi->cec_clk);
3462 if (ret) {
3463 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n",
3464 ret);
3465 goto err_iahb;
3466 }
3467 }
3468
3469 /* Product and revision IDs */
3470 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
3471 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
3472 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
3473 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
3474
3475 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
3476 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
3477 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
3478 hdmi->version, prod_id0, prod_id1);
3479 ret = -ENODEV;
3480 goto err_iahb;
3481 }
3482
3483 ret = dw_hdmi_detect_phy(hdmi);
3484 if (ret < 0)
3485 goto err_iahb;
3486
3487 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
3488 hdmi->version >> 12, hdmi->version & 0xfff,
3489 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
3490 hdmi->phy.name);
3491
3492 dw_hdmi_init_hw(hdmi);
3493
3494 irq = platform_get_irq(pdev, 0);
3495 if (irq < 0) {
3496 ret = irq;
3497 goto err_iahb;
3498 }
3499
3500 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
3501 dw_hdmi_irq, IRQF_SHARED,
3502 dev_name(dev), hdmi);
3503 if (ret)
3504 goto err_iahb;
3505
3506 /*
3507 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
3508 * N and cts values before enabling phy
3509 */
3510 hdmi_init_clk_regenerator(hdmi);
3511
3512 /* If DDC bus is not specified, try to register HDMI I2C bus */
3513 if (!hdmi->ddc) {
3514 /* Look for (optional) stuff related to unwedging */
3515 hdmi->pinctrl = devm_pinctrl_get(dev);
3516 if (!IS_ERR(hdmi->pinctrl)) {
3517 hdmi->unwedge_state =
3518 pinctrl_lookup_state(hdmi->pinctrl, "unwedge");
3519 hdmi->default_state =
3520 pinctrl_lookup_state(hdmi->pinctrl, "default");
3521
3522 if (IS_ERR(hdmi->default_state) ||
3523 IS_ERR(hdmi->unwedge_state)) {
3524 if (!IS_ERR(hdmi->unwedge_state))
3525 dev_warn(dev,
3526 "Unwedge requires default pinctrl\n");
3527 hdmi->default_state = NULL;
3528 hdmi->unwedge_state = NULL;
3529 }
3530 }
3531
3532 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
3533 if (IS_ERR(hdmi->ddc))
3534 hdmi->ddc = NULL;
3535 }
3536
3537 hdmi->bridge.driver_private = hdmi;
3538 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs;
3539 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
3540 | DRM_BRIDGE_OP_HPD;
3541 hdmi->bridge.interlace_allowed = true;
3542 hdmi->bridge.ddc = hdmi->ddc;
3543 hdmi->bridge.of_node = pdev->dev.of_node;
3544
3545 memset(&pdevinfo, 0, sizeof(pdevinfo));
3546 pdevinfo.parent = dev;
3547 pdevinfo.id = PLATFORM_DEVID_AUTO;
3548
3549 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
3550 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
3551
3552 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) {
3553 struct dw_hdmi_audio_data audio;
3554
3555 audio.phys = iores->start;
3556 audio.base = hdmi->regs;
3557 audio.irq = irq;
3558 audio.hdmi = hdmi;
3559 audio.get_eld = hdmi_audio_get_eld;
3560 hdmi->enable_audio = dw_hdmi_ahb_audio_enable;
3561 hdmi->disable_audio = dw_hdmi_ahb_audio_disable;
3562
3563 pdevinfo.name = "dw-hdmi-ahb-audio";
3564 pdevinfo.data = &audio;
3565 pdevinfo.size_data = sizeof(audio);
3566 pdevinfo.dma_mask = DMA_BIT_MASK(32);
3567 hdmi->audio = platform_device_register_full(&pdevinfo);
3568 } else if (config0 & HDMI_CONFIG0_I2S) {
3569 struct dw_hdmi_i2s_audio_data audio;
3570
3571 audio.hdmi = hdmi;
3572 audio.get_eld = hdmi_audio_get_eld;
3573 audio.write = hdmi_writeb;
3574 audio.read = hdmi_readb;
3575 hdmi->enable_audio = dw_hdmi_i2s_audio_enable;
3576 hdmi->disable_audio = dw_hdmi_i2s_audio_disable;
3577
3578 pdevinfo.name = "dw-hdmi-i2s-audio";
3579 pdevinfo.data = &audio;
3580 pdevinfo.size_data = sizeof(audio);
3581 pdevinfo.dma_mask = DMA_BIT_MASK(32);
3582 hdmi->audio = platform_device_register_full(&pdevinfo);
3583 } else if (iores && config3 & HDMI_CONFIG3_GPAUD) {
3584 struct dw_hdmi_audio_data audio;
3585
3586 audio.phys = iores->start;
3587 audio.base = hdmi->regs;
3588 audio.irq = irq;
3589 audio.hdmi = hdmi;
3590 audio.get_eld = hdmi_audio_get_eld;
3591
3592 hdmi->enable_audio = dw_hdmi_gp_audio_enable;
3593 hdmi->disable_audio = dw_hdmi_gp_audio_disable;
3594
3595 pdevinfo.name = "dw-hdmi-gp-audio";
3596 pdevinfo.id = PLATFORM_DEVID_NONE;
3597 pdevinfo.data = &audio;
3598 pdevinfo.size_data = sizeof(audio);
3599 pdevinfo.dma_mask = DMA_BIT_MASK(32);
3600 hdmi->audio = platform_device_register_full(&pdevinfo);
3601 }
3602
3603 if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) {
3604 cec.hdmi = hdmi;
3605 cec.ops = &dw_hdmi_cec_ops;
3606 cec.irq = irq;
3607
3608 pdevinfo.name = "dw-hdmi-cec";
3609 pdevinfo.data = &cec;
3610 pdevinfo.size_data = sizeof(cec);
3611 pdevinfo.dma_mask = 0;
3612
3613 hdmi->cec = platform_device_register_full(&pdevinfo);
3614 }
3615
3616 drm_bridge_add(&hdmi->bridge);
3617
3618 return hdmi;
3619
3620err_iahb:
3621 clk_disable_unprepare(hdmi->iahb_clk);
3622 clk_disable_unprepare(hdmi->cec_clk);
3623err_isfr:
3624 clk_disable_unprepare(hdmi->isfr_clk);
3625err_res:
3626 i2c_put_adapter(hdmi->ddc);
3627
3628 return ERR_PTR(ret);
3629}
3630EXPORT_SYMBOL_GPL(dw_hdmi_probe);
3631
3632void dw_hdmi_remove(struct dw_hdmi *hdmi)
3633{
3634 drm_bridge_remove(&hdmi->bridge);
3635
3636 if (hdmi->audio && !IS_ERR(hdmi->audio))
3637 platform_device_unregister(hdmi->audio);
3638 if (!IS_ERR(hdmi->cec))
3639 platform_device_unregister(hdmi->cec);
3640
3641 /* Disable all interrupts */
3642 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
3643
3644 clk_disable_unprepare(hdmi->iahb_clk);
3645 clk_disable_unprepare(hdmi->isfr_clk);
3646 clk_disable_unprepare(hdmi->cec_clk);
3647
3648 if (hdmi->i2c)
3649 i2c_del_adapter(&hdmi->i2c->adap);
3650 else
3651 i2c_put_adapter(hdmi->ddc);
3652}
3653EXPORT_SYMBOL_GPL(dw_hdmi_remove);
3654
3655/* -----------------------------------------------------------------------------
3656 * Bind/unbind API, used from platforms based on the component framework.
3657 */
3658struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
3659 struct drm_encoder *encoder,
3660 const struct dw_hdmi_plat_data *plat_data)
3661{
3662 struct dw_hdmi *hdmi;
3663 int ret;
3664
3665 hdmi = dw_hdmi_probe(pdev, plat_data);
3666 if (IS_ERR(hdmi))
3667 return hdmi;
3668
3669 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0);
3670 if (ret) {
3671 dw_hdmi_remove(hdmi);
3672 return ERR_PTR(ret);
3673 }
3674
3675 return hdmi;
3676}
3677EXPORT_SYMBOL_GPL(dw_hdmi_bind);
3678
3679void dw_hdmi_unbind(struct dw_hdmi *hdmi)
3680{
3681 dw_hdmi_remove(hdmi);
3682}
3683EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
3684
3685void dw_hdmi_resume(struct dw_hdmi *hdmi)
3686{
3687 dw_hdmi_init_hw(hdmi);
3688}
3689EXPORT_SYMBOL_GPL(dw_hdmi_resume);
3690
3691MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
3692MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
3693MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
3694MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
3695MODULE_DESCRIPTION("DW HDMI transmitter driver");
3696MODULE_LICENSE("GPL");
3697MODULE_ALIAS("platform:dw-hdmi");