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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Samsung MIPI DSIM bridge driver.
4 *
5 * Copyright (C) 2021 Amarula Solutions(India)
6 * Copyright (c) 2014 Samsung Electronics Co., Ltd
7 * Author: Jagan Teki <jagan@amarulasolutions.com>
8 *
9 * Based on exynos_drm_dsi from
10 * Tomasz Figa <t.figa@samsung.com>
11 */
12
13#include <asm/unaligned.h>
14
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/irq.h>
18#include <linux/media-bus-format.h>
19#include <linux/of.h>
20#include <linux/phy/phy.h>
21#include <linux/platform_device.h>
22
23#include <video/mipi_display.h>
24
25#include <drm/bridge/samsung-dsim.h>
26#include <drm/drm_panel.h>
27#include <drm/drm_print.h>
28
29/* returns true iff both arguments logically differs */
30#define NEQV(a, b) (!(a) ^ !(b))
31
32/* DSIM_STATUS */
33#define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
34#define DSIM_STOP_STATE_CLK BIT(8)
35#define DSIM_TX_READY_HS_CLK BIT(10)
36#define DSIM_PLL_STABLE BIT(31)
37
38/* DSIM_SWRST */
39#define DSIM_FUNCRST BIT(16)
40#define DSIM_SWRST BIT(0)
41
42/* DSIM_TIMEOUT */
43#define DSIM_LPDR_TIMEOUT(x) ((x) << 0)
44#define DSIM_BTA_TIMEOUT(x) ((x) << 16)
45
46/* DSIM_CLKCTRL */
47#define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
48#define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
49#define DSIM_LANE_ESC_CLK_EN_CLK BIT(19)
50#define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20)
51#define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20)
52#define DSIM_BYTE_CLKEN BIT(24)
53#define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
54#define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
55#define DSIM_PLL_BYPASS BIT(27)
56#define DSIM_ESC_CLKEN BIT(28)
57#define DSIM_TX_REQUEST_HSCLK BIT(31)
58
59/* DSIM_CONFIG */
60#define DSIM_LANE_EN_CLK BIT(0)
61#define DSIM_LANE_EN(x) (((x) & 0xf) << 1)
62#define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5)
63#define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8)
64#define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12)
65#define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12)
66#define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12)
67#define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12)
68#define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12)
69#define DSIM_SUB_VC (((x) & 0x3) << 16)
70#define DSIM_MAIN_VC (((x) & 0x3) << 18)
71#define DSIM_HSA_DISABLE_MODE BIT(20)
72#define DSIM_HBP_DISABLE_MODE BIT(21)
73#define DSIM_HFP_DISABLE_MODE BIT(22)
74/*
75 * The i.MX 8M Mini Applications Processor Reference Manual,
76 * Rev. 3, 11/2020 Page 4091
77 * The i.MX 8M Nano Applications Processor Reference Manual,
78 * Rev. 2, 07/2022 Page 3058
79 * The i.MX 8M Plus Applications Processor Reference Manual,
80 * Rev. 1, 06/2021 Page 5436
81 * all claims this bit is 'HseDisableMode' with the definition
82 * 0 = Disables transfer
83 * 1 = Enables transfer
84 *
85 * This clearly states that HSE is not a disabled bit.
86 *
87 * The naming convention follows as per the manual and the
88 * driver logic is based on the MIPI_DSI_MODE_VIDEO_HSE flag.
89 */
90#define DSIM_HSE_DISABLE_MODE BIT(23)
91#define DSIM_AUTO_MODE BIT(24)
92#define DSIM_VIDEO_MODE BIT(25)
93#define DSIM_BURST_MODE BIT(26)
94#define DSIM_SYNC_INFORM BIT(27)
95#define DSIM_EOT_DISABLE BIT(28)
96#define DSIM_MFLUSH_VS BIT(29)
97/* This flag is valid only for exynos3250/3472/5260/5430 */
98#define DSIM_CLKLANE_STOP BIT(30)
99
100/* DSIM_ESCMODE */
101#define DSIM_TX_TRIGGER_RST BIT(4)
102#define DSIM_TX_LPDT_LP BIT(6)
103#define DSIM_CMD_LPDT_LP BIT(7)
104#define DSIM_FORCE_BTA BIT(16)
105#define DSIM_FORCE_STOP_STATE BIT(20)
106#define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21)
107#define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21)
108
109/* DSIM_MDRESOL */
110#define DSIM_MAIN_STAND_BY BIT(31)
111#define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16)
112#define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0)
113
114/* DSIM_MVPORCH */
115#define DSIM_CMD_ALLOW(x) ((x) << 28)
116#define DSIM_STABLE_VFP(x) ((x) << 16)
117#define DSIM_MAIN_VBP(x) ((x) << 0)
118#define DSIM_CMD_ALLOW_MASK (0xf << 28)
119#define DSIM_STABLE_VFP_MASK (0x7ff << 16)
120#define DSIM_MAIN_VBP_MASK (0x7ff << 0)
121
122/* DSIM_MHPORCH */
123#define DSIM_MAIN_HFP(x) ((x) << 16)
124#define DSIM_MAIN_HBP(x) ((x) << 0)
125#define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
126#define DSIM_MAIN_HBP_MASK ((0xffff) << 0)
127
128/* DSIM_MSYNC */
129#define DSIM_MAIN_VSA(x) ((x) << 22)
130#define DSIM_MAIN_HSA(x) ((x) << 0)
131#define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
132#define DSIM_MAIN_HSA_MASK ((0xffff) << 0)
133
134/* DSIM_SDRESOL */
135#define DSIM_SUB_STANDY(x) ((x) << 31)
136#define DSIM_SUB_VRESOL(x) ((x) << 16)
137#define DSIM_SUB_HRESOL(x) ((x) << 0)
138#define DSIM_SUB_STANDY_MASK ((0x1) << 31)
139#define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
140#define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)
141
142/* DSIM_INTSRC */
143#define DSIM_INT_PLL_STABLE BIT(31)
144#define DSIM_INT_SW_RST_RELEASE BIT(30)
145#define DSIM_INT_SFR_FIFO_EMPTY BIT(29)
146#define DSIM_INT_SFR_HDR_FIFO_EMPTY BIT(28)
147#define DSIM_INT_BTA BIT(25)
148#define DSIM_INT_FRAME_DONE BIT(24)
149#define DSIM_INT_RX_TIMEOUT BIT(21)
150#define DSIM_INT_BTA_TIMEOUT BIT(20)
151#define DSIM_INT_RX_DONE BIT(18)
152#define DSIM_INT_RX_TE BIT(17)
153#define DSIM_INT_RX_ACK BIT(16)
154#define DSIM_INT_RX_ECC_ERR BIT(15)
155#define DSIM_INT_RX_CRC_ERR BIT(14)
156
157/* DSIM_FIFOCTRL */
158#define DSIM_RX_DATA_FULL BIT(25)
159#define DSIM_RX_DATA_EMPTY BIT(24)
160#define DSIM_SFR_HEADER_FULL BIT(23)
161#define DSIM_SFR_HEADER_EMPTY BIT(22)
162#define DSIM_SFR_PAYLOAD_FULL BIT(21)
163#define DSIM_SFR_PAYLOAD_EMPTY BIT(20)
164#define DSIM_I80_HEADER_FULL BIT(19)
165#define DSIM_I80_HEADER_EMPTY BIT(18)
166#define DSIM_I80_PAYLOAD_FULL BIT(17)
167#define DSIM_I80_PAYLOAD_EMPTY BIT(16)
168#define DSIM_SD_HEADER_FULL BIT(15)
169#define DSIM_SD_HEADER_EMPTY BIT(14)
170#define DSIM_SD_PAYLOAD_FULL BIT(13)
171#define DSIM_SD_PAYLOAD_EMPTY BIT(12)
172#define DSIM_MD_HEADER_FULL BIT(11)
173#define DSIM_MD_HEADER_EMPTY BIT(10)
174#define DSIM_MD_PAYLOAD_FULL BIT(9)
175#define DSIM_MD_PAYLOAD_EMPTY BIT(8)
176#define DSIM_RX_FIFO BIT(4)
177#define DSIM_SFR_FIFO BIT(3)
178#define DSIM_I80_FIFO BIT(2)
179#define DSIM_SD_FIFO BIT(1)
180#define DSIM_MD_FIFO BIT(0)
181
182/* DSIM_PHYACCHR */
183#define DSIM_AFC_EN BIT(14)
184#define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
185
186/* DSIM_PLLCTRL */
187#define DSIM_PLL_DPDNSWAP_CLK (1 << 25)
188#define DSIM_PLL_DPDNSWAP_DAT (1 << 24)
189#define DSIM_FREQ_BAND(x) ((x) << 24)
190#define DSIM_PLL_EN BIT(23)
191#define DSIM_PLL_P(x, offset) ((x) << (offset))
192#define DSIM_PLL_M(x) ((x) << 4)
193#define DSIM_PLL_S(x) ((x) << 1)
194
195/* DSIM_PHYCTRL */
196#define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0)
197#define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP BIT(30)
198#define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP BIT(14)
199
200/* DSIM_PHYTIMING */
201#define DSIM_PHYTIMING_LPX(x) ((x) << 8)
202#define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
203
204/* DSIM_PHYTIMING1 */
205#define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
206#define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16)
207#define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8)
208#define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
209
210/* DSIM_PHYTIMING2 */
211#define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
212#define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
213#define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0)
214
215#define DSI_MAX_BUS_WIDTH 4
216#define DSI_NUM_VIRTUAL_CHANNELS 4
217#define DSI_TX_FIFO_SIZE 2048
218#define DSI_RX_FIFO_SIZE 256
219#define DSI_XFER_TIMEOUT_MS 100
220#define DSI_RX_FIFO_EMPTY 0x30800002
221
222#define OLD_SCLK_MIPI_CLK_NAME "pll_clk"
223
224#define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 1000000000000ULL)
225
226static const char *const clk_names[5] = {
227 "bus_clk",
228 "sclk_mipi",
229 "phyclk_mipidphy0_bitclkdiv8",
230 "phyclk_mipidphy0_rxclkesc0",
231 "sclk_rgb_vclk_to_dsim0"
232};
233
234enum samsung_dsim_transfer_type {
235 EXYNOS_DSI_TX,
236 EXYNOS_DSI_RX,
237};
238
239enum reg_idx {
240 DSIM_STATUS_REG, /* Status register */
241 DSIM_SWRST_REG, /* Software reset register */
242 DSIM_CLKCTRL_REG, /* Clock control register */
243 DSIM_TIMEOUT_REG, /* Time out register */
244 DSIM_CONFIG_REG, /* Configuration register */
245 DSIM_ESCMODE_REG, /* Escape mode register */
246 DSIM_MDRESOL_REG,
247 DSIM_MVPORCH_REG, /* Main display Vporch register */
248 DSIM_MHPORCH_REG, /* Main display Hporch register */
249 DSIM_MSYNC_REG, /* Main display sync area register */
250 DSIM_INTSRC_REG, /* Interrupt source register */
251 DSIM_INTMSK_REG, /* Interrupt mask register */
252 DSIM_PKTHDR_REG, /* Packet Header FIFO register */
253 DSIM_PAYLOAD_REG, /* Payload FIFO register */
254 DSIM_RXFIFO_REG, /* Read FIFO register */
255 DSIM_FIFOCTRL_REG, /* FIFO status and control register */
256 DSIM_PLLCTRL_REG, /* PLL control register */
257 DSIM_PHYCTRL_REG,
258 DSIM_PHYTIMING_REG,
259 DSIM_PHYTIMING1_REG,
260 DSIM_PHYTIMING2_REG,
261 NUM_REGS
262};
263
264static const unsigned int exynos_reg_ofs[] = {
265 [DSIM_STATUS_REG] = 0x00,
266 [DSIM_SWRST_REG] = 0x04,
267 [DSIM_CLKCTRL_REG] = 0x08,
268 [DSIM_TIMEOUT_REG] = 0x0c,
269 [DSIM_CONFIG_REG] = 0x10,
270 [DSIM_ESCMODE_REG] = 0x14,
271 [DSIM_MDRESOL_REG] = 0x18,
272 [DSIM_MVPORCH_REG] = 0x1c,
273 [DSIM_MHPORCH_REG] = 0x20,
274 [DSIM_MSYNC_REG] = 0x24,
275 [DSIM_INTSRC_REG] = 0x2c,
276 [DSIM_INTMSK_REG] = 0x30,
277 [DSIM_PKTHDR_REG] = 0x34,
278 [DSIM_PAYLOAD_REG] = 0x38,
279 [DSIM_RXFIFO_REG] = 0x3c,
280 [DSIM_FIFOCTRL_REG] = 0x44,
281 [DSIM_PLLCTRL_REG] = 0x4c,
282 [DSIM_PHYCTRL_REG] = 0x5c,
283 [DSIM_PHYTIMING_REG] = 0x64,
284 [DSIM_PHYTIMING1_REG] = 0x68,
285 [DSIM_PHYTIMING2_REG] = 0x6c,
286};
287
288static const unsigned int exynos5433_reg_ofs[] = {
289 [DSIM_STATUS_REG] = 0x04,
290 [DSIM_SWRST_REG] = 0x0C,
291 [DSIM_CLKCTRL_REG] = 0x10,
292 [DSIM_TIMEOUT_REG] = 0x14,
293 [DSIM_CONFIG_REG] = 0x18,
294 [DSIM_ESCMODE_REG] = 0x1C,
295 [DSIM_MDRESOL_REG] = 0x20,
296 [DSIM_MVPORCH_REG] = 0x24,
297 [DSIM_MHPORCH_REG] = 0x28,
298 [DSIM_MSYNC_REG] = 0x2C,
299 [DSIM_INTSRC_REG] = 0x34,
300 [DSIM_INTMSK_REG] = 0x38,
301 [DSIM_PKTHDR_REG] = 0x3C,
302 [DSIM_PAYLOAD_REG] = 0x40,
303 [DSIM_RXFIFO_REG] = 0x44,
304 [DSIM_FIFOCTRL_REG] = 0x4C,
305 [DSIM_PLLCTRL_REG] = 0x94,
306 [DSIM_PHYCTRL_REG] = 0xA4,
307 [DSIM_PHYTIMING_REG] = 0xB4,
308 [DSIM_PHYTIMING1_REG] = 0xB8,
309 [DSIM_PHYTIMING2_REG] = 0xBC,
310};
311
312enum reg_value_idx {
313 RESET_TYPE,
314 PLL_TIMER,
315 STOP_STATE_CNT,
316 PHYCTRL_ULPS_EXIT,
317 PHYCTRL_VREG_LP,
318 PHYCTRL_SLEW_UP,
319 PHYTIMING_LPX,
320 PHYTIMING_HS_EXIT,
321 PHYTIMING_CLK_PREPARE,
322 PHYTIMING_CLK_ZERO,
323 PHYTIMING_CLK_POST,
324 PHYTIMING_CLK_TRAIL,
325 PHYTIMING_HS_PREPARE,
326 PHYTIMING_HS_ZERO,
327 PHYTIMING_HS_TRAIL
328};
329
330static const unsigned int reg_values[] = {
331 [RESET_TYPE] = DSIM_SWRST,
332 [PLL_TIMER] = 500,
333 [STOP_STATE_CNT] = 0xf,
334 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af),
335 [PHYCTRL_VREG_LP] = 0,
336 [PHYCTRL_SLEW_UP] = 0,
337 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
338 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
339 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
340 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27),
341 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
342 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
343 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09),
344 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
345 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
346};
347
348static const unsigned int exynos5422_reg_values[] = {
349 [RESET_TYPE] = DSIM_SWRST,
350 [PLL_TIMER] = 500,
351 [STOP_STATE_CNT] = 0xf,
352 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
353 [PHYCTRL_VREG_LP] = 0,
354 [PHYCTRL_SLEW_UP] = 0,
355 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08),
356 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d),
357 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
358 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30),
359 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
360 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a),
361 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c),
362 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11),
363 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d),
364};
365
366static const unsigned int exynos5433_reg_values[] = {
367 [RESET_TYPE] = DSIM_FUNCRST,
368 [PLL_TIMER] = 22200,
369 [STOP_STATE_CNT] = 0xa,
370 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190),
371 [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP,
372 [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP,
373 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07),
374 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c),
375 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09),
376 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d),
377 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e),
378 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09),
379 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b),
380 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10),
381 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c),
382};
383
384static const unsigned int imx8mm_dsim_reg_values[] = {
385 [RESET_TYPE] = DSIM_SWRST,
386 [PLL_TIMER] = 500,
387 [STOP_STATE_CNT] = 0xf,
388 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf),
389 [PHYCTRL_VREG_LP] = 0,
390 [PHYCTRL_SLEW_UP] = 0,
391 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06),
392 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b),
393 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07),
394 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26),
395 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d),
396 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08),
397 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08),
398 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d),
399 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b),
400};
401
402static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = {
403 .reg_ofs = exynos_reg_ofs,
404 .plltmr_reg = 0x50,
405 .has_freqband = 1,
406 .has_clklane_stop = 1,
407 .num_clks = 2,
408 .max_freq = 1000,
409 .wait_for_reset = 1,
410 .num_bits_resol = 11,
411 .pll_p_offset = 13,
412 .reg_values = reg_values,
413 .pll_fin_min = 6,
414 .pll_fin_max = 12,
415 .m_min = 41,
416 .m_max = 125,
417 .min_freq = 500,
418 .has_broken_fifoctrl_emptyhdr = 1,
419};
420
421static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = {
422 .reg_ofs = exynos_reg_ofs,
423 .plltmr_reg = 0x50,
424 .has_freqband = 1,
425 .has_clklane_stop = 1,
426 .num_clks = 2,
427 .max_freq = 1000,
428 .wait_for_reset = 1,
429 .num_bits_resol = 11,
430 .pll_p_offset = 13,
431 .reg_values = reg_values,
432 .pll_fin_min = 6,
433 .pll_fin_max = 12,
434 .m_min = 41,
435 .m_max = 125,
436 .min_freq = 500,
437 .has_broken_fifoctrl_emptyhdr = 1,
438};
439
440static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = {
441 .reg_ofs = exynos_reg_ofs,
442 .plltmr_reg = 0x58,
443 .num_clks = 2,
444 .max_freq = 1000,
445 .wait_for_reset = 1,
446 .num_bits_resol = 11,
447 .pll_p_offset = 13,
448 .reg_values = reg_values,
449 .pll_fin_min = 6,
450 .pll_fin_max = 12,
451 .m_min = 41,
452 .m_max = 125,
453 .min_freq = 500,
454};
455
456static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = {
457 .reg_ofs = exynos5433_reg_ofs,
458 .plltmr_reg = 0xa0,
459 .has_clklane_stop = 1,
460 .num_clks = 5,
461 .max_freq = 1500,
462 .wait_for_reset = 0,
463 .num_bits_resol = 12,
464 .pll_p_offset = 13,
465 .reg_values = exynos5433_reg_values,
466 .pll_fin_min = 6,
467 .pll_fin_max = 12,
468 .m_min = 41,
469 .m_max = 125,
470 .min_freq = 500,
471};
472
473static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
474 .reg_ofs = exynos5433_reg_ofs,
475 .plltmr_reg = 0xa0,
476 .has_clklane_stop = 1,
477 .num_clks = 2,
478 .max_freq = 1500,
479 .wait_for_reset = 1,
480 .num_bits_resol = 12,
481 .pll_p_offset = 13,
482 .reg_values = exynos5422_reg_values,
483 .pll_fin_min = 6,
484 .pll_fin_max = 12,
485 .m_min = 41,
486 .m_max = 125,
487 .min_freq = 500,
488};
489
490static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = {
491 .reg_ofs = exynos5433_reg_ofs,
492 .plltmr_reg = 0xa0,
493 .has_clklane_stop = 1,
494 .num_clks = 2,
495 .max_freq = 2100,
496 .wait_for_reset = 0,
497 .num_bits_resol = 12,
498 /*
499 * Unlike Exynos, PLL_P(PMS_P) offset 14 is used in i.MX8M Mini/Nano/Plus
500 * downstream driver - drivers/gpu/drm/bridge/sec-dsim.c
501 */
502 .pll_p_offset = 14,
503 .reg_values = imx8mm_dsim_reg_values,
504 .pll_fin_min = 2,
505 .pll_fin_max = 30,
506 .m_min = 64,
507 .m_max = 1023,
508 .min_freq = 1050,
509};
510
511static const struct samsung_dsim_driver_data *
512samsung_dsim_types[DSIM_TYPE_COUNT] = {
513 [DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data,
514 [DSIM_TYPE_EXYNOS4210] = &exynos4_dsi_driver_data,
515 [DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data,
516 [DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data,
517 [DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data,
518 [DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data,
519 [DSIM_TYPE_IMX8MP] = &imx8mm_dsi_driver_data,
520};
521
522static inline struct samsung_dsim *host_to_dsi(struct mipi_dsi_host *h)
523{
524 return container_of(h, struct samsung_dsim, dsi_host);
525}
526
527static inline struct samsung_dsim *bridge_to_dsi(struct drm_bridge *b)
528{
529 return container_of(b, struct samsung_dsim, bridge);
530}
531
532static inline void samsung_dsim_write(struct samsung_dsim *dsi,
533 enum reg_idx idx, u32 val)
534{
535 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
536}
537
538static inline u32 samsung_dsim_read(struct samsung_dsim *dsi, enum reg_idx idx)
539{
540 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]);
541}
542
543static void samsung_dsim_wait_for_reset(struct samsung_dsim *dsi)
544{
545 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
546 return;
547
548 dev_err(dsi->dev, "timeout waiting for reset\n");
549}
550
551static void samsung_dsim_reset(struct samsung_dsim *dsi)
552{
553 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE];
554
555 reinit_completion(&dsi->completed);
556 samsung_dsim_write(dsi, DSIM_SWRST_REG, reset_val);
557}
558
559#ifndef MHZ
560#define MHZ (1000 * 1000)
561#endif
562
563static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi,
564 unsigned long fin,
565 unsigned long fout,
566 u8 *p, u16 *m, u8 *s)
567{
568 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
569 unsigned long best_freq = 0;
570 u32 min_delta = 0xffffffff;
571 u8 p_min, p_max;
572 u8 _p, best_p;
573 u16 _m, best_m;
574 u8 _s, best_s;
575
576 p_min = DIV_ROUND_UP(fin, (12 * MHZ));
577 p_max = fin / (6 * MHZ);
578
579 for (_p = p_min; _p <= p_max; ++_p) {
580 for (_s = 0; _s <= 5; ++_s) {
581 u64 tmp;
582 u32 delta;
583
584 tmp = (u64)fout * (_p << _s);
585 do_div(tmp, fin);
586 _m = tmp;
587 if (_m < driver_data->m_min || _m > driver_data->m_max)
588 continue;
589
590 tmp = (u64)_m * fin;
591 do_div(tmp, _p);
592 if (tmp < driver_data->min_freq * MHZ ||
593 tmp > driver_data->max_freq * MHZ)
594 continue;
595
596 tmp = (u64)_m * fin;
597 do_div(tmp, _p << _s);
598
599 delta = abs(fout - tmp);
600 if (delta < min_delta) {
601 best_p = _p;
602 best_m = _m;
603 best_s = _s;
604 min_delta = delta;
605 best_freq = tmp;
606 }
607 }
608 }
609
610 if (best_freq) {
611 *p = best_p;
612 *m = best_m;
613 *s = best_s;
614 }
615
616 return best_freq;
617}
618
619static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
620 unsigned long freq)
621{
622 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
623 unsigned long fin, fout;
624 int timeout;
625 u8 p, s;
626 u16 m;
627 u32 reg;
628
629 if (dsi->pll_clk) {
630 /*
631 * Ensure that the reference clock is generated with a power of
632 * two divider from its parent, but close to the PLLs upper
633 * limit.
634 */
635 fin = clk_get_rate(clk_get_parent(dsi->pll_clk));
636 while (fin > driver_data->pll_fin_max * MHZ)
637 fin /= 2;
638 clk_set_rate(dsi->pll_clk, fin);
639
640 fin = clk_get_rate(dsi->pll_clk);
641 } else {
642 fin = dsi->pll_clk_rate;
643 }
644 dev_dbg(dsi->dev, "PLL ref clock freq %lu\n", fin);
645
646 fout = samsung_dsim_pll_find_pms(dsi, fin, freq, &p, &m, &s);
647 if (!fout) {
648 dev_err(dsi->dev,
649 "failed to find PLL PMS for requested frequency\n");
650 return 0;
651 }
652 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
653
654 writel(driver_data->reg_values[PLL_TIMER],
655 dsi->reg_base + driver_data->plltmr_reg);
656
657 reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) |
658 DSIM_PLL_M(m) | DSIM_PLL_S(s);
659
660 if (driver_data->has_freqband) {
661 static const unsigned long freq_bands[] = {
662 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
663 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
664 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
665 770 * MHZ, 870 * MHZ, 950 * MHZ,
666 };
667 int band;
668
669 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
670 if (fout < freq_bands[band])
671 break;
672
673 dev_dbg(dsi->dev, "band %d\n", band);
674
675 reg |= DSIM_FREQ_BAND(band);
676 }
677
678 if (dsi->swap_dn_dp_clk)
679 reg |= DSIM_PLL_DPDNSWAP_CLK;
680 if (dsi->swap_dn_dp_data)
681 reg |= DSIM_PLL_DPDNSWAP_DAT;
682
683 samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
684
685 timeout = 1000;
686 do {
687 if (timeout-- == 0) {
688 dev_err(dsi->dev, "PLL failed to stabilize\n");
689 return 0;
690 }
691 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
692 } while ((reg & DSIM_PLL_STABLE) == 0);
693
694 dsi->hs_clock = fout;
695
696 return fout;
697}
698
699static int samsung_dsim_enable_clock(struct samsung_dsim *dsi)
700{
701 unsigned long hs_clk, byte_clk, esc_clk, pix_clk;
702 unsigned long esc_div;
703 u32 reg;
704 struct drm_display_mode *m = &dsi->mode;
705 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
706
707 /* m->clock is in KHz */
708 pix_clk = m->clock * 1000;
709
710 /* Use burst_clk_rate if available, otherwise use the pix_clk */
711 if (dsi->burst_clk_rate)
712 hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate);
713 else
714 hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes));
715
716 if (!hs_clk) {
717 dev_err(dsi->dev, "failed to configure DSI PLL\n");
718 return -EFAULT;
719 }
720
721 byte_clk = hs_clk / 8;
722 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
723 esc_clk = byte_clk / esc_div;
724
725 if (esc_clk > 20 * MHZ) {
726 ++esc_div;
727 esc_clk = byte_clk / esc_div;
728 }
729
730 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
731 hs_clk, byte_clk, esc_clk);
732
733 reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG);
734 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
735 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
736 | DSIM_BYTE_CLK_SRC_MASK);
737 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
738 | DSIM_ESC_PRESCALER(esc_div)
739 | DSIM_LANE_ESC_CLK_EN_CLK
740 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
741 | DSIM_BYTE_CLK_SRC(0)
742 | DSIM_TX_REQUEST_HSCLK;
743 samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg);
744
745 return 0;
746}
747
748static void samsung_dsim_set_phy_ctrl(struct samsung_dsim *dsi)
749{
750 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
751 const unsigned int *reg_values = driver_data->reg_values;
752 u32 reg;
753 struct phy_configure_opts_mipi_dphy cfg;
754 int clk_prepare, lpx, clk_zero, clk_post, clk_trail;
755 int hs_exit, hs_prepare, hs_zero, hs_trail;
756 unsigned long long byte_clock = dsi->hs_clock / 8;
757
758 if (driver_data->has_freqband)
759 return;
760
761 phy_mipi_dphy_get_default_config_for_hsclk(dsi->hs_clock,
762 dsi->lanes, &cfg);
763
764 /*
765 * TODO:
766 * The tech Applications Processor manuals for i.MX8M Mini, Nano,
767 * and Plus don't state what the definition of the PHYTIMING
768 * bits are beyond their address and bit position.
769 * After reviewing NXP's downstream code, it appears
770 * that the various PHYTIMING registers take the number
771 * of cycles and use various dividers on them. This
772 * calculation does not result in an exact match to the
773 * downstream code, but it is very close to the values
774 * generated by their lookup table, and it appears
775 * to sync at a variety of resolutions. If someone
776 * can get a more accurate mathematical equation needed
777 * for these registers, this should be updated.
778 */
779
780 lpx = PS_TO_CYCLE(cfg.lpx, byte_clock);
781 hs_exit = PS_TO_CYCLE(cfg.hs_exit, byte_clock);
782 clk_prepare = PS_TO_CYCLE(cfg.clk_prepare, byte_clock);
783 clk_zero = PS_TO_CYCLE(cfg.clk_zero, byte_clock);
784 clk_post = PS_TO_CYCLE(cfg.clk_post, byte_clock);
785 clk_trail = PS_TO_CYCLE(cfg.clk_trail, byte_clock);
786 hs_prepare = PS_TO_CYCLE(cfg.hs_prepare, byte_clock);
787 hs_zero = PS_TO_CYCLE(cfg.hs_zero, byte_clock);
788 hs_trail = PS_TO_CYCLE(cfg.hs_trail, byte_clock);
789
790 /* B D-PHY: D-PHY Master & Slave Analog Block control */
791 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] |
792 reg_values[PHYCTRL_SLEW_UP];
793
794 samsung_dsim_write(dsi, DSIM_PHYCTRL_REG, reg);
795
796 /*
797 * T LPX: Transmitted length of any Low-Power state period
798 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
799 * burst
800 */
801
802 reg = DSIM_PHYTIMING_LPX(lpx) | DSIM_PHYTIMING_HS_EXIT(hs_exit);
803
804 samsung_dsim_write(dsi, DSIM_PHYTIMING_REG, reg);
805
806 /*
807 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
808 * Line state immediately before the HS-0 Line state starting the
809 * HS transmission
810 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
811 * transmitting the Clock.
812 * T CLK_POST: Time that the transmitter continues to send HS clock
813 * after the last associated Data Lane has transitioned to LP Mode
814 * Interval is defined as the period from the end of T HS-TRAIL to
815 * the beginning of T CLK-TRAIL
816 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
817 * the last payload clock bit of a HS transmission burst
818 */
819
820 reg = DSIM_PHYTIMING1_CLK_PREPARE(clk_prepare) |
821 DSIM_PHYTIMING1_CLK_ZERO(clk_zero) |
822 DSIM_PHYTIMING1_CLK_POST(clk_post) |
823 DSIM_PHYTIMING1_CLK_TRAIL(clk_trail);
824
825 samsung_dsim_write(dsi, DSIM_PHYTIMING1_REG, reg);
826
827 /*
828 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
829 * Line state immediately before the HS-0 Line state starting the
830 * HS transmission
831 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
832 * transmitting the Sync sequence.
833 * T HS-TRAIL: Time that the transmitter drives the flipped differential
834 * state after last payload data bit of a HS transmission burst
835 */
836
837 reg = DSIM_PHYTIMING2_HS_PREPARE(hs_prepare) |
838 DSIM_PHYTIMING2_HS_ZERO(hs_zero) |
839 DSIM_PHYTIMING2_HS_TRAIL(hs_trail);
840
841 samsung_dsim_write(dsi, DSIM_PHYTIMING2_REG, reg);
842}
843
844static void samsung_dsim_disable_clock(struct samsung_dsim *dsi)
845{
846 u32 reg;
847
848 reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG);
849 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
850 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
851 samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg);
852
853 reg = samsung_dsim_read(dsi, DSIM_PLLCTRL_REG);
854 reg &= ~DSIM_PLL_EN;
855 samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
856}
857
858static void samsung_dsim_enable_lane(struct samsung_dsim *dsi, u32 lane)
859{
860 u32 reg = samsung_dsim_read(dsi, DSIM_CONFIG_REG);
861
862 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK |
863 DSIM_LANE_EN(lane));
864 samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg);
865}
866
867static int samsung_dsim_init_link(struct samsung_dsim *dsi)
868{
869 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
870 int timeout;
871 u32 reg;
872 u32 lanes_mask;
873
874 /* Initialize FIFO pointers */
875 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG);
876 reg &= ~0x1f;
877 samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg);
878
879 usleep_range(9000, 11000);
880
881 reg |= 0x1f;
882 samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg);
883 usleep_range(9000, 11000);
884
885 /* DSI configuration */
886 reg = 0;
887
888 /*
889 * The first bit of mode_flags specifies display configuration.
890 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
891 * mode, otherwise it will support command mode.
892 */
893 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
894 reg |= DSIM_VIDEO_MODE;
895
896 /*
897 * The user manual describes that following bits are ignored in
898 * command mode.
899 */
900 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
901 reg |= DSIM_MFLUSH_VS;
902 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
903 reg |= DSIM_SYNC_INFORM;
904 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
905 reg |= DSIM_BURST_MODE;
906 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
907 reg |= DSIM_AUTO_MODE;
908 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
909 reg |= DSIM_HSE_DISABLE_MODE;
910 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP)
911 reg |= DSIM_HFP_DISABLE_MODE;
912 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP)
913 reg |= DSIM_HBP_DISABLE_MODE;
914 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA)
915 reg |= DSIM_HSA_DISABLE_MODE;
916 }
917
918 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
919 reg |= DSIM_EOT_DISABLE;
920
921 switch (dsi->format) {
922 case MIPI_DSI_FMT_RGB888:
923 reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
924 break;
925 case MIPI_DSI_FMT_RGB666:
926 reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
927 break;
928 case MIPI_DSI_FMT_RGB666_PACKED:
929 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
930 break;
931 case MIPI_DSI_FMT_RGB565:
932 reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
933 break;
934 default:
935 dev_err(dsi->dev, "invalid pixel format\n");
936 return -EINVAL;
937 }
938
939 /*
940 * Use non-continuous clock mode if the periparal wants and
941 * host controller supports
942 *
943 * In non-continous clock mode, host controller will turn off
944 * the HS clock between high-speed transmissions to reduce
945 * power consumption.
946 */
947 if (driver_data->has_clklane_stop &&
948 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
949 reg |= DSIM_CLKLANE_STOP;
950 samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg);
951
952 lanes_mask = BIT(dsi->lanes) - 1;
953 samsung_dsim_enable_lane(dsi, lanes_mask);
954
955 /* Check clock and data lane state are stop state */
956 timeout = 100;
957 do {
958 if (timeout-- == 0) {
959 dev_err(dsi->dev, "waiting for bus lanes timed out\n");
960 return -EFAULT;
961 }
962
963 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG);
964 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
965 != DSIM_STOP_STATE_DAT(lanes_mask))
966 continue;
967 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
968
969 reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
970 reg &= ~DSIM_STOP_STATE_CNT_MASK;
971 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]);
972 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg);
973
974 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
975 samsung_dsim_write(dsi, DSIM_TIMEOUT_REG, reg);
976
977 return 0;
978}
979
980static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi)
981{
982 struct drm_display_mode *m = &dsi->mode;
983 unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;
984 u32 reg;
985
986 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
987 u64 byte_clk = dsi->hs_clock / 8;
988 u64 pix_clk = m->clock * 1000;
989
990 int hfp = DIV64_U64_ROUND_UP((m->hsync_start - m->hdisplay) * byte_clk, pix_clk);
991 int hbp = DIV64_U64_ROUND_UP((m->htotal - m->hsync_end) * byte_clk, pix_clk);
992 int hsa = DIV64_U64_ROUND_UP((m->hsync_end - m->hsync_start) * byte_clk, pix_clk);
993
994 /* remove packet overhead when possible */
995 hfp = max(hfp - 6, 0);
996 hbp = max(hbp - 6, 0);
997 hsa = max(hsa - 6, 0);
998
999 dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u",
1000 hfp, hbp, hsa);
1001
1002 reg = DSIM_CMD_ALLOW(0xf)
1003 | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay)
1004 | DSIM_MAIN_VBP(m->vtotal - m->vsync_end);
1005 samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg);
1006
1007 reg = DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp);
1008 samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg);
1009
1010 reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)
1011 | DSIM_MAIN_HSA(hsa);
1012 samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg);
1013 }
1014 reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) |
1015 DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol);
1016
1017 samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg);
1018
1019 dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay);
1020}
1021
1022static void samsung_dsim_set_display_enable(struct samsung_dsim *dsi, bool enable)
1023{
1024 u32 reg;
1025
1026 reg = samsung_dsim_read(dsi, DSIM_MDRESOL_REG);
1027 if (enable)
1028 reg |= DSIM_MAIN_STAND_BY;
1029 else
1030 reg &= ~DSIM_MAIN_STAND_BY;
1031 samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg);
1032}
1033
1034static int samsung_dsim_wait_for_hdr_fifo(struct samsung_dsim *dsi)
1035{
1036 int timeout = 2000;
1037
1038 do {
1039 u32 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG);
1040
1041 if (!dsi->driver_data->has_broken_fifoctrl_emptyhdr) {
1042 if (reg & DSIM_SFR_HEADER_EMPTY)
1043 return 0;
1044 } else {
1045 if (!(reg & DSIM_SFR_HEADER_FULL)) {
1046 /*
1047 * Wait a little bit, so the pending data can
1048 * actually leave the FIFO to avoid overflow.
1049 */
1050 if (!cond_resched())
1051 usleep_range(950, 1050);
1052 return 0;
1053 }
1054 }
1055
1056 if (!cond_resched())
1057 usleep_range(950, 1050);
1058 } while (--timeout);
1059
1060 return -ETIMEDOUT;
1061}
1062
1063static void samsung_dsim_set_cmd_lpm(struct samsung_dsim *dsi, bool lpm)
1064{
1065 u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
1066
1067 if (lpm)
1068 v |= DSIM_CMD_LPDT_LP;
1069 else
1070 v &= ~DSIM_CMD_LPDT_LP;
1071
1072 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v);
1073}
1074
1075static void samsung_dsim_force_bta(struct samsung_dsim *dsi)
1076{
1077 u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG);
1078
1079 v |= DSIM_FORCE_BTA;
1080 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v);
1081}
1082
1083static void samsung_dsim_send_to_fifo(struct samsung_dsim *dsi,
1084 struct samsung_dsim_transfer *xfer)
1085{
1086 struct device *dev = dsi->dev;
1087 struct mipi_dsi_packet *pkt = &xfer->packet;
1088 const u8 *payload = pkt->payload + xfer->tx_done;
1089 u16 length = pkt->payload_length - xfer->tx_done;
1090 bool first = !xfer->tx_done;
1091 u32 reg;
1092
1093 dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n",
1094 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done);
1095
1096 if (length > DSI_TX_FIFO_SIZE)
1097 length = DSI_TX_FIFO_SIZE;
1098
1099 xfer->tx_done += length;
1100
1101 /* Send payload */
1102 while (length >= 4) {
1103 reg = get_unaligned_le32(payload);
1104 samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg);
1105 payload += 4;
1106 length -= 4;
1107 }
1108
1109 reg = 0;
1110 switch (length) {
1111 case 3:
1112 reg |= payload[2] << 16;
1113 fallthrough;
1114 case 2:
1115 reg |= payload[1] << 8;
1116 fallthrough;
1117 case 1:
1118 reg |= payload[0];
1119 samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg);
1120 break;
1121 }
1122
1123 /* Send packet header */
1124 if (!first)
1125 return;
1126
1127 reg = get_unaligned_le32(pkt->header);
1128 if (samsung_dsim_wait_for_hdr_fifo(dsi)) {
1129 dev_err(dev, "waiting for header FIFO timed out\n");
1130 return;
1131 }
1132
1133 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
1134 dsi->state & DSIM_STATE_CMD_LPM)) {
1135 samsung_dsim_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
1136 dsi->state ^= DSIM_STATE_CMD_LPM;
1137 }
1138
1139 samsung_dsim_write(dsi, DSIM_PKTHDR_REG, reg);
1140
1141 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
1142 samsung_dsim_force_bta(dsi);
1143}
1144
1145static void samsung_dsim_read_from_fifo(struct samsung_dsim *dsi,
1146 struct samsung_dsim_transfer *xfer)
1147{
1148 u8 *payload = xfer->rx_payload + xfer->rx_done;
1149 bool first = !xfer->rx_done;
1150 struct device *dev = dsi->dev;
1151 u16 length;
1152 u32 reg;
1153
1154 if (first) {
1155 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1156
1157 switch (reg & 0x3f) {
1158 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
1159 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1160 if (xfer->rx_len >= 2) {
1161 payload[1] = reg >> 16;
1162 ++xfer->rx_done;
1163 }
1164 fallthrough;
1165 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
1166 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1167 payload[0] = reg >> 8;
1168 ++xfer->rx_done;
1169 xfer->rx_len = xfer->rx_done;
1170 xfer->result = 0;
1171 goto clear_fifo;
1172 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1173 dev_err(dev, "DSI Error Report: 0x%04x\n", (reg >> 8) & 0xffff);
1174 xfer->result = 0;
1175 goto clear_fifo;
1176 }
1177
1178 length = (reg >> 8) & 0xffff;
1179 if (length > xfer->rx_len) {
1180 dev_err(dev,
1181 "response too long (%u > %u bytes), stripping\n",
1182 xfer->rx_len, length);
1183 length = xfer->rx_len;
1184 } else if (length < xfer->rx_len) {
1185 xfer->rx_len = length;
1186 }
1187 }
1188
1189 length = xfer->rx_len - xfer->rx_done;
1190 xfer->rx_done += length;
1191
1192 /* Receive payload */
1193 while (length >= 4) {
1194 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1195 payload[0] = (reg >> 0) & 0xff;
1196 payload[1] = (reg >> 8) & 0xff;
1197 payload[2] = (reg >> 16) & 0xff;
1198 payload[3] = (reg >> 24) & 0xff;
1199 payload += 4;
1200 length -= 4;
1201 }
1202
1203 if (length) {
1204 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1205 switch (length) {
1206 case 3:
1207 payload[2] = (reg >> 16) & 0xff;
1208 fallthrough;
1209 case 2:
1210 payload[1] = (reg >> 8) & 0xff;
1211 fallthrough;
1212 case 1:
1213 payload[0] = reg & 0xff;
1214 }
1215 }
1216
1217 if (xfer->rx_done == xfer->rx_len)
1218 xfer->result = 0;
1219
1220clear_fifo:
1221 length = DSI_RX_FIFO_SIZE / 4;
1222 do {
1223 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG);
1224 if (reg == DSI_RX_FIFO_EMPTY)
1225 break;
1226 } while (--length);
1227}
1228
1229static void samsung_dsim_transfer_start(struct samsung_dsim *dsi)
1230{
1231 unsigned long flags;
1232 struct samsung_dsim_transfer *xfer;
1233 bool start = false;
1234
1235again:
1236 spin_lock_irqsave(&dsi->transfer_lock, flags);
1237
1238 if (list_empty(&dsi->transfer_list)) {
1239 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1240 return;
1241 }
1242
1243 xfer = list_first_entry(&dsi->transfer_list,
1244 struct samsung_dsim_transfer, list);
1245
1246 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1247
1248 if (xfer->packet.payload_length &&
1249 xfer->tx_done == xfer->packet.payload_length)
1250 /* waiting for RX */
1251 return;
1252
1253 samsung_dsim_send_to_fifo(dsi, xfer);
1254
1255 if (xfer->packet.payload_length || xfer->rx_len)
1256 return;
1257
1258 xfer->result = 0;
1259 complete(&xfer->completed);
1260
1261 spin_lock_irqsave(&dsi->transfer_lock, flags);
1262
1263 list_del_init(&xfer->list);
1264 start = !list_empty(&dsi->transfer_list);
1265
1266 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1267
1268 if (start)
1269 goto again;
1270}
1271
1272static bool samsung_dsim_transfer_finish(struct samsung_dsim *dsi)
1273{
1274 struct samsung_dsim_transfer *xfer;
1275 unsigned long flags;
1276 bool start = true;
1277
1278 spin_lock_irqsave(&dsi->transfer_lock, flags);
1279
1280 if (list_empty(&dsi->transfer_list)) {
1281 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1282 return false;
1283 }
1284
1285 xfer = list_first_entry(&dsi->transfer_list,
1286 struct samsung_dsim_transfer, list);
1287
1288 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1289
1290 dev_dbg(dsi->dev,
1291 "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n",
1292 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len,
1293 xfer->rx_done);
1294
1295 if (xfer->tx_done != xfer->packet.payload_length)
1296 return true;
1297
1298 if (xfer->rx_done != xfer->rx_len)
1299 samsung_dsim_read_from_fifo(dsi, xfer);
1300
1301 if (xfer->rx_done != xfer->rx_len)
1302 return true;
1303
1304 spin_lock_irqsave(&dsi->transfer_lock, flags);
1305
1306 list_del_init(&xfer->list);
1307 start = !list_empty(&dsi->transfer_list);
1308
1309 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1310
1311 if (!xfer->rx_len)
1312 xfer->result = 0;
1313 complete(&xfer->completed);
1314
1315 return start;
1316}
1317
1318static void samsung_dsim_remove_transfer(struct samsung_dsim *dsi,
1319 struct samsung_dsim_transfer *xfer)
1320{
1321 unsigned long flags;
1322 bool start;
1323
1324 spin_lock_irqsave(&dsi->transfer_lock, flags);
1325
1326 if (!list_empty(&dsi->transfer_list) &&
1327 xfer == list_first_entry(&dsi->transfer_list,
1328 struct samsung_dsim_transfer, list)) {
1329 list_del_init(&xfer->list);
1330 start = !list_empty(&dsi->transfer_list);
1331 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1332 if (start)
1333 samsung_dsim_transfer_start(dsi);
1334 return;
1335 }
1336
1337 list_del_init(&xfer->list);
1338
1339 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1340}
1341
1342static int samsung_dsim_transfer(struct samsung_dsim *dsi,
1343 struct samsung_dsim_transfer *xfer)
1344{
1345 unsigned long flags;
1346 bool stopped;
1347
1348 xfer->tx_done = 0;
1349 xfer->rx_done = 0;
1350 xfer->result = -ETIMEDOUT;
1351 init_completion(&xfer->completed);
1352
1353 spin_lock_irqsave(&dsi->transfer_lock, flags);
1354
1355 stopped = list_empty(&dsi->transfer_list);
1356 list_add_tail(&xfer->list, &dsi->transfer_list);
1357
1358 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1359
1360 if (stopped)
1361 samsung_dsim_transfer_start(dsi);
1362
1363 wait_for_completion_timeout(&xfer->completed,
1364 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1365 if (xfer->result == -ETIMEDOUT) {
1366 struct mipi_dsi_packet *pkt = &xfer->packet;
1367
1368 samsung_dsim_remove_transfer(dsi, xfer);
1369 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header,
1370 (int)pkt->payload_length, pkt->payload);
1371 return -ETIMEDOUT;
1372 }
1373
1374 /* Also covers hardware timeout condition */
1375 return xfer->result;
1376}
1377
1378static irqreturn_t samsung_dsim_irq(int irq, void *dev_id)
1379{
1380 struct samsung_dsim *dsi = dev_id;
1381 u32 status;
1382
1383 status = samsung_dsim_read(dsi, DSIM_INTSRC_REG);
1384 if (!status) {
1385 static unsigned long j;
1386
1387 if (printk_timed_ratelimit(&j, 500))
1388 dev_warn(dsi->dev, "spurious interrupt\n");
1389 return IRQ_HANDLED;
1390 }
1391 samsung_dsim_write(dsi, DSIM_INTSRC_REG, status);
1392
1393 if (status & DSIM_INT_SW_RST_RELEASE) {
1394 unsigned long mask = ~(DSIM_INT_RX_DONE |
1395 DSIM_INT_SFR_FIFO_EMPTY |
1396 DSIM_INT_SFR_HDR_FIFO_EMPTY |
1397 DSIM_INT_RX_ECC_ERR |
1398 DSIM_INT_SW_RST_RELEASE);
1399 samsung_dsim_write(dsi, DSIM_INTMSK_REG, mask);
1400 complete(&dsi->completed);
1401 return IRQ_HANDLED;
1402 }
1403
1404 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY |
1405 DSIM_INT_PLL_STABLE)))
1406 return IRQ_HANDLED;
1407
1408 if (samsung_dsim_transfer_finish(dsi))
1409 samsung_dsim_transfer_start(dsi);
1410
1411 return IRQ_HANDLED;
1412}
1413
1414static void samsung_dsim_enable_irq(struct samsung_dsim *dsi)
1415{
1416 enable_irq(dsi->irq);
1417
1418 if (dsi->te_gpio)
1419 enable_irq(gpiod_to_irq(dsi->te_gpio));
1420}
1421
1422static void samsung_dsim_disable_irq(struct samsung_dsim *dsi)
1423{
1424 if (dsi->te_gpio)
1425 disable_irq(gpiod_to_irq(dsi->te_gpio));
1426
1427 disable_irq(dsi->irq);
1428}
1429
1430static int samsung_dsim_init(struct samsung_dsim *dsi)
1431{
1432 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
1433
1434 if (dsi->state & DSIM_STATE_INITIALIZED)
1435 return 0;
1436
1437 samsung_dsim_reset(dsi);
1438 samsung_dsim_enable_irq(dsi);
1439
1440 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST)
1441 samsung_dsim_enable_lane(dsi, BIT(dsi->lanes) - 1);
1442
1443 samsung_dsim_enable_clock(dsi);
1444 if (driver_data->wait_for_reset)
1445 samsung_dsim_wait_for_reset(dsi);
1446 samsung_dsim_set_phy_ctrl(dsi);
1447 samsung_dsim_init_link(dsi);
1448
1449 dsi->state |= DSIM_STATE_INITIALIZED;
1450
1451 return 0;
1452}
1453
1454static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge,
1455 struct drm_bridge_state *old_bridge_state)
1456{
1457 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1458 int ret;
1459
1460 if (dsi->state & DSIM_STATE_ENABLED)
1461 return;
1462
1463 ret = pm_runtime_resume_and_get(dsi->dev);
1464 if (ret < 0) {
1465 dev_err(dsi->dev, "failed to enable DSI device.\n");
1466 return;
1467 }
1468
1469 dsi->state |= DSIM_STATE_ENABLED;
1470
1471 /*
1472 * For Exynos-DSIM the downstream bridge, or panel are expecting
1473 * the host initialization during DSI transfer.
1474 */
1475 if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) {
1476 ret = samsung_dsim_init(dsi);
1477 if (ret)
1478 return;
1479 }
1480}
1481
1482static void samsung_dsim_atomic_enable(struct drm_bridge *bridge,
1483 struct drm_bridge_state *old_bridge_state)
1484{
1485 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1486
1487 samsung_dsim_set_display_mode(dsi);
1488 samsung_dsim_set_display_enable(dsi, true);
1489
1490 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE;
1491}
1492
1493static void samsung_dsim_atomic_disable(struct drm_bridge *bridge,
1494 struct drm_bridge_state *old_bridge_state)
1495{
1496 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1497
1498 if (!(dsi->state & DSIM_STATE_ENABLED))
1499 return;
1500
1501 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE;
1502}
1503
1504static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge,
1505 struct drm_bridge_state *old_bridge_state)
1506{
1507 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1508
1509 samsung_dsim_set_display_enable(dsi, false);
1510
1511 dsi->state &= ~DSIM_STATE_ENABLED;
1512 pm_runtime_put_sync(dsi->dev);
1513}
1514
1515/*
1516 * This pixel output formats list referenced from,
1517 * AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022
1518 * 3.7.4 Pixel formats
1519 * Table 14. DSI pixel packing formats
1520 */
1521static const u32 samsung_dsim_pixel_output_fmts[] = {
1522 MEDIA_BUS_FMT_YUYV10_1X20,
1523 MEDIA_BUS_FMT_YUYV12_1X24,
1524 MEDIA_BUS_FMT_UYVY8_1X16,
1525 MEDIA_BUS_FMT_RGB101010_1X30,
1526 MEDIA_BUS_FMT_RGB121212_1X36,
1527 MEDIA_BUS_FMT_RGB565_1X16,
1528 MEDIA_BUS_FMT_RGB666_1X18,
1529 MEDIA_BUS_FMT_RGB888_1X24,
1530};
1531
1532static bool samsung_dsim_pixel_output_fmt_supported(u32 fmt)
1533{
1534 int i;
1535
1536 if (fmt == MEDIA_BUS_FMT_FIXED)
1537 return false;
1538
1539 for (i = 0; i < ARRAY_SIZE(samsung_dsim_pixel_output_fmts); i++) {
1540 if (samsung_dsim_pixel_output_fmts[i] == fmt)
1541 return true;
1542 }
1543
1544 return false;
1545}
1546
1547static u32 *
1548samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
1549 struct drm_bridge_state *bridge_state,
1550 struct drm_crtc_state *crtc_state,
1551 struct drm_connector_state *conn_state,
1552 u32 output_fmt,
1553 unsigned int *num_input_fmts)
1554{
1555 u32 *input_fmts;
1556
1557 input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
1558 if (!input_fmts)
1559 return NULL;
1560
1561 if (!samsung_dsim_pixel_output_fmt_supported(output_fmt))
1562 /*
1563 * Some bridge/display drivers are still not able to pass the
1564 * correct format, so handle those pipelines by falling back
1565 * to the default format till the supported formats finalized.
1566 */
1567 output_fmt = MEDIA_BUS_FMT_RGB888_1X24;
1568
1569 input_fmts[0] = output_fmt;
1570 *num_input_fmts = 1;
1571
1572 return input_fmts;
1573}
1574
1575static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
1576 struct drm_bridge_state *bridge_state,
1577 struct drm_crtc_state *crtc_state,
1578 struct drm_connector_state *conn_state)
1579{
1580 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1581 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1582
1583 /*
1584 * The i.MX8M Mini/Nano glue logic between LCDIF and DSIM
1585 * inverts HS/VS/DE sync signals polarity, therefore, while
1586 * i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020
1587 * 13.6.3.5.2 RGB interface
1588 * i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022
1589 * 13.6.2.7.2 RGB interface
1590 * both claim "Vsync, Hsync, and VDEN are active high signals.", the
1591 * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW.
1592 *
1593 * The i.MX8M Plus glue logic between LCDIFv3 and DSIM does not
1594 * implement the same behavior, therefore LCDIFv3 must generate
1595 * HS/VS/DE signals active HIGH.
1596 */
1597 if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) {
1598 adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1599 adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1600 } else if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MP) {
1601 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1602 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1603 }
1604
1605 return 0;
1606}
1607
1608static void samsung_dsim_mode_set(struct drm_bridge *bridge,
1609 const struct drm_display_mode *mode,
1610 const struct drm_display_mode *adjusted_mode)
1611{
1612 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1613
1614 drm_mode_copy(&dsi->mode, adjusted_mode);
1615}
1616
1617static int samsung_dsim_attach(struct drm_bridge *bridge,
1618 enum drm_bridge_attach_flags flags)
1619{
1620 struct samsung_dsim *dsi = bridge_to_dsi(bridge);
1621
1622 return drm_bridge_attach(bridge->encoder, dsi->out_bridge, bridge,
1623 flags);
1624}
1625
1626static const struct drm_bridge_funcs samsung_dsim_bridge_funcs = {
1627 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1628 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1629 .atomic_reset = drm_atomic_helper_bridge_reset,
1630 .atomic_get_input_bus_fmts = samsung_dsim_atomic_get_input_bus_fmts,
1631 .atomic_check = samsung_dsim_atomic_check,
1632 .atomic_pre_enable = samsung_dsim_atomic_pre_enable,
1633 .atomic_enable = samsung_dsim_atomic_enable,
1634 .atomic_disable = samsung_dsim_atomic_disable,
1635 .atomic_post_disable = samsung_dsim_atomic_post_disable,
1636 .mode_set = samsung_dsim_mode_set,
1637 .attach = samsung_dsim_attach,
1638};
1639
1640static irqreturn_t samsung_dsim_te_irq_handler(int irq, void *dev_id)
1641{
1642 struct samsung_dsim *dsi = (struct samsung_dsim *)dev_id;
1643 const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1644
1645 if (pdata->host_ops && pdata->host_ops->te_irq_handler)
1646 return pdata->host_ops->te_irq_handler(dsi);
1647
1648 return IRQ_HANDLED;
1649}
1650
1651static int samsung_dsim_register_te_irq(struct samsung_dsim *dsi, struct device *dev)
1652{
1653 int te_gpio_irq;
1654 int ret;
1655
1656 dsi->te_gpio = devm_gpiod_get_optional(dev, "te", GPIOD_IN);
1657 if (!dsi->te_gpio)
1658 return 0;
1659 else if (IS_ERR(dsi->te_gpio))
1660 return dev_err_probe(dev, PTR_ERR(dsi->te_gpio), "failed to get te GPIO\n");
1661
1662 te_gpio_irq = gpiod_to_irq(dsi->te_gpio);
1663
1664 ret = request_threaded_irq(te_gpio_irq, samsung_dsim_te_irq_handler, NULL,
1665 IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, "TE", dsi);
1666 if (ret) {
1667 dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1668 gpiod_put(dsi->te_gpio);
1669 return ret;
1670 }
1671
1672 return 0;
1673}
1674
1675static int samsung_dsim_host_attach(struct mipi_dsi_host *host,
1676 struct mipi_dsi_device *device)
1677{
1678 struct samsung_dsim *dsi = host_to_dsi(host);
1679 const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1680 struct device *dev = dsi->dev;
1681 struct device_node *np = dev->of_node;
1682 struct device_node *remote;
1683 struct drm_panel *panel;
1684 int ret;
1685
1686 /*
1687 * Devices can also be child nodes when we also control that device
1688 * through the upstream device (ie, MIPI-DCS for a MIPI-DSI device).
1689 *
1690 * Lookup for a child node of the given parent that isn't either port
1691 * or ports.
1692 */
1693 for_each_available_child_of_node(np, remote) {
1694 if (of_node_name_eq(remote, "port") ||
1695 of_node_name_eq(remote, "ports"))
1696 continue;
1697
1698 goto of_find_panel_or_bridge;
1699 }
1700
1701 /*
1702 * of_graph_get_remote_node() produces a noisy error message if port
1703 * node isn't found and the absence of the port is a legit case here,
1704 * so at first we silently check whether graph presents in the
1705 * device-tree node.
1706 */
1707 if (!of_graph_is_present(np))
1708 return -ENODEV;
1709
1710 remote = of_graph_get_remote_node(np, 1, 0);
1711
1712of_find_panel_or_bridge:
1713 if (!remote)
1714 return -ENODEV;
1715
1716 panel = of_drm_find_panel(remote);
1717 if (!IS_ERR(panel)) {
1718 dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel);
1719 } else {
1720 dsi->out_bridge = of_drm_find_bridge(remote);
1721 if (!dsi->out_bridge)
1722 dsi->out_bridge = ERR_PTR(-EINVAL);
1723 }
1724
1725 of_node_put(remote);
1726
1727 if (IS_ERR(dsi->out_bridge)) {
1728 ret = PTR_ERR(dsi->out_bridge);
1729 DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret);
1730 return ret;
1731 }
1732
1733 DRM_DEV_INFO(dev, "Attached %s device (lanes:%d bpp:%d mode-flags:0x%lx)\n",
1734 device->name, device->lanes,
1735 mipi_dsi_pixel_format_to_bpp(device->format),
1736 device->mode_flags);
1737
1738 drm_bridge_add(&dsi->bridge);
1739
1740 /*
1741 * This is a temporary solution and should be made by more generic way.
1742 *
1743 * If attached panel device is for command mode one, dsi should register
1744 * TE interrupt handler.
1745 */
1746 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1747 ret = samsung_dsim_register_te_irq(dsi, &device->dev);
1748 if (ret)
1749 return ret;
1750 }
1751
1752 if (pdata->host_ops && pdata->host_ops->attach) {
1753 ret = pdata->host_ops->attach(dsi, device);
1754 if (ret)
1755 return ret;
1756 }
1757
1758 dsi->lanes = device->lanes;
1759 dsi->format = device->format;
1760 dsi->mode_flags = device->mode_flags;
1761
1762 return 0;
1763}
1764
1765static void samsung_dsim_unregister_te_irq(struct samsung_dsim *dsi)
1766{
1767 if (dsi->te_gpio) {
1768 free_irq(gpiod_to_irq(dsi->te_gpio), dsi);
1769 gpiod_put(dsi->te_gpio);
1770 }
1771}
1772
1773static int samsung_dsim_host_detach(struct mipi_dsi_host *host,
1774 struct mipi_dsi_device *device)
1775{
1776 struct samsung_dsim *dsi = host_to_dsi(host);
1777 const struct samsung_dsim_plat_data *pdata = dsi->plat_data;
1778
1779 dsi->out_bridge = NULL;
1780
1781 if (pdata->host_ops && pdata->host_ops->detach)
1782 pdata->host_ops->detach(dsi, device);
1783
1784 samsung_dsim_unregister_te_irq(dsi);
1785
1786 drm_bridge_remove(&dsi->bridge);
1787
1788 return 0;
1789}
1790
1791static ssize_t samsung_dsim_host_transfer(struct mipi_dsi_host *host,
1792 const struct mipi_dsi_msg *msg)
1793{
1794 struct samsung_dsim *dsi = host_to_dsi(host);
1795 struct samsung_dsim_transfer xfer;
1796 int ret;
1797
1798 if (!(dsi->state & DSIM_STATE_ENABLED))
1799 return -EINVAL;
1800
1801 ret = samsung_dsim_init(dsi);
1802 if (ret)
1803 return ret;
1804
1805 ret = mipi_dsi_create_packet(&xfer.packet, msg);
1806 if (ret < 0)
1807 return ret;
1808
1809 xfer.rx_len = msg->rx_len;
1810 xfer.rx_payload = msg->rx_buf;
1811 xfer.flags = msg->flags;
1812
1813 ret = samsung_dsim_transfer(dsi, &xfer);
1814 return (ret < 0) ? ret : xfer.rx_done;
1815}
1816
1817static const struct mipi_dsi_host_ops samsung_dsim_ops = {
1818 .attach = samsung_dsim_host_attach,
1819 .detach = samsung_dsim_host_detach,
1820 .transfer = samsung_dsim_host_transfer,
1821};
1822
1823static int samsung_dsim_of_read_u32(const struct device_node *np,
1824 const char *propname, u32 *out_value, bool optional)
1825{
1826 int ret = of_property_read_u32(np, propname, out_value);
1827
1828 if (ret < 0 && !optional)
1829 pr_err("%pOF: failed to get '%s' property\n", np, propname);
1830
1831 return ret;
1832}
1833
1834static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
1835{
1836 struct device *dev = dsi->dev;
1837 struct device_node *node = dev->of_node;
1838 u32 lane_polarities[5] = { 0 };
1839 struct device_node *endpoint;
1840 int i, nr_lanes, ret;
1841
1842 ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
1843 &dsi->pll_clk_rate, 1);
1844 /* If it doesn't exist, read it from the clock instead of failing */
1845 if (ret < 0) {
1846 dev_dbg(dev, "Using sclk_mipi for pll clock frequency\n");
1847 dsi->pll_clk = devm_clk_get(dev, "sclk_mipi");
1848 if (IS_ERR(dsi->pll_clk))
1849 return PTR_ERR(dsi->pll_clk);
1850 }
1851
1852 /* If it doesn't exist, use pixel clock instead of failing */
1853 ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency",
1854 &dsi->burst_clk_rate, 1);
1855 if (ret < 0) {
1856 dev_dbg(dev, "Using pixel clock for HS clock frequency\n");
1857 dsi->burst_clk_rate = 0;
1858 }
1859
1860 ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency",
1861 &dsi->esc_clk_rate, 0);
1862 if (ret < 0)
1863 return ret;
1864
1865 endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
1866 nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
1867 if (nr_lanes > 0 && nr_lanes <= 4) {
1868 /* Polarity 0 is clock lane, 1..4 are data lanes. */
1869 of_property_read_u32_array(endpoint, "lane-polarities",
1870 lane_polarities, nr_lanes + 1);
1871 for (i = 1; i <= nr_lanes; i++) {
1872 if (lane_polarities[1] != lane_polarities[i])
1873 DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match");
1874 }
1875 if (lane_polarities[0])
1876 dsi->swap_dn_dp_clk = true;
1877 if (lane_polarities[1])
1878 dsi->swap_dn_dp_data = true;
1879 }
1880
1881 return 0;
1882}
1883
1884static int generic_dsim_register_host(struct samsung_dsim *dsi)
1885{
1886 return mipi_dsi_host_register(&dsi->dsi_host);
1887}
1888
1889static void generic_dsim_unregister_host(struct samsung_dsim *dsi)
1890{
1891 mipi_dsi_host_unregister(&dsi->dsi_host);
1892}
1893
1894static const struct samsung_dsim_host_ops generic_dsim_host_ops = {
1895 .register_host = generic_dsim_register_host,
1896 .unregister_host = generic_dsim_unregister_host,
1897};
1898
1899static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_high = {
1900 .input_bus_flags = DRM_BUS_FLAG_DE_HIGH,
1901};
1902
1903static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_low = {
1904 .input_bus_flags = DRM_BUS_FLAG_DE_LOW,
1905};
1906
1907int samsung_dsim_probe(struct platform_device *pdev)
1908{
1909 struct device *dev = &pdev->dev;
1910 struct samsung_dsim *dsi;
1911 int ret, i;
1912
1913 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1914 if (!dsi)
1915 return -ENOMEM;
1916
1917 init_completion(&dsi->completed);
1918 spin_lock_init(&dsi->transfer_lock);
1919 INIT_LIST_HEAD(&dsi->transfer_list);
1920
1921 dsi->dsi_host.ops = &samsung_dsim_ops;
1922 dsi->dsi_host.dev = dev;
1923
1924 dsi->dev = dev;
1925 dsi->plat_data = of_device_get_match_data(dev);
1926 dsi->driver_data = samsung_dsim_types[dsi->plat_data->hw_type];
1927
1928 dsi->supplies[0].supply = "vddcore";
1929 dsi->supplies[1].supply = "vddio";
1930 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1931 dsi->supplies);
1932 if (ret)
1933 return dev_err_probe(dev, ret, "failed to get regulators\n");
1934
1935 dsi->clks = devm_kcalloc(dev, dsi->driver_data->num_clks,
1936 sizeof(*dsi->clks), GFP_KERNEL);
1937 if (!dsi->clks)
1938 return -ENOMEM;
1939
1940 for (i = 0; i < dsi->driver_data->num_clks; i++) {
1941 dsi->clks[i] = devm_clk_get(dev, clk_names[i]);
1942 if (IS_ERR(dsi->clks[i])) {
1943 if (strcmp(clk_names[i], "sclk_mipi") == 0) {
1944 dsi->clks[i] = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME);
1945 if (!IS_ERR(dsi->clks[i]))
1946 continue;
1947 }
1948
1949 dev_info(dev, "failed to get the clock: %s\n", clk_names[i]);
1950 return PTR_ERR(dsi->clks[i]);
1951 }
1952 }
1953
1954 dsi->reg_base = devm_platform_ioremap_resource(pdev, 0);
1955 if (IS_ERR(dsi->reg_base))
1956 return PTR_ERR(dsi->reg_base);
1957
1958 dsi->phy = devm_phy_optional_get(dev, "dsim");
1959 if (IS_ERR(dsi->phy)) {
1960 dev_info(dev, "failed to get dsim phy\n");
1961 return PTR_ERR(dsi->phy);
1962 }
1963
1964 dsi->irq = platform_get_irq(pdev, 0);
1965 if (dsi->irq < 0)
1966 return dsi->irq;
1967
1968 ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1969 samsung_dsim_irq,
1970 IRQF_ONESHOT | IRQF_NO_AUTOEN,
1971 dev_name(dev), dsi);
1972 if (ret) {
1973 dev_err(dev, "failed to request dsi irq\n");
1974 return ret;
1975 }
1976
1977 ret = samsung_dsim_parse_dt(dsi);
1978 if (ret)
1979 return ret;
1980
1981 platform_set_drvdata(pdev, dsi);
1982
1983 pm_runtime_enable(dev);
1984
1985 dsi->bridge.funcs = &samsung_dsim_bridge_funcs;
1986 dsi->bridge.of_node = dev->of_node;
1987 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1988
1989 /* DE_LOW: i.MX8M Mini/Nano LCDIF-DSIM glue logic inverts HS/VS/DE */
1990 if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM)
1991 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_low;
1992 else
1993 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_high;
1994
1995 if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->register_host)
1996 ret = dsi->plat_data->host_ops->register_host(dsi);
1997
1998 if (ret)
1999 goto err_disable_runtime;
2000
2001 return 0;
2002
2003err_disable_runtime:
2004 pm_runtime_disable(dev);
2005
2006 return ret;
2007}
2008EXPORT_SYMBOL_GPL(samsung_dsim_probe);
2009
2010void samsung_dsim_remove(struct platform_device *pdev)
2011{
2012 struct samsung_dsim *dsi = platform_get_drvdata(pdev);
2013
2014 pm_runtime_disable(&pdev->dev);
2015
2016 if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->unregister_host)
2017 dsi->plat_data->host_ops->unregister_host(dsi);
2018}
2019EXPORT_SYMBOL_GPL(samsung_dsim_remove);
2020
2021static int __maybe_unused samsung_dsim_suspend(struct device *dev)
2022{
2023 struct samsung_dsim *dsi = dev_get_drvdata(dev);
2024 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
2025 int ret, i;
2026
2027 usleep_range(10000, 20000);
2028
2029 if (dsi->state & DSIM_STATE_INITIALIZED) {
2030 dsi->state &= ~DSIM_STATE_INITIALIZED;
2031
2032 samsung_dsim_disable_clock(dsi);
2033
2034 samsung_dsim_disable_irq(dsi);
2035 }
2036
2037 dsi->state &= ~DSIM_STATE_CMD_LPM;
2038
2039 phy_power_off(dsi->phy);
2040
2041 for (i = driver_data->num_clks - 1; i > -1; i--)
2042 clk_disable_unprepare(dsi->clks[i]);
2043
2044 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
2045 if (ret < 0)
2046 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
2047
2048 return 0;
2049}
2050
2051static int __maybe_unused samsung_dsim_resume(struct device *dev)
2052{
2053 struct samsung_dsim *dsi = dev_get_drvdata(dev);
2054 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data;
2055 int ret, i;
2056
2057 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
2058 if (ret < 0) {
2059 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
2060 return ret;
2061 }
2062
2063 for (i = 0; i < driver_data->num_clks; i++) {
2064 ret = clk_prepare_enable(dsi->clks[i]);
2065 if (ret < 0)
2066 goto err_clk;
2067 }
2068
2069 ret = phy_power_on(dsi->phy);
2070 if (ret < 0) {
2071 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
2072 goto err_clk;
2073 }
2074
2075 return 0;
2076
2077err_clk:
2078 while (--i > -1)
2079 clk_disable_unprepare(dsi->clks[i]);
2080 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
2081
2082 return ret;
2083}
2084
2085const struct dev_pm_ops samsung_dsim_pm_ops = {
2086 SET_RUNTIME_PM_OPS(samsung_dsim_suspend, samsung_dsim_resume, NULL)
2087 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2088 pm_runtime_force_resume)
2089};
2090EXPORT_SYMBOL_GPL(samsung_dsim_pm_ops);
2091
2092static const struct samsung_dsim_plat_data samsung_dsim_imx8mm_pdata = {
2093 .hw_type = DSIM_TYPE_IMX8MM,
2094 .host_ops = &generic_dsim_host_ops,
2095};
2096
2097static const struct samsung_dsim_plat_data samsung_dsim_imx8mp_pdata = {
2098 .hw_type = DSIM_TYPE_IMX8MP,
2099 .host_ops = &generic_dsim_host_ops,
2100};
2101
2102static const struct of_device_id samsung_dsim_of_match[] = {
2103 {
2104 .compatible = "fsl,imx8mm-mipi-dsim",
2105 .data = &samsung_dsim_imx8mm_pdata,
2106 },
2107 {
2108 .compatible = "fsl,imx8mp-mipi-dsim",
2109 .data = &samsung_dsim_imx8mp_pdata,
2110 },
2111 { /* sentinel. */ }
2112};
2113MODULE_DEVICE_TABLE(of, samsung_dsim_of_match);
2114
2115static struct platform_driver samsung_dsim_driver = {
2116 .probe = samsung_dsim_probe,
2117 .remove_new = samsung_dsim_remove,
2118 .driver = {
2119 .name = "samsung-dsim",
2120 .pm = &samsung_dsim_pm_ops,
2121 .of_match_table = samsung_dsim_of_match,
2122 },
2123};
2124
2125module_platform_driver(samsung_dsim_driver);
2126
2127MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>");
2128MODULE_DESCRIPTION("Samsung MIPI DSIM controller bridge");
2129MODULE_LICENSE("GPL");